Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes: a metal layer on the via layer, the metal layer overlapping the emission region; a resonance auxiliary layer on the via layer and the metal layer, the resonance auxiliary layer exposing the metal layer; a positive electrode on the resonance auxiliary layer; and a contact layer connected to the metal layer and the positive electrode.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0181899, filed with the Korean Intellectual Property Office on December 14, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] Aspects of some embodiments of the present disclosure relate to a display device and a method of manufacturing a display device. Background art

[0004] With the development of information technology, the importance of display devices that provide a connection medium between users and information has been emphasized. Accordingly, display devices such as liquid crystal display devices and organic light - emitting display devices are increasingly used.

[0005] The above information disclosed in this background art section is only for enhancing the understanding of the background, and thus the information discussed in this background art section does not necessarily constitute prior art. Summary of the invention

[0006] Aspects of some embodiments of the present disclosure include a display device and a method of manufacturing a display device in which an anode electrode can be patterned without any etching process and electrical characteristics can be relatively improved.

[0007] According to some embodiments of the present disclosure, a display device having an emission region includes: a metal layer on a via - hole layer, the metal layer overlapping the emission region; a resonance - assisting layer on the via - hole layer and the metal layer, the resonance - assisting layer exposing the metal layer; an anode electrode on the resonance - assisting layer; and a contact layer connecting the metal layer and the anode electrode.

[0008] According to some embodiments, the metal layer may include a first metal layer connected to a via - hole of the via - hole layer, a second metal layer on the first metal layer, and a third metal layer on the second metal layer.

[0009] According to some embodiments, the conductivity of the second metal layer may be higher than the conductivity of the third metal layer.

[0010] According to some embodiments, the contact layer may connect to the second metal layer while penetrating the third metal layer.

[0011] According to some embodiments, the display device may further include a pixel - defining layer on the resonance - assisting layer, the anode electrode, and the contact layer, the pixel - defining layer exposing the anode electrode.

[0012] According to some embodiments, the display device may further include a protective layer on the anode electrode and the contact layer, and the protective layer exposes the anode electrode.

[0013] According to some embodiments, the display device may further include a pixel defining layer on the resonance assist layer, the anode electrode, and the protective layer, and the pixel defining layer has an undercut structure.

[0014] According to some embodiments, the resonance assist layer may include an inorganic material.

[0015] According to some embodiments, the contact layer may include a metal material.

[0016] According to some embodiments of the present disclosure, a method of manufacturing a display device includes: forming a metal layer on a via layer; forming a resonance assist layer on the via layer and the metal layer that exposes the metal layer; forming a first photosensitive pattern on the resonance assist layer and the exposed metal layer; forming an anode electrode on the resonance assist layer and the first photosensitive pattern; stripping the first photosensitive pattern; and forming a contact layer that penetrates the metal layer.

[0017] According to some embodiments, forming the metal layer may include: forming a first metal layer connected to the via of the via layer; forming a second metal layer on the first metal layer; and forming a third metal layer on the second metal layer.

[0018] According to some embodiments, the conductivity of the second metal layer may be higher than the conductivity of the third metal layer.

[0019] According to some embodiments, the first photosensitive pattern may be formed in an inverted conical shape.

[0020] According to some embodiments, forming the contact layer may include: forming a second photosensitive pattern on the resonance assist layer and the anode electrode; etching the third metal layer such that the second metal layer is exposed; stripping the second photosensitive pattern; and forming the contact layer on the exposed second metal layer to be connected to the anode electrode.

[0021] According to some embodiments, the method may further include: forming a pixel defining layer on the resonance assist layer, the anode electrode, and the contact layer that exposes the anode electrode.

[0022] According to some embodiments, the method may further include: forming a protective layer on the contact layer and the anode electrode.

[0023] According to some embodiments, the method may further include: forming a pixel defining layer on the resonance assist layer, the anode electrode, and the protective layer that exposes the protective layer.

[0024] According to some embodiments, the method may further include: etching the protective layer such that the pixel defining layer has an undercut structure.

[0025] According to some embodiments, the resonance assisting layer may include an inorganic material.

[0026] According to some embodiments, the contact layer may include a metal material. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Aspects in accordance with some embodiments of the present disclosure will become more apparent by referring to the accompanying drawings which are described in further detail below. Above and other aspects and features in accordance with embodiments of the present disclosure will become more obvious.

[0028] Figure 1 is a block diagram schematically illustrating a display device in accordance with some embodiments of the present disclosure.

[0029] Figure 2 is a block diagram schematically illustrating a sub-pixel in accordance with some embodiments of the present disclosure.

[0030] Figure 3 illustrates aspects of a display panel shown in accordance with some embodiments of the present disclosure Figure 1 in a plan view.

[0031] Figure 4 illustrates aspects of a display panel shown in accordance with some embodiments of the present disclosure Figure 3 in an exploded perspective view of a portion thereof.

[0032] Figure 5 is a cross-sectional view schematically illustrating a light-emitting structure in accordance with some embodiments of the present disclosure.

[0033] Figure 6 is a cross-sectional view schematically illustrating a light-emitting structure in accordance with some embodiments of the present disclosure.

[0034] Figure 7 illustrates aspects of a pixel shown in accordance with some embodiments of the present disclosure Figure 4 in a plan view.

[0035] Figure 8 illustrates aspects of a pixel shown in accordance with some embodiments of the present disclosure Figure 4 in a plan view.

[0036] Figure 9 illustrates aspects of a pixel shown in accordance with some embodiments of the present disclosure Figure 4 in a plan view.

[0037] Figure 10 is a cross-sectional view taken along line I-I' shown in accordance with some embodiments of the present disclosure Figure 7 in a cross-sectional view.

[0038] Figure 11 is a cross-sectional view taken alongFigure 7 A cross-sectional view taken along line I-I’ shown in

[0039] Figure 12 is a flowchart illustrating a method of manufacturing a display device according to some embodiments of the present disclosure.

[0040] Figures 13 to 20 is schematically illustrating aspects of the manufacturing method according to some embodiments of the present disclosure Figure 12 in a cross-sectional view shown in

[0041] Figure 21 is a flowchart illustrating a method of manufacturing a display device according to some embodiments of the present disclosure.

[0042] Figures 22 to 24 is schematically illustrating aspects of Figure 21 operations S800 to S1000 in the manufacturing method shown in according to some embodiments of the present disclosure in a cross-sectional view.

[0043] Figure 25 is a block diagram illustrating a display system according to some embodiments of the present disclosure.

[0044] Figure 26 is illustrating an application example of the display system according to some embodiments of the present disclosure Figure 25 in a perspective view shown in

[0045] Figure 27 is a view of a head-mounted display device worn by a user according to some embodiments of the present disclosure Figure 26 shown in DETAILED DESCRIPTION

[0046] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the following description, only parts necessary for understanding the operations according to the present disclosure are described, and descriptions of other parts are omitted so as not to unnecessarily obscure the subject matter of the present disclosure. In addition, the present disclosure is not limited to the disclosed embodiments herein, but may be embodied in various different forms. On the contrary, the disclosed embodiments herein are intended to more thoroughly and completely describe aspects of some embodiments of the present disclosure to more fully convey the idea of the present disclosure to those of ordinary skill in the art.

[0047] Throughout the specification, when an element is referred to as being "connected" or "coupled" to another element, the element can be directly connected or directly coupled to the other element, or indirectly connected or indirectly coupled to the other element through one or more intervening elements therebetween. Technical terms used herein are used only for the purpose of describing aspects of some embodiments and are not intended to limit the embodiments. It will be understood that when a component "comprises" an element, unless there is another description to the contrary, it should be understood that the component does not exclude another element, but may also include another element. It will be understood that for the purposes of the present disclosure, "at least one of X, Y, and Z" can be construed as only X, only Y, only Z, or any combination of two or more items of X, Y, and Z (e.g., XYZ, XY, YZ, XZ). Similarly, for the purposes of the present disclosure, "at least one selected from the group consisting of X, Y, and Z" can be construed as only X, only Y, only Z, or any combination of two or more items of X, Y, and Z (e.g., XYZ, XY, YZ, XZ).

[0048] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the "first" element discussed below may also be referred to as the "second" element without departing from the teachings of the present disclosure.

[0049] For ease of description, spatial relative terms such as "below", "above", etc. may be used herein to describe the relationship of one element to another as illustrated in the figures. It will be understood that the spatial relative terms and the illustrated configurations are intended to encompass different orientations of the device in use or operation in addition to the orientations described herein and depicted in the figures. For example, if the device in the figure is flipped, an element described as "below" or "beneath" other elements or features will then be oriented "above" the other elements or features. Thus, the term "above" can encompass both the above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are to be interpreted accordingly.

[0050] In addition, embodiments of the present disclosure are described herein with reference to schematic illustrations of ideal embodiments (and intermediate structures) thereof, so that variations in the shapes shown may be expected due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing techniques. The regions shown in the drawings are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.

[0051] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the drawings.

[0052] Figure 1 is a block diagram schematically illustrating a display device according to some embodiments of the present disclosure.

[0053] Referring to Figure 1 , the display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0054] The display panel 110 may include sub-pixels SP. The sub-pixels SP may be connected to the gate driver 120 through first gate lines GL1 to m-th gate lines GLm. The sub-pixels SP may be connected to the data driver 130 through first data lines DL1 to n-th data lines DLn. The number of rows and columns of the sub-pixels SP and thus the number of gate lines and data lines may vary according to the design and size of the display device 100.

[0055] Each of the plurality of sub-pixels SP may include at least one light-emitting element configured to generate light. Accordingly, each of the plurality of sub-pixels SP may generate light of a specific color such as red, green, blue, cyan, magenta, and / or yellow. Two or more of the plurality of sub-pixels SP may constitute a pixel PXL. For example, as Figure 1 shown, three sub-pixels SP may constitute a pixel PXL, but is not limited thereto according to embodiments of the present disclosure, and according to some embodiments, the display device 100 may be designed such that four or more sub-pixels SP may constitute a pixel PXL.

[0056] The gate driver 120 may be connected to the sub-pixels SP arranged in the row direction through first gate lines GL1 to m-th gate lines GLm. The gate driver 120 may output a gate signal to the first gate lines GL1 to m-th gate lines GLm in response to a gate control signal GCS. According to some embodiments, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting the gate signal in synchronization with the timing at which a data signal is applied, and the like.

[0057] According to some embodiments, first emission control lines EL1 to m-th emission control lines ELm connected to the sub-pixels SP in the row direction may also be provided. The gate driver 120 may include an emission control driver configured to control the first emission control lines EL1 to m-th emission control lines ELm, and the emission control driver may operate under the control of the controller 150.

[0058] The gate driver 120 may be positioned at one side of the display panel 110. However, embodiments according to the present disclosure are not limited thereto. For example, the gate driver 120 may be divided into two or more drivers that are physically and / or logically divided, and these drivers may be positioned at a first side of the display panel 110 and a second side of the display panel 110 opposite the first side. Additionally, according to some embodiments, the gate driver 120 may be divided into two or more drivers positioned on adjacent sides or more than two sides of the display panel 110. Thus, in some embodiments, the gate driver 120 may be positioned at the periphery of the display panel 110 in various forms.

[0059] The data driver 130 may be connected to sub-pixels SP arranged in a column direction through first data lines DL1 to nth data lines DLn. The data driver 130 may receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. According to some embodiments, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, and the like.

[0060] The data driver 130 may apply data signals having gray-scale voltages corresponding to the image data DATA to the first data lines DL1 to nth data lines DLn by using voltages from the voltage generator 140. When a gate signal is applied to each of the first gate lines GL1 to mth gate lines GLm, data signals corresponding to the image data DATA may be applied to the first data lines DL1 to nth data lines DLn. Thus, the corresponding sub-pixels SP may generate light corresponding to the data signals. Thus, an image may be displayed on the display panel 110.

[0061] According to some embodiments, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0062] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 may be configured to generate a plurality of voltages and supply the generated voltages to components of the display device 100. For example, the voltage generator 140 may be configured to generate a plurality of voltages by receiving an input voltage from outside the display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0063] The voltage generator 140 may generate a first power voltage VDD and a second power voltage VSS, and the generated first power voltage VDD and second power voltage VSS may be provided to the sub-pixel SP. The first power voltage VDD may have a relatively high voltage level, and the second power voltage VSS may have a voltage level lower than that of the first power voltage VDD. According to some embodiments, the first power voltage VDD or the second power voltage VSS may be provided by an external device of the display device 100.

[0064] In addition, the voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage applied to the sub-pixel SP. For example, in a sensing operation for sensing the electrical characteristics of the transistors and / or light-emitting elements of the sub-pixel SP, a reference voltage (e.g., a set or predetermined reference voltage) may be applied to the first data line DL1 to the nth data line DLn, and the voltage generator 140 may generate the reference voltage.

[0065] The controller 150 may control the overall operation of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL for controlling its display from the outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0066] The controller 150 may convert the input image data IMG to be suitable for the display device 100 or the display panel 110, and thus output image data DATA. According to some embodiments, the controller 150 may align the input image data IMG in units of rows to be suitable for the sub-pixel SP, and thus output image data DATA.

[0067] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be mounted on one integrated circuit. As Figure 1 shown, the data driver 130, the voltage generator 140, and the controller 150 may be included in the driver integrated circuit DIC. The data driver 130, the voltage generator 140, and the controller 150 may be components functionally divided in one driver integrated circuit DIC. According to some embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a component separate from the driver integrated circuit DIC.

[0068] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 may be configured to sense the temperature at its periphery and generate temperature data TEP indicating the sensed temperature. According to some embodiments, the temperature sensor 160 may be adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0069] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. According to some embodiments, the controller 150 may adjust the brightness of an image output from the display device 100 in response to the temperature data TEP. For example, the controller 150 may control components such as the data driver 130 and / or the voltage generator 140 to adjust the data signal and the first power voltage VDD and the second power voltage VSS.

[0070] Figure 2 is a block diagram schematically illustrating sub-pixels according to some embodiments of the present disclosure. In Figure 2 among them, among the multiple sub-pixels SP shown in Figure 1 the sub-pixel SPij arranged in the i-th row (where i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (where j is an integer greater than or equal to 1 and less than or equal to n) is illustrated as an example.

[0071] Referring to Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD.

[0072] The light-emitting element LD may be connected between the first power voltage node VDDN and the second power voltage node VSSN. The first power voltage node VDDN may be the node for transmitting Figure 1 the first power voltage VDD shown in, and the second power voltage node VSSN may be the node for transmitting Figure 1 the second power voltage VSS shown in.

[0073] The anode electrode AE of the light-emitting element LD may be connected to the first power voltage node VDDN through the sub-pixel circuit SPC, and the cathode electrode CE of the light-emitting element LD may be connected to the second power voltage node VSSN. For example, the anode electrode AE of the light-emitting element LD may be connected to the first power voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0074] The sub-pixel circuit SPC may be connected to Figure 1 the i-th gate line GLi among the first gate lines GL1 to the m-th gate line GLm shown in, Figure 1 the i-th emission control line ELi among the first emission control lines EL1 to the m-th emission control lines ELm shown in and Figure 1 the j-th data line DLj among the first data lines DL1 to the n-th data lines DLn shown in. The sub-pixel circuit SPC may be configured to control the light-emitting element LD according to the signals received through these signal lines.

[0075] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. According to some embodiments, as Figure 2 shown, the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC may operate in response to gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. Therefore, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC may operate in response to the gate signals received through the corresponding sub-gate lines.

[0076] The sub-pixel circuit SPC may operate in response to an emission control signal received through the i-th emission control line ELi. According to some embodiments, the i-th emission control line ELi may include one or more sub-emission control lines. When the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC may operate in response to the emission control signals received through the corresponding emission control lines.

[0077] The sub-pixel circuit SPC may receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC may store a voltage corresponding to the data signal in response to at least one of a plurality of gate signals received through the first sub-gate line SGL1 or the second sub-gate line SGL2. The sub-pixel circuit SPC may control a current flowing from the first power voltage node VDDN through the light-emitting element LD to the second power voltage node VSSN according to the stored voltage in response to the emission control signal received through the i-th emission control line ELi. Therefore, the light-emitting element LD may generate light having a brightness corresponding to the data signal.

[0078] Figure 3 is a plan view illustrating an aspect of a display panel according to some embodiments of the present disclosure Figure 1 shown therein.

[0079] Referring to Figure 3 , the display panel DP (i.e., Figure 1 the display panel 110 shown therein) may include a display area DA and a non-display area NDA. The display panel DP may display an image at or through the display area DA. The non-display area NDA may be located at the periphery of the display area DA (or outside the cover area).

[0080] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0081] When the display panel DP is used as a display screen of a head-mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, etc., the display panel DP can be positioned very close to the user's eyes. Sub-pixels SP with relatively high integration may be required. To increase the integration of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP and / or the display panel DP may be formed on the substrate SUB which is a silicon substrate. A display device 100 (see Figure 1 ) including the display panel DP formed on the substrate SUB which is a silicon substrate may be referred to as a silicon-based organic light-emitting diode (OLED) display device (OLEDoS).

[0082] The sub-pixels SP may be positioned in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiments according to the present disclosure are not limited thereto. For example, the sub-pixels SP may be arranged in a zigzag along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged in a form or layout. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0083] Two or more of the plurality of sub-pixels SP may constitute one pixel PXL.

[0084] Components for controlling the sub-pixels SP may be positioned in the non-display area NDA on the substrate SUB. For example, lines connected to the sub-pixels SP (such as Figure 1 the first gate line GL1 to the m-th gate line GLm and the first data line DL1 to the n-th data line DLn shown in

[0085] Figure 1 ) may be positioned in the non-display area NDA. At least one of the gate driver 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 shown in Figure 1 may be integrated in the non-display area NDA of the display panel DP. According to some embodiments,

[0086] the gate driver 120 shown in Figure 1 is mounted on the display panel DP and may be positioned in the non-display area NDA. According to some embodiments, the gate driver 120 may be implemented as an integrated circuit separate from the display panel DP. According to some embodiments, the temperature sensor 160 may be positioned in the non-display area NDA to sense the temperature of the display panel DP.

[0086] The pads PD may be positioned in the non-display area NDA on the substrate SUB. The pads PD may be electrically connected to the sub-pixels SP through lines. For example, the pads PD may be connected to the sub-pixels SP through the first data line DL1 to the n-th data line DLn.

[0087] The pad PD can connect the display panel DP to the display device 100 (see Figure 1 ) is connected to other components. According to some embodiments, Figure 1 The driver integrated circuit DIC shown in FIG. 1 provides voltages and signals that can be used for the operation of components included in the display panel DP through the pads PD. For example, the first data line DL1 to the nth data line DLn can be connected to the driver integrated circuit DIC through the pads PD. For example, the first power voltage VDD and the second power voltage VSS can be received from the driver integrated circuit DIC through the pads PD. When the gate driver 120 is installed in the display panel DP, the gate control signal GCS can be sent from the driver integrated circuit DIC to the gate driver 120 through the pads PD.

[0088] According to some embodiments, the circuit board may be electrically connected to the pad PD using a conductive adhesive member such as an anisotropic conductive film. The circuit board may be a flexible printed circuit board (FPCB) or a flexible film having a flexible material. The driver integrated circuit DIC may be mounted on the circuit board to be electrically connected to the pad PD.

[0089] According to some embodiments, the display area DA may have various shapes. The display area DA may have a closed loop shape including straight lines and / or curved lines. For example, the display area DA may have shapes such as polygons, circles, semicircles, and ellipses.

[0090] According to some embodiments, the display panel DP may have a flat display surface. According to some embodiments, the display panel DP may have a rounded display surface at least in part. According to some embodiments, the display panel DP may be bendable, foldable, or rollable without damaging the display device 100. The display panel DP and / or the substrate SUB may include a material having flexibility.

[0091] Figure 4 It is a diagram illustrating some embodiments of the present disclosure. Figure 3 An exploded perspective view of a portion of a display panel is shown in FIG. Figure 4 In the embodiment, for the sake of clarity and brief description, the display panel DP is schematically illustrated. Figure 3 1 and 2. Portions corresponding to the first pixel PXL1 and the second pixel PXL2 among the pixels PXL shown in FIG. Portions corresponding to other pixels of the display panel DP may also be uniformly configured.

[0092] Reference Figure 3 and Figure 4, each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, embodiments according to the present disclosure are not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels or two sub-pixels.

[0093] In Figure 4 , it can be illustrated that when observed in a third direction DR3 intersecting the first direction DR1 and the second direction DR2 (e.g., in a plan view), the first sub-pixel SP1 to the third sub-pixel SP3 may have a quadrilateral shape and have the same size. However, embodiments according to the present disclosure are not limited thereto. The first sub-pixel SP1 to the third sub-pixel SP3 may be modified to have various shapes.

[0094] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light-emitting element layer LDL, a packaging layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0095] According to some embodiments, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may be provided from a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc. According to some embodiments, the substrate SUB may include a glass substrate. According to some embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0096] The pixel circuit layer PCL may be positioned on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and conductive patterns positioned between the insulating layers. The conductive patterns of the pixel circuit layer PCL may be used as at least some of circuit elements, lines, etc. The conductive patterns may include copper, but embodiments according to the present disclosure are not limited thereto.

[0097] The circuit elements may include sub-pixel circuits SPC for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (see Figure 2)。The sub-pixel circuit SPC may include transistors and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. According to some embodiments, when the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. According to some embodiments, when the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane defined by a first direction DR1 and a second direction DR2. For example, the capacitor may include electrodes spaced apart from each other in a third direction DR3 with an insulating layer therebetween.

[0098] The lines of the pixel circuit layer PCL may include signal lines connected to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, such as gate lines, emission control lines, data lines, etc. The lines may also include lines connected to Figure 2 the first power voltage node VDDN shown in Figure 2 The lines may also include lines connected to

[0099] The light-emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, a light-emitting structure EMS, and a cathode electrode CE.

[0100] The anode electrode AE may be positioned on the pixel circuit layer PCL. The anode electrode AE may be electrically connected to the circuit elements of the pixel circuit layer PCL. The anode electrode AE may include an opaque conductive material capable of reflecting light, but the embodiments are not limited thereto.

[0101] The pixel defining layer PDL may be disposed over the anode electrode AE. The pixel defining layer PDL may include openings OP exposing a part of each of the plurality of anode electrodes AE. The openings OP of the pixel defining layer PDL may be understood as emission regions corresponding to each of the first sub-pixel SP1 to the third sub-pixel SP3.

[0102] According to some embodiments, the pixel defining layer PDL may include an inorganic material. The pixel defining layer PDL may include a plurality of stacked inorganic layers. For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x ). According to some embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited thereto.

[0103] The light-emitting structure EMS can be positioned on the anode AE exposed by the opening OP of the pixel-defining layer PDL. The light-emitting structure EMS can include a light-generating layer configured to generate light, an electron-transporting layer configured to transport electrons, a hole-transporting layer configured to transport holes, and the like.

[0104] According to some embodiments, the light-emitting structure EMS fills the opening OP of the pixel-defining layer PDL and can be entirely positioned on top of the pixel-defining layer PDL. The light-emitting structure EMS can extend across the first sub-pixel SP1 to the third sub-pixel SP3. At least some of the layers in the light-emitting structure EMS can be separated (cut) or bent at the boundaries between the first sub-pixel SP1 to the third sub-pixel SP3. However, the embodiments according to the present disclosure are not limited thereto. For example, the portions of the light-emitting structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 can be separated from each other, and each of the multiple separated portions of the light-emitting structure EMS can be positioned in the opening OP of the pixel-defining layer PDL.

[0105] The cathode CE can be positioned on the light-emitting structure EMS. The cathode CE can extend across the first sub-pixel SP1 to the third sub-pixel SP3. Thus, the cathode CE can be provided as a common electrode for the first sub-pixel SP1 to the third sub-pixel SP3.

[0106] The cathode CE can be a thin metal layer having a thickness such that light emitted from the light-emitting structure EMS can transmit therethrough. The cathode CE can be formed of a metal material to have a relatively thin thickness, or formed of a transparent conductive material. According to some embodiments, the cathode CE can include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc oxide tin, and gallium tin oxide. According to some embodiments, the cathode CE can include at least one of silver (Ag), magnesium (Mg), and mixtures thereof. However, the material of the cathode CE is not limited thereto.

[0107] It can be understood that any one of the multiple anodes AE, the overlapping portion of the light-emitting structure EMS therewith, and the overlapping portion of the cathode CE therewith constitute a light-emitting element LD (see Figure 2 ). Each of the multiple light-emitting elements LD of the first sub-pixel SP1 to the third sub-pixel SP3 can include an anode AE, the overlapping portion of the light-emitting structure EMS therewith, and the overlapping portion of the cathode CE therewith. In each of the first sub-pixel SP1 to the third sub-pixel SP3, holes injected from the anode AE and electrons injected from the cathode CE can be transported into the light-emitting layer of the light-emitting structure EMS to form excitons, and light can be generated when the excitons change from the excited state to the ground state. The brightness of the light can be determined according to the amount of current flowing through the light-emitting layer. The wavelength band of the generated light can be determined according to the configuration of the light-emitting layer.

[0108] The encapsulation layer TFE can be disposed throughout the cathode electrode CE. The encapsulation layer TFE can cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE can be configured to prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL. According to some embodiments, the encapsulation layer TFE can include a structure in which at least one inorganic layer and at least one organic layer are alternately stacked. For example, the inorganic layer can include silicon nitride, silicon oxide, silicon oxynitride (SiO x N y ), etc. For example, the organic layer can include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the encapsulation layer TFE are not limited thereto.

[0109] In order to relatively improve the encapsulation efficiency of the encapsulation layer TFE, the encapsulation layer TFE can further include a thin film containing aluminum oxide (AlO x ). The thin film containing aluminum oxide can be positioned on the top surface of the encapsulation layer TFE facing the optical function layer OFL and / or on the bottom surface of the encapsulation layer TFE facing the light-emitting element layer LDL.

[0110] The thin film containing aluminum oxide can be formed by an atomic layer deposition (ALD) process. However, the embodiments according to the present disclosure are not limited thereto. The encapsulation layer TFE can further include a thin film formed of at least one of various materials suitable for improving the encapsulation efficiency.

[0111] The optical function layer OFL can be positioned on the encapsulation layer TFE. The optical function layer OFL can include a color filter layer CFL and a lens array LA.

[0112] The color filter layer CFL can be positioned between the encapsulation layer TFE and the lens array LA. The color filter layer CFL can be configured to filter the light emitted from the light-emitting structure EMS, thereby selectively outputting light of a wavelength band or color corresponding to each sub-pixel. The color filter layer CFL can include color filters CF corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. Each of the plurality of color filters CF can allow light having a wavelength band corresponding to the corresponding sub-pixel to pass through. For example, the color filter CF corresponding to the first sub-pixel SP1 can allow red light to pass through, the color filter CF corresponding to the second sub-pixel SP2 can allow green light to pass through, and the color filter CF corresponding to the third sub-pixel SP3 can allow blue light to pass through. At least some of the color filters CF can be omitted according to the light emitted from the light-emitting structure EMS in each sub-pixel.

[0113] The lens array LA may be positioned on the color filter layer CFL. The lens array LA may include lenses LS respectively corresponding to the first sub-pixel SP1 to the third sub-pixel SP3. Each of the plurality of lenses LS may output the light emitted from the light-emitting structure EMS along an expected path, thereby improving the light-emitting efficiency. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index higher than that of the overcoat layer OC. According to some embodiments, the lens LS may include an organic material. According to some embodiments, the lens LS may include an acrylic-based material. However, the material of the lens LS is not limited thereto.

[0114] According to some embodiments, compared with the opening OP of the pixel defining layer PDL, at least some of the color filters CF in the color filter layer CFL and at least some of the lenses LS in the lens array LA may be offset in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2. For example, in the central region of the display area DA, when observed in the third direction DR3 (e.g., in a plan view), the center of the color filter CF and the center of the lens LS may be aligned or overlapped with the center of the corresponding opening OP of the pixel defining layer PDL. For example, in the central region of the display area DA, the opening OP of the pixel defining layer PDL may completely overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA.

[0115] In the region of the display area DA adjacent to the non-display area NDA, when observed in the third direction DR3 (e.g., in a plan view), the center of the color filter CF and the center of the lens LS may be offset in the planar direction from the center of the opening OP of the pixel defining layer PDL. For example, in the region of the display area DA adjacent to the non-display area NDA, the opening OP of the pixel defining layer PDL may partially overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Therefore, at the center of the display area DA, the light emitted from the light-emitting structure EMS can be effectively output in the normal direction of the display surface. At the outer part of the display area DA, the light emitted from the light-emitting structure EMS can be effectively output in a direction inclined at a certain angle (e.g., a set or predetermined angle) with respect to the normal direction.

[0116] The overcoat layer OC may be arranged throughout the lens array LA. The overcoat layer OC may cover the optical functional layer OFL, the encapsulation layer TFE, the light-emitting structure EMS, and / or the pixel circuit layer PCL. The overcoat layer OC may include various materials suitable for protecting its underlying layer from foreign substances such as dust and moisture. For example, the overcoat layer OC may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer OC may include an epoxy resin, but is not limited thereto according to the embodiments of the present disclosure. The overcoat layer OC may have a refractive index lower than that of the lens array LA.

[0117] The cover window CW can be positioned on the outer cladding OC. The cover window CW can be configured to protect its underlying layer. The cover window CW can have a refractive index higher than that of the outer cladding OC. The cover window CW can include glass, but is not limited thereto according to embodiments of the present disclosure. For example, the cover window CW can be encapsulation glass configured to protect components positioned on its bottom. According to some embodiments, the cover window CW can be omitted.

[0118] Figure 5 is a schematic cross-sectional view illustrating a light-emitting structure according to some embodiments of the present disclosure.

[0119] Referring to Figure 5 , the light-emitting structure EMS can have a series structure in which a first light-emitting unit EU1 and a second light-emitting unit EU2 are stacked.

[0120] Each of the first light-emitting unit EU1 and the second light-emitting unit EU2 can include at least one light-emitting layer that generates light according to an applied current. The first light-emitting unit EU1 can include a first light-emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light-emitting layer EML1 can be positioned between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting unit EU2 can include a second light-emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light-emitting layer EML2 can be positioned between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0121] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 can include at least one of a hole injection layer and a hole transport layer. Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 can further include a hole buffer layer, an electron blocking layer, etc. as needed. The first hole transport unit HTU1 and the second hole transport unit HTU2 can have the same configuration or different configurations.

[0122] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 can include at least one of an electron injection layer and an electron transport layer. Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 can further include an electron buffer layer, a hole blocking layer, etc. as needed. The first electron transport unit ETU1 and the second electron transport unit ETU2 can have the same configuration or different configurations.

[0123] The connection layer, which may be provided in the form of a charge generation layer CGL, may be positioned between the first light-emitting unit EU1 and the second light-emitting unit EU2 to connect the first light-emitting unit EU1 and the second light-emitting unit EU2 to each other. According to some embodiments, the charge generation layer CGL may have a stacked structure of a p-dopant layer and an n-dopant layer. For example, the p-dopant layer may include a p-type dopant such as HAT-CN, TCNQ, or NDP-9, and the n-dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or any combination thereof. However, the embodiments according to the present disclosure are not limited thereto.

[0124] According to some embodiments, the first light-emitting layer EML1 and the second light-emitting layer EML2 may generate light of different colors. The light emitted from the first light-emitting layer EML1 and the second light-emitting layer EML2, respectively, may be mixed together to be regarded as white light. For example, the first light-emitting layer EML1 may generate blue light, and the second light-emitting layer EML2 may generate yellow light. According to some embodiments, the second light-emitting layer EML2 may include a structure in which a first sub-light-emitting layer configured to generate red light and a second sub-light-emitting layer configured to generate green light are stacked. The red light and the green light may be mixed together to provide yellow light. An intermediate layer configured to perform the function of transporting holes and / or the function of blocking the transport of electrons may also be positioned between the first sub-light-emitting layer and the second sub-light-emitting layer.

[0125] According to some embodiments, the first light-emitting layer EML1 and the second light-emitting layer EML2 may generate light of the same color.

[0126] The light-emitting structure EMS may be formed by a process such as vacuum deposition or inkjet printing, but the embodiments according to the present disclosure are not limited thereto.

[0127] Unlike Figure 5 shown in Figure 4 , the light-emitting structure EMS may include one light-emitting unit. The light-emitting units included in the corresponding first sub-pixel SP1 to third sub-pixel SP3 (see Figure 4 ) may be configured to emit light of different colors. For example, the light-emitting unit of the first sub-pixel SP1 may emit red light, the light-emitting unit of the second sub-pixel SP2 may emit green light, and the light-emitting unit of the third sub-pixel SP3 may emit blue light. The light-emitting units of the first sub-pixel SP1 to the third sub-pixel SP3 may be separated from each other, and each of the separated plurality of light-emitting units may be positioned in the opening OP of the pixel defining layer PDL. Figure 4 At least some of the plurality of color filters shown in

[0128] Figure 6 may be omitted.

[0129] Referring to Figure 6, the light-emitting structure EMS’ can be a series structure in which the first light-emitting unit EU1’ to the third light-emitting unit EU3’ are stacked.

[0130] Each of the first light-emitting unit EU1’ to the third light-emitting unit EU3’ may include a light-emitting layer that generates light according to the applied current. The first light-emitting unit EU1’ may include a first light-emitting layer EML1’, a first electron transport unit ETU1’, and a first hole transport unit HTU1’. The first light-emitting layer EML1’ may be positioned between the first electron transport unit ETU1’ and the first hole transport unit HTU1’. The second light-emitting unit EU2’ may include a second light-emitting layer EML2’, a second electron transport unit ETU2’, and a second hole transport unit HTU2’. The second light-emitting layer EML2’ may be positioned between the second electron transport unit ETU2’ and the second hole transport unit HTU2’. The third light-emitting unit EU3’ may include a third light-emitting layer EML3’, a third electron transport unit ETU3’, and a third hole transport unit HTU3’. The third light-emitting layer EML3’ may be positioned between the third electron transport unit ETU3’ and the third hole transport unit HTU3’.

[0131] According to some embodiments, each of the first hole transport unit HTU1’ to the third hole transport unit HTU3’ may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer and / or an electron blocking layer, etc. The first hole transport unit HTU1’ to the third hole transport unit HTU3’ may have the same configuration or different configurations.

[0132] According to some embodiments, each of the first electron transport unit ETU1’ to the third electron transport unit ETU3’ may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. The first electron transport unit ETU1’ to the third electron transport unit ETU3’ may have the same configuration or different configurations.

[0133] The first charge generation layer CGL1’ may be positioned between the first light-emitting unit EU1’ and the second light-emitting unit EU2’. The second charge generation layer CGL2’ may be positioned between the second light-emitting unit EU2’ and the third light-emitting unit EU3’.

[0134] According to some embodiments, the first light-emitting layer EML1’ to the third light-emitting layer EML3’ may generate lights of different colors. The lights respectively emitted from the first light-emitting layer EML1’ to the third light-emitting layer EML3’ may be mixed together to be regarded as white light. For example, the first light-emitting layer EML1’ may generate blue light,

[0135] the second light-emitting layer EML2’ may generate green light, and the third light-emitting layer EML3’ may generate red light.

[0136] According to some embodiments, at least two of the first light-emitting layer EML1' to the third light-emitting layer EML3' may generate light of the same color.

[0137] Figure 7 is a plan view showing aspects of the pixels shown in accordance with some embodiments of the present disclosure Figure 4 In Figure 7 for clarity and brief description, the first pixel PXL1 among the first pixel PXL1 and the second pixel PXL2 shown in Figure 4 is schematically illustrated. Other pixels may be configured in accordance with the first pixel PXL1.

[0138] Referring to Figure 4 and Figure 7 , the first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged in a first direction DR1.

[0139] The first sub-pixel SP1 may include a first emission region EMA1 and a non-emission region NEA at the periphery of the first emission region EMA1. The second sub-pixel SP2 may include a second emission region EMA2 and a non-emission region NEA at the periphery of the second emission region EMA2. The third sub-pixel SP3 may include a third emission region EMA3 and a non-emission region NEA at the periphery of the third emission region EMA3.

[0140] The first emission region EMA1 may be a region where light is emitted from a portion of the light-emitting structure EMS corresponding to the first sub-pixel SP1 (see Figure 4 ). The second emission region EMA2 may be a region where light is emitted from a portion of the light-emitting structure EMS corresponding to the second sub-pixel SP2. The third emission region EMA3 may be a region where light is emitted from a portion of the light-emitting structure EMS corresponding to the third sub-pixel SP3. As described with reference to Figure 4 , each emission region may be understood as an opening OP of the pixel defining layer PDL corresponding to each of the first to third sub-pixels SP1 to SP3.

[0141] Figure 8 is a plan view showing aspects of the pixels shown in accordance with some embodiments of the present disclosure Figure 4 In

[0142] Referring to Figure 8 , the first pixel PXL1' may include first to third sub-pixels SP1' to SP3'.

[0143] The first sub-pixel SP1’ may include a first emission area EMA1’ and a non-emission area NEA’ at the periphery of the first emission area EMA1’. The second sub-pixel SP2’ may include a second emission area EMA2’ and a non-emission area NEA’ at the periphery of the second emission area EMA2’. The third sub-pixel SP3’ may include a third emission area EMA3’ and a non-emission area NEA’ at the periphery of the third emission area EMA3’.

[0144] The first sub-pixel SP1’ and the second sub-pixel SP2’ may be arranged in a second direction DR2. The third sub-pixel SP3’ may be positioned in a first direction DR1 with respect to each of the first sub-pixel SP1’ and the second sub-pixel SP2’.

[0145] The second sub-pixel SP2’ may have an area larger than that of the first sub-pixel SP1’, and the third sub-pixel SP3’ may have an area larger than that of the second sub-pixel SP2’. Accordingly, the second emission area EMA2’ may have an area larger than that of the first emission area EMA1’, and the third emission area EMA3’ may have an area larger than that of the second emission area EMA2’. However, the embodiments according to the present disclosure are not limited thereto. For example, the first sub-pixel SP1’ and the second sub-pixel SP2’ may have substantially the same area, and the third sub-pixel SP3’ may have an area larger than that of each of the first sub-pixel SP1’ and the second sub-pixel SP2’. Accordingly, in some embodiments, the areas of the first sub-pixel SP1’ to the third sub-pixel SP3’ may be variously modified.

[0146] Figure 9 is a plan view illustrating aspects of a pixel shown in Figure 4 some embodiments according to the present disclosure.

[0147] Referring to Figure 9 , the first pixel PXL1” may include a first sub-pixel SP1” to a third sub-pixel SP3”.

[0148] The first sub-pixel SP1” may include a first emission area EMA1” and a non-emission area NEA” at the periphery of the first emission area EMA1”. The second sub-pixel SP2” may include a second emission area EMA2” and a non-emission area NEA” at the periphery of the second emission area EMA2”. The third sub-pixel SP3” may include a third emission area EMA3” and a non-emission area NEA” at the periphery of the third emission area EMA3”.

[0149] When viewed in a third direction DR3 (e.g., in a plan view), the first sub-pixel SP1” to the third sub-pixel SP3” may have a polygonal shape. For example, the shapes of the first sub-pixel SP1” to the third sub-pixel SP3” may be asFigure 9 The hexagonal shape shown in

[0150] When viewed in a third direction DR3 (e.g., in a plan view), the first emission region EMA1” to the third emission region EMA3” may have a circular shape. However, embodiments according to the present disclosure are not limited thereto. For example, each of the first emission region EMA1” to the third emission region EMA3” may have a polygonal shape.

[0151] The first sub-pixel SP1” and the third sub-pixel SP3” may be arranged in a first direction DR1. The second sub-pixel SP2” may be arranged in a direction (or diagonal direction) that is acutely inclined based on a second direction DR2 with respect to the first sub-pixel SP1”.

[0152] Figure 7 , Figure 8 and Figure 9 The arrangement of the sub-pixels shown in

[0153] Figure 10 is a cross-sectional view taken along the line I-I’ shown in Figure 7 according to some embodiments of the present disclosure. In Figure 10 , for clarity and brevity of description, a cross-sectional view of the first sub-pixel SP1 among the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 shown in Figure 7 is schematically illustrated. The other sub-pixels may be configured in accordance with the cross-section of the first sub-pixel SP1. Figure 1 consistently.

[0154] Referring to Figure 10 , a substrate SUB and a pixel circuit layer PCL positioned on the substrate SUB are provided.

[0155] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0156] The pixel circuit layer PCL is positioned on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements of the first sub-pixel SP1. For example, the substrate SUB and the pixel circuit layer PCL may include transistors and at least one capacitor of the first sub-pixel SP1. The substrate SUB and the pixel circuit layer PCL may include Figure 7 circuit elements of the second sub-pixel SP2 and circuit elements of the third sub-pixel SP3 shown in

[0157] The via layer VIAL is positioned on the pixel circuit layer PCL. The via layer VIAL covers the pixel circuit layer PCL and may have a completely flat surface. The via layer VIAL is configured to planarize the step difference on the pixel circuit layer PCL. The via layer VIAL may include at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon carbonitride (SiCN), but is not limited thereto according to embodiments of the present disclosure. The via layer VIAL may include at least one via VIA.

[0158] On the via layer VIAL, the metal layer ML is positioned in the first sub-pixel SP1. On the via layer VIAL, the metal layer ML may be positioned in each of the second sub-pixel SP2 and the third sub-pixel SP3 shown in Figure 7 . The metal layer ML may be in contact with circuit elements positioned in the pixel circuit layer PCL through vias VIA that penetrate the via layer VIAL.

[0159] The metal layer ML can be used as a total reflection mirror that reflects light emitted from the light-emitting structure EMS toward the display surface. For example, the metal layer ML can reflect light emitted from the back surface to the front surface in the light-emitting structure EMS that overlaps with the first emission region EMA. The metal layer ML can reflect light emitted from the back surface to the front surface in the light-emitting structure EMS that overlaps with the Figure 7 second emission region EMA2 shown in. The metal layer ML can reflect light emitted from the back surface to the front surface in the light-emitting structure EMS that overlaps with the Figure 7 third emission region EMA3 shown in.

[0160] The metal layer ML may include a metal material suitable for reflecting light. The metal layer ML may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys of two or more materials selected from them, but the embodiments are not limited thereto.

[0161] According to some embodiments, the metal layer ML may have a multi-layer structure. For example, the metal layer ML may include a first metal layer ML1, a second metal layer ML2, and a third metal layer ML3.

[0162] The first metal layer ML1 is positioned on the via layer VIAL. The first metal layer ML1 may be electrically connected to the circuit elements of the pixel circuit layer PCL through the via VIA. The first metal layer ML1 can improve the electrical connection characteristics between the second metal layer ML2 and the circuit elements of the pixel circuit layer PCL. The first metal layer ML1 may include a metal material such as titanium (Ti), but is not limited thereto according to embodiments of the present disclosure.

[0163] The second metal layer ML2 is positioned on the first metal layer ML1. The second metal layer ML2 may include a metal material suitable for reflecting light and having a high electrical conductivity. For example, the electrical conductivity of the second metal layer ML2 may be higher than that of the third metal layer ML3. The second metal layer ML2 may include a metal material such as aluminum (Al), but is not limited thereto according to embodiments of the present disclosure.

[0164] The third metal layer ML3 is positioned on the second metal layer ML2. The third metal layer ML3 is configured to planarize the step difference caused by the mounds of the second metal layer ML2. The electrical conductivity of the third metal layer ML3 may be lower than that of the second metal layer ML2. The third metal layer ML3 may include a metal material such as titanium nitride (TiN), but embodiments are not limited thereto.

[0165] The resonance assist layer RAL is positioned on the via layer VIAL and the metal layer ML. The resonance assist layer RAL may completely cover the via layer VIAL and partially cover the metal layer ML. That is, the resonance assist layer RAL may expose a part of the metal layer ML. For example, the resonance assist layer RAL may expose a part of the top surface of the third metal layer ML3. The resonance assist layer RAL may include an inorganic material, but is not limited thereto according to embodiments of the present disclosure.

[0166] The metal layer ML may be used as a total mirror, and the cathode electrode CE may be used as a semi - mirror. Light emitted from the light - emitting structure EMS may be amplified by at least partially reciprocating between the metal layer ML and the cathode electrode CE, and the amplified light may be output through the cathode electrode CE. Therefore, the thickness between the metal layer ML and the cathode electrode CE may be understood as the resonance thickness of the light emitted from the light - emitting structure EMS. The resonance assist layer RAL may serve to form an optimal resonance thickness for amplifying the light emitted from the light - emitting structure EMS. That is, the thickness of the resonance assist layer RAL may be adjusted to effectively and efficiently amplify light within a specific wavelength range.

[0167] According to some embodiments, the thickness of the resonance assist layer RAL may be for the first sub - pixel SP1, the second sub - pixel SP2, and the third sub - pixel SP3 (see Figure 7) varies for each of them. The light emitted from the corresponding light-emitting structure EMS has different optimal resonance amplification thicknesses for each other. When the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 correspond to red, green, and blue respectively, the thickness of the resonance assist layer RAL of the first sub-pixel SP1 can be thinner than the thickness of the resonance assist layer RAL of the second sub-pixel SP2, and the thickness of the resonance assist layer RAL of the second sub-pixel SP2 can be thinner than the thickness of the resonance assist layer RAL of the third sub-pixel SP3. The resonance thickness of the first sub-pixel SP1 can be thinner than the resonance thickness of the second sub-pixel SP2, and the resonance thickness of the second sub-pixel SP2 can be thinner than the thickness of the resonance assist layer RAL of the third sub-pixel SP3.

[0168] The anode electrode AE overlapping with the metal layer ML is positioned on the resonance assist layer RAL. Additionally, each of the plurality of anode electrodes AE is positioned on the metal layer ML exposed by the resonance assist layer RAL. For example, each of the plurality of anode electrodes AE can be positioned on the portion of the top surface of the third metal layer ML3 exposed by the resonance assist layer RAL.

[0169] The anode electrode AE can be connected to the metal layer ML through a contact layer CTL penetrating the metal layer ML. For example, the anode electrode AE can be connected to the second metal layer ML2 through a contact layer CTL penetrating the third metal layer ML3. The anode electrode AE adjacent to the contact layer CTL can have an annular shape. For example, each of the plurality of anode electrodes AE positioned on the portion of the top surface of the third metal layer ML3 can have a hole penetrating its center.

[0170] According to some embodiments, the anode electrode AE can include at least one of various transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the embodiments according to the present disclosure are not limited thereto.

[0171] The contact layer CTL is positioned on the metal layer ML. The contact layer CTL can be electrically connected to the anode electrode AE. The contact layer CTL can partially penetrate the metal layer ML. According to some embodiments, the contact layer CTL can penetrate the third metal layer ML3 such that the second metal layer ML2 is exposed. The contact layer CTL can contact the top surface of the second metal layer ML2 while penetrating the third metal layer ML3, but the embodiments are not limited thereto. For example, the contact layer CTL can not only partially penetrate the third metal layer ML3, but also partially penetrate the second metal layer ML2. The contact layer CTL can electrically connect the second metal layer ML2 having a higher conductivity than that of the third metal layer ML3 to the anode electrode AE, thereby improving the electrical connection characteristics between the anode electrode AE and the metal layer ML. In addition, the contact layer CTL can reduce or prevent problems caused by the disconnection between the metal layer ML and the anode electrode AE adjacent to the resonance assist layer RAL or the increase in resistance due to the reduction in thickness. Therefore, the electrical characteristics of the display device 100 (see Figure 1 ) can be improved.

[0172] The contact layer CTL can include at least one of aluminum (Al), tungsten (W), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and titanium (Ti). However, the embodiments according to the present disclosure are not limited thereto.

[0173] The pixel defining layer PDL is disposed over a part of the anode electrode AE, the resonance assist layer RAL, and the contact layer CTL. The pixel defining layer PDL can include an opening OP (see Figure 4 ) that exposes a part of each of the plurality of anode electrodes AE. The opening OP of the pixel defining layer PDL can define the emission region of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (see Figure 7 ). Therefore, the pixel defining layer PDL can define the first emission region EMA1 to the third emission region EMA3 shown in Figure 7 while being positioned in the non-emission region NEA.

[0174] According to some embodiments, the pixel defining layer PDL can include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers can include at least one of silicon oxide (SiO x ) and silicon nitride (SiN x ). For example, the pixel defining layer PDL can include a first inorganic insulating layer to a third inorganic insulating layer stacked in sequence, and each of the first inorganic insulating layer to the third inorganic insulating layer can include silicon nitride, silicon oxide, and silicon oxynitride. However, the embodiments according to the present disclosure are not limited thereto.

[0175] The light-emitting structure EMS can be positioned on the anode electrode AE exposed by the opening OP of the pixel defining layer PDL (see Figure 4 ). The light-emitting structure EMS fills the opening OP of the pixel defining layer PDL and can be disposed entirely over the first sub-pixel SP1. The light-emitting structure EMS fills the opening OP of the pixel defining layer PDL and can be disposed entirely over Figure 7 the second sub-pixel SP2 and the third sub-pixel SP3 shown in

[0176] The cathode electrode CE is positioned on the light-emitting structure EMS. The cathode electrode CE can be commonly provided in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (see Figure 7 ). The cathode electrode CE can be used as a semi-mirror that allows part of the light emitted from the light-emitting structure EMS to transmit through it and part to be reflected from it.

[0177] Figure 11 is a cross-sectional view taken along the line I-I’ shown in Figure 7 according to some embodiments of the present disclosure. In Figure 11 , for clarity and brief description, a cross-sectional view of the first sub-pixel SP1 among the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 shown in Figure 7 is schematically illustrated. The other sub-pixels can be configured in the same manner as the cross-section of the first sub-pixel SP1. Regarding Figure 1 , the description of the portions overlapping with the portions shown in Figure 11 will be omitted or simplified. Figure 10 the portions shown in

[0178] Referring to Figure 11 , the protective layer PL is positioned on the contact layer CTL and a portion of the anode electrode AE. The protective layer PL can include a transparent metal oxide. For example, the protective layer PL can include at least one of indium zinc oxide (IZO) and indium gallium zinc oxide (IGZO), but is not limited thereto according to embodiments of the present disclosure. The protective layer PL can include an opening that exposes one surface of each of the plurality of anode electrodes AE. When forming the opening OP of the pixel defining layer PDL (see Figure 4 ), the protective layer PL can protect the anode electrode AE.

[0179] The pixel defining layer PDL is positioned on the resonance assist layer RAL, a portion of the anode electrode AE, the protective layer PL, and a portion of the light-emitting structure EMS. The pixel defining layer PDL can have an undercut structure due to the protective layer PL. Thus, the light-emitting structure EMS can be at least cut or bent. For example, since the p-hole injection layer doped with a p-type dopant included in the light-emitting structure EMS is cut or bent, a discontinuous portion can be formed in the light-emitting structure EMS.

[0180] In addition, when the light-emitting structure EMS has a series structure including two or more light-emitting units, since the charge generation layer CGL (see Figure 5 ) included in the light-emitting structure EMS is cut or bent, a discontinuous portion may be formed in the light-emitting structure EMS. Therefore, it is possible to reduce the current (or leakage current) leaking from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (see Figure 7 ) included in the light-emitting structure EMS to an adjacent sub-pixel through the layers included in the light-emitting structure EMS.

[0181] Figure 12 is a flowchart illustrating a method of manufacturing a display device according to some embodiments of the present disclosure. Although various operations are illustrated in Figure 12 , the embodiments according to the present disclosure are not limited thereto. For example, according to some embodiments, the method of manufacturing a display device may include additional operations or fewer operations, or the order of operations may be changed (unless otherwise explicitly stated or implied) without departing from the spirit and scope of the embodiments according to the present disclosure. Figures 13 to 20 is a schematic cross-sectional view illustrating aspects of the manufacturing method shown in Figure 12 according to some embodiments of the present disclosure.

[0182] Referring to Figure 12 , the method of manufacturing a display device may include an operation S100 of forming a metal layer, an operation S200 of forming a resonance assisting layer, an operation S300 of forming a first photosensitive pattern, an operation S400 of forming an anode electrode, an operation S500 of peeling the first photosensitive pattern, an operation S600 of etching the metal layer, an operation S700 of forming a contact layer, and an operation S800 of forming a pixel defining layer.

[0183] Referring to Figure 12 and Figure 13 , a metal layer ML (S100) is formed. For example, the metal layer ML may be formed on a via layer VIAL positioned on a pixel circuit layer PCL, and the pixel circuit layer PCL is positioned on a substrate SUB. According to some embodiments, the metal layer ML having a multi-layer structure may be formed by forming a first metal layer ML1 connected to a via VIA on the via layer VIAL, forming a second metal layer ML2 on the first metal layer ML1, and forming a third metal layer ML3 on the second metal layer ML2.

[0184] Referring to Figure 12 and Figure 14, a resonance assist layer RAL (S200) is formed. For example, the resonance assist layer RAL may be formed on a part of the via layer VIAL and the metal layer ML. After the resonance assist layer RAL is formed on the via layer VIAL and the metal layer ML, a part of the top surface of the third metal layer ML3 may be exposed by partially etching the resonance assist layer RAL. Additionally, a step difference may be generated in the resonance assist layer RAL by partially etching the resonance assist layer RAL.

[0185] Referring to Figure 12 and Figure 15 , a first photosensitive pattern PP1 (S300) is formed. For example, the first photosensitive pattern PP1 may be formed on the partially etched resonance assist layer RAL and the third metal layer ML3 exposed by the resonance assist layer RAL. The first photosensitive pattern PP1 may be patterned by applying a photosensitive material on the resonance assist layer RAL and the third metal layer ML3 and then exposing and developing the applied photosensitive material. According to some embodiments, the first photosensitive pattern PP1 may be patterned to have an inverted conical shape. This is for the purpose of patterning a later-described anodic electrode AE (see Figure 16 ) at a desired position.

[0186] Referring to Figure 12 and Figure 16 , an anodic electrode AE (S400) is formed. For example, the anodic electrode AE may be formed on a part of the resonance assist layer RAL and a part of the third metal layer ML3. Additionally, each of the plurality of anodic electrodes AE may be formed on the first photosensitive pattern PP1. That is, the anodic electrode AE may not be formed on the resonance assist layer RAL and the third metal layer ML3 that respectively overlap with the first photosensitive pattern PP1 having an inverted conical shape.

[0187] Referring to Figure 12 and Figure 17 , the first photosensitive pattern PP1 is stripped (S500). For example, the remaining first photosensitive pattern PP1 (see Figure 16 ) may be stripped and removed. In this process, the anodic electrode AE on the first photosensitive pattern PP1 may be removed together with the first photosensitive pattern PP1. Therefore, the anodic electrode AE overlapping with the metal layer ML may be formed on the resonance assist layer RAL. Additionally, the anodic electrode AE having an annular shape may be formed on the third metal layer ML3.

[0188] Referring to Figures 15 to 17 , the anodic electrode AE can be easily patterned into a desired pattern without any etching process. That is, the anodic electrode AE can be easily patterned into a desired pattern by using the stripping process of the first photosensitive pattern PP1.

[0189] Referring to Figure 12 and Figure 18, etch the metal layer ML (S600). For example, the third metal layer ML3 can be etched such that the second metal layer ML2 is exposed. For example, by applying a photosensitive material on the resonance assist layer RAL and the anode electrode AE, and then exposing and developing the applied photosensitive material to pattern the second photosensitive pattern PP2. Thereafter, the second photosensitive pattern PP2 and the anode electrode AE can be used as masks to etch the third metal layer ML3. Thus, the anode electrode AE of the resonance assist layer RAL extending onto the third metal layer ML3 can be used as a hard mask. Different from that shown in Figure 18 , the second metal layer ML2 can be exposed by further partially etching the second metal layer ML2.

[0190] Referring to Figure 12 and Figure 19 , form the contact layer CTL (S700). For example, the contact layer CTL can be formed on the second metal layer ML2. The contact layer CTL can be deposited on the second metal layer ML2 to a certain thickness (e.g., a set or predetermined thickness) to connect to the anode electrode AE. The anode electrode AE can be connected to the second metal layer ML2 having a relatively higher conductivity than that of the third metal layer ML3 through the contact layer CTL. Thus, the electrical connection characteristics between the anode electrode AE and the metal layer ML can be improved.

[0191] Referring to Figure 12 and Figure 20 , form the pixel defining layer PDL (S800). For example, the pixel defining layer PDL can be formed on the resonance assist layer RAL, a part of the anode electrode AE, and the contact layer CTL. The pixel defining layer PDL can be formed on a part of the anode electrode AE to expose the anode electrode AE.

[0192] Figure 21 is a flowchart illustrating a method of manufacturing a display device according to some embodiments of the present disclosure. Although various operations are shown in Figure 21 , the embodiments according to the present disclosure are not limited thereto. For example, according to some embodiments, the method of manufacturing a display device may include additional operations or fewer operations, or the order of operations may be changed (unless otherwise explicitly stated or implied) without departing from the spirit and scope of the embodiments according to the present disclosure. Regarding Figure 21 , the description of parts overlapping with those shown in Figures 12 to 20 will be simplified or omitted. Figures 22 to 24 is a schematic cross-sectional view illustrating operations S800 to S1000 in the manufacturing method shown in Figure 21 according to some embodiments of the present disclosure.

[0193] Referring to Figure 21, the method of manufacturing a display device may include an operation S100 of forming a metal layer, an operation S200 of forming a resonance assist layer, an operation S300 of forming a first photosensitive pattern, an operation S400 of forming an anode electrode, an operation S500 of stripping the first photosensitive pattern, an operation S600 of etching the metal layer, an operation S700 of forming a contact layer, an operation S800 of forming a protective layer, an operation S900 of forming a pixel defining layer, and an operation S1000 of etching the protective layer.

[0194] Refer to Figure 21 and Figure 22 , a protective layer PL (S800) is formed. For example, the protective layer PL may be formed on the anode electrode AE and the contact layer CTL. The protective layer PL may be patterned to cover the flat surface of the anode electrode AE.

[0195] Refer to Figure 21 and Figure 23 , a pixel defining layer PDL (S900) is formed. For example, the pixel defining layer PDL may be formed on a part of the resonance assist layer RAL, the anode electrode AE, and the protective layer PL. For example, after the pixel defining layer PDL is formed on the resonance assist layer RAL, the anode electrode AE, and the protective layer PL, the protective layer PL may be exposed by partially etching the pixel defining layer PDL. That is, the pixel defining layer PDL may be etched until the protective layer PL is exposed. The protective layer PL may be used as an etch stop layer, thereby preventing the top surface of each of the plurality of anode electrodes AE from being damaged in the process of etching the pixel defining layer PDL.

[0196] Refer to Figure 21 and Figure 24 , the protective layer PL is etched (S1000). For example, the protective layer PL may be partially etched such that the pixel defining layer PDL has an undercut structure. Thus, a protective layer PL exposing the anode electrode AE may be formed. When the pixel defining layer PDL has an undercut structure, since the p-hole injection layer or the charge generation layer CGL (refer to Figure 11 ) included in the light-emitting structure EMS (refer to Figure 5 ) positioned on the anode electrode AE is cut or bent, leakage current flowing between adjacent sub-pixels can be prevented.

[0197] Figure 25 is a block diagram illustrating a display system according to some embodiments of the present disclosure.

[0198] Refer to Figure 25 , the display system 1000 may include a processor 1100 and a first display device 1210 and a second display device 1220.

[0199] The processor 1100 can execute various tasks and various calculations. According to some embodiments, the processor 1100 may include an application processor (AP), a graphics processing unit (GPU), a microprocessor, a central processing unit (CPU), etc. The processor 1100 can be connected to other components of the display system 1000 through a bus system to control the components of the display system 1000.

[0200] In Figure 25 , it is illustrated that the display system 1000 includes a first display device 1210 and a second display device 1220. The processor 1100 can be connected to the first display device 1210 through a first channel CH1 and to the second display device 1220 through a second channel CH2.

[0201] Through the first channel CH1, the processor 1100 can transmit first image data IMG1 and a first control signal CTRL1 to the first display device 1210. The first display device 1210 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 can be configured in accordance with the display device 100 described with reference to Figure 1 . The first image data IMG1 and the first control signal CTRL1 can be respectively provided as Figure 1 the input image data IMG and the control signal CTRL shown in

[0202] Through the second channel CH2, the processor 1100 can transmit second image data IMG2 and a second control signal CTRL2 to the second display device 1220. The second display device 1220 can display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 can be configured in accordance with the display device 100 described with reference to Figure 1 . The second image data IMG2 and the second control signal CTRL2 can be respectively provided as Figure 1 the image data IMG and the control signal CTRL shown in

[0203] The display system 1000 may include a computing system for providing an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, or an ultra-mobile computer (UMPC). The display system 1000 may include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0204] Figure 26 is a perspective view showing an application example of the display system shown in Figure 25 according to some embodiments of the present disclosure.

[0205] Referring to Figure 26 , Figure 25 the display system 1000 shown in

[0206] can be applied to the head-mounted display device 2000. The head-mounted display device 2000 can be a wearable electronic device that can be worn on the user's head.

[0207] The head-mounted display device 2000 can include a head mounting band 2100 and a display device housing 2200. The head mounting band 2100 can be connected to the display device housing 2200. The head mounting band 2100 can include a horizontal band and / or a vertical band for fixing the head-mounted display device 2000 to the user's head. The horizontal band can be configured to surround the side portion of the user's head, and the vertical band can be configured to surround the upper portion of the user's head. However, embodiments of the present disclosure are not limited thereto. For example, the head mounting band 2100 can be implemented in the form of a glasses frame, a helmet, etc. Figure 25 The display device housing 2200 can accommodate Figure 25 the first display device 1210 and the second display device 1220 shown in

[0208] Figure 27 is a view of a head-mounted display device worn by a user according to some embodiments of the present disclosure. Figure 26 shown in

[0209] Referring to Figure 27 , the first display panel DP1 of the first display device 1210 and the second display panel DP2 of the second display device 1220 can be positioned in the head-mounted display device 2000. The head-mounted display device 2000 can further include a left eye lens LLNS and a right eye lens RLNS.

[0210] In the display device housing 2200, the right eye lens RLNS can be positioned between the first display panel DP1 and the user's right eye. In the display device housing 2200, the left eye lens LLNS can be positioned between the second display panel DP2 and the user's left eye.

[0211] The image output from the first display panel DP1 can be observed by the user's right eye through the right eye lens RLNS. The right eye lens RLNS can refract the light emitted from the first display panel DP1 to face the user's right eye. The right eye lens RLNS can perform an optical function for adjusting the viewing distance between the first display panel DP1 and the user's right eye.

[0212] The image output from the second display panel DP2 can be observed by the user's left eye through the left-eye lens LLNS. The left-eye lens LLNS can refract the light emitted from the second display panel DP2 towards the user's left eye. The left-eye lens LLNS can perform an optical function for adjusting the viewing distance between the second display panel DP2 and the user's left eye.

[0213] According to some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped cross-section. According to some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical characteristics. Each display panel may output images corresponding respectively to the sub-regions of the multi-channel lens, and the output images may be observed by the user while passing through the respective sub-regions.

[0214] The embodiments described in detail above are provided to explain the present disclosure, but these embodiments are not intended to limit the scope of the present disclosure. Those skilled in the art should understand that various changes, substitutions, and alterations can be made therein without departing from the scope of the present disclosure as defined by the appended claims and their equivalents.

[0215] The scope of the embodiments according to the present disclosure is not limited by the detailed description of this specification, but should be defined by the appended claims and their equivalents. In addition, all changes or modifications obtained from the claims and their equivalents according to the embodiments of the present disclosure should be construed as being included within the scope of the embodiments according to the present disclosure. Embodiments may be combined to form additional embodiments.

Claims

1. A display device having an emission area, the display device comprising: a metal layer, the metal layer being on the through-hole layer, and the metal layer overlapping the emission area; a resonance auxiliary layer, the resonance auxiliary layer being on the through-hole layer and the metal layer, the resonance auxiliary layer exposing the metal layer; an anode electrode, the anode electrode being on the resonance auxiliary layer; as well as A contact layer is connected to the metal layer and the anode electrode.

2. The display device according to claim 1, wherein: The metal layer comprises: a first metal layer connected to a via of the via layer; a second metal layer, the second metal layer being on the first metal layer; and A third metal layer is on the second metal layer.

3. The display device according to claim 2, wherein: The electrical conductivity of the second metal layer is higher than that of the third metal layer.

4. The display device according to claim 3, wherein: The contact layer is connected to the second metal layer and penetrates the third metal layer.

5. The display device according to claim 1, further comprising: A pixel defining layer is provided on the resonance auxiliary layer, the anode electrode and the contact layer, and the pixel defining layer exposes the anode electrode.

6. The display device according to claim 1, further comprising: A protection layer is disposed on the anode electrode and the contact layer, and the protection layer exposes the anode electrode.

7. The display device according to claim 6, further comprising: A pixel defining layer is provided on the resonance auxiliary layer, the anode electrode and the protection layer, and the pixel defining layer has an undercut structure.

8. The display device according to claim 1, wherein: The resonance auxiliary layer includes an inorganic material.

9. The display device according to claim 1, wherein: The contact layer includes a metal material.

10. A method for manufacturing a display device, the method comprising: forming a metal layer on the via layer; forming a resonance auxiliary layer exposing the metal layer on the through hole layer and the metal layer; forming a first photosensitive pattern on the resonance auxiliary layer and the exposed metal layer; forming an anode electrode on the resonance auxiliary layer and the first photosensitive pattern; peeling off the first photosensitive pattern; as well as A contact layer is formed penetrating the metal layer.

11. The method for manufacturing a display device according to claim 10, wherein: Forming the metal layer comprises: forming a first metal layer of vias connected to the via layer; forming a second metal layer on the first metal layer; and A third metal layer is formed on the second metal layer.

12. The method for manufacturing a display device according to claim 11, wherein: The electrical conductivity of the second metal layer is higher than that of the third metal layer.

13. The method for manufacturing a display device according to claim 10, wherein: The first photosensitive pattern is formed in an inverted tapered shape.

14. The method for manufacturing a display device according to claim 11, wherein: Forming the contact layer comprises: forming a second photosensitive pattern on the resonance auxiliary layer and the anode electrode; etching the third metal layer so that the second metal layer is exposed; peeling off the second photosensitive pattern; and The contact layer is formed on the exposed second metal layer to be connected to the anode electrode.

15. The method for manufacturing a display device according to claim 10, further comprising: A pixel defining layer exposing the anode electrode is formed on the resonance auxiliary layer, the anode electrode and the contact layer.

16. The method for manufacturing a display device according to claim 10, further comprising: A protection layer is formed on the contact layer and the anode electrode.

17. The method for manufacturing a display device according to claim 16, further comprising: A pixel defining layer exposing the protection layer is formed on the resonance auxiliary layer, the anode electrode, and the protection layer.

18. The method for manufacturing a display device according to claim 17, further comprising: The protection layer is etched so that the pixel defining layer has an undercut structure.

19. The method for manufacturing a display device according to claim 10, wherein: The resonance auxiliary layer includes an inorganic material.

20. The method for manufacturing a display device according to claim 10, wherein: The contact layer includes a metal material.

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