Display panel, preparation method thereof and display device

Abstract

The invention provides a display panel, a preparation method of the display panel and a display device. A first protective layer disposed on the substrate; the driving function layer is arranged on the side, away from the substrate, of the first protection layer, and the driving function layer comprises at least one transistor and an electrical structure located on one side of the transistor; wherein the first protection layer is configured to collect electric field lines from the electrical structure to the transistor. By suppressing the electric field intensity in the substrate, the movement of ions in the substrate is weakened, the transistor performance is improved, and the residual image problem of the display panel is further improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel, a preparation method thereof, and a display device. Background Art

[0002] Polyimide (PI for short) is a high-performance organic polymer material, which is widely used in the microelectronics field due to its excellent thermal stability, chemical stability, and mechanical properties. Especially in flexible display technologies, the PI substrate, as a supporting material, can withstand high-temperature processes without deformation, and at the same time endows the display with flexibility, making it an ideal choice for manufacturing flexible organic light-emitting diodes (OLEDs) and liquid crystal displays (LCDs).

[0003] However, the inventors of the present application have found that in the related art, during the operation of a display device, the transistors in the display device may experience performance degradation due to long-term exposure to electrical stress, especially the drift of the threshold voltage (Vth). The instability of Vth will lead to a decline in the display picture quality, thereby affecting the electrical performance and reliability of the device, and may even cause adverse phenomena such as image retention. Summary of the Invention

[0004] In view of this, an object of the present application is to provide a display panel, a preparation method thereof, and a display device to solve or partially solve the above problems.

[0005] As an aspect of the present application, a display panel is provided, including:

[0006] A substrate;

[0007] A first protective layer disposed on the substrate;

[0008] A driving functional layer disposed on a side of the first protective layer away from the substrate, the driving functional layer including at least one transistor and an electrical structure located on one side of the transistor;

[0009] Wherein, the first protective layer is configured to: converge the electric field lines from the electrical structure to the transistor.

[0010] Optionally, the material for manufacturing the first protective layer includes a material with a dielectric constant higher than a first dielectric constant threshold.

[0011] Optionally, the driving functional layer includes a plurality of pixel circuits arranged in an array in a display area of the display panel, the pixel circuit including at least one first transistor and a first electrical device located on one side of the first transistor;

[0012] The first protective layer is configured to: converge the electric field lines from the first electrical device to the first transistor.

[0013] Optionally, the driving functional layer includes a gate driving circuit located in the non-display area of the display panel, and the gate driving circuit includes at least one second transistor and a second electrical device located on one side of the second transistor;

[0014] The first protective layer is configured to: converge the electric field lines from the second electrical device to the second transistor.

[0015] Optionally, the electrical structure includes a signal line for providing an electrical signal to the display panel.

[0016] Optionally, the signal line includes a data line.

[0017] Optionally, the display panel further includes:

[0018] A second protective layer, located between the first protective layer and the driving functional layer;

[0019] Wherein, the material for manufacturing the second protective layer includes a material with a dielectric constant lower than a second dielectric constant threshold, and the second dielectric constant threshold is less than or equal to the first dielectric constant threshold.

[0020] Optionally, the material for manufacturing the substrate includes polyimide.

[0021] As a second aspect of the present application, a method for manufacturing a display panel is provided, including:

[0022] Providing a substrate;

[0023] Forming a first protective layer on the substrate;

[0024] Forming a driving functional layer on the first protective layer, the driving functional layer includes at least one transistor and an electrical structure located on one side of the transistor;

[0025] Wherein, the first protective layer is configured to: converge the electric field lines from the electrical structure to the transistor.

[0026] Optionally, the material for manufacturing the first protective layer includes a material with a dielectric constant higher than a first dielectric constant threshold.

[0027] Optionally, after forming the first protective layer on the substrate, the method further includes:

[0028] A second protective layer is formed on the first protective layer, and the material used to fabricate the second protective layer includes a material with a dielectric constant lower than a second dielectric constant threshold, and the second dielectric constant threshold is less than or equal to the first dielectric constant threshold.

[0029] As a third aspect of the present application, a display device is provided, including the display panel described in the first aspect.

[0030] As can be seen from the above, for the display panel, the manufacturing method thereof, and the display device provided in the present application, by providing a first protective layer between the substrate and the driving functional layer, and the first protective layer is used to converge the electric field lines from the electrical structure to the transistor, which helps to control and guide the distribution of the electric field lines, making the electric field lines concentrated in the protective layer, suppressing the electric field intensity inside the substrate, thereby weakening the movement of ions in the substrate, improving the transistor performance, and further improving the display defect problem.

[0031] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the description. And in order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention are specifically exemplified below. Description of the Drawings

[0032] In order to more clearly illustrate the technical solutions in the present application or related technologies, the following will briefly introduce the drawings required for use in the embodiments or related technology descriptions. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0033] Figure 1 A schematic block diagram of a display device provided by an embodiment of the present application;

[0034] Figure 2A A schematic block diagram of a display panel provided by an embodiment of the present application;

[0035] Figure 2B A schematic circuit structure diagram of a display panel provided by an embodiment of the present application;

[0036] Figure 2C A schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0037] Figure 3A A schematic structure diagram of a display panel provided by an embodiment of the present application;

[0038] Figure 3B A schematic structure diagram of another display panel provided by an embodiment of the present application;

[0039] Figure 3C Schematic diagram of another structure of the display panel provided by the embodiment of the present application;

[0040] Figure 4 Flowchart of a method for manufacturing a display panel provided by the embodiment of the present application. Detailed implementation manners

[0041] To make the objectives, technical solutions and advantages of the present application clearer and more understandable, the following further describes the present application in detail with reference to specific embodiments and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0042] It should be noted that in the embodiments of the present application, words such as "exemplarily" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplarily" or "for example" in the embodiments of the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplarily" or "for example" is intended to present relevant concepts in a specific manner. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the ordinary meaning understood by those of ordinary skill in the art to which the present application belongs.

[0043] It should be noted that unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the ordinary meaning understood by those of ordinary skill in the art to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. Words such as "comprising" or "including" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. "Connection" or "coupling" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to represent relative position relationships, and when the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0044] In describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral one; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical contact or electrical contact. The term "coupled" or "communicatively coupled" may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0045] As used in the specification and claims of this application, "parallel", "perpendicular", and "equal" include the described situations and situations similar to the described situations, and the range of the similar situations is within an acceptable deviation range, where the acceptable deviation range is determined by those of ordinary skill in the art considering the measurements being discussed and the errors associated with the measurements of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, and the acceptable deviation range for approximate parallelism can be, for example, within 5° deviation; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, and the acceptable deviation range for approximate perpendicularity can also be, for example, within 5° deviation. "Equal" includes absolute equality and approximate equality, and the acceptable deviation range for approximate equality can be, for example, that the difference between the two equal ones is less than or equal to 5% of either one.

[0046] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0047] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of the regions are enlarged for clarity. Therefore, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Accordingly, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0048] Figure 1 A schematic block diagram of a display device provided by some embodiments of the present disclosure is shown.

[0049] As Figure 1As shown, the display device 100 includes a display panel 200, a gate driver 102, a timing controller 104, and a data driver 106. The display panel 200 includes a plurality of pixel units P defined by the intersection of a plurality of scan lines Scan and a plurality of data lines Data. The display panel 200 may be, for example, the display panel provided in any embodiment of the present disclosure. The gate driver 102 is configured to drive a plurality of scan lines GL; the data driver 106 is configured to drive a plurality of data lines DL; the timing controller 104 is configured to process the image data RGB input from outside the display device 100, provide the processed image data RGB to the data driver 106, and output a scan control signal GCS and a data control signal DCS to the gate driver 102 and the data driver 106 to control the gate driver 102 and the data driver 106.

[0050] For example, the gate driver 102 may be implemented as a semiconductor chip or integrated in the display panel 200 to form a gate driver on array (GOA) circuit.

[0051] For example, the data driver 106 converts the digital image data RGB input from the timing controller 104 into a data signal according to a plurality of data control signals DCS from the timing controller 104 using a reference gamma voltage. The data driver 106 provides the converted data signal to a plurality of data lines DL. For example, the data driver 106 may be implemented as a semiconductor chip.

[0052] For example, the timing controller 104 processes the externally input image data RGB to match the size and resolution of the display panel 200, and then provides the processed image data to the data driver 106. The timing controller 104 generates a plurality of scan control signals GCS and a plurality of data control signals DCS using the synchronization signals (such as dot clock DCLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync) input from outside the display device 100. The timing controller 104 respectively provides the generated scan control signal GCS and data control signal DCS to the gate driver 104 and the data driver 106 for controlling the gate driver 102 and the data driver 106. The display device 100 may further include other components, such as a signal decoding circuit, a voltage conversion circuit, etc. These components may be, for example, existing conventional components and will not be elaborated here. The display device 100 may be applied to any product or component with a display function, such as an e-book, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0053] Figure 2A It is a schematic block diagram of a display panel provided in some embodiments of the present disclosure.

[0054] As Figure 2A shown, in some embodiments, the display panel 200 may include a plurality of pixel units 201 and a gate driving circuit 202. Among them, the plurality of pixel units 201, for example, may be arranged in an array. Each pixel unit 201 may further include a pixel circuit 2011. The gate driving circuit 202 (i.e., the gate driver 102) may include a plurality of cascaded GOA circuits 2021. For example, the display panel 200 may be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, or other applicable display panels. Each pixel unit 201 not only includes the pixel circuit 2011, but may also include a light-emitting element (such as an OLED, a QLED, etc.).

[0055] For example, the display panel 200 may be a rectangular panel, a circular panel, an oval panel, or a polygonal panel, etc. In addition, the display panel 200 may not only be a flat panel, but also a curved panel, or even a spherical panel, etc. For example, the display panel 200 may also have a touch function, that is, the display panel 200 may be a touch display panel. For example, the display panel 200 may be applied to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. For example, the display panel 200 may be a flexible display panel, so as to meet various actual application requirements. For example, the display panel 200 may be applied to a curved screen, etc.

[0056] For the sake of clarity and conciseness, the embodiments of the present disclosure do not show all the constituent units of the display panel 200. To implement the basic functions of the display panel 200, those skilled in the art may provide and set other structures not shown according to specific needs, and the embodiments of the present disclosure do not limit this. Figure 2B The partial circuit structure diagram of the display panel 200 provided by some embodiments of the present disclosure is shown.

[0057] As Figure 2B shown, the circuit includes a pixel unit 201 and a gate driving circuit 202. In the display panel 200, a plurality of gate lines 201A and a plurality of data lines 201B are arranged in an array and intersect to define a plurality of pixel circuits 2011.

[0058] Exemplarily, taking the OLED panel as an example, as Figure 2B shown, the pixel circuit used in the display panel 200 may be a 2T1C pixel circuit, that is, two thin-film transistors (TFTs) and a storage capacitor Cs are used to implement the basic function of driving the OLED to emit light. As Figure 2BAs shown, in a 2T1C pixel circuit, a switching transistor T0, a driving transistor N0, and a storage capacitor Cs may be included. For example, the gate of the switching transistor T0 is connected to a scan line (e.g., Figure 1 the scan line GL) to receive a scan signal Scan1, the first pole is connected to a data line (e.g., Figure 1 the data line DL) to receive a data signal Vdata, and the second pole is connected to the gate of the driving transistor N0. The first pole of the driving transistor N0 is connected to a first voltage terminal to receive a first voltage Vdd (e.g., a high voltage), and the second pole is connected to the anode of the OLED. One end of the storage capacitor Cs is connected to the second pole of the switching transistor T0 and the gate of the driving transistor N0, and the other end is connected to the first pole of the driving transistor N0 and the first voltage terminal. The cathode of the OLED is connected to a second voltage terminal to receive a second voltage Vss (a low voltage, e.g., a ground voltage).

[0059] The driving method of this 2T1C pixel circuit is to control the brightness (gray scale) of the pixel via two TFTs and the storage capacitor Cs. When a scan signal Scanl is applied through the scan line to turn on the switching transistor T0, the data signal Vdata sent by the data driving circuit through the data line will charge the storage capacitor Cs via the switching transistor T0, thereby storing the data signal Vdata in the storage capacitor Cs, and the stored data signal Vdata controls the conduction degree of the driving transistor N0, thereby controlling the magnitude of the current flowing through the driving transistor to drive the OLED to emit light, that is, this current determines the gray scale of the pixel's light emission. In Figure 2B the 2T1C pixel circuit shown, the switching transistor T0 may be an N-type transistor and the driving transistor N0 may be a P-type transistor.

[0060] As Figure 2C shown, the pixel circuit 2011 may also be another 2T1C pixel circuit, including a switching transistor T0, a driving transistor N0, and a storage capacitor Cs, but its connection method is slightly changed, and the driving transistor N0 is an N-type transistor. Figure 2C The pixel circuit with respect to Figure 2B the changes include: the anode of the OLED is connected to the first voltage terminal to receive the first voltage Vdd (e.g., a high voltage), and the cathode is connected to the drain of the driving transistor N0. The first pole of the driving transistor N0 is connected to the second voltage terminal to receive the second voltage Vss (a low voltage, e.g., a ground voltage). One end of the storage capacitor Cs is connected to the second pole of the switching transistor TO and the gate of the driving transistor N0, and the other end is connected to the first pole of the driving transistor N0 and the second voltage terminal. The working method of this 2T1C pixel circuit is basically the same as that of the pixel circuit shown in Figure 2B , which will not be elaborated here.

[0061] In addition, forFigure 2B and Figure 2C For the pixel circuit shown, the switching transistor T0 is not limited to an N-type transistor and can also be a P-type transistor. Accordingly, the polarity of the scan signal Scanl for controlling its conduction or cutoff can be changed correspondingly.

[0062] The OLED display device generally includes a plurality of pixel units arranged in an array, and each pixel unit can include the above pixel circuit, for example. In the OLED display device, the threshold voltages of the driving transistors in each pixel circuit may vary due to the manufacturing process, and the threshold voltages of the driving transistors may drift due to, for example, the influence of temperature changes. Therefore, the difference in the threshold voltages of each driving transistor may cause poor display (such as uneven display), so it is necessary to compensate for the threshold voltage. At the same time, when the transistor is in the off state, the existence of leakage current may also cause poor display. Therefore, other pixel circuits with compensation functions can also be provided on the basis of the above 2T1C pixel circuit. The compensation function can be achieved through voltage compensation, current compensation or hybrid compensation. The pixel circuit with compensation function can be 4TIC or 4T2C, etc., which will not be elaborated here.

[0063] Returning to Figure 2B , the shift register unit (i.e., the GOA circuit 2021) corresponding to the pixel circuit 2011 of the nth row (n is greater than or equal to 2) of the gate driving circuit 202 can further include a transistor T1, a transistor T2, a transistor T3, a transistor T4 and a storage capacitor C1.

[0064] The transistor T1 in the shift register unit is the output transistor of the signal output end of the shift register unit. For example, the first pole of the transistor T1 is connected to the first clock signal CLK1, and the second pole of the transistor T1 is connected to the first pole of the transistor T2 to obtain the output end of the shift register unit, and can output the gate scan signal Gn for the pixel circuit 2011 of the nth row (this signal is a square wave pulse signal, and correspondingly the pulse part is the on level and the non-pulse part is the off level), and the input signal for the next-stage shift register unit. As Figure 2B shown, the gate scan signal Gn can provide the scan signal Scan1 for the pixel circuit. The gate of the transistor T1 is connected to the pull-up node PU, and thus is connected to the first pole of the transistor T3 and the second pole of the transistor T4.

[0065] The second pole of transistor T2 is connected to the second pole of transistor T3 and the low-level signal VGL. The gate of transistor T2 is connected to the gate of transistor T3 and the output terminal of the shift register unit of the next row, i.e., the (n + 1)-th row, to receive the gate scan signal G(n + 1) as the output pull-down control signal. The first pole of transistor T2 is connected to the second pole of transistor T1, so it can be turned on under the control of the pull-down control signal, and pull down the output signal at the output terminal to the low-level signal VGL when the gate scan signal Gn is not required to be output.

[0066] The first pole of transistor T3 is also connected to the pull-up node PU, and thus is electrically connected to the second pole of transistor T4 and the gate of transistor T1. The second pole of transistor T3 is connected to the low-level signal VGL. The gate of transistor T3 is also connected to the output terminal of the shift register unit of the next row, i.e., the (n + 1)-th row, to receive the gate scan signal G(n + 1) as the reset control signal (which is also the output pull-down control signal), so that it can be turned on under the control of this reset control signal, reset the pull-up node PU to the low-level signal VGL, and thus turn off transistor T1.

[0067] The first pole of transistor T4 is connected to its own gate, and is connected to the output terminal of the shift register unit of the previous row, i.e., the (n - 1)-th row, to receive the gate scan signal G(n - 1) as the input signal (and the input control signal). The second pole of transistor T4 is connected to the pull-up node PU, so that when transistor T4 is turned on, the pull-up node PU can be charged, so that the voltage of the pull-up node PU can turn on transistor T1, and thus the first clock signal CLK1 is output through the output terminal. One end of the storage capacitor C1 is connected to the gate of transistor T1, i.e., the pull-up node PU, and the other end is connected to the second pole of transistor T1, so that the level of the pull-up node PU can be stored, and the level of the pull-up node PU can be further pulled up through its own bootstrap effect when transistor T1 is turned on for output to improve the output performance.

[0068] When the gate driving circuit operates, when the gate scanning signal G(n - 1) is at a high level, the transistor T4 conducts and charges the pull-up node PU. The rising level of the pull-up node PU causes the transistor T1 to conduct. Therefore, the first clock signal CLK1 can be output at the output terminal through the transistor T1, that is, the gate scanning signal Gn is equal to the first clock signal CLK1. When the first clock signal CLK1 is at a high level, the gate scanning signal Gn also outputs a high level. When the gate scanning signal Gn is at a high level, the shift register unit (i.e., the GOA circuit 2021) of the gate driving circuit 202 inputs this high-level signal Gn to the gate lines 201A of the corresponding rows of the display panel, so that the gates of all the switching transistors T0 in the pixel circuits 2011 corresponding to the row of gate lines 201A are applied with this signal (for example, the scanning signal Scan1), so that these switching transistors T0 are all turned on. The data signal Vdata is input to the storage capacitor Cs of the corresponding pixel circuit 2011 through the switching transistor T0 in each pixel circuit to charge the storage capacitor Cs in the corresponding pixel circuit 2011, thereby realizing the writing and holding of the signal voltage of the pixel circuit 2011. When the gate scanning signal G(n + 1) is at a high level, the transistors T2 and T3 are turned on, achieving the effect of resetting the pull-up node PU and pulling down the output terminal. Therefore, through the gate driving circuit 202, for example, the function of driving the display panel 200 line by line can be realized.

[0069] Since the sources and drains of the above-mentioned various transistors are symmetric, their sources and drains can be interchanged. The first pole can be, for example, the source or the drain, and the second pole can be, for example, the drain or the source. In the present disclosure, the sources and drains of the thin-film transistors are collectively referred to as "source-drains", and are distinguished as the first source-drain and the second source-drain. For example, the above-mentioned various transistors can be N-type transistors. Of course, the above-mentioned various transistors are not limited to N-type transistors, and can also be at least partially P-type transistors. Thus, the polarities of the corresponding turn-on signal STV and the output scanning signal can be changed accordingly.

[0070] It should be noted that in the embodiments of the present disclosure, the structure of the shift register unit of the gate driving circuit 202 is not limited to the structure described above. The shift register unit of the gate driving circuit 202 can be any applicable structure, and can also include more or fewer transistors and / or capacitors. For example, sub-circuits for realizing functions such as pull-up node control, pull-down node control, and noise reduction are added. The embodiments of the present disclosure do not limit this.

[0071] Figure 3A A schematic cross-sectional structure diagram of an exemplary display panel 200 is shown.

[0072] As Figure 3AAs shown, exemplarily, along the light-emitting direction of the display panel 200, a substrate 302, a buffer layer 304, and a driving functional layer 306 can be sequentially arranged. The buffer layer 304 is disposed on the substrate 302; the driving functional layer 306 is disposed on a side of the buffer layer 304 away from the substrate 302, and the driving functional layer includes at least one transistor 310 and an electrical structure 3072 located on one side of the transistor 310.

[0073] In some embodiments, the electrical structure 3072 can be Figures 1 to 2C electrical devices and signal traces other than transistors in Figures 1 to 2C . Therefore, the electrical structure 3072 can generate an external electric field, such that electric field lines are evenly distributed between the electrical structure 3072 and the transistor 310. Among them, some electric field lines pass through the substrate 302, resulting in the substrate 302 being affected by electrical stress for a long time. Ions in the substrate 302 move under the action of the external electric field, resulting in uneven distribution of ions in the substrate 302, and thus generating an unevenly distributed electric field in the substrate 302 (as shown in Figure 3A ), and the transistor 310 is affected by such an electric field, resulting in performance degradation and a decrease in the display picture quality. In particular, when the manufacturing material of the substrate 302 is polyimide, this problem is more serious.

[0074] In view of this, embodiments of the present disclosure provide a display panel to at least partially solve this problem.

[0075] Figure 3B It is a schematic structural diagram of a display panel provided by an embodiment of the present application.

[0076] As Figure 3B shown, the display panel 200 includes: a substrate 302; a first protective layer 308 disposed on the substrate 302; a driving functional layer 306 disposed on a side of the first protective layer 308 away from the substrate 302, and the driving functional layer 306 includes at least one transistor 310 and an electrical structure 3072 located on one side of the transistor 310. Among them, the first protective layer 308 is configured to: collect the electric field lines from the electrical structure 3072 to the transistor 310. In this way, by using the first protective layer 308 to collect the electric field lines from the electrical structure 3072 to the transistor 310, it helps to control and guide the distribution of the electric field lines, such that at least most of the electric field lines are concentrated in the protective layer, reducing the influence of the electric field lines on the substrate, further weakening the movement of ions in the substrate, thereby suppressing the internal electric field strength of the substrate, improving the transistor performance, and further improving the display defect problem. Exemplarily, by using methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or sputtering, one or more layers of the first protective layer can be uniformly deposited above the substrate 302.

[0077] In some embodiments, the transistor 310 may be a thin film transistor (TFT). Optionally, as Figure 3B shown, the transistor 310 may further include an active layer 3064, a first insulating layer 3062, a gate 3066, a second insulating layer 3068, and source / drain electrodes 3070. Among them, the source / drain electrodes 3070 may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0078] Optionally, a buffer layer 304 is included between the substrate 302 and the first protective layer 308. The buffer layer 304 can absorb and disperse the stress between the substrate 302 and the first protective layer 308 caused by the applied electrodes, thereby reducing the influence of these stresses on the transistor performance. At the same time, the buffer layer 304 helps to planarize the surface of the substrate 302, provides a more uniform attachment surface for the subsequent deposition of the first protective layer 308, and helps to improve the coverage quality and electrical performance of the first protective layer 308. In addition, the buffer layer 304 can act as an additional dielectric layer to help further optimize the electric field distribution, reduce the direct impact of the electric field on the substrate 302, and thus improve the stability of the transistor.

[0079] In some embodiments, the material of the active layer 3064 may be low temperature poly-silicon (Slow Temperature Poly-silicon, abbreviated as LTP), or may be an oxide (Oxide) such as indium gallium zinc oxide. The low temperature poly-silicon thin film transistor has advantages such as high mobility and fast charging, and the oxide thin film transistor has advantages such as low leakage current. In some examples, the low temperature poly-silicon thin film transistor and the oxide thin film transistor can be integrated on a display panel to form a low temperature polycrystalline oxide display panel. By utilizing the advantages of both, high resolution (pixel per inch, abbreviated as PPI), low frequency driving can be achieved, power consumption can be reduced, and display quality can be improved. However, this embodiment is not limited thereto.

[0080] In some embodiments, the first insulating layer 3062 may be referred to as a gate insulating (GI) layer and serves as an insulating layer between the gate 3066 and the active layer 3064.

[0081] In some embodiments, the electrical structure 3072 is disposed on the same layer as the gate 3066, so that a pattern including the electrical structure 3072 and the gate 3066 can be formed by using a single patterning process.

[0082] In some exemplary embodiments, the material for fabricating the first protective layer 308 includes a material having a dielectric constant higher than a first dielectric constant threshold. The first dielectric constant threshold can be set as needed, for example, 3.9 to 200. Optionally, the material for fabricating the first protective layer 308 can be, for example, at least one of high dielectric constant (High-K) materials such as silicon nitride (SiN x ), aluminum oxide (Al2O3), titanium dioxide (TiO2), hafnium oxide (HfO2), etc. Among them, the first protective layer 308 can be a single-layer structure formed by the above single material or a stacked structure formed by at least two of the above materials, such as SiN x / Al2O3 or TiO2 / SiN x / HfO2.

[0083] It should be noted that the first dielectric constant threshold can be the dielectric constant value of silicon dioxide, which is 3.9. That is to say, a material with a dielectric constant greater than 3.9 can be regarded as a High-K material. Using a High-K material to fabricate the first protective layer 308 can make the electric field lines generated by an externally applied electric signal more concentrated in the first protective layer 308, and only a very small number of electric field lines can enter the substrate 302. Thus, the electric field intensity inside the substrate 302 can be reduced to a greater extent, and the degree of ion movement or molecular polarization in the substrate 302 can be weakened.

[0084] In the display panel of the related art, the electric field lines are disorderly distributed, resulting in unnecessary electric field interference on the transistor. Under the condition of long-term electrical stress, the performance of the transistor will degenerate, such as the drift of the threshold voltage (Vth). This degradation phenomenon will lead to a decrease in the display picture quality and affect the electrical performance and reliability of the device. By using a material with a dielectric constant higher than a certain threshold in the first protective layer, the electric field lines from the electrical structure 3072 to the transistor 310 are effectively concentrated. This design makes the electric field lines more orderly, reduces the interference of the electric field on the transistor, and thus improves the stability and reliability of the transistor.

[0085] In some embodiments, the driving functional layer 306 includes a plurality of pixel circuits (for example, Figure 2A the pixel circuit 2011) arranged in an array in the display area of the display panel. Exemplarily, as Figures 2A to 2C shown, the pixel circuit may further include at least one first transistor (for example, a switching transistor T0, a driving transistor N0, etc.) and a first electrical device (for example, an OLED, a storage capacitor Cs, a signal line of the first voltage Vdd, a signal line of the second voltage Vss, a scan line 201A, a data line 201B, etc.) located on one side of the first transistor; the first protective layer 308 is configured to: concentrate the electric field lines from the first electrical device to the first transistor.

[0086] In this way, by providing a first protective layer 308 under the pixel circuit in the display area to reduce the ion movement of the substrate 302 under the pixel circuit, the performance of the transistors in the pixel circuit can be effectively improved. Moreover, since the change in the threshold voltage of the driving transistor N0 has a crucial impact on the display effect, by providing a first protective layer 308 under the pixel circuit to reduce the ion movement of the substrate 302 under the pixel circuit, the display effect can be effectively improved.

[0087] In some embodiments, the driving functional layer 306 includes a gate driving circuit located in the non-display area of the display panel (e.g., Figure 2A the gate driving circuit 202). Exemplarily, as Figure 2B shown, the gate driving circuit (or GOA circuit) may further include at least one second transistor (e.g., transistors T1 to T4) and a second electrical device located on one side of the second transistor (e.g., storage capacitor C1, signal line of the first clock signal CLK1, signal line of the low-level signal VGL, etc.); the first protective layer 308 is configured to: converge the electric field lines from the second electrical device to the second transistor.

[0088] In this way, by providing a first protective layer 308 under the gate driving circuit in the non-display area to converge the electric field lines and reduce interference, the performance of the transistors in the gate driving circuit can be effectively improved.

[0089] Optionally, the electrical structure 3072 includes signal lines for providing electrical signals to the display panel. Among them, the signal lines include data lines, power lines, gate lines, etc.

[0090] In some embodiments, as Figure 3C shown, a second protective layer 308-1 may further be included between the first protective layer 308 and the driving functional layer 306, wherein the manufacturing material of the second protective layer 308-1 includes a material with a dielectric constant lower than the second dielectric constant threshold, and the second dielectric constant threshold is less than or equal to the first dielectric constant threshold.

[0091] In some exemplary embodiments, the manufacturing material of the second protective layer 308-1 includes a material with a dielectric constant lower than the second dielectric constant threshold, and the second dielectric constant threshold is less than or equal to the first dielectric constant threshold of 3.9. Therefore, a material with a dielectric constant lower than 3.9 can be regarded as a low dielectric constant (Low-K) material and is suitable for manufacturing the second protective layer 108-1. For example, the Low-K material may be a single-layer or laminated structure formed by organic polymer materials such as polyimide, benzocyclobutene (BCB), and fluorinated polyimide; it may also be a structure formed by porous silicon-based materials such as porous silica and porous alumina. Similarly, the second protective layer 308-2 may be a single-layer structure formed by the above single material or a laminated structure formed by at least two of the above materials.

[0092] It should be noted that when the electric field lines propagate from the first protective layer 308 with a high dielectric constant to the second protective layer 308-1 with a low dielectric constant, due to the change in the dielectric constant, the electric field lines will undergo a refraction phenomenon similar to that of light propagating between different media. This refraction effect helps to more intensively guide the electric field lines to the first protective layer 308, thereby reducing the distribution of the electric field inside the substrate and lowering the electric field strength. In addition, the propagation path of the electric field lines in the low-dielectric-constant material is shorter, and the electric field energy is more concentrated, further optimizing the distribution and shielding effect of the electric field and improving the performance and durability of the display panel.

[0093] Optionally, the material for manufacturing the substrate 302 includes polyimide (PI). As a flexible substrate material, PI can be used to manufacture flexible display screens, for example, for foldable screens or rollable screens. This material has excellent thermal stability, chemical stability, and mechanical properties, can meet the requirements of high-temperature processes, and endows the display with flexibility at the same time.

[0094] Optionally, the display panel can adopt a two-layer substrate structure, and buffer layers are respectively provided on each layer of the substrate. The structure of the two-layer substrate can provide additional support and stability, which is particularly important for large-size or high-resolution display panels. In addition, the buffer layer of each layer of the substrate can further enhance the structural stability and prevent the panel from deforming during manufacturing or use. When using flexible materials to manufacture the substrate, the two-layer substrate can provide higher mechanical strength, so as to withstand bending or folding without sacrificing the display performance.

[0095] In summary, the embodiments of the present disclosure provide a display panel. By providing a first protective layer between the substrate and the driving functional layer 306, and the first protective layer is used to collect the electric field lines from the electrical structure 3072 to the transistor, it helps to control and guide the distribution of the electric field lines, making the electric field lines concentrated in the protective layer, suppressing the electric field strength inside the substrate, thereby weakening the movement of ions in the substrate, improving the transistor performance, and further improving the afterimage problem of the OLED display end field.

[0096] Based on the same inventive concept, referring to Figure 4 As shown, the embodiments of the present application provide a method for manufacturing a display panel for manufacturing the display panel according to any one of the above embodiments, including:

[0097] S401. Provide a substrate.

[0098] In some embodiments, the substrate material includes glass, quartz, polyimide (PI), etc. The glass substrate has good light transmittance and flatness and is suitable for most display technologies; the polyimide substrate has flexibility and is suitable for flexible display technologies.

[0099] In some embodiments, the substrate can be patterned. These patterns can be conductive channels for guiding electric field lines or strengthening structures for enhancing the structural strength of the flexible substrate, etc., so as to more flexibly adapt to different application scenarios, such as wearable devices, rollable displays, etc.

[0100] S402. Form a first protective layer on the substrate.

[0101] In some embodiments, the material for making the first protective layer includes materials with a dielectric constant higher than the first dielectric constant threshold of 3.9. For example, silicon nitride (SiN x )), aluminum oxide (Al2O3), titanium dioxide (TiO2), hafnium oxide (HfO2), etc. These materials can effectively collect electric field lines and reduce the influence of the electric field on the substrate.

[0102] Optionally, processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. can be used to form the first protective layer, and the material thickness is between 1 - 5 microns.

[0103] In some embodiments, the first protective layer is patterned. Through the exposure and development processes of a photolithography mask and photoresist, the required patterns are formed. These patterns can be functional patterns such as conductive channels and insulating regions, which can more precisely control the distribution of electric field lines, reduce unnecessary electric field interference, and optimize the performance of the display panel, such as improving the conduction efficiency and enhancing the insulation effect.

[0104] In the display panel of the related art, the electric field lines are disorderly distributed, resulting in unnecessary electric field interference on the transistors. Under the condition of long-term exposure to electrical stress, the performance of the transistors will degrade, such as the drift of the threshold voltage (Vth). This degradation phenomenon will lead to a decline in the display image quality and affect the electrical performance and reliability of the device. By using materials with a dielectric constant higher than a certain threshold in the first protective layer, the electric field lines from the electrical structure to the transistors are effectively collected. This design makes the electric field lines more orderly, reduces the interference of the electric field on the transistors, and thus improves the stability and reliability of the transistors.

[0105] S403. Form a driving functional layer on the first protective layer. The driving functional layer includes at least one transistor and an electrical structure located on one side of the transistor.

[0106] In some embodiments, the transistor is fabricated using semiconductor processes such as photolithography, etching, doping, etc. The type of the transistor can be a thin film transistor, a bipolar junction transistor (BJT), a metal oxide semiconductor field effect transistor (MOSFET), etc.

[0107] Optionally, the above transistor may be a thin-film transistor. The gate and source-drain electrodes in the transistor may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0108] In some embodiments, during the formation of the driving functional layer, through precise lithography technology, components such as transistors and signal lines are arranged and connected according to a predetermined pattern, improving the reliability and stability of the display panel.

[0109] It should be noted that the first protective layer not only serves as an isolation layer between the driving functional layer and the substrate, but is also configured to collect the electric field lines from the electrical structure to the transistor, thereby reducing the influence of the electric field on the substrate and subsequent layers and improving the stability of the display panel.

[0110] Optionally, after forming the first protective layer on the substrate, the method further includes the following S404:

[0111] S404: Form a second protective layer on the first protective layer.

[0112] In some embodiments, the preparation method of the second protective layer is the same as that of the first protective layer in S402. The material of the second protective layer includes materials with a dielectric constant lower than the second dielectric constant threshold. For example, porous silicon-based materials such as porous silica and porous alumina, and the second dielectric constant threshold is less than or equal to the first dielectric constant threshold of 3.9.

[0113] It should be noted that when the electric field lines propagate from the first protective layer with a high dielectric constant to the second protective layer with a low dielectric constant, due to the change in the dielectric constant, the electric field lines will undergo a refraction phenomenon similar to that of light propagating between different media. This refraction effect helps to more concentratedly guide the electric field lines to the transistor, thereby reducing the distribution of the electric field inside the substrate and reducing the electric field intensity. In addition, the propagation path of the electric field lines in the low dielectric constant material is shorter, and the electric field energy is more concentrated, thereby further optimizing the distribution and shielding effect of the electric field and improving the performance and durability of the display panel.

[0114] In some embodiments, the second protective layer is patterned. Through the exposure and development processes of the photolithography mask and photoresist, the required patterns are formed. These patterns can be shielding layers for protecting components such as transistors and signal lines, or reinforcing ribs for enhancing the structural strength of the display panel. The patterned second protective layer can more effectively protect components such as transistors and signal lines from the influence of the external environment. The addition of patterned structures such as reinforcing ribs can enhance the structural strength of the display panel and improve its impact resistance and vibration resistance.

[0115] In summary, the embodiments of the present disclosure provide a method for manufacturing a display panel. By providing a first protective layer between the substrate and the driving functional layer, and the first protective layer is used to collect the electric field lines from the electrical structure to the transistor, which helps to control and guide the distribution of the electric field lines, so that the electric field lines are concentrated in the protective layer, suppressing the electric field strength inside the substrate, thereby weakening the movement of ions in the substrate, improving the transistor performance, and further improving the display defect problem.

[0116] It can be understood that the "patterning" mentioned herein, when the patterned material is an inorganic material or a metal, "patterning" includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping. When the patterned material is an organic material, "patterning" includes processes such as mask exposure and development. The evaporation, deposition, coating, and coating mentioned herein are all mature manufacturing processes in related technologies.

[0117] It should be noted that some embodiments of the present application have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the above embodiments and still achieve the desired results. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0118] Those of ordinary skill in the art should understand that: the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the present application (including the claims) is limited to these examples; under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of brevity.

[0119] In addition, for simplicity of explanation and discussion, and so as not to make the embodiments of the present application difficult to understand, known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Further, the devices may be shown in block diagram form in order to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that details regarding the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present application are to be implemented (i.e., these details should be entirely within the understanding of those skilled in the art). In cases where specific details (such as circuits) are set forth to describe exemplary embodiments of the present application, it will be apparent to those skilled in the art that the embodiments of the present application may be practiced without these specific details or with variations of these specific details. Accordingly, these descriptions should be considered illustrative rather than restrictive.

[0120] Although the present application has been described in connection with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures (such as dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0121] Embodiments of the present application are intended to cover all such alternatives, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the embodiments of the present application shall be included within the protection scope of the present application.

Claims

1. A display panel, characterized in that: include: substrate; A first protective layer is disposed on the substrate; A driving function layer, disposed on a side of the first protective layer away from the substrate, the driving function layer comprising at least one transistor and an electrical structure located on one side of the transistor; Wherein, the first protection layer is configured to collect electric field lines from the electrical structure to the transistor.

2. The display panel according to claim 1, characterized in that: The first protection layer is made of a material having a dielectric constant higher than a first dielectric constant threshold.

3. The display panel according to claim 1, characterized in that: The driving function layer includes a plurality of pixel circuits arranged in an array in a display area of ​​the display panel, wherein the pixel circuit includes at least one first transistor and a first electrical device located on one side of the first transistor; The first protection layer is configured to collect electric field lines from the first electrical device to the first transistor.

4. The display panel according to claim 1, characterized in that: The driving function layer includes a gate driving circuit located in a non-display area of ​​the display panel, and the gate driving circuit includes at least one second transistor and a second electrical device located on one side of the second transistor; The first protection layer is configured to collect electric field lines from the second electrical device to the second transistor.

5. The display panel according to claim 1, characterized in that: The electrical structure includes a signal line for providing an electrical signal to the display panel.

6. The display panel according to claim 5, characterized in that: The signal line includes a data line.

7. The display panel according to claim 2, characterized in that: The display panel further includes: A second protective layer, located between the first protective layer and the driving function layer; The second protective layer is made of a material having a dielectric constant lower than a second dielectric constant threshold, and the second dielectric constant threshold is less than or equal to the first dielectric constant threshold.

8. The display panel according to any one of claims 1 to 7, characterized in that: The substrate is made of a material including polyimide.

9. A method for preparing a display panel, characterized in that: The method comprises: providing a substrate; forming a first protective layer on the substrate; forming a driving function layer on the first protective layer, wherein the driving function layer includes at least one transistor and an electrical structure located on one side of the transistor; Wherein, the first protection layer is configured to collect electric field lines from the electrical structure to the transistor. 10 . The method for manufacturing a display panel according to claim 9 , wherein a material for manufacturing the first protective layer comprises a material having a dielectric constant higher than a first dielectric constant threshold.

11. The method for preparing a display panel according to claim 10, characterized in that: After forming a first protective layer on the substrate, the method further includes: A second protective layer is formed on the first protective layer, wherein the second protective layer is made of a material having a dielectric constant lower than a second dielectric constant threshold value, and the second dielectric constant threshold value is less than or equal to the first dielectric constant threshold value.

12. A display device, characterized in that: A display panel comprising any one of claims 1 to 8.

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