Method of manufacturing display device

Abstract

The invention relates to a method of manufacturing a display device. The display device includes: a substrate; a pixel circuit layer on the substrate; a light emitting layer on the pixel circuit layer and including a light emitting element; a color filter layer on the light emitting layer and including a color filter; and a lens array on the color filter layer, in which the lens array includes a plurality of lenses having a convex shape in a direction opposite to a direction toward the substrate, and the plurality of lenses include a negative photoresist composition.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0188430, filed with the Korean Intellectual Property Office on December 21, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] Aspects of some embodiments of the present disclosure relate to a display device and a method of manufacturing a display device. Background art

[0004] Recently, as consumers' interest in information display has increased, research and development of display devices have been continuously carried out. In particular, microlenses can be used to increase the resolution of each pixel included in a display device.

[0005] Recently, due to the reduction in the size of optical components and the development of application technologies, application devices using a microlens array in a conventional geometric - optics - based lens can be applied to display devices related to AR / VR.

[0006] The above information disclosed in this background art section is only for enhancing the understanding of the background art, and thus the information discussed in this background art section does not necessarily constitute prior art. Summary of the invention

[0007] Aspects of some embodiments of the present disclosure include a display device having relatively improved reliability. For example, the display device can relatively improve the reliability of microlenses by forming a fine pattern through a lithography process without a separate etching process.

[0008] Aspects of some embodiments of the present disclosure include a method of manufacturing a display device having relatively improved reliability.

[0009] According to some embodiments of the present disclosure, a display device includes: a substrate; a pixel circuit layer on the substrate; a light - emitting layer on the pixel circuit layer and including a light - emitting element; a color filter layer on the light - emitting layer and including color filters; and a lens array on the color filter layer, wherein the lens array includes a plurality of lenses having a convex shape in a direction opposite to the direction toward the substrate, and the plurality of lenses include a negative photoresist composition.

[0010] According to some embodiments, the plurality of lenses may include an optically transparent material.

[0011] According to some embodiments, the plurality of lenses may overlap the color filters respectively.

[0012] According to some embodiments, a color filter may include a first color filter, a second color filter, and a third color filter spaced apart from each other in a first direction, a plurality of lenses may include a first lens on the first color filter, a second lens on the second color filter, and a third lens on the third color filter, and each of the first lens to the third lens may have a convex shape.

[0013] According to some embodiments, the color filters may overlap with light-emitting elements, respectively.

[0014] According to some embodiments of the present disclosure, in a method of manufacturing a display device, the method includes: forming a light-emitting layer on a substrate; forming a color filter layer including a color filter on the light-emitting layer; and forming a lens array on the color filter layer, wherein the lens array includes a plurality of lenses having a convex shape in a direction opposite to the direction toward the substrate, and wherein forming the lens array includes: forming dams on the color filter layer; filling an optically transparent material between the dams; completely exposing the dams and the optically transparent material; removing the exposed dams by developing the exposed dams and the exposed optically transparent material while leaving the exposed optically transparent material; and curing the remaining optically transparent material to form a plurality of lenses.

[0015] According to some embodiments, the plurality of lenses may include a negative photoresist composition.

[0016] According to some embodiments, by using heat to cure the remaining optically transparent material, a convex shape of the plurality of lenses may be formed.

[0017] According to some embodiments, the plurality of lenses may overlap with the color filters, respectively.

[0018] According to some embodiments, forming the dams may include: applying a photoresist on the color filter layer; exposing the photoresist using a mask; applying heat to the unexposed photoresist to form the dams.

[0019] According to some embodiments, each of the dams may have an inverted conical shape.

[0020] According to some embodiments, the dams may include a positive photoresist composition.

[0021] According to some embodiments, the dams may include a liquid-repellent material.

[0022] According to some embodiments, a portion of each of the dams adjacent to the upper surface may have hydrophobicity.

[0023] According to some embodiments, the color filter may include a first color filter, a second color filter, and a third color filter spaced apart from each other in a first direction, and the dams may include a first dam overlapping with an area between the first color filter and the second color filter and a second dam overlapping with an area between the second color filter and the third color filter.

[0024] According to some embodiments, the optically transparent material may be in direct contact with the second color filter between the first dam and the second dam.

[0025] According to some embodiments, the plurality of lenses may include a first lens on the first color filter, a second lens on the second color filter, and a third lens on the third color filter, and each of the first lens to the third lens may have a convex shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A block diagram of a display device according to some embodiments of the present disclosure is shown.

[0027] Figure 2 Shown according to some embodiments Figure 1 A top plan view of a display panel of

[0028] Figure 3 Shown according to some embodiments Figure 1 A cross-sectional view of a display panel of

[0029] Figure 4 Shown according to some embodiments Figure 2 A block diagram of one of the sub-pixels of

[0030] Figure 5 Shown according to some embodiments Figure 2 A top plan view of one of the pixels of

[0031] Figure 6 Shown along Figure 5 A cross-sectional view taken along line I-I' of

[0032] Figure 7 Shown according to some embodiments Figure 2 A top plan view of one of the pixels of

[0033] Figure 8 Shown according to some embodiments Figure 2 A top plan view of one of the pixels of

[0034] Figure 9 Shown according to some embodiments of manufacturing Figure 6 A flowchart of a method of a display device of

[0035] Figure 10 Shown in Figure 9 A cross-sectional view of the display device in operation S1020 of

[0036] Figures 11 to 13 Shown for explaining Figure 9Cross-sectional view of a display device in terms of operation S1031.

[0037] Figure 14 Shows in Figure 9 Cross-sectional view of a display device in operation S1033.

[0038] Figure 15 Shows in Figure 9 Cross-sectional view of a display device in operation S1034.

[0039] Figure 16 Shows in Figure 9 Cross-sectional view of a display device in operation S1035. Detailed Description

[0040] Hereinafter, aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The following description is intended to provide only sufficient disclosure to enable an understanding of the operation of the present invention, and any other disclosure is omitted to avoid obscuring the scope of the present invention. In addition, the inventive concept can be implemented in different forms and is not limited to the embodiments set forth herein. The embodiments described herein are provided for the purpose of fully describing the technical concept of the present invention so that those skilled in the art can easily practice the present invention.

[0041] Throughout the specification, when an element is described as "connected" to another element, this includes not only "directly connected" but also "indirectly connected" with another device therebetween. The terms used herein are for the purpose of describing particular embodiments and are not intended to limit the scope of the present invention. Throughout the specification, unless explicitly stated to the contrary, the word "comprising" and variations such as "comprises" or "comprising" will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements. For the purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be construed to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XY, YZ, and XZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0042] Although terms such as first, second, etc. may be used herein to describe various constituent elements, these constituent elements should not be limited by these terms. These terms are used to distinguish one constituent element from another. Thus, without departing from the teachings of the present disclosure, the first constituent element discussed below may be referred to as the second constituent element.

[0043] For descriptive purposes, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein and are used to describe the relationship of one element or feature to another (or others) element or feature as shown in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figures is flipped, an element described as "below" or "beneath" another element or feature will then be oriented "above" the other element or feature. Thus, the term "below" can encompass both an upper and a lower orientation. In addition, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus, the spatial relative descriptors used herein should be interpreted accordingly.

[0044] Various embodiments are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments. Accordingly, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments disclosed herein should not be construed as limited to the shapes of the particular regions shown, but should include deviations in shapes, for example, due to manufacturing. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to be limiting.

[0045] Figure 1 A block diagram of a display device according to some embodiments of the present disclosure is shown.

[0046] Reference Figure 1 , the display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0047] The display panel 110 may include sub-pixels SP. The sub-pixels SP may be connected to the gate driver 120 through the first gate line GL1 to the m-th gate line GLm. The sub-pixels SP may be connected to the data driver 130 through the first data line DL1 to the n-th data line DLn.

[0048] Each of the sub-pixels SP may include at least one light-emitting element configured to generate light. Thus, the sub-pixels SP may respectively generate light of a specific color such as red, green, blue, cyan, magenta, yellow, etc. Two or more of the sub-pixels SP may constitute one pixel PXL. For example, as Figure 1 shown, three sub-pixels SP may constitute one pixel PXL.

[0049] The gate driver 120 may be connected to the sub-pixels SP arranged in the row direction through the first gate line GL1 to the m-th gate line GLm. The gate driver 120 may output gate signals to the first gate line GL1 to the m-th gate line GLm in response to a gate control signal GCS. According to some embodiments, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for synchronously outputting gate signals with the timing of applying data signals, and the like.

[0050] According to some embodiments, the first emission control lines EL1 to the m-th emission control lines ELm connected to the sub-pixels SP in the row direction may also be provided. In this case, the gate driver 120 may include an emission control driver configured to control the first emission control lines EL1 to the m-th emission control lines ELm, and the emission control driver may operate under the control of the controller 150.

[0051] The gate driver 120 may be located on one side of the display panel 110. However, the embodiments according to the present disclosure are not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically separated drivers, and the drivers may be located on one side of the display panel 110 and the other side opposite to one side of the display panel 110. As described above, according to embodiments, the gate driver 120 may be arranged around the display panel 110 in various forms.

[0052] The data driver 130 may be connected to the sub-pixels SP arranged in the column direction through the first data line DL1 to the n-th data line DLn. The data driver 130 may receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. According to some embodiments, the data control signal DCS may include a source start pulse signal, a source shift clock signal, a source output enable signal, and the like.

[0053] The data driver 130 may apply data signals having gray-scale voltages corresponding to the image data DATA to the first data line DL1 to the n-th data line DLn using voltages from the voltage generator 140. When gate signals are applied to each of the first gate line GL1 to the m-th gate line GLm, data signals corresponding to the image data DATA may be applied to the data lines DL1 to DLn. Accordingly, the corresponding sub-pixels SP may generate light corresponding to the data signals. Thus, an image may be displayed on the display panel 110.

[0054] According to some embodiments, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0055] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 may be configured to generate multiple voltages and supply the generated voltages to components of the display device 100. For example, the voltage generator 140 may be configured to generate multiple voltages by receiving an input voltage from outside the display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0056] The voltage generator 140 may generate a first power supply voltage VDD and a second power supply voltage VSS, and the generated first power supply voltage VDD and second power supply voltage VSS may be supplied to the sub-pixel SP. The first power supply voltage VDD may have a relatively high voltage level, and the second power supply voltage VSS may have a voltage level lower than the first power supply voltage VDD. According to some embodiments, the first power supply voltage VDD or the second power supply voltage VSS may be provided by an external device of the display device 100.

[0057] In addition, the voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage applied to the sub-pixel SP. For example, during a sensing operation for sensing the electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a reference voltage (e.g., a set reference voltage or a predetermined reference voltage) may be applied to the first data line DL1 to the nth data line DLn, and the voltage generator 140 may generate the reference voltage.

[0058] The controller 150 may control various operations of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL for controlling the display of the input image data IMG from outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0059] The controller 150 may convert the input image data IMG into image data DATA suitable for output to the display device 100 or the display panel 110. According to some embodiments, the controller 150 may output the image data DATA by aligning the input image data IMG to be suitable for the sub-pixels SP of the row unit.

[0060] Two or more of the components of the data driver 130, the voltage generator 140, and the controller 150 may be mounted on one integrated circuit. As Figure 1As shown, the data driver 130, the voltage generator 140, and the controller 150 may be included in the driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140, and the controller 150 may be functionally separated component elements within one driver integrated circuit DIC. According to some embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a component element separated from the driver integrated circuit DIC.

[0061] Figure 2 A top plan view of a display panel according to some embodiments is shown. Figure 1 of the display panel.

[0062] Referring to Figure 2 , Figure 1 the display panel 110 may include a display area DA and a non-display area NDA. The display panel 110 may display an image at the display area DA. The non-display area NDA may be disposed around the display area DA.

[0063] The display panel 110 may include a substrate SUB, sub-pixels SP, and pads PD.

[0064] When the display panel 110 is used as a display screen of a head-mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, or an augmented reality (AR) device, the display panel 110 may be positioned very close to the user's eyes. In this case, sub-pixels SP with relatively high integration may be required. According to some embodiments, in order to increase the integration of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP may be formed on the substrate SUB which is a silicon substrate.

[0065] The sub-pixels SP may be located in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiments according to the present disclosure are not limited thereto. For example, the sub-pixels SP may be arranged in a zigzag form along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged in a shape or arrangement. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0066] Two or more of the plurality of sub-pixels SP may constitute one pixel PXL.

[0067] The component elements for controlling the sub-pixels SP may be located in the non-display area NDA on the substrate SUB. For example, such as Figure 1The wirings connecting the first gate line GL1 to the m-th gate line GLm and the first data line DL1 to the n-th data line DLn to the sub-pixel SP may be located in the non-display area NDA.

[0068] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, and the controller 150 in may be integrated in the non-display area NDA of the display panel 110. According to some embodiments, Figure 1 The gate driver 120 of may be mounted on the display panel 110 and may be located in the non-display area NDA. According to some embodiments, the gate driver 120 may be implemented as an integrated circuit separated from the display panel 110.

[0069] The pad PD may be located in the non-display area NDA on the substrate SUB. The pad PD may be electrically connected to the sub-pixel SP through wirings. For example, the pad PD may be connected to the sub-pixel SP through the first data line DL1 to the n-th data line DLn.

[0070] The pad PD may connect the display panel 110 to other constituent elements of the display device 100 (see Figure 1 ). According to some embodiments, the voltages and signals required for the operation of the constituent elements included in the display panel 110 may be provided from Figure 1 the driver integrated circuit DIC of. For example, the first data line DL1 to the n-th data line DLn may be connected to the driver integrated circuit DIC through the pad PD. For example, the first power supply voltage VDD and the second power supply voltage VSS may be received from the driver integrated circuit DIC through the pad PD. For example, when the gate driver 120 is mounted on the display panel 110, the gate control signal GCS may be sent from the driver integrated circuit DIC to the gate driver 120 through the pad PD.

[0071] According to some embodiments, the circuit board may be electrically connected to the pad PD by using a conductive bonding member such as an anisotropic conductive film. In this case, the circuit board may be a flexible printed circuit board (FPCB) or a flexible film made of a flexible material. The driver integrated circuit DIC may be mounted on the circuit board to be electrically connected to the pad PD.

[0072] According to some embodiments, the display area DA may have various shapes. The display area DA may have a closed-loop shape including sides with straight lines and / or curves. For example, the display area DA may have a shape such as a polygon shape, a circular shape, a semi-circular shape, and an elliptical shape.

[0073] According to some embodiments, the display panel 110 may have a flat display surface. According to some embodiments, the display panel 110 may have an at least partially rounded display surface. According to some embodiments, the display panel 110 may be bendable, foldable, or rollable. In these cases, the display panel 110 and / or the substrate SUB may include materials having a flexible property.

[0074] Figure 3 A cross-sectional view of a display panel according to some embodiments is shown. Figure 1 of the display panel.

[0075] Referring to Figure 3 , the display panel 110 may include a substrate SUB, a pixel circuit layer PCL, a light-emitting layer LDL, a thin-film encapsulation layer TFE, a color filter layer CFL, and an outer coating OC.

[0076] The substrate SUB may include a semiconductor substrate. For example, the substrate SUB may include a silicon bulk wafer or an epitaxial wafer. The epitaxial wafer may include a layer of crystalline material grown on a silicon bulk substrate by an epitaxial process, i.e., an epitaxial layer. The substrate SUB is not limited to a silicon bulk wafer or an epitaxial wafer, but may be formed using various wafers such as a polished wafer, an annealed wafer, and a silicon-on-insulator (SOI) wafer.

[0077] The pixel circuit layer PCL may be located on the substrate SUB. The pixel circuit layer PCL may include circuit elements of sub-pixel circuits SPC (refer to Figure 4 ) and at least one insulating layer located between the circuit elements. The circuit elements may include a plurality of transistors and signal lines connected to the transistors. For example, the transistors may be metal-oxide-semiconductor field-effect transistors (MOSFETs), but are not limited thereto according to embodiments of the present disclosure. In addition, the transistors may have a structure in which a semiconductor layer, a gate electrode, and source / drain electrodes are sequentially stacked and insulating layers are interposed therebetween.

[0078] The substrate SUB and the pixel circuit layer PCL described above may be formed by applying semiconductor processes and equipment, but are not limited thereto according to embodiments of the present disclosure.

[0079] The light-emitting layer LDL may include light-emitting elements LD (refer to Figure 6 ) that emit light. The light-emitting elements LD may be respectively located in a first sub-pixel SP1 to a third sub-pixel SP3 (refer to Figure 6)Among them. According to some embodiments, the light-emitting elements LD may emit light of the same color respectively. In this case, due to the color filter layers CFL of different colors located on each light-emitting element LD, the first sub-pixel SP1 to the third sub-pixel SP3 may emit light of different colors. According to some embodiments, the light-emitting elements LD may emit light of different colors respectively. However, the color, type, etc. of the light-emitting elements LD of the light-emitting layer LDL are not limited.

[0080] The thin film encapsulation layer TFE may be located on the light-emitting layer LDL. The thin film encapsulation layer TFE may cover the light-emitting layer LDL to prevent or reduce the penetration of contaminants such as external air and moisture into the light-emitting elements LD.

[0081] The color filter layer CFL may be located on the thin film encapsulation layer TFE. The color filter layer CFL may include color filters that selectively transmit light of one color. That is, the color filter layer CFL may selectively transmit the light emitted from the light-emitting elements LD in the image display direction (or the front direction) of the display panel 110, but is not limited thereto.

[0082] According to some embodiments, a lens array LA (see Figure 6 ) may be located on the color filter layer CFL. The lens array LA may include a plurality of lenses, and the lenses may be arranged corresponding to each sub-pixel SP. The lens array LA may be used to increase the extraction efficiency of the light emitted from the light-emitting elements LD.

[0083] The outer coating OC may be located on the pixel PXL having the above-described constituent elements. The outer coating OC may prevent or reduce the penetration of contaminants or impurities such as moisture or air from the outside, which may damage or contaminate the color filter CF (see Figure 6 ). In addition, the outer coating OC may prevent or reduce the diffusion of the material of the color filter CF into other constituent elements. However, although it has been described by way of example that the outer coating OC is not included in each of the pixels PXL and is a separate constituent element, according to the embodiments of the present disclosure, it is not limited thereto. The outer coating OC may be a partial constituent element included in each of the pixels PXL.

[0084] Figure 4 Shows Figure 2 A block diagram of an example of one of the sub-pixels. In Figure 4 , among the sub-pixels SP of Figure 2 , as an example, the sub-pixel SPij located in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) is shown.

[0085] Refer to Figure 4 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD.

[0086] The light-emitting element LD may be connected between a first power supply voltage node VDDN and a second power supply voltage node VSSN. In this case, the first power supply voltage node VDDN may be a node for transmitting Figure 1 the first power supply voltage VDD, and the second power supply voltage node VSSN may be a node for transmitting Figure 1 the second power supply voltage VSS.

[0087] The anode electrode AE of the light-emitting element LD may be connected to the first power supply voltage node VDDN through the sub-pixel circuit SPC, and the cathode electrode CE of the light-emitting element LD may be connected to the second power supply voltage node VSSN. For example, the anode electrode AE of the light-emitting element LD may be connected to the first power supply voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0088] The sub-pixel circuit SPC may be connected to Figure 1 the i-th gate line GLi among the first gate lines GL1 to the m-th gate line GLm of Figure 1 the first light emission control lines EL1 to the m-th light emission control lines ELm of Figure 1 and the j-th data line DLj among the first data lines DL1 to the n-th data lines DLn of. The sub-pixel circuit SPC may be configured to control the light-emitting element LD according to signals received through these signal lines.

[0089] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. In an embodiment, as Figure 4 shown in, the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC may operate in response to gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. Therefore, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC may operate in response to gate signals received through the corresponding sub-gate lines.

[0090] The sub-pixel circuit SPC may operate in response to a light emission control signal received through the i-th light emission control line ELi. In an embodiment, the i-th light emission control line ELi may include one or more sub-light emission control lines. When the i-th light emission control line ELi includes two or more sub-light emission control lines, the sub-pixel circuit SPC may operate in response to light emission control signals received through the corresponding sub-light emission control lines.

[0091] The sub-pixel circuit SPC may receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC may store a voltage corresponding to the data signal in response to at least one of the gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. In response to the light emission control signal received through the i-th light emission control line ELi, the sub-pixel circuit SPC may adjust the current flowing from the first power supply voltage node VDDN to the second power supply voltage node VSSN through the light emitting element LD according to the stored voltage. Accordingly, the light emitting element LD may generate light having a brightness corresponding to the data signal.

[0092] Figure 5 A top plan view of one of the pixels according to some embodiments is shown. Figure 2 of a pixel.

[0093] Referring to Figure 5 , the first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged in a first direction DR1. In addition, the first to third sub-pixels SP1 to SP3 may include first to third color filters CF1 to CF3, respectively.

[0094] The first sub-pixel SP1 may include the first color filter CF1 and a black matrix BM surrounding the first color filter CF1. The second sub-pixel SP2 may include the second color filter CF2 and a black matrix BM surrounding the second color filter CF2. The third sub-pixel SP3 may include the third color filter CF3 and a black matrix BM surrounding the third color filter CF3. However, the black matrix BM surrounding the first to third color filters CF1 to CF3 may be omitted. For example, when the black matrix BM is omitted, the first to third color filters CF1 to CF3 may be arranged such that the first to third color filters CF1 to CF3 at least partially overlap each other. Alternatively, the first to third color filters CF1 to CF3 may be arranged in contact with each other.

[0095] The first color filter CF1 may be located in a region overlapping with a light emitting region that emits light from the first sub-pixel SP1. The first color filter CF1 may selectively transmit light of a first color. For example, the first color filter CF1 may include a first color filter material that transmits light of the first color and blocks light of the second and third colors. Accordingly, the first color filter CF1 may be understood as a light emitting region where light emitted from the first sub-pixel SP1 is output.

[0096] The second color filter CF2 may be located in a region overlapping with a light-emitting region that emits light from the second sub-pixel SP2. The second color filter CF2 may selectively transmit light of a second color. For example, the second color filter CF2 may include a color filter material of the second color that transmits light of the second color and blocks light of the first and third colors. Accordingly, the second color filter CF2 may be understood as a light-emitting region where light emitted from the second sub-pixel SP2 is output.

[0097] The third color filter CF3 may be located in a region overlapping with a light-emitting region that emits light from the third sub-pixel SP3. The third color filter CF3 may selectively transmit light of a third color. For example, the third color filter CF3 may include a color filter material of the third color that transmits light of the third color and blocks light of the first and second colors. Accordingly, the third color filter CF3 may be understood as a light-emitting region where light emitted from the third sub-pixel SP3 is output.

[0098] In addition, according to some embodiments, the first lens LS1 (see Figure 6 ) may be arranged to overlap with the first color filter CF1 of the first sub-pixel SP1. The second lens LS2 (see Figure 6 ) may be arranged to overlap with the second color filter CF2 of the second sub-pixel SP2. The third lens LS3 (see Figure 6 ) may be arranged to overlap with the third color filter CF3 of the third sub-pixel SP3.

[0099] Figure 6 A cross-sectional view taken along line I-I' of Figure 5 is shown.

[0100] Referring to Figure 6 , the first pixel PXL1 may include a substrate SUB, a pixel circuit layer PCL, a light-emitting layer LDL, a thin-film encapsulation layer TFE, an optical function layer OFL, an outer coating OC, and a cover window CW. In addition, the optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0101] The light-emitting layer LDL including the first light-emitting element LD1 to the third light-emitting element LD3 may be located on the substrate SUB. In addition, the pixel circuit layer PCL may be located between the substrate SUB and the light-emitting layer LDL.

[0102] The pixel circuit layer PCL may include various driving elements and wirings for driving the first light-emitting element LD1 to the third light-emitting element LD3. For example, the pixel circuit layer PCL may include sub-pixel circuits SPC included in each of the first sub-pixel SP1 to the third sub-pixel SP3 (refer to Figure 4The transistors and storage capacitors in []. For example, the pixel circuit layer PCL may also include wirings such as scan lines and data lines connected to the first sub-pixel SP1 to the third sub-pixel SP3 of each pixel. In addition, the pixel circuit layer PCL may include various constituent elements, and the embodiments are not limited thereto.

[0103] The light-emitting layer LDL may include a first light-emitting element LD1 located in the first sub-pixel SP1, a second light-emitting element LD2 located in the second sub-pixel SP2, and a third light-emitting element LD3 located in the third sub-pixel SP3. According to some embodiments, each of the first light-emitting element LD1 to the third light-emitting element LD3 may include a self-emitting element such as an organic light-emitting diode. For example, each of the first light-emitting element LD1 to the third light-emitting element LD3 may have a structure in which an anode electrode AE (see Figure 4 ), a hole transport layer, an organic light-emitting layer, an electron transport layer, and a cathode electrode CE (see Figure 4 ) are stacked in sequence, but are not limited thereto. For example, each of the first light-emitting element LD1 to the third light-emitting element LD3 may include an inorganic light-emitting element including an inorganic light-emitting material and a light-emitting element (quantum dot display element) that emits light by changing the wavelength of light emitted by quantum dots.

[0104] According to some embodiments, the anode electrode AE may be patterned and formed for each of the first sub-pixel SP1 to the third sub-pixel SP3. Since the anode electrode AE supplies holes to the organic light-emitting layer, the anode electrode AE may be made of a transparent conductive material having a high work function. For example, the anode electrode AE may be made of a transparent conductive material such as tin oxide (TO), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), etc., but is not limited thereto.

[0105] The organic light-emitting layer may be located between the anode electrode AE and the cathode electrode CE. The organic light-emitting layer may emit light by combining electrons and holes supplied from the anode electrode AE and the cathode electrode CE.

[0106] The cathode electrode CE may be located on the organic light-emitting layer. The cathode electrode CE may be formed as a single layer covering the entire surface of the substrate SUB. The respective cathode electrodes CE of the first sub-pixel SP1 to the third sub-pixel SP3 may be connected to each other to be integrally formed. Since the cathode electrode CE supplies electrons to the organic light-emitting layer, the cathode electrode CE may include a conductive material having a low work function. For example, the cathode electrode CE may be made of a ytterbium (Yb) alloy. In addition, the cathode electrode CE may be made of a metal material such as silver (Ag), copper (Cu), magnesium-silver (Mg-Ag) alloy, or a very thin metal material, but is not limited thereto.

[0107] The thin film encapsulation layer TFE may be located on the light emitting layer LDL. The thin film encapsulation layer TFE may be an encapsulation substrate or a multi-layer encapsulation film. When the thin film encapsulation layer TFE is in the form of an encapsulation film, it may include an inorganic film and / or an organic film. For example, the thin film encapsulation layer TFE may have a structure in which an inorganic film, an organic film, and an inorganic film are stacked in sequence. The thin film encapsulation layer TFE may prevent or reduce the penetration of contaminants such as external air and moisture into the light emitting layer LDL and the pixel circuit layer PCL.

[0108] The optical function layer OFL may be located on the thin film encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA. According to some embodiments, the optical function layer OFL may be attached to the thin film encapsulation layer TFE through an adhesive layer. For example, the optical function layer OFL may be manufactured separately to be attached to the thin film encapsulation layer TFE through an adhesive layer.

[0109] The color filter layer CFL may be located on the thin film encapsulation layer TFE. The color filter layer CFL may include a first color filter CF1 to a third color filter CF3 located in a first direction DR1. The first color filter CF1 may be located in the first sub-pixel SP1, the second color filter CF2 may be located in the second sub-pixel SP2, and the third color filter CF3 may be located in the third sub-pixel SP3.

[0110] For example, the first color filter CF1 may overlap with the first light emitting element LD1 on one surface of the thin film encapsulation layer TFE. The second color filter CF2 may overlap with the second light emitting element LD2 on one surface of the thin film encapsulation layer TFE. The third color filter CF3 may overlap with the third light emitting element LD3 on one surface of the thin film encapsulation layer TFE.

[0111] The colors of the first color filter CF1 to the third color filter CF3 may correspond to the colors of the light emitted from the first sub-pixel SP1 to the third sub-pixel SP3, respectively. For example, the first color filter CF1 is a red color filter and may include a red color filter material (e.g., a pigment or a dye). The second color filter CF2 is a green color filter and may include a green color filter material (e.g., a pigment or a dye). The third color filter CF3 is a blue color filter and may include a blue color filter material (e.g., a pigment or a dye).

[0112] The color filter layer CFL further includes a black matrix located between the color filters CF. For example, the color filter layer CFL may include a first black matrix BM1 located between the first color filter CF1 and the second color filter CF2 and a second black matrix BM2 located between the second color filter CF2 and the third color filter CF3. The first black matrix BM1 and the second black matrix BM2 may include at least one light-blocking material and / or reflective material such that they can be configured to allow the light emitted from the light-emitting layer LDL to travel in the image display direction.

[0113] For example, each of the first color filter CF1 to the third color filter CF3 may be in contact with at least one of the first black matrix BM1 and the second black matrix BM2. The first color filter CF1 may be in contact with the first black matrix BM1. The second color filter CF2 may be in contact with the first black matrix BM1 and the second black matrix BM2. The third color filter CF3 may be in contact with the second black matrix BM2. In addition, Figure 6 The situation where adjacent color filters CF are shown to be arranged spaced apart from each other with the black matrix BM therebetween is an example, but this is not limiting. For example, the black matrix BM located between adjacent color filters CF may be omitted. For example, when the black matrix BM is omitted, the first color filter CF1 to the third color filter CF3 may be arranged such that the first color filter CF1 to the third color filter CF3 at least partially overlap each other. Alternatively, the first color filter CF1 to the third color filter CF3 may be arranged in contact with each other.

[0114] The lens array LA may be located on the color filter layer CFL. The lens array LA may include lenses LS respectively overlapping the first sub-pixel SP1 to the third sub-pixel SP3. The lens array LA may collect the light emitted from the light-emitting layer LDL and passing through the color filter layer CFL. For example, the lens array LA may refract the light passing through the color filter layer CFL to direct it generally in the third direction DR3. The lens array LA may be used to increase the extraction efficiency of the light emitted from the first light-emitting element LD1 to the third light-emitting element LD3.

[0115] The lens array LA may include a first lens LS1 to a third lens LS3. The first lens LS1 to the third lens LS3 may be located on the color filter layer CFL. For example, the first lens LS1 may be located on the first color filter CF1. The second lens LS2 may be located on the second color filter CF2. The third lens LS3 may be located on the third color filter CF3.

[0116] The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index higher than that of the outer coating OC. According to some embodiments, the lens LS may include an optically transparent material. For example, the optically transparent material may include at least one of an optically clear resin (OCR) and an optically clear adhesive (OCA). However, the material of the lens LS is not limited thereto. For example, the lens LS may include an acrylic material.

[0117] The first lens LS1 to the third lens LS3 may have a convex shape in the third direction DR3. The cross-section of each of the first lens LS1 to the third lens LS3 may have a shape that thickens toward its center. The first lens LS1 to the third lens LS3 have a generally convex lens shape that can increase the light condensing effect. According to some embodiments of the present disclosure, the first lens LS1 to the third lens LS3 may be formed by a lithography process without an etching process. In this case, the first lens LS1 to the third lens LS3 may include a negative photoresist composition.

[0118] A method of manufacturing the lens array LA will be described later with reference to Figures 9 to 16 description.

[0119] The outer coating OC may be located on the first lens LS1 to the third lens LS3. The outer coating OC may cover the optical functional layer OFL, the thin film encapsulation layer TFE, the light emitting layer LDL, and / or the pixel circuit layer PCL. The outer coating OC may include various materials suitable for protecting its underlying layer from foreign substances such as dust and moisture. For example, the outer coating OC may include at least one of an inorganic insulating film and an organic insulating film. For example, the outer coating OC may include an epoxy resin, but the embodiments are not limited thereto. The outer coating OC may have a refractive index lower than that of the lens array LA.

[0120] The cover window CW may be located on the outer coating OC. The cover window CW is configured to protect its underlying layer. The cover window CW may include glass, but the embodiments are not limited thereto. For example, the cover window CW may be an encapsulation glass configured to protect the constituent elements located therebelow. According to some embodiments, the cover window CW may be omitted.

[0121] Figure 7 Shows a top plan view of one of the pixels according to some embodiments of Figure 2 the pixel.

[0122] Reference Figure 7 , the first pixel PXL1' may include a first sub-pixel SP1' to a third sub-pixel SP3'. In addition, the first sub-pixel SP1' to the third sub-pixel SP3' may include first color filters CF1' to third color filters CF3' corresponding to each sub-pixel.

[0123] The first sub-pixel SP1' may include a first color filter CF1' and a black matrix BM' surrounding the first color filter CF1'. The second sub-pixel SP2' may include a second color filter CF2' and a black matrix BM' surrounding the second color filter CF2'. The third sub-pixel SP3' may include a third color filter CF3' and a black matrix BM' surrounding the third color filter CF3'. However, the black matrix BM' surrounding the first color filter CF1' to the third color filter CF3' may be omitted. For example, when the black matrix BM' is omitted, the first color filter CF1' to the third color filter CF3' may be arranged such that the first color filter CF1' to the third color filter CF3' at least partially overlap each other. Alternatively, the first color filter CF1' to the third color filter CF3' may be arranged to be in contact with each other.

[0124] The first sub-pixel SP1' and the second sub-pixel SP2' may be arranged in a second direction DR2. The third sub-pixel SP3' may be arranged in a first direction DR1 with respect to each of the first sub-pixel SP1' and the second sub-pixel SP2'. Accordingly, the first color filter CF1' and the second color filter CF2' may be arranged in the second direction DR2. The third color filter CF3' may be arranged in the first direction DR1 with respect to each of the first color filter CF1' and the second color filter CF2'.

[0125] The second sub-pixel SP2' may have an area larger than that of the first sub-pixel SP1', and the third sub-pixel SP3' may have an area larger than that of the second sub-pixel SP2'.

[0126] Accordingly, the second color filter CF2' may have an area larger than that of the first color filter CF1', and the third color filter CF3' may have an area larger than that of the second color filter CF2'. However, the embodiments are not limited thereto. For example, the first sub-pixel SP1' and the second sub-pixel SP2' may have substantially the same area, and the third sub-pixel SP3' may have an area larger than each of the first sub-pixel SP1' and the second sub-pixel SP2'. Accordingly, the areas of the first sub-pixel SP1' to the third sub-pixel SP3' may vary in various ways according to the embodiments. Accordingly, the areas of the first color filter CF1' to the third color filter CF3' may vary in various ways according to the first sub-pixel SP1' to the third sub-pixel SP3'.

[0127] Figure 8 A top plan view of one of the pixels according to some embodiments is shown. Figure 2 of a pixel.

[0128] Refer to Figure 8, the first pixel PXL1” may include first to third sub-pixels SP1” to SP3”. The first sub-pixel SP1” may include a first color filter CF1” and a black matrix BM” around the first color filter CF1”. The second sub-pixel SP2” may include a second color filter CF2” and a black matrix BM” around the second color filter CF2”. The third sub-pixel SP3” may include a third color filter CF3” and a black matrix BM” around the third color filter CF3”. However, the black matrix BM” around the first to third color filters CF1” to CF3” may be omitted. For example, when the black matrix BM” is omitted, the first to third color filters CF1” to CF3” may be arranged such that the first to third color filters CF1” to CF3” at least partially overlap each other. Alternatively, the first to third color filters CF1” to CF3” may be arranged to contact each other.

[0129] When viewed in the third direction DR3, the first to third sub-pixels SP1” to SP3” may have a polygonal shape. For example, the shape of the first to third sub-pixels SP1” to SP3” may have a hexagonal shape as shown in Figure 8 the figure.

[0130] When viewed in the third direction DR3, the first to third color filters CF1” to CF3” may have a circular shape. However, the embodiments are not limited thereto. For example, each of the first to third color filters CF1” to CF3” may have a polygonal shape.

[0131] The first sub-pixel SP1” and the second sub-pixel SP2” may be arranged in the first direction DR1. The third sub-pixel SP3” may be arranged in a direction (or diagonal direction) that is inclined at an acute angle with respect to the first sub-pixel SP1” in a direction opposite to the second direction DR2. Thus, the first color filter CF1” and the second color filter CF2” may be arranged in the first direction DR1. The third color filter CF3” may be arranged in a direction (or diagonal direction) that is inclined at an acute angle with respect to the first color filter CF1” in a direction opposite to the second direction DR2.

[0132] Figure 5 , Figure 7 and Figure 8 the arrangement of the sub-pixels shown in the figure is only an example, and the embodiments are not limited thereto.

[0133] Each pixel may include two or more sub-pixels, the sub-pixels may be arranged differently, each of the sub-pixels may have various shapes, and each of its color filters may also have various shapes.

[0134] Figure 9 shows the manufacturing according to some embodimentsFigure 6 Flowchart of a method for a display device. Although various operations are shown in Figure 9 , according to embodiments of the present disclosure, it is not limited thereto, and according to some embodiments, without departing from the spirit and scope of the embodiments of the present disclosure, the method for manufacturing a display device may include additional operations or fewer operations, or the order of operations may vary.

[0135] Figure 10 Shows a cross-sectional view of a display device in operation S1020 of Figure 9 . Figures 11 to 13 Shows a cross-sectional view of a display device for explaining aspects of operation S1031 of Figure 9 . Figure 14 Shows a cross-sectional view of a display device in operation S1033 of Figure 9 . Figure 15 Shows a cross-sectional view of a display device in operation S1034 of Figure 9 . Figure 16 Shows a cross-sectional view of a display device in operation S1035 of Figure 9 .

[0136] First, referring to Figure 9 , a method for manufacturing a display device 100 according to embodiments of the present disclosure may include: forming a light-emitting layer (S1010); forming a color filter layer (S1020); and forming a lens array (S1030). In addition, forming the lens array (S1030) may include: forming dams (S1031); filling with an optically transparent material (S1032); exposing the entire surface (S1033); developing the optically transparent material (S1034); and curing using heat (S1035).

[0137] More specifically, referring to Figure 9 and Figure 10 , in S1010, a light-emitting layer LDL including a first light-emitting element LD1 to a third light-emitting element LD3 may be formed on a substrate SUB. First, a pixel circuit layer PCL may be formed on the substrate SUB, and then a light-emitting layer LDL may be formed on the pixel circuit layer PCL.

[0138] The first light-emitting element LD1 to the third light-emitting element LD3 may be formed at positions corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. In an embodiment, the first light-emitting element LD1 to the third light-emitting element LD3 may include an organic light-emitting diode, an inorganic light-emitting element, and / or a light-emitting element (quantum dot display element) that emits light by changing the wavelength of light emitted using quantum dots. However, the type of the first light-emitting element LD1 to the third light-emitting element LD3 is not limited thereto.

[0139] In addition, a thin film encapsulation layer TFE may be formed on the light emitting layer LDL. However, if necessary, the thin film encapsulation layer TFE may be omitted.

[0140] In S1020, a color filter layer CFL including a first color filter CF1 to a third color filter CF3 may be formed on the thin film encapsulation layer TFE. The first color filter CF1 to the third color filter CF3 may be formed as a single layer, and the first color filter CF1 to the third color filter CF3 may be spaced apart from each other in a first direction DR1.

[0141] According to some embodiments, a first black matrix BM1 may be located between the first color filter CF1 and the second color filter CF2, and a second black matrix BM2 may be located between the second color filter CF2 and the third color filter CF3. Carbon, titanium oxide, and iron oxide may be used alone or in combination to form the first black matrix BM1 and the second black matrix BM2. However, the material that blocks light is not limited thereto. According to some embodiments, the first black matrix BM1 and the second black matrix BM2 may be formed by forming a material on the light emitting layer LDL and then patterning the material using a photolithography process. However, the first black matrix BM1 and the second black matrix BM2 located between the first color filter CF1 to the third color filter CF3 may be omitted.

[0142] The first color filter CF1 to the third color filter CF3 may be formed using an inkjet method, various coating methods (including a slit coating method), a photolithography method, etc. In the case of a coating or inkjet method, a solution including each pigment and a solvent may be formed in the light emitting region of each of the first light emitting element LD1 to the third light emitting element LD3. In addition, the first color filter CF1 to the third color filter CF3 may be formed by removing the solvent through a process of curing the corresponding solution. In the case of a photolithography method, a photosensitive solution including each pigment and a solution may be formed in the light emitting region of each of the first light emitting element LD1 to the third light emitting element LD3. In addition, the first color filter CF1 to the third color filter CF3 may be formed by partially curing the solution to remove the solvent and then performing an exposure and development process.

[0143] In S1030, a lens array LA may be formed. S1030 may include S1031 to S1035.

[0144] In S1031, a bank BNK (see Figure 13 ) may be formed. First, referring to Figure 11 , a material for forming the bank BNK (see Figure 13) The photoresist BNK_PR. In this case, the height H of the applied photoresist BNK_PR can be from about 1 μm to about 10 μm. However, it is not limited thereto and can be about 100 μm or less according to the design conditions of the pixel PXL.

[0145] According to some embodiments, the photoresist BNK_PR applied to form the bank BNK may include a positive photoresist composition. The positive photoresist composition may be a photoresist in which the unexposed portion is cured. The positive photoresist composition may have a physical property such that the solubility in the developing solution increases according to the exposure amount. That is, by developing the positive photoresist composition, a pattern from which the exposed area is removed can be obtained.

[0146] Reference Figure 12 , the photoresist BNK_PR applied on the color filter layer CFL can be exposed through the mask MSK. The opening M_OP of the mask MSK can be located in the area where the bank BNK is not formed, that is, in the area where the lens LS is formed. In addition, by irradiating ultraviolet light UV through the opening M_OP of the mask MSK, the applied photoresist BNK_PR can be exposed. For example, the mask MSK may have a first opening M_OP1 overlapping with the first color filter CF1, a second opening M_OP2 overlapping with the second color filter CF2, and a third opening M_OP3 overlapping with the third color filter CF3. By irradiating ultraviolet light UV through the first opening M_OP1 to the third opening M_OP3 of the mask MSK, only the photoresist BNK_PR applied on the first color filter CF1 to the third color filter CF3 can be exposed.

[0147] Reference Figure 13, the bank BNK can be formed by exposing the photoresist BNK_PR exposed on the color filter layer CFL. Since the photoresist BNK_PR includes a positive photoresist composition, the photoresist BNK_PR in the region overlapping with the opening M_OP of the mask MSK can be removed by exposure. In addition, the bank BNK can be formed by applying heat to the photoresist BNK_PR in the region not overlapping with the opening M_OP of the mask MSK. For example, the photoresist BNK_PR on the first color filter CF1 to the third color filter CF3 overlapping with the first opening M_OP1 to the third opening M_OP3 of the mask MSK can be removed. On the other hand, the photoresist BNK_PR on the first black matrix BM1 and the second black matrix BM2 not overlapping with the first opening M_OP1 to the third opening M_OP3 of the mask MSK can be retained. In addition, the bank BNK can be formed from the photoresist BNK_PR on the first black matrix BM1 and the second black matrix BM2. The bank BNK formed as described above can include a first bank BNK1 overlapping with the region between the first color filter CF1 and the second color filter CF2 and a second bank BNK2 overlapping with the region between the second color filter CF2 and the third color filter CF3.

[0148] The bank BNK can have an inverted conical shape. Each of the first bank BNK1 and the second bank BNK2 can have a cross-sectional shape in which the cross-sectional area narrows from the upper surface S1 to the lower surface S2. According to some embodiments, when exposing the photoresist BNK_PR, the inverted conical shape of each of the first bank BNK1 and the second bank BNK2 can be formed by adjusting the exposure energy, exposure angle, etc.

[0149] An opening OP can be formed between the banks BNK, so that the upper surface S3 of each color filter CF can be exposed.

[0150] Reference Figure 9 and Figure 14 , in S1032, the opening OP between the banks BNK can be filled with the optically transparent material OTM. The optically transparent material OTM can be filled in the opening OP between the banks BNK by an inkjet process or a filling process. For example, the optically transparent material OTM can be filled between the first bank BNK1 and the second bank BNK2 so that it can directly contact the second color filter CF2.

[0151] According to some embodiments of the present disclosure, the filled optically transparent material OTM for forming the lens LS can include a negative photoresist composition. The negative photoresist composition can be a photoresist in which the irradiated part is cured. The negative photoresist composition can have a physical property such that the solubility in the developing solution decreases according to the exposure amount. That is, by developing the negative photoresist composition, a pattern corresponding to the exposed area can be obtained.

[0152] According to some embodiments, the bank BNK may include a liquid-repellent material. Since the contact angle with the optically transparent material OTM is relatively large due to the liquid-repellent material, the bank BNK may push the optically transparent material OTM. The liquid-repellent material constituting the bank BNK may include an organic polymer material. For example, the liquid-repellent material may include a polymer material in which fluorine groups (F) are mixed with an organic material such as polyimide. Accordingly, the bank BNK may have hydrophobicity as the liquid-repellent material. According to some embodiments, the bank BNK may have hydrophobicity on their respective upper surfaces S1. Since the bank BNK has hydrophobicity, the optically transparent material OTM may be stably filled into the opening OP between the bank BNKs and may not remain on the upper surface S1 of each of the bank BNKs. In addition, due to the pinning phenomenon, the optically transparent material OTM may not overflow from the opening OP between the bank BNKs.

[0153] In S1033, the bank BNK and the optically transparent material OTM may be fully exposed without a separate mask. By irradiating ultraviolet light UV in a direction opposite to the third direction DR3, the respective upper surfaces of the bank BNK and the optically transparent material OTM may be fully exposed.

[0154] Reference Figure 9 and Figure 15 Referring to and, in S1034, by developing the exposed bank BNK and the exposed optically transparent material OTM, the exposed bank BNK may be removed and the exposed optically transparent material OTM may be left. The lens LS may be formed of the optically transparent material OTM remaining on the color filter CF. According to some embodiments, since the first bank BNK1 and the second bank BNK2 include a positive photoresist composition, the solubility in the developer may increase due to the exposure in S1033. The first bank BNK1 and the second bank BNK2 may be removed by development. On the other hand, since the optically transparent material OTM overlapping each of the first color filter CF1 to the third color filter CF3 includes a negative photoresist composition, the solubility in the developer may decrease due to the exposure in S1033. The optically transparent material OTM overlapping each of the first color filter CF1 to the third color filter CF3 may form the first lens LS1 to the third lens LS3.

[0155] In this way, by using a positive photoresist composition and a negative photoresist composition together, the pattern of the lens array LA may be formed with only one exposure. That is, the bank BNK including the positive photoresist composition may be removed by exposure, and the pattern of the lens LS including the negative photoresist composition may be left by exposure.

[0156] According to some embodiments, the first lens LS1 to the third lens LS3 may be spaced apart from each other in the first direction DR1. The first lens LS1 may be located on the color filter layer CFL to overlap with the first color filter CF1. The second lens LS2 may be located on the color filter layer CFL to overlap with the second color filter CF2. The third lens LS3 may be located on the color filter layer CFL to overlap with the third color filter CF3.

[0157] Reference Figure 15 , the lens LS may have a tapered shape. Each of the lenses LS may have a trapezoidal cross-sectional shape. According to some embodiments, the lens LS may have a shape complementary to the shape of the bank BNK. For example, when the bank BNK has an inverted tapered shape, the lens LS may have a tapered shape.

[0158] Reference Figure 9 and Figure 16 , in S1035, the first lens LS1 to the third lens LS3 may be cured. After exposure in S1033 and development in S1034, heat may be used to cure the first lens LS1 to the third lens LS3. By heat curing, the positive photoresist composition constituting the first lens LS1 to the third lens LS3 may flow partially. Accordingly, the first lens LS1 to the third lens LS3 may have a slightly curved convex shape. In particular, when heat curing is performed at a low temperature of about 100 °C or lower, for example, fine patterning of the lens array LA can be performed.

[0159] Thereafter, an outer coating OC (see Figure 6 ) may be formed on the first lens LS1 to the third lens LS3. The outer coating OC may provide a planarized upper surface on the first lens LS1 to the third lens LS3.

[0160] In a display device and a method of manufacturing a display device according to an embodiment of the present disclosure, by forming a fine pattern of a lens array by photolithography without a separate etching process, defects such as increased roughness, under-etching, and over-etching that occur in the etching process can be eliminated. In addition, a mask pattern process for etching can be omitted, thereby reducing the manufacturing cost due to process reduction.

[0161] According to some embodiments of the present disclosure, there are provided a display device and a method of manufacturing a display device having relatively improved reliability.

[0162] Features of embodiments of the present disclosure are not limited to the above-described content, and more various effects are included in this specification.

[0163] Although some embodiments and implementation aspects have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the embodiments according to the present disclosure are not limited to the embodiments specifically described herein, but rather to the broader scope of the presented claims and various obvious modifications and equivalent arrangements.

Claims

1. A method for manufacturing a display device, comprising: forming a light-emitting layer on a substrate; forming a color filter layer including a color filter on the light emitting layer; as well as forming a lens array on the color filter layer, wherein the lens array includes a plurality of lenses having a convex shape in a direction opposite to a direction toward the substrate, Wherein, forming the lens array comprises: forming a bank on the color filter layer; filling optically transparent material between the banks; completely exposing the bank and the optically transparent material; removing the exposed banks by developing the exposed banks and the exposed optically transparent material while leaving the exposed optically transparent material; and curing the remaining optically transparent material to form the plurality of lenses, Wherein, the plurality of lenses comprises a negative photoresist composition.

2. The method for manufacturing the display device according to claim 1, wherein: The convex shape of the plurality of lenses is formed by curing the remaining optically transparent material using heat.

3. The method for manufacturing the display device according to claim 1, wherein: The plurality of lenses overlap the color filters, respectively.

4. The method for manufacturing the display device according to claim 1, wherein: Forming the embankment includes: applying a photoresist on the color filter layer; exposing the photoresist using a mask; and Heat is applied to the unexposed photoresist to form the bank.

5. The method for manufacturing the display device according to claim 1, wherein: Each of the banks has an inverted tapered shape.

6. The method for manufacturing the display device according to claim 1, wherein: The bank includes a positive photoresist composition.

7. The method for manufacturing the display device according to claim 1, wherein: The bank comprises a liquid repellent material, and Wherein, a portion of each of the banks adjacent to the upper surface is hydrophobic.

8. The method for manufacturing the display device according to claim 1, wherein: The color filter includes a first color filter, a second color filter, and a third color filter spaced apart from each other in a first direction, and The bank includes a first bank overlapping a region between the first color filter and the second color filter and a second bank overlapping a region between the second color filter and the third color filter.

9. The method for manufacturing the display device according to claim 8, wherein: The optically transparent material is in direct contact with the second color filter between the first bank and the second bank.

10. The method for manufacturing the display device according to claim 8, wherein: The plurality of lenses include a first lens on the first color filter, a second lens on the second color filter, and a third lens on the third color filter, and Each of the first to third lenses has a convex shape.

Images