Display substrate, display device and electronic device

Abstract

A display substrate, a display device and an electronic device, the display substrate comprises a substrate and a plurality of sub-pixels arranged on the substrate, at least one sub-pixel comprises a pixel driving circuit, and at least one pixel driving circuit comprises a plurality of first-type transistors (M1) and a plurality of second-type transistors (M2), the orthographic projection of the at least one first-type transistor (M1) on the substrate is at least partially overlapped with the orthographic projection of the at least one second-type transistor (M2) on the substrate.

Description

Display substrate, display device, electronic device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate, a display device, and an electronic device. Background Art

[0002] Organic Light Emitting Diodes (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, an embodiment of the present disclosure provides a display substrate comprising a substrate and a plurality of sub-pixels arranged on the substrate, wherein at least one sub-pixel comprises a pixel driving circuit, and at least one pixel driving circuit comprises a plurality of first-type transistors and a plurality of second-type transistors, and an orthographic projection of at least one first-type transistor on the substrate at least partially overlaps with an orthographic projection of at least one second-type transistor on the substrate.

[0006] In an exemplary embodiment, the pixel driving circuits of the plurality of sub-pixels form a plurality of rows, a light-transmitting area is provided between two adjacent rows of pixel driving circuits, and the light-transmitting area has no overlapping area with the orthographic projection of the pixel driving circuit on the substrate.

[0007] In an exemplary embodiment, the display substrate further includes a shielding layer, which is located between the base and the pixel driving circuit in a direction perpendicular to the plane of the display substrate. The shielding layer is provided with a light-transmitting opening, and the boundary lines of the light-transmitting opening are smoothly connected.

[0008] In an exemplary embodiment, the display substrate further includes a black matrix layer. In a direction perpendicular to the plane of the display substrate, the black matrix layer is located on a side of the pixel driving circuit away from the substrate. The black matrix layer is provided with a light-transmitting opening, and the boundary lines of the light-transmitting opening are smoothly connected.

[0009] In an exemplary embodiment, an orthographic projection of the light-transmitting opening on the substrate overlaps with an orthographic projection of the light-transmitting region on the substrate.

[0010] In an exemplary embodiment, the light-transmitting opening is in the shape of an ellipse or a polygon, and the corners of the polygon are configured as rounded structures.

[0011] In an exemplary embodiment, the display substrate further includes an anode conductive layer, which is located on a side of the pixel driving circuit away from the substrate. The anode conductive layer includes a plurality of anodes, and each sub-pixel includes at least one anode. The anode and the pixel driving circuit in the same sub-pixel are electrically connected to each other, and there is no overlapping area between the anode and the orthographic projection of the light-transmitting area on the substrate.

[0012] In an exemplary embodiment, the plurality of sub-pixels include a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels, the anode area of ​​the first sub-pixels and the anode area of ​​the second sub-pixels are both larger than the anode area of ​​the third sub-pixels, and the orthographic projections of the anodes of the first sub-pixels and the second sub-pixels on the substrate are within the range of the orthographic projection of the pixel driving circuit on the substrate.

[0013] In an exemplary embodiment, on a plane parallel to the display substrate, the anodes of the plurality of third sub-pixels are arranged in an array, and in the row direction, the light-transmitting area is located between the anodes of two adjacent columns of third sub-pixels; in the column direction, the anodes of the first sub-pixels and the anodes of the second sub-pixels are alternately arranged, and the light-transmitting area is located between the anodes of the adjacent first sub-pixels and the anodes of the second sub-pixels.

[0014] In an exemplary embodiment, the first type of transistor includes at least a third transistor serving as a driving transistor, the second type of transistor includes at least a first transistor serving as a first initialization transistor, the second electrode of the first transistor is electrically connected to the second electrode of the third transistor, and the orthographic projection of the first transistor on the substrate at least partially overlaps with the orthographic projection of the third transistor on the substrate.

[0015] In an exemplary embodiment, the orthographic projections of the control electrode and the active layer of the third transistor on the substrate at least partially overlap with the orthographic projections of the control electrode and the active layer of the first transistor on the substrate, respectively.

[0016] In an exemplary embodiment, the first type of transistor further includes a sixth transistor serving as a light-emitting transistor, the second type of transistor further includes a seventh transistor serving as a second initialization transistor, the first electrode of the sixth transistor and the second electrode of the seventh transistor are both electrically connected to the second electrode of the third transistor; and the orthographic projection of the sixth transistor on the substrate at least partially overlaps with the orthographic projection of the seventh transistor on the substrate.

[0017] In an exemplary embodiment, the orthographic projections of the control electrode and the active layer of the sixth transistor on the substrate at least partially overlap with the orthographic projections of the control electrode and the active layer of the seventh transistor on the substrate, respectively.

[0018] In an exemplary embodiment, the first type of transistors further includes a fourth transistor serving as a data writing transistor and a fifth transistor serving as a light emitting transistor, the second type of transistors further includes a second transistor serving as a compensation transistor and an eighth transistor serving as a third initialization transistor, the second electrode of the fourth transistor, the second electrode of the fifth transistor, and the second electrode of the eighth transistor are all electrically connected to the first electrode of the third transistor, the first electrode of the second transistor is electrically connected to the control electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the second electrode of the third transistor;

[0019] On a plane parallel to the display substrate, in a first direction, the fourth transistor and the fifth transistor are located on one side of the first transistor and the third transistor, the second transistor, the sixth transistor and the seventh transistor are located on the other side of the third transistor and the first transistor, and the eighth transistor is located between the fifth transistor and the seventh transistor; in a second direction, the fourth transistor and the second transistor are located on one side of the third transistor, and the fifth to eighth transistors are located on the other side of the third transistor, and the first direction intersects with the second direction.

[0020] In an exemplary embodiment, an orthographic projection of the active layer of the second transistor on the substrate at least partially overlaps with an orthographic projection of the active layer of the sixth transistor on the substrate.

[0021] In an exemplary embodiment, the display substrate further includes a driving circuit layer, the driving circuit layer including pixel driving circuits for the plurality of sub-pixels, the pixel driving circuit further including a storage capacitor, and in a direction perpendicular to a plane of the display substrate, the driving circuit layer includes a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a second semiconductor layer, and a fourth conductive layer sequentially disposed on the substrate;

[0022] The first semiconductor layer includes at least: the active layer of the first type of transistor; the first conductive layer includes at least: the control electrode of the first type of transistor and the first plate of the storage capacitor; the second conductive layer includes at least: the second plate of the storage capacitor; the third conductive layer includes at least: the shielding layer of the second type of transistor; the second semiconductor layer includes at least: the active layer of the second type of transistor; the fourth conductive layer includes at least: the control electrode of the second type of transistor.

[0023] In an exemplary embodiment, the driving circuit layer further includes a fifth conductive layer, the fifth conductive layer being located on a side of the fourth conductive layer away from the second semiconductor layer, the fifth conductive layer at least including: a first electrode and a second electrode of the first type transistor and the second type transistor;

[0024] The orthographic projections of the first electrode plate and the second electrode plate on the substrate at least partially overlap with the orthographic projection of the third transistor on the substrate. On a plane parallel to the display substrate, in the second direction, a connection structure is provided on the side of the first electrode plate close to the second transistor. The orthographic projection of the connection structure on the substrate does not at least partially overlap with the orthographic projections of the storage capacitor and the third transistor on the substrate. The first electrode of the second transistor is electrically connected to the connection structure through a via, and there is no overlapping area between the orthographic projection of the second transistor on the substrate and the orthographic projection of the storage capacitor on the substrate.

[0025] In an exemplary embodiment, the pixel driving circuits of the plurality of sub-pixels form multiple columns, and the driving circuit layer further includes a sixth conductive layer and a seventh conductive layer. In a direction perpendicular to the plane of the display substrate, the sixth conductive layer is located on a side of the fifth conductive layer away from the fourth conductive layer, and the seventh conductive layer is located on a side of the sixth conductive layer away from the fifth conductive layer. The sixth conductive layer at least includes: a data signal line electrically connected to a first electrode of a fourth transistor in one column of the pixel driving circuits; the seventh conductive layer at least includes: a first power line electrically connected to a first electrode of a fifth transistor in two adjacent columns of the pixel driving circuits and a second plate of a storage capacitor.

[0026] On a plane parallel to the display substrate, the data signal lines and the first power lines extend along the second direction and are spaced apart along the first direction. The data signal lines of two adjacent columns of pixel driving circuits are located on either side of the first power lines electrically connected to the two adjacent columns of pixel driving circuits. The two adjacent columns of pixel driving circuits are symmetrically arranged along a second center line, which is the center line between the two adjacent columns of pixel driving circuits extending along the second direction. In an exemplary embodiment, the sixth conductive layer further includes a shielding electrode, and the seventh conductive layer further includes a first power connection line and a second power connection line.

[0027] On a plane parallel to the display substrate, the first power connection line extends along the second direction, the second power connection line extends along the first direction, and each second power connection line is connected to at least part of the first power connection line; in the first direction, the shielding electrode and the first power connection line are located between two adjacent data signal lines; in the second direction, the first power connection line is located between two adjacent second power connection lines, and both ends of the first power connection line are respectively connected to the two adjacent second power connection lines;

[0028] The orthographic projection of the shielding electrode on the substrate covers the orthographic projection of the connection structure on the substrate; the first power connection line at least partially overlaps with the orthographic projection of the shielding electrode on the substrate, and the first power connection line is electrically connected to the shielding electrode through a via.

[0029] In an exemplary embodiment, at least a portion of the structure of the first type of transistor and at least a portion of the structure of the second type of transistor are located in different conductive layers, at least a portion of the structure of the first type of transistor and at least a portion of the structure of the second type of transistor are located in different conductive layers, the orthographic projections of at least a portion of the structure of at least one of the first type of transistor and at least a portion of the structure of the second type of transistor on the substrate at least partially overlap, and the partial structures include one or more of the control electrode and the active layer of the transistor.

[0030] In a second aspect, an embodiment of the present disclosure further provides a display substrate, comprising a base and a plurality of sub-pixels arranged on the base, wherein a light-transmitting area is provided between at least two adjacent sub-pixels, and boundary lines of the light-transmitting area are smoothly connected.

[0031] In an exemplary embodiment, the subpixels include pixel driver circuits, the pixel driver circuits for the plurality of subpixels form multiple rows, and the light-transmitting region is located between two adjacent rows of pixel driver circuits. In an exemplary embodiment, the display substrate further includes a shielding layer, located perpendicular to the plane of the display substrate between the base and the pixel driver circuits, the shielding layer having light-transmitting openings, the boundaries of which are smoothly connected.

[0032] In an exemplary embodiment, the display substrate further includes a black matrix layer. In a direction perpendicular to the plane of the display substrate, the black matrix layer is located on a side of the pixel driving circuit away from the substrate. The black matrix layer is provided with a light-transmitting opening, and the boundary lines of the light-transmitting opening are smoothly connected.

[0033] In an exemplary embodiment, an orthographic projection of the light-transmitting opening on the substrate overlaps with an orthographic projection of the light-transmitting region on the substrate.

[0034] In an exemplary embodiment, the light-transmitting opening is in the shape of an ellipse or a polygon, and the corners of the polygon are configured as rounded structures.

[0035] In an exemplary embodiment, the display substrate further includes an anode conductive layer and a driving circuit layer, the pixel driving circuit is arranged in the driving circuit layer, the anode conductive layer is located on a side of the driving circuit layer away from the substrate, the anode conductive layer includes a plurality of anodes, each sub-pixel includes at least one anode, the anode and the pixel driving circuit in the same sub-pixel are electrically connected to each other, and there is no overlapping area between the anode and the orthographic projection of the light-transmitting area on the substrate.

[0036] In an exemplary embodiment, the plurality of sub-pixels include a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels, the anode area of ​​the first sub-pixels and the anode area of ​​the second sub-pixels are both larger than the anode area of ​​the third sub-pixels, and the orthographic projections of the anodes of the first sub-pixels and the second sub-pixels on the substrate are within the range of the orthographic projection of the pixel driving circuit on the substrate.

[0037] In an exemplary embodiment, on a plane parallel to the display substrate, the anodes of the plurality of third sub-pixels are arranged in an array, and in the row direction, the light-transmitting area is located between the anodes of two adjacent columns of third sub-pixels; in the column direction, the anodes of the first sub-pixels and the anodes of the second sub-pixels are alternately arranged, and the light-transmitting area is located between the anodes of the adjacent first sub-pixels and the anodes of the second sub-pixels.

[0038] In a third aspect, embodiments of the present disclosure further provide a display substrate, comprising a substrate and a plurality of pixels, a plurality of data signal lines, and a plurality of first power lines disposed on the substrate, wherein the plurality of data signal lines and the plurality of first power lines extend along a second direction and are arranged at intervals along the first direction on a plane parallel to the display substrate, and the first direction intersects the second direction;

[0039] At least some of the sub-pixels include pixel driving circuits, and the pixel driving circuits of multiple sub-pixels form multiple columns. Each data signal line is electrically connected to at least some of the pixel driving circuits in one column of pixel driving circuits, and each first power line is electrically connected to at least some of the pixel driving circuits in at least one column of pixel driving circuits. In the first direction, two adjacent data signal lines are located on both sides of the first power line.

[0040] In an exemplary embodiment, each first power line is electrically connected to two adjacent columns of pixel driving circuits, and the two adjacent columns of pixel driving circuits are symmetrically arranged along a second center line, which is a center line of the two adjacent columns of pixel driving circuits extending along the second direction.

[0041] In an exemplary embodiment, the pixel driving circuit further includes a shielding electrode. In the first direction, the shielding electrode is disposed between two adjacent data signal lines. In the same column of pixel driving circuits, the data signal line is located between the shielding electrode and the first power line.

[0042] In an exemplary embodiment, the display substrate further includes a first power connection line and a second power connection line, wherein, on a plane parallel to the display substrate, the first power connection line extends along the second direction, the second power connection line extends along the first direction, and each second power connection line is connected to at least part of the first power line;

[0043] In the first direction, the first power connection line is located between two adjacent data signal lines; in the second direction, the first power connection line is located between two adjacent second power connection lines, and both ends of the first power connection line are respectively connected to the two adjacent second power connection lines;

[0044] The shielding electrode and the data signal line are located in the same conductive layer, the first power line, the first power connection line and the second power connection line are located in the same conductive layer, and the data signal line and the first power line are located in different conductive layers; the first power connection line and the orthographic projection of the shielding electrode on the substrate at least partially overlap, and the first power line and the shielding electrode are electrically connected through a via.

[0045] In a fourth aspect, an embodiment of the present disclosure further provides a display device, comprising the display substrate described in any of the above embodiments.

[0046] In a fifth aspect, an embodiment of the present disclosure further provides an electronic device, comprising a sensor and the display device described in any of the above embodiments, wherein the display device comprises a display substrate, the sensor is located on a side of a non-display surface of the display substrate, the display substrate comprises a first display area, and the orthographic projection of the sensor on the display substrate at least partially overlaps with the first display area of ​​the display substrate.

[0047] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0049] FIG1 is a schematic structural diagram of a display substrate;

[0050] FIG2 is an equivalent circuit diagram of a pixel driving circuit;

[0051] FIG3 is a timing diagram showing the operation of the pixel driving circuit provided in FIG2 ;

[0052] FIG4 is a schematic diagram showing a planar structure of a display substrate provided by an exemplary embodiment of the present disclosure;

[0053] FIG5 a is a schematic diagram showing a planar structure of a display substrate provided by an exemplary embodiment of the present disclosure;

[0054] FIG5 b is a schematic diagram showing a planar structure of a display substrate provided by an exemplary embodiment of the present disclosure;

[0055] FIG5 c is a schematic diagram showing a planar structure of a display substrate provided by an exemplary embodiment of the present disclosure;

[0056] FIG6 a is a schematic diagram showing a planar structure of a shielding layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0057] FIG6 b is a schematic diagram showing a planar structure of a shielding layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0058] FIG6 c is a schematic diagram showing a planar structure of a black matrix layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0059] FIG6 d is a schematic diagram showing a planar structure of a black matrix layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0060] FIG6e is a schematic diagram showing a planar structure of a display substrate provided by an exemplary embodiment of the present disclosure;

[0061] FIG6 f is a schematic diagram showing a planar structure of a display substrate provided by an exemplary embodiment of the present disclosure;

[0062] FIG6g is a schematic diagram showing a planar structure of a display substrate provided by an exemplary embodiment of the present disclosure;

[0063] FIG6h is a schematic diagram showing a planar structure of a display substrate provided by an exemplary embodiment of the present disclosure;

[0064] FIG7 is an equivalent circuit diagram of a pixel driving circuit provided by an exemplary embodiment of the present disclosure;

[0065] FIG8 is a timing diagram showing an operation of the pixel driving circuit provided in FIG7 ;

[0066] FIG9 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a shielding layer is formed;

[0067] FIG10 a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a first semiconductor layer is formed;

[0068] FIG10 b is a schematic diagram showing a planar structure of the first semiconductor layer in FIG10 a ;

[0069] FIG11a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a first conductive layer is formed;

[0070] FIG11b is a schematic diagram showing the planar structure of the first conductive layer in FIG11a;

[0071] FIG12a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a second conductive layer is formed;

[0072] FIG12b is a schematic diagram showing the planar structure of the second conductive layer in FIG12a;

[0073] FIG13a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a third conductive layer is formed;

[0074] FIG13b is a schematic diagram showing the planar structure of the third conductive layer in FIG12a;

[0075] FIG14a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a second semiconductor layer is formed;

[0076] FIG14b is a schematic diagram showing a planar structure of the second semiconductor conductive layer in FIG14a;

[0077] FIG15a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fourth conductive layer is formed;

[0078] FIG15b is a schematic diagram showing a planar structure of the fourth conductive layer in FIG15a;

[0079] FIG16 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a seventh insulating layer is formed;

[0080] FIG17a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fifth conductive layer is formed;

[0081] FIG17b is a schematic diagram showing the planar structure of the fifth conductive layer in FIG17a;

[0082] FIG18 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a first planarization layer is formed;

[0083] FIG19a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a sixth conductive layer is formed;

[0084] FIG19b is a schematic diagram showing the planar structure of the sixth conductive layer in FIG19a;

[0085] FIG20 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a second planarization layer is formed;

[0086] FIG21 a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a seventh conductive layer is formed;

[0087] FIG21 b is a schematic diagram showing the planar structure of the seventh conductive layer in FIG21 a ;

[0088] FIG22 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a third planarization layer is formed;

[0089] FIG23a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after an anode layer is formed;

[0090] FIG23 b is a schematic diagram showing the planar structure of the anode layer in FIG23 a ;

[0091] FIG24 a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a pixel definition layer is formed;

[0092] FIG24 b is a schematic diagram showing the planar structure of the pixel definition layer in FIG24 a ;

[0093] FIG25 is a schematic diagram of a display device provided by an exemplary embodiment of the present disclosure;

[0094] FIG. 26 is a schematic diagram of an electronic device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0095] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a number of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0096] The scales of the figures in this disclosure are intended to serve as a reference for actual processes, but are not intended to be limiting. For example, the thickness and spacing of each film layer, and the width and spacing of each signal line, can be adjusted based on actual conditions. The figures described in this disclosure are merely schematic diagrams of the structures, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0097] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0098] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0099] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0100] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0101] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, "source electrode" and "drain electrode" can be interchangeable, and "source terminal" and "drain terminal" can be interchangeable. In the disclosed embodiments, the gate electrode can be referred to as the control electrode.

[0102] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0103] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0104] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0105] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0106] The term "about" in the embodiments of the present disclosure does not strictly define the limits and allows for numerical values ​​within the range of process and measurement errors.

[0107] Figure 1 is a schematic diagram of a planar structure of a display substrate. In some examples, as shown in Figure 1, the display substrate may include: a display area AA and a peripheral area BB located outside the display area AA. The display area AA of the display substrate may include at least: a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the second display area A2 may surround the first display area A1. The peripheral area BB may surround the second display area A2. However, this embodiment is not limited to this.

[0108] In some examples, as shown in Figure 1, the first display area A1 may be a light-transmitting display area, and may also be referred to as an under-screen camera (FDC, Full Display With Camera) area. The second display area A2 may be referred to as a normal display area. For example, the orthographic projection of a sensor (such as a camera or other hardware) on the display substrate may be located within the first display area A1 of the display substrate. In some examples, as shown in Figure 1, the first display area A1 may be circular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 may be rectangular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the inscribed circle of the first display area A1.

[0109] In some examples, as shown in FIG1 , the first display area A1 can be located at the top center of the display area AA. The second display area A2 can surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 can be located at other locations, such as the upper left corner, lower left corner, lower right corner, or upper right corner of the display area AA. For example, the second display area A2 can surround at least one side of the first display area A1.

[0110] In some examples, as shown in FIG1 , the display area AA may be a rectangle, such as a rounded rectangle. The first display area A1 may be circular or elliptical. However, this embodiment is not limited thereto. For example, the first display area A1 may be a rectangle, a semicircle, a pentagon, or other shapes.

[0111] In some examples, the display area AA may be provided with a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a pixel driving circuit and a light-emitting element. The pixel driving circuit may be configured to drive the connected light-emitting element. For example, the pixel driving circuit may be configured to provide a driving current to drive the light-emitting element to emit light. The pixel driving circuit may include a plurality of transistors and at least one capacitor. For example, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0112] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel driving circuit. The light-emitting color of the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel driving circuit. However, this embodiment is not limited to this.

[0113] Figure 2 is a schematic diagram of the structure of a pixel drive circuit. Figure 2 uses 8T1C as an example. As shown in Figure 2, the pixel drive circuit can be connected to 11 signal lines (data line Data, first scan line Gate1, second scan line Gate2, first reset line Reset1, second reset line Reset2, light-emitting line E, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, first power line VDD, and second power line VSS). Among them, the gate lines include: first scan line Gate1, second scan line Gate2, first reset line Reset1, second reset line Reset2, and light-emitting line E.

[0114] In an exemplary embodiment, as shown in FIG2 , a control electrode of a first transistor T1 is connected to a first reset line Reset1, a first electrode of the first transistor T1 is connected to a first initial signal line INIT1, and a second electrode of the first transistor is connected to a third node N3. A control electrode of a second transistor T2 is connected to a second scan line Gate2, a first electrode of the second transistor T2 is connected to a first node N1, and a second electrode of the second transistor T2 is connected to a third node N3. A control electrode of a third transistor T3 is connected to a first node N1, a first electrode of the third transistor T3 is connected to a second node N2, and a second electrode of the third transistor T3 is connected to the third node N3. A control electrode of a fourth transistor T4 is connected to a first scan line Gate1, a first electrode of the fourth transistor T4 is connected to a data line Data, and a second electrode of the fourth transistor T4 is connected to a second node N2. A control electrode of a fifth transistor T5 is connected to an emission line E, a first electrode of the fifth transistor T5 is connected to a first power line VDD, and a second electrode of the fifth transistor T5 is connected to a second node N2. A control electrode of the sixth transistor T6 is connected to the emission line E, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4. A control electrode of the seventh transistor T7 is connected to the second reset line Reset2, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4. A control electrode of the eighth transistor T8 is connected to the second reset line Reset2, a first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and a second electrode of the eighth transistor T8 is connected to the second node N2. A first end of the capacitor C is connected to the first power supply line VDD, and a second end of the capacitor C is connected to the first node N1.

[0115] In an exemplary embodiment, a first electrode of the light emitting device is electrically connected to the fourth node N4, a second electrode of the light emitting device is connected to the second power line VSS,

[0116] In an exemplary embodiment, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously provided high level signal.

[0117] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0118] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include P-type transistors and N-type transistors.

[0119] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0120] In an exemplary embodiment, as shown in FIG. 2 , the second transistor T2 may be an N-type transistor, and the first transistor T1 and the third transistor T3 to the eighth transistor T8 may be P-type transistors.

[0121] FIG3 illustrates an operation process of the pixel driving circuit provided in FIG2. In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0122] The first phase P1 is called the first reset phase. The signal on the second reset line Reset2 is a low-level signal, and the signals on the first reset line Reset1, the first scan line Gate1, the second scan line Gate2, and the light-emitting line E are high-level signals. The signal on the second reset line Reset2 is a low-level signal, turning on the seventh transistor T7 and the eighth transistor T8. The signal on the second initial signal line INIT2 is supplied to the fourth node N4, initializing (resetting) the first electrode of the light-emitting device L and clearing the existing charge in the first electrode of the light-emitting device L. The signal on the third initial signal line INIT3 is supplied to the second node N2, initializing (resetting) the second node N2 and clearing the existing charge in the second node N2. During this phase, the third transistor T3 is turned on. The signal on the second scan line Gate2 is a high-level signal, turning on the second transistor T2. The signal of the second node N2 is provided to the first node N1 and the third node N3. The first node N1 and the third node N3 are initialized. The signals of the first reset line Reset1, the first scan line Gate1, and the light-emitting line E are high-level signals. The first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. At this stage, the light-emitting device L does not emit light.

[0123] The second phase P2, known as the second reset phase, is characterized by a low-level signal on the first reset line Reset1, while the signals on the second reset line Reset2, the first scan line Gate1, the second scan line Gate2, and the light-emitting line E are high-level signals. The low-level signal on the first reset line Reset1 causes the first transistor T1 and the signal on the first initial signal line INIT1 to be supplied to the third node N3, reinitializing (resetting) the third node N3 and clearing the charge previously stored in the third node N3. During this phase, the third transistor T3 remains on. The high-level signal on the second scan line Gate2 turns on the second transistor T2. The charge on the third node N3 is supplied to the first node N1, continuously initializing the first node N1. The high-level signals on the second reset line Reset2, the first scan line Gate1, and the light-emitting line E are all high-level signals. The fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. During this phase, the light-emitting device L does not emit light.

[0124] In the third phase P3, also known as the data writing phase or threshold compensation phase, the signal on the first scan line Gate1 is a low-level signal, while the signals on the first reset line Reset1, the second reset line Reset2, the second scan line Gate2, and the light-emitting line E are high-level signals. The data line Data outputs a data voltage. During this phase, the third transistor T3 is continuously turned on. The signal on the first scan line Gate1 is a low-level signal, turning on the fourth transistor T4. The signal on the second scan line Gate2 is a high-level signal, turning on the second transistor T2. The data voltage output by the data line Data is provided to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data line Data and the threshold voltage of the third transistor T3 is charged into the capacitor C. The voltage at the second end of the capacitor C (the first node N1) is Vd-|Vth|, where Vd is the data voltage output by the data line Data and Vth is the threshold voltage of the third transistor T3. The signals of the first reset line Reset1, the second reset line Reset2 and the light emitting line E are high level signals, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off. In this stage, the light emitting device L does not emit light.

[0125] In the fourth phase P4, known as the continuous compensation phase, the signals on the first reset line Reset1, the second reset line Reset2, the first scan line Gate1, the second scan line Gate2, and the light-emitting line E are high-level signals. The signal on the second scan line Gate2 is high-level signals, the second transistor T2 is continuously turned on, the signals on the first scan line Gate1, the first reset line Reset1, the second reset line Reset2, and the light-emitting line E are high-level signals, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. Although the signal on the data line Data stops being written, the second node N2 is still provided to the first node N1 through the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, continuously compensating for the threshold voltage of the third transistor T3.

[0126] In the fifth stage P5, referred to as the bias stage, the signals on the second scan line Gate2 and the second reset line Reset2 are low-level signals, while the signals on the first reset line Reset1, the first scan line Gate1, and the light-emitting line E are high-level signals. The signal on the second scan line Gate2 is low-level, while the signals on the first scan line Gate1, the first reset line Reset1, and the light-emitting line E are high-level signals. The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all turned off. The signal on the second reset line Reset2 is low-level, while the seventh transistor T7 and the eighth transistor T8 are turned on. The signal on the third initial signal line INIT3 is written to the second node N2 and the third node N3, and the signal on the second initial signal line INIT2 is written to the fourth node N3. During this stage, the third transistor T3 is in a biased state, and the light-emitting device L does not emit light.

[0127] In the sixth phase P6, known as the light-emitting phase, the signals on the light-emitting line E and the second scan line Gate2 are low-level signals, while the signals on the first reset line Reset1, the second reset line Reset2, and the first scan line Gate1 are high-level signals. The signal on the light-emitting signal line E is low-level, turning on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light-emitting device L to emit light.

[0128] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0129] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0130] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0131] With the continuous development of display technology, cameras are usually installed on display devices to meet the needs of shooting or face recognition. In order to maximize the screen-to-body ratio, technologies such as bangs screen, water drop screen, and hollowing out in the screen have appeared one after another. These technologies are achieved by making holes in part of the display area and placing a camera below the hole area to reduce the area occupied by the camera, thereby increasing the screen-to-body ratio. However, the above technology requires digging out part of the display area, which will cause part of the display image to be unable to be displayed, and the screen-to-body ratio cannot be further increased. In order to avoid punching holes in the display area and to make a true full screen possible while ensuring the practicality of the display substrate, an external pixel drive circuit method or a built-in pixel drive circuit method is usually adopted in the camera area under the screen.

[0132] The external pixel driver circuit method involves placing the pixel driver circuit connected to the light-emitting elements in the under-screen camera area in the normal display area. By separating the light-emitting elements and the pixel driver circuit, the light transmittance of the under-screen camera area is improved. Since the under-screen camera area does not have a pixel driver circuit, there is no other light-shielding layer in this area except for the anode of the light-emitting element, which can achieve higher light transmittance. However, in this method, the pixel driver circuit and the light-emitting element need to be electrically connected via conductive wires. Limited by the space for arranging the conductive wires, the size (e.g., aperture) of the under-screen camera area of ​​the display substrate using the external pixel driver circuit method is limited. Increasing the aperture of the under-screen camera area usually requires increasing the masking process for the conductive wires, resulting in increased costs. Furthermore, the conductive wires are usually made of transparent conductive materials, such as indium tin oxide (ITO). Due to the high sheet resistance of ITO, the conductive wires are loaded heavily, which can easily affect the brightness of the light-emitting elements in the under-screen camera area, reducing the brightness of the under-screen camera area and causing poor display quality in the under-screen camera area, such as vertical display mura.

[0133] The built-in pixel driver circuit method involves installing a light-emitting element and the pixel driver circuit connected to it in the under-screen camera area. Compared to the external pixel driver circuit method, the built-in method eliminates the need for long conductive wires to connect the pixel driver circuit and the light-emitting element in the under-screen camera area, thus avoiding display issues in the under-screen camera area caused by the conductive wires. Furthermore, the built-in method places no restrictions on the size of the under-screen camera area and can support under-screen camera areas with large apertures. However, in display substrates using the built-in pixel driver circuit method, the under-screen camera area has a large number of pixel driver circuit signal traces, making it difficult to avoid the light-transmitting area. Consequently, the transmittance of the under-screen camera area is affected.

[0134] In the structure of the pixel driving circuit shown in FIG2 , the second transistor T2 is an N-type transistor, and the first transistor T1, the third transistor T3, the third transistor T8, and the eighth transistor T9 are P-type transistors. That is, there is one N-type transistor and seven P-type transistors in the pixel driving circuit. This structure has the following problems: On the one hand, because the control electrodes of the seven P-type transistors are located in the same conductive layer, and the source, drain, and channel electrodes of the seven P-type transistors are located in the same film layer, the wiring space for the P-type transistors is limited, resulting in a large space occupation of the pixel driving circuit, making it difficult to increase the PPI (Pixels Per Inch, also known as pixel density) of the display substrate. Due to the large space occupied by the pixel driving circuit, the transmittance is affected. On the other hand, because the top gate, bottom gate, and channel of the N-type transistor occupy a total of three film layers, and the space occupied by one N-type transistor is redundant, the display substrate space is wasted to a certain extent.

[0135] An exemplary embodiment of the present disclosure provides a display substrate, which may include: a substrate and a plurality of sub-pixels arranged on the substrate, at least one sub-pixel including a pixel driving circuit, at least one pixel driving circuit including a plurality of first-type transistors and a plurality of second-type transistors, and an orthographic projection of at least one first-type transistor on the substrate at least partially overlapping with an orthographic projection of at least one second-type transistor on the substrate.

[0136] In the display substrate provided by the embodiment of the present disclosure, the orthographic projection of at least one first-type transistor in the display substrate on the substrate at least partially overlaps with the orthographic projection of at least one second-type transistor on the substrate, which can reduce the area of ​​the pixel driving circuit, save space on the display substrate, and improve the transmittance of the display substrate or the PPI of the display substrate.

[0137] As shown in Figure 4, the display substrate provided by the embodiment of the present disclosure may include a substrate and a plurality of sub-pixels arranged on the substrate, at least one sub-pixel may include a pixel driving circuit, at least one pixel driving circuit may include a plurality of first-type transistors M1 and a plurality of second-type transistors M2, and the orthographic projection of at least one first-type transistor M1 on the substrate at least partially overlaps with the orthographic projection of at least one second-type transistor M2 on the substrate.

[0138] In an exemplary embodiment, the display substrate may include a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a second semiconductor layer and a fourth conductive layer sequentially arranged on the substrate, wherein the first-type transistor M1 may include at least an active layer arranged in the first semiconductor layer (as shown in FIG10b ), and a control electrode arranged in the first conductive layer (as shown in FIG11b , which may be referred to as a first gate metal GATE1 layer); the second-type transistor M2 may include a shielding line arranged in the third conductive layer (as shown in FIG13b , which may be referred to as a third gate metal GATE3 layer), an active layer arranged in the second semiconductor layer (as shown in FIG14b ), and a control electrode arranged in the fourth conductive layer (as shown in FIG15b , which may be referred to as a fourth gate metal GATE4 layer).

[0139] In an exemplary embodiment, the active layer of at least a portion of the first type transistor M1 (as shown in FIG10b ) may at least partially overlap with the orthographic projection of at least a portion of the active layer of at least a portion of the second type transistor M2 (as shown in FIG14b ) on the substrate. In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region disposed between the first region and the second region. In an exemplary embodiment, the orthographic projection of at least a portion of the channel region of at least a portion of the first type transistor M1 (as shown in FIG10b ) may at least partially overlap with the orthographic projection of at least a portion of the channel region of at least a portion of the second type transistor M2 (as shown in FIG14b ) on the substrate.

[0140] In an exemplary embodiment, orthographic projections of control electrodes of at least a portion of the first type transistors M1 and control electrodes of at least a portion of the second type transistors M2 on the substrate may at least partially overlap.

[0141] In an exemplary embodiment, the first type of transistor M1 may be a low temperature polysilicon thin film transistor (ie, a P-type transistor), and the second type of transistor M2 may be an oxide thin film transistor (ie, an N-type transistor).

[0142] In an exemplary embodiment, as shown in FIG4 , the first type of transistor M1 may include at least a third transistor T3 serving as a driving transistor, and the second type of transistor M2 may include at least a first transistor T1 serving as a first initialization transistor; an orthographic projection of the first transistor T1 on the substrate at least partially overlaps with an orthographic projection of the third transistor T3 on the substrate. In an exemplary embodiment, a second electrode of the first transistor T1 may be electrically connected to a second electrode of the third transistor T3, and the first transistor T1 may be configured to provide a first initialization signal to the third transistor T3.

[0143] In an exemplary embodiment, as shown in FIG4 , the orthographic projections of the control electrode and active layer of the third transistor T3 on the substrate at least partially overlap with the orthographic projections of the control electrode and active layer of the first transistor T1 on the substrate, respectively. As shown in FIG10 b and FIG14 b , the orthographic projection of the active layer 21 of the first transistor T1 on the substrate may at least partially overlap with the orthographic projection of the active layer 23 of the third transistor T3 on the substrate. For example, the orthographic projection of the channel region 21-3 of the first transistor T1 on the substrate may at least partially overlap with the orthographic projection of the channel region 23-3 of the third transistor T3 on the substrate. As shown in FIG11 b , FIG13 b , and FIG15 b , the orthographic projection of the control electrode 33 of the third transistor T3 on the substrate at least partially overlaps with the orthographic projection of the control electrode (which may be referred to as a gate, including the bottom gate 52-1 in FIG13 b and the top gate 62-1 in FIG15 b ) of the first transistor T1 on the substrate.

[0144] In an exemplary embodiment, as shown in Figures 4, 11b and 12b, the pixel driving circuit may include a storage capacitor, which may include a first electrode plate 33 and a second electrode plate 43. The first electrode plate 33 may serve as a control electrode of the third transistor T3, and the orthographic projections of the first electrode plate 33, the second electrode plate 43, the channel region 23-3 of the active layer 23 of the third transistor T3, and the channel region 21-3 of the active layer 21 of the first transistor T1 on the substrate at least partially overlap.

[0145] In an exemplary embodiment, as shown in FIG4 , the first type of transistor M1 may further include a sixth transistor T6 serving as a light-emitting transistor, and the second type of transistor M2 may further include a seventh transistor T7 serving as a second initialization transistor. The orthographic projection of the sixth transistor T6 on the substrate at least partially overlaps with the orthographic projection of the seventh transistor T7 on the substrate. In an exemplary embodiment, the first electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 are both electrically connected to the second electrode of the third transistor T3, and the seventh transistor T7 may be configured to provide a second initialization signal to the third transistor T3.

[0146] In an exemplary embodiment, as shown in FIG4 , the orthographic projections of the control electrode and active layer of the sixth transistor T6 on the substrate at least partially overlap with the orthographic projections of the control electrode and active layer of the seventh transistor T7 on the substrate, respectively. As shown in FIG10 b and FIG14 b , the orthographic projection of the active layer 26 of the sixth transistor T6 on the substrate may at least partially overlap with the orthographic projection of the active layer 27 of the seventh transistor T7 on the substrate. For example, the orthographic projection of the channel region 26-3 of the active layer 26 of the sixth transistor T6 on the substrate may at least partially overlap with the orthographic projection of the channel region 27-3 of the active layer 27 of the seventh transistor T7 on the substrate; and the orthographic projection of the second region 26-2 of the active layer 26 of the sixth transistor T6 on the substrate may at least partially overlap with the orthographic projection of the second region 27-2 of the active layer 27 of the seventh transistor T7 on the substrate. As shown in Figures 11b, 13b and 15b, the positive projection of the control electrode 32-6 of the sixth transistor T6 on the substrate at least partially overlaps with the positive projection of the control electrode (which can be called a gate, including the bottom gate 53-7 in Figure 13b and the top gate 63-7 in Figure 15b) of the seventh transistor T7 on the substrate.

[0147] In an exemplary embodiment, as shown in Figure 4, the first type of transistor M1 may further include a fourth transistor T4 as a data writing transistor and a fifth transistor T5 as a light emitting transistor, and the second type of transistor M2 may further include a second transistor T2 as a compensation transistor and an eighth transistor T8 as a third initialization transistor; in an exemplary embodiment, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 are all electrically connected to the first electrode of the third transistor T3, the first electrode of the second transistor T2 is electrically connected to the control electrode of the third transistor T3, and the second electrode of the second transistor is electrically connected to the second electrode of the third transistor T3; in an exemplary embodiment, the fourth transistor T4 can be configured to provide a data signal to the third transistor T3, and the second transistor T2 is configured to provide a compensation signal to the third transistor T3.

[0148] In an exemplary embodiment, as shown in FIG4 , the orthographic projection of the active layer of the second transistor T2 on the substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor T6 on the substrate. As shown in FIG10 b and FIG14 b , the orthographic projection of the active layer 26 of the sixth transistor T6 on the substrate may at least partially overlap with the orthographic projection of the active layer 22 of the second transistor T2 on the substrate. For example, the orthographic projection of the first region 26 - 1 of the active layer 26 of the sixth transistor T6 on the substrate may at least partially overlap with the orthographic projection of the second region 22 - 2 of the active layer 22 of the second transistor T2 on the substrate.

[0149] In an exemplary embodiment, as shown in FIG4 , on a plane parallel to the display substrate, in a first direction X, the fourth transistor T4 and the fifth transistor T5 are located on one side of the first transistor T1 and the third transistor T3, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are located on the other side of the third transistor T3 and the first transistor T1, and the eighth transistor T8 is located between the fifth transistor T5 and the seventh transistor T7; in a second direction Y, the fourth transistor T4 and the second transistor T2 are located on one side of the third transistor T3, and the fifth transistor T5 to the eighth transistor T8 are located on the other side of the third transistor T3, and the first direction X intersects with the second direction Y.

[0150] In an exemplary embodiment, as shown in Figure 4, at least a portion of the structure of the first type of transistor M1 and at least a portion of the structure of the second type of transistor M2 are located in different conductive layers, and the orthographic projections of at least a portion of the structure of at least a first type of transistor M1 and at least a portion of the structure of the second type of transistor M2 on the substrate at least partially overlap, and the partial structure may include one or more of the control electrode and active layer of the transistor (which may include at least a portion of the first type of transistor M1 and at least a portion of the second type of transistor M2).

[0151] In an exemplary embodiment, the orthographic projection of the control electrode of at least one first-type transistor M1 on the substrate at least partially overlaps with the orthographic projection of the control electrode of at least one second-type transistor M2 on the substrate. For example, as shown in Figures 4, 11a, 11b, 13b, 15a, and 15b, the orthographic projection of the control electrode 33 of the third transistor T3 on the substrate at least partially overlaps with the orthographic projection of the control electrode (including the top gate electrode 62-1 and the ground gate electrode 52-1) of the first transistor T1, and the orthographic projection of the control electrode 32-6 of the sixth transistor T6 on the substrate at least partially overlaps with the orthographic projection of the control electrode (including the top gate electrode 63-7 and the bottom gate electrode 53-7) of the seventh transistor T7 on the substrate.

[0152] In an exemplary embodiment, an orthographic projection of the active layer of at least one first-type transistor M1 on the substrate at least partially overlaps with an orthographic projection of the active layer of at least one second-type transistor M2 on the substrate. For example, as shown in Figures 4, 10b, 11a, and 14a to 15a, a first region 26-1 of the active layer 26 of the sixth transistor T6 may at least partially overlap with an orthographic projection of the second region 22-2 of the active layer 22 of the second transistor T2 on the substrate; an orthographic projection of the channel region 27-3 and the second region 27-2 of the active layer 27 of the seventh transistor T7 on the substrate at least partially overlaps with an orthographic projection of the channel region 26-3 and the second region 26-2 of the active layer 26 of the sixth transistor T6 on the substrate, respectively; and an orthographic projection of the channel region 23-3 of the active layer 23 of the third transistor T3 on the substrate at least partially overlaps with an orthographic projection of the channel region 21-3 of the active layer 21 of the first transistor T1 on the substrate.

[0153] In an exemplary embodiment, as shown in Figures 5a and 5b, the pixel driver circuits for multiple sub-pixels are arranged in multiple rows, with a light-transmitting region K1 positioned between adjacent rows of pixel driver circuits. The light-transmitting region K1 and the orthographic projection of the pixel driver circuits on the substrate do not overlap, thereby preventing the pixel driver circuits from obstructing the light-transmitting region K1. In an exemplary embodiment, in a structure where an under-display camera is not required, the light-transmitting region K1 may be omitted, as shown in Figure 5c, further improving the PPI of the display substrate.

[0154] In an exemplary embodiment, as shown in Figures 6a and 6b, the display substrate may further include a blocking layer. In a direction perpendicular to the plane of the display substrate, the blocking layer may be located between the base and the pixel driving circuit. The blocking layer is provided with a light-transmitting opening K2, and the boundary lines of the light-transmitting opening K2 are smoothly connected. Figures 6e and 6f are schematic diagrams of the planar structure in which the blocking layer in the display substrate is provided with a light-transmitting opening K2. As shown in Figures 6a, 6b, 6e and 6f, the shape of the light-transmitting area K1 in Figures 6e and 6f may be consistent with the shape of the light-transmitting opening K2 in the blocking layer shown in Figures 6a and 6b.

[0155] In an exemplary embodiment, as shown in Figures 6c and 6d, the display substrate may further include a black matrix layer. The black matrix layer may be located on a side of the pixel driving circuit away from the substrate, perpendicular to the plane of the display substrate. The black matrix layer may be provided with a light-transmitting opening K2, with the boundary lines of the light-transmitting opening K2 being smoothly connected. Figures 6g and 6h are schematic planar structural diagrams of a shielding layer in the display substrate having a light-transmitting opening K2. As shown in Figures 6c, 6d, 6g, and 6h, the shape of the light-transmitting region K1 in Figures 6g and 6h may be consistent with the shape of the light-transmitting opening K2 in the black matrix layer shown in Figures 6c and 6d. In an exemplary embodiment, K3 in Figures 6c and 6d is a light-transmitting hole corresponding to the pixel opening. The black matrix layer may be provided on a side of the encapsulation layer away from the substrate.

[0156] In an exemplary embodiment, as shown in Figures 6a to 6d, the shape of the light-transmitting opening K2 can be an ellipse or a polygon, with the corners of the polygon being rounded. As shown in Figures 6b and 6d, the shape of the light-transmitting opening K2 can be a rectangle, with the corners of the rectangle being rounded, with one set of opposite sides of the rectangle being shorter. When the corners are rounded, the shorter set of opposite sides forms an arc.

[0157] In an exemplary embodiment, as shown in FIG. 6 a to FIG. 6 h , the orthographic projection of the light-transmitting opening K2 on the substrate overlaps with the orthographic projection of the light-transmitting area K1 on the substrate.

[0158] In an exemplary embodiment, a light-transmitting opening K2 is provided in the shielding layer or the black matrix layer. The light-transmitting opening K2 can define the shape of the light-transmitting area K1 in the display substrate. The boundary lines of the light-transmitting opening K2 are smoothly connected, which can reduce diffraction and thus improve the display effect. In an exemplary embodiment, the light-transmitting opening K2 can be implemented by a film layer in the shielding layer or the black matrix, or can be implemented by combining the two film layers. For example, the light-transmitting opening K2 in the black matrix layer and the light-transmitting opening K2 in the shielding layer can be spaced apart, or the orthographic projections of the light-transmitting opening K2 in the black matrix layer and the light-transmitting opening K2 in the shielding layer on the substrate at least partially overlap, thereby forming the final light-transmitting area K1.

[0159] In an exemplary embodiment, as shown in Figures 6e and 6f, the display substrate may further include an anode conductive layer, which is located on a side of the pixel driving circuit away from the substrate. The anode conductive layer may include a plurality of anodes 100, and each sub-pixel includes at least one anode 100. The anode 100 and the pixel driving circuit in the same sub-pixel are electrically connected to each other, and there is no overlapping area between the anode 100 and the orthographic projection of the light-transmitting area K1 on the substrate.

[0160] In an exemplary embodiment, as shown in Figures 6e and 6f, the plurality of sub-pixels may include a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels, the anode area of ​​the first sub-pixels and the anode area of ​​the second sub-pixels are both larger than the anode area of ​​the third sub-pixels, and the orthographic projections of the anodes of the first sub-pixels and the second sub-pixels on the substrate are within the range of the orthographic projection of the pixel driving circuit on the substrate.

[0161] In an exemplary embodiment, as shown in Figures 6e and 6f , a plurality of anodes 1003 of the third sub-pixels are arranged in an array on a plane parallel to the display substrate. In the row direction (i.e., the first direction X), the light-transmitting region K1 is located between the anodes 1003 of the third sub-pixels in two adjacent columns. In the column direction (i.e., the second direction Y), the anodes 1001 of the first sub-pixels and the anodes 1002 of the second sub-pixels are arranged alternately, and the light-transmitting region K2 may be located between the anodes 1001 of the first sub-pixels and the anodes 1002 of the second sub-pixels. In an exemplary embodiment, the row direction may be the first direction X, and the column direction may be the second direction Y.

[0162] In an exemplary embodiment, since the light-transmitting area K1 is located in the gap between two adjacent rows of pixel driving circuits, that is, no pixel driving circuit is set in the light-transmitting area K1 to avoid obstruction of the pixel driving circuit, in this case, the light-transmitting area K1 is set between the anodes 1003 of two adjacent third sub-pixels in the first direction X, so as to increase the area of ​​the light-transmitting area K1 as much as possible; if the light-transmitting area K1 is set between the anodes 1001 of two adjacent first sub-pixels, or the light-transmitting area K1 is set between the anodes 1002 of two adjacent second sub-pixels, or the light-transmitting area K1 is set between the anodes 1001 and the anodes 1002 of the adjacent first sub-pixels in the first direction X, since the areas of the anodes 1001 and the anodes 1002 of the first sub-pixels and the second sub-pixels are both larger than the area of ​​the anode 1003 of the third sub-pixel, the area of ​​the light-transmitting area K1 will be reduced, and the transmittance of the display substrate will be difficult to improve. In addition, since the orthographic projections of the anodes of the first sub-pixel and the second sub-pixel on the substrate are within the range of the orthographic projection of the pixel driving circuit on the substrate, in the column direction (i.e., the second direction Y), the light-transmitting area K1 is set between the anodes 1001 and the anodes 1002 of the adjacent first sub-pixel. The anodes of the first sub-pixel and the second sub-pixel will not occupy the space of the light-transmitting area K1 and will not affect the transmittance. With a reasonable design of the anode, the transmittance can be increased as much as possible.

[0163] In an exemplary embodiment, the display substrate includes a driving circuit layer, the driving circuit layer includes pixel driving circuits for a plurality of sub-pixels, and the pixel driving circuits may further include storage capacitors. In a direction perpendicular to the plane of the display substrate, the driving circuit layer includes a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a second semiconductor layer, and a fourth conductive layer sequentially disposed on a substrate.

[0164] The first semiconductor layer includes at least: an active layer of the first type transistor M1; the first conductive layer includes at least: a control electrode of the first type transistor M1 and a first plate of the storage capacitor; the second conductive layer includes at least: a second plate of the storage capacitor; the third conductive layer includes at least: a shielding layer of the second type transistor M2; the second semiconductor layer includes at least: an active layer of the second type transistor M2; and the fourth conductive layer includes at least: a control electrode of the second type transistor M2.

[0165] In an exemplary embodiment, the driving circuit layer may further include a fifth conductive layer, the fifth conductive layer being located on a side of the fourth conductive layer away from the second semiconductor layer, the fifth conductive layer including at least: a first electrode and a second electrode of the first type transistor M1 and a second type transistor M2;

[0166] The orthographic projections of the first electrode plate and the second electrode plate on the substrate at least partially overlap with the orthographic projection of the third transistor T3 on the substrate. In a plane parallel to the display substrate, in the second direction Y, a connection structure 33-1 is provided on the side of the first electrode plate close to the second transistor T2 (as shown in Figure 4). The orthographic projection of the connection structure 33-1 on the substrate does not at least partially overlap with the orthographic projections of the storage capacitor and the third transistor T3 on the substrate. The first electrode of the second transistor T2 is electrically connected to the connection structure through a via, and there is no overlapping area between the orthographic projection of the second transistor T2 on the substrate and the orthographic projection of the storage capacitor on the substrate.

[0167] In an exemplary embodiment, the pixel driving circuits of the plurality of sub-pixels form a plurality of columns, and the driving circuit layer further includes a sixth conductive layer and a seventh conductive layer. In a direction perpendicular to the plane of the display substrate, the sixth conductive layer is located on a side of the fifth conductive layer away from the fourth conductive layer, and the seventh conductive layer is located on a side of the sixth conductive layer away from the fifth conductive layer. As shown in FIG5 a , the sixth conductive layer at least includes: a data signal line 81, the data signal line 81 being electrically connected to the first electrode of the fourth transistor T4 in one column of the pixel driving circuits; the seventh conductive layer at least includes: a first power line 91, the first power line 91 being electrically connected to the first electrode of the fifth transistor T5 in two adjacent columns of the pixel driving circuits and the second plate of the storage capacitor;

[0168] On a plane parallel to the display substrate, the data signal lines 81 and the first power lines 91 extend along the second direction Y and are spaced apart along the first direction X. The data signal lines 81 of two adjacent columns of pixel driving circuits are located on either side of the first power lines 91 electrically connected to the two adjacent columns of pixel driving circuits. The two adjacent columns of pixel driving circuits are symmetrically arranged along a second center line Q2-Q2, which is the center line extending along the second direction Y between the two adjacent columns of pixel driving circuits. In the disclosed embodiment, the first power lines 91 separate the two adjacent data signal lines 81, thereby preventing signal crosstalk between the two adjacent data signal lines 81.

[0169] In an exemplary embodiment, as shown in FIG5 a , the sixth conductive layer may further include a shielding electrode 84 , and the seventh conductive layer may further include a first power connection line 93 and a second power connection line 94 ;

[0170] On a plane parallel to the display substrate, the first power connection line 93 extends along the second direction Y, and the second power connection line 94 extends along the first direction X, with each second power connection line 94 connected to at least part of the first power connection line 91. In the first direction, the shielding electrode 84 and the first power connection line 93 are located between two adjacent data signal lines 81. In the second direction, the first power connection line 93 is located between two adjacent second power connection lines 94, with both ends of the first power connection line 93 respectively connected to the two adjacent second power connection lines 94.

[0171] The orthographic projection of the shielding electrode 84 on the substrate covers the orthographic projection of the connection structure 33 - 1 on the substrate; the orthographic projections of the first power connection line 93 and the shielding electrode 81 on the substrate at least partially overlap, and the first power connection line 93 and the shielding electrode 84 are electrically connected through a via.

[0172] In the embodiment of the present disclosure, the shielding electrode 84 is located between two adjacent data signal lines 81. On the one hand, it can avoid signal crosstalk between the two adjacent data signal lines 81. On the other hand, it can shield the first node N1 of the pixel driving circuit (the first node N1 in Figure 2, which is also the node where the connection structure 33-1 is located), thereby shielding the influence of other signals on the first node N1 of the pixel driving circuit.

[0173] In the embodiment of the present disclosure, the second power connection line 94 is interconnected with the first power connection line 91 and the first power connection line 93 to form a grid structure, so that the power signal provided by the first power line 91 to the display substrate is kept as consistent as possible, thereby improving display uniformity.

[0174] In an exemplary embodiment, the orthographic projections of the first power line 91 and the two data signal lines 81 adjacent to the first power line 91 on the substrate can be symmetrical with respect to the orthographic projection of the midline of the main body of the anode 1003 of the third sub-pixel extending along the second direction Y on the substrate. This allows the anode 1003 of the third sub-pixel to be located as centrally as possible between the first power line 91 and the two data signal lines 81 adjacent to the first power line 91, thereby increasing the area of ​​the light-transmitting region K1 as much as possible, thereby improving the light transmittance of the display substrate.

[0175] In an exemplary embodiment, as shown in FIG6e and FIG6f , the orthographic projection of the anode 1003 of the third subpixel on the substrate may at least partially overlap with the orthographic projections of two adjacent rows of pixel driving circuits and the gap between two adjacent rows of pixel driving circuits on the substrate. In an exemplary embodiment, the orthographic projection of the anode 1003 of the third sub-pixel on the substrate may at least partially overlap with the orthographic projections of at least part of the film layers in the pixel driving circuits of two adjacent rows on the substrate. For example, at least part of the film layers in the pixel driving circuit may include at least part of or all of the following: a first semiconductor layer (as shown in FIG10b ), a first conductive layer (as shown in FIG11b , which may be referred to as a first gate metal GATE1 layer), a second conductive layer (as shown in FIG12b , which may be referred to as a second gate metal GATE2 layer), a third conductive layer (as shown in FIG13b , which may be referred to as a third gate metal GATE3 layer), a second semiconductor layer (as shown in FIG14b ), a fourth conductive layer (as shown in FIG15b , which may be referred to as a fourth gate metal GATE4 layer), a fifth conductive layer (as shown in FIG17b , which may be referred to as a first source / drain metal SD1 layer), a sixth conductive layer (as shown in FIG19b , which may be referred to as a second source / drain metal SD2 layer), and a seventh conductive layer (as shown in FIG21b , which may be referred to as a third source / drain metal SD3 layer). In an exemplary embodiment, the orthographic projection of the anode 1003 of the third sub-pixel on the substrate may not have an overlapping area with the orthographic projection of the second semiconductor layer in two adjacent rows of pixel driving circuits on the substrate.

[0176] In an exemplary embodiment, the orthographic projections of the anode 1001 of the first sub-pixel and the anode 1002 of the second sub-pixel on the substrate may at least partially overlap with the orthographic projections of at least a portion of the film layers of the corresponding pixel driving circuit on the substrate. For example, at least a portion of the film layers of the pixel driving circuit may be a portion or all of the first semiconductor layer (as shown in FIG10b ), the first conductive layer (as shown in FIG11b , which may be referred to as the first gate metal GATE1 layer), the second conductive layer (as shown in FIG12b , which may be referred to as the second gate metal GATE2 layer), the third conductive layer (as shown in FIG13b , which may be referred to as the third gate metal GATE3 layer), the second semiconductor layer (as shown in FIG14b ), the fourth conductive layer (as shown in FIG15b , which may be referred to as the fourth gate metal GATE4 layer), the fifth conductive layer (as shown in FIG17b , which may be referred to as the first source / drain metal SD1 layer), the sixth conductive layer (as shown in FIG19b , which may be referred to as the second source / drain metal SD2 layer), or the seventh conductive layer (as shown in FIG21b , which may be referred to as the third source / drain metal SD3 layer) in the pixel driving circuit. In an exemplary embodiment, orthographic projections of the anode 1001 of the first subpixel and the anode 1002 of the second subpixel on the substrate may at least partially overlap with orthographic projections of corresponding shielding layers (as shown in FIG. 9 ) on the substrate.

[0177] The embodiment of the present disclosure further provides a display substrate, as shown in Figures 6c to 6g, which may include a substrate and a plurality of sub-pixels arranged on the substrate, with a light-transmitting area K1 provided between at least two adjacent sub-pixels, and the boundary lines of the light-transmitting area K1 are smoothly connected.

[0178] In the display substrate provided by the embodiment of the present disclosure, a light-transmitting area is provided between at least two adjacent sub-pixels, and the boundary lines of the light-transmitting area are smoothly connected, which can reduce diffraction and thus improve the display effect.

[0179] In an exemplary embodiment, the subpixels include pixel driving circuits, the pixel driving circuits of the plurality of subpixels form multiple rows, and the light-transmitting area is located between two adjacent rows of pixel driving circuits, thereby preventing the pixel driving circuits from blocking the light-transmitting area K1.

[0180] In an exemplary embodiment, as shown in Figures 6a and 6b, the display substrate may further include a blocking layer. In a direction perpendicular to the plane of the display substrate, the blocking layer may be located between the base and the pixel driving circuit. The blocking layer is provided with a light-transmitting opening K2, and the boundary lines of the light-transmitting opening K2 are smoothly connected. Figures 6e and 6f are schematic diagrams of the planar structure in which the blocking layer in the display substrate is provided with a light-transmitting opening K2. As shown in Figures 6a, 6b, 6e and 6f, the shape of the light-transmitting area K1 in Figures 6e and 6f may be consistent with the shape of the light-transmitting opening K2 in the blocking layer shown in Figures 6a and 6b.

[0181] In an exemplary embodiment, as shown in Figures 6c and 6d, the display substrate may further include a black matrix layer. The black matrix layer may be located on a side of the pixel driving circuit away from the substrate, perpendicular to the plane of the display substrate. The black matrix layer may be provided with a light-transmitting opening K2, with the boundary lines of the light-transmitting opening K2 being smoothly connected. Figures 6g and 6h are schematic planar structural diagrams of a shielding layer in the display substrate having a light-transmitting opening K2. As shown in Figures 6c, 6d, 6g, and 6h, the shape of the light-transmitting region K1 in Figures 6g and 6h may be consistent with the shape of the light-transmitting opening K2 in the black matrix layer shown in Figures 6c and 6d. In an exemplary embodiment, K3 in Figures 6c and 6d is a light-transmitting hole corresponding to the pixel opening. The black matrix layer may be provided on a side of the encapsulation layer away from the substrate.

[0182] In an exemplary embodiment, as shown in Figures 6a to 6d, the shape of the light-transmitting opening K2 can be an ellipse or a polygon, with the corners of the polygon being rounded. As shown in Figures 6b and 6d, the shape of the light-transmitting opening K2 can be a rectangle, with the corners of the rectangle being rounded, with one set of opposite sides of the rectangle being shorter. When the corners are rounded, the shorter set of opposite sides forms an arc.

[0183] In an exemplary embodiment, as shown in FIG. 6 a to FIG. 6 h , the orthographic projection of the light-transmitting opening K2 on the substrate overlaps with the orthographic projection of the light-transmitting area K1 on the substrate.

[0184] In an exemplary embodiment, a light-transmitting opening K2 is provided in the shielding layer or the black matrix layer. The light-transmitting opening K2 can define the shape of the light-transmitting area K1 in the display substrate. The boundary lines of the light-transmitting opening K2 are smoothly connected, which can reduce diffraction and thus improve the display effect. In an exemplary embodiment, the light-transmitting opening K2 can be implemented by a film layer in the shielding layer or the black matrix, or can be implemented by combining the two film layers. For example, the light-transmitting opening K2 in the black matrix layer and the light-transmitting opening K2 in the shielding layer can be spaced apart, or the orthographic projections of the light-transmitting opening K2 in the black matrix layer and the light-transmitting opening K2 in the shielding layer on the substrate at least partially overlap, thereby forming the final light-transmitting area K1.

[0185] In an exemplary embodiment, as shown in Figures 6e and 6f, the display substrate may further include an anode conductive layer and a driving circuit layer, the pixel driving circuit is arranged in the driving circuit layer, the anode conductive layer is located on the side of the driving circuit layer away from the substrate, the anode conductive layer may include a plurality of anodes 100, each sub-pixel includes at least one anode 100, the anode 100 and the pixel driving circuit in the same sub-pixel are electrically connected to each other, and there is no overlapping area between the anode 100 and the orthographic projection of the light-transmitting area K1 on the substrate.

[0186] In an exemplary embodiment, as shown in Figures 6e and 6f, the plurality of sub-pixels may include a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels, the anode area of ​​the first sub-pixels and the anode area of ​​the second sub-pixels are both larger than the anode area of ​​the third sub-pixels, and the orthographic projections of the anodes of the first sub-pixels and the second sub-pixels on the substrate are within the range of the orthographic projection of the pixel driving circuit on the substrate.

[0187] In an exemplary embodiment, as shown in Figures 6e and 6f , a plurality of anodes 1003 of the third sub-pixels are arranged in an array on a plane parallel to the display substrate. In the row direction (i.e., the first direction X), the light-transmitting region K1 is located between the anodes 1003 of the third sub-pixels in two adjacent columns. In the column direction (i.e., the second direction Y), the anodes 1001 of the first sub-pixels and the anodes 1002 of the second sub-pixels are arranged alternately, and the light-transmitting region K2 may be located between the anodes 1001 of the first sub-pixels and the anodes 1002 of the second sub-pixels. In an exemplary embodiment, the column direction may be the second direction Y.

[0188] In an exemplary embodiment, since the light-transmitting area K1 is located in the gap between two adjacent rows of pixel driving circuits, that is, no pixel driving circuit is set in the light-transmitting area K1 to avoid obstruction of the pixel driving circuit, in this case, the light-transmitting area K1 is set between the anodes 1003 of two adjacent third sub-pixels in the first direction X, so as to increase the area of ​​the light-transmitting area K1 as much as possible; if the light-transmitting area K1 is set between the anodes 1001 of two adjacent first sub-pixels, or the light-transmitting area K1 is set between the anodes 1002 of two adjacent second sub-pixels, or the light-transmitting area K1 is set between the anodes 1001 and the anodes 1002 of the adjacent first sub-pixels in the first direction X, since the areas of the anodes 1001 and the anodes 1002 of the first sub-pixels and the second sub-pixels are both larger than the area of ​​the anode 1003 of the third sub-pixel, the area of ​​the light-transmitting area K1 will be reduced, and the transmittance of the display substrate will be difficult to improve. In addition, since the orthographic projections of the anodes of the first sub-pixel and the second sub-pixel on the substrate are within the range of the orthographic projection of the pixel driving circuit on the substrate, in the column direction (i.e., the second direction Y), the light-transmitting area K1 is set between the anodes 1001 and the anodes 1002 of the adjacent first sub-pixel. The anodes of the first sub-pixel and the second sub-pixel will not occupy the space of the light-transmitting area K1 and will not affect the transmittance. With a reasonable design of the anode, the transmittance can be increased as much as possible.

[0189] The present disclosure also provides a display substrate, as shown in FIG5 a , comprising a substrate and a plurality of pixels, a plurality of data signal lines 81 , and a plurality of first power lines 91 disposed on the substrate. In a plane parallel to the display substrate, the plurality of data signal lines 81 and the plurality of first power lines 91 extend along a second direction Y and are arranged at intervals along a first direction X, where the first direction X intersects the second direction Y.

[0190] At least some of the sub-pixels include pixel driving circuits, and the pixel driving circuits of multiple sub-pixels form multiple columns. Each data signal line 81 is electrically connected to at least some of the pixel driving circuits in one column of pixel driving circuits, and each first power line 91 is electrically connected to at least some of the pixel driving circuits in at least one column of pixel driving circuits. In the first direction X, two adjacent data signal lines 81 are located on both sides of the first power line 91.

[0191] In the display substrate provided by the embodiment of the present disclosure, two adjacent data signal lines 81 are separated by the first power line 91 , thereby avoiding signal crosstalk between the two adjacent data signal lines 81 .

[0192] In an exemplary embodiment, as shown in FIG5 a, each first power line 91 is electrically connected to two adjacent columns of pixel driving circuits, and the two adjacent columns of pixel driving circuits are symmetrically arranged along the second center line Q2-Q2, which is the center line of the two adjacent columns of pixel driving circuits extending along the second direction Y.

[0193] In an exemplary embodiment, as shown in FIG5a , the pixel driving circuit may further include a shielding electrode 84. In the first direction X, the shielding electrode 84 is disposed between two adjacent data signal lines 81. In the same column of pixel driving circuits, the data signal line 81 is located between the shielding electrode 84 and the first power line 91. In the embodiment of the present disclosure, the shielding electrode 84 is located between two adjacent data signal lines 81 to prevent signal crosstalk between the two adjacent data signal lines 81.

[0194] In an exemplary embodiment, as shown in FIG5 a , the display substrate may further include a first power connection line 93 and a second power connection line 94 . In a plane parallel to the display substrate, the first power connection line 93 extends along the second direction Y, and the second power connection line 94 extends along the first direction X. Each second power connection line 94 is connected to at least part of the first power line 91 .

[0195] In the first direction X, the first power connection line 93 is located between two adjacent data signal lines 81; in the second direction Y, the first power connection line 93 is located between two adjacent second power connection lines 94, and both ends of the first power connection line 93 are respectively connected to the two adjacent second power connection lines 94;

[0196] The shielding electrode 84 and the data signal line 81 are located in the same conductive layer, the first power line 91, the first power connection line 93 and the second power connection line 94 are located in the same conductive layer, and the data signal line 81 and the first power line 91 are located in different conductive layers; the orthographic projections of the first power connection line 93 and the shielding electrode 84 on the substrate at least partially overlap, and the first power line 91 and the shielding electrode 84 are electrically connected through a via.

[0197] In the embodiment of the present disclosure, the second power connection line 94 is interconnected with the first power connection line 91 and the first power connection line 93 to form a grid structure, so that the power signal provided by the first power line 91 to the display substrate is kept as consistent as possible, thereby improving display uniformity.

[0198] In the display substrate provided by the embodiment of the present disclosure, the equivalent circuit of the pixel driving circuit may be as shown in FIG7 . The difference between FIG7 and FIG2 is that the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are N-type transistors. FIG8 is an operation timing diagram of the pixel driving circuit provided by FIG7 . In an exemplary embodiment, the operation process of the pixel driving circuit shown in FIG7 may include:

[0199] The first phase P1 is called the first reset phase. The first reset line Reset1 is a low-level signal, while the signals on the second reset line Reset2, the first scan line Gate1, the second scan line Gate2, and the light-emitting line E are high-level signals. The signal on the second reset line Reset2 is a high-level signal, turning on the seventh transistor T7 and the eighth transistor T8. The signal on the second initial signal line INIT2 is supplied to the fourth node N4, initializing (resetting) the first electrode of the light-emitting device L and clearing the existing charge in the first electrode of the light-emitting device L. The signal on the third initial signal line INIT3 is supplied to the second node N2, initializing (resetting) the second node N2 and clearing the existing charge in the second node N2. During this phase, the third transistor T3 is turned on. The signal on the second scan line Gate2 is a high-level signal, turning on the second transistor T2. The signal of the second node N2 is provided to the first node N1 and the third node N3. The first node N1 and the third node N3 are initialized. The first reset line Reset1 is a low-level signal, the signals of the first scan line Gate1 and the light-emitting line E are high-level signals, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. At this stage, the light-emitting device L does not emit light.

[0200] The second phase P2, known as the second reset phase, is characterized by a low-level signal on the second reset line Reset2, while the signals on the first reset line Reset1, the first scan line Gate1, the second scan line Gate2, and the light-emitting line E are high-level signals. The high-level signal on the first reset line Reset1 causes the first transistor T1 and the signal on the first initial signal line INIT1 to be supplied to the third node N3, reinitializing (resetting) the third node N3 and clearing the existing charge in the third node N3. During this phase, the third transistor T3 is continuously turned on. The signal on the second scan line Gate2 is high-level, turning on the second transistor T2. The charge on the third node N3 is supplied to the first node N1, continuously initializing the first node N1. The second reset line Reset2 is low-level, and the signals on the first scan line Gate1 and the light-emitting line E are high-level signals. The fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. During this phase, the light-emitting device L does not emit light.

[0201] In the third phase P3, also known as the data writing phase or threshold compensation phase, the signal on the first scan line Gate1 is low, the first reset line Reset1 and the second reset line Reset2 are low, and the signals on the second scan line Gate2 and the light-emitting line E are high. The data line Data outputs a data voltage. During this phase, the third transistor T3 is continuously on. The low signal on the first scan line Gate1 turns on the fourth transistor T4. The high signal on the second scan line Gate2 turns on the second transistor T2. The data voltage output by the data line Data is provided to the first node N1 via the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data line Data and the threshold voltage of the third transistor T3 is charged into the capacitor C. The voltage at the second end of the capacitor C (the first node N1) is Vd-|Vth|, where Vd is the data voltage output by the data line Data and Vth is the threshold voltage of the third transistor T3. The first reset line Reset1 and the second reset line Reset2 are low level signals, the signal of the light emitting line E is high level signal, the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off. In this stage, the light emitting device L does not emit light.

[0202] In the fourth phase P4, known as the continuous compensation phase, the first reset line Reset1 and the second reset line Reset2 are low-level signals, while the signals on the first scan line Gate1, the second scan line Gate2, and the light-emitting line E are high-level signals. The signal on the second scan line Gate2 is high-level, and the second transistor T2 is continuously turned on. The first reset line Reset1 and the second reset line Reset2 are low-level signals, while the signals on the first scan line Gate1 and the light-emitting line E are high-level signals. The first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. Although the data line Data signal is no longer being written, the second node N2 is still provided to the first node N1 via the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, continuously compensating for the threshold voltage of the third transistor T3.

[0203] In the fifth stage P5, referred to as the bias stage, the first reset line Reset1 and the second scan line Gate2 are low-level signals, while the signals on the second reset line Reset2, the first scan line Gate1, and the light-emitting line E are high-level signals. The signals on the first reset line Reset1 and the second scan line Gate2 are low-level signals, the signals on the first scan line Gate1 and the light-emitting line E are high-level signals, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all turned off. The signal on the second reset line Reset2 is high-level, the seventh transistor T7 and the eighth transistor T8 are turned on, the signal on the third initial signal line INIT3 is written to the second node N2 and the third node N3, and the signal on the second initial signal line INIT2 is written to the fourth node N3. During this stage, the third transistor T3 is in a biased state, and the light-emitting device L does not emit light.

[0204] In the sixth phase P6, also known as the light-emitting phase, the signals on the first reset line Reset1, the second reset line Reset2, the light-emitting line E, and the second scan line Gate2 are low-level signals, while the signal on the first scan line Gate1 is high-level. The signal on the light-emitting signal line E is low-level, turning on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light-emitting device L to emit light.

[0205] The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a layer of thin film made by deposition, coating, or other processes on a substrate (or base substrate) of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in the direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. This is exemplified below using the preparation process of a display substrate:

[0206] In some examples, the preparation process of the display substrate may include the following operations. The display area AA driving circuit layer (which may be referred to as the circuit structure layer) is described below. This example is described using the first pixel driving circuit as the aforementioned 8T1C structure as an example. The connection relationship between the eight transistors and the storage capacitor in each first pixel driving circuit can be referred to the equivalent circuit diagram shown in Figure 7.

[0207] (101) Provide a substrate. In an exemplary embodiment, the substrate may be referred to as a base. In some examples, the substrate may be a rigid substrate or a flexible substrate. For example, the rigid substrate may be, but is not limited to, one or more of glass and quartz; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked thereon. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0208] (102) Forming a blocking layer pattern. In an exemplary embodiment, forming the blocking layer pattern may include: depositing a conductive film of the blocking layer on a substrate, patterning the conductive film of the blocking layer through a patterning process, and forming the blocking layer pattern on the substrate, as shown in FIG9 , which is a planar structural diagram of the blocking layer pattern in two sub-pixels.

[0209] In an exemplary embodiment, the blocking layer pattern of each sub-pixel may include a first blocking structure 11 , a second blocking structure 12 , a third blocking structure 13 , and a fourth blocking structure 14 .

[0210] In an exemplary embodiment, the first shielding structure 11 may be rectangular, the second shielding structure 12 and the third shielding structure 13 may be zigzag-shaped extending along the second direction Y, and the fourth shielding structure 14 may be L-shaped. The second shielding structure 12 and the third shielding structure 13 may be arranged sequentially in the second direction Y. In the first direction X, the fourth shielding structure 14 may be located on one side of the first shielding structure 11, while the second shielding structure 12 and the third shielding structure 13 may be located on the other side of the first shielding structure 11.

[0211] In an exemplary embodiment, the second to fourth connection structures 12 to 14 of each sub-pixel are connected to the first connection structure 11 to form an interconnected integral structure.

[0212] In an exemplary embodiment, the shapes of the shielding layers in two adjacent columns of sub-pixels can be symmetrical along the second centerline Q2-Q2, which can be the centerline between the two adjacent columns of sub-pixels extending along the second direction Y. In an exemplary embodiment, within the same row of sub-pixels, multiple shielding layers form multiple shielding structure groups, with the same shielding structure group including shielding layers for two adjacent sub-pixels. The fourth shielding structures 14 within the same shielding structure group are interconnected as an integrated structure, ensuring that the shielding layers of two adjacent sub-pixels in the display substrate have the same potential, which helps improve the uniformity of the panel, avoid display defects on the display substrate, and ensure the display quality of the display substrate. For example, within the Mth row of sub-pixels, the fourth shielding structures 14 in the Nth and N+1th columns of sub-pixels can be interconnected as an integrated structure.

[0213] In an exemplary embodiment, the blocking layer pattern can be formed after preparing the second flexible material (PI2) layer, that is, the blocking layer pattern can be arranged on the second flexible material (PI2) layer, and after the blocking layer pattern is prepared, the second barrier (Barrier2) layer is prepared; or, the blocking layer pattern can be formed after preparing the first flexible material (PI1) layer, that is, the blocking layer pattern can be arranged on the first flexible material (PI1) layer, and after the blocking layer pattern is prepared, the second flexible material (PI2) layer is prepared. The embodiments of the present disclosure are not limited to this.

[0214] (103) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the blocking layer pattern, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIG10a and FIG10b , where FIG10b is a plan view schematically illustrating the first semiconductor layers of the two sub-pixels in FIG10a .

[0215] In an exemplary embodiment, the first semiconductor layer pattern of each sub-pixel may include the active layer 2 of the third transistor T3 to the active layer 26 of the sixth transistor T6 , and the active layers 23 of the third transistor T3 to the active layer 26 of the sixth transistor T6 are connected to each other as an integral structure.

[0216] In an exemplary embodiment, in the first direction X, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on the same side of the active layer 23 of the third transistor T3, and the active layer 26 of the sixth transistor T6 is located on the other side of the active layer 23 of the third transistor T3; in the second direction Y, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on both sides of the active layer 23 of the third transistor T3, and the active layer 25 of the fifth transistor T5 and the second region 26-2 of the active layer 26 of the sixth transistor T6 are located on the same side of the active layer 23 of the third transistor T3, and the active layer 24 of the fourth transistor T4 and the first region 26-1 of the sixth transistor T6 are located on the same side of the active layer 23 of the third transistor T3.

[0217] In an exemplary embodiment, the sub-pixel in the Mth row and the Nth column is used as an example for description: in the first direction X, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on a side of the active layer 23 of the third transistor T3 away from the sub-pixel in the N+1th column, and the active layer 26 of the sixth transistor T6 is located on a side of the active layer 23 of the third transistor T3 away from the sub-pixel in the N-1th column; in the second direction Y, the active layer 24 of the fourth transistor T4 is located on a side of the active layer 23 of the third transistor T3 away from the sub-pixel in the M+1th row, and the active layer 25 of the fifth transistor T5 is located on a side of the active layer 23 of the third transistor T3 away from the sub-pixel in the M-1th row.

[0218] In an exemplary embodiment, the active layer 23 of the third transistor T3 may be shaped like an Ω or an X, the active layer 24 of the fourth transistor T4 may be shaped like an I, the active layer 25 of the fifth transistor T5 may be shaped like an L, and the active layer 26 of the sixth transistor T6 may be shaped like a zigzag extending along the second direction Y or may be shaped like an L.

[0219] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the first region 23-1 of the active layer 23 of the third transistor T3 may serve as the second region 24-2 of the active layer 24 of the fourth transistor T4 and the second region 25-2 of the active layer 25 of the fifth transistor T5. The second region 23-2 of the active layer 23 of the third transistor T3 may serve as the first region 26-1 of the active layer 26 of the sixth transistor T6. The first region 24-1 of the active layer 24 of the fourth transistor T4, the first region 25-1 of the active layer 25 of the fifth transistor T5, and the first region 26-1 and the second region 26-2 of the active layer 26 of the sixth transistor T6 may be provided separately. In an exemplary embodiment, the channel region 23-3 of the active layer 23 of the third transistor T3 may be located between the first region 23-1 and the second region 23-2 of the active layer 23 of the third transistor T3, the channel region 24-3 of the active layer 24 of the fourth transistor T4 may be located between the first region 24-1 and the second region 24-2 of the active layer 24 of the fourth transistor T4, the channel region 25-3 of the active layer 25 of the fifth transistor T5 may be located between the first region 25-1 and the second region 25-2 of the active layer 25 of the fifth transistor T5, and the channel region 26-3 of the active layer 26 of the sixth transistor T6 may be located between the first region 26-1 and the second region 26-2 of the active layer 26 of the sixth transistor T6.

[0220] In an exemplary embodiment, the shapes of the semiconductor layers in two adjacent columns of sub-pixels may be symmetrical along the second center line Q2-Q2. In an exemplary embodiment, the first semiconductor layer may be polycrystalline silicon (p-Si), meaning that the fourth transistor T4 through the sixth transistor T6 may be LTPS thin-film transistors. In an exemplary embodiment, patterning the first semiconductor film through a patterning process may include: first forming an amorphous silicon (a-Si) film on a first insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and then crystallizing the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, patterning the polycrystalline silicon film to form a first semiconductor layer pattern.

[0221] (104) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG11a and FIG11b , where FIG11b is a plan view schematic diagram of the first conductive layer in FIG11a . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0222] In an exemplary embodiment, the first conductive layer pattern may include at least: a first scanning signal line 31 (i.e., the first scanning line Gate1 in Figure 7), a light-emitting control line 32 (i.e., the light-emitting line E in Figure 7), and a first electrode 33 of a storage capacitor (which can serve as a control electrode of a third transistor T3). The main parts of the first scanning signal line 31 and the light-emitting control line 32 may extend along the first direction X.

[0223] In an exemplary embodiment, in the second direction Y, the first scanning signal line 31 and the light-emitting control line E are located on both sides of the first electrode 33 of the storage capacitor. For example, in the same sub-pixel, the first scanning signal line 31, the first electrode 33 of the storage capacitor, and the light-emitting control line 32 can be arranged along the second direction Y.

[0224] Take the M-th row and N-th column sub-pixel as an example: in the second direction Y, in the same sub-pixel, the light-emitting control line 32 can be located on the side of the first plate 33 of the storage capacitor close to the M+1-th row sub-pixel, and the first scanning signal line 31 can be located on the side of the first plate 33 of the storage capacitor close to the M-1-th row sub-pixel.

[0225] In an exemplary embodiment, the first electrode plate 33 may be located between the light-emission control line 32 and the first scan signal line 31 in the second direction Y. The first electrode plate 33 may be rectangular, and the corners of the rectangle may be chamfered. The orthographic projection of the first electrode plate 33 on the substrate overlaps with the orthographic projection of the active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 33 may serve as both a plate of the storage capacitor and a control electrode of the third transistor T3. In an exemplary embodiment, a connection structure 33-1 is provided on a side of the first electrode plate 33 near the first scan signal line 31.

[0226] In an exemplary embodiment, the first scan signal line 31 may have a zigzag structure extending along the first direction X. The first scan signal line 31 may bypass the connection structure 33-1 provided on the first electrode plate 33 of the storage capacitor in a direction opposite to the second direction Y. In an exemplary embodiment, the region where the first scan signal line 31 overlaps with the active layer 24 of the fourth transistor T4 may serve as the control electrode 31-4 of the fourth transistor T4.

[0227] In an exemplary embodiment, the region where the light emission control line 32 overlaps the active layer of the fifth transistor T5 may serve as the control electrode 32-5 of the fifth transistor T5, and the region where the light emission control line 32 overlaps the active layer of the sixth transistor T6 may serve as the control electrode 32-6 of the sixth transistor T6.

[0228] In an exemplary embodiment, the shapes of the first conductive layers in two adjacent columns of sub-pixels may be symmetrical along the second center line Q2-Q2. In an exemplary embodiment, the light emission control lines 32 may be designed with equal widths or with unequal widths, which not only facilitates the layout of the pixel structure but also reduces parasitic capacitance between signal lines.

[0229] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the third transistor T3 to the sixth transistor T6, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the active layer 23 of the third transistor T3 to the active layer 26 of the sixth transistor T6 are both conductorized.

[0230] (105) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG. 12a and FIG. 12b, FIG. 12a is a planar structural diagram of two sub-pixels, and FIG. 12b is a planar schematic diagram of the second conductive layer in FIG. 12a. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0231] In an exemplary embodiment, the second conductive layer pattern includes at least a first initial signal line 41 (i.e., the first initial signal line INIT1 in FIG. 7 ), a second initial signal line 42 (i.e., the second initial signal line INIT2 in FIG. 7 ), and a second plate 43 of a storage capacitor. The second plate 43 of the storage capacitor serves as the other plate of the storage capacitor. In the second direction Y, in the same sub-pixel, the first initial signal line 41 and the second initial signal line 42 are located on either side of the second plate 42. For example, in the same sub-pixel, the first initial signal line 41, the second plate 43 of the storage capacitor, and the second initial signal line 42 are arranged sequentially along the second direction Y.

[0232] In an exemplary embodiment, the outline of the second electrode plate 43 can be rectangular, and the corners of the rectangle can be chamfered. There is an overlapping area between the orthographic projection of the second electrode plate 43 on the substrate and the orthographic projection of the first electrode plate 33 on the substrate. The first electrode plate 33 and the second electrode plate 43 constitute a storage capacitor of the pixel driving circuit.

[0233] In an exemplary embodiment, in the same sub-pixel row, two adjacent second plates 43 are connected to each other, so that multiple second plates 43 located in the same sub-pixel row have approximately the same potential, which can ensure that the second plates of the storage capacitors of adjacent sub-pixels have the same potential, which is beneficial to improving the uniformity of the panel display, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0234] In an exemplary embodiment, the first preliminary signal line 41 and the second preliminary signal line 42 may be in the shape of a bar extending in the first direction X or a zigzag line.

[0235] In an exemplary embodiment, shapes of the second conductive layers in two adjacent columns of sub-pixels may be symmetrical along the second center line Q2 - Q2 .

[0236] (106) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a fourth insulating film and a third conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process to form a fourth insulating layer covering the second conductive layer, and a third conductive layer pattern disposed on the fourth insulating layer, as shown in FIG13a and FIG13b, FIG13a is a planar structural diagram of two sub-pixels, and FIG13b is a planar schematic diagram of the third conductive layer in FIG13a. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0237] In an exemplary embodiment, the third conductive layer pattern includes at least a first shielding line 51, a second shielding line 52, and a third shielding line 53. In an exemplary embodiment, in the second direction Y, in a sub-pixel row, the first shielding line 51 and the third shielding line 53 may be located on both sides of the second shielding line 52. For example, in a sub-pixel row, the first shielding line 51, the second shielding line 52, and the third shielding line 53 are arranged sequentially along the second direction Y.

[0238] In an exemplary embodiment, the orthographic projection of the first shielding line 51 on the substrate at least partially overlaps with the orthographic projection of the first scan signal line 31 on the substrate, which can save space on the display substrate and help improve the PPI and transmittance of the display substrate. In an exemplary embodiment, the first shielding line 51 can be a zigzag structure extending along the first direction X. The first shielding line 51 can bypass the connection structure 33-1 provided on the first plate 33 of the storage capacitor in the opposite direction of the second direction Y.

[0239] In an exemplary embodiment, the second shielding line 52 may be a fold line structure extending along the first direction X.

[0240] In an exemplary embodiment, the orthographic projection of the third shielding line 53 on the substrate at least partially overlaps with the orthographic projection of the light-emitting control line 32 on the substrate, which can save space on the display substrate and help improve the PPI and transmittance of the display substrate. In an exemplary embodiment, the third shielding line 53 can be a folded line structure or a strip structure extending along the first direction X.

[0241] In an exemplary embodiment, the first shielding line 51 can serve as a shielding layer for the second transistor T2, shielding the channel of the second transistor T2 to ensure the electrical performance of the oxide second transistor T2. In an exemplary embodiment, the signal of the first shielding line 51 and the second scan signal line formed subsequently can be the same, that is, the first shielding line 51 and the second scan signal line formed subsequently are connected in parallel, and both are connected to the same signal source, so that the first shielding line 51 and the channel region 22-3 of the active layer 22 of the second transistor T2 can serve as the bottom gate electrode (i.e., the bottom control electrode 51-2) of the second transistor T2, forming a dual-gate structure of the second transistor T2.

[0242] In an exemplary embodiment, the second shielding line 52 can serve as a shielding layer for the first transistor T1, shielding the channel of the first transistor T1 to ensure the electrical performance of the oxide first transistor T1. In an exemplary embodiment, the second shielding line 52 and the signal of the subsequently formed first reset control line can be the same, that is, the second shielding line 52 and the subsequently formed first reset control line are connected in parallel, and both are connected to the same signal source, so that the area where the second shielding line 52 overlaps with the channel region 21-3 of the active layer 21 of the first transistor T1 can serve as the bottom gate electrode (i.e., bottom control electrode 52-1) of the first transistor T1, forming a dual-gate structure of the first transistor T1.

[0243] In an exemplary embodiment, the third shielding line 53 can serve as a shielding layer for the seventh transistor T7 and the eighth transistor T8, shielding the channels of the seventh transistor T7 and the eighth transistor T8 to ensure the electrical performance of the oxide seventh transistor T7 and the eighth transistor T8. In an exemplary embodiment, the signal of the third shielding line 53 and the second reset control line formed subsequently can be the same, that is, the third shielding line 53 is connected in parallel with the second reset control line formed subsequently, and both are connected to the same signal source, so that the area where the third shielding line 53 overlaps with the channel region of the active layer of the seventh transistor T7 and the eighth transistor T8 can serve as the bottom gate electrode (i.e., bottom control electrode 53-7) of the seventh transistor T7 and the bottom gate electrode (i.e., bottom control electrode 53-8) of the eighth transistor T8, forming a dual-gate structure of the seventh transistor T7 and the eighth transistor T8.

[0244] In an exemplary embodiment, shapes of the third conductive layers in two adjacent columns of sub-pixels may be symmetrical along the second center line Q2 - Q2 .

[0245] (107) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: depositing a fifth insulating film and a second semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second semiconductor film through a patterning process to form a fifth insulating layer covering the third conductive layer, and a second semiconductor layer pattern disposed on the fifth insulating layer, as shown in FIG14a and FIG14b, where FIG14a is a planar structural diagram of two sub-pixels, and FIG14b is a planar schematic diagram of the second semiconductor layer in FIG14a.

[0246] In an exemplary embodiment, the second semiconductor layer pattern in each sub-pixel includes at least an active layer 21 of the first transistor T1 , an active layer 22 of the first transistor T2 , an active layer 27 of the seventh transistor T7 , and an active layer 28 of the eighth transistor T8 .

[0247] In an exemplary embodiment, the active layer 21 of the first transistor T1 may be shaped like an L, the active layer 22 of the second transistor T2, the active layer 27 of the seventh transistor T7, and the active layer 28 of the eighth transistor T8 may be shaped like an I, and the first and second regions of the active layer 21 of the first transistor T1, the active layer 22 of the second transistor T2, the active layer 27 of the seventh transistor T7, and the active layer 28 of the eighth transistor T8 may be separately provided.

[0248] In an exemplary embodiment, shapes of the second semiconductor layers in two adjacent columns of sub-pixels may be symmetrical along the second center line Q2 - Q2 .

[0249] In an exemplary embodiment, in a plane parallel to the display substrate, in a first direction X, the active layer 21 of the first transistor T1 may be located between the active layer 24 of the fourth transistor T4 and the active layer 22 of the second transistor T2, and the active layer 28 of the eighth transistor T8 may be located between the active layer 25 of the fifth transistor T5 and the active layer 27 of the seventh transistor T7; in a second direction Y, the active layer 28 of the eighth transistor T8 may be located on a side of the active layer 23 of the third transistor T3 away from the active layer 24 of the fourth transistor T4, the active layer 25 of the fifth transistor T5, the active layer 27 of the seventh transistor T7, and the active layer 28 of the eighth transistor T8 are located on the same side of the active layer 23 of the third transistor T3, and the active layer 22 of the second transistor T2, the active layer 25 of the seventh transistor T7, and the active layer 28 of the eighth transistor T8 are located on the same side of the active layer 23 of the third transistor T3. The active layer 24 of the fourth transistor T4 is located on the other side of the active layer 23 of the third transistor T3. The orthographic projection of the active layer 21 of the first transistor T1 on the substrate at least partially overlaps with the orthographic projection of the active layer 23 of the third transistor T3 on the substrate. The orthographic projections of the active layer 22 of the second transistor T2 and the active layer 27 of the seventh transistor T7 on the substrate partially overlap with the orthographic projection of the active layer 26 of the sixth transistor T6 on the substrate. For example, the orthographic projection of the active layer 22 of the second transistor T2 on the substrate partially overlaps with the orthographic projection of the first area 26-1 of the active layer 26 of the sixth transistor T6 on the substrate. The orthographic projection of the active layer 27 of the seventh transistor T7 on the substrate partially overlaps with the orthographic projection of the second area 26-2 of the active layer 26 of the sixth transistor T6 on the substrate.

[0250] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the first region and the second region of the active layer of the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 may be independently provided. In an exemplary embodiment, the channel region 21-3 of the active layer 21 of the first transistor T1 may be located between the first region 21-1 and the second region 21-2; the channel region 22-3 of the active layer 22 of the second transistor T2 may be located between the first region 22-1 and the second region 22-2; the channel region 27-3 of the active layer 27 of the seventh transistor T7 may be located between the first region 27-1 and the second region 27-2; and the channel region 28-3 of the active layer 28 of the eighth transistor T8 may be located between the first region 28-1 and the second region 28-2.

[0251] In an exemplary embodiment, the second semiconductor layer may be made of an oxide, i.e., the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are oxide thin-film transistors. In an exemplary embodiment, the oxide may be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc oxynitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxysulfide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the second semiconductor thin film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon. Since the leakage current of the IGZO TFT is relatively small, leakage of the first node N1 during the light emitting phase can be avoided.

[0252] In an exemplary embodiment, shapes of the second semiconductor layers in two adjacent columns of sub-pixels may be symmetrical along the second center line Q2 - Q2 .

[0253] (108) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a sixth insulating film and a fourth conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a fourth conductive layer pattern disposed on the sixth insulating layer, as shown in FIG. 15a and FIG. 15b , FIG. 15a is a planar structural diagram of two sub-pixels, and FIG. 15b is a planar schematic diagram of the fourth conductive layer in FIG. 15a . In an exemplary embodiment, the fourth conductive layer may be referred to as a fourth gate metal (GATE4) layer.

[0254] In an exemplary embodiment, the fourth conductive layer pattern includes at least: a second scan signal line 61 (i.e., the second scan line Gate2 in FIG. 7 ), a first reset control line 62 (i.e., the first reset line Reset1 in FIG. 7 ), a second reset control line 63 (i.e., the second reset line Reset2 in FIG. 7 ), and a third initial signal line 64 (i.e., the third initial signal line INIT3 in FIG. 7 ). In an exemplary embodiment, in a sub-pixel row, the second scan signal line 61, the first reset control line 62, the second reset control line 63, and the third initial signal line 64 are arranged sequentially along the second direction Y.

[0255] In an exemplary embodiment, the second scan signal line 61 can be a zigzag structure extending along the first direction X, and the second scan signal line 61 can bypass the connection structure 33-1 provided on the first electrode plate 33 of the storage capacitor in the opposite direction of the second direction Y. In an exemplary embodiment, the orthographic projection of the second scan signal line 61 on the substrate at least partially overlaps with the orthographic projection of the first shielding line 51 on the substrate. In an exemplary embodiment, the area where the second scan signal line 61 overlaps with the active layer 22 of the second transistor T2 serves as the control electrode (which can be called the top gate) 61-2 of the second transistor T2. In an exemplary embodiment, the signals of the first shielding line 51 and the second scan signal line 61 can be the same, that is, the two are connected in parallel and connected to the same signal source, so that the first shielding line 51 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the second transistor T2, forming a dual-gate structure of the second transistor T2.

[0256] In an exemplary embodiment, the first reset control line 62 may be a zigzag line extending along the first direction X. The orthographic projection of the first reset control line 62 on the substrate at least partially overlaps with the orthographic projection of the second shielding line 52 on the substrate. In an exemplary embodiment, the portion where the first reset control line 62 overlaps with the active layer 21 of the first transistor T1 may serve as the control electrode 62-1 of the first transistor T1. In an exemplary embodiment, the signals of the second shielding line 52 and the first reset control line 62 may be the same, i.e., the two are connected in parallel and connected to the same signal source, so that the second shielding line 52 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the first transistor T1, forming a dual-gate structure for the first transistor T1.

[0257] In an exemplary embodiment, the second reset control line 63 may be a zigzag structure extending along the first direction X. The orthographic projection of the second reset control line 63 on the substrate at least partially overlaps with the orthographic projection of the third shielding line 53 on the substrate. In an exemplary embodiment, the area where the second reset control line 63 overlaps with the active layer of the seventh transistor T7 and the eighth transistor T8 may serve as the control electrode 63-7 of the seventh transistor T7 and the control electrode 63-8 of the eighth transistor T8. In an exemplary embodiment, the signals of the third shielding line 53 and the second reset control line 63 may be the same, that is, the two are connected in parallel and connected to the same signal source, so that the third shielding line 53 can serve as the bottom gate electrode (i.e., bottom control electrode) of the seventh transistor T7 and the eighth transistor T8, forming a double-gate structure of the seventh transistor T7 and the eighth transistor T8.

[0258] In an exemplary embodiment, the third preliminary signal line 64 may be a zigzag structure or a bar structure extending along the first direction X.

[0259] In an exemplary embodiment, shapes of the fourth conductive layers in two adjacent columns of sub-pixels may be symmetrical along the second center line Q2 - Q2 .

[0260] (109) Forming a seventh insulating layer pattern. In an exemplary embodiment, forming the seventh insulating layer pattern may include: depositing a seventh insulating film on the substrate on which the aforementioned pattern is formed, patterning the seventh insulating film using a patterning process to form a seventh insulating layer covering the fourth conductive layer, wherein a plurality of via holes are provided on the seventh insulating layer, as shown in FIG16 , which is a planar structural diagram of two sub-pixels.

[0261] In an exemplary embodiment, the multiple via holes in each sub-pixel include at least a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9, a tenth via hole V10, an eleventh via hole V11, a twelfth via hole V12, a thirteenth via hole V13, a fourteenth via hole V14, a fifteenth via hole V15, a sixteenth via hole V16, a seventeenth via hole V17, and an eighteenth via hole V18.

[0262] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the orthographic projection of the active layer 24 of the fourth transistor T4 on the substrate. The seventh insulating layer, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the first via hole V1 are etched away, exposing the surface of the first region 24-1 of the active layer 24 of the fourth transistor T4. The first via hole V1 is configured to connect the first electrode of the subsequently formed fourth transistor T4 to the active layer 24 of the fourth transistor T4 through the via hole.

[0263] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the orthographic projection of the active layer 24 of the fourth transistor T4 on the substrate. The seventh insulating layer, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the second via V2 are etched away, exposing the surface of the second region 24-2 of the active layer 24 of the fourth transistor T4 (also the first region 23-1 of the active layer 23 of the third transistor T3 and the second region 25-2 of the active layer 25 of the fifth transistor T5). The second via V2 is configured to connect the second electrode of the subsequently formed fourth transistor T4 to the active layer 24 of the fourth transistor T4 through the via, connect the second electrode of the subsequently formed fifth transistor T5 to the active layer 25 of the fifth transistor T5 through the via, and connect the first electrode of the subsequently formed third transistor T3 to the active layer 23 of the third transistor T3 through the via.

[0264] In the exemplary embodiment, the orthographic projection of the third via V3 on the substrate is located within the orthographic projection of the active layer 25 of the fifth transistor T5 on the substrate. The seventh insulating layer, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the third via V3 are etched away, exposing the first region 25-1 of the active layer 25 of the fifth transistor T5. The third via V3 is configured to connect the first electrode of the subsequently formed fifth transistor T5 to the active layer 25 of the fifth transistor T5 through the via.

[0265] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is within the range of the orthographic projection of the active layer 26 of the sixth transistor T6 on the substrate. The seventh insulating layer, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away, exposing the surface of the first region 26-1 of the active layer 26 of the sixth transistor T6 (also the second region 23-2 of the active layer 23 of the third transistor T3). The fourth via V4 is configured to connect the first electrode of the subsequently formed sixth transistor T6 to the active layer 26 of the sixth transistor T6 through the via, and to connect the second electrode of the subsequently formed third transistor T3 to the active layer 23 of the third transistor T3 through the via.

[0266] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the orthographic projection of the active layer 26 of the sixth transistor T6 on the substrate. The seventh insulating layer, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via V5 are etched away, exposing the surface of the second region 26-2 of the active layer 26 of the sixth transistor T6. The fifth via V5 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the active layer 26 of the sixth transistor T6 through the via.

[0267] In the exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the orthographic projection of the active layer 21 of the first transistor T1 on the substrate. The seventh and sixth insulating layers within the sixth via V6 are etched away, exposing the surface of the first region 21-1 of the active layer 21 of the first transistor T1. The sixth via V6 is configured to connect the first electrode of the subsequently formed first transistor T1 to the active layer 21 of the first transistor T1 through the via.

[0268] In the exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the orthographic projection of the active layer 21 of the first transistor T1 on the substrate. The seventh and sixth insulating layers within the seventh via V7 are etched away, exposing the surface of the second region 21-2 of the active layer 21 of the first transistor T1. The seventh via V7 is configured to connect the second electrode of the subsequently formed first transistor T1 to the active layer 21 of the first transistor T1 through the via.

[0269] In the exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the orthographic projection of the active layer 22 of the second transistor T2 on the substrate. The seventh and sixth insulating layers within the eighth via V8 are etched away, exposing the surface of the first region 22-1 of the active layer 22 of the second transistor T2. The eighth via V8 is configured to connect the first electrode of the subsequently formed second transistor T22 to the active layer 22 of the second transistor T2 through the via.

[0270] In the exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the orthographic projection of the active layer 22 of the second transistor T2 on the substrate. The seventh and sixth insulating layers within the ninth via V9 are etched away, exposing the surface of the second region 22-2 of the active layer 22 of the second transistor T2. The ninth via V9 is configured to connect the second electrode of the subsequently formed second transistor T2 to the active layer 22 of the second transistor T2 through the ninth via V9.

[0271] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is located within the orthographic projection of the active layer 27 of the seventh transistor T7 on the substrate. The seventh and sixth insulating layers within the tenth via V10 are etched away, exposing the surface of the first region 27-1 of the active layer 27 of the seventh transistor T7. The tenth via V10 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the active layer 27 of the seventh transistor T7 through the via.

[0272] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the orthographic projection of the active layer 27 of the seventh transistor T7 on the substrate. The seventh and sixth insulating layers within the eleventh via hole V11 are etched away, exposing the surface of the second region 27-2 of the active layer 27 of the seventh transistor T7. The eleventh via hole V11 is configured to connect the second electrode of the subsequently formed seventh transistor T7 to the active layer 27 of the seventh transistor T7 through the via hole.

[0273] In the exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the orthographic projection of the active layer 28 of the eighth transistor T8 on the substrate. The seventh and sixth insulating layers within the twelfth via V12 are etched away, exposing the surface of the first region 28-1 of the active layer 28 of the eighth transistor T8. The twelfth via V12 is configured to connect the first electrode of the subsequently formed eighth transistor T8 to the active layer 28 of the eighth transistor T8 through the via.

[0274] In the exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the orthographic projection of the active layer 28 of the eighth transistor T8 on the substrate. The seventh and sixth insulating layers within the thirteenth via hole V13 are etched away, exposing the surface of the second region 28-2 of the active layer 28 of the eighth transistor T8. The thirteenth via hole V13 is configured to connect the second electrode of the subsequently formed eighth transistor T8 to the active layer 28 of the eighth transistor T8 through the via hole.

[0275] In the exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the orthographic projection of the connection structure 33-1 in the first electrode plate 33 on the substrate. The seventh insulating layer, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, and the third insulating layer within the fourteenth via V14 are etched away, exposing the surface of the connection structure 33-1. The fourteenth via V14 is configured to connect the first electrode of the subsequently formed second transistor T2 to the connection structure 33-1 through the via.

[0276] In an exemplary embodiment, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the first initial signal line 41 on the substrate. The seventh insulating layer, the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer within the fifteenth via hole V15 are etched away, exposing the surface of the first initial signal line 41. The fifteenth via hole V15 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first initial signal line 41 through the via hole.

[0277] In an exemplary embodiment, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the second initial signal line 42 on the substrate. The seventh insulating layer, the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer within the sixteenth via hole V16 are etched away, exposing the surface of the second initial signal line 42. The sixteenth via hole V16 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the second initial signal line 42 through the via hole.

[0278] In the exemplary embodiment, the orthographic projection of the seventeenth via hole V17 on the substrate is located within the orthographic projection of the second electrode plate 43 of the storage capacitor on the substrate. The seventh insulating layer, the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer within the seventeenth via hole V17 are etched away, exposing the surface of the second electrode plate 43 of the storage capacitor. The seventeenth via hole V17 is configured to connect the first electrode of the subsequently formed fifth transistor T5 to the second electrode plate 43 of the storage capacitor through the via hole.

[0279] In an exemplary embodiment, the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the third initial signal line 64 on the substrate. The seventh insulating layer within the eighteenth via hole V18 is etched away, exposing the surface of the third initial signal line 64. The eighteenth via hole V18 is configured to connect the first electrode of the subsequently formed eighth transistor T8 to the third initial signal line 64 through the via hole.

[0280] (110) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, patterning the fifth conductive film using a patterning process, and forming a fifth conductive layer disposed on the seventh insulating layer, as shown in FIG. 17a and FIG. 17b , where FIG. 17a is a planar structural diagram of two sub-pixels, and FIG. 17b is a planar schematic diagram of the fifth conductive layer in FIG. 17a . In an exemplary embodiment, the fifth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0281] In an exemplary embodiment, the fifth conductive layer includes at least a first connection electrode 71 , a second connection electrode 72 , a third connection electrode 73 , a fourth connection electrode 74 , a fifth connection electrode 75 , a sixth connection electrode 76 , a seventh connection electrode 77 , an eighth connection electrode 78 , and a ninth connection electrode 79 .

[0282] In an exemplary embodiment, the first connection electrode 71 may be in the shape of a strip with a main portion extending along the second direction Y. One end of the first connection electrode 71 is connected to the first region 21-1 of the active layer 21 of the first transistor T1 via a sixth via hole V6, and the other end is connected to the first initial signal line 41 in the row of sub-pixels via a fifteenth via hole V15. In an exemplary embodiment, the first connection electrode 71 may serve as the first electrode of the first transistor T1 and is configured to be connected to the first initial signal line 41 and the active layer 21 of the first transistor T1.

[0283] In an exemplary embodiment, the main portion of the second connection electrode 72 extends along the second direction Y. Its first end is connected to the second region 21-2 of the active layer 21 of the first transistor T1 via the seventh via V7, and its second end is connected to the second region 22-2 of the active layer 22 of the second transistor T2 via the ninth via V9. Furthermore, it is connected to the first region 26-1 of the active layer 26 of the sixth transistor T6 (also the second region 23-2 of the active layer 23 of the third transistor T3) via the fourth via V4. This allows the second electrodes of the first transistor T1, the second transistor T2, the third transistor T3, and the first electrode of the sixth transistor T6 to have the same potential. In an exemplary embodiment, the second connection electrode 72 can function as the second electrodes of the first transistor T1, the second transistor T2, the third transistor T3, and the first electrode of the sixth transistor T6.

[0284] In an exemplary embodiment, the third connection electrode 73 may have a strip-shaped structure. The extension direction of the third connection electrode 73 may form an acute angle with the second direction Y. One end of the third connection electrode 73 may be connected to the first region 22-1 of the active layer 22 of the second transistor T2 via an eighth via V8, and the other end may be connected to the connection structure 33-1 via a fourteenth via V14. This allows the first region 22-1 of the active layer 22 of the second transistor T2 and the first electrode plate 33 to have the same potential. In an exemplary embodiment, the third connection electrode 73 may serve as the first electrode of the second transistor T2.

[0285] In an exemplary embodiment, the fourth connection electrode 74 may be substantially rectangular, with chamfered corners. The fourth connection electrode 74 may be connected to the first region 24-1 of the active layer 24 of the fourth transistor T4 via a first via hole V1. In an exemplary embodiment, the fourth connection electrode 74 may serve as a first electrode of the fourth transistor T4. In an exemplary embodiment, the fourth connection electrode 74 may be configured to be electrically connected to a subsequently formed data signal line.

[0286] In an exemplary embodiment, the fifth connection electrode 75 may be shaped like a zigzag line extending along the second direction Y. One end of the fifth connection electrode 75 is connected to the second region 28-2 of the active layer 28 of the eighth transistor T8 via a thirteenth via hole V13, and the other end is connected to the second region 24-2 of the fourth transistor T4 (also the first region 23-1 of the active layer 23 of the third transistor T3 and the second region 25-2 of the active layer 25 of the fifth transistor T5) via a second via hole V2. In an exemplary embodiment, the fifth connection electrode 75 may serve as the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5.

[0287] In an exemplary embodiment, the sixth connection electrode 76 may be in the shape of a bar or a zigzag line extending along the second direction Y. One end of the sixth connection electrode 76 may be connected to the first region 25-1 of the active layer 25 of the fifth transistor T5 via the third via V3, and the other end may be connected to the second electrode plate 43 via the seventeenth via V17, so that the first region 25-1 of the active layer 25 of the fifth transistor T5 and the second electrode plate 43 have the same potential. In an exemplary embodiment, the sixth connection electrode 76 may serve as the first electrode of the fifth transistor T5.

[0288] In an exemplary embodiment, the seventh connection electrode 77 may be L-shaped. The seventh connection electrode 77 may be connected to the first region 27-1 of the active layer 27 of the seventh transistor T7 via a tenth via hole V10, and to the second initial signal line 42 via a sixteenth via hole V16. In an exemplary embodiment, the seventh connection electrode 77 may serve as the first electrode of the seventh transistor T7. In an exemplary embodiment, in the Mth row of sub-pixels, the seventh connection electrodes 77 in the Nth and N+1th columns of the sub-pixels are connected to each other as an integrated structure, and the seventh connection electrodes 77 in the N+2nd and N+3th columns of the sub-pixels are connected to each other as an integrated structure.

[0289] In an exemplary embodiment, the eighth connection electrode 78 may have a polygonal structure (e.g., a substantially triangular structure). The eighth connection electrode 78 may be connected to the second region 26-6 of the active layer 26 of the sixth transistor T6 via a fifth via V5, and may be connected to the second region 27-2 of the active layer 27 of the seventh transistor T7 via an eleventh via V11. In an exemplary embodiment, the eighth connection electrode 58 may serve as the first electrode of the ninth transistor T9, so that the second region 26-2 of the active layer 26 of the sixth transistor T6 and the second region 27-2 of the active layer 27 of the seventh transistor T7 have the same potential. In an exemplary embodiment, the eighth connection electrode 78 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In an exemplary embodiment, the eighth connection electrode 78 is configured to be connected to the anode connection electrode of a subsequently formed light-emitting element.

[0290] In an exemplary embodiment, the ninth connection electrode 79 may be a strip-shaped structure with a main portion extending along the second direction Y. The ninth connection electrode 79 is connected to the first region 28-1 of the active layer 28 of the eighth transistor T8 through a twelfth via hole V12 and to the third initial signal line 64 through an eighteenth via hole V18. The third initial signal line 64 can write an initial voltage to multiple eighth transistors T8 in a subpixel row, thereby electrically connecting the third initial signal line 64 to the first region 28-1 of the active layer 28 of the eighth transistor T8. In an exemplary embodiment, since the third initial signal line 64 is connected to the first region 18-1 of the active layer 28 of all eighth transistors T8 in a subpixel row, the first electrodes of all eighth transistors T8 in a subpixel row can be guaranteed to have the same potential, which is beneficial for improving the uniformity of the panel, avoiding display defects on the display substrate, and ensuring the display quality of the display substrate. In an exemplary embodiment, the ninth connection electrode 79 can serve as the first electrode of the eighth transistor T8.

[0291] In an exemplary embodiment, shapes of the fifth conductive layers in two adjacent columns of sub-pixels may be symmetrical along the second center line Q2 - Q2 .

[0292] (111) Forming patterns of an eighth insulating layer and a first planar layer. In an exemplary embodiment, forming patterns of the eighth insulating layer and the first planar layer may include: first depositing an eighth insulating film on the substrate on which the aforementioned pattern is formed, then coating the first planar film, patterning the first planar film and the eighth insulating film using a patterning process to form an eighth insulating layer covering the fifth conductive layer pattern and a first planar layer disposed on the eighth insulating layer, wherein a plurality of vias are disposed on the eighth insulating layer and the first planar layer, as shown in FIG18 , which is a planar structural diagram of two sub-pixels.

[0293] In an exemplary embodiment, the plurality of via holes in each sub-pixel may include at least a nineteenth via hole V19 , a twentieth via hole V20 , and a twenty-first via hole V21 .

[0294] In an exemplary embodiment, the orthographic projection of the nineteenth via hole V19 on the substrate is located within the range of the orthographic projection of the fourth connection electrode 74 on the substrate. The first planar layer and the eighth insulating layer within the nineteenth via hole V19 are etched away, exposing the surface of the fourth connection electrode 74. The nineteenth via hole V19 is configured to allow a subsequently formed data signal line to be connected to the fourth connection electrode 74 through the via hole.

[0295] In an exemplary embodiment, the orthographic projection of the twentieth via hole V20 on the substrate is within the range of the orthographic projection of the sixth connection electrode 76 on the substrate. The first planar layer and the eighth insulating layer within the twentieth via hole V20 are etched away, exposing the surface of the sixth connection electrode 76. The twentieth via hole V20 is configured to electrically connect a subsequently formed first power transfer electrode to the sixth connection electrode 76 through the via hole.

[0296] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the eighth connection electrode 78 on the substrate. The first planar layer and the eighth insulating layer within the twenty-first via hole V21 are etched away, exposing the surface of the eighth connection electrode 78. The twenty-first via hole V21 is configured to connect an anode connection electrode of a subsequently formed light-emitting element (e.g., a subsequently formed first anode connection electrode) to the eighth connection electrode 78 through the via hole.

[0297] (112) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming the sixth conductive layer may include: depositing a sixth conductive film on the substrate having the aforementioned pattern formed thereon, patterning the sixth conductive film using a patterning process, and forming a sixth conductive layer disposed on the first flat layer, as shown in FIG. 19a and FIG. 19b , where FIG. 19a is a planar structural diagram of two sub-pixels, and FIG. 19b is a planar schematic diagram of the sixth conductive layer in FIG. 19a . In an exemplary embodiment, the sixth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0298] In an exemplary embodiment, the sixth conductive layer at least includes: a data signal line 81 (ie, the data line Data in FIG. 7 ), a first power transfer electrode 82 , a first anode connection electrode 83 , and a shielding electrode 84 .

[0299] In an exemplary embodiment, the data signal line 81 is in the shape of a bar or a broken line, the main portion of which extends along the second direction Y. The data signal line 81 is connected to the fourth connection electrode 74 through the nineteenth via V19. Since the fourth connection electrode 74 is connected to the first area 24-1 of the active layer 24 of the fourth transistor T4 through the via, the data signal line 81 is connected to the first electrode of the fourth transistor T4, thereby writing the data signal into the fourth transistor T4.

[0300] In an exemplary embodiment, the first power adapter electrode 82 is in the shape of a zigzag line or a strip, with a main portion extending along the second direction Y. The first power adapter electrode 82 is connected to the sixth connection electrode 76 via a twentieth via hole V20. Because the sixth connection electrode 76 is connected to the first region 25-1 of the active layer 25 of the fifth transistor T5 and the second electrode plate 43 via the via hole, the first power adapter electrode 82 is connected to the first electrode and the second electrode plate 43 of the fifth transistor T5. This allows the power signal of the subsequently formed first power line to be written to the second electrode plate 43 and the first electrode of the fifth transistor T5.

[0301] In an exemplary embodiment, the first anode connection electrode 83 has a zigzag or strip shape, with a main portion extending along the second direction Y. The first anode connection electrode 83 is connected to the eighth connection electrode 78 via a twenty-first via hole V21. Because the eighth connection electrode 78 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 via the via hole, the first anode connection electrode 83 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In the same sub-pixel, in the first direction X, the first power adapter electrode 82 and the first anode connection electrode 83 can be located on both sides of the data signal line 81.

[0302] In an exemplary embodiment, the shielding electrode 84 may be substantially n-shaped. In the first direction X, the shielding electrode 84 may be located between two adjacent data signal lines 81. In the second direction Y, the first anode connection electrode 83 may be located on one side of the shielding electrode 84. For example, the shielding electrode 84 and the first anode connection electrode 83 may be arranged sequentially along the second direction Y. In an exemplary embodiment, the orthographic projection of the shielding electrode 84 on the substrate may at least partially overlap with the orthographic projections of the second connection electrode 72 and the third connection electrode 73 on the substrate, thereby shielding the first node N1 of the pixel driving circuit from the influence of other signals on the first node N1 of the pixel driving circuit. In an exemplary embodiment, in the same sub-pixel row, one shielding electrode 84 may shield the first nodes N1 of two adjacent sub-pixels.

[0303] (113) Forming a second flat layer pattern. In an exemplary embodiment, forming the second flat layer pattern may include: coating a second flat film on the substrate on which the aforementioned pattern is formed, patterning the second flat film using a patterning process to form a second flat layer covering the sixth conductive layer pattern, wherein a plurality of vias are provided on the second flat layer, as shown in FIG20 , which is a planar structural diagram of two sub-pixels.

[0304] In an exemplary embodiment, the plurality of via holes may include at least a twenty-second via hole V22 , a twenty-third via hole V23 , and a twenty-fourth via hole V24 .

[0305] In an exemplary embodiment, the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the shielding electrode 84 on the substrate, the second flat layer in the twenty-second via V22 is removed to expose the surface of the shielding electrode 84, and the twenty-second via V22 is configured to electrically connect the subsequently formed first power signal connection line to the shielding electrode 84 through the via.

[0306] In an exemplary embodiment, the orthographic projection of the twenty-third via V23 on the substrate is located within the range of the orthographic projection of the first power conversion electrode 82 on the substrate, the second flat layer in the twenty-third via V23 is removed, exposing the surface of the first power conversion electrode 82, and the twenty-third via V23 is configured to electrically connect the subsequently formed first power line to the first power conversion electrode 82 through the via.

[0307] In an exemplary embodiment, the via holes of each sub-pixel include at least a twenty-fourth via hole V24. The orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the first anode connecting electrode 83 on the substrate. The second planar layer within the twenty-fourth via hole V24 is removed, exposing the surface of the first anode connecting electrode 83. The twenty-fourth via hole V24 is configured to electrically connect a subsequently formed second anode connecting electrode to the first anode connecting electrode 83 through the via hole.

[0308] (114) Forming a seventh conductive layer pattern. In an exemplary embodiment, forming the seventh conductive layer may include: depositing a seventh conductive film on the substrate having the aforementioned pattern formed thereon, patterning the seventh conductive film using a patterning process, and forming a seventh conductive layer disposed on the second flat layer, as shown in FIG. 21a and FIG. 21b , where FIG. 21a is a planar structural diagram of two sub-pixels, and FIG. 21b is a planar schematic diagram of the seventh conductive layer in FIG. 21a . In an exemplary embodiment, the seventh conductive layer may be referred to as a third source / drain metal (SD3) layer.

[0309] In an exemplary embodiment, the seventh conductive layer includes at least a first power line 91 (i.e., the first power line VDD in FIG. 7 ), a second anode connection electrode 92, a first power connection line 93, and a second power connection line 94. In an exemplary embodiment, the first anode connection electrode 83 and the second anode connection electrode 92 may be anode connection electrodes of a light-emitting element.

[0310] In an exemplary embodiment, the first power line 91 is in the shape of a zigzag line or a strip, with its main portion extending along the second direction Y. The first power line 91 is connected to the first power adapter electrode 82 via a twenty-third via hole V23. Since the first power adapter electrode 82 is connected to the sixth connection electrode 76 via the via hole, and the sixth connection electrode 76 is connected to the first region 25-1 of the active layer 25 and the second electrode plate 43 of the fifth transistor T5 via the via hole, the first power line 91 is connected to the first electrode and the second electrode plate 43 of the fifth transistor T5, thereby realizing the connection between the first power line 91 and the second electrode plate 43 of the fifth transistor T5, and the power signal is written to the second electrode plate 43 and the first electrode of the fifth transistor T5.

[0311] In an exemplary embodiment, multiple columns of first power lines 91 are electrically connected to multiple rows of sub-pixels' second plates 43 (multiple second plates 43 in the same row of sub-pixels are interconnected) to form a grid, which can enable the multiple first power lines 91 in the display substrate to have basically the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0312] In an exemplary embodiment, the second anode connection electrode 92 may be substantially rectangular or strip-shaped extending along the second direction Y. The second anode connection electrode 92 is connected to the first anode connection electrode 83 via a twenty-fourth via hole V24. Since the first anode connection electrode 83 is connected to the eighth connection electrode 78 via the via hole, and the eighth connection electrode 78 is connected to the second region 26-2 of the active layer 26 of the sixth transistor T6 (also the second region 27-2 of the active layer 27 of the seventh transistor T7) via the via hole, the second anode connection electrode 92 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0313] In an exemplary embodiment, the first power connection line 93 can be a strip structure extending along the second direction Y. The first power connection line 93 can be electrically connected to the shielding electrode 84 through the twenty-second via V22. The first power connection line 93 can be connected to the first power line 91 through the second power connection line 94 or to the first power signal supply line located in the border area (Figures 21a and 21b show that the first power connection line 93 is connected to the first power line 91 through the second power connection line 94) to provide a power signal to the shielding electrode 84.

[0314] In an exemplary embodiment, the second power connection line 94 may be a strip-shaped structure extending along the first direction X, and the second power connection line 94 may be connected to the first power line 91. The second power connection line 94 is interconnected with the first power line 91 and the first power connection line 93 to form a grid-like structure, so that the power signal provided by the first power line 91 to the display substrate is kept as consistent as possible, thereby improving display uniformity.

[0315] (115) Forming a third planar layer pattern. In an exemplary embodiment, forming the third planar layer pattern may include: coating a third planar film on the substrate on which the aforementioned pattern is formed, patterning the third planar film using a patterning process to form a third planar layer covering the seventh conductive layer pattern, wherein a plurality of via holes are provided on the third planar layer, as shown in FIG22 , which is a planar structural diagram of two sub-pixels.

[0316] In an exemplary embodiment, the plurality of via holes may include at least a twenty-fifth via hole V25 .

[0317] In an exemplary embodiment, the via holes of each subpixel include at least a twenty-fifth via hole V25. The orthographic projection of the twenty-fifth via hole V25 on the substrate is located within the range of the orthographic projection of the second anode connecting electrode 92 on the substrate. The third planar layer within the twenty-fifth via hole V25 is removed, exposing the surface of the second anode connecting electrode 92. The twenty-fifth via hole V25 is configured to electrically connect a subsequently formed anode to the second anode connecting electrode 92 through the via hole. In an exemplary embodiment, the twenty-fifth via hole V25 can serve as an anode via hole.

[0318] At this point, the driving circuit layer is completed on the substrate. In an exemplary embodiment, in a plane perpendicular to the display substrate, the driving circuit layer may include a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a second semiconductor layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer sequentially disposed on the substrate.

[0319] In an exemplary embodiment, the driving circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, a seventh insulating layer, an eighth insulating layer, a first flat layer, a second flat layer and a third flat layer, the first insulating layer being arranged between the substrate (or blocking layer) and the first semiconductor layer, the second insulating layer being arranged between the first semiconductor layer and the first conductive layer, the third insulating layer being arranged between the first conductive layer and the second conductive layer, the fourth insulating layer being arranged between the second conductive layer and the third conductive layer, the fifth insulating layer being arranged between the third conductive layer and the second semiconductor layer, the sixth insulating layer being arranged between the second semiconductor layer and the fourth conductive layer, the seventh insulating layer being arranged between the fourth conductive layer and the fifth conductive layer, the eighth insulating layer and the first flat layer being arranged between the fifth conductive layer and the sixth conductive layer, the second flat layer being arranged between the sixth conductive layer and the seventh conductive layer, and the third flat layer being arranged on the seventh conductive layer.

[0320] In an exemplary embodiment, after the driving circuit layer is prepared, a light-emitting structure layer is prepared on the driving circuit layer. The preparation process of the light-emitting structure layer may include the following operations: forming an anode pattern (i.e., an anode conductive layer), the anode is connected to the second anode connection electrode through an anode via (i.e., the twenty-fifth via V25); forming a pixel definition layer, the pixel definition layer is provided with a pixel opening, and the pixel opening exposes the anode; forming an organic light-emitting layer by evaporation or inkjet printing, the organic light-emitting layer is connected to the anode through the pixel opening, and a cathode is formed on the organic light-emitting layer; forming an encapsulation layer, the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is provided between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer; forming a black matrix layer. The steps of forming the anode conductive layer, the pixel definition layer, the encapsulation layer, and the black matrix layer are as follows:

[0321] (116) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer pattern disposed on the third flat layer, as shown in FIG. 23a and FIG. 23b , where FIG. 23a is a schematic planar structure diagram of two sub-pixels, and FIG. 23b is a schematic planar diagram of the anode conductive layer in FIG. 23a .

[0322] In an exemplary embodiment, the anode conductive layer pattern may include at least a plurality of anodes 100, as shown in Figures 6e and 6f, and the plurality of anodes 100 may include: a first anode 1001 of a red light-emitting unit (i.e., the anode 1001 of a first sub-pixel), a second anode 1002 of a blue light-emitting unit (i.e., the anode 1002 of a second sub-pixel), and a third anode 1003 of a green light-emitting unit (i.e., the anode 1003 of a third sub-pixel). The area where the first anode 1001 is located can form a red light-emitting unit that emits red light, the area where the second anode 1002 is located can form a blue light-emitting unit that emits blue light, and the area where the third anode 1003 is located can form a green light-emitting unit that emits green light.

[0323] In an exemplary embodiment, the first anode 1001, the second anode 1002, and the third anode 1003 can be connected to the second anode connection electrode 92 in the corresponding sub-pixel through the twenty-fifth via hole V25. Since the second anode connection electrode 92 in the sub-pixel is electrically connected to the second electrode of the sixth transistor T6 (also the second electrode of the seventh transistor T7) through the via hole, the first anode 1001, the second anode 1002, and the third anode 1003 can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 through the second anode connection electrode 92, respectively, thereby enabling the pixel driving circuit to drive the light-emitting device to emit light.

[0324] In an exemplary embodiment, the anode 100 may include an anode main portion 101 and an anode connecting portion 102. The anode main portion 101 may have a circular or elliptical structure. One end of the anode connecting portion 102 is connected to the anode main portion 101, and the other end is electrically connected to the second anode connecting electrode 92 through the twenty-fifth via hole V25. The anode connecting portion 102 may have a strip-shaped structure and may be configured to compensate for differences in parasitic capacitance generated by signal routing between multiple sub-pixels. By providing the anode connecting portion 102, the parasitic capacitance of the multiple sub-pixels can be kept consistent, thereby improving the display uniformity of the display substrate.

[0325] (117) Forming a pixel definition layer pattern. In an exemplary embodiment, forming the pixel definition layer pattern may include: depositing a pixel definition layer thin film on the substrate on which the aforementioned pattern is formed, and patterning the pixel definition layer thin film using a patterning process to form an anode conductive layer pattern disposed on the anode conductive layer, as shown in FIG. 24a and FIG. 24b , where FIG. 24a is a schematic plan view of the structure of four sub-pixels, and FIG. 24b is a schematic plan view of the pixel definition layer in FIG. 24a .

[0326] In an exemplary embodiment, the pixel definition layer pattern may include at least a plurality of pixel openings, a plurality of pixel openings K0, and the plurality of pixel openings K0 may include a first pixel opening K01, a second pixel opening K02, and a third pixel opening K03, wherein the orthographic projection of the first pixel opening K01 on the substrate is located within the range of the orthographic projection of the first anode 1001 on the substrate, the orthographic projection of the second pixel opening K02 on the substrate is located within the range of the orthographic projection of the second anode 1002 on the substrate, and the orthographic projection of the third pixel opening K03 on the substrate is located within the range of the orthographic projection of the third anode 1003 on the substrate.

[0327] (118) Forming an encapsulation layer pattern. In an exemplary embodiment, forming the encapsulation layer may include: depositing an encapsulation layer thin film on the substrate on which the aforementioned pattern is formed, and patterning the encapsulation layer thin film using a patterning process to form an encapsulation layer pattern disposed on the pixel definition layer.

[0328] (119) Forming a black matrix layer pattern. In an exemplary embodiment, forming the black matrix layer pattern may include: depositing a black matrix layer film on the substrate on which the aforementioned pattern is formed, patterning the black matrix layer film using a patterning process, and forming a black matrix layer pattern disposed on the encapsulation layer, as shown in FIG6c, FIG6d, FIG6g, and FIG6h. FIG6g and FIG6h are schematic planar structural diagrams of four sub-pixels, and FIG6c and FIG6d are schematic planar diagrams of the pixel definition layer in FIG6h and FIG6g, respectively.

[0329] In an exemplary embodiment, the black matrix layer pattern may include at least a plurality of light-transmitting holes K3 and a plurality of light-transmitting openings K2. The orthographic projections of the plurality of light-transmitting holes K3 on the substrate overlap the orthographic projections of the plurality of pixel openings K0 on the substrate. Typically, the light-transmitting holes K3 are larger than their corresponding pixel openings K0 to avoid blocking the pixel openings. The plurality of light-transmitting openings K2 form a plurality of light-transmitting regions K1 to improve the light transmittance of the display substrate.

[0330] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, the sixth conductive layer, and the seventh conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer, the seventh insulating layer, and the eighth insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first planarizing layer, the second planarizing layer, and the third planarizing layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The anode layer can be made of reflective materials such as metal, and the cathode can be made of transparent conductive materials. However, this embodiment is not limited to this.

[0331] The structure of the display substrate of this embodiment and its preparation process are merely exemplary. In some exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. The preparation process of this exemplary embodiment can be implemented using currently mature preparation equipment and is well compatible with existing preparation processes. The process is simple to implement, easy to implement, with high production efficiency, low production cost, and high yield rate. The display substrate of the embodiment of the present disclosure can be applied to other display devices having pixel driving circuits, such as quantum dot displays, etc., and the present disclosure is not limited thereto.

[0332] The embodiment of the present disclosure further provides a display device, as shown in FIG25 , which may include the display substrate described in any of the above embodiments.

[0333] An embodiment of the present disclosure also provides an electronic device, as shown in Figure 26, which may include a sensor and a display device as described in Figure 25, the display device may include the display substrate described in any of the above embodiments, the sensor may be located on a side of the non-display surface of the display substrate, the display substrate may include a first display area, and the orthographic projection of the sensor on the display substrate at least partially overlaps with the first display area of ​​the display substrate.

[0334] In an exemplary embodiment, as shown in FIG1 , the display substrate may include a first display area A1 and a second display area A2. The second display area A2 may be located on at least one side of the first display area A1. For example, the second display area A2 may be disposed around the first display area A1. In some examples, as shown in FIG1 , the first display area A1 may be a light-transmitting display area, which may also be referred to as a Full Display With Camera (FDC) area; the second display area A2 may be referred to as a normal display area. For example, the orthographic projection of a sensor (e.g., hardware such as a camera) on the display substrate may be located within the first display area A1 of the display substrate. In some examples, as shown in FIG1 , the first display area A1 may be circular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 may be rectangular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the inscribed circle of the first display area A1.

[0335] In an exemplary embodiment, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation device.

[0336] In the display substrate, display device, and electronic device provided by the embodiments of the present disclosure, the orthographic projection of at least one first-type transistor in the display substrate on the substrate at least partially overlaps with the orthographic projection of at least one second-type transistor on the substrate, which can reduce the area of ​​the pixel driving circuit, save space on the display substrate, and improve the transmittance of the display substrate or the PPI of the display substrate.

[0337] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0338] In the absence of conflict, the embodiments of the present disclosure, i.e., features in the embodiments, can be combined with each other to form new embodiments.

[0339] Although the embodiments disclosed in the present disclosure are as described above, the contents are only embodiments adopted to facilitate understanding of the embodiments of the present disclosure and are not intended to limit the embodiments of the present disclosure. Any person skilled in the art in the field to which the embodiments of the present disclosure belong may make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the embodiments of the present disclosure, but the scope of patent protection of the embodiments of the present disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, comprising a substrate and a plurality of sub-pixels arranged on the substrate, at least one sub-pixel comprising a pixel driving circuit, at least one pixel driving circuit comprising a plurality of first-type transistors and a plurality of second-type transistors, and an orthographic projection of at least one of the first-type transistors on the substrate at least partially overlaps with an orthographic projection of at least one of the second-type transistors on the substrate.

2. The display substrate according to claim 1, wherein: The pixel driving circuits of the plurality of sub-pixels form a plurality of rows, a light-transmitting area is provided between two adjacent rows of pixel driving circuits, and there is no overlapping area between the light-transmitting area and the orthographic projection of the pixel driving circuit on the substrate.

3. The display substrate according to claim 2, further comprising a shielding layer, wherein in a direction perpendicular to the plane where the display substrate is located, the shielding layer is located between the base and the pixel driving circuit, the shielding layer is provided with a light-transmitting opening, and the boundary lines of the light-transmitting opening are smoothly connected; Alternatively, the display substrate further comprises a black matrix layer, which is located on a side of the pixel driving circuit away from the base in a direction perpendicular to the plane of the display substrate, and the black matrix layer is provided with a light-transmitting opening, and the boundary lines of the light-transmitting opening are smoothly connected.

4. The display substrate according to claim 3, wherein: An orthographic projection of the light-transmitting opening on the substrate overlaps with an orthographic projection of the light-transmitting area on the substrate.

5. The display substrate according to claim 3, wherein: The shape of the light-transmitting opening is an ellipse or a polygon, and the corners of the polygon are configured as rounded structures.

6. The display substrate according to any one of claims 2 to 4, further comprising an anode conductive layer, wherein the anode conductive layer is located on a side of the pixel driving circuit away from the substrate, the anode conductive layer comprises a plurality of anodes, each sub-pixel comprises at least one anode, the anode and the pixel driving circuit in the same sub-pixel are electrically connected to each other, and there is no overlapping area between the anode and the orthographic projection of the light-transmitting area on the substrate.

7. The display substrate according to claim 6, wherein: The multiple sub-pixels include multiple first sub-pixels, multiple second sub-pixels and multiple third sub-pixels, the anode area of ​​the first sub-pixels and the anode area of ​​the second sub-pixels are both larger than the anode area of ​​the third sub-pixels, and the orthographic projections of the anodes of the first sub-pixels and the second sub-pixels on the substrate are within the range of the orthographic projection of the pixel driving circuit on the substrate.

8. The display substrate according to claim 7, wherein: On a plane parallel to the display substrate, the anodes of the plurality of third sub-pixels are arranged in an array, and in the row direction, the light-transmitting area is located between the anodes of two adjacent columns of third sub-pixels; in the column direction, the anodes of the first sub-pixels and the anodes of the second sub-pixels are alternately arranged, and the light-transmitting area is located between the anodes of the adjacent first sub-pixels and the anodes of the second sub-pixels.

9. The display substrate according to claim 1, wherein: The first type of transistors includes at least a third transistor as a driving transistor, the second type of transistors includes at least a first transistor as a first initialization transistor, the second electrode of the first transistor is electrically connected to the second electrode of the third transistor; the orthographic projection of the first transistor on the substrate at least partially overlaps with the orthographic projection of the third transistor on the substrate.

10. The display substrate according to claim 9, wherein: The orthographic projections of the control electrode and the active layer of the third transistor on the substrate at least partially overlap with the orthographic projections of the control electrode and the active layer of the first transistor on the substrate respectively.

11. The display substrate according to claim 9, wherein: The first type of transistor also includes a sixth transistor serving as a light-emitting transistor, and the second type of transistor also includes a seventh transistor serving as a second initialization transistor, the first electrode of the sixth transistor and the second electrode of the seventh transistor being electrically connected to the second electrode of the third transistor; the orthographic projection of the sixth transistor on the substrate at least partially overlaps with the orthographic projection of the seventh transistor on the substrate.

12. The display substrate according to claim 11, wherein: The orthographic projections of the control electrode and the active layer of the sixth transistor on the substrate at least partially overlap with the orthographic projections of the control electrode and the active layer of the seventh transistor on the substrate respectively.

13. The display substrate according to claim 11, wherein: The first type of transistors further includes a fourth transistor as a data writing transistor and a fifth transistor as a light emitting transistor, the second type of transistors further includes a second transistor as a compensation transistor and an eighth transistor as a third initialization transistor, the second electrode of the fourth transistor, the second electrode of the fifth transistor and the second electrode of the eighth transistor are all electrically connected to the first electrode of the third transistor, the first electrode of the second transistor is electrically connected to the control electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the second electrode of the third transistor; On a plane parallel to the display substrate, in a first direction, the fourth transistor and the fifth transistor are located on one side of the first transistor and the third transistor, the second transistor, the sixth transistor and the seventh transistor are located on the other side of the third transistor and the first transistor, and the eighth transistor is located between the fifth transistor and the seventh transistor; in a second direction, the fourth transistor and the second transistor are located on one side of the third transistor, and the fifth transistor to the eighth transistor are located on the other side of the third transistor, and the first direction intersects with the second direction.

14. The display substrate according to claim 13, wherein: An orthographic projection of the active layer of the second transistor on the substrate at least partially overlaps with an orthographic projection of the active layer of the sixth transistor on the substrate.

15. The display substrate according to claim 13, further comprising a driving circuit layer, wherein the driving circuit layer is provided with pixel driving circuits of the plurality of sub-pixels, wherein the pixel driving circuit further comprises a storage capacitor, and in a direction perpendicular to the plane where the display substrate is located, the driving circuit layer comprises a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a second semiconductor layer, and a fourth conductive layer sequentially arranged on the substrate; The first semiconductor layer at least comprises: an active layer of the first type of transistor; The first conductive layer includes at least: the control electrode of the first type of transistor and the first plate of the storage capacitor; the second conductive layer includes at least: the second plate of the storage capacitor; the third conductive layer includes at least: the shielding layer of the second type of transistor; the second semiconductor layer includes at least: the active layer of the second type of transistor; the fourth conductive layer includes at least: the control electrode of the second type of transistor.

16. The display substrate according to claim 15, wherein: The driving circuit layer further includes a fifth conductive layer, the fifth conductive layer is located on a side of the fourth conductive layer away from the second semiconductor layer, and the fifth conductive layer at least includes: a first electrode and a second electrode of the first type transistor and the second type transistor; The orthographic projections of the first electrode plate and the second electrode plate on the substrate at least partially overlap with the orthographic projection of the third transistor on the substrate. On a plane parallel to the display substrate, in the second direction, a connecting structure is provided on a side of the first electrode plate close to the second transistor, and the orthographic projection of the connecting structure on the substrate does not at least partially overlap with the orthographic projections of the storage capacitor and the third transistor on the substrate. The first electrode of the second transistor is electrically connected to the connecting structure through a via, and there is no overlapping area between the orthographic projection of the second transistor on the substrate and the orthographic projection of the storage capacitor on the substrate.

17. The display substrate according to claim 16, wherein: The pixel driving circuits of the plurality of sub-pixels form a plurality of columns, the driving circuit layer further comprises a sixth conductive layer and a seventh conductive layer, in a direction perpendicular to the plane where the display substrate is located, the sixth conductive layer is located on a side of the fifth conductive layer away from the fourth conductive layer, the seventh conductive layer is located on a side of the sixth conductive layer away from the fifth conductive layer, the sixth conductive layer at least comprises: a data signal line, the data signal line is electrically connected to a first electrode of a fourth transistor in one column of the pixel driving circuit; the seventh conductive layer at least comprises: a first power line, the first power line is electrically connected to a first electrode of a fifth transistor in two adjacent columns of the pixel driving circuit and a second plate of a storage capacitor; On a plane parallel to the display substrate, the data signal lines and the first power lines extend along the second direction and are arranged at intervals along the first direction, and the data signal lines of two adjacent columns of pixel driving circuits are located adjacent to the two adjacent columns. The column pixel driving circuits are electrically connected to both sides of the first power line; two adjacent columns of pixel driving circuits are symmetrically arranged along a second center line, and the second center line is a center line of two adjacent columns of pixel driving circuits extending along a second direction.

18. The display substrate according to claim 17, wherein: The sixth conductive layer further includes a shielding electrode, and the seventh conductive layer further includes a first power connection line and a second power connection line; On a plane parallel to the display substrate, the first power connection line extends along the second direction, the second power connection line extends along the first direction, and each second power connection line is connected to at least part of the first power connection line; in the first direction, the shielding electrode and the first power connection line are located between two adjacent data signal lines; in the second direction, the first power connection line is located between two adjacent second power connection lines, and two ends of the first power connection line are respectively connected to two adjacent second power connection lines; The orthographic projection of the shielding electrode on the substrate covers the orthographic projection of the connecting structure on the substrate; the first power connection line at least partially overlaps with the orthographic projection of the shielding electrode on the substrate, and the first power connection line is electrically connected to the shielding electrode through a via.

19. The display substrate according to claim 1, wherein: At least a portion of the structure of the first type of transistor and at least a portion of the structure of the second type of transistor are located in different conductive layers, and the orthographic projections of at least a portion of the structure of at least one of the first type of transistor and at least a portion of the structure of at least one of the second type of transistor on the substrate at least partially overlap, and the partial structure includes one or more of the control electrode and the active layer of the transistor.

20. A display substrate, comprising a substrate and a plurality of sub-pixels, a plurality of data signal lines, and a plurality of first power lines disposed on the substrate, wherein on a plane parallel to the display substrate, the plurality of data signal lines and the plurality of first power lines extend along a second direction and are arranged at intervals along a first direction, and the first direction intersects with the second direction; At least some of the sub-pixels include pixel driving circuits, the pixel driving circuits of multiple sub-pixels form multiple columns, each data signal line is electrically connected to at least some of the pixel driving circuits in one column, each first power line is electrically connected to at least some of the pixel driving circuits in at least one column of pixel driving circuits, and in the first direction, two adjacent data signal lines are located on both sides of the first power line.

21. The display substrate according to claim 20, wherein: Each first power line is electrically connected to two adjacent columns of pixel driving circuits, and the two adjacent columns of pixel driving circuits are symmetrically arranged along a second center line, and the second center line is a center line of the two adjacent columns of pixel driving circuits extending along the second direction.

22. The display substrate according to claim 21, wherein: The pixel driving circuit further includes a shielding electrode. In the first direction, the shielding electrode is disposed between two adjacent data signal lines. In the same column of pixel driving circuits, the data signal line is located between the shielding electrode and the first power line.

23. The display substrate according to claim 22, further comprising a first power connection line and a second power connection line, wherein on a plane parallel to the display substrate, the first power connection line extends along the second direction, the second power connection line extends along the first direction, and each second power connection line is connected to at least part of the first power line; In the first direction, the first power connection line is located between two adjacent data signal lines; in the second direction, the first power connection line is located between two adjacent second power connection lines, and both ends of the first power connection line are respectively connected to the two adjacent second power connection lines; The shielding electrode and the data signal line are located in the same conductive layer, the first power line, the first power connection line and the second power connection line are located in the same conductive layer, and the data signal line and the first power line are located in different conductive layers; the first power connection line and the shielding electrode are at least partially overlapped in their orthographic projections on the substrate, and the first power line is electrically connected to the shielding electrode through a via.

24. A display device comprising a display substrate, wherein the display substrate is the display substrate according to any one of claims 1 to 19, or the display substrate is the display substrate according to any one of claims 20 to 23.

25. An electronic device comprising a sensor and a display device as claimed in claim 24, wherein the display device comprises a display substrate, the sensor is located on a side of a non-display surface of the display substrate, the display substrate comprises a first display area, and the orthographic projection of the sensor on the display substrate at least partially overlaps with the first display area of ​​the display substrate.

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