Electro-optical device and electronic apparatus

Abstract

The invention provides an electro-optical device and an electronic apparatus capable of reducing delay of an image signal. An electro-optical device includes a plurality of video signal lines and a plurality of lead-in video signal lines traversing a data line driving circuit. The lead-in video signal lines include a first lead-in video signal line having a shortest first wiring length and a second lead-in video signal line having a longest second wiring length. The image signal lines include a first image signal line electrically connected to the first lead-in image signal line and a second image signal line electrically connected to the second lead-in image signal line. A length from the first connection point to one end of the first video signal line is a third wiring length. A length from the first connection point to the other end of the first video signal line is a fourth wiring length. The length from the second connection point to one end of the second video signal line is a fifth wiring length. The length from the second connection point to the other end of the second video signal line is a sixth wiring length. The longest one of the fifth wiring length and the sixth wiring length is shorter than the longest one of the third wiring length and the fourth wiring length.

Description

Technical Field

[0001] The present invention relates to an electro-optical device and an electronic device. Background Art

[0002] Conventionally, as one of the driving methods for achieving high-speed driving of a liquid crystal panel, a phase unfolding driving method is known. A liquid crystal panel driven by the phase unfolding driving method is disclosed in Patent Document 1. In addition, the phase unfolding driving method is sometimes also referred to as a block sequential driving method.

[0003] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2016-99492

[0004] In the liquid crystal panel disclosed in Patent Document 1, on the element substrate, a group of image signal lines extending from an image signal terminal group is arranged so as to bypass a data line driving circuit. According to such a wiring layout, since the propagation path of the image signal in the liquid crystal panel becomes longer, a delay of the image signal occurs. The delay of the image signal hinders the high-speed driving of the liquid crystal panel. Summary of the Invention

[0005] An electro-optical device according to one aspect of the present invention includes: a plurality of scan lines extending in a first direction; a plurality of data lines extending in a second direction intersecting the first direction; pixels correspondingly arranged at respective positions where the plurality of scan lines and the plurality of data lines intersect in a display area; a data line driving circuit arranged at a position separated from one end side in the second direction from the display area; a plurality of image signal lines arranged between the display area and the data line driving circuit and extending in the first direction; and a plurality of lead-in image signal lines extending in the second direction and electrically connected to the plurality of image signal lines one by one. When viewed from above, the plurality of lead-in image signal lines cross the data line driving circuit. The plurality of lead-in image signal lines include: a first lead-in image signal line having a shortest first wiring length; and a second lead-in image signal line having a longest second wiring length. The plurality of image signal lines include: a first image signal line electrically connected to the first lead-in image signal line at a first connection point; and a second image signal line electrically connected to the second lead-in image signal line at a second connection point. The length from the first connection point to one end of the first image signal line is a third wiring length, the length from the first connection point to the other end of the first image signal line is a fourth wiring length, the length from the second connection point to one end of the second image signal line is a fifth wiring length, and the length from the second connection point to the other end of the second image signal line is a sixth wiring length. The longest wiring length among the fifth wiring length and the sixth wiring length is shorter than the longest wiring length among the third wiring length and the fourth wiring length.

[0006] An electronic device according to one embodiment of the present invention includes the electro-optical device according to the above embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. is a plan view schematically showing the structure of the liquid crystal panel in the present embodiment.

[0008] Figure 2 is along Figure 1 sectional view taken along line H-H' of.

[0009] Figure 3 FIG. is a plan view showing the circuit structure of the element substrate.

[0010] Figure 4 is to Figure 3 part of the enlarged view of.

[0011] Figure 5 is from Figure 4 FIG. shows a pair of image signal lines A1 and the introduced image signal line B1, and a pair of image signal lines A12 and the introduced image signal line B12.

[0012] Figure 6 FIG. shows a first example of the wiring pattern of the introduced image signal line.

[0013] Figure 7 FIG. shows a second example of the wiring pattern of the introduced image signal line.

[0014] Figure 8 FIG. shows a third example of the wiring pattern of the introduced image signal line.

[0015] Figure 9 FIG. shows a fourth example of the wiring pattern of the introduced image signal line.

[0016] Figure 10 FIG. is a plan view showing the wiring layout of the comparative example.

[0017] Figure 11 FIG. schematically shows the delay time of the image signal in the present embodiment and the delay time of the image signal in the comparative example.

[0018] Figure 12 FIG. is an explanatory view showing the schematic structure of the projector.

[0019] Figure 13 FIG. shows a first modification of the liquid crystal panel.

[0020] Figure 14 FIG. shows a second modification of the liquid crystal panel.

[0021] Figure 15This is a diagram showing a third modified example of a liquid crystal panel.

[0022] Reference numeral description

[0023] 10: Liquid crystal panel; 11: Element substrate; 12: Counter substrate; 13: Sealant; 14: Liquid crystal layer; 21: External connection terminal; 31: Scan line; 32: Data line; 33: First scan line driver circuit; 34: Second scan line driver circuit; 35: Data line driver circuit; 36: Precharge circuit; 37: Switch array circuit; 38: Image signal line group; 39: Lead-in image signal line group; A1 to A12: Image signal lines; B1 to B12: Lead-in image signal lines; 25: Image signal terminal group; E: Display area; P: Pixel. Detailed implementation

[0024] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Here, in the following figures, in order to make components, wirings, circuits, etc. distinguishable, these scales may sometimes be different from the actual ones. In addition, in the following figures, as needed, the XYZ axes are marked as mutually orthogonal coordinate axes. In each figure, the direction indicated by each arrow along the axis is set as the + direction, and the direction opposite to the + direction is set as the - direction.

[0025] 1. Electro-optical device

[0026] First, refer to Figure 1 and Figure 2 to describe the schematic structure of the liquid crystal panel 10 in this embodiment. The liquid crystal panel 10 is an example of an electro-optical device. Figure 1 This is a top view showing the schematic structure of the liquid crystal panel 10. Figure 2 This is a cross-sectional view along the Figure 1 H-H' line. In addition, in the following description, "top view" means observing the liquid crystal panel 10 from the +Z direction.

[0027] For example, the liquid crystal panel 10 is an active drive type liquid crystal panel having pixel switching elements such as TFTs (Thin Film Transistors) for each pixel P. In addition, the liquid crystal panel 10 is driven in a phase unfolding drive method. Such a liquid crystal panel 10 can be suitably used as a light modulation device in electronic devices such as projectors.

[0028] The liquid crystal panel 10 includes a device substrate 11, a counter substrate 12, a sealant 13, and a liquid crystal layer 14. The device substrate 11 and the counter substrate 12 both have a rectangular shape when viewed from above. The device substrate 11 and the counter substrate 12 are bonded to each other in a facing manner via the sealant 13. The sealant 13 is provided in a frame shape along the outer edge of the counter substrate 12. The sealant 13 is an adhesive made of a photocurable resin, a thermosetting resin, or the like, and contains a gap material such as glass fibers or glass beads for making the gap between the device substrate 11 and the counter substrate 12 a specified value.

[0029] The liquid crystal layer 14 is disposed in the region sandwiched by the device substrate 11 and the counter substrate 12 and surrounded by the sealant 13. The liquid crystal layer 14 is formed of, for example, a liquid crystal having negative dielectric anisotropy. For example, the liquid crystal layer 14 is formed by the liquid crystal droplet discharge method of discharging liquid crystal. That is, in the liquid crystal panel 10 of the present embodiment, there is no liquid crystal inlet for enclosing liquid crystal. A display region E having a rectangular shape when viewed from above is disposed in the region surrounded by the sealant 13. The display region E includes a plurality of pixels P arranged in a matrix.

[0030] The device substrate 11 includes a light-transmissive pixel electrode 15 provided for each pixel P, a pixel switching element (not shown) disposed corresponding to the pixel electrode 15, and a first alignment film 16 disposed to cover the pixel electrode 15. The counter substrate 12 includes a partition portion 17, a common electrode 18, and a second alignment film 19 disposed to cover the common electrode 18.

[0031] The pixel electrode 15 and the common electrode 18 are formed of a transparent conductive material such as ITO (Indium Tin Oxide), for example. The device substrate 11 and the counter substrate 12 are substrates having light-transmissivity, and a glass substrate or a quartz substrate is used, for example. The first alignment film 16 and the second alignment film 19 are formed of an inorganic material such as silicon oxide.

[0032] In Figure 1 The partition portion 17 indicated by dots is a light-shielding film formed so as to surround the display region E when viewed from above. Although not shown in Figure 1 and Figure 2 The device substrate 11 includes a peripheral circuit disposed in the region between the display region E and the sealant 13. That is, the partition portion 17 is disposed so as to overlap the peripheral circuit when viewed from above, and prevents the light L incident from the outside of the liquid crystal panel 10 to the counter substrate 12 from irradiating the peripheral circuit. Thereby, it is possible to prevent the peripheral circuit from malfunctioning due to the light L.

[0033] Four inter-substrate conduction portions 20 for obtaining electrical conduction between the component substrate 11 and the counter substrate 12 are arranged corresponding to the four corners of the counter substrate 12. The four inter-substrate conduction portions 20 are electrically connected to the common electrode 18 disposed on the counter substrate 12. On the surface of the portion of the component substrate 11 that protrudes in the -Y direction from the counter substrate 12, a plurality of external connection terminals 21 are arranged at fixed intervals along the X axis. As will be described later, two of the plurality of external connection terminals 21 are electrically connected to the common electrode 18 via the inter-substrate conduction portion 20.

[0034] The above is the description of the schematic structure of the liquid crystal panel 10. Hereinafter, with reference to Figure 3 and Figure 4 the circuit structure of the component substrate 11 will be described in detail. In the following description, the +X direction may sometimes be referred to as left or the left side, and the -X direction may sometimes be referred to as right or the right side. In addition, the +Y direction may sometimes be referred to as down or the lower side, and the -Y direction may sometimes be referred to as up or the upper side. The X axis is an example of an axis along the first direction. The Y axis is an example of an axis along the second direction intersecting the first direction. The upper side is an example of one end side of the axis along the second direction.

[0035] Figure 3 is a top view showing the circuit structure of the component substrate 11. Figure 4 is to Figure 3 a partially enlarged view of. As Figure 3 shown, the component substrate 11 includes a plurality of scanning lines 31, a plurality of data lines 32, a first scanning line driving circuit 33, a second scanning line driving circuit 34, a data line driving circuit 35, a precharge circuit 36, a switch array circuit 37, an image signal line group 38, an introduced image signal line group 39, a first level shifter group 40, a second level shifter group 41, and an inspection circuit 42.

[0036] In addition, in Figure 3 letters and notations are used to represent the signals and potentials input from a control device (not shown) for controlling the liquid crystal panel 10 to the external connection terminals 21, and the signals output from the external connection terminals 21 to the control device.

[0037] For example, a first common potential LCCOM supplied to the common electrode 18 is input to the external connection terminal 21 located at the leftmost side and the external connection terminal 21 located at the rightmost side among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 to which the first common potential LCCOM is input from the control device is referred to as the "LCCOM terminal". Although not shown in Figure 3 these two LCCOM terminals are electrically connected to the common electrode 18 via the four inter-substrate conduction portions 20.

[0038] The first low potential VSSY supplied to the first scan line driving circuit 33 and the second scan line driving circuit 34 is input to the second external connection terminal 21 from the left among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 that inputs the first low potential VSSY from the control device is referred to as the "VSSY terminal".

[0039] The first high potential VDDY supplied to the first scan line driving circuit 33 and the second scan line driving circuit 34 is input to the third external connection terminal 21 from the left among the plurality of external connection terminals 21. The first high potential VDDY is a potential higher than the first low potential VSSY. In the following description, the external connection terminal 21 that inputs the first high potential VDDY from the control device is referred to as the "VDDY terminal".

[0040] The precharge control signal PCG supplied to the precharge circuit 36 is input to the fourth external connection terminal 21 from the left among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 that inputs the precharge control signal PCG from the control device is referred to as the "PCG terminal".

[0041] The first start pulse signal DY supplied to the first scan line driving circuit 33 and the second scan line driving circuit 34 is input to the fifth external connection terminal 21 from the left among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 that inputs the first start pulse signal DY from the control device is referred to as the "DY terminal".

[0042] The first shift control signal DIRY supplied to the first scan line driving circuit 33 and the second scan line driving circuit 34 is input to the sixth external connection terminal 21 from the left among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 that inputs the first shift control signal DIRY from the control device is referred to as the "DIRY terminal".

[0043] The first clock signal CLY supplied to the first scan line driving circuit 33 and the second scan line driving circuit 34 is input to the seventh external connection terminal 21 from the left among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 that inputs the first clock signal CLY from the control device is referred to as the "CLY terminal".

[0044] The first inverted clock signal CLYB supplied to the first scan line driving circuit 33 and the second scan line driving circuit 34 is input to the eighth external connection terminal 21 from the left among the plurality of external connection terminals 21. The first inverted clock signal CLYB is an inverted signal of the first clock signal CLY. In the following description, the external connection terminal 21 that inputs the first inverted clock signal CLYB from the control device is referred to as the "CLYB terminal".

[0045] An enable signal ENBY supplied to the first scan line driving circuit 33 and the second scan line driving circuit 34 is input to the ninth external connection terminal 21 from the left among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 to which the enable signal ENBY is input from the control device is referred to as the "ENBY terminal".

[0046] The tenth external connection terminal 21 from the left among the plurality of external connection terminals 21 is an output terminal for outputting an inspection result signal TESTO. The inspection result signal TESTO is a signal output from an inspection circuit 42 described later. The inspection result signal TESTO is, for example, a signal for determining an abnormal operation of the first level shifter group 40 and the second level shifter group 41. In the following description, the external connection terminal 21 that outputs the inspection result signal TESTO is referred to as the "TESTO terminal".

[0047] A mode switching signal MODE supplied to the inspection circuit 42 is input to the eleventh external connection terminal 21 from the left among the plurality of external connection terminals 21. The mode switching signal MODE is, for example, a signal for switching the inspection object, and selects the first level shifter group 40 or the second level shifter group 41 as the object for abnormality determination. In the following description, the external connection terminal 21 to which the mode switching signal MODE is input is referred to as the "MODE terminal".

[0048] A second start pulse signal DX supplied to the data line driving circuit 35 is input to the twelfth external connection terminal 21 from the left among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 to which the second start pulse signal DX is input from the control device is referred to as the "DX terminal".

[0049] A second shift control signal DIRX supplied to the data line driving circuit 35 is input to the thirteenth external connection terminal 21 from the left among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 to which the second shift control signal DIRX is input from the control device is referred to as the "DIRX terminal".

[0050] A second clock signal CLX supplied to the data line driving circuit 35 is input to the fourteenth external connection terminal 21 from the left among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 to which the second clock signal CLX is input from the control device is referred to as the "CLX terminal".

[0051] The second inverted clock signal CLXB supplied to the data line driver circuit 35 is input to the fifteenth external connection terminal 21 from the left among the plurality of external connection terminals 21. The second inverted clock signal CLXB is an inverted signal of the second clock signal CLX. In the following description, the external connection terminal 21 to which the second inverted clock signal CLXB is input from the control device is referred to as the "CLXB terminal".

[0052] The second enable signal ENBX2 supplied to the data line driver circuit 35 is input to the sixteenth external connection terminal 21 from the left among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 to which the second enable signal ENBX2 is input from the control device is referred to as the "ENBX2 terminal".

[0053] The first enable signal ENBX1 supplied to the data line driver circuit 35 is input to the seventeenth external connection terminal 21 from the left among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 to which the first enable signal ENBX1 is input from the control device is referred to as the "ENBX1 terminal".

[0054] The second low potential VSSX supplied to the data line driver circuit 35 is input to the eighteenth external connection terminal 21 from the left among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 to which the second low potential VSSX is input from the control device is referred to as the "VSSX terminal".

[0055] The second high potential VDDX supplied to the data line driver circuit 35 is input to the nineteenth external connection terminal 21 from the left among the plurality of external connection terminals 21. The second high potential VDDX is a potential higher than the second low potential VSSX. In the following description, the external connection terminal 21 to which the second high potential VDDX is input from the control device is referred to as the "VDDX terminal".

[0056] The precharge potential VPCG supplied to the precharge circuit 36 is input to the second external connection terminal 21 from the right among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 to which the precharge potential VPCG is input from the control device is referred to as the "VPCG terminal".

[0057] The second common potential VCOM supplied to one electrode of the auxiliary capacitor for each pixel P is input to the third external connection terminal 21 from the right among the plurality of external connection terminals 21. The second common potential VCOM may be the same potential as the first common potential LCCOM or may be a potential different from the first common potential LCCOM. In the following description, the external connection terminal 21 to which the second common potential VCOM is input from the control device is referred to as the "VCOM terminal". The VCOM terminal is electrically connected to one electrode of the auxiliary capacitor for each pixel P via a wiring (not shown).

[0058] The first-phase video signal VID1 is input to the fourth external connection terminal 21 from the right among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 to which the video signal VID1 is input from the control device is referred to as the "VID1 terminal".

[0059] The second-phase video signal VID2 is input to the fifth external connection terminal 21 from the right among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 to which the video signal VID2 is input from the control device is referred to as the "VID2 terminal".

[0060] The third-phase video signal VID3 is input to the sixth external connection terminal 21 from the right among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 to which the video signal VID3 is input from the control device is referred to as the "VID3 terminal".

[0061] The fourth-phase video signal VIID4 is input to the seventh external connection terminal 21 from the right among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 to which the video signal VID4 is input from the control device is referred to as the "VID4 terminal".

[0062] The fifth-phase video signal VID5 is input to the eighth external connection terminal 21 from the right among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 to which the video signal VID5 is input from the control device is referred to as the "VID5 terminal".

[0063] The sixth-phase video signal VID6 is input to the ninth external connection terminal 21 from the right among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 to which the video signal VID6 is input from the control device is referred to as the "VID6 terminal".

[0064] The seventh-phase video signal VID7 is input to the tenth external connection terminal 21 from the right among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 to which the video signal VID7 is input from the control device is referred to as the "VID7 terminal".

[0065] The image signal VID8 of the eighth phase is input to the eleventh external connection terminal 21 from the right among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 that inputs the image signal VID8 from the control device is referred to as the "VID8 terminal".

[0066] The image signal VID9 of the ninth phase is input to the twelfth external connection terminal 21 from the right among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 that inputs the image signal VID9 from the control device is referred to as the "VID9 terminal".

[0067] The image signal VID10 of the tenth phase is input to the thirteenth external connection terminal 21 from the right among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 that inputs the image signal VID10 from the control device is referred to as the "VID10 terminal".

[0068] The image signal VID11 of the eleventh phase is input to the fourteenth external connection terminal 21 from the right among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 that inputs the image signal VID11 from the control device is referred to as the "VID11 terminal".

[0069] The image signal VID12 of the twelfth phase is input to the fifteenth external connection terminal 21 from the right among the plurality of external connection terminals 21. In the following description, the external connection terminal 21 that inputs the image signal VID12 from the control device is referred to as the "VID12 terminal".

[0070] As described above, the liquid crystal panel 10 of the present embodiment is driven by a 12-phase phase-expanded driving method. In the following description, the terminal group including 12 external connection terminals 21 from the VID1 terminal to the VID12 terminal is referred to as the "video signal terminal group 25". The center of the video signal terminal group 25 is located at a position shifted to the right from the display center line CL. In addition, for the sake of explanation, the VID12 terminal in the video signal terminal group 25 is located near the display center line CL. A modification example of this offset amount will be described later. The display center line CL is a line that passes through the center of the display area E and extends along the Y-axis. In addition, for the sake of explanation, the liquid crystal panel 10 of the present embodiment is a 12-phase phase-expanded driving method. In an actual liquid crystal panel 10, for example, it is a 48-phase phase-expanded driving method, and the video signal terminal group 25 is composed of 48 external connection terminals 21. The control circuit of the liquid crystal panel 10 is, for example, an integrated circuit with a single-chip structure, and supplies the video signals VID1 to VID12 and various driving signals to the liquid crystal panel 10. The video signals VID1 to VID12 are analog voltage signals, and the other driving signals are digital signals. In the integrated circuit that is the control circuit of the liquid crystal panel 10, the analog signal generation unit and the digital signal generation unit are mostly separated and arranged in view of noise countermeasures and layout efficiency. As a result, the output terminals of the video signals VID1 to VID12 in the integrated circuit are arranged in a block, and as a result, the video signal terminal group 25 in the liquid crystal panel 10 is arranged to be offset to one side with respect to the display center line CL.

[0071] A plurality of scan lines 31 extend along the X-axis and traverse the display area E along the X-axis. The plurality of scan lines 31 are arranged at fixed intervals along the Y-axis. A plurality of data lines 32 extend along the Y-axis and traverse the display area E along the Y-axis. The plurality of data lines 32 are arranged at fixed intervals along the X-axis. In the display area E, pixels P are arranged corresponding to the respective positions where the plurality of scan lines 31 and the plurality of data lines 32 intersect.

[0072] Although not shown in Figure 3 for the sake of simplicity, the gate of the pixel switching element disposed in the pixel P is electrically connected to the scan line 31 corresponding to the pixel P. The source of the pixel switching element disposed in the pixel P is electrically connected to the data line 32 corresponding to the pixel P. In addition, the drain of the pixel switching element disposed in the pixel P is electrically connected to the pixel electrode 15 disposed in the pixel P.

[0073] The first scan line driving circuit 33 is disposed on the left side of the display area E and extends along the Y-axis. The second scan line driving circuit 34 is disposed on the right side of the display area E and extends along the Y-axis. The first scan line driving circuit 33 is electrically connected to one end of each scan line 31. The second scan line driving circuit 34 is electrically connected to the other end of each scan line 31.

[0074] The first scan line driver circuit 33 and the second scan line driver circuit 34 are electrically connected to the DY terminal, the DIRY terminal, the CLY terminal, the CLYB terminal, and the ENBY terminal via the first level shifter group 40, respectively. In addition, the first scan line driver circuit 33 and the second scan line driver circuit 34 are electrically connected to the VDDY terminal and the VSSY terminal via wirings (not shown).

[0075] The first level shifter group 40 includes six level shifters represented by the symbol "L / S". The first start pulse signal DY input to the DY terminal, the first shift control signal DIRY input to the DIRY terminal, the first clock signal CLY input to the CLY terminal, the first inverted clock signal CLYB input to the CLYB terminal, and the enable signal ENBY input to the ENBY terminal are supplied to the first scan line driver circuit 33 and the second scan line driver circuit 34 via the level shifters corresponding to the respective terminals. In the first level shifter group 40, for example, buffer circuits commensurate with the driving loads of the respective signal lines may also be included. Further, in the case of a clock signal, for example, a phase difference correction circuit may also be included. As described above, due to the offset arrangement of the image signal terminal group 25, the input signal terminal group for the first level shifter group 40 is offset in the direction opposite to the offset direction of the image signal terminal group 25 with respect to the display center line CL. In this way, the outer dimensions of the liquid crystal panel 10 can be formed compactly.

[0076] Via the level shifters corresponding to the DY terminal, the DIRY terminal, the CLY terminal, the CLYB terminal, and the ENBY terminal respectively, the voltage levels of the first start pulse signal DY, the first shift control signal DIRY, the first clock signal CLY, the first inverted clock signal CLYB, and the enable signal ENBY are adjusted to values suitable for the first scan line driver circuit 33 and the second scan line driver circuit 34.

[0077] The first high potential VDDY and the first low potential VSSY are supplied to the first scan line driver circuit 33 and the second scan line driver circuit 34 via the VDDY terminal and the VSSY terminal. The first scan line driver circuit 33 and the second scan line driver circuit 34 use the potential difference between the first high potential VDDY and the first low potential VSSY as the power supply voltage.

[0078] Although in Figure 3The illustration is omitted, but the first scan line driving circuit 33 and the second scan line driving circuit 34 include a first shift register circuit, a first waveform shaping circuit, and a first buffer circuit. The first shift register circuit starts a transfer operation synchronously with the first start pulse signal DY. The shift direction of the first shift register circuit is controlled by the first shift control signal DIRY. The first clock signal CLY and the first inverted clock signal CLYB are used as clock signals for the first shift register circuit.

[0079] The first shift register circuit includes a plurality of flip-flops corresponding one-to-one to a plurality of scan lines 31. The first waveform shaping circuit includes a plurality of AND circuits corresponding one-to-one to the plurality of scan lines 31. The enable signal ENBY is input to each AND circuit included in the first waveform shaping circuit. For example, the output signal of the flip-flop corresponding to the scan line 31(i) is input to the AND circuit corresponding to the scan line 31(i). In addition, the scan line 31(i) refers to the i-th scan line 31 from the bottom among the plurality of scan lines 31. i is an integer from 1 to N. N is the total number of scan lines 31.

[0080] The AND circuit corresponding to the scan line 31(i) outputs, as a scan signal supplied to the scan line 31(i), a signal representing the logical product of the output signal of the flip-flop corresponding to the scan line 31(i) and the enable signal ENBY. The scan signal output from the AND circuit corresponding to the scan line 31(i) is buffered by the first buffer circuit and then supplied to the scan line 31(i).

[0081] The precharge circuit 36 is disposed below the display area E and extends along the X axis. The precharge circuit 36 is electrically connected to one end of each data line 32. The precharge circuit 36 is electrically connected to the PCG terminal via a level shifter included in the first level shifter group 40. In addition, the precharge circuit 36 is electrically connected to the VPCG terminal via a wiring (not shown).

[0082] The precharge control signal PCG input to the PCG terminal is supplied to the precharge circuit 36 via the level shifter corresponding to the PCG terminal. The voltage level of the precharge control signal PCG is adjusted to a value suitable for the precharge circuit 36 by the level shifter corresponding to the PCG terminal. The precharge potential VPCG is supplied to the precharge circuit 36 via the VPCG terminal.

[0083] Although the illustration is omitted in Figure 3 the precharge circuit 36 includes a plurality of switching elements corresponding one-to-one to the plurality of data lines 32. Each switching element included in the precharge circuit 36 is controlled by the precharge control signal PCG. When each switching element included in the precharge circuit 36 is controlled by the precharge control signal PCG to be in the on state, the precharge potential VPCG is supplied to each data line 32.

[0084] The switch array circuit 37 is disposed above the display area E and extends along the X axis. The image signal line group 38 is disposed above the switch array circuit 37 and extends along the X axis. The data line driving circuit 35 is disposed above the image signal line group 38 and extends along the X axis. In other words, the data line driving circuit 35 is disposed at a position separated upward from the display area E. Thus, these circuit elements are arranged in the order of the switch array circuit 37, the image signal line group 38, the data line driving circuit 35, and the image signal terminal group 25 from the display area E upward.

[0085] The image signal line group 38 is electrically connected to the image signal terminal group 25 via the leading-in image signal line group 39. As Figure 4 shown, the image signal line group 38 is disposed between the display area E and the data line driving circuit 35 and includes 12 image signal lines A1 to A12 extending along the X axis. More specifically, the image signal line group 38 is typically disposed between the switch array circuit 37 and the data line driving circuit 35. The image signal lines A1 to A12 are arranged at fixed intervals along the Y axis. In addition, the image signal lines A1 to A12 typically extend corresponding to the width of the display area E in the X direction.

[0086] The leading-in image signal line group 39 includes 12 leading-in image signal lines B1 to B12 extending along the Y axis and electrically connected to the 12 image signal lines A1 to A12 one-to-one. The leading-in image signal lines B1 to B12 are arranged at fixed intervals along the X axis, for example. When viewed from above, the leading-in image signal lines B1 to B12 cross the data line driving circuit 35. That is, in the element substrate 11, at least the data line driving circuit 35 and the image signal line group 38 are formed in a layer different from the layer in which the leading-in image signal line group 39 is formed. For example, the wiring layer in which the leading-in image signal line group 39 is formed is formed mainly of aluminum. And it is disposed on an insulating layer that is laminated on the gate electrode, source electrode, drain electrode of the transistor constituting the data line driving circuit 35 and the wiring layer constituting the image signal line group 38. Due to such a structure, the leading-in image signal lines B1 to B12 can cross the data line driving circuit 35 when viewed from above.

[0087] Among the image signal lines A1 to A12, the topmost image signal line A1, that is, the image signal line A1 closest to the data line driving circuit 35, is electrically connected to the VID1 terminal via the introduced image signal line B1. The VID1 terminal is the rightmost image signal terminal among the image signal terminals included in the image signal terminal group 25. In other words, the VID1 terminal is the image signal terminal with the largest offset amount among the image signal terminals located at positions offset to the right from the display center line CL. The image signal VID1 input to the VID1 terminal is supplied to the image signal line A1 via the introduced image signal line B1.

[0088] Among the image signal lines A1 to A12, the second image signal line A2 from the top is electrically connected to the VID2 terminal via the introduced image signal line B2. The VID2 terminal is the second image signal terminal from the right among the image signal terminals included in the image signal terminal group 25. The image signal VID2 input to the VID2 terminal is supplied to the image signal line A2 via the introduced image signal line B2.

[0089] Among the image signal lines A1 to A12, the third image signal line A3 from the top is electrically connected to the VID3 terminal via the introduced image signal line B3. The VID3 terminal is the third image signal terminal from the right among the image signal terminals included in the image signal terminal group 25. The image signal VID3 input to the VID3 terminal is supplied to the image signal line A3 via the introduced image signal line B3.

[0090] Among the image signal lines A1 to A12, the fourth image signal line A4 from the top is electrically connected to the VID4 terminal via the introduced image signal line B4. The VID4 terminal is the fourth image signal terminal from the right among the image signal terminals included in the image signal terminal group 25. The image signal VID4 input to the VID4 terminal is supplied to the image signal line A4 via the introduced image signal line B4.

[0091] Among the image signal lines A1 to A12, the fifth image signal line A5 from the top is electrically connected to the VID5 terminal via the introduced image signal line B5. The VID5 terminal is the fifth image signal terminal from the right among the image signal terminals included in the image signal terminal group 25. The image signal VID5 input to the VID5 terminal is supplied to the image signal line A2 via the introduced image signal line B5.

[0092] Among the image signal lines A1 to A12, the sixth image signal line A6 from the top is electrically connected to the VID6 terminal via the introduced image signal line B6. The VID6 terminal is the sixth image signal terminal from the right among the image signal terminals included in the image signal terminal group 25. The image signal VID6 input to the VID6 terminal is supplied to the image signal line A6 via the introduced image signal line B6.

[0093] The seventh image signal line A7 from the top among the image signal lines A1 to A12 is electrically connected to the VID7 terminal via the introduced image signal line B7. The VID7 terminal is the seventh image signal terminal from the right among the image signal terminals included in the image signal terminal group 25. The image signal VID7 input to the VID7 terminal is supplied to the image signal line A7 via the introduced image signal line B7.

[0094] The eighth image signal line A8 from the top among the image signal lines A1 to A12 is electrically connected to the VID8 terminal via the introduced image signal line B8. The VID8 terminal is the eighth image signal terminal from the right among the image signal terminals included in the image signal terminal group 25. The image signal VID8 input to the VID8 terminal is supplied to the image signal line A8 via the introduced image signal line B8.

[0095] The ninth image signal line A9 from the top among the image signal lines A1 to A12 is electrically connected to the VID9 terminal via the introduced image signal line B9. The VID9 terminal is the ninth image signal terminal from the right among the image signal terminals included in the image signal terminal group 25. The image signal VID9 input to the VID9 terminal is supplied to the image signal line A9 via the introduced image signal line B9.

[0096] The tenth image signal line A10 from the top among the image signal lines A1 to A12 is electrically connected to the VID10 terminal via the introduced image signal line B10. The VID10 terminal is the tenth image signal terminal from the right among the image signal terminals included in the image signal terminal group 25. The image signal VID10 input to the VID10 terminal is supplied to the image signal line A10 via the introduced image signal line B10.

[0097] The eleventh image signal line A11 from the top among the image signal lines A1 to A12 is electrically connected to the VID11 terminal via the introduced image signal line B11. The VID11 terminal is the eleventh image signal terminal from the right among the image signal terminals included in the image signal terminal group 25. The image signal VID11 input to the VID11 terminal is supplied to the image signal line A11 via the introduced image signal line B11.

[0098] The twelfth image signal line A12 from the top among the image signal lines A1 to A12, that is, the image signal line A12 farthest from the data line driver circuit 35, is electrically connected to the VID12 terminal via the introduced image signal line B12. The VID12 terminal is the leftmost image signal terminal among the image signal terminals included in the image signal terminal group 25. The image signal VID12 input to the VID12 terminal is supplied to the image signal line A12 via the introduced image signal line B12.

[0099] The switching array circuit 37 is electrically connected to the other ends of the respective data lines 32. The switching array circuit 37 includes a plurality of switching elements SW that correspond one-to-one to the plurality of data lines 32. For example, the switching element SW is a TFT. In addition, for the purpose of coping with high-speed writing, a CMOS structure is also often adopted.

[0100] The data line 32(a) is electrically connected to the video signal line A1 via the switching element SW corresponding to the data line 32(a). In addition, the data line 32(a) refers to the a-th data line 32 from the left among the plurality of data lines 32. a is represented by the following formula (1). In the following formula (1), j is an integer from 0 to M. M is a value obtained by subtracting 1 from the value obtained by dividing the total number of data lines 32 by 12.

[0101] a = 12×j + 1 …(1)

[0102] For example, as understood by substituting 0 as the value of j into the above formula (1), the first data line 32(1) from the left is electrically connected to the video signal line A1 via the switching element SW corresponding to the data line 32(1). In addition, for example, as understood by substituting 1 as the value of j into the above formula (1), the thirteenth data line 32(13) from the left is electrically connected to the video signal line A1 via the switching element SW corresponding to the data line 32(13).

[0103] The data line 32(b) is electrically connected to the video signal line A2 via the switching element SW corresponding to the data line 32(b). In addition, the data line 32(b) refers to the b-th data line 32 from the left among the plurality of data lines 32. b is represented by the following formula (2).

[0104] b = 12×j + 2 …(2)

[0105] For example, as understood by substituting 0 as the value of j into the above formula (2), the second data line 32(2) from the left is electrically connected to the video signal line A2 via the switching element SW corresponding to the data line 32(2). In addition, for example, as understood by substituting 1 as the value of j into the above formula (2), the fourteenth data line 32(14) from the left is electrically connected to the video signal line A2 via the switching element SW corresponding to the data line 32(14).

[0106] The data line 32(c) is electrically connected to the video signal line A3 via the switching element SW corresponding to the data line 32(c). In addition, the data line 32(c) refers to the c-th data line 32 from the left among the plurality of data lines 32. c is represented by the following formula (3).

[0107] c = 12×j + 3 …(3)

[0108] For example, as understood by substituting 0 for the value of j in the above equation (3), the third data line 32(3) from the left is electrically connected to the video signal line A3 via the switching element SW corresponding to the data line 32(3). Additionally, for example, as understood by substituting 1 for the value of j in the above equation (3), the fifteenth data line 32(15) from the left is electrically connected to the video signal line A3 via the switching element SW corresponding to the data line 32(15).

[0109] The data line 32(d) is electrically connected to the video signal line A4 via the switching element SW corresponding to the data line 32(d). Further, the data line 32(d) refers to the d-th data line 32 among the plurality of data lines 32. d is represented by the following equation (4).

[0110] d = 12×j + 4…(4)

[0111] For example, as understood by substituting 0 for the value of j in the above equation (4), the fourth data line 32(4) from the left is electrically connected to the video signal line A4 via the switching element SW corresponding to the data line 32(4). Additionally, for example, as understood by substituting 1 for the value of j in the above equation (4), the sixteenth data line 32(16) from the left is electrically connected to the video signal line A4 via the switching element SW corresponding to the data line 32(16).

[0112] The data line 32(e) is electrically connected to the video signal line A5 via the switching element SW corresponding to the data line 32(e). Further, the data line 32(e) refers to the e-th data line 32 among the plurality of data lines 32. e is represented by the following equation (5).

[0113] e = 12×j + 5…(5)

[0114] For example, as understood by substituting 0 for the value of j in the above equation (5), the fifth data line 32(5) from the left is electrically connected to the video signal line A5 via the switching element SW corresponding to the data line 32(5). Additionally, for example, as understood by substituting 1 for the value of j in the above equation (5), the seventeenth data line 32(17) from the left is electrically connected to the video signal line A5 via the switching element SW corresponding to the data line 32(17).

[0115] The data line 32(f) is electrically connected to the video signal line A6 via the switching element SW corresponding to the data line 32(f). Further, the data line 32(f) refers to the f-th data line 32 among the plurality of data lines 32. f is represented by the following equation (6).

[0116] f = 12×j + 6…(6)

[0117] For example, as understood by substituting 0 for the value of j in the above equation (6), the sixth data line 32(6) from the left is electrically connected to the image signal line A6 via the switching element SW corresponding to the data line 32(6). Additionally, for example, as understood by substituting 1 for the value of j in the above equation (6), the eighteenth data line 32(18) from the left is electrically connected to the image signal line A6 via the switching element SW corresponding to the data line 32(18).

[0118] The data line 32(g) is electrically connected to the image signal line A7 via the switching element SW corresponding to the data line 32(g). Further, the data line 32(g) refers to the g-th data line 32 from the left among the plurality of data lines 32. g is represented by the following equation (7).

[0119] g = 12×j + 7…(7)

[0120] For example, as understood by substituting 0 for the value of j in the above equation (7), the seventh data line 32(7) from the left is electrically connected to the image signal line A7 via the switching element SW corresponding to the data line 32(7). Additionally, for example, as understood by substituting 1 for the value of j in the above equation (7), the nineteenth data line 32(19) from the left is electrically connected to the image signal line A7 via the switching element SW corresponding to the data line 32(19).

[0121] The data line 32(h) is electrically connected to the image signal line A8 via the switching element SW corresponding to the data line 32(h). Further, the data line 32(h) refers to the h-th data line 32 from the left among the plurality of data lines 32. h is represented by the following equation (8).

[0122] h = 12×j + 8…(8)

[0123] For example, as understood by substituting 0 for the value of j in the above equation (8), the eighth data line 32(8) from the left is electrically connected to the image signal line A8 via the switching element SW corresponding to the data line 32(8). Additionally, for example, as understood by substituting 1 for the value of j in the above equation (8), the twentieth data line 32(20) from the left is electrically connected to the image signal line A8 via the switching element SW corresponding to the data line 32(20).

[0124] The data line 32(k) is electrically connected to the image signal line A9 via the switching element SW corresponding to the data line 32(k). Further, the data line 32(k) refers to the k-th data line 32 from the left among the plurality of data lines 32. k is represented by the following equation (9).

[0125] k = 12×j + 9…(9)

[0126] For example, as understood by substituting 0 for the value of j in the above formula (9), the ninth data line 32(9) from the left is electrically connected to the image signal line A9 via the switching element SW corresponding to the data line 32(9). Additionally, for example, as understood by substituting 1 for the value of j in the above formula (9), the twenty - first data line 32(21) from the left is electrically connected to the image signal line A9 via the switching element SW corresponding to the data line 32(21).

[0127] The data line 32(m) is electrically connected to the image signal line A10 via the switching element SW corresponding to the data line 32(m). Further, the data line 32(m) refers to the m - th data line 32 from the left among the plurality of data lines 32. m is represented by the following formula (10).

[0128] m = 12×j + 10…(10)

[0129] For example, as understood by substituting 0 for the value of j in the above formula (10), the tenth data line 32(10) from the left is electrically connected to the image signal line A10 via the switching element SW corresponding to the data line 32(10). Additionally, for example, as understood by substituting 1 for the value of j in the above formula (10), the twenty - second data line 32(22) from the left is electrically connected to the image signal line A10 via the switching element SW corresponding to the data line 32(22).

[0130] The data line 32(n) is electrically connected to the image signal line A11 via the switching element SW corresponding to the data line 32(n). Further, the data line 32(n) refers to the n - th data line 32 from the left among the plurality of data lines 32. n is represented by the following formula (11).

[0131] n = 12×j + 11…(11)

[0132] For example, as understood by substituting 0 for the value of j in the above formula (11), the eleventh data line 32(11) from the left is electrically connected to the image signal line A11 via the switching element SW corresponding to the data line 32(11). Additionally, for example, as understood by substituting 1 for the value of j in the above formula (11), the twenty - third data line 32(23) from the left is electrically connected to the image signal line A11 via the switching element SW corresponding to the data line 32(23).

[0133] The data line 32(p) is electrically connected to the image signal line A12 via the switching element SW corresponding to the data line 32(p). Further, the data line 32(p) refers to the p - th data line 32 from the left among the plurality of data lines 32. p is represented by the following formula (12).

[0134] p = 12×j + 12…(12)

[0135] For example, as understood by substituting 0 for the value of j in the above equation (12), the twelfth data line 32(12) from the left is electrically connected to the image signal line A12 via the switch element SW corresponding to the data line 32(12). Additionally, for example, as understood by substituting 1 for the value of j in the above equation (12), the twenty-fourth data line 32(24) from the left is electrically connected to the image signal line A12 via the switch element SW corresponding to the data line 32(24).

[0136] The switch array circuit 37 includes a plurality of switch blocks SWB. Each switch block SWB contains 12 switch elements SW. The switch elements SW included in the switch array circuit 37 are controlled by the data line driving circuit 35 described later in units of switch blocks SWB.

[0137] The data line driving circuit 35 is electrically connected to the DX terminal, DIRX terminal, CLX terminal, CLXB terminal, ENBX1 terminal, and ENBX2 terminal via the second level shifter group 41, respectively. Additionally, the data line driving circuit 35 is electrically connected to the VDDX terminal and VSSX terminal via wiring (not shown), respectively.

[0138] The second level shifter group 41 includes six level shifters represented by the symbol "L / S". The second start pulse signal DX input to the DX terminal, the second shift control signal DIRX input to the DIRX terminal, the second clock signal CLX input to the CLX terminal, the second inverted clock signal CLXB input to the CLXB terminal, the first enable signal ENBX1 input to the ENBX1 terminal, and the second enable signal ENBX2 input to the ENBX2 terminal are supplied to the data line driving circuit 35 via the level shifters corresponding to the respective terminals. In the second level shifter group 41, for example, a buffer circuit commensurate with the driving load of each signal line may also be included. Further, in the case of a clock signal, for example, a phase difference correction circuit may also be included. As described previously, due to the offset arrangement of the image signal terminal group 25, the input signal terminal group for the second level shifter group 41 is offset in the direction opposite to the offset direction of the image signal terminal group 25 with respect to the display center line CL. In this way, the outer dimensions of the liquid crystal panel 10 can be formed compactly.

[0139] Via level shifters corresponding to the DX terminal, DIRX terminal, CLX terminal, CLXB terminal, ENBX1 terminal, and ENBX2 terminal respectively, the voltage levels of the second start pulse signal DX, the second shift control signal DIRX, the second clock signal CLX, the second inverted clock signal CLXB, the first enable signal ENBX1, and the second enable signal ENBX2 are adjusted to values suitable for the data line driver circuit 35. Additionally, by using two systems, the first enable signal ENBX1 and the second enable signal ENBX2, it is possible to reliably shape the write selection period of about several tens of nanoseconds, in other words, the on period of the switching element SW, and thus it is possible to handle high-speed writing.

[0140] The second high potential VDDX and the second low potential VSSX are supplied to the data line driver circuit 35 via the VDDX terminal and the VSSX terminal. The data line driver circuit 35 uses the potential difference between the second high potential VDDX and the second low potential VSSX as the power supply voltage.

[0141] Although not shown in Figure 3 and Figure 4 for the sake of simplicity, the data line driver circuit 35 includes a second shift register circuit, a second waveform shaping circuit, and a second buffer circuit. The second shift register circuit starts the transfer operation synchronously with the second start pulse signal DX. The shift direction of the second shift register circuit is controlled by the second shift control signal DIRX. The second clock signal CLX and the second inverted clock signal CLXB are used as the clock signals for the second shift register circuit.

[0142] The second shift register circuit includes a plurality of flip-flops corresponding one-to-one to a plurality of switch blocks SWB. The second waveform shaping circuit includes a plurality of AND circuits corresponding one-to-one to the plurality of switch blocks SWB. The first enable signal ENBX1 is input to the AND circuits corresponding to the odd-numbered switch blocks SWB counted from the left. The second enable signal ENBX2 is input to the AND circuits corresponding to the even-numbered switch blocks SWB counted from the left.

[0143] For example, the output signal of the flip-flop corresponding to the switch block SWB(r) is input to the AND circuit corresponding to the switch block SWB(r). Additionally, the switch block SWB(r) refers to the r-th switch block SWB counted from the left among the plurality of switch blocks SWB. r is an integer from 1 to K. K is the total number of switch blocks SWB.

[0144] The AND circuit corresponding to the switch block SWB(r) outputs, as a switch control signal supplied to the switch block SWB(r), a signal representing the logical product of the output signal of the flip-flop corresponding to the switch block SWB(r) and the first enable signal ENBX1 or the second enable signal ENBX2. The switch control signal output from the AND circuit corresponding to the switch block SWB(r) is buffered by the second buffer circuit and then supplied to the switch block SWB(r).

[0145] When a switch control signal is supplied to the switch block SWB(r), all 12 switch elements SW included in the switch block SWB(r) become in the on state. For example, when a switch control signal is supplied to the first switch block SWB(1) from the left, the 12 switch elements SW corresponding to the 12 data lines 32 from the data line 32(1) to the data line 32(12) become in the on state.

[0146] In this case, for example, the video signal VID1 input to the VID1 terminal is supplied to the data line 32(1) via the incoming video signal line B1 and the video signal line A1. Further, in this case, for example, the video signal VID12 input to the VID12 terminal is supplied to the data line 32(12) via the incoming video signal line B12 and the video signal line A12.

[0147] Further, for example, when a switch control signal is supplied to the second switch block SWB(2) from the left, the 12 switch elements SW corresponding to the 12 data lines 32 from the data line 32(13) to the data line 32(24) become in the on state. In this case, for example, the video signal VID1 input to the VID1 terminal is supplied to the data line 32(13) via the incoming video signal line B1 and the video signal line A1. Further, in this case, for example, the video signal VID12 input to the VID12 terminal is supplied to the data line 32(24) via the incoming video signal line B12 and the video signal line A12.

[0148] As understood from the above description, for example, when a scan signal is supplied to the scan line 31(i) and a switch control signal is supplied to the switch block SWB(1), the pixel switch element of the pixel P corresponding to the position where the scan line 31(i) intersects the data line 32(1) becomes in the on state, and the potential difference between the video signal VID1 and the first common potential LCCOM is applied to the liquid crystal layer 14 between the pixel electrode 15 and the common electrode 18 of the pixel P. Further, in this case, for example, the pixel switch element of the pixel P corresponding to the position where the scan line 31(i) intersects the data line 32(12) becomes in the on state, and the potential difference between the video signal VID12 and the first common potential LCCOM is applied to the liquid crystal layer 14 between the pixel electrode 15 and the common electrode 18 of the pixel P.

[0149] Further, for example, when a scan signal is supplied to the scan line 31(i) and a switch control signal is supplied to the switch block SWB(2), the pixel switch element of the pixel P corresponding to the position where the scan line 31(i) intersects the data line 32(13) becomes conductive, and the potential difference between the video signal VID1 and the first common potential LCCOM is applied to the liquid crystal layer 14 between the pixel electrode 15 and the common electrode 18 of the pixel P. Further, in this case, for example, the pixel switch element of the pixel P corresponding to the position where the scan line 31(i) intersects the data line 32(24) becomes conductive, and the potential difference between the video signal VID12 and the first common potential LCCOM is applied to the liquid crystal layer 14 between the pixel electrode 15 and the common electrode 18 of the pixel P.

[0150] The inspection circuit 42 is electrically connected to the PCG terminal, the DY terminal, the DIRY terminal, the CLY terminal, the CLYB terminal, and the ENBY terminal via the first level shifter group 40, respectively. In addition, the inspection circuit 42 is electrically connected to the DX terminal, the DIRX terminal, the CLX terminal, the CLXB terminal, the ENBX1 terminal, and the ENBX2 terminal via the second level shifter group 41, respectively. Further, the inspection circuit 42 is electrically connected to the MODE terminal and the TESTO terminal.

[0151] The inspection circuit 42 switches to either the first inspection mode or the second inspection mode according to the mode switching signal MODE input from an inspection device (not shown) via the MODE terminal.

[0152] When the inspection mode is the first inspection mode, the inspection circuit 42 checks whether the first level shifter group 40 operates normally based on the precharge control signal PCG, the first start pulse signal DY, the first shift control signal DIRY, the first clock signal CLY, the first inverted clock signal CLYB, and the enable signal ENBY.

[0153] When the inspection mode is the second inspection mode, the inspection circuit 42 checks whether the second level shifter group 41 operates normally based on the second start pulse signal DX, the second shift control signal DIRX, the second clock signal CLX, the second inverted clock signal CLXB, the first enable signal ENBX1, and the second enable signal ENBX2.

[0154] After inspecting the first level shifter group 40 or the second level shifter group 41, the inspection circuit 42 outputs an inspection result signal TESTO indicating the inspection result to the TESTO terminal. The inspection result signal TESTO output from the inspection circuit 42 to the TESTO terminal is output from the TESTO terminal to an inspection device (not shown).

[0155] The above is the description of the circuit structure of the component substrate 11. Next, with reference to Figure 5 the relationship between the image signal lines A1 to A12 and the introduced image signal lines B1 to B12 will be described in more detail. Figure 5 It is extracted from Figure 4 a diagram showing the paired image signal line A1 and the introduced image signal line B1, and the paired image signal line A12 and the introduced image signal line B12.

[0156] In the following description, as an example, the introduced image signal line B1 having the shortest first wiring length L1 among the introduced image signal lines B1 to B12 is referred to as the "first introduced image signal line B1", and the introduced image signal line B12 having the longest second wiring length L2 is referred to as the "second introduced image signal line B12". In addition, the image signal line A1 among the image signal lines A1 to A12 that is electrically connected to the first introduced image signal line B1 at the first connection point P1 is referred to as the "first image signal line A1", and the image signal line A12 that is electrically connected to the second introduced image signal line B12 at the second connection point P2 is referred to as the "second image signal line A12".

[0157] The length from the first connection point P1 to the left end of the first image signal line A1 is the third wiring length L3. The length from the first connection point P1 to the right end of the first image signal line A1 is the fourth wiring length L4. The length from the second connection point P2 to the left end of the second image signal line A12 is the fifth wiring length L5. The length from the second connection point P2 to the right end of the second image signal line A12 is the sixth wiring length L6. The longest wiring length among the fifth wiring length L5 and the sixth wiring length L6 is shorter than the longest wiring length among the third wiring length L3 and the fourth wiring length L4.

[0158] That is, the first introduced image signal line B1, the second introduced image signal line B12, the first image signal line A1, and the second image signal line A12 are in a relationship that satisfies the following equations (13) and (14). In addition, in the following equation (14), MAX(L5:L6) represents the longest wiring length among the fifth wiring length L5 and the sixth wiring length L6, and MAX(L3:L4) represents the longest wiring length among the third wiring length L3 and the fourth wiring length L4.

[0159] L1 < L2…(13)

[0160] MAX(L5:L6) < MAX(L3:L4)…(14)

[0161] In addition, when the fifth wiring length L5 is equal to the sixth wiring length L6, either the fifth wiring length L5 or the sixth wiring length L6 can be the left side of the above formula (14). Similarly, when the third wiring length L3 is equal to the fourth wiring length L4, either the third wiring length L3 or the fourth wiring length L4 can be the right side of the above formula (14).

[0162] Figures 6 to 9 FIG. is an example of a wiring pattern of the first introduced video signal line B1. Figure 6 FIG. is an example of a wiring pattern of the first introduced video signal line B1 that is linearly arranged with substantially equal width from the VID1 terminal. Figure 7 FIG. is an example of a wiring pattern of the first introduced video signal line B1 that is arranged with substantially equal width from the VID1 terminal via a bent portion. Figure 8 FIG. is an example of a wiring pattern of the first introduced video signal line B1 that is arranged with substantially equal width from the VID1 terminal via a diagonal portion intersecting the Y direction. Figure 9 FIG. is an example of a wiring pattern of the first introduced video signal line B1 that is arranged via a widened portion. In addition, Figure 9 a widened portion like that has a special effect through research and configuration, which will be described in detail later. Regarding the introduced video signal line, it is not limited to being composed of the same wiring layer, and of course, it can also pass through different wiring layers. As Figures 6 to 9 shown, the first wiring length L1 of the first introduced video signal line B1 is defined as the length of a line segment that connects the VID1 terminal and the contact hole CH with substantially the shortest distance within the wiring pattern of the first introduced video signal line B1. Therefore, the magnitude of the length of this line segment is substantially synonymous with the magnitude of the wiring resistance of the first introduced video signal line B1. The contact hole CH is, for example, an opening formed in an insulating layer disposed between the wiring layer constituting the first introduced video signal line B1 and the wiring constituting the first video signal line A1. This opening can be processed by etching the insulating layer using a photolithography method. At the opening, the wiring layer constituting the video signal line A1 is exposed. Therefore, if the wiring layer constituting the first introduced video signal line B1 is sputter-deposited, the first introduced video signal line B1 is physically in contact with the first video signal line A1, and thus electrically connected. The contact hole CH is located at the first connection point P1 and electrically connects the first introduced video signal line B1 and the first video signal line A1. The definition of the second wiring length L2 of the second introduced video signal line B12 is the same as the definition of the first wiring length L1.

[0163] In the above description, attention is focused on the paired video signal lines A1 and introduced video signal lines B1, and the paired video signal lines A12 and introduced video signal lines B12. However, from Figure 3 and Figure 4It can be seen that the paired image signal lines A1 and the introduced image signal line B1, any arbitrarily selected image signal line other than the paired image signal line A1, and the introduced image signal line electrically connected thereto also satisfy the relationships of the above equations (13) and (14).

[0164] For example, in the case where the introduced image signal line B1 having the shortest first wiring length L1 among the introduced image signal lines B1 to B12 is selected as the "first introduced image signal line" and the introduced image signal line B6 is assumed to be the "second introduced image signal line" for selection, the image signal line A1 becomes the "first image signal line" and the image signal line A6 becomes the "second image signal line". In this case, the first introduced image signal line B1, the second introduced image signal line B6, the first image signal line A1, and the second image signal line A6 also satisfy the relationships of the above equations (13) and (14).

[0165] As described above, the liquid crystal panel 10 of the present embodiment has a structure in which the image signal lines A1 to A12 disposed between the display region E and the data line driver circuit 35 are electrically connected to the introduced image signal lines B1 to B12 passing through the data line driver circuit 35 in a one-to-one manner. According to the liquid crystal panel 10 having such a structure, compared with the prior art in which the image signal line group is arranged so as to bypass the data line driver circuit, the length of the propagation path of the image signals VID1 to VID12 is shortened, and thus the delay of the image signals VID1 to VID12 can be reduced.

[0166] In addition, the liquid crystal panel 10 of the present embodiment has a structure in which the introduced image signal lines B1 and B12 and the two image signal lines connected to these two introduced image signal lines satisfy the relationships of the above equations (13) and (14). As will be described below, according to the liquid crystal panel 10 having such a structure, compared with the comparative example described later, regarding the connection points of the introduced image signal lines and the image signal lines, the delay related to the image signals with a large deviation amount from the display center line CL can be reduced.

[0167] Figure 10 It is a top view showing the wiring layout of the comparative example. Hereinafter, for the sake of convenience of explanation, the same symbols are used to describe the wiring layout of the comparative example. As will be described with reference to Figure 4 the same, in the present embodiment, the first image signal line A1 from the top among the image signal lines A1 to A12, that is, the image signal line A1 closest to the data line driver circuit 35, is electrically connected to the VID1 terminal via the introduced image signal line B1. Figure 4 As described, in the present embodiment, the first image signal line A1 from the top among the image signal lines A1 to A12, that is, the image signal line A1 closest to the data line driver circuit 35, is electrically connected to the VID1 terminal via the introduced image signal line B1.

[0168] As described above, the VID1 terminal is the rightmost video signal terminal among the video signal terminals included in the video signal terminal group 25. In other words, the VID1 terminal is the video signal terminal with the largest offset amount among the video signal terminals located at positions offset to the right from the display center line CL. On the other hand, as Figure 10 shown, in the comparative example, the twelfth video signal line A12 from the top among the video signal lines A1 to A12, that is, the video signal line A12 farthest from the data line driving circuit 35, is electrically connected to the VID1 terminal via the lead-in video signal line B1.

[0169] In addition, as described with reference to Figure 4 , in the present embodiment, the twelfth video signal line A12 from the top among the video signal lines A1 to A12, that is, the video signal line A12 farthest from the data line driving circuit 35, is electrically connected to the VID12 terminal via the lead-in video signal line B12. On the other hand, as Figure 10 shown, in the comparative example, the first video signal line A1 from the top among the video signal lines A1 to A12, that is, the video signal line A1 closest to the data line driving circuit 35, is electrically connected to the VID12 terminal via the lead-in video signal line B12.

[0170] In Figure 4 the present embodiment shown, the point where the lead-in video signal line B1 extending from the VID1 terminal is electrically connected to the video signal line A1 is set as "connection point P1a", and the point where the lead-in video signal line B12 extending from the VID12 terminal is electrically connected to the video signal line A12 is set as "connection point P12a". In addition, in Figure 4 the present embodiment shown, the left end of the video signal line A1 is set as "end point P1b", and the left end of the video signal line A12 is set as "end point P12b".

[0171] On the other hand, in Figure 10 the comparative example shown, the point where the lead-in video signal line B1 extending from the VID1 terminal is electrically connected to the video signal line A12 is set as "connection point P1a", and the point where the lead-in video signal line B12 extending from the VID12 terminal is electrically connected to the video signal line A1 is set as "connection point P12a". In addition, in Figure 10 the comparative example shown, the left end of the video signal line A12 is set as "end point P1b", and the left end of the video signal line A1 is set as "end point P12b".

[0172] Here, a summary of the difference in signal delay between Figure 4 the present embodiment shown and Figure 10 the comparative example shown is described. Figure 11is a diagram schematically showing the delay times of the video signals VID1 and VID12 of the present embodiment and the delay times of the video signals VID1 and VID12 of the comparative example. As Figure 11 shown, in both the present embodiment and the comparative example, the delay time of the video signal VID1 at the connection point P1a with respect to the VID1 terminal is set to "Td1a". In addition, in both the present embodiment and the comparative example, the delay time of the video signal VID12 at the connection point P12a with respect to the VID12 terminal is set to "Td12a".

[0173] Here, regarding the introduction of the video signal lines B1 and B12, it is treated as a case where the parasitic capacitance is extremely small, and the wiring resistance is mainly considered. At each connection point P1a and P12a, the time constant of this wiring resistance and the parasitic capacitance based on the video signal lines A1 and A12 extending along the X-axis can be seen.

[0174] When considering that the parasitic capacitances of the video signal lines A1 and A12 are close to each other, due to the wiring resistance difference caused by the wiring length difference of the introduced video signal lines B1 and B12, in the present embodiment, the delay time Td1a of the video signal VID1 is shorter than the delay time Td12a of the video signal VID12. On the other hand, in the comparative example, the magnitude relationship is reversed, and the delay time Td1a of the video signal VID1 becomes longer than the delay time Td12a of the video signal VID12.

[0175] In addition, in the present embodiment and the comparative example, at Figure 11 the moment t0 shown, the video signal VID1 is ideally input to the VID1 terminal, and the video signal VID12 is ideally input to the VID12 terminal. The delay time Td1a of the video signal VID1 in the present embodiment is approximately equal to the delay time Td12a of the video signal VID12 in the comparative example, which corresponds to the time from the moment t0 to the moment t1.

[0176] Next, as Figure 11 shown, in both the present embodiment and the comparative example, the delay time of the video signal VID1 at the end point P1b with respect to the connection point P1a is set to "Td1b". In addition, in both the present embodiment and the comparative example, the delay time of the video signal VID12 at the end point P12b with respect to the connection point P12a is set to "Td12b".

[0177] In the image signal lines A1 and A12 extending along the X-axis, it can be considered that the parasitic capacitance and the wiring resistance are distributed substantially evenly. Therefore, when taking the connection point P1a as a reference, the maximum delay of the image signal VID1 occurs at the end point P1b. Similarly, when taking the connection point P12a as a reference, the maximum delay of the image signal VID12 occurs at the end point P12b. Therefore, by focusing on the delays at the end point P1b, which is the farthest from the connection point P1a, and the end point P12b, which is the farthest from the connection point P12a, an overview of the delay of the image signal can be examined.

[0178] In the present embodiment, the distance between the connection point P1a and the end point P1b is longer than the distance between the connection point P12a and the end point P12b. Therefore, in this embodiment, the delay time Td1b of the image signal VID1 is greater than the delay time Td12b of the image signal VID12. Similarly, in the comparative example, the distance between the connection point P1a and the end point P1b is longer than the distance between the connection point P12a and the end point P12b. Therefore, the delay time Td1b of the image signal VID1 is greater than the delay time Td12b of the image signal VID12.

[0179] In the present embodiment, the delay of the image signal VID1 at the end point P1b is the time t2 with respect to the VID1 terminal. On the other hand, in the comparative example, the delay of the image signal VID1 at the end point P1b is the time t3 with respect to the VID1 terminal. Thus, according to the liquid crystal panel 10 of the present embodiment, compared with Figure 10 the comparative example shown, the delay of the image signal VID1 input to the VID1 terminal with the largest offset amount among the image signal terminals located at positions shifted to the right from the display center line CL can be reduced. In addition, in the present embodiment, the signal delay is the smallest near the connection point P1a, and the signal delay corresponds to the time t1. On the contrary, the signal delay is the largest near the end point P12b, and the signal delay corresponds to the time t4. Therefore, overall, the signal delay distribution of the image signals VID1 to VID12 is from the time t1 to the time t4. On the other hand, in the comparative example, the signal delay is the smallest near the connection point P12a, and the signal delay corresponds to the time t1. On the contrary, the signal delay is the largest near the end point P1b, and the signal delay corresponds to the time t3. Therefore, overall, the signal delay distribution of the image signals VID1 to VID12 is from the time t1 to the time t3. Therefore, according to the present embodiment, the time of the image signals is consistent, and thus it is suitable for high-speed driving.

[0180] (Effect of the present embodiment)

[0181] As described above, the liquid crystal panel 10 of the present embodiment includes: a plurality of scan lines 31 extending along the X axis; a plurality of data lines 32 extending along the Y axis intersecting the X axis; pixels P correspondingly disposed at respective positions where the plurality of scan lines 31 intersect the plurality of data lines 32 in the display area E; a data line driving circuit 35 disposed at a position spaced upward from the display area E; twelve video signal lines A1 to A12 disposed between the display area E and the data line driving circuit 35 and extending along the X axis; and twelve introduced video signal lines B1 to B12 extending along the Y axis and electrically connected to the twelve video signal lines A1 to A12 one-to-one.

[0182] When viewed from above, the introduced video signal lines B1 to B12 cross the data line driving circuit 35.

[0183] The introduced video signal lines B1 to B12 include a first introduced video signal line B1 having the shortest first wiring length L1 and a second introduced video signal line B12 having the longest second wiring length L2.

[0184] The video signal lines A1 to A12 include a first video signal line A1 electrically connected to the first introduced video signal line B1 at a first connection point P1 and a second video signal line A12 electrically connected to the second introduced video signal line B12 at a second connection point P2.

[0185] The length from the first connection point P1 to the left end of the first video signal line A1 is a third wiring length L3. The length from the first connection point P1 to the right end of the first video signal line A1 is a fourth wiring length L4. The length from the second connection point P2 to the left end of the second video signal line A12 is a fifth wiring length L5.

[0186] The length from the second connection point P2 to the right end of the second video signal line A12 is a sixth wiring length L6.

[0187] The longest wiring length among the fifth wiring length L5 and the sixth wiring length L6 is shorter than the longest wiring length among the third wiring length L3 and the fourth wiring length L4.

[0188] According to the liquid crystal panel 10 of the present embodiment as described above, compared with the prior art in which the video signal line group is arranged in a manner of bypassing the data line driving circuit, the length of the propagation path of the video signals VID1 to VID12 is shortened, so that the delay of the video signals VID1 to VID12 can be reduced. In addition, according to the liquid crystal panel 10 of the present embodiment, compared with Figure 10Compared with the comparative example shown, it is possible to reduce the delay of the video signal VID1, which has the largest offset amount, input to the video signal terminal located at a position shifted to the right from the display center line CL. In addition, it is possible to reduce the delay difference between the video signals VID1 to VID12. As a result, high-speed driving of the liquid crystal panel 10 can be achieved.

[0189] 2. Electronic device

[0190] Figure 12 FIG. is a schematic structural diagram showing the structure of a projector 100 as an electronic device according to the present embodiment. Hereinafter, as an electronic device including the liquid crystal panel 10 of the present embodiment, the projector 100 will be described as an example.

[0191] The projector 100 is a three-panel projector, and includes: a lamp unit 101 as a light source; dichroic mirrors 102 and 103 as a color separation optical system; a liquid crystal panel 10B corresponding to blue light B; a liquid crystal panel 10G corresponding to green light G; a liquid crystal panel 10R corresponding to red light R; three reflecting mirrors 111, 112, and 113; three relay lenses 121, 122, and 123; a dichroic prism 130 as a color synthesis optical system; and a projection lens 140 as a projection optical system. An image is projected onto a screen SC through the projection optical system. In addition, the relay lenses 121, 122, and 123 and the reflecting mirrors 112 and 113 constitute a relay lens system 120. In addition, the projector 100 includes a control device 150 that controls the liquid crystal panels 10B, 10G, and 10R.

[0192] 3. Modification example

[0193] As described above, the embodiments of the present disclosure have been described, but the technical scope of the present disclosure is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present disclosure. For example, consider the following modification examples.

[0194] (1) When observing Figure 11 , it is possible to expect to reduce the difference in the delay time Td1a at the first connection point and the delay time Td12a at the second connection point, and it is also effective in reducing the delay difference between the video signals VID1 to VID12. Figure 13 FIG. shows a first modification example of the liquid crystal panel 10. As Figure 13 shown, each of the introduced video signal lines B1 to B12 may have a widened portion 50. The widened portion 50 is a portion having a larger width than other portions in the wiring pattern of each of the introduced video signal lines B1 to B12. For example, each widened portion 50 has a rectangular shape.

[0195] All the widening portions 50 have the same width. Among the 12 widening portions 50, the widening portion 50 located at the leftmost side, that is, the widening portion 50 for introducing the video signal line B12, has the longest length. As moving from the video signal line B1 for introduction towards the video signal line B12 for introduction, the length of the widening portion 50 gradually becomes longer.

[0196] For example, the video signal line B1 for introduction having the shortest first wiring length L1 among the video signal lines B1 to B12 for introduction is set as the "first video signal line for introduction", and the video signal line B12 for introduction having the longest second wiring length L2 is set as the "second video signal line for introduction". In addition, the widening portion 50 of the first video signal line for introduction B1 is set as the "first widening portion 50(1)", and the widening portion 50 of the second video signal line for introduction B12 is set as the "second widening portion 50(12)".

[0197] That is, in the first modification example, the first video signal line for introduction B1 has the first widening portion 50(1), and the second video signal line for introduction B12 has the second widening portion 50(12). The width of the first widening portion 50(1) is the same as the width of the second widening portion 50(12). The length of the first widening portion 50(1) is shorter than the length of the second widening portion 50(12). Therefore, a wiring resistance difference is generated due to the difference in the length of the widening portion 50.

[0198] According to the first modification example as described above, the wiring resistance of the video signal lines B1 to B12 for introduction becomes smaller from the video signal line B1 for introduction towards the video signal line B12 for introduction. As a result, the delay time Td12a of the video signal VID12 at the connection point P12a based on the VID12 terminal becomes shorter. As Figure 11 shown, if the delay time Td12a of the video signal VID12 becomes shorter, the delay difference of the video signals VID1 to VID12 can be reduced, and thus further high-speed driving of the liquid crystal panel 10 can be achieved.

[0199] In addition, as Figure 13 shown, preferably, in a plan view, all the widening portions 50 including the first widening portion 50(1) and the second widening portion 50(12) are arranged at positions not overlapping with the data line driving circuit 35. More specifically, all the widening portions 50 including the first widening portion 50(1) and the second widening portion 50(12) are preferably arranged between the data line driving circuit 35 and the video signal terminal group 25. In other words, the position overlapping with the data line driving circuit 35 refers to, for example, a portion overlapping with the driving signal line, the driving potential line supplied to the data line driving circuit 35, and the transistors constituting the data line driving circuit 35 in a plan view, and the widening portion 50 is preferably arranged avoiding these portions. Thereby, an unnecessary parasitic capacitance can be avoided from being generated between all the widening portions 50 and various wirings constituting the data line driving circuit 35.

[0200] (2) Figure 14 This is a diagram showing a second modification example of the liquid crystal panel 10. As Figure 14 shown, each of the introduced image signal lines B1 to B12 may also have a widened portion 60. The widened portion 60 is a portion in the wiring pattern of each of the introduced image signal lines B1 to B12 where the width is larger than other portions. For example, each widened portion 60 has a rectangular shape.

[0201] The lengths of all the widened portions 60 are the same. The width of the widened portion 60 of the introduced image signal line B1, which is the rightmost one among the 12 widened portions 60, is the smallest. As moving from the introduced image signal line B1 toward the introduced image signal line B12, the width of the widened portion 60 gradually increases.

[0202] For example, similar to the first modification example, the widened portion 60 of the first introduced image signal line B1 is designated as "first widened portion 60(1)", and the widened portion 60 of the second introduced image signal line B12 is designated as "second widened portion 60(12)". That is, in the second modification example, the first introduced image signal line B1 has the first widened portion 60(1), and the second introduced image signal line B12 has the second widened portion 60(12).

[0203] The length of the first widened portion 60(1) is the same as the length of the second widened portion 60(12). The width of the first widened portion 60(1) is smaller than the width of the second widened portion 60(12).

[0204] According to the second modification example as described above, the wiring resistance of the introduced image signal lines B1 to B12 becomes smaller from the introduced image signal line B1 toward the introduced image signal line B12. As a result, the delay time Td12a of the image signal VID12 at the connection point P12a based on the VID12 terminal becomes shorter. As Figure 11 shown, if the delay time Td12a of the image signal VID12 becomes shorter, the delay difference of the image signals VID1 to VID12 is reduced, and thus further high-speed driving of the liquid crystal panel 10 can be achieved.

[0205] In addition, similar to the first modification example, as Figure 14 shown, preferably, in a top view, all the widened portions 60 including the first widened portion 60(1) and the second widened portion 60(12) are arranged at positions that do not overlap with the data line driver circuit 35. More specifically, all the widened portions 60 including the first widened portion 60(1) and the second widened portion 60(12) are preferably arranged between the data line driver circuit 35 and the image signal terminal group 25.

[0206] (3)In the above-described embodiment, the liquid crystal panel 10 driven by the 12-phase phase-expanded driving method is illustrated. However, the present disclosure can also be applied to a liquid crystal panel driven by a phase-expanded driving method other than 12 phases. The number of image signal lines, the introduced image signal lines, and the image signal terminals may be appropriately changed according to the number of phases.

[0207] (4)In the structures shown in the first modification example and the second modification example, the wiring resistance of the introduced image signal lines is adjusted. However, the wiring resistance can also be adjusted by a structure other than the structures shown in the first modification example and the second modification example. For example, instead of using the widened portions 50 and 60, a wiring resistance body bent in a zigzag shape may be provided. In this case, the extension of the bend becomes longer from the introduced image signal line B1 toward the introduced image signal line B12. In addition, it is not mandatory to provide a resistance adjustment unit for each introduced image signal line. For example, it may be configured such that the same resistance value adjustment 1 is performed on the introduced image signal lines B1 and B2, and the same resistance value adjustment 2 is performed on the introduced image signal lines B3 and B4.

[0208] (5)In the above-described embodiment, for the sake of convenience of explanation, the VID12 terminal in the image signal terminal group 25 is located near the display center line CL. However, it is not limited thereto, and some of the VID1 terminals to VID12 terminals may be offset to the left side from the display center line CL, and some of the other terminals may be offset to the right side from the display center line CL. For example, as Figure 15 shown, the VID9 terminal may also be located near the display center line CL. Even in such a case, the present invention can be applied within the range satisfying the equations (13) and (14). For example, when the VID9 terminal is located near the display center line CL, in Figure 15 the farthest point P1b of the image signal line A1 with respect to the connection point P1a is located on the +X direction side. On the other hand, it can be considered that the farthest point P12b of the image signal line A12 with respect to the connection point P12a becomes the -X direction side. In this case, it can also be configured to satisfy the equations (13) and (14). At this time, the absolute value of the offset amount of the connection point P1a from the display center line CL is set as OFF1, and the absolute value of the offset amount of the connection point P12a from the display center line CL is set as OFF2, and OFF1 is greater than OFF2. In addition, if the introduced image signal lines B1 to B12 are arranged substantially linearly from the VID terminal 1 to the VID terminal 12 and are electrically connected to the image signal lines A1 to A12, the absolute value of the offset amount of the VID terminal 1 from the display center line CL is greater than the absolute value of the offset amount of the VID terminal 12 from the display center line CL.

[0209] (6) In the above-described embodiment, the liquid crystal panel 10 is exemplified as the electro-optical device of the present disclosure, but the present disclosure can also be applied to other electro-optical devices such as an OLED (Organic Electro Luminescence Diode) panel. In addition, the element substrate 11 and the counter substrate 12 are not limited to glass substrates, and can also be applied to other electro-optical devices made of plastic substrates.

[0210] (7) In the above-described embodiment, the projector 100 is exemplified as the electronic device having the liquid crystal panel 10, but the electronic device of the present disclosure is not limited thereto. For example, the electronic device of the present disclosure can also be a 3D printer that cures a resin liquid using light emitted from an electro-optical device such as the liquid crystal panel 10, a HUD (Head-Up Display), an HMD (Head Mounted Display), a monitor for a personal computer, a digital camera, and a television set.

[0211] [Summary of the Present Disclosure]

[0212] Hereinafter, the summary of the present disclosure is noted.

[0213] (Supplementary Note 1) An electro-optical device includes: a plurality of scan lines extending in a first direction; a plurality of data lines extending in a second direction intersecting the first direction; pixels correspondingly disposed at respective positions where the plurality of scan lines and the plurality of data lines intersect in a display area; a data line driving circuit disposed at a position spaced apart from one end side of the display area in the second direction; a plurality of image signal lines disposed between the display area and the data line driving circuit and extending in the first direction; and a plurality of lead-in image signal lines extending in the second direction and electrically connected to the plurality of image signal lines one-to-one. When viewed from above, the plurality of lead-in image signal lines cross the data line driving circuit. The plurality of lead-in image signal lines include: a first lead-in image signal line having a shortest first wiring length; and a second lead-in image signal line having a longest second wiring length. The plurality of image signal lines include: a first image signal line electrically connected to the first lead-in image signal line at a first connection point; and a second image signal line electrically connected to the second lead-in image signal line at a second connection point. The length from the first connection point to one end of the first image signal line is a third wiring length, the length from the first connection point to the other end of the first image signal line is a fourth wiring length, the length from the second connection point to one end of the second image signal line is a fifth wiring length, and the length from the second connection point to the other end of the second image signal line is a sixth wiring length. The longest wiring length among the fifth wiring length and the sixth wiring length is shorter than the longest wiring length among the third wiring length and the fourth wiring length.

[0214] The electro-optical device described in Supplementary Note 1 has the following structure: A plurality of image signal lines disposed between the display area and the data line driving circuit are electrically connected to a plurality of lead-in image signal lines crossing the data line driving circuit one-to-one. According to the electro-optical device having such a structure, compared with the prior art in which the image signal line group is disposed so as to bypass the data line driving circuit, the length of the propagation path of the image signal becomes shorter, and thus the delay of the image signal can be reduced. In addition, according to the electro-optical device described in Supplementary Note 1, compared with Figure 10 the comparative example shown, the delay of the image signal propagating in the lead-in image signal line located at the position farthest from the display center line can be reduced. As a result, high-speed driving of the electro-optical device can be achieved.

[0215] (Supplementary Note 2) According to the electro-optical device described in Supplementary Note 1, the first lead-in image signal line has a first widened portion, the second lead-in image signal line has a second widened portion, the width of the first widened portion is the same as the width of the second widened portion, and the length of the first widened portion is shorter than the length of the second widened portion.

[0216] According to the electro-optical device described in Supplementary Note 2, the wiring resistance of the second introduced video signal line having the longest second wiring length becomes smaller, so the signal delay at the second connection point can be reduced. As a result, further high-speed driving of the electro-optical device can be achieved.

[0217] (Supplementary Note 3) According to the electro-optical device described in Supplementary Note 1, the first introduced video signal line has a first widened portion, the second introduced video signal line has a second widened portion, the length of the first widened portion is the same as the length of the second widened portion, and the width of the first widened portion is smaller than the width of the second widened portion.

[0218] According to the electro-optical device described in Supplementary Note 3, the wiring resistance of the second introduced video signal line having the longest second wiring length becomes smaller, so the signal delay at the second connection point can be reduced. As a result, further high-speed driving of the electro-optical device can be achieved.

[0219] (Supplementary Note 4) According to the electro-optical device described in Supplementary Note 2 or Supplementary Note 3, when viewed from above, the first widened portion and the second widened portion are arranged at positions not overlapping with the data line driving circuit.

[0220] According to the electro-optical device described in Supplementary Note 4, since the first widened portion and the second widened portion are arranged at positions not overlapping with the data line driving circuit when viewed from above, parasitic capacitance can be avoided from being generated between the first widened portion and the second widened portion and various wirings constituting the data line driving circuit. Therefore, an increase in unnecessary signal delay at the connection points of the respective introduced video signal lines and the video signal lines is suppressed.

[0221] (Supplementary Note 5) An electronic device having the electro-optical device described in any one of Supplementary Notes 1 to 4.

Claims

1. An electro-optical device comprising: a plurality of scan lines extending along a first direction; a plurality of data lines extending along a second direction intersecting the first direction; Pixels are correspondingly arranged at positions where the plurality of scan lines intersect the plurality of data lines in the display area; a data line driving circuit disposed at a position away from the display area toward one end side of the second direction; a plurality of image signal lines, which are arranged between the display area and the data line driving circuit and extend along the first direction; as well as a plurality of incoming image signal lines extending along the second direction and electrically connected to the plurality of image signal lines one by one, When viewed from above, the plurality of lead-in image signal lines traverse the data line driving circuit, and the plurality of lead-in image signal lines include: a first lead-in image signal line having the shortest first wiring length; and a second lead-in image signal line having the longest second wiring length, The plurality of image signal lines include: a first image signal line electrically connected to the first incoming image signal line at a first connection point; and a second image signal line electrically connected to the second incoming image signal line at a second connection point, The length from the first connection point to one end of the first image signal line is a third wiring length. The length from the first connection point to the other end of the first image signal line is a fourth wiring length. The length from the second connection point to one end of the second image signal line is a fifth wiring length. The length from the second connection point to the other end of the second image signal line is a sixth wiring length, The longest wiring length of the fifth wiring length and the sixth wiring length is shorter than the longest wiring length of the third wiring length and the fourth wiring length.

2. The electro-optical device according to claim 1, wherein: The first incoming image signal line has a first widened portion, The second incoming image signal line has a second widened portion, The width of the first widened portion is the same as the width of the second widened portion, The length of the first widened portion is shorter than the length of the second widened portion.

3. The electro-optical device according to claim 1, wherein: The first incoming image signal line has a first widened portion, The second incoming image signal line has a second widened portion, The length of the first widened portion is the same as the length of the second widened portion, The width of the first widened portion is smaller than the width of the second widened portion.

4. The electro-optical device according to claim 2 or 3, wherein: The first widened portion and the second widened portion are arranged at positions that do not overlap with the data line driving circuit in a plan view. 5 . An electronic device comprising the electro-optical device according to claim 1 .

Images