Numerical control equipment cooperative scheduling method and system based on heterogeneous computing architecture

Abstract

The invention relates to a numerical control equipment cooperative scheduling method and system based on a heterogeneous computing architecture, and aims to solve the core problems of multi-brand numerical control equipment protocol isomerism, weak digital twin generalization ability, low multi-objective optimization efficiency, quantum era communication security and the like in the industrial internet. Real-time analysis and unified format conversion of 18 industrial protocols are realized through a PDSA-Chip hardware-level protocol conversion module; in combination with a transfer learning digital twinning technology, cross-brand equipment parameter self-calibration is completed within 72 hours; a quantum annealing and NSGA-III collaborative optimization algorithm is adopted, the machining parameter optimization period is shortened to 1 / 3 of that of a traditional method, energy consumption, precision and the service life of a tool are dynamically balanced, and the service life of the tool is prolonged by 37% in a high-load scene; an NTRU lattice encryption and chaos confusion fused anti-quantum security communication system is constructed, the G code confusion degree is larger than 98%, and SL3-level quantum attacks are defended.

Description

Technical Field

[0001] The present invention relates to the field of numerical control manufacturing technology, and specifically to a method and system for collaborative scheduling of numerical control equipment based on a heterogeneous computing architecture. Background Art

[0002] With the development of the industrial Internet, the demand for intelligent scheduling of numerical control equipment has become increasingly prominent. The existing technologies have the following bottlenecks:

[0003] Protocol heterogeneity problem: Multi-brand numerical control equipment (such as Fanuc, Siemens) uses proprietary communication protocols (Modbus, OPCUA, etc.). The traditional software protocol stack has low conversion efficiency (delay > 100 μs) and high power consumption (≥5 W), making it difficult to meet real-time requirements.

[0004] Weak generalization ability of digital twin: Existing digital twin models rely on single-device data training. Cross-brand parameter migration requires manual intervention and has a long adaptation period (> 15 days), making it difficult to support rapid equipment deployment.

[0005] Limitations in the performance of optimization algorithms: Classic heuristic algorithms (such as genetic algorithms) have a slow convergence speed in multi-objective machining parameter optimization and cannot balance the dynamic constraints of energy consumption, accuracy, and tool life.

[0006] Security threats in the quantum era: Traditional RSA encryption faces the risk of being cracked by quantum computers, and the transmission security of industrial control instructions (such as G-code) urgently requires post-quantum encryption technology for protection.

[0007] Therefore, a method and system for collaborative scheduling of numerical control equipment based on a heterogeneous computing architecture are needed to solve the above problems. Summary of the Invention

[0008] In order to solve the problems of the existing technology, the present invention provides a method and system for collaborative scheduling of numerical control equipment based on a heterogeneous computing architecture.

[0009] In order to solve the above technical problems, the present invention is realized through the following technical solutions: A method for collaborative scheduling of numerical control equipment based on a heterogeneous computing architecture, characterized by comprising the following steps:

[0010] S1. Protocol heterogeneous processing: Perform hardware-level protocol conversion on the industrial protocols of multi-source numerical control equipment through an embedded hardware chip (PDSA-Chip), and perform the following operations:

[0011] Identify the protocol features of Modbus, OPCUA, and MTConnect protocols based on a fuzzy matching algorithm;

[0012] Convert the heterogeneous protocols into a unified data format through an FPGA logic circuit, with a conversion delay ≤ 35 μs;

[0013] S2. Edge Digital Twin Construction: Generate digital twins synchronously at the edge computing nodes of the device side, including:

[0014] Collect physical parameters such as spindle vibration, temperature, and tool wear in real time;

[0015] Self-calibrate the dynamic parameters of the twin body within 72 hours through a transfer learning model, with the model generalization error < 2%;

[0016] S3. Quantum Collaborative Optimization: Perform multi-objective machining optimization at the cloud scheduling layer, specifically including:

[0017] Input the device status data into the preprocessing module of the quantum annealing algorithm to generate an initial Pareto solution set;

[0018] Use the NSGA-III algorithm to perform multi-dimensional optimization on machining parameters (spindle speed, feed rate, cutting depth), and the objective function covers energy consumption, accuracy, and tool life;

[0019] S4. Quantum-Resistant Secure Transmission: Send the optimization instructions through the secure communication layer, including:

[0020] Encrypt the instruction stream based on lattice-based cryptography to generate post-quantum key pairs;

[0021] Use the chaotic encryption algorithm to dynamically obfuscate the G code, with the obfuscation degree > 98%;

[0022] Among them, steps S1 - S4 are implemented for hardware acceleration through heterogeneous computing units (FPGA + NPU), and the end-to-end system delay ≤ 20ms.

[0023] In this aspect, the protocol conversion of traditional CNC equipment relies on software middleware (such as OPC servers), which has problems of high CPU resource occupancy and large conversion delay. This method breaks through the performance bottleneck of the software protocol stack through hardware-level protocol fuzzy matching.

[0024] PDSA-Chip Architecture:

[0025] Hardware Composition: Xilinx Zynq UltraScale+ MPSoC chip, integrated with a dual-core ARM Cortex-A53 processor and a programmable logic unit (PL);

[0026] Protocol Feature Library: Burn the message structure templates of 18 industrial protocols (Modbus address mapping table, OPC UA node ID database);

[0027] Real-Time Conversion Process:

[0028] Input data frame → CRC check → Protocol feature extraction (message header length / check bit type) → FPGA fuzzy matching → Unified JSON format output

[0029] Performance metrics: Conversion latency ≤ 35 μs (measured average value 28.4 μs), power consumption 1.2 W (traditional solution ≥ 5 W).

[0030] Edge digital twin synchronization mechanism:

[0031] Data acquisition:

[0032] Vibration sensor: Kistler 8766A three-axis accelerometer, sampling rate 50 kHz, range ±500 g;

[0033] Temperature monitoring: FLIR A315 infrared thermal imager, spatial resolution 1.1 mrad, temperature measurement accuracy ±2 °C;

[0034] Transfer learning model:

[0035] Pre-training dataset: 10^6 sets of processing logs (rotation speed - torque - vibration relationship) of the Fanuc 30i system;

[0036] Fine-tuning stage: 3×10^4 sets of data of the target device (Siemens 840D), batch size 256, learning rate 1e-4;

[0037] Loss function: Mean squared error (MSE) combined with domain adaptation difference loss (MMDLoss).

[0038] Quantum-classical optimization collaboration:

[0039] Quantum preprocessing:

[0040] Hamiltonian encoding: Map the processing parameters (rotation speed n, feed rate f, cutting depth a_p) to spin variables:

[0041]

[0042] J is the coupling coefficient between parameters, and h is the device state weight;

[0043] D-Wave 2000Q parameters: Annealing time 200 μs, read 1000 times of sampling;

[0044] NSGA-III optimization:

[0045] Population size 500, crossover probability 0.85 (simulated binary crossover), mutation probability 0.15 (polynomial mutation);

[0046] Constraint conditions: Spindle power ≤ 22 kW, tool stress < 1200 MPa.

[0047] Quantum-resistant secure transmission:

[0048] NTRU encryption parameters:

[0049]

[0050]

[0051] Chaotic confusion process:

[0052] Original G-code → ASCII to binary → Split by byte → Generate Logistic chaotic sequence → XOR operation → Circular shift → Ciphertext output

[0053] Security performance: Passed the NIST SP800-208 test, and the quantum-resistant attack strength reached level SL3.

[0054] In a specific implementation of the first aspect, the fuzzy matching algorithm in step S1 is specifically:

[0055] Construct a protocol feature vector space, and the dimensions include: message header length, check bit type, data frame interval;

[0056] Use cosine similarity to calculate the protocol matching degree, and the similarity threshold is set to 0.93;

[0057] When an unknown protocol is detected, start the deep learning protocol prediction model accelerated by NPU, where the protocol recognition accuracy rate ≥ 99.2%.

[0058] In a specific implementation of the first aspect, the transfer learning model in step S2 includes:

[0059] Source domain model pre-training: Train an LSTM network based on the machining data of the Fanuc 30i system;

[0060] Target domain adaptation: Align the feature distributions of the Siemens 840D system through domain-adversarial training;

[0061] Model fine-tuning: Update the parameters of the fully connected layer using 3×10^4 groups of data collected by the target device.

[0062] In a specific implementation of the first aspect, the cooperation method of the quantum annealing algorithm and NSGA-III in step S3 is:

[0063] Quantum annealing module preprocessing: Solve the Hamiltonian of the machining parameter combination on a D-Wave quantum computer;

[0064] Classical optimization module refinement: Use the solution output by quantum annealing as the initial population of the NSGA-III algorithm;

[0065] Dynamic weight adjustment: Adjust the optimization weight ratio of energy consumption and accuracy according to the real-time load status of the device.

[0066] In a second aspect, a collaborative scheduling system for numerical control equipment based on a heterogeneous computing architecture includes:

[0067] Protocol adaptation module: An embedded hardware unit integrating PDSA-Chip chips, supporting at least 18 industrial protocol conversions;

[0068] Edge computing module: A heterogeneous computing node (FPGA + ARM architecture) deployed on the device side, running a digital twin engine;

[0069] Collaborative scheduling module: A cloud server cluster, including a quantum computing interface and a multi-objective optimization algorithm library;

[0070] Secure communication module: An industrial switch supporting post-quantum encryption protocols, with a built-in chaotic encryption coprocessor;

[0071] The connection relationship between each component is as follows:

[0072] The protocol adaptation module is connected to the numerical control equipment through an industrial Ethernet;

[0073] The edge computing module is directly connected to the protocol adaptation module through a PCIe4.0 bus;

[0074] The collaborative scheduling module communicates with the edge computing module through TSN (Time-Sensitive Network);

[0075] The secure communication module is integrated between the protocol adaptation module and the collaborative scheduling module.

[0076] In a specific implementation of the second aspect, the PDSA-Chip chip includes:

[0077] Protocol recognition unit: A fuzzy matching circuit based on hardware acceleration;

[0078] Data conversion unit: Supports the mutual conversion between IEEE754 floating-point format and G-code instructions;

[0079] Secure storage unit: A device-unique identification code generated by a physically unclonable function (PUF).

[0080] In a specific implementation of the second aspect, the implementation method of the digital twin engine is:

[0081] Physical simulation layer: A cutting dynamics model based on finite element analysis;

[0082] Data-driven layer: An LSTM prediction network integrating a transfer learning framework;

[0083] Control Interface Layer: Interacts with the PLC controller in real time through the OPC UA protocol.

[0084] In a specific implementation of the second aspect, the encryption process of the secure communication module includes:

[0085] Key Generation: Lattice Public Key Infrastructure (PKI) based on the NTRU algorithm;

[0086] Dynamic Confusion: Performs a non-linear transformation on the numerical control instruction stream using an improved Logistic chaotic map;

[0087] Integrity Verification: Verifies the packet hash value through a blockchain smart contract.

[0088] In a specific implementation of the second aspect, the hardware architecture of the heterogeneous computing unit is:

[0089] FPGA Part: Implements the hardware logic circuit for protocol conversion and chaotic encryption;

[0090] NPU Part: Runs matrix acceleration calculations for the transfer learning model and vibration compensation algorithm;

[0091] Data Exchange Channel: Implements zero-copy data transfer between the FPGA and the NPU using the AXI-Stream bus.

[0092] In the third aspect, a numerical control processing device includes a numerical control device collaborative scheduling system based on a heterogeneous computing architecture and is applied to a five-axis linkage machining center, a turning-milling compound machine tool, or a laser cutting device.

[0093] The beneficial effects of the present invention are:

[0094] 1. The present invention realizes industrial protocol conversion through the hardware-level PDSA-Chip chip, reduces the power consumption of traditional software middleware from more than 5W to 1.2W, compresses the conversion delay from the microsecond level to an average of 28.4 μs, supports parallel processing of 18 protocols, and significantly reduces the communication bottleneck of industrial networks; the digital twin technology based on transfer learning realizes cross-brand device parameter self-calibration within 72 hours (such as Fanuc → Siemens), with a model generalization error < 2%, breaks through the limitation of traditional digital twin relying on single-device data training, and reduces the cost of enterprise equipment upgrade and transformation; the quantum-classical hybrid optimization framework shortens the processing parameter optimization cycle to 1 / 3 of the traditional algorithm. Through the dynamic weight adjustment mechanism, the tool life can be increased by 37%, the energy consumption can be reduced by 18%, and the machining accuracy fluctuation can be controlled within the range of ±5 μm in high-load device scenarios.

[0095] 2. The FPGA+NPU hardware architecture enables parallel processing of protocol conversion, encryption operations, and AI inference, with an end-to-end latency ≤ 20ms, achieving a performance improvement of over 40 times compared to the pure CPU solution. Among them, the AXI-Stream bus enables zero-copy data transfer, achieving a data throughput of 8Gbps at the edge computing node; the NTRU lattice encryption and improved Logistic chaotic mapping technology are adopted to build a post-quantum secure communication system, which has passed the NIST SP800-208 security certification, can resist quantum computer attacks (SL3 level), and at the same time achieves a G-code confusion degree > 98%, ensuring the transmission security of industrial control instructions; the system supports the access of multiple types of devices such as five-axis linkage machining centers and turning-milling compound machine tools, realizes the unique identification of devices through physical unclonable functions (PUF), and combines blockchain hash verification technology to build a traceable industrial Internet of Things security ecosystem. Description of the Drawings

[0096] Figure 1 It is a schematic diagram of the overall system architecture of the present invention.

[0097] Figure 2 It is a schematic diagram of the internal structure of the PDSA-Chip of the present invention.

[0098] Figure 3 It is a schematic diagram of the quantum-classical optimization process of the present invention.

[0099] Figure 4 It is a schematic diagram of the digital twin hierarchical architecture of the present invention.

[0100] Figure 5 It is a schematic diagram of the anti-quantum secure timing of the present invention.

[0101] Figure 6 It is a schematic diagram of the heterogeneous computing topology of the present invention. Detailed Embodiments

[0102] Next, in combination with the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0103] As Figures 1 to 6 shown, a numerical control equipment collaborative scheduling method and system based on a heterogeneous computing architecture.

[0104] Please refer to Figure 1 shown. This system adopts a four-layer heterogeneous computing architecture to achieve a full-process closed-loop from data acquisition to optimized control of numerical control equipment:

[0105] Protocol Adaptation Layer

[0106] Hardware Configuration: Xilinx Zynq UltraScale+ MPSoC chip (PDSA-Chip module configured on the PL side)

[0107] Protocol Conversion Process:

[0108] The input device data frame (such as Modbus RTU message) is transmitted to the PDSA-Chip through the EtherCAT bus (cycle 1ms);

[0109] The hardware fuzzy matching circuit extracts the message header features (start bit length, checksum type, etc.) and compares them with 18 pre-stored protocol templates;

[0110] The FPGA logic circuit performs format conversion (Modbus→JSON), and the conversion delay is measured to be 28.4μs (standard deviation ±3.2μs);

[0111] Output a unified format data stream to the edge computing layer, with a bandwidth utilization rate ≥95%.

[0112] Edge Computing Layer

[0113] Hardware Platform: NVIDIA Jetson AGX Orin (computing power 200 TOPS, memory 32GB LPDDR5)

[0114] Digital Twin Construction:

[0115] Real-time collect spindle vibration (Kistler 8766A, 50kHz) and tool temperature (FLIR A315, 0.1℃ accuracy) data;

[0116] Based on the LSTM model of transfer learning (input layer 128 nodes, hidden layer 256 nodes) to predict the device status, complete cross-brand parameter migration (Fanuc→Siemens) within 72 hours, and the model verification error is 1.8%;

[0117] Microsecond-level vibration compensation: Adjust the G-code trajectory according to the prediction deviation, and the compensation response time ≤50μs.

[0118] Collaborative Scheduling Layer

[0119] Quantum-Classical Optimization Process:

[0120] Quantum preprocessing: Encode the processing parameters into the Ising model (coupling coefficient J = 0.75, magnetic field strength h = 0.3) on the D-Wave 2000Q quantum computer to generate an initial solution set (1000 samples);

[0121] NSGA-III Iteration: population size 500, crossover rate 0.85 (simulated binary crossover), mutation rate 0.15 (polynomial mutation);

[0122] Dynamic weight adjustment: when the spindle power > 80% of the rated value, the energy consumption weight α increases from 0.5 to 0.7, and the optimized tool life is increased by 37%.

[0123] Secure communication layer

[0124] Quantum-resistant encryption process:

[0125] Key exchange: the NTRU algorithm (modulus q = 2^31, polynomial degree n = 743) generates public / private key pairs;

[0126] Chaotic confusion: improved Logistic mapping (μ = 3.92, fractal parameter 0.02) iterates 256 times, and the confusion degree is 98.3%;

[0127] Blockchain verification: Hyperledger Fabric verifies data hashes (SHA3-512), and the forged instruction interception rate is 100%.

[0128] II. Key module technical parameters

[0129] Please refer to Figure 2 the PDSA-Chip protocol conversion module shown.

[0130]

[0131] Please refer to Figure 4 the digital twin engine shown

[0132]

[0133] Please refer to Figure 6 shown: heterogeneous computing unit

[0134]

[0135] III. Core algorithm implementation details 1. Quantum-classical hybrid optimization ( Figure 3 )

[0136] Hamiltonian encoding formula:

[0137]

[0138] where s_i ∈ {-1, 1} represents the machining parameter state (rotation speed, feed rate, etc.), and J_{ij} is the coupling coefficient between parameters.

[0139] NSGA-III constraint conditions:

[0140] Spindle power ≤ 22kW (hard constraint)

[0141] Tool stress ≤ 1200 MPa (based on material fatigue limit).

[0142] Please refer to Figure 4 the migration learning model training shown

[0143] Domain adversarial training parameters:

[0144] Insertion position of the Gradient Reversal Layer (GRL): After the 3rd layer of LSTM

[0145] Adversarial loss weight λ: Initially 0.5, increasing by 0.05 per epoch to 1.0

[0146] Optimizer: Adam (lr = 1e-4, β1 = 0.9, β2 = 0.999).

[0147] Please refer to Figure 5 the chaotic encryption algorithm shown

[0148] Improved formula of Logistic mapping:

[0149] x n+1 = μx n (1 - x n ) + 0.02sin(2πx n ).

[0150] The initial value x_0 is generated from the NTRU public key hash value;

[0151] The iteration result generates a chaotic sequence, which is bitwise XORed with the ASCII characters of the G-code.

[0152] This technical solution forms a practical CNC Internet of Things system through the closed-loop of four core technologies: hardware acceleration protocol conversion, edge digital twin, quantum optimization decision-making, and quantum-resistant secure transmission. All technical parameters have been verified by a third-party laboratory and meet the conditions for industrial mass production.

[0153] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for collaborative scheduling of numerical control equipment based on heterogeneous computing architecture, characterized in that: The following steps are involved: S1. Protocol heterogeneity processing: Perform hardware-level protocol conversion on the industrial protocols of multi-source CNC equipment through an embedded hardware chip (PDSA-Chip), and perform the following operations: Identify Modbus, OPCUA, and MTConnect protocol features based on fuzzy matching algorithms; Convert heterogeneous protocols into a unified data format through FPGA logic circuits, with a conversion delay of ≤35μs; S2. Edge digital twin construction: Synchronously generate digital twins at the edge computing node on the device side, including: Real-time collection of physical parameters such as spindle vibration, temperature, and tool wear; The transfer learning model can self-calibrate the twin dynamic parameters within 72 hours, and the model generalization error is less than 2%; S3. Quantum collaborative optimization: Perform multi-objective processing optimization in the cloud scheduling layer, including: Input the device state data into the quantum annealing algorithm preprocessing module to generate an initial Pareto solution set; The NSGA-III algorithm is used to perform multi-dimensional optimization of machining parameters (speed, feed rate, cutting depth), and the objective function covers energy consumption, accuracy, and tool life; S4. Quantum-resistant secure transmission: Optimization instructions are issued through the secure communication layer, including: Generate post-quantum keys based on Lattice-based cryptography to encrypt instruction streams; Adopt chaotic encryption algorithm to dynamically obfuscate G code, with obfuscation degree > 98%; Among them, steps S1-S4 are hardware accelerated through heterogeneous computing units (FPGA+NPU), and the end-to-end system delay is ≤20ms.

2. The method for collaborative scheduling of numerical control equipment based on heterogeneous computing architecture according to claim 1, characterized in that: The fuzzy matching algorithm in step S1 is specifically: Construct a protocol feature vector space, the dimensions of which include: message header length, check bit type, and data frame interval; The cosine similarity was used to calculate the protocol matching, and the similarity threshold was set to 0.93; When an unknown protocol is detected, the NPU-accelerated deep learning protocol prediction model is launched with a protocol recognition accuracy of ≥ 99.2%.

3. The method for collaborative scheduling of numerical control equipment based on heterogeneous computing architecture according to claim 1, characterized in that: The transfer learning model in step S2 includes: Source domain model pre-training: LSTM network training based on FANUC 30i system processing data; Target domain adaptation: Align the feature distribution of Siemens 840D system through domain adversarial training; Model fine-tuning: Use 3×10^4 sets of data collected from the target device to update the parameters of the fully connected layer.

4. The method for collaborative scheduling of numerical control equipment based on heterogeneous computing architecture according to claim 1, characterized in that: The coordination mode of the quantum annealing algorithm and NSGA-III in step S3 is: Quantum annealing module preprocessing: solving the Hamiltonian of the processing parameter combination on the D-Wave quantum computer; Classical optimization module refinement: The quantum annealing output solution is used as the initial population of the NSGA-III algorithm; Dynamic weight adjustment: Adjust the optimal weight ratio of energy consumption and accuracy according to the real-time load status of the device.

5. A CNC equipment collaborative scheduling system based on heterogeneous computing architecture, characterized by: include: Protocol adapter module: an embedded hardware unit with integrated PDSA-Chip chip, supporting at least 18 industrial protocol conversions; Edge computing module: a heterogeneous computing node (FPGA+ARM architecture) deployed on the device side to run the digital twin engine; Collaborative scheduling module: cloud server cluster, including quantum computing interface and multi-objective optimization algorithm library; Secure communication module: industrial switch supporting post-quantum encryption protocol and built-in chaos encryption coprocessor; The connection relationship between the components is as follows: The protocol adapter module connects to the CNC equipment via industrial Ethernet; The edge computing module and the protocol adapter module are directly connected via the PCIe4.0 bus; The collaborative scheduling module communicates with the edge computing module through TSN (time-sensitive network); The secure communication module is integrated between the protocol adaptation module and the collaborative scheduling module.

6. The CNC equipment collaborative scheduling system based on heterogeneous computing architecture according to claim 5 is characterized in that: The PDSA-Chip comprises: Protocol identification unit: fuzzy matching circuit based on hardware acceleration; Data conversion unit: supports conversion between IEEE754 floating point format and G code instructions; Secure storage unit: A device-unique identification code generated by a physically unclonable function (PUF).

7. The CNC equipment collaborative scheduling system based on heterogeneous computing architecture according to claim 5 is characterized in that: The digital twin engine is implemented as follows: Physical simulation layer: cutting dynamics model based on finite element analysis; Data-driven layer: LSTM prediction network integrating transfer learning framework; Control interface layer: Real-time interaction with PLC controller through OPC UA protocol.

8. The CNC equipment collaborative scheduling system based on heterogeneous computing architecture according to claim 5 is characterized in that: The encryption process of the secure communication module includes: Key generation: Lattice public key infrastructure (PKI) based on NTRU algorithm; Dynamic obfuscation: Improved Logistic chaotic mapping is used to perform nonlinear transformation on CNC instruction stream; Integrity verification: Verify the data packet hash value through the blockchain smart contract.

9. The CNC equipment collaborative scheduling system based on heterogeneous computing architecture according to claim 5 is characterized in that: The hardware architecture of the heterogeneous computing unit is: FPGA part: hardware logic circuit to realize protocol conversion and chaos encryption; NPU part: runs the matrix acceleration calculation of the transfer learning model and vibration compensation algorithm; Data exchange channel: AXI-Stream bus is used to achieve zero-copy data transmission between FPGA and NPU.

10. A CNC machining equipment, characterized in that: A collaborative scheduling system for CNC equipment based on a heterogeneous computing architecture comprises the system as described in any one of claims 5 to 9, and is applied to a five-axis machining center, a turning-milling machine tool or a laser cutting equipment.

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