Display panel

Abstract

A display panel is provided with a display area, an external circuit area, a first circuit area and a second circuit area. The external circuit area is located at the edge of the display panel, and the first circuit area is located between the external circuit area and the second circuit area. The display panel comprises a pixel array, a plurality of gate drive circuit groups, a plurality of first signal line groups and a plurality of second signal line groups. The gate drive circuit group is arranged between the second line area and the display area. The first signal line group extends from the external circuit area to the first circuit area and the second circuit area. The second signal line group extends from the second line area and is connected to the corresponding gate drive circuit group. In the second circuit area, a first part of the first signal line group overlapped with the second signal line group has a first width, a second part of the first signal line group not overlapped with the second signal line group has a third width, the third width is larger than the first width, and the width of the overlapped contact part of the second signal line group and the first signal line group is the same.

Description

[0001] This application is a divisional application. The application number of its parent application is 201811034539.3, the applicant is AU Optronics Corp., the application date is September 5, 2018, and the invention title is Display Panel. Technical Field

[0002] The present invention relates to a display panel, and more particularly to a display panel with a gradient circuit design. Background Art

[0003] In recent years, display panels with high resolution and large size have gradually attracted market attention. However, as the size of the display panel increases, the length of the signal lines also increases, so it is necessary to increase the width of the signal lines to reduce their resistance. In addition, as the resolution of the display panel increases, under the limitation that the scanning frequency cannot be reduced, the number of signal lines must also increase to avoid insufficient charging time of the capacitance resulting in a reduction in the image quality of the display screen.

[0004] However, increasing the width and number of signal lines will lead to an increase in the cross-line capacitance between the signal lines, resulting in problems such as an increase in the operating temperature of the driving circuit and a delay in the overall output signal. Therefore, how to effectively suppress the increase in cross-line capacitance without sacrificing the circuit layout space is one of the problems that current R & D personnel urgently want to solve. Summary of the Invention

[0005] The present invention provides a display panel that can effectively suppress the increase in cross-line capacitance.

[0006] An embodiment of the present invention provides a display panel having a display area, a first circuit area, a second circuit area, and an external circuit area. The external circuit area is located at the edge of the display panel, and the first circuit area is located between the external circuit area and the second circuit area. The display panel includes a pixel array, a plurality of gate driver circuit groups, a plurality of first signal line groups, and a plurality of second signal line groups. The pixel array is disposed in the display area. The gate driver circuit groups are disposed between the second circuit area and the display area, and the gate driver circuit groups are electrically connected to the pixel array. The first signal line groups extend from the external circuit area to the first circuit area and the second circuit area. The second signal line groups extend from the second circuit area and are connected to the corresponding gate driver circuit groups. The second signal line groups are respectively connected to the corresponding first signal line groups, and a part of the second signal line groups overlaps with the first signal line groups. In the second circuit area, a first part of the first signal line group that overlaps with the second signal line group has a first width, and a second part of the first signal line group that does not overlap with the second signal line group has a third width, where the third width is greater than the first width.

[0007] Another embodiment of the present invention provides a display panel, which has a display area, a first circuit area, a second circuit area, and an external circuit area. The external circuit area is located at the edge of the display panel, and the first circuit area is located between the external circuit area and the second circuit area. The display panel includes a pixel array, a plurality of gate driving circuit groups, a plurality of first signal line groups, and a plurality of second signal line groups. The pixel array is disposed in the display area. The gate driving circuit groups are disposed between the second circuit area and the display area, and the gate driving circuit groups are electrically connected to the pixel array. The first signal line groups extend from the external circuit area to the first circuit area and the second circuit area. The second signal line groups extend from the second circuit area and are connected to the corresponding gate driving circuit groups. The second signal line groups are respectively connected to the corresponding first signal line groups, and a part of the second signal line groups overlaps with the first signal line groups. The first part of the first signal line groups overlapping with the second signal line groups has a first width, and the first signal line groups have a second width in the first circuit area, and the first widths of the first signal line groups at different positions on the panel may be different from each other.

[0008] Based on the above, in the display panel of the above embodiment of the present invention, for the second circuit area, the first part of the first signal line groups overlapping with the second signal line groups has a first width, and the second part of the first signal line groups not overlapping with the second signal line groups has a third width greater than the first width. In this way, the rising amplitude of the cross-line capacitance between the first signal line groups and the second signal line groups can be effectively suppressed, so that the gate driving circuit has good output performance.

[0009] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but it is not intended to limit the present invention. Description of the Drawings

[0010] Figure 1 It is a top view schematic diagram of a display panel according to an embodiment of the present invention.

[0011] Figure 2A It is Figure 1 an enlarged view of the area enclosed by the dashed line R in

[0012] Figure 2B It is Figure 1 an enlarged view of the area enclosed by the dashed line WR1 in

[0013] Figure 2C It is a schematic diagram of the first width of the first signal line groups changing with the number of stages of the gate driving circuit groups.

[0014] Figure 3 It is a curve diagram of the first width changing with the number of stages of the gate driving circuit groups.

[0015] Among them, reference numerals:

[0016] 100: Display panel

[0017] 102: Substrate

[0018] 104: Pixel array

[0019] 106: Gate driving circuit group

[0020] 106a, 106b, 106c: Gate driving circuit

[0021] 108: First signal line group

[0022] 108a, 108b, 108c, 108d: First signal line

[0023] 110: Second signal line group

[0024] 110a, 110b, 110c: Second signal line

[0025] DR: Display area

[0026] WR1: First circuit area

[0027] WR2: Second circuit area

[0028] PR: External circuit area

[0029] PX: Sub-pixel

[0030] SL: Scanning line

[0031] DL: Data line

[0032] TFT: Active element

[0033] PE: Pixel electrode

[0034] W1, W1a, W1b, W1c: First width

[0035] W2: Second width

[0036] W3: Third width Detailed implementation manners

[0037] The structural principle and working principle of the present invention will be specifically described below with reference to the accompanying drawings:

[0038] The present invention will be described more fully hereinafter with reference to the drawings of the present embodiment. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The thicknesses of the layers and regions in the drawings are enlarged for clarity. The same or similar reference numerals denote the same or similar elements, and will not be described repeatedly in the following paragraphs. In addition, the directional terms mentioned in the embodiments, such as: up, down, left, right, front or back, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0039] Figure 1 It is a top view schematic diagram of a display panel according to an embodiment of the present invention. Figure 2A is Figure 1 an enlarged view of the region enclosed by the dashed line R in Figure 2B is Figure 1 an enlarged view of the region enclosed by the dashed line WR1 in Figure 3 It is a graph showing the variation of the first width with the number of stages of the gate driving circuit group.

[0040] Please refer to Figure 1 , the display panel 100 has a display area DR, a first wiring area WR1, a second wiring area WR2, and an external circuit area PR. The external circuit area PR can be located at the edge of the display panel 100, and the external circuit area PR can have circuit contacts or driving elements. In the present embodiment, the driving elements in the external circuit area PR can be arranged on the front surface of the substrate 102 (for example, the surface facing the viewer) by surface mount technique (SMT), but the present invention is not limited thereto. In other embodiments, the driving elements in the external circuit area PR can also be arranged on the back surface of the substrate 102 (for example, the surface facing away from the viewer) by a flexible printed circuit (FPC). In the present embodiment, the first wiring area WR1 is located between the external circuit area PR and the second wiring area WR2. In other words, in terms of relative position, the first wiring area WR1 is closer to the external circuit area PR and the second wiring area WR2 is farther from the external circuit area PR. In some embodiments, the signal lines (such as HC signal lines) in the first wiring area WR1 can be cascaded with the driving elements in the external circuit area PR in a wire on array (WOA) manner. That is, the first wiring area WR1 can also be referred to as the WOA area.

[0041] The display panel 100 may include a pixel array 104, a plurality of gate driver circuit groups 106, a plurality of first signal line groups 108, and a plurality of second signal line groups 110. In some embodiments, the pixel array 104, the plurality of gate driver circuit groups 106, the plurality of first signal line groups 108, and the plurality of second signal line groups 110 may be respectively disposed on a substrate 102. The material of the substrate 102 may be a glass substrate, a quartz substrate, or an organic polymer substrate, and the present invention is not limited thereto.

[0042] The pixel array 104 is disposed in the display area DR. The pixel array 104 includes a plurality of sub-pixels PX arranged in an array, a plurality of scan lines SL, and a plurality of data lines DL. In the present embodiment, the sub-pixels PX may be electrically connected to the corresponding scan lines SL and data lines DL, and the scan lines SL and the data lines DL may intersect each other. In some embodiments, the sub-pixels PX may include active elements TFTs and pixel electrodes PE, wherein the active elements TFTs may be electrically connected to the pixel electrodes PE. The active elements TFTs may include gates, sources, and drains. In the present embodiment, the gates of the active elements TFTs may be electrically connected to the corresponding scan lines SL; the sources of the active elements TFTs may be electrically connected to the corresponding data lines DL; the drains D of the active elements TFTs may be electrically connected to the corresponding pixel electrodes PE. In some embodiments, the gates of the active elements TFTs and the scan lines SL may be formed of the same patterned conductive layer, and the scan lines SL and the data lines DL may belong to different patterned conductive layers. The active elements TFTs may be bottom-gate transistors, top-gate transistors, three-dimensional transistors, or other suitable transistors. In some embodiments, the pixel electrodes PE may selectively include a plurality of slits (not shown) having different extending directions or a plurality of slits having substantially the same extending direction, but the present invention is not limited thereto.

[0043] The gate driver circuit groups 106 are disposed between the second circuit area WR2 and the display area DR, and the gate driver circuit groups 106 are electrically connected to the pixel array 104. For example, the gate driver circuit groups 106 are electrically connected to the corresponding scan lines SL and are electrically connected to the gates in the active elements TFTs. In the present embodiment, the gate driver circuit groups 106 may be arranged along the extending direction of the data lines DL. In some embodiments, each of the gate driver circuit groups 106 may include a plurality of gate driver circuits 106a to 106c. In some embodiments, when forming the active elements TFTs in the pixel array 104, the active elements of the gate driver circuits 106a to 106c may be formed in the second circuit area WR2 at the same time, so that the large-area gate driver ICs can be replaced, thereby reducing the border width of the display panel 100. It should be noted that Figure 2AThe gate drive circuit group 106 is described by taking three gate drive circuits 106a - 106c as an example, but the present invention is not limited thereto. The number of gate drive circuits in each gate drive circuit group 106 can be appropriately adjusted according to the design. In addition, the number of gate drive circuit groups 106 can also be appropriately adjusted according to the size or resolution of the display panel 100.

[0044] The first signal line group 108 extends from the external circuit area PR to the first circuit area WR1 and the second circuit area WR2. In some embodiments, the extension direction of the first signal line group 108 disposed in the first circuit area WR1 may be different from the extension direction of the first signal line group 108 disposed in the second circuit area WR2 (as Figure 1 shown). In some embodiments, the first signal line group 108 may include a start signal line, a high-frequency signal line, a low-frequency signal line, a low-level signal line, a constant voltage signal line, or a combination thereof. In some embodiments, the temperature of the first signal line group 108 in the first circuit area WR1 may be lower than 45°C to avoid safety problems of the display panel 100 due to excessive temperature. In some embodiments, the first signal line group 108 may be electrically connected to a driving element disposed in the external circuit area PR. In this embodiment, each first signal line group 108 may include a plurality of first signal lines 108a - 108d. It should be noted that Figure 2A the first signal line group 108 is described by taking four first signal lines 108a - 108d as an example, but the present invention is not limited thereto. The number of first signal lines in each first signal line group 108 can be appropriately adjusted according to the design. In addition, the number of first signal line groups 108 can also be appropriately adjusted according to the size or resolution of the display panel 100. In this embodiment, the first signal line group 108 may be electrically connected to the corresponding driving elements DV in the external circuit area PR respectively. For example, the first signal line group 108 is connected to the driving element DV through the corresponding pads PD respectively (as Figure 2B shown).

[0045] The second signal line group 110 extends from the second wiring region WR2 and is connected to the corresponding gate driving circuit group 106, wherein the second signal line group 110 is respectively connected to the corresponding first signal line group 108, and the second signal line group 110 partially overlaps the first signal line group 108. In this embodiment, the second signal line group 110 can overlap with the first signal line group 108 disposed in the second wiring region WR2, while the first signal line group 108 disposed in the first wiring region WR1 may not overlap with the second signal line group 110. In some embodiments, the second signal line group 110 and the first signal line group 108 may be partially staggered, and the second signal line group 110 and the first signal line group 108 may be disposed on different layers. In this embodiment, each second signal line group 110 may include a plurality of second signal lines 110a to 110c. It should be noted that Figure 2A the second signal line group 110 in

[0046] is illustrated by taking three second signal lines 110a to 110c as an example, but the present invention is not limited thereto, and the number of second signal lines in each second signal line group 110 can be appropriately adjusted according to the design. In addition, the number of second signal line groups 110 can also be appropriately adjusted according to the size or resolution of the display panel 100. Figure 1 、 Figure 2A and Figure 2B Please refer to

[0047] In the second wiring region WR2, the first signal line group 108 overlapping the first part of the second signal line group 110 has a first width W1, while the second part of the first signal line group 108 not overlapping the second signal line group 110 has a third width W3 greater than the first width W1. In this way, the rising amplitude of the crosstalk capacitance between the first signal line group 108 and the second signal line group 110 can be effectively suppressed, so that the gate driving circuit has good output performance. A B In some embodiments, the current of the first signal line group 108 in the first part is I

[0048] In addition, since the resistive-capacitive (RC) of the signal lines is uniformly distributed, the current of the first signal line group 108 will become smaller and smaller as it moves away from the signal source (such as the driving element in the external circuit region PR). Therefore, when the ratio of the first width W1 to the second width W2 is approximately equal to in the case of, the first width W1 between each first signal line group 108 can be different from each other. As shown in Figure 2C and Figure 3 , the first widths W1a, W1b, and W1c can become smaller and smaller as they move away from the signal source (W1c < W1b < W1a). In this way, the overlapping area between the first signal line group 108 and the second signal line group 110 can become smaller and smaller as it moves away from the signal source, effectively suppressing the increase in the cross-line capacitance between the first signal line group 108 and the second signal line group 110.

[0049] Based on the above, the display panel 100 can significantly improve the capacitive load of the overall signal lines without sacrificing any circuit layout space or changing the circuit design, enabling the gate driving circuit to not only have good output performance but also reduce its operating temperature.

[0050] In this embodiment, the magnitude of the current of the first signal line group 108 in the second circuit region WR2 is related to the number of stages of the gate driving circuit group 106. For example, the display panel 100 may include 270 stages of the gate driving circuit group 106, and each stage of the gate driving circuit group 106 includes a plurality of gate driving circuits (such as gate driving circuits 106a to 106c). Among them, the one closest to the external circuit region PR in the gate driving circuit group 106 is the 270th stage of the gate driving circuit group 106. The current of the first signal line group 108 used to connect the 270th stage of the gate driving circuit group 106 is approximately equal to the current of the first signal line group 108 in the first circuit region WR1 (270 / 270); and the current of the first signal line group 108 used to connect the 260th stage of the gate driving circuit group 106 is approximately equal to 99.3% of the current of the first signal line group 108 in the first circuit region WR1 (260 / 270). That is to say, the corresponding first width W1 can be calculated by the number of stages of the gate driving circuit group 106 and the width of the first signal line group 108 in the first circuit region WR1 (i.e., the second width W2).

[0051] In this embodiment, the first width W1 of the first signal line group 108 closest to the external circuit region PR can be greater than the first width W1 of the other first signal line group 108 far from the external circuit region PR. That is to say, the first width W1 of the first signal line group 108 can show a gradually decreasing trend as it moves away from the external circuit region PR (as shown in Figure 2C and Figure 3As shown. In addition, each first signal line group 108 may include a plurality of first signal lines 108a-108d, and the widths of the portions of the first signal lines 108a-108d that overlap the second signal line group 110 are all the same. In other words, the first widths W1 between each first signal line group 108 may be different from each other, but the first widths W1 of the first signal lines 108a-108d in each first signal line group 108 may be the same as each other, but the present invention is not limited thereto. In some other embodiments, the first widths W1 between each first signal line group 108 may be different from each other, and the first widths W1 of the first signal lines 108a-108d in each first signal line group 108 may be designed to be different from each other according to the current density.

[0052] In some embodiments, the second portion of the first signal line group 108 that does not overlap the second signal line group 110 has a third width W3, and the third width W3 is approximately equal to the second width W2, so that the first signal line group 108 has a good impedance match, thereby improving the quality of signal transmission. In this embodiment, the third width W3 may be greater than or equal to the first width W1. For example, the display panel 100 may include 270 levels of gate driving circuit groups 106. When the current used to connect the 270th level of gate driving circuit group 106 in the first signal line group 108 is approximately equal to the current in the first signal line group 108 in the first line region WR1 (270 / 270), the third width W3 may be approximately equal to the first width W1. In addition, when the current used to connect the 260th level of gate driving circuit group 106 in the first signal line group 108 is approximately equal to 99.3% of the current in the first signal line group 108 in the first line region WR1 (260 / 270), the third width W3 may be greater than the first width W1.

[0053] In some embodiments, the contours of the first signal line groups 108 may be selectively the same as each other, so that the first signal line groups 108 have a good impedance match, thereby improving the quality of signal transmission. For example, as the first signal line groups 108 are electrically connected to different levels of gate driving circuit groups 106, the number of times they are crossed by the second signal line group 110 is also different. As Figure 1 shown, the first signal line group 108 used to electrically connect to the gate driving circuit group 106 with a larger level (for example, the gate driving circuit group 106 closer to the external circuit region PR) has more times of being crossed by the second signal line group 110, so there are more width reduction points of the first signal line group 108, resulting in different contours of each first signal line group 108. However, in order to make the first signal line groups 108 have a good impedance match, the first signal line groups 108 may be selectively made to have the same contour.

[0054] In some embodiments, asFigure 3 As shown, after the first width W1 is reduced to the minimum value, it can no longer be reduced and remains at the minimum value. For example, for the first signal line group 108 connecting the gate driving circuit group 106 of the 200th stage, its first width W1 has reached the minimum value. Therefore, for the first signal line group 108 connecting the gate driving circuit group 106 of the 199th stage, its first width W1 will remain at the minimum value and will not continue to decrease. In this embodiment, the minimum value is illustrated by taking 10μm as an example, but the present invention is not limited thereto. In other embodiments, the above-mentioned minimum value can be appropriately adjusted according to the limits of the processing machine.

[0055] The features of the present invention will be described more specifically below with reference to Experimental Example 1 and Comparative Example 1. Although the following experimental examples are described, without departing from the scope of the present invention, the signal lines, materials, dimensions, test methods, test parameters, etc. used can be appropriately changed. Therefore, the present invention should not be restrictively interpreted by the embodiments described below.

[0056] Experimental Example 1

[0057] The information of the display panel of Experimental Example 1 is as follows.

[0058] Width of the active element in the gate driving circuit (T21 width): 21041μm

[0059] Second width (WWOA): 130μm

[0060] First width (Wbus_X_Over): 130μm to 10μm (as Figure 3 shown)

[0061] Comparative Example 1

[0062] The information of the display panel of Comparative Example 1 is as follows.

[0063] Width of the active element in the gate driving circuit (T21 width): 21041μm

[0064] Second width (WWOA): 130μm

[0065] First width (Wbus_X_Over): 130μm

[0066] Response time test

[0067] The reaction time of the HC signal line was tested for Experimental Example 1 and Comparative Example 1, and the experimental results are summarized in Table 1. The reaction time is obtained, for example, by the following test method, but is not limited thereto. The reaction time test uses an LCD5100 type luminance meter manufactured by Otsuka Electronics Co., Ltd. The light source is a halogen lamp. The low-pass filter is set to 5 kHz. The sample is placed in a TN element in a normally white mode with a cell gap of 5.0 μm and a twist angle of 80 degrees between two glass substrates. A rectangular wave (60 Hz, 5 V, 0.5 s) is applied to the element. At this time, light is irradiated on the element from the vertical direction, and the amount of light transmitted through the element is measured. When the amount of light reaches the maximum, it is regarded as a transmittance of 100%, and when the amount of light is the minimum, it is regarded as a transmittance of 0%. The rise time is the time required for the transmittance to change from 10% to 90%. The fall time is the time required for the transmittance to change from 90% to 10%. The reaction time is expressed as the sum of the rise time and the fall time thus obtained.

[0068] Cross-line capacitance test

[0069] The cross-line capacitance between the HC signal lines was tested for Experimental Example 1 and Comparative Example 1, and the experimental results are summarized in Table 1.

[0070] [Table 1]

[0071]

[0072]

[0073] As can be seen from Table 1, compared with Comparative Example 1, Experimental Example 1 with a gradually changing line width has better reaction time and smaller cross-line capacitance.

[0074] In summary, in the display panel of the above embodiment, for the second line region, the first part of the first signal line group overlapping the second signal line group has a first width, and the second part of the first signal line group not overlapping the second signal line group has a third width greater than the first width. In this way, the increase in the cross-line capacitance between the first signal line group and the second signal line group can be effectively suppressed, so that the gate driving circuit has good output performance.

[0075] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding changes and deformations should all fall within the protection scope of the appended claims of the present invention.

Claims

1. A display panel having a display area, a first circuit area, a second circuit area, and an external circuit area. The external circuit area is located at the edge of the display panel, and the first circuit area is located between the external circuit area and the second circuit area. It is characterized in that, The display panel includes: A pixel array disposed in the display area; A plurality of gate driver circuit groups disposed between the second circuit area and the display area, and the gate driver circuit groups are electrically connected to the pixel array; A plurality of first signal line groups extending from the external circuit area to the first circuit area and the second circuit area; and A plurality of second signal line groups extending from the second circuit area and connected to corresponding gate driver circuit groups, the second signal line groups are respectively connected to corresponding first signal line groups, and the second signal line groups partially overlap the first signal line groups, Wherein in the second circuit area, a first portion of the first signal line groups overlapping the second signal line groups has a first width, and a second portion of the first signal line groups not overlapping the second signal line groups has a third width, wherein the third width is greater than the first width and the width of the overlapping contact portion between the second signal line group and the first signal line group is the same.

2. The display panel according to claim 1, wherein And the current of these first signal line groups in the first part is I A , and these first signal line groups have a second width in the first circuit region, and the current of these first signal line groups in the first circuit region is I B , the ratio of the first width to the second width is approximately equal to 3. The display panel according to claim 2, characterized in that, The third width is approximately equal to the second width.

4. The display panel according to claim 1, wherein Wherein the first width between each of the first signal line groups can be different from each other.

5. The display panel according to claim 4, characterized in that, Wherein the first width of one of the first signal line groups adjacent to the external circuit area is greater than the first width of the other of the first signal line groups far from the external circuit area.

6. The display panel according to claim 1, characterized in that Wherein each first signal line group includes a plurality of first signal lines, and the widths of the first signal lines overlapping the first portion of the second signal line groups are all the same.

7. The display panel according to claim 1, characterized in that Wherein the first signal line groups include start signal lines, high-frequency signal lines, low-frequency signal lines, low-level signal lines or constant voltage signal lines.

8. A display panel having a display area, a first circuit area, a second circuit area, and an external circuit area, the external circuit area being located at an edge of the display panel, and the first circuit area being located between the external circuit area and the second circuit area, characterized in that, The display panel includes: A pixel array disposed in the display area; A plurality of gate driver circuit groups disposed between the second circuit area and the display area, and the gate driver circuit groups are electrically connected to the pixel array; A plurality of first signal line groups extending from the external circuit area to the first circuit area and the second circuit area; and A plurality of second signal line groups extending from the second circuit area and connected to corresponding gate driver circuit groups, the second signal line groups are respectively connected to corresponding first signal line groups, and the second signal line groups partially overlap the first signal line groups, A first portion of the first signal line groups overlapping the second signal line groups has a first width, and the first signal line groups have a second width in the first circuit area, and the first width between each of the first signal line groups is different from each other and the width of the overlapping contact portion between the second signal line group and the first signal line group is the same.

9. The display panel according to claim 8, wherein The current where the first signal line groups overlap the first part of the second signal line groups is I A , and the current of the first signal line groups in the first line region is I B , the ratio of the first width to the second width is approximately equal to 10. The display panel according to claim 8, wherein, Wherein in the second circuit area, a second portion of the first signal line groups not overlapping the second signal line groups has a third width, and the third width is approximately equal to the second width.

11. The display panel according to claim 10, characterized in that, Wherein the third width is greater than the first width.

12. The display panel according to claim 8, wherein Wherein the first width of one of the first signal line groups adjacent to the external circuit area is greater than the first width of the other of the first signal line groups far from the external circuit area.

13. The display panel according to claim 8, wherein Wherein each first signal line group includes a plurality of first signal lines, and the widths of the first signal lines overlapping the first portion of the second signal line groups are all the same.

14. The display panel according to claim 8, wherein Wherein, the first signal line groups include start signal lines, high-frequency signal lines, low-frequency signal lines, low-level signal lines or constant-voltage signal lines.

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