Shifting register, driving circuit, driving method and display device
By designing a shift register including input circuit, pull-down circuit and output circuit, the problem of gate driving circuit in display products withstand high voltages is solved, and the transistor protection and stable operation of the display device are achieved.
Patent Information
- Application Number
- CN202510502726.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-21
- Publication Date
- 2025-06-27
AI Technical Summary
In the pixel circuit of the display product, the gate driving circuit needs to output a high voltage scan signal, causing the transistor to withstand a large span voltage, which may cause device damage.
A shift register is provided, including an input circuit, a first pull-down circuit, a second pull-down circuit and an output circuit. Through the coordination of these circuits, the node potential is controlled by using the input signal and the power supply voltage to output a clock signal and reduce the voltage requirement for the gate driving circuit.
By stably controlling the node potential in the shift register, the damage to the transistor by high voltage is avoided, ensuring the stable operation of the display device and the normality of the screen display.
Smart Images
Figure CN120220570A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of display technologies, and in particular, to a shift register, a driving circuit, a driving method, and a display device. Background Art
[0002] In the pixel circuits of some display products, the gate driving circuit needs to output a scanning signal with a relatively high voltage to drive the opening and closing of transistors. However, this causes the transistors in the gate driving circuit to withstand a large cross-voltage, resulting in device damage. Summary of the Invention
[0003] To solve the above problems, the present disclosure provides a shift register, a driving circuit, a driving method, and a display device.
[0004] According to a first aspect, the present disclosure provides a shift register, including: an input circuit electrically connected to an input terminal and a first power supply, the input circuit being configured to control the potential of a first node by using an input signal under the control of the input signal from the input terminal, and to control the potential of a second node by using a first power supply voltage from the first power supply under the control of the first power supply voltage; a first pull-down circuit electrically connected to a second power supply, the input terminal, the first node, and the second node, the first pull-down circuit being configured to control the potential of the second node by using a second power supply voltage of the second power supply under the control of the potential of the first node and the input signal; a second pull-down circuit electrically connected to the first node, the second node, and a third power supply, the second pull-down circuit being configured to control the potential of the first node according to the potential of the second node and a third power supply voltage of the third power supply; and an output circuit electrically connected to the first node, the second node, the second power supply, a clock terminal, and an output terminal, the output circuit being configured to output an output signal via the output terminal based on a clock signal from the clock terminal and the second power supply voltage under the control of the potential of the first node and the potential of the second node; wherein the second power supply voltage is less than or equal to the third power supply voltage.
[0005] According to a second aspect, the present disclosure provides a driving circuit including M cascaded shift registers provided in embodiments of the present disclosure, where M is an integer greater than 1.
[0006] According to a third aspect, the present disclosure provides a display device including the driving circuit provided in embodiments of the present disclosure.
[0007] According to a fourth aspect, the present disclosure provides a driving method, which is applied to the shift register provided in the embodiments of the present disclosure, and includes: controlling the potential of a first node by using an input signal under the control of the input signal from an input terminal, and controlling the potential of a second node by using a first power supply voltage from a first power supply under the control of the first power supply voltage; controlling the potential of the second node by using the first power supply voltage of the first power supply under the control of the potential of the first node and the input signal; controlling the potential of the first node according to the potential of the second node and a second power supply voltage of a second power supply; and outputting an output signal based on a clock signal from a clock terminal and the first power supply voltage under the control of the potential of the first node and the potential of the second node. Description of the Drawings
[0008] Figure 1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure;
[0009] Figure 2 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;
[0010] Figure 3 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;
[0011] Figure 4 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;
[0012] Figure 5 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;
[0013] Figure 6 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;
[0014] Figure 7 is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure;
[0015] Figure 8 is a schematic structural diagram of a display device according to an embodiment of the present disclosure; and
[0016] Figure 9 is a flowchart of a driving method according to an embodiment of the present disclosure. Detailed Embodiments
[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only a part rather than all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts fall within the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are denoted by the same or similar reference numerals. In the following description, some specific embodiments are for illustrative purposes only and should not be construed as any limitation to the present disclosure, but merely examples of the embodiments of the present disclosure. When it may cause confusion in the understanding of the present disclosure, conventional structures or configurations will be omitted. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual sizes and proportions, but only illustrate the content of the embodiments of the present disclosure.
[0018] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the ordinary meanings understood by those skilled in the art. The "first", "second", and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components.
[0019] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" may mean that two components are directly connected, or may mean that the two components are connected via one or more other components. In addition, the two components may be connected or coupled by wired or wireless means.
[0020] In the embodiments of the present disclosure, the source and drain of the switching transistor are symmetric, so the source and drain can be interchanged. In the embodiments of the present disclosure, according to its function, the gate can be referred to as the control electrode, one of the source and drain can be referred to as the first electrode, and the other of the source and drain can be referred to as the second electrode.
[0021] In addition, in the description of the embodiments of the present disclosure, the terms "first power supply voltage" and "second power supply voltage" are only used to distinguish the different amplitudes of the two power supply voltages. For example, in the following, the "first power supply voltage" is taken as a relatively high voltage, and the "second power supply voltage", "third power supply voltage", and "fourth power supply voltage" are taken as relatively low voltages for description. Those skilled in the art can understand that the present disclosure is not limited thereto.
[0022] It should be noted that in the description of the embodiments of the present disclosure, INPUT can represent both the input signal terminal and the input signal provided by the input terminal, and can also represent the level of the input signal. Similarly, the symbol CLK can represent both the clock terminal and the clock signal provided by the clock terminal, and can also represent the level of the clock signal. OUT can represent both the output terminal and the output signal output by the output terminal, and can also represent the level of the output signal. VGH and VGL can represent both the power supply terminal and the power supply voltage provided by the power supply terminal. For example, the power supply VGH can provide a high-level voltage, and the power supply VGL can provide a low-level voltage. The same applies to the following embodiments and will not be elaborated further.
[0023] Figure 1 It is a schematic structural diagram of a shift register according to an embodiment of the present disclosure.
[0024] As Figure 1 shown, the shift register 100 includes an input circuit 110, a first pull-down circuit 120, a second pull-down circuit 130, and an output circuit 140.
[0025] In the embodiments of the present disclosure, the input circuit 110 is electrically connected to the input terminal INPUT and the first power supply VGH. Under the control of the input signal INPUT from the input terminal INPUT, the potential of the first node N1 is controlled by the input signal INPUT. Under the control of the first power supply voltage VGH from the first power supply VGH, the potential of the second node N2 is controlled by the first power supply voltage VGH.
[0026] For example, the input signal INPUT can control the connection state or disconnection state between the input terminal INPUT and the first node N1. When the input signal INPUT is at a high level, the connection between the input terminal INPUT and the first node N1 is in a connected state, and the input circuit 110 writes the high level of the input signal INPUT to the first node N1, raising the potential of the first node N1.
[0027] For example, the first power supply voltage VGH can control the connection state between the first power supply VGH and the second node N2. At this time, the first control circuit 110 writes the first power supply voltage VGH to the second node N2. It should be noted that the first power supply voltage VGH provided by the first power supply VGH changes periodically between high and low levels. When the first power supply voltage VGH is at a low level, the connection between the first power supply VGH and the second node N2 is in a disconnected state.
[0028] In an embodiment of the present disclosure, the first pull-down circuit 120 is electrically connected to a second power supply VGH, an input terminal INPUT, a first node N1, and a second node N2. Under the control of the potential of the first node N1 and the input signal INPUT, the first pull-down circuit 120 controls the potential of the second node N2 by using the second power supply voltage VGH of the second power supply VGH.
[0029] For example, the potential of the first node N1 can control the connection state or disconnection state between the second power supply VGH and the second node N2. When the potential of the first node N1 is high and the second power supply VGH and the second node N2 are in a connected state, the first pull-down circuit 120 writes the second power supply voltage VGH to the second node N2, pulling down the potential of the second node N2.
[0030] For example, the potential of the input signal INPUT can also control the connection state or disconnection state between the second power supply VGH and the second node N2. When the input signal INPUT is at a high level and the second power supply VGH and the second node N2 are in a connected state, the first pull-down circuit 120 writes the second power supply voltage VGH to the second node N2, pulling down the potential of the second node N2.
[0031] In an embodiment of the present disclosure, the second pull-down circuit 130 is electrically connected to the first node N1, the second node N2, and a third power supply LVGL. The second pull-down circuit 130 controls the potential of the first node N1 according to the potential of the second node N2 and the third power supply voltage LVGL of the third power supply LVGL.
[0032] For example, the voltage difference between the potential of the second node N2 and the third power supply voltage LVGL can control the connection state or disconnection state between the third power supply LVGL and the first node N1. When the potential of the second node N2 is less than or equal to the third power supply voltage LVGL, the third power supply LVGL and the first node N1 are in a disconnected state, and at this time, the third power supply voltage LVGL does not change the high potential of the first node N1.
[0033] When the potential of the second node N2 is greater than the third power supply voltage LVGL, the third power supply LVGL and the first node N1 are in a connected state, and the second pull-down circuit 130 writes the third power supply voltage LVGL to the first node N1, pulling down the potential of the first node N1.
[0034] In an embodiment of the present disclosure, the output circuit 140 is electrically connected to the first node N1, the second node N2, a second power supply VGL, a clock terminal CLK, and an output terminal OUT. Under the control of the potential of the first node N1 and the potential of the second node B2, the output circuit 140 outputs an output signal OUT via the output terminal OUT based on the clock signal CLK from the clock terminal CLK and the second power supply voltage VGL.
[0035] For example, the potential of the first node N1 can control the connection state or disconnection state between the clock terminal CLK and the output terminal OUT. When the clock terminal CLK and the output terminal OUT are in the connected state, the output circuit 140 provides the clock signal CLK to the output terminal OUT, and the output signal OUT output by the output terminal OUT has the same level as the clock signal CLK1.
[0036] For example, the potential of the second node N2 can control the connection state or disconnection state between the second power supply VGL and the output terminal OUT. When the second power supply VGL and the output terminal OUT are in the connected state, the output circuit 140 provides the second power supply voltage VGL to the output terminal OUT, and the output signal OUT output by the output terminal OUT is a low-level signal.
[0037] For example, when the potential of the first node N1 is at a high level, the clock terminal CLK and the output terminal OUT are in the connected state. When the potential of the first node N1 is at a low level, the clock terminal CLK and the output terminal OUT are in the disconnected state.
[0038] To ensure that the output terminal OUT can output a signal with the level of the clock signal CLK, it is necessary to ensure that the potential of the first node N1 is stably maintained at a high level. In this case, the second pull-down circuit 130 needs to control the disconnection state between the third power supply LVGL and the first node N1, so as to avoid the potential of the first node N1 being pulled down.
[0039] In the embodiment of the present disclosure, the second power supply voltage VGH is less than or equal to the third power supply voltage LVGL. The smaller the second power supply voltage VGH is relative to the third power supply voltage LVGL, the more stable the disconnection state between the third power supply LVGL and the first node N1 is, which enables the first node N1 to be stably maintained at a high potential, so that the output circuit 140 can stably output the clock signal and avoid abnormal screen display.
[0040] Figure 2 It is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.
[0041] As Figure 2 shown, the shift register 200 includes an input circuit 210, a first pull-down circuit 220, a second pull-down circuit 230, an output circuit 240, and a control circuit 250. The input circuit 210, the first pull-down circuit 220, and the output circuit 240 can refer to the input circuit 110, the first pull-down circuit 120, and the output circuit 140 described above. For the sake of brevity, the similar parts will not be described again.
[0042] In an embodiment of the present disclosure, the control circuit 250 is electrically connected to the third power supply LVGL, the second node N2, and the third node N3. The second pull-down circuit 230 is electrically connected to the third node N3 and is electrically connected to the third power supply LVGL via the control circuit 250.
[0043] In an embodiment of the present disclosure, the control circuit 250 controls the potential of the third node N3 according to the potential of the second node N2 and the third power supply voltage LVGL. The second pull-down circuit 230 controls the potential of the first node N1 according to the potential of the third node N3 and the potential of the second node N2.
[0044] For example, the voltage difference between the potential of the second node N2 and the third power supply voltage LVGL can control the connection state or disconnection state between the third power supply LVGL and the third node N3. When the potential of the second node N2 is less than or equal to the third power supply voltage LVGL, the connection between the third power supply LVGL and the third node N3 is in a disconnected state, and at this time, the third power supply voltage LVGL does not change the high potential of the third node N3. When the potential of the second node N2 is greater than the third power supply voltage LVGL, the connection between the third power supply LVGL and the third node N3 is in a connected state, and the control circuit 250 writes the third power supply voltage LVGL to the third node N3, pulling down the potential of the third node N3.
[0045] For example, the voltage difference between the potential of the second node N2 and the potential of the third node N3 can control the connection state or disconnection state between the third node N3 and the first node N1. When the potential of the second node N2 is less than or equal to the third node N3, the connection between the third node N3 and the first node N1 is in a disconnected state, and at this time, the potential of the third node N3 is not written to the high potential of the first node N1. When the potential of the second node N2 is greater than the third node N3, the connection between the first node N1 and the third node N3 is in a connected state, and the second pull-down circuit 230 writes the potential of the third node N3 to the first node N1, pulling down the potential of the first node N1.
[0046] In an embodiment of the present disclosure, the control circuit 250 also controls the connection state between the third power supply LVGL and the third node N3 based on the voltage difference between the third node N3 and the third power supply voltage LVGL. The second pull-down circuit 230 also controls the connection state between the first node N1 and the third node N3 based on the voltage difference between the third node N3 and the first node N1.
[0047] For example, when the potential of the second node N2 is at a low potential and the potential of the second node N2 is greater than or equal to that of the third node N3, the second pull-down circuit 230 also controls the state such that a weakly connected state can be formed between the first node N1 and the third node N3. At this time, based on the potential difference between the potential of the first node N1 and the potential of the third node N3, the second pull-down circuit 230 controls a leakage current to be formed between the first node N1 and the third node N3. The greater the potential of the first node N1 relative to the potential of the third node N3, the more stable the connected state between the first node N1 and the third node N3, which causes the potential of the first node N1 to be pulled down by the potential of the third node N3.
[0048] For example, when the potential of the second node N2 is at a low potential and the potential of the second node N2 is greater than or equal to the third power supply voltage LVGL, the control circuit 250 also controls the state such that a weakly connected state can be formed between the third power supply LVGL and the third node N3. At this time, based on the potential difference between the potential of the third power supply voltage LVGL and the potential of the third node N3, the control circuit 250 controls a leakage current to be formed between the third power supply LVGL and the third node N3. The greater the potential of the third node N3 relative to the third power supply voltage LVGL, the more stable the connected state between the third node N3 and the third power supply LVGL, which causes the potential of the third node N3 to be pulled down by the potential of the third power supply voltage LVGL.
[0049] In the embodiment of the present disclosure, when the potential of the first node N1 is at a high potential, the potential difference between the first node N1 and the third node N3 is much greater than the potential difference between the third node N3 and the third power supply voltage LVGL. Therefore, the leakage current formed between the third power supply LVGL and the third node N3 is small, and the degree of pulling down the potential of the third node N3 is small. This also causes the degree of pulling down the potential of the first node N1 by the third node N3 to be small, thereby stabilizing the high potential of the first node N1 and enabling the output circuit 240 to stably output a clock signal, avoiding abnormal display of the screen.
[0050] Figure 3 It is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.
[0051] As Figure 3 shown, the shift register 300 includes an input circuit 310, a first pull-down circuit 320, a second pull-down circuit 330, an output circuit 340, a first reset circuit 360, and a second reset circuit 370.
[0052] In the embodiment of the present disclosure, the input circuit 310, the first pull-down circuit 320, the second pull-down circuit 330, and the output circuit 340 may refer to the input circuit 110, the first pull-down circuit 120, the second pull-down circuit 130, and the output circuit 140 described above. For the sake of brevity, the similar parts will not be described again.
[0053] In the embodiment of the present disclosure, the first reset circuit 360 is electrically connected to the third power supply LVGL, the first reset terminal STV0, and the first node N1. The first reset circuit 360 controls the potential of the first node N1 according to the first reset signal STV0 from the first reset terminal STV0 and the third power supply voltage LVGL. The second reset circuit 370 is electrically connected to the third power supply LVGL, the second reset terminal RESET, and the first node N1. The second reset circuit 370 controls the potential of the first node N1 according to the second reset signal RESET from the second reset terminal RESET and the third power supply voltage LVGL.
[0054] For example, the first reset terminal STV0 may be the total reset terminal of the first node N1. For multiple cascaded shift registers 400, the first reset terminal STV0 may be used to simultaneously reset the first nodes N1 of the multiple shift registers. The second reset terminal RESET may be the reset terminal of the first node N1, and the second reset terminal RESET may be used to reset the first node N1 of a single shift register.
[0055] In the embodiment of the present disclosure, the potential of the first reset signal STV0 may control the connection state or disconnection state between the third power supply LVGL and the first node N1. For example, the high level of the first reset signal STV0 may control the connection state between the third power supply LVGL and the first node N1. At this time, the first reset circuit 360 writes the third power supply voltage LVGL1 into the first node N1, pulling down the potential of the first node N1 to achieve the potential reset of the first node N1. The low level of the first reset signal STV0 may control the disconnection state between the third power supply LVGL and the first node N1.
[0056] When the first reset signal STV0 is at a low level, the first reset circuit 360 may also control the weak connection state between the third power supply LVGL and the first node N1 based on the voltage difference between the level of the first reset signal STV0 and the third power supply voltage LVGL. For example, when the first reset signal STV0 is at a low level and the potential of the first reset signal STV0 is greater than or equal to the third power supply voltage LVGL, the first reset circuit 360 may also control the weak connection state between the third power supply LVGL and the first node N1.
[0057] In an embodiment of the present disclosure, to prevent the first reset circuit 360 from pulling down the potential of the first node N1 using the third power supply voltage LVGL, the present disclosure sets the third power supply voltage LVGL to be greater than the low potential of the first reset signal STV0. Since the low potential of the first reset signal STV0 is the same as the second power supply voltage VGL, the present disclosure sets the third power supply voltage LVGL to be greater than the low potential of the second power supply voltage VGL.
[0058] The greater the third power supply voltage LVGL is relative to the low potential of the first reset signal STV0, the more stable the disconnected state between the third power supply LVGL and the first node N1 is, which enables the first node N1 to stably maintain a high potential.
[0059] In an embodiment of the present disclosure, the potential of the second reset signal RESET can control the connection state or disconnection state between the third power supply LVGL and the first node N1. For example, a high level of the second reset signal RESET can control the connection state between the third power supply LVGL and the first node N1. At this time, the second reset circuit 370 writes the third power supply voltage LVGL1 to the first node N1 to pull down the potential of the first node N1, thereby realizing the potential reset of the first node N1. A low level of the second reset signal RESET can control the disconnection state between the third power supply LVGL and the first node N1.
[0060] When the second reset signal RESET is at a low level, the second reset circuit 370 can also control the weak connection state between the third power supply LVGL and the first node N1 based on the voltage difference between the level of the second reset signal RESET and the third power supply voltage LVGL. For example, when the second reset signal RESET is at a low level and the potential of the second reset signal RESET is greater than or equal to the third power supply voltage LVGL, the second reset circuit 370 can also control the state of the weak connection state between the third power supply LVGL and the first node N1.
[0061] In an embodiment of the present disclosure, to prevent the second reset circuit 370 from pulling down the potential of the first node N1 using the third power supply voltage LVGL, the present disclosure sets the third power supply voltage LVGL to be greater than the low potential of the second reset signal RESET. Since the low potential of the second reset signal RESET is the same as the second power supply voltage VGL, the present disclosure sets the third power supply voltage LVGL to be greater than the low potential of the second power supply voltage VGL.
[0062] The greater the third power supply voltage LVGL is relative to the low potential of the second reset signal RESET, the more stable the disconnected state between the third power supply LVGL and the first node N1 is, which enables the first node N1 to stably maintain a high potential.
[0063] Figure 4 It is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.
[0064] As Figure 4 shown, the shift register 400 includes an input circuit 410, a first pull-down circuit 420, a second pull-down circuit 430, an output circuit 450, a first reset circuit 460, and a second reset circuit 470.
[0065] In the embodiments of the present disclosure, the input circuit 410, the first pull-down circuit 420, the second pull-down circuit 430, and the output circuit 450 may refer to the input circuit 110, the first pull-down circuit 120, the second pull-down circuit 130, and the output circuit 150. For the sake of brevity, similar parts will not be described again.
[0066] In the embodiments of the present disclosure, the first reset circuit 460 is electrically connected to a first reset terminal STV0, a second reset terminal RESET, a third power supply LVGL, and a fourth node N4. The first reset circuit 460 controls the potential of the fourth node N4 according to a first reset signal STV0 from the first reset terminal STV0, a second reset signal RESET from the second reset terminal RESET, and the third power supply voltage.
[0067] The second reset circuit 470 is electrically connected to the first reset terminal STV0, the second reset terminal RESET, the fourth node N4, and the first node N1. The second reset circuit 470 controls the potential of the first node N1 according to the first reset signal STV0, the second reset signal RESET, and the potential of the fourth node N4.
[0068] In the embodiments of the present disclosure,
[0069] In the embodiments of the present disclosure, the potential of the first reset signal STV0 controls the connection state or disconnection state between the third power supply LVGL and the fourth node N4, and the potential of the first reset signal STV0 also controls the connection state or disconnection state between the first node N1 and the fourth node N4.
[0070] For example, a high level of the first reset signal STV0 may control the connection state between the third power supply LVGL and the fourth node N4, and control the connection state between the first node N1 and the fourth node N4. At this time, the first reset circuit 460 writes the third power supply voltage LVGL1 into the fourth node N4, pulling down the potential of the fourth node N4. The second reset circuit 470 writes the potential of the fourth node N4 into the first node N1, pulling down the potential of the first node N1, thereby realizing the reset of the potential of the first node N1.
[0071] In the embodiments of the present disclosure, the potential of the second reset signal RESET controls the connection state or disconnection state between the third power supply LVGL and the fourth node N4, and the potential of the second reset signal RESET also controls the connection state or disconnection state between the first node N1 and the fourth node N4.
[0072] For example, the high level of the second reset signal RESET can control the connection state between the third power supply LVGL and the fourth node N4, and control the connection state between the first node N1 and the fourth node N4. At this time, the first reset circuit 460 writes the third power supply voltage LVGL1 to the fourth node N4, pulling down the potential of the fourth node N4, and the second reset circuit 470 writes the potential of the fourth node N4 to the first node N1, pulling down the potential of the first node N1, so as to realize the potential reset of the first node N1.
[0073] In the embodiments of the present disclosure, in the case of the low level of the first reset signal STV0 and the low level of the second reset signal RESET, the first reset circuit 460 can also control the third power supply LVGL and the fourth node N4 to be in a weakly connected state based on the voltage difference between the fourth node N4 and the third power supply voltage LVGL. The second reset circuit 470 also controls the first node N1 and the fourth node N4 to be in a weakly connected state based on the voltage difference between the fourth node N4 and the first node N1.
[0074] At this time, based on the potential difference between the potential of the first node N1 and the potential of the fourth node N4, the second reset circuit 470 controls a leakage current to be formed between the first node N1 and the fourth node N4. The greater the potential of the first node N1 relative to the potential of the fourth node N4, the more stable the connection state between the first node N1 and the fourth node N4, which causes the potential of the first node N1 to be pulled down by the potential of the fourth node N4.
[0075] Based on the potential difference between the potential of the third power supply voltage LVGL and the potential of the fourth node N4, the first reset circuit 460 controls a leakage current to be formed between the third power supply LVGL and the fourth node N4. The greater the potential of the fourth node N4 relative to the third power supply voltage LVGL, the more stable the connection state between the fourth node N4 and the third power supply LVGL, which causes the potential of the fourth node N4 to be pulled down by the potential of the third power supply voltage LVGL.
[0076] In an embodiment of the present disclosure, when the potential of the first node N1 is at a high potential, the potential difference between the first node N1 and the fourth node N4 is much greater than the potential difference between the fourth node N4 and the third power supply voltage LVGL. Therefore, the leakage current formed between the third power supply LVGL and the fourth node N4 is small, and the degree of pulling down the potential of the fourth node N4 is small. This also makes the degree of pulling down the potential of the fourth node N4 on the potential of the first node N1 small, so as to stabilize the high potential of the first node N1, enabling the output circuit 440 to stably output a clock signal and avoiding abnormal display of the screen.
[0077] Figure 5 It is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.
[0078] In an embodiment of the present disclosure, the shift register 500 includes an input circuit 510, a first pull-down circuit 520, a second pull-down circuit 530, an output circuit 540, a first reset circuit 560, and a second reset circuit 570.
[0079] In an embodiment of the present disclosure, the input circuit 510 includes transistors T9 to T11, the first pull-down circuit 520 includes transistors T112 to T15, the second pull-down circuit 530 includes transistors T1 and T2, the output circuit 540 includes transistors T16 to T23 and a capacitor C, the first reset circuit 560 includes a transistor T5, and the second reset circuit 570 includes a transistor T6.
[0080] The first power supply VGH includes a first sub-power supply VDD1 and a second sub-power supply VDD2. The power supply voltages of the first sub-power supply VDD1 and the second sub-power supply VDD2 are alternately set high. The second node N2 includes a first sub-node N2-1 and a second sub-node N2-2. The output terminal includes a first output terminal OUT1 and a second output terminal OUT2.
[0081] In an embodiment of the present disclosure, the control electrode of the transistor T1 (first transistor) is electrically connected to the first sub-node N2-1, the first electrode of the transistor T1 is electrically connected to the first node N1, and the second electrode of the transistor T1 is electrically connected to the third power supply LVGL.
[0082] The control electrode of the transistor T2 (second transistor) is electrically connected to the second sub-node N2-2, the first electrode of the transistor T2 is electrically connected to the first node N1, and the second electrode of the transistor T2 is electrically connected to the third power supply LVGL.
[0083] The control electrode of the transistor T5 (fifth transistor) is electrically connected to the first reset terminal STV0, the first electrode of the transistor T5 is electrically connected to the first node N1, and the second electrode of the transistor T5 is electrically connected to the third power supply LVGL.
[0084] The control electrode of transistor T6 (the sixth transistor) is electrically connected to the second reset terminal RESET. The first electrode of transistor T6 is electrically connected to the first node N1. The second electrode of transistor T6 is electrically connected to the third power supply LVGL.
[0085] The control electrode of transistor T9 is electrically connected to the input terminal INPUT. The first electrode of transistor T9 is electrically connected to the input terminal INPUT. The second electrode of transistor T9 is electrically connected to the first node N1.
[0086] The control electrode of transistor T10 is electrically connected to the first sub-power supply VDD1. The first electrode of transistor T10 is electrically connected to the first sub-power supply VDD1. The second electrode of transistor T10 is electrically connected to the first sub-node N2-1.
[0087] The control electrode of transistor T11 is electrically connected to the second sub-power supply VDD2. The first electrode of transistor T11 is electrically connected to the second sub-power supply VDD2. The second electrode of transistor T11 is electrically connected to the second sub-node N2-2.
[0088] The control electrode of transistor T12 is electrically connected to the first node N1. The first electrode of transistor T12 is electrically connected to the first sub-node N2-1. The second electrode of transistor T12 is electrically connected to the second power supply VGL.
[0089] The control electrode of transistor T13 is electrically connected to the input terminal INPUT. The first electrode of transistor T13 is electrically connected to the first sub-node N2-1. The second electrode of transistor T13 is electrically connected to the second power supply VGL.
[0090] The control electrode of transistor T14 is electrically connected to the first node N1. The first electrode of transistor T14 is electrically connected to the second sub-node N2-2. The second electrode of transistor T14 is electrically connected to the second power supply VGL.
[0091] The control electrode of transistor T15 is electrically connected to the input terminal INPUT. The first electrode of transistor T15 is electrically connected to the second sub-node N2-2. The second electrode of transistor T15 is electrically connected to the second power supply VGL.
[0092] The control electrode of transistor T16 is electrically connected to the first node N1. The first electrode of transistor T16 is electrically connected to the clock terminal CLK. The second electrode of transistor T16 is electrically connected to the second output terminal OUT2.
[0093] The control electrode of transistor T17 is electrically connected to the first node N1. The first electrode of transistor T17 is electrically connected to the clock terminal CLK. The second electrode of transistor T17 is electrically connected to the first output terminal OUT1.
[0094] The control electrode of transistor T18 is electrically connected to the first sub-node N2-1, the first pole of transistor T18 is electrically connected to the second output terminal OUT2, and the second pole of transistor T18 is electrically connected to the second power supply VGL.
[0095] The control electrode of transistor T19 is electrically connected to the second sub-node N2-2, the first pole of transistor T19 is electrically connected to the second output terminal OUT2, and the second pole of transistor T19 is electrically connected to the second power supply VGL.
[0096] The control electrode of transistor T20 is electrically connected to the first sub-node N2-1, the first pole of transistor T20 is electrically connected to the first output terminal OUT1, and the second pole of transistor T20 is electrically connected to the second power supply VGL.
[0097] The control electrode of transistor T21 is electrically connected to the second sub-node N2-2, the first pole of transistor T21 is electrically connected to the first output terminal OUT1, and the second pole of transistor T21 is electrically connected to the second power supply VGL.
[0098] The control electrode of transistor T22 is electrically connected to the second reset terminal RESET, the first pole of transistor T22 is electrically connected to the first output terminal OUT1, and the second pole of transistor T22 is electrically connected to the second power supply VGL.
[0099] The control electrode of transistor T23 is electrically connected to the total reset terminal TotalRST, the first pole of transistor T23 is electrically connected to the first output terminal OUT1, and the second pole of transistor T23 is electrically connected to the second power supply VGL.
[0100] The first end of capacitor C is connected to the first node N1, and the second end of C is connected to the first output terminal OUTl.
[0101] In the embodiments of the present disclosure, transistors T1 to T23 are N-type TFT transistors. For example, thin film transistors with an active layer of indium gallium zinc oxide (IGZO). Those skilled in the art can understand that transistors T1 to T23 in the present disclosure can also be P-type TFT transistors, such as thin film transistors with an active layer of low-temperature doped polysilicon (LTPS), and the level of the gate conduction signal of each transistor can be changed accordingly.
[0102] In addition, those skilled in the art can understand that the storage capacitor can be respectively implemented as a single capacitor or multiple capacitive units connected in parallel or in series, as long as its corresponding function can be achieved.
[0103] In the description of the embodiments of the present disclosure, the first node N1, the first sub-node N2-1, and the second sub-node N2-2 do not represent actually existing components, but represent the convergence points of relevant circuit connections in the circuit diagram.
[0104] Next, takingFigure 5 Taking the structure of the shift register 500 shown as an example, the working process of the shift register provided by the embodiments of the present disclosure will be described.
[0105] Under the control of the high level of the input signal INPUT, the transistors T9, T13, and T15 are turned on. The input signal INPUT is written into the first node N1 through the transistor T9, and the potential of the first node N1 is raised. The second power supply voltage VGL is written into the first sub-node N2-1 through the transistor T13 and into the second node N2-2 through the transistor T15, and the potentials of the first sub-node N2-1 and the second node N2-2 are lowered.
[0106] At this time, under the control of the high potential of the first node N1, the transistors T12, T14, T16, and T17 are turned on. Under the control of the low potentials of the first sub-node N2-1 and the second node N2-2, the transistors T1, T2, T18, T19, T20, and T21 are turned off.
[0107] In this case, the clock signal CLK is written into the first output terminal OUT1 through the transistor T17, and the first output terminal OUT1 outputs the level signal of the clock signal CLK. The clock signal CLK1 charges the capacitor C, so that the capacitor C2 stores the level of the clock signal CLK. The clock signal CLK is written into the second output terminal OUT2 through the transistor T16, and the second output terminal OUT2 outputs the level signal of the clock signal CLK.
[0108] The high level of the first sub-power supply voltage VDD1 controls the on or off of the transistor T10, and the second sub-power supply voltage VDD2 controls the on or off of the transistor T11.
[0109] When the first sub-power supply voltage VDD1 is at a high level, the transistor 10 is turned on, and the first sub-power supply voltage VDD1 is written into the first sub-node N2-1 through the transistor 10, raising the potential of the first sub-node N2-1. At this time, the transistors T1, T18, and T20 are turned on. The third power supply voltage LVGL is written into the first node N1 through the transistor T1, lowering the potential of the first node N1. At this time, the transistors T12, T14, T16, and T17 are turned off.
[0110] In this case, the second power supply voltage VGL is written into the first output terminal OUT1 through the transistor T20, and the first output terminal OUT1 outputs a low-level signal. The second power supply voltage VGL is written into the second output terminal OUT2 through the transistor T18, and the second output terminal OUT2 outputs a low-level signal.
[0111] When the second sub - power supply voltage VDD2 is at a high level, transistor 11 is turned on, and the second sub - power supply voltage VDD2 is written to the second sub - node N2 - 2 through transistor 11, raising the potential of the second sub - node N2 - 2. At this time, transistors T2, T19, and T21 are turned on. The third power supply voltage LVGL is written to the first node N1 through transistor T2, lowering the potential of the first node N1. At this time, transistors T12, T14, 16, and T17 are turned off.
[0112] In this case, the second power supply voltage VGL is written to the first output terminal OUT1 through transistor T21, and the first output terminal OUT1 outputs a low - level signal. The second power supply voltage VGL is written to the second output terminal OUT2 through transistor T19, and the second output terminal OUT2 outputs a low - level signal.
[0113] In the embodiment of the present disclosure, when the first reset signal STV0 is at a high level, transistor T5 is turned on, and the third power supply voltage LVGL is written to the first node N1 through transistor T5, lowering the potential of the first node N1 to reset the potential of the first node N1. The first reset signal STV0 can be a frame start signal, and the overall reset of each shift register unit is achieved by using the frame start signal.
[0114] In the embodiment of the present disclosure, when the second reset signal RESET is at a high level, transistor T6 is turned on, and the third power supply voltage LVGL is written to the first node N1 through transistor T6, lowering the potential of the first node N1 to reset the potential of the first node N1.
[0115] When the second reset signal RESET is at a high level, transistor T22 is turned on, and the second power supply voltage VGL is written to the first output terminal OUT1 through transistor T22, lowering the potential of the first output terminal OUT1 to reset the potential of the first output terminal OUT1.
[0116] In the embodiment of the present disclosure, when the reset signal TotalRST is at a high level, transistor T23 is turned on, and the second power supply voltage VGL is written to the first output terminal OUT1 through transistor T23, lowering the potential of the first output terminal OUT1 to reset the potential of the first output terminal OUT1. The reset signal TotalRST can be a total reset signal, and the first output terminals OUT1 of multiple cascaded shift register units are reset as a whole.
[0117] In an embodiment of the present disclosure, the first sub-node N2-1 is written with the second power supply voltage VGL. At this time, the potential of the first sub-node N2-1 is the second power supply voltage VGL, and the gate voltage Vg1 of the transistor T1 is VGL. Since the potential of the source of the transistor T1 is electrically connected to the third power supply voltage LVGL, the gate-source voltage Vgs1 of the transistor T1 = VGL - LVGL. Since the third power supply voltage LVGL is greater than the second power supply voltage VGL, the gate-source voltage Vgs1 of the transistor T1 is less than 0. The transistor T1 is an Nmos transistor, and the threshold voltage Vth1 of the transistor T1 ≤ 0. When Vgs1 < Vth1, the transistor T1 is turned off, which can prevent the third power supply voltage LVGL from pulling down the potential of the first node N1. By setting VGL - LVGL < Vth1, the transistor T1 can be controlled to turn off. For example, -1V < Vth1, and VGL - LVGL ≤ -1V is set.
[0118] In an embodiment of the present disclosure, the second sub-node N2-2 is written with the second power supply voltage VGL. At this time, the potential of the second sub-node N2-2 is the second power supply voltage VGL, the gate voltage Vg2 of the transistor T2 is VGL, and the gate-source voltage Vgs2 of the transistor T2 = VGL - LVGL. Since the third power supply voltage LVGL is greater than the second power supply voltage VGL, the gate-source voltage Vgs2 of the transistor T2 is less than 0. The transistor T2 is an Nmos transistor, and the threshold voltage Vth2 of the transistor T2 ≤ 0. By setting VGL - LVGL < Vth2, the transistor T2 can be controlled to turn off, which can prevent the third power supply voltage LVGL from pulling down the potential of the first node N1.
[0119] In an embodiment of the present disclosure, the gate voltage Vg5 of the transistor T5 is STV0, and the gate-source voltage Vgs5 of the transistor T5 = STV0 - LVGL. The low level of the first reset signal STV0 can be VGL, and the gate-source voltage Vgs5 of the transistor T5 = VGL - LVGL. Since the third power supply voltage LVGL is greater than the second power supply voltage VGL, the gate-source voltage Vgs5 of the transistor T5 is less than 0. The transistor T5 is an Nmos transistor, and the threshold voltage Vth5 of the transistor T5 ≤ 0. By setting VGL - LVGL < Vth5, the transistor T5 can be controlled to turn off, which can prevent the third power supply voltage LVGL from pulling down the potential of the first node N1.
[0120] In the embodiment of the present disclosure, the gate voltage Vg6 of the transistor T6 is RESET, and the gate-source voltage Vgs6 of the transistor T6 = RESET - LVGL. The low level of the second reset signal RESET can be VGL, and the gate-source voltage Vgs6 of the transistor T6 = VGL - LVGL. Since the third power supply voltage LVGL is greater than the second power supply voltage VGL, the gate-source voltage Vgs6 of the transistor T6 is less than 0. The transistor T6 is an Nmos transistor, and the threshold voltage Vth6 of the transistor T6 ≤ 0. By setting VGL - LVGL < Vth6, the transistor T6 can be controlled to turn off, which can prevent the third power supply voltage LVGL from pulling down the potential of the first node N1.
[0121] In the embodiment of the present disclosure, by setting the voltage value of the third power supply voltage LVGL, the transistors T5, T6, T1, and T2 can be prevented from being mis-conducted, thereby stabilizing the potential of the first node N1.
[0122] Figure 6 It is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.
[0123] As Figure 6 shown, the shift register 600 includes an input circuit 610, a first pull-down circuit 620, a second pull-down circuit 630, an output circuit 640, a control circuit 650, a first reset circuit 660, and a second reset circuit 670.
[0124] In the embodiment of the present disclosure, the input circuit 610, the first pull-down circuit 620, and the output circuit 640 can refer to the input circuit 510, the first pull-down circuit 520, and the output circuit 540 described above. For the sake of brevity, similar parts will not be described again.
[0125] In the embodiment of the present disclosure, the control circuit 650 includes transistors T3 and T4. The first reset circuit 660 includes transistors T5 and T7. The second reset circuit 670 includes transistors T6 and T8.
[0126] The control electrode of the transistor T1 is electrically connected to the first sub-node N2-1, the first electrode of the transistor T1 is electrically connected to the first node N1, and the second electrode of the transistor T1 is electrically connected to the third node N3.
[0127] The control electrode of the transistor T2 is electrically connected to the second sub-node N2-2, the first electrode of the transistor T2 is electrically connected to the first node, and the second electrode of the transistor T2 is electrically connected to the third node N3.
[0128] The control electrode of the transistor T3 (the third transistor) is electrically connected to the first sub-node N2-1, the first electrode of the transistor T3 is electrically connected to the third node N3, and the second electrode of the transistor is electrically connected to the third power supply LVGL.
[0129] The control electrode of transistor T4 (the fourth transistor) is electrically connected to the second sub-node N2-2, the first electrode of transistor T4 is electrically connected to the third node N3, and the second electrode of transistor T4 is electrically connected to the third power supply LVGL.
[0130] The control electrode of transistor T5 is electrically connected to the first reset terminal STV0, the first electrode of transistor T5 is electrically connected to the fourth node N4, and the second electrode of transistor T5 is electrically connected to the third power supply LVGL.
[0131] The control electrode of transistor T6 is electrically connected to the second reset terminal RESET, the first electrode of transistor T6 is electrically connected to the first node N1, and the second electrode of transistor T6 is electrically connected to the fourth node N4.
[0132] The control electrode of transistor T7 (the seventh transistor) is electrically connected to the second reset terminal RESET, the first electrode of transistor T7 is electrically connected to the fourth node N4, and the second electrode of transistor T7 is electrically connected to the third power supply LVGL.
[0133] The control electrode of transistor T8 (the eighth transistor) is electrically connected to the first reset terminal STV0, the first electrode of transistor T8 is electrically connected to the first node N1, and the second electrode of transistor T8 is electrically connected to the fourth node N4.
[0134] In the description of the embodiments of the present disclosure, the third node N3 and the fourth node N4 do not represent actually existing components, but represent the convergence points of relevant circuit connections in the circuit diagram.
[0135] In the embodiments of the present disclosure, the second power supply voltage VGL may be the same as the third power supply voltage LVGL. Therefore, the second power supply VGL can be multiplexed, and the second electrodes of transistors T3, T4, T5, T7, T12 to T15 are all connected to the second power supply VGL.
[0136] In the embodiments of the present disclosure, when the first node N1 is at a high level, transistors T12 and T14 are turned on. At this time, when the first sub-node N2-1 and the second sub-node N2-2 are at a low level, transistors T1, T3, T2, and T4 are turned off.
[0137] When the first sub-node N2-1 and the second sub-node N2-2 are at a high level, transistors T1, T3, T2, and T4 are turned on. At this time, the potential of the first node N1 is pulled down by the second power supply VGL.
[0138] In an embodiment of the present disclosure, when the first reset signal STV0 is at a high level, the transistor T5 and the transistor T8 are turned on, and the second power supply voltage VGL is written to the first node N1 through the transistor T5 and the transistor T8, pulling down the potential of the first node N1 to reset the potential of the first node N1.
[0139] In an embodiment of the present disclosure, when the second reset signal RESET is at a high level, the transistor T6 and the transistor T7 are turned on, and the second power supply voltage VGL is written to the first node N1 through the transistor T6 and the transistor T7, pulling down the potential of the first node N1 to reset the potential of the first node N1.
[0140] In an embodiment of the present disclosure, the high potential of the input signal INPUT is written to the first node N1. At this time, the drain voltages Vd of the transistors T1, T2, T6, and T8 are all the potential of the first node N1.
[0141] The source-drain voltage Vds1 of the transistor T1 and the source-drain voltage Vds2 of the transistor T2 are both INPUT - VN3, and the source-drain voltage Vds3 of the transistor T3 and the source-drain voltage Vds4 of the transistor T4 are both VN3 - VGL. INPUT is the high level of the input signal INPUT, and VN3 is the potential of the third node N3.
[0142] The source-drain voltage Vds6 of the transistor T6 and the source-drain voltage Vds8 of the transistor T8 are both INPUT - VN4, and the source-drain voltage Vds5 of the transistor T5 and the source-drain voltage Vds7 of the transistor T7 are both VN4 - VGL. VN4 is the potential of the fourth node N3.
[0143] When the high level of the input signal INPUT is much greater than the second power supply voltage VGL, Vds1 and Vds2 are larger, Vds3 and Vds4 are smaller, Vds6 and Vds8 are larger, and Vds5 and Vds7 are smaller.
[0144] According to the linear current formula of the thin film transistor (TFT) as follows:
[0145]
[0146] Where Ids is the current passing through the transistor, Vgs is the gate-source voltage of the transistor, Vth is the threshold voltage of the transistor, and Vds is the source-drain voltage of the transistor. W and L are the width and length of the transistor channel respectively, μ is the mobility of electrons in the conductive channel, and Cgi is the oxide layer capacitance.
[0147] According to the current formula, the larger the source-drain voltage Vds, the more fully the transistor is turned on, and the larger the drain current Ids.
[0148] In the embodiment of the present disclosure, since Vdsl and Vds2 are much larger than Vds3 and Vds4, transistors T1 and T2 may be in a fully-conducting state with a relatively large leakage current. However, transistors T3 and T4 are in a weakly-conducting state with an insufficient conducting state and a relatively small leakage current. Therefore, when transistors T1 and T2 are conducting, transistors T3 and T4 cause the second power supply voltage VGL to pull down the potential of the third node N3 to a relatively low extent, thereby pulling down the potential of the first node N1 to a relatively low extent and stabilizing the potential of the first node N1.
[0149] Since Vds6 and Vds8 are much larger than Vds5 and Vds7, transistors T6 and T8 may be in a fully-conducting state with a relatively large leakage current. However, transistors T5 and T7 are in a weakly-conducting state with an insufficient conducting state and a relatively small leakage current. Therefore, when transistors T6 and T8 are conducting, transistors T5 and T7 cause the second power supply voltage VGL to pull down the potential of the third node N4 to a relatively low extent, thereby pulling down the potential of the first node N1 to a relatively low extent and stabilizing the potential of the first node N1.
[0150] Figure 7 It is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure.
[0151] As Figure 7 shown, the driving circuit 700 includes M cascaded shift registers, where M is a positive integer greater than 1. The M shift registers include a first-stage shift register STl, …, an m-stage shift register STm, …, and an M-stage shift register STM.
[0152] In the embodiment of the present disclosure, the shift register ST1 can be any one of the foregoing shift registers 100, 200, 300, 400, 500, and 600. For example, all M shift registers are shift register 500. For example, all M shift registers are shift register 600. Details are not described herein again.
[0153] In the embodiment of the present disclosure, in the M cascaded shift registers, the input signal INPUT of the input terminal INPUT of the first-stage shift register ST1 is the start signal GSTV.
[0154] In an embodiment of the present disclosure, the output terminals of the shift register include a first output terminal OUT1 and a second output terminal OUT2. The first-stage shift register ST1, …, the m-stage shift register STm, …, the M-stage shift register STM respectively output first output signals OUT1(1), …, first output signals OUT1(m), …, first output signals OUT1(M) based on their respective first output terminals OUT, thereby realizing the driving of the pixel array in the display panel.
[0155] In an embodiment of the present disclosure, the input terminal INPUT of the m-stage shift register STm is electrically connected to the output terminal of the (m - x)-stage shift register, where x < m ≤ M, and x and m are integers. For example, x can be 1, 2, 3, …… The m-stage shift register STm uses the second output signal OUT2 of the previous-stage shift register as the input signal INPUT to realize the driving of the m-stage shift register STm.
[0156] In an embodiment of the present disclosure, the second reset terminal RESET of the m-stage shift register is electrically connected to the output terminal of the (m + y)-stage shift register, where 1 < m ≤ M - y, and y and m are integers. For example, y can be 1, 2, 3, …… The m-stage shift register STm uses the second output signal OUT2 of the subsequent-stage shift register as the second reset signal RESET to realize the reset of the m-stage shift register STm.
[0157] Figure 8 It is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
[0158] As Figure 8 shown, the display device 800 may include a driving circuit 810.
[0159] In an embodiment of the present disclosure, the driving circuit 810 may be the driving circuit 700 described above, which will not be elaborated here.
[0160] Figure 9 It is a flowchart of a driving method according to an embodiment of the present disclosure.
[0161] As Figure 9 shown, the driving method may include operations S910 to S940.
[0162] In operation S910, under the control of an input signal from an input terminal, the potential of a first node is controlled using the input signal, and under the control of a first power supply voltage from a first power supply, the potential of a second node is controlled using the first power supply voltage.
[0163] In operation S920, under the control of the potential of the first node and the input signal, the potential of the second node is controlled using the first power supply voltage of the first power supply.
[0164] In operation S930, the potential of the first node is controlled according to the potential of the second node and the second power supply voltage of the second power supply.
[0165] In operation S940, under the control of the potential of the first node and the potential of the second node, an output signal is output based on a clock signal from a clock terminal and a first power supply voltage.
[0166] In the embodiments of the present disclosure, operations S910 to S940 are similar to the operations performed by the shift register 100 described above, and will not be described in detail herein.
[0167] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the above-mentioned module, program segment, or part of code contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, and the combination of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.
[0168] Those skilled in the art can understand that the features recited in the various embodiments and / or claims of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly recited in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features recited in the various embodiments and / or claims of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.
[0169] The embodiments of the present disclosure have been described above. However, these embodiments are merely for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments have been described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present disclosure.
Claims
1. A shift register, comprising: an input circuit electrically connected to an input terminal and a first power supply, the input circuit being configured to control the potential of the first node by using the input signal under the control of an input signal from the input terminal, and to control the potential of the second node by using the first power supply voltage under the control of a first power supply voltage from the first power supply; a first pull-down circuit electrically connected to a second power supply, the input terminal, the first node and the second node, the first pull-down circuit being configured to control the potential of the second node using a second power supply voltage of the second power supply under the control of the potential of the first node and the input signal; a second pull-down circuit electrically connected to the first node, the second node and a third power supply, the second pull-down circuit being configured to control the potential of the first node according to the potential of the second node and a third power supply voltage of the third power supply; as well as an output circuit electrically connected to the first node, the second node, the second power supply, a clock terminal and an output terminal, the output circuit being configured to output an output signal via the output terminal based on a clock signal from the clock terminal and the second power supply voltage under control of the potential of the first node and the potential of the second node; Wherein, the second power supply voltage is less than or equal to the third power supply voltage.
2. The shift register according to claim 1, wherein: Also includes: a control circuit electrically connected to the third power supply, the second node and a third node, the control circuit being configured to control the potential of the third node according to the potential of the second node and the third power supply voltage; The second pull-down circuit is electrically connected to the third node and is electrically connected to the third power supply via the control circuit. The second pull-down circuit is also configured to control the potential of the first node according to the potential of the third node and the potential of the second node.
3. The shift register according to claim 1 or 2, further comprising: a first reset circuit electrically connected to the third power supply, the first reset terminal and the first node, the first reset circuit being configured to control a potential of the first node according to a first reset signal from the first reset terminal and the third power supply voltage; as well as The second reset circuit is electrically connected to the third power supply, the second reset terminal and the first node, and the second reset circuit is configured to control the potential of the first node according to a second reset signal from the second reset terminal and the third power supply voltage.
4. The shift register according to claim 1 or 2, further comprising: a first reset circuit electrically connected to the first reset terminal, the second reset terminal, the third power supply and the fourth node, the first reset circuit being configured to control the potential of the fourth node according to a first reset signal from the first reset terminal, a second reset signal from the second reset terminal and the third power supply voltage; as well as A second reset circuit is electrically connected to the first reset terminal, the second reset terminal, the fourth node and the first node, and the second reset circuit is configured to control the potential of the first node according to the first reset signal, the second reset signal and the potential of the fourth node.
5. The shift register according to claim 1, wherein: The second pull-down circuit includes a first transistor and a second transistor, and the second node includes a first sub-node and a second sub-node; wherein the control electrode of the first transistor is electrically connected to the first subnode, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third power source; and A control electrode of the second transistor is electrically connected to the second sub-node, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the third power source.
6. The shift register according to claim 2, wherein: The second pull-down circuit includes a first transistor and a second transistor, the control circuit includes a third transistor and a fourth transistor, and the second node includes a first sub-node and a second sub-node; wherein the control electrode of the first transistor is electrically connected to the first sub-node, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third node; The control electrode of the second transistor is electrically connected to the second sub-node, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node; The control electrode of the third transistor is electrically connected to the first subnode, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the third power source; and A control electrode of the fourth transistor is electrically connected to the second subnode, a first electrode of the fourth transistor is electrically connected to the third node, and a second electrode of the fourth transistor is electrically connected to the third power source.
7. The shift register according to claim 3, wherein: The first reset circuit includes a fifth transistor, and the second reset transistor includes a sixth transistor; wherein a control electrode of the fifth transistor is electrically connected to the first reset terminal, a first electrode of the fifth transistor is electrically connected to the first node, and a second electrode of the fifth transistor is electrically connected to the third power supply; and A control electrode of the sixth transistor is electrically connected to the second reset terminal, a first electrode of the sixth transistor is electrically connected to the first node, and a second electrode of the sixth transistor is electrically connected to the third power supply.
8. The shift register according to claim 4, wherein: The first reset circuit includes a fifth transistor and a seventh transistor, and the second reset transistor includes a sixth transistor and an eighth transistor; Wherein, the control electrode of the fifth transistor is electrically connected to the first reset terminal, the first electrode of the fifth transistor is electrically connected to the fourth node, and the second electrode of the fifth transistor is electrically connected to the third power supply; The control electrode of the sixth transistor is electrically connected to the second reset terminal, the first electrode of the sixth transistor is electrically connected to the first node, and the second electrode of the sixth transistor is electrically connected to the fourth node; The control electrode of the seventh transistor is electrically connected to the second reset terminal, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the third power supply; and A control electrode of the eighth transistor is electrically connected to the first reset terminal, a first electrode of the eighth transistor is electrically connected to the first node, and a second electrode of the eighth transistor is electrically connected to the fourth node.
9. A driving circuit, comprising M cascaded shift registers according to any one of claims 1 to 8, wherein M is an integer greater than 1.
10. The driving circuit according to claim 9, wherein: The input end of the m-th shift register is electrically connected to the output end of the mx-th shift register, x<m≤M, and x and m are integers.
11. The driving circuit according to claim 9, wherein: The second reset terminal of the m-th stage shift register is electrically connected to the output terminal of the m+y-th stage shift register, 1<m≤My, y and m are integers.
12. A display device, comprising: A drive circuit as claimed in any one of claims 9 to 11.
13. A driving method, applied to the shift register according to any one of claims 1 to 8, comprising: Under the control of an input signal from an input terminal, the potential of the first node is controlled by the input signal, and under the control of a first power supply voltage from a first power supply, the potential of the second node is controlled by the first power supply voltage; Under the control of the potential of the first node and the input signal, controlling the potential of the second node by using a first power supply voltage of a first power supply; controlling the potential of the first node according to the potential of the second node and a second power supply voltage of a second power supply; as well as Under the control of the potential of the first node and the potential of the second node, an output signal is output based on a clock signal from a clock terminal and the first power supply voltage.