Pixel circuit and display device including same

Abstract

The invention discloses a pixel circuit and a display device including the same. A pixel circuit of the present disclosure includes: a driving element configured to adjust a current flowing to a light emitting element according to a gate-source voltage thereof; and a boost circuit electrically connected to the driving element. The driving element includes a first electrode, a gate electrode, and a second electrode. The booster circuit supplies a current to the first electrode of the driving element in each of a first mode and a second mode, and a peak current supplied to the first electrode of the driving element during the second mode is greater than a peak current supplied to the first electrode of the driving element during the first mode.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0190879, filed on December 26, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a pixel circuit and a display device including the pixel circuit. Background art

[0004] Flat panel display devices include liquid crystal displays (LCDs), electroluminescent displays, field emission displays, plasma display panels, etc. According to the material of the light - emitting layer, electroluminescent displays can be classified into inorganic light - emitting displays and organic light - emitting displays.

[0005] In recent years, point light sources using light - emitting diodes (LEDs) can be used as backlight light sources for liquid crystal displays (LCDs) to precisely achieve local dimming.

[0006] Although organic light - emitting diodes (OLEDs) require a separate encapsulation layer to protect the organic materials from moisture, micro - LEDs do not require an encapsulation layer, emit light faster, and have better light efficiency and impact resistance than OLEDs.

[0007] External light reflected from the display panel may cause deterioration in the visibility of the image being reproduced. To overcome this, it is necessary to drive the pixels at a high brightness. However, driving the pixels at a high brightness increases the dynamic range of the data voltage applied to the pixels, which increases power consumption and reduces the voltage margin required for external compensation. Summary of the invention

[0008] The present disclosure aims to solve the above - mentioned needs and / or problems.

[0009] The present disclosure provides a pixel circuit capable of driving pixels at a high brightness without increasing the dynamic range of the data voltage and ensuring a sufficient compensation margin voltage, and a display device including the pixel circuit.

[0010] The problems to be solved by the present disclosure are not limited to the problems mentioned above, and those skilled in the art will clearly understand other problems not mentioned based on the following description.

[0011] In one embodiment, a pixel circuit includes: a light-emitting element; a driving element connected to the light-emitting element and configured to adjust a current flowing to the light-emitting element according to a gate-source voltage of the driving element, the driving element including a first electrode, a gate electrode, and a second electrode; and a boosting circuit electrically connected to the driving element and configured to supply a current to the first electrode of the driving element in each of a first mode and a second mode, wherein a first peak value of the current supplied to the first electrode of the driving element in the second mode is greater than a second peak value of the current supplied to the first electrode of the driving element in the first mode.

[0012] In one embodiment, a display device includes: a plurality of pixels, each of the plurality of pixels including: a light-emitting element; a driving element electrically connected to the light-emitting element and configured to control a current flowing to the light-emitting element, the driving element including a first electrode, a gate electrode, and a second electrode; and a boosting circuit electrically connected to the first electrode of the driving element, the boosting circuit including: a first switching element including a first electrode connected to a first node to which a first input voltage is applied, a gate electrode connected to a third node, and a second electrode connected to the first electrode of the driving element; a second switching element electrically connected to a second node to which a second input voltage is applied and electrically connected to the first switching element at the third node, the second switching element being configured to supply the second input voltage to the third node in response to a first selection signal; and a first capacitor connected to a node to which a first boosting signal is applied and electrically connected to the gate electrode of the first switching element at the third node, wherein, during a first mode of the display device, the first boosting signal is a first boosting voltage, and a magnitude of a current supplied to the first electrode of the driving element is a first value, and during a second mode of the display device, the first boosting signal is a second boosting voltage greater than the first boosting voltage, and a magnitude of a current supplied to the first electrode of the driving element is a second value greater than the first value.

[0013] According to the present disclosure, by embedding a boosting circuit in each of the pixels, it is possible to drive the pixels at high brightness without increasing a dynamic range of a data voltage output from a data driving circuit in an HDR mode. Therefore, the present disclosure enables driving a display device with low power, and a compensation margin voltage for compensating electrical characteristics of a transistor can be sufficiently ensured within an output voltage range of the data driving circuit.

[0014] According to the present disclosure, within an output voltage range of a data driving circuit, a dynamic range of an HDR mode can be set to be the same as a dynamic range of an SDR mode, thereby sufficiently ensuring a compensation margin voltage to extend a lifespan of the display device without deteriorating image quality.

[0015] The threshold voltage sensing of the driving element and the writing of pixel data can be separated in time to ensure sufficient time for threshold voltage sensing, which can accurately compensate for the threshold voltage of the driving element and improve the brightness uniformity on the screen.

[0016] According to the present disclosure, by separating the capacitor for storing the threshold voltage of the driving device and the capacitor for storing the data voltage, error components can be prevented from charging in the main node of the pixel circuit.

[0017] According to the present disclosure, when the driving frequency of the pixel changes with the change of the refresh rate, by separately setting the anode reset voltage from the reference voltage, the brightness difference of the pixel can be minimized or at least reduced.

[0018] According to the present disclosure, the low-power driving of the display device can be achieved by separately setting the anode reset voltage from the reference voltage so that the cathode voltage can be set to 0 [V].

[0019] According to the present disclosure, the level shifter and the gate driver can be shared in the driving circuit of the display panel designed with different pixels. For example, in the present disclosure, one shift register and four edge flip-flops can be used to output the pulses of the first to fifth gate signals and can be shared with other pixel circuits.

[0020] The effects of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] By describing in detail the exemplary embodiments of the present disclosure with reference to the accompanying drawings, the above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art. In the drawings:

[0022] Figure 1A and Figure 1B is a diagram showing a pixel circuit according to an embodiment of the present disclosure;

[0023] Figure 2 is a circuit diagram showing a boost circuit according to an embodiment of the present disclosure;

[0024] Figure 3 is showing Figure 2 the waveforms of the operation of the boost circuit shown in the SDR mode and the HDR mode;

[0025] Figure 4 is a circuit diagram showing a boost circuit according to another embodiment of the present disclosure;

[0026] Figures 5A to 5B Shows Figure 4 The waveforms of the operation of the boost circuit shown in the HDR mode;

[0027] Figure 6 Is a circuit diagram showing a pixel circuit according to an embodiment of the present disclosure;

[0028] Figure 7 Shows Figure 6 The waveform diagram of the operation of the boost circuit shown in the SDR mode and the HDR mode;

[0029] Figure 8 Shows for verification Figure 7 The diagram showing the simulation results of the boost effect of the pixel circuit shown;

[0030] Figure 9 Is a circuit diagram showing a pixel circuit according to another embodiment of the present disclosure;

[0031] Figure 10 Is a circuit diagram showing a pixel circuit according to yet another embodiment of the present disclosure;

[0032] Figure 11 Shows the application to Figure 10 The waveform diagram of the gate signal and the data voltage of the pixel circuit shown;

[0033] Figure 12 Is a block diagram showing a display device according to an embodiment of the present disclosure;

[0034] Figure 13 Is a block diagram showing a display device according to another embodiment of the present disclosure;

[0035] Figure 14 Shows Figure 13 The perspective view of the display panel and the backlight unit shown; and

[0036] Figure 15 Is a diagram showing an example of the dynamic range of the data voltage output from the data driver. Detailed Description

[0037] The advantages and features of the present disclosure and the method for realizing the same will be more clearly understood from the embodiments described below with reference to the drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in various different forms. On the contrary, the present embodiments will make the disclosure of the present disclosure complete and enable those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is only limited within the scope of the appended claims.

[0038] The shapes, dimensions, ratios, angles, numbers, etc. shown in the drawings for describing the embodiments of the present disclosure are only examples, and the present disclosure is not limited thereto. Throughout the present specification, like reference numerals generally denote like elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0039] Terms such as "comprising", "including", "having", and "containing" used herein generally intend to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular may include the plural unless otherwise explicitly stated.

[0040] Even if not explicitly stated, components are interpreted to include a normal error range.

[0041] When describing the positional or interconnection relationship between two components, such as "above...", "over...", "below...", "next to...", "connected or coupled to...", "crossing", "intersecting", etc., one or more other components may be inserted between them unless the terms "immediately" or "directly" are used.

[0042] When describing the time precedence relationship, such as "after...", "behind...", "immediately following", "before...", etc., it may not be continuous on a time basis unless the terms "immediately" or "directly" are used.

[0043] Terms such as "first", "second", etc. may be used to distinguish elements from each other, but the functions or structures of the components are not limited by the serial numbers or component names in front of the components.

[0044] The following embodiments may be partially or wholly joined or combined with each other and may be linked and operated in various technical ways. The embodiments may be executed independently or in association with each other.

[0045] The pixel circuit and the gate driving circuit of the display device may include a plurality of transistors. The transistors may be implemented as thin film transistors (TFTs). The transistors may be implemented as oxide thin film transistors (TFTs) including oxide semiconductors, low temperature polycrystalline silicon TFTs (LTPS TFTs) including low temperature polycrystalline silicon, etc.

[0046] Hereinafter, the pixel circuit may represent at least one of a display pixel circuit of a display panel for visually reproducing an input image and a local dimming pixel circuit for driving a light source that irradiates light to the display panel. The data written to the pixel circuit may be pixel data written to the display pixel circuit or local dimming data written to the local dimming pixel circuit.

[0047] A transistor is a three - electrode element including a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. In a transistor, carriers start to flow from the source. The drain is the electrode through which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n - channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. The n - channel transistor has a current direction from the drain to the source. In the case of a p - channel transistor (p - channel metal - oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p - channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the present disclosure is not limited to the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0048] The gate signal swings between a gate - on voltage and a gate - off voltage. The transistor turns on in response to the gate - on voltage and turns off in response to the gate - off voltage. In the case of an n - channel transistor, the gate - on voltage can be a gate - high voltage VGH, and the gate - off voltage can be a gate - low voltage VGL. In the case of a p - channel transistor, the gate - on voltage can be a gate - low voltage VGL, and the gate - off voltage can be a gate - high voltage VGH.

[0049] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0050] Figure 1A and Figure 1B is a diagram showing a pixel circuit according to an embodiment of the present disclosure.

[0051] Referring to Figure 1A and Figure 1B , the pixel circuit includes a light - emitting element EL, a driving element DT for driving the light - emitting element EL, and a boosting circuit 10. The pixel circuit may further include a compensation circuit 20 electrically connected to the driving element DT. The boosting circuit 10 and the compensation circuit 20 may include a plurality of switching elements. The switching elements of the boosting circuit 10 and the compensation circuit 20 and the driving element DT may be implemented as transistors.

[0052] The boosting circuit 10 receives a first input voltage, a second input voltage Vini, a selection signal S1, and a boosting signal S2, and selectively raises the voltage applied to the driving element DT for driving the pixel at high brightness. The first input voltage may be as Figure 1AThe pixel driving voltage EVDD shown, or the voltage input through the light-emitting element EL that is turned on as shown in Figure 1B The first input voltage may be a constant voltage supplied to the boost circuit 10 through the first node n1 of the boost circuit 10, and the second input voltage Vini may be a constant voltage supplied to the boost circuit 10 through the second node n2 of the boost circuit 10. The boost circuit 10 may include a plurality of switching elements and capacitors.

[0053] The boost circuit 10 drives the pixels in a standard dynamic range (SDR) in the first mode (hereinafter referred to as the "SDR mode"). The boost circuit 10 may drive the pixels in a high dynamic range (HDR) in the second mode (hereinafter referred to as the "HDR mode"). The boost circuit 10 supplies current to the first electrode of the driving element DT in each of the SDR mode and the HDR mode. The boost circuit 10 may cause the first peak value of the current supplied to the first electrode of the driving element DT in the HDR mode to be greater than the second peak value of the current supplied to the first electrode of the driving element in the SDR mode. That is, the magnitude of the current supplied to the first electrode of the driving element DT during the HDR mode is a second value that is greater than the first value of the magnitude of the current supplied to the first electrode of the driving element DT during the SDR mode.

[0054] The boost circuit 10 may include a plurality of switching elements and capacitors electrically connected to the driving element DT. The compensation circuit 20 may receive the data voltage Vdata of the pixel data, the gate signals G1, G2, and apply the data voltage Vdata of the pixel data to the gate electrode of the driving element DT. The boost circuit 10 may be implemented as an external compensation circuit and / or an internal compensation circuit. The external compensation circuit senses the electrical characteristics of the driving device DT, such as its threshold voltage and mobility, and modulates the pixel data (digital data) of the input image by the amount of deviation (or change) of the electrical characteristics of the driving device DT to compensate for the deviation (or change) of the electrical characteristics of the driving device DT in real time at each pixel. The internal compensation circuit samples the threshold voltage of the driving device DT embedded in each of the pixel circuits of each sub-pixel, and compensates the gate-source voltage of the driving device DT through the threshold voltage.

[0055] The light-emitting element EL may be implemented as, but not limited to, an organic light-emitting diode (OLED), a micro LED, a mini LED, etc. The light-emitting element EL may include an anode electrode, a cathode electrode, and a light-emitting layer formed between the electrodes.

[0056] As shown in Figure 1A The anode electrode of the light-emitting element EL is electrically connected to the second electrode of the driving element DT, and the cathode voltage EVSS may be applied to its cathode electrode. As shown in Figure 1BAs shown, a pixel driving voltage EVDD is applied to an anode electrode of a light-emitting element EL, and a cathode electrode of the light-emitting element EL can be electrically connected to a boosting circuit 10 through a first node n1.

[0057] A driving element DT includes a first electrode connected to the boosting circuit 10, a gate electrode connected to a compensation circuit 20, and a second electrode. The driving element DT drives the light-emitting element EL by adjusting a current required to drive the light-emitting element EL with its gate-source voltage. The gate-source voltage of the driving element DT varies with a data voltage Vdata. Accordingly, the pixel can emit light with a luminance corresponding to a grayscale value of pixel data.

[0058] Figure 2 is a circuit diagram showing a boosting circuit according to an embodiment of the present disclosure. Figure 3 is showing Figure 2 operation waveforms of the boosting circuit shown in an SDR mode and an HDR mode. In Figure 3 ,"VGH" is a gate conduction voltage, and "VGL" is a gate cutoff voltage. "VBH" is a boosted high voltage, and "VBL" is a boosted low voltage.

[0059] Referring to Figure 2 and Figure 3 , the boosting circuit 10 includes a first switching element M1, a second switching element M2, and a capacitor C11. The switching elements M1 and M2 can be implemented as but are not limited to n-channel transistors.

[0060] The first switching element M1 is connected between the first node n1 and the first electrode of the driving element DT, and is turned on in response to a gate conduction voltage VGH of a selection signal S1. When the first switching element M1 is turned on, the first switching element M1 supplies a voltage to the first electrode of the driving element DT. In the HDR mode, a gate voltage Vg of the first switching element M1 can be boosted to increase an amount of a source-drain current of the first switching element M1, thereby increasing a voltage applied to the driving element DT. The first switching element M1 includes a first electrode connected to the first node n1, a gate electrode connected to a third node n3, and a second electrode connected to the first electrode of the driving element DT.

[0061] The second switching element M2 is connected between a second node n2 and the third node n3, and is turned on in response to a gate conduction voltage VGH of the selection signal S1. When the second switching element M2 is turned on, a second input voltage Vini input to the second node n2 is applied to the third node n3. The second switching element M2 includes a first electrode connected to the second node n2, a gate electrode to which the selection signal S1 is applied, and a second electrode connected to the third node n3.

[0062] The capacitor C11 is a coupling capacitor connected between the node to which the boost signal S2 is applied and the third node n3 to transmit the voltage of the boost signal S2 to the third node n3. The voltage of the boost signal S2 can be a pulse voltage that swings between the boost high voltage VBH and the boost low voltage VBL. When the boost high voltage VBH is applied to the third node n3, the gate voltage Vg of the first switching element M1 can be boosted such that the voltage applied to the gate electrode of the first switching element M1 can be as high as Vini+(VBH - VBL), as shown in Table 1 below.

[0063] The gate voltage Vg applied to the third node n3 can be controlled as shown in Table 1 below. In Table 1, "boost off" is the SDR mode, and "boost on" is the HDR mode. In the SDR mode, the gate voltage Vg of the first switching element M1 is the voltage Vini, while in the HDR mode, the gate voltage Vg of the first switching element M1 increases to the voltage Vini+(VBH - VBL). Therefore, the boost circuit can control the peak current flowing through the first switching element M1, thereby increasing the brightness of the pixel more in the HDR mode than in the SDR mode. When the amount of current flowing through the first switching element M1 increases, the voltage applied to the first electrode of the driving element DT increases, and the amount of current flowing through the light-emitting element EL also increases, which can increase the brightness of the light-emitting element EL.

[0064] [Table 1]

[0065] Vg Boost turn-off Vini Boost turn-on Vini + (VBH - VBL)

[0066] Refer to Figure 3 , the voltage of the selection signal S1 can be generated as a pulse that swings between the gate-on voltage VGH and the gate-off voltage VGL in the SDR mode (boost off) and the HDR mode (boost on), respectively. After the pulse of the selection signal S1 decreases to the gate-off voltage VGL, the voltage of the boost signal S2 can be the boost low voltage VBL in the SDR mode (boost off), and can be generated as the boost high voltage VBH in the HDR mode (boost on), which is higher than the boost low voltage VBL. In the SDR mode (boost off), the gate voltage Vg of the first switching element M1 is equal to the second input voltage Vini, while in the HDR mode, the gate voltage Vg of the first switching element M1 is boosted to a voltage Vg = Vini+(VBH - VBL) higher than Vini. Figure 3 The voltages set in the simulation are shown, and these voltages are set to but not limited to VGH = 6V, VGL = 0V, VBH = 17V, VBL = 0V, and Vini = 3V. Figure 4 is a circuit diagram showing a boost circuit according to another embodiment of the present disclosure. Figure 5A andFigure 5B shows Figure 4 a waveform diagram of the operation of the boost circuit shown in the HDR mode.

[0067] Referring to Figures 4 to 5B , the boost circuit 10 includes a first switching element M1, a second switching element M2, a third switching element M3, a first capacitor C11, and a second capacitor C12. The switching elements M1, M2, and M3 may be implemented as n-channel transistors, but are not limited thereto.

[0068] The first switching element M1 includes a first electrode connected to the first node n1, a gate electrode connected to the third node n3, and a second electrode connected to the first electrode of the driving element DT.

[0069] The second switching element M2 is connected between the second node n2 and the fourth node n4 and conducts in response to the gate conduction voltage VGH of the selection signal S1. When the second switching element M2 conducts, the second input voltage Vini input to the second node n2 is applied to the fourth node n4. The second switching element M2 includes a first electrode connected to the second node n2, a gate electrode to which the selection signal S1 is applied, and a second electrode connected to the fourth node n4.

[0070] The first capacitor C11 is a coupling capacitor connected between the node to which the boost signal S2 is applied and the fourth node n4 to transmit the voltage of the boost signal S2 to the fourth node n4. In the HDR mode, the voltage of the boost signal S2 is applied as the boost high voltage VBH to increase the voltage of the fourth node n4.

[0071] The third switching element M3 is connected between the third node n3 and the fourth node n4 and conducts in response to the gate conduction voltage VGH of the second selection signal S3. When the third switching element M3 conducts, the voltage of the fourth node n4 is applied to the third node n3. The third switching element M3 includes a first electrode connected to the fourth node n4, a gate electrode to which the second selection signal S3 is applied, and a second electrode connected to the third node n3.

[0072] The second capacitor C12 is a coupling capacitor connected between the node to which the second boost signal S4 is applied and the third node n3 to transmit the voltage of the second boost signal S4 to the third node n3. In the HDR mode, the voltage of the second boost signal S4 is applied as the boost high voltage VBH to increase the voltage of the third node n3.

[0073] Figure 5A An example is shown in which the boost circuit 10 boosts the gate voltage Vg only by primary boosting.

[0074] Referring to Figure 5A, the second switching element M2 and the third switching element M3 are turned on in response to the gate conduction voltage VGH of the first selection signal S1 and the second selection signal S3, and when the second boosting signal S4 is the boosting high voltage VBH, the gate voltage Vg applied to the third node n3 is boosted to Vg = Vini + (VBH - VBL). After the pulses of the first selection signal S1 and the second selection signal S3 are generated simultaneously to turn on the second switching element M2 and the third switching element M3 simultaneously, the voltage of the second boosting signal S4 can be increased to the boosting high voltage VBH. When the boosting circuit 10 only performs the primary boosting operation, the voltage of the boosting signal S2 is the boosting low voltage VBL.

[0075] Figure 5B An example in which the boosting circuit 10 further increases the gate voltage Vg through primary boosting and secondary boosting is shown.

[0076] Refer to Figure 5B , the second switching element M2 is turned on in response to the gate conduction voltage VGH of the selection signal S1, so that the voltage of the fourth node n4 is boosted, which occurs when the boosting signal S2 is the boosting high voltage VBH.

[0077] Subsequently, the third switching element M3 is turned on in response to the gate conduction voltage VGH of the second selection signal S3, so that the voltage of the second boosting signal S4 is increased to the boosting high voltage VBH. In this case, the gate voltage Vg applied to the third node n3 can be boosted to Vg = Vini + (VBH - VBL) * 2.

[0078] Figure 6 is a circuit diagram showing a pixel circuit according to an embodiment of the present disclosure. Figure 7 is showing Figure 6 the waveforms of the operations of the boosting circuit shown in the SDR mode and the HDR mode.

[0079] Refer to Figure 6 and Figure 7 , the pixel circuit includes a light emitting element EL, a driving element DT for driving the light emitting element EL, a boosting circuit 10, and a compensation circuit 20. The boosting circuit 10 and the compensation circuit 20 may include a plurality of switching elements M1, M2, M31, and T1, T2. The switching elements M1, M2, M31, T1, and T2 of the boosting circuit 10 and the compensation circuit 20 and the driving element DT may be implemented as n-channel transistors, but are not limited thereto.

[0080] The pixel circuit is connected to a data line DL to which a data voltage Vdata is applied and a gate line to which a gate signal SCAN, SENSE, and selection signals S1, S31 are applied. The gates SCAN and SENSE may include a first gate signal SCAN and a second gate signal SENSE. The pixel circuit is connected to a constant voltage node to which a DC voltage (or a constant voltage) is applied, for example, a VDD node (a first constant voltage node) to which a pixel driving voltage EVDD is applied, a VSS node (a second constant voltage node) to which a cathode voltage is applied, and a REF node (a third constant voltage node) to which a reference voltage Vref is applied. The constant voltage nodes are connected to power lines provided on the display panel, and the power lines may be commonly connected to all pixels.

[0081] In the SDR mode and the HDR mode, the dynamic range of the data voltage Vdata may be set to be the same. For example, in the SDR mode and in the HDR mode, the data voltage Vdata may have a dynamic range of 0V to 18V. The data voltage Vdata may be a voltage selected according to the gray value of the pixel data. The reference voltage Vref may be a voltage selected from a voltage range of 1V to 3V. The pixel driving voltage EVDD may be a voltage selected from a voltage range between 15V and 20V, and the cathode voltage EVSS may be 0V, but is not limited thereto. The gate-on voltage VGH of the gate signals SCAN, SENSE, and the selection signal S1 may be set to 24V, and the gate-off voltage VGL of the gate signals SCAN, SENSE, and the selection signal S1 may be set to -12V, but is not limited thereto. The second input voltage Vini may be 3V to 12V. The boost high voltage VBH and the boost low voltage VBL of the boost signal S2 may be selected between 0V and 17V. In one example, the boost high voltage VBH may be selected from voltages between 5V and 12V, and the boost low voltage VBL may be selected from voltages between 0V and 5V. These voltages are not limited to those shown in the above figures.

[0082] The driving element DT includes a first electrode connected to a first pixel node D, a gate electrode connected to a second pixel node G, and a second electrode connected to a third pixel node S. The light-emitting element EL includes an anode electrode connected to the third pixel node S and a cathode electrode connected to a VSS node to which a cathode voltage EVSS is applied.

[0083] The boost circuit 10 may include a first switching element M1, a second switching element M2, and a capacitor C11. The boost circuit 10 may be implemented as Figure 4 the multi-boost circuit shown. The boost circuit 10 may further include a reset switching element M31.

[0084] The reset switch element M31 is connected between the third node n3 and the VSS node, and can be turned on in response to the gate conduction voltage VGH of the reset signal S31, and turned off in response to the gate turn-off voltage VGL of the reset signal S31. As Figure 7 shown, when the reset switch element M31 is turned on, the third node n3 can be electrically connected to the VSS node, so that the gate voltage Vg of the third node n3 can be reset.

[0085] The compensation circuit 20 may include a first pixel switch element T1, a second pixel switch element T2, and a storage capacitor Cst.

[0086] The first pixel switch element T1 is connected between the data line to which the data voltage Vdata is applied and the second pixel node G, and is turned on in response to the gate conduction voltage VGH of the first gate signal SCAN. When the first pixel switch element T1 is turned on, the data voltage Vdata is applied to the second pixel node G. The first pixel switch element T1 includes a first electrode connected to the data line, a second electrode connected to the second pixel node G, and a gate electrode connected to the gate line to which the first gate signal SCAN is applied.

[0087] The second pixel switch element T2 is connected between the REF node to which the reference voltage Vref is applied and the third pixel node S, and is turned on in response to the gate conduction voltage VGH of the second gate signal SENSE. When the second pixel switch element T2 is turned on, the reference voltage Vref is applied to the third pixel node S. The second pixel switch element T2 includes a first electrode connected to the REF node, a second electrode connected to the third pixel node S, and a gate electrode connected to the gate line to which the second gate signal SENSE is applied.

[0088] The storage capacitor Cst is connected between the second pixel node G and the third pixel node S to charge the gate-source voltage of the driving element DT.

[0089] As Figure 7 shown, in the HDR mode (boost turn-on), the gate voltage Vg of the first switch element M1 is boosted to increase the drain current (Id) of the driving element DT. Therefore, in the HDR mode (boost turn-on), the amount of current flowing to the light-emitting element EL increases, so that the light-emitting element EL can emit light with high brightness.

[0090] Figure 8 is a diagram showing Figure 7 the simulation results for verifying Figure 8Among them, the abscissa is the data voltage (Vdata [V]), and the ordinate is the average current (Iavg) of the drain current (Id) supplied to the driving element DT through the first switching element M1. The simulation conditions are as follows: EVDD = 15V, Vini = 3V, Vref = 0V, Vdata = 0 to 3V, S1 = 6V, SCAN = 6V, SENSE = 6V, S2 = 17V, C11 = Cst = 1Nf, the resistance (R) of the VDD node = 100Ω, the channel width (W) of the transistors DT and M1 is 200μm, and the channel length (L) of the transistors DT and M1 is 10μm. As Figure 8 shown, in this simulation, it is found that the current (Iavg) flowing through the first switching element M1 is higher in the HDR mode than in the SDR mode.

[0091] Figure 9 is a circuit diagram showing a pixel circuit according to another embodiment of the present disclosure. In this embodiment, components that are substantially the same as those in the previous embodiment are denoted by the same reference numerals and will not be described in detail. The pixel circuit PIX can be substantially the same as the Figure 6 circuit shown.

[0092] Referring to Figure 9 , the first switching element T1 of the pixel circuit PIX is connected to the data line DL, and the second switching element T2 is connected to the reference voltage line RL to which the reference voltage Vref is applied.

[0093] The present disclosure may include a digital-to-analog converter (DAC) that converts pixel data or local dimming data input as a digital signal into a data voltage Vdata and outputs it in a display mode, an analog-to-digital converter (ADC) that converts the voltage charged on the reference voltage line RL into digital data and outputs it, a boost voltage generator 900, a sampling switch element SAM, and a reference voltage switch element SPRE. The DAC, ADC, sampling switch element SAM, and reference voltage switch element SPRE may be embedded in a driver IC (DIC) in which a data driver is integrated.

[0094] The boost voltage generator 900 may be implemented as a level shifter that converts the voltage level of a digital signal into a boost high voltage VBH and a boost low voltage VBL, or it may be implemented as a DAC that converts a digital signal into an analog voltage. The digital signal input to the boost voltage generator 900 may include data values indicating the voltage levels of each of the boost high voltage VBH and the boost low voltage VBL. This digital signal may be derived from Figure 12 and Figure 13The controllers 130 and 500 shown. The boost voltage generator 900 can be embedded in the driving IC (DIC) or provided outside the driving IC, and is electrically connected to the pixel circuit PIX through the sampling switch element SAM. The sampling switch element SAM and the reference voltage switch element SPRE can be turned on / off under the control of the controller.

[0095] The sensing circuit of the external compensation circuit can include an ADC, a sampling switch element SAM, and a reference voltage switch element SPRE to sense the threshold voltage of the driving element DT in the sensing mode. The sensing mode can be activated during at least one of the following sequences: the power-on sequence for applying power to the display device, the vertical blanking time during the display time, and the power-off sequence when the power-off switch of the display device is turned on.

[0096] In the sensing mode, the second switch element T2 of the pixel circuit PIX and the reference voltage switch element SPRE are turned on to apply the reference voltage Vref to the reference voltage line RL. At this time, the sampling switch element SAM connects the reference voltage line RL to the floating node 92. Subsequently, when the sampling switch element SAM is connected to the input node 91 of the ADC, the voltage of the third pixel node D is input to the ADC through the reference voltage line RL, so that the threshold voltage of the driving element DT can be sensed.

[0097] The display mode can be divided into an HDR mode and an SDR mode. In the display mode, the data voltage Vdata is applied to the second pixel node G through the first pixel switch element T1, and the boost signal S2 output from the boost voltage generator 900 is applied to the capacitor C11 through the reference voltage line RL. At this time, the sampling switch element SAM can connect the reference voltage line RL to the output node 93 of the boost voltage generator 900, and the second pixel switch element T2 can be turned off. In the HDR mode, the voltage of the boost signal S2 can be increased to the boost high voltage VBH. In the SDR mode, the voltage of the boost signal S2 can be maintained at the boost low voltage VBL.

[0098] Figure 10 is a circuit diagram showing a pixel circuit according to another embodiment of the present disclosure. In this embodiment, components that are substantially the same as those in the previous embodiment are denoted by the same reference numerals and will not be described in detail. Although Figure 2 the pixel circuit shown has been applied to Figure 10 the boost circuit 10 in Figure 4 the boost circuit shown. Figure 11 is a waveform diagram showing the gate signal and data voltage applied to Figure 10 the pixel circuit shown.

[0099] Refer to Figure 10And Figure 11 , the compensation circuit 20 may include a first pixel switching element T1, a second pixel switching element T2, a third pixel switching element T3, and a capacitor Cst.

[0100] The third pixel switching element T3 is connected between a constant voltage node to which an initialization voltage Vini2 is applied and a second pixel node G, and is turned on in response to a gate conduction voltage VGH of a third gate signal INIT. When the third pixel switching element T3 is turned on, the initialization voltage Vini2 is applied to the second pixel node G. The initialization voltage Vini2 may be set to, but is not limited to, a voltage between 3V and 12V.

[0101] The pixel circuit may be driven through an initialization phase, a threshold voltage sampling phase, a floating sensing phase, a data writing phase, and a light emitting phase. The initialization phase is executed during a first period Pi. During the first period Pi, the third pixel switching element T3 is turned on in response to a gate conduction voltage VGH of a third gate signal INIT, and the second pixel switching element T2 is turned on in response to a gate conduction voltage VGH of a second gate signal SENSE. During the first period Pi, the driving element DT may be turned on.

[0102] The threshold voltage sampling phase and the floating phase are executed during a second period Ps and a third period Pf. During the second period Ps, the second pixel switching element T2 remains in the on state. During the second period Ps, when the voltage of the third pixel node S rises and the gate-source voltage of the driving element DT is lower than the threshold voltage of the driving element DT, the driving element DT is turned off, so that the voltage of the third node S can be sensed through the REF node and the reference voltage line RL. The gate signals SCAN, SENSE, and INIT are at a gate cutoff voltage VGL during the third period Pf. During the third period Pf, the first to third pixel switching elements T1, T2, and T3 are in the off state, so the second pixel node G and the third pixel node S are floating.

[0103] A data writing phase is performed during the fourth period Pwr. During the fourth period Pwr, the first switching element T1 is turned on in response to the gate-on voltage VGH of the first gate signal SCAN synchronized with the data voltage Vdata. During the fourth period Pwr, the data voltage Vdata may be applied to the second pixel node G, and thus the gate-source voltage of the driving element DT for driving the light-emitting element EL may be set according to the data voltage Vdata. In this case, the mobility (μ) of the driving element DT can be compensated. For example, when the mobility of the driving element DT is large within the fourth period Pwr, the voltage of the third pixel node S increases, which reduces the gate-source voltage of the driving element DT. In contrast, when the mobility of the driving element DT is relatively small, the voltage of the third node S decreases, which increases the gate-source voltage Vgs of the driving element DT. A light-emitting phase is performed during the fifth period Pem. During the fifth period Pem, the light-emitting element EL can emit light through the current generated according to the gate-source voltage of the driving element DT. In the HDR mode, during the fourth period Pwr or the fifth period Pem, the drain current of the driving element DT can be increased by the boost circuit 10 to increase the brightness of the light-emitting element EL.

[0104] Figure 12 is a block diagram showing a display device according to an embodiment of the present disclosure.

[0105] Referring to Figure 12 , the display device includes a display panel 100 and a display panel driving circuit for writing pixel data into the display pixels 101 of the display panel 100. The display device further includes a power supply 140.

[0106] The display panel 100 may be, but is not limited to, a panel having a rectangular structure, which has a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. For example, the display panel 100 may be a deformed panel that is at least partially curved or elliptical.

[0107] The display area AA of the display panel 100 includes a pixel array for displaying an input image thereon. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and a plurality of display pixels 101. The display panel 100 may further include power lines commonly connected to the display pixels 101. The power lines may be commonly connected to the pixel circuits and supply the voltage required to drive the display pixels 101 to the display pixels 101.

[0108] Each of the display pixels 101 is connected to a corresponding data line 102, a plurality of gate lines 103, and a power line. Constant voltages such as a pixel driving voltage EVDD, a cathode voltage EVSS, a second input voltage Vini, a reference voltage Vref, and an initialization voltage Vini2 can be supplied to the display pixels 101 through the power line. The gate lines may include a first gate line to which a first gate signal SCAN is applied, a second gate line to which a second gate signal SENSE is applied, a third gate line to which a third gate signal INIT is applied, a fourth gate line to which a selection signal S1 is applied, and a fifth gate line to which a second selection signal S3 is applied. According to the above-described embodiments of the pixel circuit, some of the gate signals and selection signals can be omitted.

[0109] Each of the display pixels 101 can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color implementation. Each of the display pixels 101 may further include a white sub-pixel. Each of the sub-pixels includes a display pixel circuit for driving a light-emitting element. The display pixel circuit can be implemented as any one of the pixel circuits shown in FIGS. 1 to Figure 9 any of the pixel circuits shown.

[0110] The display array AA includes a plurality of display pixel lines L1 to Ln. Each of the display pixel lines L1 to Ln includes a row of display pixels 101 arranged in the display area AA of the display panel 100 in the gate line direction (X-axis direction). The display pixels 101 provided in one pixel line may share the gate lines 103. The sub-pixels arranged in the column direction (Y-axis direction) along the data line share the same data line 102. One horizontal period is a time obtained by dividing one frame period by the total number of the display pixel lines L1 to Ln.

[0111] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel can be applied to a transparent display device in which an image is displayed on the screen and an actual object is visible outside the display panel. The display panel 100 can be made into a flexible display panel that can be flexibly bent.

[0112] The power supply 140 receives the input voltage provided by the host system 300 and outputs the voltages required to drive the display pixels 101 of the display panel 100 and the display panel driving circuit. To this end, the power supply 140 may include a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 140 may output a constant voltage (or DC voltage) through the DC-DC converter, for example, the gate-on voltage VHG, the gate-off voltage VGL, the pixel driving voltage EVDD, the cathode voltage EVSS, the IC driving voltage for the display panel driving circuit, etc. The gate-on voltage VGH and the gate-off voltage VGL are supplied to the level shifter 150 and the gate driver 120.

[0113] The power supply 140 may further include a gamma voltage generator. The gamma voltage generator receives a high-potential reference voltage and a low-potential reference voltage and outputs a plurality of gamma reference voltages divided at a predetermined voltage interval on a preset gamma curve (for example, a 2.2 gamma curve). The gamma reference voltages are supplied to the data driver 110. In the data driver 110, the gamma reference voltages are divided by a voltage dividing circuit and subdivided into gray-scale voltages. The gamma voltage generator may be implemented as a programmable gamma circuit capable of adjusting each gamma reference voltage according to digital data. The controller 130 or the host system 300 or a separate external device may update the digital data stored in the register of the programmable gamma circuit through a communication interface.

[0114] The display panel driving circuit writes the pixel data of the input image to the display pixels 101 of the display panel 100 under the control of the controller 130. The display panel driving circuit includes a data driver 110, a gate driver 120, a boost voltage generator 900, and a level shifter 150. The display panel driving circuit may further include a touch sensor driver for driving a touch sensor. Figure 12 The touch sensor driver is omitted. The data driver 110 and the touch sensor driver may be integrated together in a driving integrated circuit (DIC).

[0115] The data driver 110 receives the pixel data of the input image from the controller 130 and outputs a data voltage Vdata. The data driver 110 may receive gamma reference voltages and generate gamma compensation voltages of gray scales through a voltage dividing circuit. The gamma compensation voltages of each gray scale are supplied to a digital-to-analog converter (“DAC”) provided on the corresponding channel of the data driver 110.

[0116] The data driver 110 samples and latches the digital data received from the controller 130, and then inputs the digital data to the DAC. The digital data includes pixel data of the input image. The DAC converts the pixel data into a gamma-compensated voltage and outputs the data voltage Vdata of the pixel data.

[0117] The gate driver 120 may be formed on the display panel 100 together with the circuit elements and wirings of the display area AA. The gate driver 120 may be disposed in the non-display area NA on at least one of the right or left sides outside the display area AA in the display panel 100, or at least a part of the gate driver 120 may be disposed within the display area AA.

[0118] The gate driver 120 may be disposed in the non-display areas NA on both sides of the display panel 100, with the display area AA of the display panel being between the non-display areas NA, and may supply gate pulses from both sides of the gate line 103 in a dual-feed method. The gate driver 120 may be disposed in at least one of the left non-display area NA and the right non-display area NA of the display panel 100 to supply a gate signal to the gate line 103 in a single-feed method. The gate driver 120 may use a shift register or an edge trigger to shift the pulses of the gate signal to sequentially supply these signals to the gate line 103.

[0119] The gate driver 120 may include a first gate driver that supplies a first gate signal SCAN to the first gate line, a second gate driver that supplies a second gate signal SENSE to the second gate line, a third gate driver that supplies a third gate signal INIT to the third gate line, a fourth gate driver that supplies a selection signal S1 to the fourth gate line, and a fifth gate driver that supplies a second selection signal S3 to the fifth gate line. According to the above-described embodiments of the pixel circuit, some of the gate drivers may be omitted.

[0120] The boost voltage generator 900 outputs a boost high voltage VBH in the HDR mode and a boost low voltage VBL in the SDR mode under the control of the controller 130. The boost voltage generator 900 may output the boost high voltage VBH and the boost low voltage VBL, and the voltage levels thereof may be changed by the controller 130 using a level shifter or an ADC.

[0121] The controller 130 receives an input image signal and a timing signal synchronized with the input image signal from the host system 300. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a period of one horizontal period (1H).

[0122] The controller 130 generates a timing control signal for controlling the operation timing of each of the data driver 110, the gate driver 120, and the boost voltage generator 900 based on the timing signals such as Vsync, Hsync, and DE received from the host system 300 to control the display panel driving circuit. The voltage level of the timing control signal output from the controller 130 may be shifted by the level shifter 150.

[0123] Figure 13 is a block diagram showing a display device according to another embodiment of the present disclosure. Figure 14 is a diagram showing Figure 13 a perspective view of the display panel and the backlight unit shown.

[0124] Referring to Figure 13 and Figure 14 , the display device includes a display panel 400, a display panel driving circuit for writing pixel data to the display pixels 401 of the display panel 400, a backlight unit 200 for irradiating the display panel 400 with light emitted from the light emitting elements EL of the local dimming pixels 201, and a backlight driving circuit for writing local dimming data to the local dimming pixels 201.

[0125] The display panel 400 may be a transmissive display panel including a liquid crystal layer without light emitting elements. On the lower transparent substrate of the display panel 400, data lines 402 and gate lines 403 intersect, and display pixels 401 connected to the data lines 402 and the gate lines 403 are provided. A black matrix, a color filter, and a common electrode to which a common voltage is applied may be formed on the upper transparent substrate of the display panel 400. The common electrode may be formed on the upper transparent substrate in a vertical field driving mode such as a TN (twisted nematic) mode and a VA (vertical alignment) mode, and may be provided on the lower transparent substrate together with the pixel electrodes of the display pixels 401 in a horizontal field driving mode such as an IPS (in-plane switching) mode and an FFS (fringe field switching) mode.

[0126] Polarizers having orthogonal optical axes are attached to each of the upper and lower transparent substrates of the display panel 400. In each of the upper and lower transparent substrates of the display panel 400, an alignment film for setting the pretilt angle of the liquid crystal is formed on the inner surface in contact with the liquid crystal layer.

[0127] Each of the display pixels 401 can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color realization. Each of the display pixels 401 can also include a white sub-pixel. Each of the sub-pixels can include a switching element, such as a TFT, which transfers the data voltage applied to the data line 402 to the pixel electrode in response to a gate signal from the gate line 403. Each sub-pixel uses liquid crystal molecules driven by the electric field between the pixel electrode and the common electrode to adjust the light transmittance of the light passing through the polarizer.

[0128] The display array AA includes a plurality of display pixel lines L1 to Ln. Each of the display pixel lines L1 to Ln includes a row of display pixels 401 arranged in the display area AA of the display panel 400 in the gate line direction (X-axis direction).

[0129] The power supply 440 receives the input voltage provided from the host system 600 and outputs the voltages required to drive the display pixels 401 of the display panel 400, the display panel driving circuit, the local dimming pixels 201, and the backlight driving circuit.

[0130] The display panel driving circuit writes the pixel data of the input image into the display pixels 401 of the display panel 400 under the control of the first controller 430. The display panel driving circuit includes a data driver 410 and a gate driver 420. The display panel driving circuit may also include a touch sensor driver for driving the touch sensor.

[0131] The data driver 410 receives the pixel data of the input image provided as a digital signal from the first controller 430 and outputs a data voltage Vdata to be supplied to the data line 402. The gate driver 420 outputs pulses of the gate signal to be sequentially supplied to the gate line 403 of the display panel 400.

[0132] The first controller 430 receives an input image signal and a timing signal synchronized with the input image signal from the host system 600. The first controller 430 generates a data timing control signal for controlling the operation timing of the data driver 410 and a gate timing control signal for controlling the operation timing of the gate driver 420 to control the display panel driving circuit. The voltage level of the timing control signal output from the first controller 430 can be shifted by the level shifter 450.

[0133] The first controller 430 or the second controller 500 generates local dimming data based on the pixel data of the input image. The first controller 430 or the second controller 500 can calculate the local dimming data for each block of the display panel 400 by reducing the pixel data of the input image. The display area AA of the display panel 400 can be virtually divided into a plurality of blocks, and the backlight brightness of these blocks is independently controlled by local dimming. Each of the blocks of the display panel 400 includes a plurality of pixels. The local dimming data can be calculated as, but not limited to, the average value of the pixel data in units of the blocks of the reduced input image. The first controller 430 can send the pixel data or the local dimming data of the input image to the second controller 500.

[0134] The backlight unit 200 includes a plurality of data lines 202, a plurality of gate lines 203 intersecting the data lines 202, and a plurality of local dimming pixels 201. The backlight unit 200 may further include a power line commonly connected to the local dimming pixels 201.

[0135] Each of the local dimming pixels 201 includes a local dimming pixel circuit for driving the corresponding light-emitting element EL. The local dimming pixel circuit is connected to the data line 202, the plurality of gate lines 203, and the power line. The gate line 203 may include a first gate line to which a first gate signal SCAN is applied, a second gate line to which a second gate signal SENSE is applied, a third gate line to which a third gate signal INIT is applied, a fourth gate line to which a selection signal S1 is applied, and a fifth gate line to which a second selection signal S3 is applied. According to the implementation manner of the above pixel circuit, some of the gate signals and selection signals may be omitted. The local dimming pixel circuit can be implemented as any one of the pixel circuits shown in FIGS. 1 to Figure 9 any of the pixel circuits shown above.

[0136] As Figure 14 shown, the light-emitting element EL of the backlight unit 200 may be disposed below the display panel 400. The backlight unit 200 may further include the light-emitting element EL of the local dimming pixel 201 and one or more optical sheets 250 disposed between the display panels 400. The optical sheet 250 uniformly irradiates the light from the light-emitting element EL in a direction perpendicular to the surface of the display panel 400.

[0137] The backlight driving circuit writes the local dimming data into the local dimming pixel 201 under the control of the second controller 500. The display panel driving circuit includes a data driver 210, a gate driver 220, and a boost voltage generator 910.

[0138] The data driver 210 can convert the local dimming data received from the second controller 500 into a data voltage and supply it to the data line 202 connected to the local dimming pixel 201.

[0139] The gate driver 220 may sequentially supply pulses of gate signals to the gate lines 203. The gate driver 220 may include a first gate driver that supplies a first gate signal SCAN to a first gate line, a second gate driver that supplies a second gate signal SENSE to a second gate line, a third gate driver that supplies a third gate signal INIT to a third gate line, a fourth gate driver that supplies a selection signal S1 to a fourth gate line, and a fifth gate driver that supplies a second selection signal S3 to a fifth gate line. According to the above-described embodiment of the pixel circuit, some of the gate drivers may be omitted.

[0140] The boost voltage generator 910 outputs a boosted high voltage VBH in the HDR mode and a boosted low voltage VBL in the SDR mode under the control of the second controller 500. The boost voltage generator 910 may output the boosted high voltage VBH and the boosted low voltage VBL, and the voltage levels thereof may be changed by the second controller 500 using a level shifter or an ADC.

[0141] The second controller 500 may receive local dimming data output from the first controller 430. In other embodiments, the second controller 500 may receive pixel data of an input image from the first controller 430 and generate local dimming data as a result of analyzing the pixel data of the input image. The second controller 500 may send the local dimming data to the data driver 210 and control the operation timings of the data driver 210, the gate driver 220, and the boost voltage generator 910.

[0142] Figure 15 is a diagram showing an example of the dynamic range of data voltages output from a data driver.

[0143] Referring to Figure 15 , by means of a boost circuit embedded in the pixel circuit, the dynamic range of the data voltage Vdata output from the data drivers 110, 210, and 410 may include the same SDR / HDR driving voltage range and compensation margin voltage range in both the HDR mode and the SDR mode. The compensation margin voltage is the range of compensation voltages added to the data voltage to compensate for the threshold voltage of the driving element DT sensed by the pixel when the threshold voltage changes. In the dynamic range of the data voltage Vdata output from the data drivers 110, 210, and 410, since the dynamic range of the HDR mode is the same as that of the SDR mode, a sufficient compensation margin voltage may be ensured to extend the lifespan of the display device without degrading the image quality.

[0144] According to one or more embodiments of the present disclosure, the display device can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, sliding devices, variable devices, electronic notepads, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation, vehicle navigation, vehicle display devices, vehicle devices, theater devices, theater display devices, TVs, wallpaper devices, sign devices, game devices, laptops, monitors, cameras, video cameras, and home appliances, etc. Additionally, the display device according to one or more embodiments of the present disclosure can be applied to an organic light-emitting lighting device or an inorganic light-emitting lighting device.

[0145] The objects to be achieved by the present disclosure, the means for achieving the objects, and the effects of the present disclosure described above do not specify the essential features of the claims, and thus, the scope of the claims is not limited to the disclosure of the present disclosure.

[0146] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and do not limit the present disclosure.

Claims

1. A pixel circuit, comprising: Light emitting element; a driving element connected to the light emitting element and configured to adjust a current flowing to the light emitting element according to a gate-source voltage of the driving element, the driving element comprising a first electrode, a gate electrode, and a second electrode; as well as a boost circuit electrically connected to the drive element, the boost circuit being configured to supply current to the first electrode of the drive element in each of a first mode and a second mode, A first peak value of the current supplied to the first electrode of the driving element in the second mode is greater than a second peak value of the current supplied to the first electrode of the driving element in the first mode.

2. The pixel circuit according to claim 1, wherein: The light emitting element includes an anode electrode electrically connected to the second electrode of the driving element and a cathode electrode receiving a cathode voltage, and Wherein, a first input voltage greater than the cathode voltage is applied to the boost circuit through a first node.

3. The pixel circuit according to claim 1, wherein: The light emitting element includes an anode electrode electrically connected to the boosting circuit and receiving a first input voltage through a first node.

4. The pixel circuit according to claim 1, wherein: The boost circuit comprises: a first switching element including a first electrode connected to the first node, a gate electrode connected to the third node, and a second electrode connected to the first electrode of the driving element; a second switching element connected to a second node to which a second input voltage is applied and the third node, the second switching element being configured to supply the second input voltage to the third node in response to being turned on in response to a selection signal; and a capacitor connected to a node to which a boost signal is applied and connected to a gate electrode of the first switching element and the second switching element at the third node, wherein a first input voltage is applied to the first node, or a cathode electrode of the light emitting element is connected to the first node, and the boost signal is a boost low voltage during the first mode, and is a boost high voltage greater than the boost low voltage during the second mode.

5. The pixel circuit according to claim 4, further comprising: a boost voltage generator configured to output the boost high voltage and the boost low voltage; a reference voltage line connected to the capacitor; a reference voltage switching element configured to supply a reference voltage to the reference voltage line; as well as A sampling switch element is configured to selectively connect the reference voltage line to one of an input node of an analog-to-digital converter, a floating node, and an output node of the boost voltage generator.

6. The pixel circuit according to claim 1, wherein: The boost circuit comprises: a first switching element including a first electrode connected to the first node, a gate electrode connected to the third node, and a second electrode connected to the first electrode of the driving element; a second switching element connected to the second node to which the second input voltage is applied and a fourth node, the second switching element being configured to supply the second input voltage to the fourth node in response to being turned on in response to the first selection signal; a first capacitor connected to a node to which the first boost signal is applied and connected to the second switching element at the fourth node; a third switching element connected to the gate electrode of the first switching element at the third node and to the second switching element at the fourth node, the third switching element being configured to apply a voltage of the fourth node to the third node in response to being turned on in response to a second selection signal; and a second capacitor connected to a node to which a second boost signal is applied and connected to a gate electrode of the first switching element and the third switching element at the third node, wherein a first input voltage is applied to the first node, or a cathode electrode of the light emitting element is connected to the first node, and the second boost signal is a boost low voltage during the first mode, and is a boost high voltage greater than the boost low voltage during the second mode.

7. The pixel circuit according to claim 6, wherein: The second mode includes a primary boost mode and a secondary boost mode, Wherein, during the primary boost mode, the first boost signal is a boost low voltage, and during the secondary boost mode, the first boost signal is a boost high voltage.

8. The pixel circuit according to claim 1, further comprising: a first pixel switching element connected to a data line to which a data voltage is applied and connected to a gate electrode of the driving element at a second pixel node, the first pixel switching element being configured to apply the data voltage to the second pixel node in response to being turned on in response to a first gate signal; a second pixel switching element connected to a node to which a reference voltage is applied and connected to the second electrode of the driving element at a third pixel node, the second pixel switching element being configured to apply the reference voltage to the third pixel node in response to being turned on in response to a second gate signal; as well as a storage capacitor connected to the second pixel node and the third pixel node, The first electrode of the driving element is connected to a first pixel node, and the first pixel node is connected to the boosting circuit.

9. The pixel circuit according to claim 8, further comprising: A third pixel switching element, the third pixel switching element is connected to a node to which an initialization voltage is applied, and is connected to the gate electrode of the driving element and the first pixel switching element at the second pixel node, the third pixel switching element being configured to apply the initialization voltage to the second pixel node in response to being turned on in response to a third gate signal.

10. A display device, comprising: A plurality of pixels, each pixel of the plurality of pixels comprising: Light emitting element; a driving element electrically connected to the light emitting element and configured to control a current flowing to the light emitting element, the driving element comprising a first electrode, a gate electrode, and a second electrode; and A boost circuit electrically connected to the first electrode of the driving element, the boost circuit comprising: a first switching element including a first electrode connected to a first node to which a first input voltage is applied, a gate electrode connected to a third node, and a second electrode connected to the first electrode of the driving element; a second switching element electrically connected to a second node to which a second input voltage is applied and configured to be electrically connected to the a first switching element configured to supply the second input voltage to the third node in response to a first selection signal; and a first capacitor connected to a node to which a first boost signal is applied and electrically connected to a gate electrode of the first switching element at the third node; During a first mode of the display device, the first boost signal is a first boost voltage, and the magnitude of the current supplied to the first electrode of the driving element is a first value, and during a second mode of the display device, the first boost signal is a second boost voltage greater than the first boost voltage, and the magnitude of the current supplied to the first electrode of the driving element is a second value greater than the first value.

11. The display device according to claim 10, further comprising: a display panel, the display panel comprising a plurality of data lines to which data voltages are applied, a plurality of gate lines to which gate signals and selection signals are applied, a plurality of power lines, and the plurality of pixels; a data driver configured to receive pixel data from an input image and output a data voltage; a gate driver configured to output the gate signal and the selection signal; as well as A boost voltage generator is configured to output the first boost signal.

12. The display device according to claim 10, further comprising: a display panel into which pixel data of an input image is written; as well as a backlight unit configured to irradiate light to the display panel, the backlight unit comprising: a plurality of data lines to which data voltages are applied; a plurality of gate lines to which gate signals and selection signals are applied; Multiple power lines; and The plurality of pixels.

Images