Display panel and display device including same

Abstract

An embodiment discloses a display panel and a display device including the same, the display panel including a plurality of pixels, and gate lines and data lines connected to the plurality of pixels, each of the plurality of pixels includes 1-1 and 1-2 sub-pixels of a first color, 2-1 and 2-2 sub-pixels of a second color, and 3-1 and 3-2 sub-pixels of a third color, where each of the 2-1 and 2-2 sub-pixels includes a light emitting element and a compensation circuit, and each of the 2-1 and 2-2 sub-pixels includes a light emitting element and a compensation circuit. And the compensation circuit of the 2-1 sub-pixel and the compensation circuit of the 2-2 sub-pixel are connected to one data line.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0192978, filed on December 27, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] This specification relates to a display panel and a display device including the display panel. Background art

[0004] An organic light - emitting display device reproduces an image by causing an organic light - emitting diode (OLED) provided in each pixel to emit light in response to an input image signal. The organic light - emitting display device may have a fast response time, high luminous efficiency, high brightness, and a wide viewing angle, and represent black gradation as complete black, and thus has excellent contrast and color gamut. Such an organic light - emitting display device does not require a backlight unit.

[0005] In recent years, a micro - display device using a light - emitting diode (LED) as a light - emitting element in a pixel, which is an inorganic light - emitting element and is manufactured in a micro - size of about 100 μm or less, has received increasing attention as a next - generation display device. Since the LED is made of an inorganic material, it does not require a separate encapsulation layer to protect the organic material from moisture, and has excellent reliability and a longer lifespan than the OLED. In addition, the LED can be turned on and off quickly, and has high luminous efficiency and impact resistance.

[0006] A problem with these micro - display devices is that two LEDs are arranged in parallel in a single sub - pixel, and thus when one of the LEDs experiences a short - circuit failure and dims, the other LED also dims. Summary of the invention

[0007] This specification aims to provide a display panel that causes another light - emitting element to emit light even when a light - emitting element in one of a plurality of sub - pixels dims, and a display device including the display panel.

[0008] This specification also aims to provide a display panel in which a light - emitting element can be repaired and a display device including the display panel.

[0009] The object of this specification is not limited to the above - mentioned objects, and other objects not described above will be clearly understood by those skilled in the art from the following description.

[0010] According to one aspect of the present invention, a display panel is provided. The display panel includes a plurality of pixels, and gate lines and data lines connected to the plurality of pixels. Each of the plurality of pixels includes a 1-1 sub-pixel and a 1-2 sub-pixel of a first color, a 2-1 sub-pixel and a 2-2 sub-pixel of a second color, and a 3-1 sub-pixel and a 3-2 sub-pixel of a third color. Each of the 2-1 sub-pixel and the 2-2 sub-pixel includes a light-emitting element and a compensation circuit, and the compensation circuits of the 2-1 sub-pixel and the 2-2 sub-pixel are connected to one data line. Description of the Drawings

[0011] The above and other objects, features, and advantages of the present invention will become more apparent to those of ordinary skill in the art by referring to the following detailed description of its exemplary embodiments with reference to the accompanying drawings, in which:

[0012] Figure 1 is a block diagram schematically showing the configuration of a display device according to an embodiment of the present specification;

[0013] Figure 2 is a partial cross-sectional view showing pad electrodes and side lines provided on the outer periphery of a display panel according to an embodiment of the present specification;

[0014] Figure 3 is a perspective view showing a tiled display device according to an embodiment of the present specification;

[0015] Figure 4 is a plan view showing the planar structure of a display panel according to an embodiment of the present specification;

[0016] Figure 5 is a cross-sectional view showing the cross-sectional structure of a display panel according to an embodiment of the present specification;

[0017] Figure 6 is a diagram showing a pixel structure according to an embodiment of the present specification;

[0018] Figure 7 is a diagram showing a red sub-pixel according to an embodiment of the present specification;

[0019] Figure 8 is a diagram showing a green sub-pixel according to an embodiment of the present specification;

[0020] Figure 9 is a diagram showing a blue sub-pixel according to an embodiment of the present specification;

[0021] Figure 10 is a diagram showing the cathodes of a red sub-pixel, a green sub-pixel, and a blue sub-pixel;

[0022] Figure 11 is a circuit diagram schematically showing a pixel circuit according to an embodiment of the present specification;

[0023] Figure 12 is a circuit diagram showing a pixel circuit according to another embodiment of the present specification;

[0024] Figure 13 is a waveform diagram of a pixel circuit according to another embodiment of the present specification;

[0025] Figure 14 is a diagram showing a pixel in which sub-pixels are connected in parallel;

[0026] Figure 15 shows Figure 14 sub-pixels;

[0027] Figure 16 and Figure 17 is a diagram showing a repair method of a display panel according to an embodiment of the present specification. Detailed Description of the Invention

[0028] Advantages and features of the invention disclosed in the present specification and methods for realizing the advantages and features will be more clearly understood from the embodiments described below with reference to the accompanying drawings. The present invention is not limited to the following embodiments but can be implemented in various different forms. The embodiments are provided only to complete the present invention and fully provide the scope of the present invention to those of ordinary skill in the art to which the present invention pertains, and the present invention will be defined by the appended claims.

[0029] When describing the present invention, when it is determined that a detailed description of well-known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

[0030] Terms such as "including", "having", and "consisting of" used herein are intended to allow the addition of other elements, unless the term is used together with the term "only". When a component is expressed in the singular form, it can be interpreted as the plural form unless otherwise clearly stated.

[0031] When using terms such as "on", "above", "below", "adjacent to", "connected or coupled", "crossed or intersected" to describe the positional or interconnection relationship between two components, one or more other components may be interposed between the two components, unless the term is used together with the term "immediately" or "directly".

[0032] When using terms such as "after", "subsequently", "next", "before" to describe the chronological relationship, discontinuous cases may be included, unless the term "immediately" or "directly" is used.

[0033] Although ordinal numbers such as first, second, etc. are used to distinguish components, the functions or structures of these components are not limited by the ordinal numbers before the components or the names of the components.

[0034] The following embodiments can be partially or wholly combined or combined with each other, and can be interoperable and executed in various ways technically. Each embodiment can be operable independently of each other and can be implemented together in a related relationship.

[0035] In the embodiments of this specification, the pixel and the display panel driving circuit include transistors. A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. The carriers in the transistor start to flow from the source. The drain is an electrode through which the carriers discharge from the transistor to the outside. In the transistor, the carriers flow from the source to the drain. In the case of an n-channel transistor, the carriers are electrons, so the source voltage is lower than the drain voltage to make the electrons flow from the source to the drain. In an n-channel transistor, the current flows from the drain to the source. In the case of a p-channel transistor, the carriers are holes, so the source voltage is higher than the drain voltage to make the holes flow from the source to the drain. In a p-channel transistor, since the holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the positions of the source and the drain of the transistor are not fixed. For example, the source and the drain are interchangeable according to the applied voltage. Therefore, this specification is not limited by the source and the drain of the transistor. In the following description, the source and the drain of the transistor will be referred to as the first electrode and the second electrode.

[0036] The gate signal can swing between the gate-on voltage and the gate-off voltage. The transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage can be the gate high voltage VGH, and the gate-off voltage can be the gate low voltage VGL. In the case of a p-channel transistor, the gate-on voltage can be the gate low voltage VGL, and the gate-off voltage can be the gate high voltage VGH.

[0037] The term "line" mentioned in the embodiments of this specification can be interpreted as a wiring to which a signal or a voltage is applied.

[0038] The terms (including technical terms and scientific terms) used in the embodiments of this specification can be interpreted with the meanings commonly understood by those skilled in the art, unless otherwise specifically defined and described, and the commonly used terms, such as the terms defined in a dictionary, can be understood by considering their context meanings in the related art.

[0039] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0040] Refer to Figure 1, the display device 100 includes: a display panel PN, the display panel PN includes a display area AA provided with a plurality of pixels; and a display panel driving circuit configured to drive the pixels.

[0041] The display panel PN may be a panel having a rectangular structure with a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction, but the present specification is not limited thereto. Each of the pixels includes a plurality of sub-pixels SP of different colors. The display area AA on which an input image is displayed in the display panel PN may be a screen viewed from the front of the display panel PN.

[0042] The display panel driving circuit includes a data driver DD, a gate driver GD, and a timing controller TC configured to control the gate driver GD and the data driver DD.

[0043] An input image is displayed on the sub-pixels SP provided in the display area AA of the display panel PN. Each of the sub-pixels SP includes a light-emitting element and a pixel circuit configured to drive the light-emitting element. The light-emitting element may be a light-emitting diode (LED) or a micro-LED.

[0044] On the display panel PN, a plurality of gate lines SL and a plurality of data lines DL are provided to cross each other. Each of the sub-pixels SP is connected to the gate line SL and the data line DL. The Figure 1 power supply lines omitted therefrom may be connected to each of the sub-pixels SP. In the display panel PN, a non-display area NA may be provided outside the display area AA.

[0045] The gate driver GD provides a gate signal to the gate line SL in response to a gate control signal provided from the timing controller TC. The gate driver GD may be provided at least in the non-display area NA of the display panel PN as Figure 1 shown, or may be provided in the display area AA.

[0046] The data driver DD converts the image data received from the timing controller TC into a gamma compensation voltage in response to a data control signal provided from the timing controller TC to output a data voltage. The data voltage output from the data driver DD is provided to the data line DL.

[0047] The timing controller TC arranges (aligns) the image data input from the outside and supplies the image data to the data driver DD. The timing controller TC can generate a gate control signal and a data control signal based on timing signals synchronized with the input image signal, such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal. The timing controller TC supplies the gate control signal and the data control signal to the gate driver GD and the data driver DD, respectively, to control the operating timings of the gate driver GD and the data driver DD.

[0048] Link lines and pad electrodes for transmitting signals to the sub-pixels SP in the display area AA can be provided in the non-display area NA. One or more of the gate driver IC in which the circuit of the gate driver GD is integrated and the data driver IC in which the circuit of the data driver DD is integrated can be provided in the non-display area NA. The non-display area NA can include the back surface of the display panel PN, that is, the back surface where the sub-pixels SP do not exist. The non-display area NA can be minimized to the extent that the non-display area NA is not visible when an image is displayed on the display panel PN.

[0049] The display panel driving circuit can be connected to the display panel PN in various ways to drive the pixels. For example, the gate driver GD can be provided in the non-display area NA by the gate-in-panel (GIP) method or between a plurality of sub-pixels SP in the display area AA by the gate-in-area (GIA) method. The data driver DD and the timing controller TC can be formed on separate flexible films and printed circuit boards (PCBs), and can be electrically connected to the display panel PN by bonding the terminals of the flexible film to the pad electrodes formed in the non-display area NA of the display panel PN. The flexible film bonded to the display panel PN can be connected to a PCB on which circuit elements are mounted and lines are formed.

[0050] Side lines for connecting the signal lines on the front surface of the display panel PN to the pad electrodes on the back surface of the display panel PN can be formed on the outer peripheral side surface of the display panel PN. The method of electrically connecting the front and back surfaces of the display panel PN by the side lines can minimize the non-display area NA observed from the front surface of the display panel PN. In Figure 2 ,"SRL" represents the side line. When the gate driver GD, the data driver DD, and the timing controller TC are electrically connected to the display panel PN by the above method, a substantially borderless screen can be realized on the display panel PN.

[0051] Refer to Figure 2, a plurality of pad electrodes for transmitting various signals to the sub-pixels SP are provided in the non-display area NA of the display panel PN. For example, a first pad electrode PAD1 configured to transmit signals to the sub-pixels SP can be provided in the non-display area NA provided on the front surface of the display panel PN. A second pad electrode PAD2 electrically connected to circuit elements (such as a flexible film and a PCB) is provided in the non-display area NA provided on the back surface of the display panel PN. The non-display area NA provided on the outer periphery of the front surface of the display panel PN on which an image is displayed can be minimized in size by only providing a pad area in which the first pad electrode PAD1 is arranged.

[0052] Various signal lines connected to the sub-pixels SP, such as gate lines SL or data lines DL, can extend to the non-display area NA to be electrically connected to the first pad electrode PAD1.

[0053] The display panel PN may include side lines SRL provided on the side surface of the outer periphery of the display panel PN. The side lines SRL can electrically connect the first pad electrode PAD1 provided on the outer periphery of the front surface of the display panel PN across the side surface of the display panel PN to the second pad electrode PAD2 provided on the outer periphery of the back surface of the display panel PN. Signals output from the circuit elements provided on the back surface of the display panel PN can be transmitted to the sub-pixels SP and the gate driver GD in the display area AA via the second pad electrode PAD2, the side lines SRL, and the first pad electrode PAD1. Therefore, the area of the non-display area NA at the front surface of the display panel PN can be minimized by forming a signal transmission path across the outer peripheries of the front surface, side surface, and back surface of the display panel PN.

[0054] A plurality of display modules can be combined on one plane to be implemented as a large-screen tiled display device. Each of the display modules can be implemented as a single display device, and the combination of the plurality of display modules can be implemented as a large-screen tiled display device. Each of the display modules includes a display panel PN, a driving circuit of the display panel PN, and circuit elements and a module cover member combined with the back surface of the display panel PN.

[0055] Refer to Figure 3 , the large-screen tiled display device TD includes a plurality of display modules provided on the XY plane. Each of the display modules includes a display panel PN that reproduces an input image. When the non-display area NA is minimized at the outer periphery of the front surface of each display panel PN, a large-screen image can be reproduced between adjacent display panels PN without seeing a seam.

[0056] The display panel PN can be assembled on a plane such that the separation distance D1 between the outermost pixels PX of one display panel PN and the outermost pixels PX of another display panel PN adjacent to the one display panel PN is substantially equal to the separation distance D2 between adjacent pixels PX in the display area AA of the display panel PN. Accordingly, the separation distances D1 and D2 between adjacent pixels PX are equal to each other throughout the large-screen display area of the tiled display device TD, thereby ensuring that the seam area is not visually recognized.

[0057] In the tiled display device TD, a plurality of display modules can share one timing controller TC. A host system can be connected to the plurality of timing controllers TC to transmit video signals reproduced on all the display panels PN of the large-screen tiled display device TD to the timing controller TC and synchronize the timing controller TC.

[0058] Figure 4 is a plan view schematically showing a planar structure of a display panel according to an embodiment of the present specification.

[0059] Referring to Figure 4 , the display panel PN includes a substrate SUBS on which a pixel array and a circuit of a gate driver GD are provided. The display panel PN can be a panel having a rectangular structure with a length in the row direction (X-axis direction), a width in the column direction (Y-axis direction), and a thickness in the thickness direction (Z-axis direction), but the present specification is not limited thereto.

[0060] The substrate SUBS can be an insulating substrate that supports components provided on the upper part of the display device. The substrate SUBS can have a structure in which a plurality of substrates are stacked. The substrate SUBS can be made of glass, a polymer resin, or a plastic substrate.

[0061] On one surface (or the front surface) of the substrate SUBS, the display area AA can include a plurality of pixel areas UPA, a plurality of gate drive areas GA, and a plurality of pad areas PA1 and PA2. One or more pixels PX can be provided in each of the pixel areas UPA. The pixel areas UPA can be arranged along a plurality of row lines and a plurality of column lines. Each of the pixels PX includes a plurality of sub-pixels SP of different colors. Each of the sub-pixels SP includes a light-emitting element and a pixel circuit and can thus emit light independently. The sub-pixels SP can include red sub-pixels, blue sub-pixels, green sub-pixels, etc., but the present specification is not limited thereto.

[0062] Multiple gate driving regions GA include the circuits of the gate driver GD. The gate driving regions GA may be formed between multiple pixel regions UPA in the row direction and / or the column direction. The gate driver GD formed in the gate driving region GA may supply gate signals to multiple gate lines SL. The gate driving regions GA may be disposed between adjacent pixel regions UPD in the row direction (X-axis direction).

[0063] The first pad region PA1 includes multiple first pad electrodes PAD1 disposed on the outer periphery of the front surface on one side (or the upper side) of the display panel PN. The first pad electrodes PAD1 may transmit various signals to various lines extending in the column direction in the display area AA. The first pad electrodes PAD1 include: data pads DP, where the data pads DP are connected to the data lines DL to transmit the data voltage output from the data driver DD to the data lines DL; and gate pads GP, where the gate pads GP are connected to the gate driver GD to transmit a clock signal, a start signal, a gate low voltage, a gate high voltage, etc. to the gate driver GD to drive the gate driver GD. The clock signal, start signal, gate low voltage, gate high voltage, etc. for driving the gate driver GD may be generated from the timing controller TC and applied to the gate pads GP via a level shifter and a PCB. The first pad electrodes PAD1 may include multiple power supply lines to which a direct current (DC) voltage (or a constant voltage) is applied.

[0064] The substrate SUBS of the display panel PN includes gate driving lines connected to the gate pads GP in the column direction and multiple gate driving lines GVL extending in the row direction. The gate driving lines in the column direction may be connected to the gate driving lines GVL in the row direction via contact holes passing through the insulating film. The gate driving lines GVL transmit signals required for driving the gate driver GD distributed in the gate driving region GA to the circuits of the gate driver GD, such as a clock signal, a start signal, a gate high voltage, a gate low voltage, etc.

[0065] The second pad region PA2 includes multiple second pad electrodes PAD2 disposed on the outer periphery of the front surface on the other side (or the lower side) of the display panel PN. The second pad region PA2 may include multiple low-potential power supply pads VP2.

[0066] The DC voltage applied to the power supply lines may be output from a power supply circuit (omitted in the figure) and applied to the power supply pads VP1 and VP2 connected to the power supply lines via a PCB. The power supply circuit may be a DC-DC converter disposed on a PCB or control boards CTB1 and CTB2 provided on the back surface of the display panel PN and converting the DC input voltage output from the main power supply into a DC voltage suitable for driving the display panel PN.

[0067] Power pads VP1 and VP2 connected to a power supply line may include: a plurality of high-potential power pads VP1 disposed on a first pad region PA1 to transmit a high-potential power supply voltage to a high-potential power supply line VL1; and a plurality of low-potential power pads VP2 disposed on a second pad region PA2 to transmit a low-potential power supply voltage to a low-potential power supply line VL2.

[0068] Data pads DP connected one-to-one to data lines DL may each have a relatively narrow width, and power pads VP1 and VP2 and gate pads GP may each have a relatively wide width. Each of the low-potential power pads VP2 may have a greater width than each of the high-potential power pads VP1.

[0069] To minimize the outermost non-display region NA of the display panel PN, a pixel array, lines, and pads are formed on the front surface of the substrate of the display panel PN, and then, the outermost portion except for the scribing line SCL indicated by a dashed line is removed, whereby a substrate SUBS having a minimum non-display region NA can be prepared. After the scribing process, the rough edges on the outer periphery of the substrate SUBS may be polished or laser-trimmed. Short pad electrodes PAD1 and PAD2 remain on the outer periphery of the front surface of the substrate SUBS, and their sizes are correspondingly reduced.

[0070] Data lines DL may extend in a column direction (Y direction) on the substrate SUBS and overlap with a pixel region UPA. The data lines DL supply data voltages to pixel circuits of each of the sub-pixels SP. Gate lines SL may extend in a row direction (X direction) on the substrate SUBS of the display panel PN and overlap with the pixel region UPA and a gate driving region GA. The gate lines SL may span the pixel region UPA and the gate driving region GA and supply gate signals output from a gate driver GD to pixel circuits of each of the sub-pixels SP.

[0071] The high-potential power supply line VL1 extends in the column direction (Y direction), and one or more of them are connected to an auxiliary high-potential power supply line AVL1 extending in the row direction (X direction) in a mesh structure. The auxiliary high-potential power supply line AVL1 is connected to sub-pixels SP disposed in the row direction (X direction). Accordingly, the high-potential power supply voltage applied to the high-potential power supply line VL1 can be transmitted to the sub-pixels SP via the auxiliary high-potential power supply line AVL1.

[0072] The low-potential power line VL2 extends in the column direction (Y direction), and one or more of them are connected to the auxiliary low-potential power line AVL2 extending in the row direction (X direction) in a mesh structure. The auxiliary low-potential power line AVL2 is connected to the sub-pixels SP provided in the row direction (X direction). Therefore, the sub-pixels SP are connected to the auxiliary low-potential power line AVL2 to which the low-potential power supply voltage is applied.

[0073] Due to the mesh structure of the power line, the resistance of the power line may be reduced, which can reduce the voltage drop of the high-potential power supply voltage and the variation of the power supply voltage within the display area AA.

[0074] The substrate SUBS of the display panel PN may include one or more alignment keys AK1 and AK2 provided between the pixel regions UPA. The alignment keys AK1 and AK2 can be used for alignment during the manufacturing process of the display panel PN. The first alignment key AK1 can be provided in the gate driving region GA. The first alignment key AK1 can be used to check the alignment position of each light-emitting element. The first alignment key AK1 can be formed in a cross pattern, but this specification is not limited thereto. The second alignment key AK2 can overlap with the high-potential power line HL. The high-potential power line HL can be separated from the second alignment key AK2 by including a hole formed at the overlapping position with the second alignment key AK2. The second alignment key AK2 can be used to align the display panel PN to a donor substrate. The donor substrate is an intermediate medium for mounting light-emitting elements on the substrate SUBS of the display panel PN. A plurality of light-emitting elements manufactured on a semiconductor wafer can be attached to and transferred to the donor substrate, and the light-emitting elements attached to the donor substrate can be transferred to the substrate SUBS. The second alignment key AK2 can be formed in a circular or annular pattern, but this specification is not limited thereto.

[0075] Figure 5 is a cross-sectional view showing the cross-sectional structure of a display panel according to an embodiment of the present invention.

[0076] Referring to Figure 5 , a pixel circuit for driving the light-emitting element ED is provided in each of the plurality of sub-pixels SP on the first substrate SUBS1. The pixel circuit may include a plurality of thin-film transistors and one or more capacitors. For convenience of description, the driving element DT, the first capacitor C1, and the second capacitor C2 used in the pixel circuit are described, but the display panel PN may further include other circuit elements.

[0077] The pattern of the first metal layer can be disposed on the first substrate SUBS1. The pattern of the first metal layer can include a light-shielding layer BSM. The light-shielding layer BSM can minimize leakage current by blocking light incident on the active layer ACT of the driving element DT. The light-shielding layer BSM can be formed of an opaque conductive material, for example, metals such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), alloys of these metals, or a multi-layer metal layer.

[0078] The buffer layer BUF can be disposed on the light-shielding layer BSM. The buffer layer BUF can block the penetration of moisture or impurities through the first substrate 11. The buffer layer BUF can be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer insulating layer.

[0079] The driving element DT including the active layer ACT, the gate GE, the source SE, and the drain DE can be disposed on the buffer layer BUF.

[0080] The active layer ACT can be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but the present invention is not limited thereto. The gate insulating layer GI electrically insulates the active layer ACT from the gate GE of the driving element DT. The gate insulating layer GI can be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer insulating layer.

[0081] The pattern of the second metal layer can be disposed on the gate insulating layer GI. The pattern of the second metal layer can include the gate GE of the driving element DT. The second metal layer can be formed of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or a multi-layer metal layer.

[0082] The first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 are disposed on the gate GE. In the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2, contact holes are formed for each of the source SE and the drain DE of the driving element DT to connect to the active layer ACT. Each of the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 can be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer insulating layer.

[0083] The pattern of the third metal layer can be disposed on the second interlayer insulating layer ILD2. The pattern of the third metal layer can include the source SE and the drain DE that overlap with the active layer ACT and are connected to the active layer ACT through the contact holes passing through the interlayer insulating layers ILD1 and ILD2. The source SE can be connected to the capacitors C1 and C2 and the first electrode E1 of the light-emitting element ED. The third metal layer can be formed of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or a multi-layer metal layer.

[0084] The first capacitor C1 includes a first capacitor electrode C1a and a second capacitor electrode C1b. The first capacitor electrode C1a may be formed as a pattern of a second metal layer provided on the gate insulating layer GI. The second capacitor electrode C1b is formed as a pattern of a fourth metal layer provided on the first interlayer insulating layer ILD1 and overlaps with the first capacitor electrode C1a, and the first interlayer insulating layer ILD1 is interposed between the second capacitor electrode C1b and the first capacitor electrode C1a. The second capacitor electrode C1b may be connected to the source SE of the driving element DT. The fourth metal layer may be formed of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or a multi-layer metal layer.

[0085] The second capacitor C2 includes a third capacitor electrode C2a that overlaps with the first capacitor electrode C1a, and a buffer layer BUF and a gate insulating layer GI are interposed between the first capacitor electrode C1a and the third capacitor electrode C2a. The third capacitor electrode C2a may be formed as a pattern of a first metal layer provided on the first substrate SUBS1.

[0086] The second capacitor C2 is electrically connected between the source SE of the driving element DT and the light-emitting element ED to increase the capacitance of the light-emitting element ED, which can increase the brightness when the light-emitting element ED emits light.

[0087] The first passivation layer PAS1 covers the pattern of the third metal layer and the second interlayer insulating layer ILD2 to thereby coat the pattern of the third metal layer. The first passivation layer PAS1 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer insulating layer.

[0088] The first planarization layer PLN1 is provided on the first passivation layer PAS1. The first planarization layer PLN1 covers the first passivation layer PAS1 to planarize the surface on which the light-emitting element is provided. The first planarization layer PLN1 may be a thick single-layer or multi-layer organic insulating layer made of benzocyclobutene or allyl organic material.

[0089] The pattern of the fifth metal layer may be disposed on the first planarization layer PLN1. The pattern of the fifth metal layer may include a reflective layer RF. The reflective layer RF reflects the light from the light-emitting element ED toward the front surface of the display panel PN to increase the light efficiency, and may be used as an electrode for connecting the light-emitting element ED to the pixel circuit or the power line. The reflective layer RF may be electrically connected to the source SE of the driving element DT and the first capacitor C1 through the contact hole CH1 passing through the first planarization layer PLN1 and the first passivation layer PAS1. In addition, the reflective layer RF may be electrically connected to the first electrode E1 of the light-emitting element ED through the anode AND, or may electrically connect the second electrode E2 of the light-emitting element ED to the high-potential power line HL. The fifth metal layer may be formed of silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), a transparent electrode material (e.g., indium tin oxide (ITO)), or a multi-layer metal layer.

[0090] The second passivation layer PAS2 covers the pattern of the fifth metal layer and the first planarization layer PLN1. The second passivation layer PAS2 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer insulating layer.

[0091] An adhesive layer AD may be disposed on the second passivation layer PAS2 to fix the light-emitting element ED. The adhesive layer AD may be formed of a photocurable resin that can be cured by light. The adhesive layer AD may be formed of an allyl-based material containing a photosensitizer, but the present invention is not limited thereto. The adhesive layer AD may be formed on the entire surface of the first substrate SUBS1 except for the pad regions PA1 and PA2 where the first pad electrodes PAD1 are to be provided.

[0092] The light-emitting element ED of each sub-pixel in the sub-pixel SP may be disposed on the adhesive layer AD. Each of the light-emitting elements ED emits light through the current from the driving element DT. The light-emitting element ED may include a red light-emitting element ED, a green light-emitting element ED, and a blue light-emitting element ED. The light-emitting element ED may be an LED or a micro-LED.

[0093] Each of the light-emitting elements ED includes a first semiconductor pattern SEM1, a light-emitting layer EM, a second semiconductor pattern SEM2, a first electrode E1, and a second electrode E2.

[0094] The first semiconductor pattern SEM1 is disposed on the adhesive layer AD, and the second semiconductor pattern SEM2 is disposed on the first semiconductor pattern SEM1. The first semiconductor pattern SEM1 and the second semiconductor pattern SEM2 may be formed as semiconductor patterns obtained by doping a semiconductor material with n-type impurities and p-type impurities. For example, each of the first semiconductor pattern SEM1 and the second semiconductor pattern SEM2 may be a layer formed by doping a material such as gallium nitride (GaN), aluminum indium phosphide (InAlP), gallium arsenide (GaAs), etc. with n-type impurities or p-type impurities. In addition, the p-type impurities may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurities may be silicon (Si), germanium (Ge), tin (Sn), etc., but the present invention is not limited thereto.

[0095] The light-emitting layer EM is disposed between the first semiconductor pattern SEM1 and the second semiconductor pattern SEM2. The light-emitting layer EM can emit light by receiving holes and electrons from the first semiconductor pattern SEM1 and the second semiconductor pattern SEM2. The light-emitting layer EM may be formed as a single layer or a multi-quantum well (MQW) structure, and may be formed of, for example, indium gallium nitride (InGaN), gallium nitride (GaN), etc.

[0096] The first electrode E1 is disposed on the first semiconductor pattern SEM1. The first electrode E1 electrically connects the driving element DT and the first semiconductor pattern SEM1. The first semiconductor pattern SEM1 may be formed of a semiconductor layer doped with n-type impurities. The first electrode E1 may be the anode of the light-emitting element ED disposed on the first semiconductor pattern SEM1 and electrically connected to the driving element DT and the capacitors C1 and C2 via the reflective layer RF. The first electrode E1 may be disposed on the upper surface of the first semiconductor layer SEM1. The first electrode E1 may be formed of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof.

[0097] The second electrode E2 is disposed on the second semiconductor pattern SEM2. The second electrode E2 electrically connects the high-potential power supply line HL and the second semiconductor layer SEM2. The second semiconductor layer SEM2 may be formed as a semiconductor layer doped with p-type impurities. The second electrode E2 may be the cathode CAT of the light-emitting element ED. The second electrode E2 may be formed of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof.

[0098] The light-emitting element ED may include a packaging layer ENS. The packaging layer ENS covers the semiconductor patterns SEM1 and SEM2 and the electrodes E1 and E2 to protect the light-emitting element ED. The packaging layer ENS and the third planarization layer PLN3 include contact holes exposing the first electrode E1 and the second electrode E2. The anode AND is connected to the reflective layer RF through the first contact hole passing through the packaging layer ENS and the third planarization layer PLN3. The cathode CAT is connected to the second electrode E2 through the second contact hole passing through the packaging layer ENS and the third planarization layer PLN3. On the other hand, a part of the side surface of the first semiconductor pattern SEM1 may be exposed because there is no packaging layer ENS thereon.

[0099] The second planarization layer PLN2 and the third planarization layer PLN3 may cover the adhesive layer AD and the light-emitting element ED. The second planarization layer PLN2 contacts the lower end of the side surface of the light-emitting element ED and fixes the light-emitting element ED. The third planarization layer PLN3 covers the light-emitting element ED on the second planarization layer PLN2. The third planarization layer PLN3 includes contact holes exposing the first electrode E1 and the second electrode E2 of the light-emitting element ED. The second planarization layer PLN2 and the third planarization layer PLN3 may be formed of a single layer or multiple layers of an organic insulating material (e.g., photoresist or allyl organic material).

[0100] The pattern of the sixth metal layer may be provided on the third planarization layer PLN3. The sixth metal layer may include the anode AND and the cathode CAT. The anode AND electrically connects the first electrode E1 of the light-emitting element ED to the reflective layer RF. The anode AND may be connected to the first electrode E1 of the light-emitting element ED through the contact hole passing through the insulating layers PLN3 and ENS, and may be connected to the reflective layer RF through the contact hole passing through the insulating layers PAS2, AD, PLN2, and PLN3.

[0101] The cathode CAT is connected to the second electrode E2 of the light-emitting element ED through the contact hole passing through the insulating layers PLN3 and ENS. The cathode CAT may be connected to the low-potential power supply line CL.

[0102] According to an embodiment, the light-emitting element ED is shown as having a horizontal structure with electrodes connected to the upper surfaces of the first semiconductor pattern SEM1 and the second semiconductor pattern SEM2, but the present invention is not necessarily limited thereto. As an example, the light-emitting element ED may have a vertical structure with the anode AND disposed below the first semiconductor pattern SEM1.

[0103] A bank pattern BB may be provided on the second planarization layer PLN2. The bank pattern BB may be spaced apart from the light-emitting element ED by a certain distance. The bank pattern BB may cover a portion of the anode AND that exists in the contact hole passing through the insulating layers PLN2 and PLN3. The bank pattern BB may prevent optical crosstalk between the sub-pixels SP to reduce color mixing between the sub-pixels SP. For this purpose, the bank pattern BB may be formed of a black resin, but the present invention is not limited thereto.

[0104] The first protective layer CPA may cover the sixth metal layer, the bank pattern BB, the second planarization layer PLN2, and the third planarization layer PLN3. The first protective layer CPA may be formed of a single-layer or multi-layer insulating layer such as transparent epoxy resin, silicon oxide (SiOx), or silicon nitride (SiNx).

[0105] Each first pad electrode PAD1 provided in the pad regions PA1 and PA2 of the first substrate SUBS1 may have a multi-layer metal layer structure. For example, each first pad electrode PAD1 may include a first pad metal layer PE1a, a second pad metal layer PE1b, and a third pad metal layer PE1c laminated on the outermost periphery of the front surface of the first substrate SUBS1.

[0106] The pattern of the third metal layer provided on the second interlayer insulating layer ILD2 may further include a first pad metal layer PE1a. The first pad metal layer PE1a may be formed of the same metal as the source SE and the drain DE of the driving element DT, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or a multi-layer metal layer.

[0107] The pattern of the fifth metal layer provided on the first planarization layer PLN1 may further include a second pad metal layer PE1b. The second pad metal layer PE1b may be formed of the same metal as the reflective layer RF, such as silver (Ag), aluminum (Al), molybdenum (Mo), or a multi-layer metal layer.

[0108] The pattern of the sixth metal layer provided on the third planarization layer PLN3 may further include a third pad metal layer PE1c. The third pad metal layer PE1c may be formed of the same conductive material as the anode AND and the cathode CAT, such as a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a multi-layer metal layer.

[0109] The first metal layer ML1, the second metal layer ML2, and a plurality of insulating layers may be disposed under the first pad electrode PAD1. By disposing the first metal layer ML1, the second metal layer ML2, and a plurality of insulating layers under the first pad electrode PAD1, the step difference of the first pad electrode PAD1 can be adjusted. For example, a buffer layer BUF, a gate insulating layer GI, the first metal layer ML1, a first interlayer insulating layer ILD1, and the second metal layer ML2 may be sequentially disposed between the first pad electrode PAD1 and the first substrate SUBS1. The pattern of the second metal layer disposed on the gate insulating layer GI may include the first metal layer ML1. The pattern of the fourth metal layer disposed on the first interlayer insulating layer ILD1 may include the second metal layer ML2. The plurality of insulating layers and the metal layers ML1 and ML2 under the first pad electrode PAD1 are not limited to Figure 5 the content shown.

[0110] The second substrate SUBS2 may be disposed on the back surface of the first substrate SUBS1. A bonding layer BDL is disposed between the first substrate SUBS1 and the second substrate SUBS2. The bonding layer BDL is cured by various curing methods to bond the first substrate SUBS1 and the second substrate SUBS2. The bonding layer BDL may be disposed only in a partial area or the entire area between the first substrate SUBS1 and the second substrate SUBS2. The first substrate SUBS1 and the second substrate SUBS2 may be simultaneously scribed and polished so that the side surfaces of the first substrate SUBS1 and the second substrate SUBS2 can be formed without steps.

[0111] A plurality of second pad electrodes PAD2 may be disposed on the outermost periphery of the back surface of the second substrate SUBS2. The second pad electrodes PAD2 are electrically connected to the side lines SRL and the first pad electrode PAD1 to transmit signals from circuit elements disposed on the back surface of the second substrate SUBS2 to sub-pixels SP disposed on the upper surface of the first substrate SUBS1.

[0112] Each second pad electrode PAD2 may have a multi-layer metal layer structure. For example, each of the second pad electrodes PAD2 may include a first pad metal layer PE2a, a second pad metal layer PE2b, and a third pad metal layer PE2c stacked on the outer periphery of the back surface of the second substrate SUBS2. Each of the first pad metal layer PE2a and the second pad metal layer PE2b may be formed of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or a multi-layer metal layer. The third pad metal layer PE2c may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0113] The second protective layer BCL may be disposed on the back surface of the second substrate SUBS2. The second protective layer BCL may cover various lines except the second pad electrode PAD2 on the back surface of the second substrate SUBS2. The second protective layer BCL may be made of an organic insulating material such as benzocyclobutene or allyl organic insulating material.

[0114] Circuit elements such as a plurality of flexible films, a PCB, etc. may be disposed on the back side of the second substrate SUBS2. The output terminal of the flexible film is electrically connected to the second pad electrode PAD2, and the input terminal of the flexible film is electrically connected to the output terminal of the PCB. Therefore, the signal or voltage output from the PCB can be transmitted to the sub-pixel SP disposed on the front surface of the first substrate SUBS1 via the flexible film, the second pad electrode PAD2, the side line SRL, the plurality of first pad electrodes PAD1, and the lines connected to the first pad electrodes PAD1.

[0115] The side line SRL straddles the side surfaces of the first substrate SUBS1 and the second substrate SUBS2 and electrically connects the first pad electrode PAD1 and the second pad electrode PAD2. The side line SRL may be formed on the side surfaces of the first substrate SUBS1 and the second substrate SUBS2 by a pad printing method using a conductive ink containing silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), etc.

[0116] The side insulating layer SDI may cover the side line SRL formed on the outermost peripheries of the upper surface, side surfaces, and back surface of the first substrate SUBS1 and the second substrate SUBS2 joined to each other. When the side line SRL is made of metal, external light may be reflected from the side line SRL, or the light emitted from the light-emitting element ED may be reflected from the side line SRL and visually recognized by the user. To improve the image quality degradation caused by such reflected light, the side insulating layer SDI may contain a black material that absorbs external light. For example, the side insulating layer SDI may be formed on the outermost peripheries of the first substrate SUBS1 and the second substrate SUBS2 using a black ink that can be applied by printing.

[0117] The sealing layer SS may cover the side insulating layer SDI to protect the display panel PN from external impacts, moisture, oxygen, etc. For example, the sealing layer SS may be made of black ink, polyimide (PI), polyurethane (PU), epoxy resin, allyl insulating material, etc. The sealing layer SS may be a concept including the side insulating layer SDI. That is, the sealing layer SS and the side insulating layer SDI may be configured as one layer.

[0118] The cover film MF can cover the front surface of the display panel PN. The cover film MF can include one or more of various functional films such as a light-scattering prevention film, an antiglare film, an antireflection film, a low-reflection film, an organic light-emitting diode (OLED) transmittance controllable film, a color difference compensation film, a polarizing plate, etc. The light-scattering prevention film prevents substrate fragments or particles from splashing when the display panel PN is broken. By widely adhering the sealing layer SS to the front surface of the first substrate SUBS1 and then cutting along a cutting line overlapping with the sealing layer SS, the cover film MF can be cut and removed together with the outside of the sealing layer SS. Therefore, the outermost exposed surfaces of the cover film MF and the sealing layer SS can form the same plane without steps.

[0119] Figure 6 is a diagram showing a pixel according to an embodiment of the present specification. Figure 7 is a diagram showing a red sub-pixel according to an embodiment of the present specification. Figure 8 is a diagram showing a green sub-pixel according to an embodiment of the present specification. Figure 9 is a diagram showing a blue sub-pixel according to an embodiment of the present specification. Figure 10 is a diagram showing cathodes of a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0120] Referring to Figure 6 , a pixel can include six sub-pixels. As an example, a pixel can include two red sub-pixels R1 and R2, two green sub-pixels G1 and G2, and two blue sub-pixels B1 and B2. Each of the sub-pixels can include a light-emitting element and a pixel circuit including a compensation circuit. The compensation circuit is a circuit for compensating the threshold voltage of a driving element, and the pixel circuit can be a circuit including a light-emitting element, a driving element, and a compensation circuit. When a sub-pixel includes two light-emitting elements and one compensation circuit, the sub-pixel can be defined as one sub-pixel.

[0121] According to an embodiment, each of the sub-pixels R1, R2, G1, G2, B1, and B2 can be driven independently or simultaneously. The multiple sub-pixels R1, R2, G1, G2, B1, and B2 can be simultaneously driven by sharing one gate line. However, the present invention is not necessarily limited thereto, and multiple gate lines can be configured such that the pixels R1, G1, and B1 of the first pixel group connected to the first gate line SCAN1 and the pixels R2, G2, and B2 of the second pixel group connected to the second gate line SCAN2 can be driven independently.

[0122] The two red sub-pixels R1 and R2 can be respectively connected to the data lines VdataR1 and VdataR2. On the other hand, the two green sub-pixels G1 and G2 can share one data line VdataG, and the two blue sub-pixels B1 and B2 can share one data line VdataB. Therefore, the number of data lines can be reduced.

[0123] The red sub-pixels R1 and R2 have relatively low efficiency and can thus be independently driven to adjust their brightness, while the green sub-pixels G1 and G2 and the blue sub-pixels B1 and B2 have relatively high efficiency and can thus emit light simultaneously using one data line.

[0124] In this case, since the two light-emitting elements are turned on simultaneously by a data voltage, it is possible to advantageously output a desired brightness even when the data voltage is decreased. However, the present invention is not necessarily limited thereto, and the green sub-pixels and the blue sub-pixels can also be respectively connected to the data lines and independently driven.

[0125] Referring to Figure 7 , the red sub-pixel can include a first red sub-pixel (1-1 sub-pixel) R1 and a second red sub-pixel (1-2 sub-pixel) R2. The first red sub-pixel R1 can include a first red light-emitting element ED11 and a first red compensation circuit PC11. The first red light-emitting element ED11 can be connected to an anode AND connected to a high-potential power supply line HL, and a cathode CAT connected to a low-potential power supply line CL1. The first red compensation circuit PC11 can be connected between the first data line VdataR1 and the low-potential power supply line CL1.

[0126] The second red sub-pixel R2 can include a second red light-emitting element ED12 and a second red compensation circuit PC12. The second red light-emitting element ED12 can be connected to an anode connected to the high-potential power supply line HL, and a cathode connected to a low-potential power supply line CL2. The second red compensation circuit PC12 can be connected between the second data line VdataR2 and the low-potential power supply line CL2.

[0127] According to an embodiment, the first red sub-pixel R1 and the second red sub-pixel R2 are respectively connected to the first data line VdataR1 and the second data line VdataR2, and thus can be independently driven. Therefore, when the voltage levels applied to the first data line VdataR1 and the second data line VdataR2 are differentially adjusted, the first red light-emitting element ED11 and the second red light-emitting element ED12 can emit light with different brightnesses. That is, the brightnesses of the first red light-emitting element ED11 and the second red light-emitting element ED12 can be independently controlled according to the total brightness of the red light to be output from the pixel. Alternatively, the first red light-emitting element ED11 and the second red light-emitting element ED12 can be alternately driven. However, the present invention is not necessarily limited thereto, and the first red sub-pixel R1 and the second red sub-pixel R2 can be simultaneously driven through one data line. Since each of the first red sub-pixel R1 and the second red sub-pixel R2 is configured as an independent pixel, even when a short-circuit failure occurs in one of the first red sub-pixel R1 and the second red sub-pixel R2, the failure does not affect the other.

[0128] Referring to Figure 8 , the green sub-pixel may include a first green sub-pixel (2-1 sub-pixel) G1 and a second green sub-pixel (2-2 sub-pixel) G2. The first green sub-pixel G1 may include a first green light-emitting element ED21 and a first green compensation circuit PC21. The first green light-emitting element ED21 may be connected to an anode connected to the high-potential power supply line HL and a cathode connected to the low-potential power supply line CL3. The first green compensation circuit PC21 may be connected between the third data line VdataG and the low-potential power supply line CL3.

[0129] The second green sub-pixel G2 may include a second green light-emitting element ED22 and a second green compensation circuit PC22. The second green light-emitting element ED22 may be connected to an anode connected to the high-potential power supply line HL and a cathode connected to the low-potential power supply line CL4. The second green compensation circuit PC22 may be connected between the third data line VdataG and the low-potential power supply line CL4.

[0130] According to an embodiment, the first green sub-pixel G1 and the second green sub-pixel G2 are commonly connected to the third data line VdataG and thus can be simultaneously driven. Therefore, the data voltage can be set relatively low. For example, when the data voltage applied to output a predetermined brightness of the green sub-pixel in a corresponding frame is 1V, since two green light-emitting elements emit light, even when the data voltage is reduced to 0.5V and applied, green light with a desired brightness can be output.

[0131] As an example, in the case of a second pixel in which one of the first green sub-pixel G1 and the second green sub-pixel G2 fails, only one sub-pixel is used to adjust the brightness. Therefore, compared with the first pixel in which both sub-pixels emit light, it is necessary to apply twice the data voltage to adjust to achieve the same brightness.

[0132] According to an embodiment, the anodes of the first green light-emitting element ED21 and the second green light-emitting element ED22 can be electrically separated from each other, and the cathodes of the first green light-emitting element ED21 and the second green light-emitting element ED22 can be electrically separated from each other. Therefore, even when the high-potential voltage VDD and the low-potential voltage VSS are short-circuited due to the failure of the first green light-emitting element ED21 and the first green light-emitting element ED21 becomes dim, the adjacent second green light-emitting element ED22 is not affected.

[0133] The failure of the first green light-emitting element ED21 can be a failure of the electrode pad or a failure caused by an inherent defect of the semiconductor layer itself. The micro-sized light-emitting diodes are small in size, so they are easily affected by static electricity, and are manufactured on a wafer at a micro-scale and then transferred to a panel, so the failure rate is high due to various reasons.

[0134] Therefore, in the case where the first green light-emitting element ED21 and the second green light-emitting element ED22 are connected in series or in parallel, when one of the light-emitting elements experiences a short-circuit failure (where the high-potential voltage VDD and the low-potential voltage VSS are short-circuited) and becomes dim, the adjacent normal light-emitting element may also become a dark spot due to the flow of the short-circuit current. However, according to the embodiment, since the anode and cathode of the first green light-emitting element ED21 are separated from the anode and cathode of the second green light-emitting element ED22, even when one of the light-emitting elements experiences a short-circuit failure, it is possible to prevent the adjacent light-emitting element from becoming dim. Therefore, the adjacent light-emitting elements can operate normally.

[0135] Refer to Figure 9 As shown in FIG. [Reference number], the blue sub-pixel may include a first blue sub-pixel (3-1 sub-pixel) B1 and a second blue sub-pixel (3-2 sub-pixel) B2. The first blue sub-pixel B1 may include a first blue light-emitting element ED31 and a first blue compensation circuit PC31. The first blue light-emitting element ED31 may be connected to an anode connected to the high-potential power supply line HL and a cathode connected to the low-potential power supply line CL5. The first blue compensation circuit PC31 may be connected between the fourth data line VdataB and the low-potential power supply line CL5.

[0136] The second blue sub-pixel B2 may include a second blue light-emitting element ED32 and a second blue compensation circuit PC32. The second blue light-emitting element ED32 may be connected to an anode connected to a high-potential power supply line HL and a cathode connected to a low-potential power supply line CL6. The second blue compensation circuit PC32 may be connected between a fourth data line VdataB and the low-potential power supply line CL6.

[0137] According to an embodiment, the first blue sub-pixel B1 and the second blue sub-pixel B2 are commonly connected to the fourth data line VdataB and can thus be driven simultaneously. Therefore, the data voltage can be set lower than the voltage level for causing one blue light-emitting element to emit light at a desired brightness.

[0138] As an example, in the case of a fourth pixel in which one of the first blue sub-pixel B1 and the second blue sub-pixel B2 fails, only one sub-pixel is used to adjust the brightness. Therefore, compared with the third pixel in which both sub-pixels emit light, twice the data voltage needs to be applied for adjustment to achieve the same brightness.

[0139] In addition, the anodes of the first blue light-emitting element ED31 and the second blue light-emitting element ED32 may be electrically separated from each other, and the cathodes of the first blue light-emitting element ED31 and the second blue light-emitting element ED32 may be electrically separated from each other. Therefore, even when one of the light-emitting elements experiences a short-circuit failure, it is possible to prevent the adjacent light-emitting elements from also dimming.

[0140] Referring to Figure 10 , in a pixel, the anodes And1 of the first red sub-pixel R1, the anodes And2 of the second red sub-pixel R2, the anodes And3 of the first green sub-pixel G1, the anodes And4 of the second green sub-pixel G2, the anodes And5 of the first blue sub-pixel B1, and the anodes And6 of the second blue sub-pixel B2 may be electrically separated from each other.

[0141] In addition, the cathodes Cat1 of the first red sub-pixel R1, the cathodes Cat2 of the second red sub-pixel R2, the cathodes Cat3 of the first green sub-pixel G1, the cathodes Cat4 of the second green sub-pixel G2, the cathodes Cat5 of the first blue sub-pixel B1, and the cathodes Cat6 of the second blue sub-pixel B2 may be electrically separated from each other.

[0142] In addition, multiple high-potential power supply lines HL respectively connected to the anodes And1 to And6 may be separated from each other, and multiple low-potential power supply lines CL respectively connected to the cathodes Cat1 to Cat6 may also be separated from each other. Therefore, it is possible to prevent the light-emitting elements of adjacent sub-pixels from dimming due to a short-circuit failure of the light-emitting element of any one of the multiple sub-pixels.

[0143] Figure 11 is a circuit diagram showing a schematic pixel circuit according to an embodiment of the present specification. Figure 12 is a circuit diagram showing a pixel circuit according to an embodiment of the present specification.

[0144] Referring to Figure 11 , sub-pixels SP1 and SP2 of the same color each include a light-emitting element ED, a driving element DT, a first switching element M1, and a compensation circuit PC. Sub-pixels SP1 and SP2 of the same color may be green sub-pixels or blue sub-pixels.

[0145] Since the two sub-pixels SP1 and SP2 have the same structure as the data line PL2 to which the data voltage Vdata is applied and inserted therebetween, the pixel circuits of each sub-pixel are described with the same reference numerals. Hereinafter, the description will be based on the second sub-pixel SP2 provided on the right side.

[0146] The second sub-pixel SP2 may include a light-emitting element ED, a driving element DT, a first switching element M1, and a compensation circuit PC. The light-emitting element ED, the driving element DT, and the first switching element M1 may be connected in series between the high-potential voltage VDD and the low-potential voltage VSS.

[0147] The driving element DT adjusts the current flowing through the drain-source channel according to the gate-source voltage. The gate-source voltage of the driving element DT varies according to the data voltage Vdata of the pixel data applied to the gate of the driving element DT. Therefore, the current flowing through the driving element DT varies according to the data voltage Vdata. The light-emitting element ED may be driven by the current flowing from the driving element DT to emit light. The capacitor C may be connected between the gate of the driving element DT and the first electrode. The capacitor C is charged with the gate-source voltage of the driving element DT.

[0148] The driving element DT may be connected between the light-emitting element ED and the first switching element M1. In this case, the driving element DT includes a gate to which the data voltage Vdata is applied, a first electrode connected to the cathode of the light-emitting element ED, and a second electrode connected to the first electrode of the first switching element M1.

[0149] The first switching element M1 switches the current path between the high potential voltage VDD and the low potential voltage VSS. The first switching element M1 can be turned on in response to the gate conduction voltage of one of the gate signals GATE1 and GATE2, and can be turned off in response to the gate cut-off voltage of one of the gate signals GATE1 and GATE2. When the first switching element M1 is turned on, the driving element DT and the light-emitting element ED are electrically connected to each other, so that current can be supplied to the light-emitting element ED. When the first switching element M1 is turned off, the current path between the high potential voltage VDD and the low potential voltage VSS is blocked, and thus, current is not supplied to the light-emitting element ED.

[0150] The first switching element M1 can be connected between the driving element DT and the cathode voltage VSS. In this case, the first switching element M1 includes a gate connected to the first gate line, a first electrode connected to the second electrode of the driving element DT, and a second electrode connected to the node to which the cathode voltage VSS is applied.

[0151] The pixel circuit may further include a second switching element M2. The second switching element M2 is connected between the cathode and the anode of the light-emitting element ED and can be turned on in response to the gate signal applied through the compensation circuit. When the second switching element M2 is turned on, the cathode and the anode of the light-emitting element ED are short-circuited, so that the light-emitting element ED does not emit light. The second switching element M2 can prevent the light-emitting element ED from emitting light when the pixel circuit is initialized and the threshold voltage of the driving element DT is sampled. The second switching element M2 includes a gate connected to the second gate line, a first electrode connected to the anode of the light-emitting element ED, and a second electrode connected to the cathode of the light-emitting element ED.

[0152] The first switching element M1 can be turned on in response to the gate conduction voltage of the light-emitting signal and turned off in response to the gate cut-off voltage of the light-emitting signal, but the present invention is not limited thereto. The second switching element M2 can be turned on in response to the gate conduction voltage of the first scan signal and turned off in response to the gate cut-off voltage of the first scan signal, but the present invention is not limited thereto.

[0153] The compensation circuit PC is connected to the data line to which the data voltage Vdata is applied, the gate line to which one or more scan signals SCAN1 and SCAN2 are applied, the gate of the driving element DT, and the gate of the first switching element M1. One or more scan signals SCAN1 and SCAN2 can be applied to the compensation circuit.

[0154] The compensation circuit uses multiple transistors to transfer the data voltage Vdata to the gate of the driving element DT. The compensation circuit samples the threshold voltage of the driving element DT on the capacitor C and compensates the gate voltage of the driving element DT through the threshold voltage of the driving element DT. The compensation circuit can utilize a source follower or a diode-connected circuit to compensate the threshold voltage of the driving element DT.

[0155] Referring Figure 12 , the pixel circuit may include a driving element DT connected to the light-emitting element ED, multiple switching elements M1 to M6, and multiple capacitors C1 to C3. The driving element DT and the multiple switching elements M1 to M6 may be P-channel transistors, but the present invention is not necessarily limited thereto.

[0156] The driving element DT may have a gate G connected to the first node n1, a source S connected to the second node n2, and a drain D connected to the third node n3.

[0157] The light-emitting element ED may be disposed between the second node n2 and the high-potential voltage VDD. The light-emitting element ED may be a micro-sized light-emitting diode, but the present invention is not necessarily limited thereto. The source S of the driving element DT may be connected to the cathode of the light-emitting element ED.

[0158] The first switching element M1 may be connected between the third node N3 of the driving element DT and the low-potential voltage VSS. When the first switching element M1 is turned on in response to the gate conduction voltage of the light-emitting signal EM, the first switching element M1 may connect the third node n3 to the low-potential voltage VSS.

[0159] The second switching element M2 is connected between the cathode and the anode of the light-emitting element ED and may be turned on by the gate conduction voltage of the first scan signal SCAN1. When the second switching element M2 is turned on, the light-emitting element does not emit light.

[0160] The third switching element M3 is connected between the reference voltage line PL1 and the fourth node n4. When the third switching element M3 is turned on in response to the gate conduction voltage of the light-emitting signal EM, the reference voltage Vref may be applied to the fourth node n4.

[0161] The fourth switching element M4 is disposed between the third node n3 and the first node n1. When the fourth switching element M4 is turned on in response to the gate conduction voltage of the first scan signal SCAN1, the third node n3 may be connected to the first node n1.

[0162] The fifth switching element M5 is disposed between the reference voltage line PL1 and the fifth node n5. When the fifth switching element M5 is turned on in response to the gate conduction voltage of the second scan signal SCAN2, the reference voltage Vref may be applied to the fifth node n5.

[0163] The sixth switching element M6 is disposed between the data line PL2 and the fourth node n4. When the sixth switching element M6 is turned on in response to the gate conduction voltage of the first scan signal SCAN1, the data voltage Vdata can be applied to the fourth node n4.

[0164] The first capacitor C1 can be disposed between the first node n1 and the fourth node n4, and the second capacitor C2 can be disposed between the first node n1 and the second node n2, and the third capacitor C3 can be disposed between the second capacitor C2 and the anode of the light-emitting element ED. The threshold voltage of the driving element and the data voltage can be stored in the second capacitor C2 and the third capacitor C3, respectively.

[0165] Refer to Figure 13 , in the first initialization period INI1, the first scan signal SCAN1 can be output as the gate cut-off voltage VGH, and the second scan signal SCAN2 can be output as the gate conduction voltage VGL. The fifth switching element M5 to which the second scan signal SCAN2 is applied can be turned on and the reference voltage can be applied to the third node n3. The reference voltage Vref applied during the light-emitting period of the previous frame can be held at the first node n1, and the reference voltage Vref can be applied to the third node n3.

[0166] In the second initialization period INI2, both the first scan signal SCAN1 and the second scan signal SCAN2 are output as the gate conduction voltage VGL, so that the second switching element M2, the fourth switching element M4, the fifth switching element M5, and the sixth switching element M6 can be turned on. Therefore, the data voltage Vdata can be charged to the first node n1, and the reference voltage Vref can be charged to the first node n1, so that the first capacitor C1 can be initialized. In addition, the gate of the driving element DT can be initialized to the reference voltage Vref. In this case, since the second switching element M2 is turned on, the cathode and the anode of the light-emitting element ED may be short-circuited, and thus, the light-emitting element ED may not emit light.

[0167] In the sampling period SAM, the first scan signal SCAN1 has the gate conduction voltage VGL and the second scan signal SCAN2 has the gate cut-off voltage VGH, so that the sixth switching element M6, the fourth switching element M4, and the second switching element M2 can be turned on. Therefore, a voltage of VDD+Vth can be stored at the first node n1.

[0168] In the holding period HOL, the first scan signal SCAN1, the second scan signal SCAN2, and the light-emitting signal EM all have the gate cut-off voltage VGH, and thus, all the switching elements may be turned off. Therefore, a voltage of VDD+Vth can be held at the first node n1.

[0169] During the light-emitting period EMI, the first scan signal SCAN1 and the second scan signal SCAN2 may have a gate cut-off voltage VGH, and the light-emitting signal EM may have a gate-on voltage VGL. The first switching element M1 and the third switching element M3 may be turned on. Therefore, the reference voltage Vref may be applied to the first node n1, and due to capacitor coupling, a voltage of VDD + Vth - (Vdata - Vref) may be applied to the first node n1.

[0170] The current Ids flowing through the driving element DT can be defined as k(IVgsl - lVthl) 2 . Therefore, assuming k(VDD - VDD - Vth + Vdata - Vref + Vth) 2 , the expression can be simplified to k(Vdata - Vref) 2 . Therefore, the threshold voltage of the driving element can be compensated.

[0171] Figure 14 is a diagram showing pixels in which sub-pixels are connected in parallel. Figure 15 is a diagram showing Figure 14 sub-pixels.

[0172] Referring to Figure 14 and Figure 15 , the pixel may include four sub-pixels R1, R2, G, and B. That is, the pixel may include a first red sub-pixel R1, a second red sub-pixel R2, a green sub-pixel G, and a blue sub-pixel B.

[0173] The first red sub-pixel R1 and the second red sub-pixel R2 may each include a light-emitting element ED and a compensation circuit PC, which have the same structure as Figure 7 . However, the green sub-pixel G may have two green light-emitting elements ED arranged in parallel, and the two green light-emitting elements ED may share a compensation circuit PC. In addition, the red sub-pixel R may have two red light-emitting elements ED arranged in parallel, and the two red light-emitting elements ED may share a compensation circuit PC. With this structure, the number of compensation circuits can be reduced, thereby increasing the aperture ratio.

[0174] However, since the two green light-emitting elements ED1 and ED2 are connected in parallel, there is a problem that when one of the light-emitting elements experiences a short-circuit failure and becomes dim, the adjacent light-emitting element also short-circuits and becomes dim. Therefore, there is a problem that all the green light-emitting elements ED1 and ED2 in the corresponding pixel become dim.

[0175] Figure 16 and Figure 17 are diagrams showing the process of repairing sub-pixels.

[0176] Reference Figure 16 As shown in Figure 16 , a plurality of pixels may include a first pixel PIXEL(N) disposed on a first pixel line and a second pixel PIXEL(N+1) disposed on a second pixel line. The first pixel PIXEL(N) may include a first sub-pixel SP1 and a second sub-pixel SP2 of the same color, and the second pixel PIXEL(N+1) may include a third sub-pixel SP3 and a fourth sub-pixel SP4 of the same color. The first pixel line and the second pixel line may be adjacent to each other in the column direction (Y-axis direction), but the present invention is not limited thereto.

[0177] Each of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 includes a light-emitting element ED, a compensation circuit PC, a high-potential power supply line HL, and a low-potential power supply line CL.

[0178] The first sub-pixel SP1 may be arranged to face the third sub-pixel SP3 in the column direction, and the second sub-pixel SP2 may be arranged to face the fourth sub-pixel SP4 in the column direction.

[0179] The low-potential power supply line CL11 provided in the first sub-pixel SP1 may extend toward the third sub-pixel SP3, and the low-potential power supply line CL13 provided in the third sub-pixel SP3 may extend toward the first sub-pixel SP1. In addition, the low-potential power supply line CL12 provided in the second sub-pixel SP2 may extend toward the fourth sub-pixel SP4, and the low-potential power supply line CL14 provided in the fourth sub-pixel SP4 may extend toward the second sub-pixel SP2.

[0180] A welding portion WP may be formed at an end of each of the low-potential power supply lines CL11, CL12, CL13, and CL14 extending outside each sub-pixel. The welding portion WP includes metal layers overlapping each other (with an insulating layer therebetween) and may be selectively connected in a welding process.

[0181] Reference Figure 17 As shown in Figure 17 , when a failure occurs in the compensation circuit PC of the fourth sub-pixel SP4, a repair portion WP2 may be formed by connecting the welding portion WP of the low-potential power supply line CL14 of the fourth sub-pixel SP4 to the welding portion WP of the low-potential power supply line CL12 of the second sub-pixel SP2. Therefore, in this case, the welding portion WP may be connected after electrically disconnecting the light-emitting element ED from the compensation circuit PC in the fourth sub-pixel SP4. With this configuration, when a failure occurs in the compensation circuit of each sub-pixel, the compensation circuit may be connected to the compensation circuit of an adjacent sub-pixel and may operate normally.

[0182] A display panel according to an embodiment of the present specification and a display device including the display panel may be described as follows.

[0183] A display panel according to an embodiment of the present specification includes a plurality of pixels, and gate lines and data lines connected to the plurality of pixels, wherein each of the plurality of pixels includes a 1-1 sub-pixel and a 1-2 sub-pixel of a first color, a 2-1 sub-pixel and a 2-2 sub-pixel of a second color, and a 3-1 sub-pixel and a 3-2 sub-pixel of a third color, wherein each of the 2-1 sub-pixel and the 2-2 sub-pixel includes a light-emitting element and a compensation circuit, and the compensation circuits of the 2-1 sub-pixel and the 2-2 sub-pixel are connected to one data line.

[0184] According to one or more embodiments of the present specification, the 1-1 sub-pixel may include a first compensation circuit connected to a first data line, and the 1-2 sub-pixel may include a second compensation circuit connected to a second data line.

[0185] According to one or more embodiments of the present specification, each of the 3-1 sub-pixel and the 3-2 sub-pixel may include a compensation circuit, and the compensation circuits of the 3-1 sub-pixel and the 3-2 sub-pixel may be connected to one data line.

[0186] According to one or more embodiments of the present specification, the first color may be red, the second color may be green, and the third color may be blue.

[0187] According to one or more embodiments of the present specification, the plurality of pixels may include: a first pixel, in which when a data voltage is applied, both the 2-1 sub-pixel and the 2-2 sub-pixel emit light; and a second pixel, in which when a data voltage is applied, only one of the 2-1 sub-pixel and the 2-2 sub-pixel emits light.

[0188] According to one or more embodiments of the present specification, the data voltages applied to the 2-1 sub-pixel and the 2-2 sub-pixel of the second pixel may be greater than the data voltages applied to the 2-1 sub-pixel and the 2-2 sub-pixel of the first pixel.

[0189] According to one or more embodiments of the present specification, the plurality of pixels may include: a third pixel, in which when a data voltage is applied, both the 3-1 sub-pixel and the 3-2 sub-pixel emit light; and a fourth pixel, in which when a data voltage is applied, only one of the 3-1 sub-pixel and the 3-2 sub-pixel emits light.

[0190] According to one or more embodiments of the present specification, the data voltages applied to the 3-1 sub-pixel and the 3-2 sub-pixel of the fourth pixel may be greater than the data voltages applied to the 3-1 sub-pixel and the 3-2 sub-pixel of the third pixel.

[0191] According to one or more embodiments of the present specification, the display panel may include a first gate line connected to 1-1 sub-pixels, 2-1 sub-pixels, and 3-1 sub-pixels, and a second gate line connected to 1-2 sub-pixels, 2-2 sub-pixels, and 3-2 sub-pixels.

[0192] According to one or more embodiments of the present specification, each of the 1-1 sub-pixels to 3-2 sub-pixels may include an anode and a cathode for applying a voltage to the light-emitting element. The anodes of the 1-1 sub-pixels to 3-2 sub-pixels may be separated from each other, and the cathodes of the 1-1 sub-pixels to 3-2 sub-pixels may be separated from each other.

[0193] According to one or more embodiments of the present specification, the compensation circuits of the 2-1 sub-pixels and the compensation circuits of the 2-2 sub-pixels may have the same structure.

[0194] According to one or more embodiments of the present specification, the plurality of pixels may include a plurality of first pixels disposed in a first pixel line and a plurality of second pixels disposed in a second pixel line adjacent to the first pixel line. The 2-1 sub-pixel of the first pixel may include a first low-potential power line connected to the first cathode of the 2-1 sub-pixel of the first pixel. The 2-1 sub-pixel of the second pixel may include a second low-potential power line connected to the second cathode of the 2-1 sub-pixel of the second pixel. The first low-potential power line may extend toward the second cathode, the second low-potential power line may extend toward the first cathode, and the first low-potential power line and the second low-potential power line may be electrically connected to each other.

[0195] According to one or more embodiments of the present specification, the first low-potential power line of the 2-1 sub-pixel of the first pixel may be electrically connected to the compensation circuit of the 2-1 sub-pixel of the second pixel.

[0196] According to one or more embodiments of the present specification, the first compensation circuit of the 1-1 sub-pixel may be connected between the first data line and the first low-potential line, and the second compensation circuit of the 1-2 sub-pixel may be connected between the second data line and the second low-potential line.

[0197] A display device according to an embodiment of the present specification includes: a display panel including a plurality of pixels, and gate lines and data lines connected to the plurality of pixels; a gate driver connected to the gate lines; and a data driver connected to the data lines. Each of the plurality of pixels includes 1-1 sub-pixels and 1-2 sub-pixels of a first color, 2-1 sub-pixels and 2-2 sub-pixels of a second color, and 3-1 sub-pixels and 3-2 sub-pixels of a third color. Each of the 2-1 sub-pixels and the 2-2 sub-pixels includes a light-emitting element and a compensation circuit, and the compensation circuits of the 2-1 sub-pixels and the 2-2 sub-pixels are connected to one data line.

[0198] According to one or more embodiments of the present specification, the 1-1 sub-pixel may include a first compensation circuit connected to a first data line, and the 1-2 sub-pixel may include a second compensation circuit connected to a second data line.

[0199] According to one or more embodiments of the present specification, each of the 3-1 sub-pixel and the 3-2 sub-pixel may include a compensation circuit, and the compensation circuits of the 3-1 sub-pixel and the 3-2 sub-pixel may be connected to one data line.

[0200] According to one or more embodiments of the present specification, the first color may be red, the second color may be green, and the third color may be blue.

[0201] According to one or more embodiments of the present specification, a plurality of pixels may include: a first pixel in which when a data voltage is applied, both the 2-1 sub-pixel and the 2-2 sub-pixel emit light; and a second pixel in which when a data voltage is applied, only one of the 2-1 sub-pixel and the 2-2 sub-pixel emits light.

[0202] According to one or more embodiments of the present specification, the data voltages applied to the 2-1 sub-pixel and the 2-2 sub-pixel of the second pixel may be greater than the data voltages applied to the 2-1 sub-pixel and the 2-2 sub-pixel of the first pixel.

[0203] The display device according to an embodiment of the present specification may be applicable to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved surface devices, sliding devices, variable devices, electronic notepads, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptops, netbook computers, workstations, navigation systems, navigation systems for vehicles, display devices for vehicles, devices for vehicles, theater devices, theater display devices, televisions, wallpaper devices, sign devices, game devices, laptops, monitors, cameras, portable video cameras, consumer electronic devices, etc.

[0204] According to the present specification, even when one of the light-emitting elements of a plurality of sub-pixels becomes dim, the remaining light-emitting elements can still emit light. Therefore, the number of dark points in the light-emitting elements of the display device can be reduced. In addition, low-power operation can be achieved.

[0205] In addition, by using a pixel structure that is beneficial to improving dark points, a display panel that is beneficial to process optimization, high efficiency, high brightness, and long life can be achieved.

[0206] It should be noted that the advantageous effects of this specification are not limited to the above effects, and other effects not described herein will be obvious to those skilled in the art from the following description.

[0207] Although the embodiments of this specification and their advantages have been described in detail with reference to the accompanying drawings, it will be apparent to those skilled in the art to which this specification pertains that modifications can be made without departing from the scope of this specification. Therefore, the scope of this specification will be defined by the appended claims rather than the above detailed description, and all changes and modifications derived from the meaning and scope of the claims and their equivalents should be understood to be included within the scope of this specification.

Claims

1. A display panel, comprising: Multiple pixels; as well as gate lines and data lines connected to the plurality of pixels, Wherein, each of the plurality of pixels comprises: A 1-1 subpixel and a 1-2 subpixel of a first color; A 2-1 sub-pixel and a 2-2 sub-pixel of a second color; and 3-1 sub-pixel and 3-2 sub-pixel of the third color, Each of the 2-1 sub-pixel and the 2-2 sub-pixel includes a light emitting element and a compensation circuit, and The compensation circuit of the 2-1 sub-pixel and the compensation circuit of the 2-2 sub-pixel are connected to one data line.

2. The display panel according to claim 1, wherein: The 1-1 sub-pixel includes a first compensation circuit connected to a first data line, and The 1-2 sub-pixel includes a second compensation circuit connected to a second data line.

3. The display panel according to claim 1, wherein: Each of the 3-1 sub-pixel and the 3-2 sub-pixel includes a compensation circuit, and The compensation circuit of the 3-1 sub-pixel and the compensation circuit of the 3-2 sub-pixel are connected to one data line.

4. The display panel according to claim 1, wherein: The first color is red, The second color is green, and The third color is blue.

5. The display panel according to claim 1, wherein: The plurality of pixels comprises: a first pixel, in which both the 2-1 sub-pixel and the 2-2 sub-pixel emit light when a data voltage is applied thereto; and A second pixel in which only one of the 2-1 sub-pixel and the 2-2 sub-pixel emits light when a data voltage is applied.

6. The display panel according to claim 5, wherein: The data voltages applied to the 2-1 sub-pixel and the 2-2 sub-pixel of the second pixel are greater than the data voltages applied to the 2-1 sub-pixel and the 2-2 sub-pixel of the first pixel.

7. The display panel according to claim 5, wherein: The plurality of pixels comprises: a third pixel in which both the 3-1 sub-pixel and the 3-2 sub-pixel emit light when a data voltage is applied; and A fourth pixel in which only one of the 3-1 sub-pixel and the 3-2 sub-pixel emits light when a data voltage is applied.

8. The display panel according to claim 7, wherein: The data voltages applied to the 3-1 sub-pixel and the 3-2 sub-pixel of the fourth pixel are greater than the data voltages applied to the 3-1 sub-pixel and the 3-2 sub-pixel of the third pixel.

9. The display panel according to claim 1, comprising: a first gate line connected to the 1-1 sub-pixel, the 2-1 sub-pixel, and the 3-1 sub-pixel; as well as A second gate line connected to the 1-2 sub-pixel, the 2-2 sub-pixel, and the 3-2 sub-pixel.

10. The display panel according to claim 1, wherein: Each of the 1-1 to 3-2 sub-pixels includes an anode and a cathode for applying a voltage to the light emitting element. The anodes of the 1-1 sub-pixel to the 3-2 sub-pixel are separated from each other, and The cathodes of the 1-1 to 3-2 sub-pixels are separated from each other.

11. The display panel according to claim 1, wherein: The compensation circuit of the 2-1 sub-pixel and the compensation circuit of the 2-2 sub-pixel have the same structure.

12. The display panel according to claim 1, wherein: The plurality of pixels include a plurality of first pixels arranged in a first pixel line, and a plurality of second pixels arranged in a second pixel line adjacent to the first pixel line, The 2-1 sub-pixel of the first pixel includes a first low potential power line connected to a first cathode of the 2-1 sub-pixel of the first pixel, The 2-1 sub-pixel of the second pixel includes a second low potential power line connected to a second cathode of the 2-1 sub-pixel of the second pixel, The first low potential power line extends toward the second cathode, The second low potential power line extends toward the first cathode, and The first low potential power line and the second low potential power line are electrically connected to each other.

13. The display panel according to claim 12, wherein: The first low potential power line of the 2-1 sub-pixel of the second pixel is electrically connected to the compensation circuit of the 2-1 sub-pixel of the first pixel.

14. The display panel according to claim 2, wherein: The first compensation circuit of the 1-1 sub-pixel is connected between the first data line and the first low potential line, and The second compensation circuit of the 1-2 sub-pixel is connected between the second data line and the second low potential line.

15. A display device, comprising: A display panel including a plurality of pixels and gate lines and data lines connected to the plurality of pixels; a gate driver connected to the gate line; as well as a data driver connected to the data line, Wherein, each of the plurality of pixels comprises: A 1-1 subpixel and a 1-2 subpixel of a first color; A 2-1 sub-pixel and a 2-2 sub-pixel of a second color; and 3-1 sub-pixel and 3-2 sub-pixel of the third color, Each of the 2-1 sub-pixel and the 2-2 sub-pixel includes a light emitting element and a compensation circuit, and The compensation circuit of the 2-1 sub-pixel and the compensation circuit of the 2-2 sub-pixel are connected to one data line.

16. The display device according to claim 15, wherein: The 1-1 sub-pixel includes a first compensation circuit connected to a first data line, and The 1-2 sub-pixel includes a second compensation circuit connected to a second data line.

17. The display device according to claim 15, wherein: Each of the 3-1 sub-pixel and the 3-2 sub-pixel includes a compensation circuit, and The compensation circuit of the 3-1 sub-pixel and the compensation circuit of the 3-2 sub-pixel are connected to one data line.

18. The display device according to claim 15, wherein: The first color is red, The second color is green, and The third color is blue.

19. The display device according to claim 15, wherein: The plurality of pixels comprises: a first pixel, in which both the 2-1 sub-pixel and the 2-2 sub-pixel emit light when a data voltage is applied thereto; and A second pixel in which only one of the 2-1 sub-pixel and the 2-2 sub-pixel emits light when a data voltage is applied.

20. The display device according to claim 19, wherein: The data voltages applied to the 2-1 sub-pixel and the 2-2 sub-pixel of the second pixel are greater than the data voltages applied to the 2-1 sub-pixel and the 2-2 sub-pixel of the first pixel.

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