Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel is arranged in a first direction; at least one of the first clock signal line, the second clock signal line, the third clock signal line, the first high-potential signal line, the second high-potential signal line, the first low-potential signal line, the second low-potential signal line, the second reset control line and the low-frequency signal line is arranged between the first reset control line and the third low-potential signal line. Therefore, the signal line arranged between the first reset control line and the third low-potential signal line can be directly connected to the corresponding transistor without occupying the space of the wiring area of the gate drive circuit, the occupied space of the transistor area of the gate drive circuit can be reduced, the occupied space of the gate drive circuit is reduced, and the reliability of the gate drive circuit is improved. The frame of the display panel is reduced.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display devices are widely used in various fields because of their light weight, wide viewing angle, low power consumption, fast response speed, low temperature resistance, high luminous efficiency, and the ability to fabricate flexible curved display screens. In order to reduce the number of driving chips, reduce the bezel, and lower costs, a gate driving circuit is used to replace the gate driving chip to drive the pixel circuit. Specifically, the gate driving circuit includes a thin-film transistor setting area and a signal routing area. Thin-film transistors are provided in the thin-film transistor setting area, and signal routes are provided in the signal routing area. The signal routes are connected to the thin-film transistors through connection lines. However, in actual use, it is found that the gate driving circuit occupies a large amount of space, and as the resolution of the OLED display device increases, the number of stages of the gate driving circuit increases, resulting in a reduction in the longitudinal space that the gate driving circuit can occupy and a further increase in the lateral space occupied by the gate driving circuit, leading to a large bezel of the display panel.

[0003] Therefore, there is a technical problem in the current display device that the lateral space occupied by the thin-film transistor setting area and the signal routing area in the gate driving circuit is large, resulting in a large bezel of the display device. Summary of the Invention

[0004] Embodiments of this application provide a display panel and a display device to solve the technical problem in the current display device that the lateral space occupied by the thin-film transistor setting area and the signal routing area in the gate driving circuit is large, resulting in a large bezel of the display device.

[0005] To achieve the above object, according to the first aspect of this application, a display panel is provided, which includes:

[0006] Multiple rows of pixels, where the pixels include light-emitting devices and pixel driving circuits;

[0007] The multi-stage gate driving circuit is electrically connected to the corresponding pixel driving circuit respectively. Each stage of the gate driving circuit includes a first type of gate circuit, a second type of gate circuit, and a third type of gate circuit. The first type of gate circuit is electrically connected to at least a first clock signal line, a second clock signal line, a first high-potential signal line, a first low-potential signal line, a second low-potential signal line, a first reset control line, and a low-frequency signal line. The second type of gate circuit is electrically connected to at least the first high-potential signal line, the second low-potential signal line, a third clock signal line of the display panel, and a second reset control line of the display panel. The third type of gate circuit is electrically connected to at least the first high-potential signal line, a second high-potential signal line, the second low-potential signal line, and a third low-potential signal line;

[0008] Wherein, the first reset control line, the first type of gate circuit, the second type of gate circuit, the third type of gate circuit, and the third low-potential signal line are arranged along a first direction. In the first direction, at least one of the first clock signal line, the second clock signal line, the third clock signal line, the first high-potential signal line, the second high-potential signal line, the first low-potential signal line, the second low-potential signal line, the second reset control line, and the low-frequency signal line is arranged between the first reset control line and the third low-potential signal line.

[0009] According to the second aspect of the present application, a display device is provided. The display device includes the display panel as described in any one of the above embodiments.

[0010] The embodiments of the present application provide a display panel and a display device. By arranging at least one of the first clock signal line, the second clock signal line, the third clock signal line, the first high-potential signal line, the second high-potential signal line, the first low-potential signal line, the second low-potential signal line, the second reset control line, and the low-frequency signal line between the first reset control line and the third low-potential signal line in the first direction, the signal lines arranged between the first reset control line and the third low-potential signal line can be directly connected to the corresponding transistors, without occupying the space of the signal line routing area of the gate driving circuit, and the space of the transistor area of the gate driving circuit occupied can be reduced, the space occupied by the gate driving circuit can be reduced, and the border of the display panel can be reduced. Description of the Drawings

[0011] Figure 1 It is a schematic diagram of a display device for comparison.

[0012] Figure 2 It is a plan view of the display panel provided by the embodiment of the present application.

[0013] Figure 3Schematic cross-sectional view of the display panel provided by the embodiment of the present application.

[0014] Figure 4 Circuit diagram of the pixel driving circuit provided by the embodiment of the present application.

[0015] Figure 5 Circuit diagram of the first type of gate circuit provided by the embodiment of the present application.

[0016] Figure 6 Circuit diagram of the second type of gate circuit provided by the embodiment of the present application.

[0017] Figure 7 Circuit diagram of the third type of gate circuit provided by the embodiment of the present application.

[0018] Figure 8 Stacked diagram of the light-shielding layer, active layer, gate layer, and first source-drain layer of the display panel provided by the embodiment of the present application.

[0019] Fig. 9 For Figure 8 Exploded view of the light-shielding layer of the display panel in

[0020] Fig.10 For Figure 8 Exploded view of the active layer of the display panel in

[0021] Fig.11 For Figure 8 Exploded view of the gate layer of the display panel in

[0022] Fig.12 For Figure 8 Exploded view of the first source-drain layer of the display panel in

[0023] Fig.13 For Figure 8 Stacked diagram of the light-shielding layer and active layer of the display panel in

[0024] Fig.14 For Figure 8 Stacked diagram of the light-shielding layer, active layer, and gate layer of the display panel in

[0025] Fig.15 For Figure 8 Stacked diagram of the light-shielding layer and the first via of the display panel in

[0026] Fig.16 For Figure 8 Stacked diagram of the light-shielding layer and the first source-drain layer in

[0027] Fig.17 For Figure 8 Stacked diagram of the gate layer and the second via in

[0028] Fig.18 The Figure 8 stacked diagram of the gate layer and the first source-drain layer in

[0029] Fig.19 The Figure 8 partial enlarged view of the corresponding area of the first type of gate circuit of the display panel in

[0030] Fig. 20 The Fig.19 exploded view of the light-shielding layer of the display panel in

[0031] Fig.21 The Fig.19 exploded view of the active layer of the display panel in

[0032] Fig. 22 The Fig.19 exploded view of the gate layer of the display panel in

[0033] Fig.23 The Fig.19 exploded view of the first source-drain layer of the display panel in

[0034] Fig.24 The Figure 8 partial enlarged view of the corresponding area of the second type of gate circuit of the display panel in

[0035] Fig.25 The Fig.24 exploded view of the light-shielding layer of the display panel in

[0036] Fig.26 The Fig.24 exploded view of the active layer of the display panel in

[0037] Fig. 27 The Fig.24 exploded view of the gate layer of the display panel in

[0038] Fig.28 The Fig.24 exploded view of the first source-drain layer of the display panel in

[0039] Fig.29 The Figure 8 partial enlarged view of the corresponding area of the third type of gate circuit of the display panel in

[0040] Fig.30 The Fig.29 exploded view of the light-shielding layer of the display panel in

[0041] Fig.31 The Fig.29 exploded view of the active layer of the display panel in

[0042] Fig.32For Fig.29 Exploded view of the gate layer of the display panel in

[0043] Fig.33 For Fig.29 Exploded view of the first source-drain layer of the display panel in

[0044] Description of reference numerals:

[0045] 1. Comparison display device; 11. Pixel circuit; 12. Gate circuit 12; 121. Trace area; 122. Transistor area; 121a. Signal trace; 122a. Thin film transistor.

[0046] 2. Display panel; 201. Display area; 202. Non-display area; 21. Pixel driving circuit; 22. Gate driving circuit; 22a. First type of gate circuit; 22b. Second type of gate circuit; 22c. Third type of gate circuit.

[0047] 211. Substrate; 212. Light-shielding layer; 213. Buffer layer; 214. Semiconductor layer; 215. First gate insulating layer; 216. Active layer; 217. Second gate insulating layer; 218. Gate layer; 219. First interlayer insulating layer; 221. First source-drain layer; 222. Second interlayer insulating layer; 223. Second source-drain layer; 224. Passivation layer; 225. Third source-drain layer; 226. First planarization layer; 227. Second planarization layer; 228. Pixel electrode layer; 229. First pixel defining layer; 231. Second pixel defining layer; 411. First via; 412. Second via; T1. Driving transistor; T2. Switching transistor; T3. Reset transistor; T4. Initialization transistor.

[0048] VST1. First reset control line; VST2. Second reset control line; VGH1. First high potential signal line; VGH2. Second high potential signal line; VGL1. First low potential signal line; VGL2. Second low potential signal line; VGL3. Third low potential signal line; LC. Low frequency signal line; CKA. First clock signal line; CKA1. First clock first line; CKA2. First clock second line; CKA3. First clock third line; CKA4. First clock fourth line; CKB. Second clock signal line; CKBi. First group of sub-lines; CKBj. Second group of sub-lines; CKB1. Second clock first line; CKB2. Second clock second line; CKB3. Second clock third line; CKB4. Second clock fourth line; CKB5. Second clock fifth line; CKB6. Second clock sixth line; CKB7. Second clock seventh line; CKB8. Second clock eighth line; CKC. Third clock signal line; CKC1. Third clock first line; CKC2. Third clock second line; CKC3. Third clock third line; CKC4. Third clock fourth line.

[0049] VST1a, the first part of the first reset control line; VST1b, the second part of the first reset control line; VST1c, the third part of the first reset control line; VST2a, the first part of the second reset control line; VST2b, the second part of the second reset control line; VST2c, the third part of the second reset control line; VGH1a, the first part of the first high potential signal line; VGH1b, the second part of the first high potential signal line; VGH1c, the third part of the first high potential signal line; VGH2a, the first part of the second high potential signal line; VGH2b, the second part of the second high potential signal line; VGH2c, the third part of the second high potential signal line; VGL1a, the first part of the first low potential signal line; VGL1b, the second part of the first low potential signal line; VGL1c, the third part of the first low potential signal line; VGL2a, the first part of the second low potential signal line; VGL2b, the second part of the second low potential signal line; VGL2c, the third part of the second low potential signal line; VGL3a, the first part of the third low potential signal line; VGL3b, the second part of the third low potential signal line; VGL3c, the third part of the third low potential signal line; LCa, the first part of the low frequency signal line; LCb, the second part of the low frequency signal line; LCc, the third part of the low frequency signal line; CKAa, the first part of the first clock signal line; CKAb, the second part of the first clock signal line; CKAc, the third part of the first clock signal line; CKA1a, the first part of the first clock first line; CKA1b, the second part of the first clock first line; CKA1c, the third part of the first clock first line; CKA2a, the first part of the first clock second line; CKA2b, the second part of the first clock second line; CKA2c, the third part of the first clock second line; CKA3a, the first part of the first clock third line; CKA3b, the second part of the first clock third line; CKA3c, the third part of the first clock third line; CKA4a, the first part of the first clock fourth line; CKA4b, the second part of the first clock third line; CKA4c, the third part of the first clock fourth line; CKBa, the first part of the second clock signal line; CKBb, the second part of the second clock signal line; CKBc, the third part of the second clock signal line; CKBia, the first part of the first group of sub-lines; CKBib, the second part of the first group of sub-lines; CKBic, the third part of the first group of sub-lines; CKBja, the first part of the second group of sub-lines; CKBjb, the second part of the second group of sub-lines; CKBjc, the third part of the second group of sub-lines; CKB1a, the first part of the second clock first line; CKB1b, the second part of the second clock first line; CKB1c, the third part of the second clock first line; CKB2a, the first part of the second clock second line; CKB2b, the second part of the second clock second line;CKB2c, the third part of the second line of the second clock; CKB3a, the first part of the third line of the second clock; CKB3b, the second part of the third line of the second clock; CKB3c, the third part of the third line of the second clock; CKB4a, the first part of the fourth line of the second clock; CKB4b, the second part of the fourth line of the second clock; CKB4c, the third part of the fourth line of the second clock; CKB5a, the first part of the fifth line of the second clock; CKB5b, the second part of the fifth line of the second clock; CKB5c, the third part of the fifth line of the second clock; CKB6a, the first part of the sixth line of the second clock; CKB6b, the second part of the sixth line of the second clock; CKB6c, the third part of the sixth line of the second clock; CKB7a, the first part of the seventh line of the second clock; CKB7b, the second part of the seventh line of the second clock; CKB7c, the third part of the seventh line of the second clock; CKB8a, the first part of the eighth line of the second clock; CKB8b, the second part of the eighth line of the second clock; CKB8c, the third part of the eighth line of the second clock; CKCa, the first part of the third clock signal line; CKCb, the second part of the third clock signal line; CKCc, the third part of the third clock signal line; CKC1a, the first part of the first line of the third clock; CKC1b, the second part of the first line of the third clock; CKC1c, the third part of the first line of the third clock; CKC2a, the first part of the second line of the third clock; CKC2b, the second part of the second line of the third clock; CKC2c, the third part of the second line of the third clock; CKC3a, the first part of the third line of the third clock; CKC3b, the second part of the third line of the third clock; CKC3c, the third part of the third line of the third clock; CKC4a, the first part of the fourth line of the third clock; CKC4b, the second part of the fourth line of the third clock; CKC4c, the third part of the fourth line of the third clock.;

[0050] 311. First pull-up control module; 312. First pull-up module; 313. First pull-down module; 314. First pull-down maintenance module; 315. First inverter module; 316. First negative-bias protection module; 317. First reset module; T11j. First pull-up control transistor; T12j. Second pull-up control transistor; T81j. Third pull-up control transistor; T81j1. First pull-up control sub-transistor; T81j2. Second pull-up control sub-transistor; T21j. First pull-up transistor; T22j. Second pull-up transistor; T23j. Third pull-up transistor; T31j. First pull-down transistor; T32j. Second pull-down transistor; T33j. Third pull-down transistor; T41j. Fourth pull-down transistor; T41j1. First pull-down sub-transistor; T41j2. Second pull-down sub-transistor; T42j. First pull-down maintenance transistor; T42j1. First pull-down maintenance sub-transistor; T42j2. Second pull-down maintenance sub-transistor; T51j. First inverter transistor; T51j1. First inverter sub-transistor; T51j2. Second inverter sub-transistor; T52j. Second inverter transistor; T53j. Third inverter transistor; T54j. Fourth inverter transistor; T55j. Fifth inverter transistor; T71j. First negative-bias protection transistor; T71j1. First negative-bias protection sub-transistor; T71j2. Second negative-bias protection sub-transistor; T43j. First reset transistor; T43j1. First reset sub-transistor; T43j2. Second reset sub-transistor; C1. First capacitor; C11. First sub-capacitor; C12. Second sub-capacitor; C13. Third sub-capacitor; C14. Fourth sub-capacitor.

[0051] The active part of the first pull-up control transistor, T11jA; the active part of the second pull-up control transistor, T12jA; the active part of the third pull-up control transistor, T81jA; the active part of the first pull-up control sub-transistor, T81j1A; the active part of the second pull-up control sub-transistor, T81j2A; the active part of the first pull-up transistor, T21jA; the active part of the second pull-up transistor, T22jA; the active part of the third pull-up transistor, T23jA; the active part of the first pull-down transistor, T31jA; the active part of the second pull-down transistor, T32jA; the active part of the third pull-down transistor, T33jA; the active part of the fourth pull-down transistor, T41jA; the active part of the first pull-down sub-transistor, T41j1A; the active part of the second pull-down sub-transistor, T41j2A; the active part of the first pull-down holding transistor, T42jA; the active part of the first pull-down holding sub-transistor, T42j1A; the active part of the second pull-down holding sub-transistor, T42j2A; the active part of the first inverter transistor, T51jA; the active part of the first inverter sub-transistor, T51j1A; the active part of the second inverter sub-transistor, T51j2A; the active part of the second inverter transistor, T52jA; the active part of the third inverter transistor, T53jA; the active part of the fourth inverter transistor, T54jA; the active part of the fifth inverter transistor, T55jA; the active part of the first reset transistor, T43jA; the active part of the first reset sub-transistor, T43j1A; the active part of the second reset sub-transistor, T43j1A; the active part of the first negative-bias protection transistor, T71jA; the active part of the first negative-bias protection sub-transistor, T71j1A; the active part of the second negative-bias protection sub-transistor, T71j2A.

[0052] The gate of the first pull-up control transistor, T11jG; the gate of the second pull-up control transistor, T12jG; the gate of the third pull-up control transistor, T81jG; the gate of the first pull-up control sub-transistor, T81j1G; the gate of the second pull-up control sub-transistor, T81j2G; the gate of the first pull-up transistor, T21jG; the gate of the second pull-up transistor, T22jG; the gate of the third pull-up transistor, T23jG; the gate of the first pull-down transistor, T31jG; the gate of the second pull-down transistor, T32jG; the gate of the third pull-down transistor, T33jG; the gate of the fourth pull-down transistor, T41jG; the gate of the first pull-down sub-transistor, T41j1G; the gate of the second pull-down sub-transistor, T41j2G; the gate of the first pull-down maintenance transistor, T42jG; the gate of the first pull-down maintenance sub-transistor, T42j1G; the gate of the second pull-down maintenance sub-transistor, T42j2G; the gate of the first inverter transistor, T51jG; the gate of the first inverter sub-transistor, T51j1G; the gate of the second inverter sub-transistor, T51j2G; the gate of the second inverter transistor, T52jG; the gate of the third inverter transistor, T53jG; the gate of the fourth inverter transistor, T54jG; the gate of the fifth inverter transistor, T55jG; the gate of the first reset transistor, T43jG; the gate of the first reset sub-transistor, T43j1G; the gate of the second reset sub-transistor, T43j1G; the gate of the first negative-bias protection transistor, T71jG; the gate of the first negative-bias protection sub-transistor, T71j1G; the gate of the second negative-bias protection sub-transistor, T71j2G.

[0053] The first electrode of the first pull-up control transistor, T11jS; the first electrode of the second pull-up control transistor, T12jS; the first electrode of the third pull-up control transistor, T81jS; the first electrode of the second pull-up control sub-transistor, T81j2S; the first electrode of the first pull-up transistor, T21jS; the first electrode of the second pull-up transistor, T22jS; the first electrode of the third pull-up transistor, T23jS; the first electrode of the first pull-down transistor, T31jS; the first electrode of the second pull-down transistor, T32jS; the first electrode of the third pull-down transistor, T33jS; the first electrode of the fourth pull-down transistor, T41jS; the first electrode of the first pull-down sub-transistor, T41j1S; the first electrode of the second pull-down sub-transistor, T41j2S; the first electrode of the first pull-down maintenance transistor, T42jS; the first electrode of the first pull-down maintenance sub-transistor, T42j1S; the first electrode of the second pull-down maintenance sub-transistor, T42j2S; the first electrode of the first inverter transistor, T51jS; the first electrode of the first inverter sub-transistor, T51j1S; the first electrode of the second inverter transistor, T52jS; the first electrode of the third inverter transistor, T53jS; the first electrode of the fourth inverter transistor, T54jS; the first electrode of the fifth inverter transistor, T55jS; the first electrode of the first reset transistor, T43jS; the first electrode of the first reset sub-transistor, T43j1S; the first electrode of the first negative-bias protection transistor, T71jS; the first electrode of the second negative-bias protection sub-transistor, T71j2S.

[0054] T11jD, the second electrode of the first pull-up control transistor; T12jD, the second electrode of the second pull-up control transistor; T81jD, the second electrode of the third pull-up control transistor; T81j1D, the second electrode of the first pull-up control sub-transistor; T81j2D, the second electrode of the second pull-up control sub-transistor; T21jD, the second electrode of the first pull-up transistor; T22jD, the second electrode of the second pull-up transistor; T23jD, the second electrode of the third pull-up transistor; T31jD, the second electrode of the first pull-down transistor; T32jD, the second electrode of the second pull-down transistor; T33jD, the second electrode of the third pull-down transistor; T41jD, the second electrode of the fourth pull-down transistor; T41j1D, the second electrode of the first pull-down sub-transistor; T41j2D, the second electrode of the second pull-down sub-transistor; T42jD, the second electrode of the first pull-down maintenance transistor; T42j2D, the second electrode of the second pull-down maintenance sub-transistor; T51jD, the second electrode of the first inverter transistor; T51j1D, the second electrode of the first inverter sub-transistor; T51j2D, the second electrode of the second inverter sub-transistor; T52jD, the second electrode of the second inverter transistor; T53jD, the second electrode of the third inverter transistor; T54jD, the second electrode of the fourth inverter transistor; T55jD, the second electrode of the fifth inverter transistor; T43jD, the second electrode of the first reset transistor; T43j1D, the second electrode of the first reset sub-transistor; T43j1D, the second electrode of the second reset sub-transistor; T71jD, the second electrode of the first negative-bias protection transistor; T71j1D, the second electrode of the first negative-bias protection sub-transistor; T71j2D, the second electrode of the second negative-bias protection sub-transistor; C11a, the first plate of the first sub-capacitor; C11a1, the first part of the first plate of the first sub-capacitor; C11a2, the second part of the first plate of the first sub-capacitor; C11b, the second plate of the first sub-capacitor; C12a, the first plate of the second sub-capacitor; C12a1, the first part of the first plate of the second sub-capacitor; C12a2, the second part of the first plate of the second sub-capacitor; C12b, the second plate of the second sub-capacitor; C13a, the first plate of the third sub-capacitor; C13a1, the first part of the first plate of the third sub-capacitor; C13a2, the second part of the first plate of the third sub-capacitor; C13b, the second plate of the fourth sub-capacitor; C14a, the first plate of the fourth sub-capacitor; C14a1, the first part of the first plate of the fourth sub-capacitor; C14a2, the second part of the first plate of the fourth sub-capacitor; C14b, the second plate of the fourth sub-capacitor.

[0055] Q1[n], the first pull-up node; QB1[n], the first pull-down node; N1[n], the first internal node; Gn[n], the first signal output terminal of the first type of gate circuit at this level; Gn[n - 1], the first signal output terminal of the first type of gate circuit at the previous level; Gn[m], the first signal output terminal of the first type of gate circuit at another level; Cout[n], the stage transmission output terminal of the first type of gate circuit at this level; Cout[n - 2], the stage transmission output terminal of the first type of gate circuit at the two previous levels; Cout[n + 2], the stage transmission output terminal of the first type of gate circuit at the two next levels.

[0056] 321, the second pull-up control module; 322, the second pull-up module; 323, the second pull-down module; 324, the second pull-down maintenance module; 325, the second inverter module; 326, the second negative-bias protection module; 327, the second reset module; T11i, the fourth pull-up control transistor; T12i, the fifth pull-up control transistor; T81i, the sixth pull-up control transistor; T81i1, the third pull-up control sub-transistor; T81i2, the fourth pull-up control sub-transistor; T21i, the fourth pull-up transistor; T31i, the fifth pull-down transistor; T41i, the sixth pull-down transistor; T41i1, the third pull-down sub-transistor; T41i2, the fourth pull-down sub-transistor; T42i, the second pull-down maintenance transistor; T42i1, the third pull-down maintenance sub-transistor; T42i2, the fourth pull-down maintenance sub-transistor; T51i, the sixth inverter transistor; T51i1, the third inverter sub-transistor; T51i2, the fourth inverter sub-transistor; T52i, the seventh inverter transistor; T53i, the eighth inverter transistor; T54i, the ninth inverter transistor; T55i, the tenth inverter transistor; T61i, the second negative-bias protection transistor; T61i1, the third negative-bias protection sub-transistor; T61i2, the fourth negative-bias protection sub-transistor; T43i, the second reset transistor; T43i1, the third reset sub-transistor; T43i2, the fourth reset sub-transistor; C2, the second capacitor.

[0057] T11iA, the active part of the fourth pull-up control transistor; T12iA, the active part of the fifth pull-up control transistor; T81iA, the active part of the sixth pull-up control transistor; T81i1A, the active part of the third pull-up control sub-transistor; T81i2A, the active part of the fourth pull-up control sub-transistor; T21iA, the active part of the fourth pull-up transistor; T31iA, the active part of the fifth pull-down transistor; T41iA, the active part of the sixth pull-down transistor; T41i1A, the active part of the third pull-down sub-transistor; T41i2A, the active part of the fourth pull-down sub-transistor; T42iA, the active part of the second pull-down maintenance transistor; T42i1A, the active part of the third pull-down maintenance sub-transistor; T42i2A, the active part of the fourth pull-down maintenance sub-transistor; T51iA, the active part of the sixth inverter transistor; T51i1A, the active part of the third inverter sub-transistor; T51i2A, the active part of the fourth inverter sub-transistor; T52iA, the active part of the seventh inverter transistor; T53iA, the active part of the eighth inverter transistor; T54iA, the active part of the ninth inverter transistor; T55iA, the active part of the tenth inverter transistor; T43iA, the active part of the second reset transistor; T43i1A, the active part of the third reset sub-transistor; T43i1A, the active part of the fourth reset sub-transistor; T61iA, the active part of the second negative-bias protection transistor; T61i1A, the active part of the third negative-bias protection sub-transistor; T61i2A, the active part of the fourth negative-bias protection sub-transistor.

[0058] T11iG, the gate of the fourth pull-up control transistor; T12iG, the gate of the fifth pull-up control transistor; T81iG, the gate of the sixth pull-up control transistor; T81i1G, the gate of the third pull-up control sub-transistor; T81i2G, the gate of the fourth pull-up control sub-transistor; T21iG, the gate of the fourth pull-up transistor; T31iG, the gate of the fifth pull-down transistor; T41iG, the gate of the sixth pull-down transistor; T41i1G, the gate of the third pull-down sub-transistor; T41i2G, the gate of the fourth pull-down sub-transistor; T42iG, the gate of the second pull-down maintenance transistor; T42i1G, the gate of the third pull-down maintenance sub-transistor; T42i2G, the gate of the fourth pull-down maintenance sub-transistor; T51iG, the gate of the sixth inverter transistor; T51i1G, the gate of the third inverter sub-transistor; T51i2G, the gate of the fourth inverter sub-transistor; T52iG, the gate of the seventh inverter transistor; T53iG, the gate of the eighth inverter transistor; T54iG, the gate of the ninth inverter transistor; T55iG, the gate of the tenth inverter transistor; T43iG, the gate of the second reset transistor; T43i1G, the gate of the third reset sub-transistor; T43i1G, the gate of the fourth reset sub-transistor; T61iG, the gate of the second negative-bias protection transistor; T61i1G, the gate of the third negative-bias protection sub-transistor; T61i2G, the gate of the fourth negative-bias protection sub-transistor.

[0059] The first electrode of the fourth pull-up control transistor, T11iS; the first electrode of the fifth pull-up control transistor, T12iS; the first electrode of the sixth pull-up control transistor, T81iS; the first electrode of the fourth pull-up control sub-transistor, T81i2S; the first electrode of the fourth pull-up transistor, T21iS; the first electrode of the fifth pull-down transistor, T31iS; the first electrode of the sixth pull-down transistor, T41iS; the first electrode of the third pull-down sub-transistor, T41i1S; the first electrode of the fourth pull-down sub-transistor, T41i2S; the first electrode of the second pull-down maintenance transistor, T42iS; the first electrode of the third pull-down maintenance sub-transistor, T42i1S; the first electrode of the fourth pull-down maintenance sub-transistor, T42i2S; the first electrode of the sixth inverter transistor, T51iS; the first electrode of the third inverter sub-transistor, T51i1S; the first electrode of the seventh inverter transistor, T52iS; the first electrode of the eighth inverter transistor, T53iS; the first electrode of the ninth inverter transistor, T54iS; the first electrode of the tenth inverter transistor, T55iS; the first electrode of the second reset transistor, T43iS; the first electrode of the third reset sub-transistor, T43i1S; the first electrode of the second negative-bias protection transistor, T61iS; the first electrode of the fourth negative-bias protection sub-transistor, T61i2S.

[0060] T11iD, the second electrode of the fourth pull-up control transistor; T12iD, the second electrode of the fifth pull-up control transistor; T81iD, the second electrode of the sixth pull-up control transistor; T81i1D, the second electrode of the third pull-up control sub-tube; T81i2D, the second electrode of the fourth pull-up control sub-tube; T21iD, the second electrode of the fourth pull-up transistor; T31iD, the second electrode of the fifth pull-down transistor; T41iD, the second electrode of the sixth pull-down transistor; T41i1D, the second electrode of the third pull-down sub-tube; T41i2D, the second electrode of the fourth pull-down sub-tube; T42iD, the second electrode of the second pull-down sustaining transistor; T42i2D, the second electrode of the fourth pull-down sustaining sub-tube; T51iD, the second electrode of the sixth inverting transistor; T51i1D, the second electrode of the third inverting sub-tube; T51i2D, the second electrode of the fourth inverting transistor; T52iD, the second electrode of the seventh inverting transistor; T53iD, the second electrode of the eighth inverting transistor; T54iD, the second electrode of the ninth inverting transistor; T55iD, the second electrode of the tenth inverting transistor; T43iD, the second electrode of the second reset transistor; T43i1D, the second electrode of the third reset sub-tube; T43i1D, the second electrode of the fourth reset sub-tube; T61iD, the second electrode of the second anti-negative bias transistor; T61i1D, the second electrode of the third anti-negative bias sub-tube; T61i2D, the second electrode of the fourth anti-negative bias sub-tube; C2a, the first plate of the second capacitor; C2a1, the first part of the first plate of the second capacitor; C2a2, the second part of the first plate of the second capacitor; C2b, the second plate of the second capacitor.

[0061] Q2[n], the second pull-up node; QB2[n], the second pull-down node; N2[n], the second internal node; INI[n], the second signal output terminal of the second type gate circuit at this level; INI[n-2], the second signal output terminal of the second type gate circuit at the previous two levels; INI[n+1], the second signal output terminal of the second type gate circuit at the next level; INI[n+2], the second signal output terminal of the second type gate circuit at the next two levels.

[0062] 331. The third pull-up control module; 332. The third pull-up module; 333. The third pull-down module; 334. The third pull-down maintenance module; 335. The third inverter module; 336. The third negative-bias protection module; T11r. The seventh pull-up control transistor; T21r. The fifth pull-up transistor; T31r. The seventh pull-down transistor; T41r. The eighth pull-down transistor; T41r1. The fifth pull-down sub-transistor; T41r2. The sixth pull-down sub-transistor; T42r. The third pull-down maintenance transistor; T42r1. The fifth pull-down maintenance sub-transistor; T42r2. The sixth pull-down maintenance sub-transistor; T51r. The eleventh inverter transistor; T51r1. The fifth inverter sub-transistor; T51r2. The sixth inverter sub-transistor; T52r. The twelfth inverter transistor; T52r1. The seventh inverter sub-transistor; T52r2. The eighth inverter sub-transistor; T53r. The thirteenth inverter transistor; T54r. The fourteenth inverter transistor; T55r. The fifteenth inverter transistor; T56r. The sixteenth inverter transistor; T61r. The third negative-bias protection transistor; T61r1. The fifth negative-bias protection sub-transistor; T61r2. The sixth negative-bias protection sub-transistor; C3. The third capacitor; C4. The fourth capacitor.

[0063] T11rA. The active part of the seventh pull-up control transistor; T21rA. The active part of the fifth pull-up transistor; T31rA. The active part of the seventh pull-down transistor; T41rA. The active part of the eighth pull-down transistor; T41r1A. The active part of the fifth pull-down sub-transistor; T41r2A. The active part of the sixth pull-down sub-transistor; T42rA. The active part of the third pull-down maintenance transistor; T42r1A. The active part of the fifth pull-down maintenance sub-transistor; T42r2A. The active part of the sixth pull-down maintenance sub-transistor; T51rA. The active part of the eleventh inverter transistor; T51r1A. The active part of the fifth inverter sub-transistor; T51r2A. The active part of the sixth inverter sub-transistor; T52rA. The active part of the twelfth inverter transistor; T52r1A. The active part of the seventh inverter sub-transistor; T52r2A. The active part of the eighth inverter sub-transistor; T53rA. The active part of the thirteenth inverter transistor; T54rA. The active part of the fourteenth inverter transistor; T55rA. The active part of the fifteenth inverter transistor; T56rA. The active part of the sixteenth inverter transistor; T61rA. The active part of the third negative-bias protection transistor; T61r1A. The active part of the fifth negative-bias protection sub-transistor; T61r2A. The active part of the sixth negative-bias protection sub-transistor.

[0064] The gate of the seventh pull-up control transistor, T11rG; the gate of the fifth pull-up transistor, T21rG; the gate of the seventh pull-down transistor, T31rG; the gate of the eighth pull-down transistor, T41rG; the gate of the fifth pull-down sub-transistor, T41r1G; the gate of the sixth pull-down sub-transistor, T41r2G; the gate of the third pull-down maintenance transistor, T42rG; the gate of the fifth pull-down maintenance sub-transistor, T42r1G; the gate of the sixth pull-down maintenance sub-transistor, T42r2G; the gate of the eleventh inverter transistor, T51rG; the gate of the fifth inverter sub-transistor, T51r1G; the gate of the sixth inverter sub-transistor, T51r2G; the gate of the twelfth inverter transistor, T52rG; the gate of the seventh inverter sub-transistor, T52r1G; the gate of the eighth inverter sub-transistor, T52r2G; the gate of the thirteenth inverter transistor, T53rG; the gate of the fourteenth inverter transistor, T54rG; the gate of the fifteenth inverter transistor, T55rG; the gate of the sixteenth inverter transistor, T56rG; the gate of the third negative-bias protection transistor, T61rG; the gate of the fifth negative-bias protection sub-transistor, T61r1G; the gate of the sixth negative-bias protection sub-transistor, T61r2G.

[0065] The first electrode of the seventh pull-up control transistor, T11rS; the first electrode of the fifth pull-up transistor, T21rS; the first electrode of the seventh pull-down transistor, T31rS; the first electrode of the eighth pull-down transistor, T41rS; the first electrode of the fifth pull-down sub-transistor, T41r1S; the first electrode of the third pull-down maintenance transistor, T42rS; the first electrode of the fifth pull-down maintenance sub-transistor, T42r1S; the first electrode of the sixth pull-down maintenance sub-transistor, T42r2S; the first electrode of the eleventh inverter transistor, T51rS; the first electrode of the fifth inverter sub-transistor, T51r1S; the first electrode of the twelfth inverter transistor, T52rS; the first electrode of the seventh inverter sub-transistor, T52r1S; the first electrode of the eighth inverter sub-transistor, T52r2S; the first electrode of the thirteenth inverter transistor, T53rS; the first electrode of the fourteenth inverter transistor, T54rS; the first electrode of the fifteenth inverter transistor, T55rS; the first electrode of the sixteenth inverter transistor, T56rS; the first electrode of the third negative-bias protection transistor, T61rS; the first electrode of the sixth negative-bias protection sub-transistor, T61r2S.

[0066] T11rD, the second electrode of the seventh pull-up control transistor; T21rD, the second electrode of the fifth pull-up transistor; T31rD, the second electrode of the seventh pull-down transistor; T41rD, the second electrode of the eighth pull-down transistor; T41r1D, the second electrode of the fifth pull-down sub-transistor; T41r2D, the second electrode of the sixth pull-down sub-transistor; T42rD, the second electrode of the third pull-down maintenance transistor; T42r1D, the second electrode of the fifth pull-down maintenance sub-transistor; T42r2D, the second electrode of the sixth pull-down maintenance sub-transistor; T51rD, the second electrode of the eleventh inverter transistor; T51r1D, the second electrode of the fifth inverter sub-transistor; T51r2D, the second electrode of the sixth inverter sub-transistor; T52rD, the second electrode of the twelfth inverter transistor; T52r1D, the second electrode of the seventh inverter sub-transistor; T52r2D, the second electrode of the eighth inverter sub-transistor; T53rD, the second electrode of the thirteenth inverter transistor; T54rD, the second electrode of the fourteenth inverter transistor; T56rD, the second electrode of the sixteenth inverter transistor; T61rD, the second electrode of the third negative-bias protection transistor; T61r1D, the second electrode of the fifth negative-bias protection sub-transistor; T61r2D, the second electrode of the sixth negative-bias protection sub-transistor; C3a, the first plate of the third capacitor; C3a1, the first part of the first plate of the third capacitor; C3a2, the second part of the first plate of the third capacitor; C3b, the second plate of the third capacitor; C4a, the first plate of the fourth capacitor; C4b, the second plate of the fourth capacitor.

[0067] Q3[n], the third pull-up node; QB3[n], the third pull-down node; N3[n], the third internal node; REF[n], the third signal output terminal of the third type of gate circuit of this stage.

[0068] X, the first direction; Y, the second direction. Detailed implementation manners

[0069] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

[0070] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "installation", "connection", "connection", and "electrical connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a connection that can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0071] In order to illustrate the principle of the technical problems in the embodiments of the present application, some comparative display devices are provided. It can be understood that these comparative display devices cannot be regarded as the prior art in the embodiments of the present application. As Figure 1 shown, the comparative display device 1 includes a pixel circuit 11 and a gate circuit 12. The gate circuit 12 is respectively provided with a wiring area 121 and a transistor area 122. A signal wiring 121a is arranged in the wiring area 121, and a thin-film transistor 122a is arranged in the transistor area 122. By extending the signal wiring 121a from the wiring area 121 into the transistor area 122 and connecting it to the corresponding transistor 122a, the normal operation of the gate circuit 12 is realized. However, from Figure 1 it can be seen that since the wiring area 121 and the transistor area 122 are separately arranged, the wiring area 121 needs to occupy a large space, and when the signal wiring 121a extends into the transistor area 122, each transistor needs to occupy more space in order to avoid the unconnected signal wiring 121a, resulting in a large space occupied by the gate circuit 12. Therefore, the current display device has the technical problem that the lateral space occupied by the thin-film transistor setting area and the signal wiring area in the gate driving circuit is large, resulting in a large border of the display device.

[0072] The embodiments of the present application provide a display panel 2 and a display device to solve the above technical problems.

[0073] Based on the problem that the wiring area and the transistor area in the comparative display device need to be separately arranged, resulting in both the wiring area and the transistor area occupying a large space, the embodiments of the present application adjust aspects such as the setting position of the signal line, the setting film layer of the signal line, and the arrangement mode of the signal lines, and / or adjust aspects such as the setting position of the transistor, the arrangement mode of the transistors, and the design of the transistor structure, so as to reduce the occupied space of the gate driving circuit 22 and reduce the border of the display panel 2.

[0074] Figure 1 It is a schematic diagram of the comparative display device. Figure 2 It is a plan schematic diagram of the display panel provided by the embodiment of the present application. Figure 3Schematic cross-sectional view of the display panel provided by the embodiment of the present application. Figure 4 Circuit diagram of the pixel driving circuit provided by the embodiment of the present application. Figure 5 Circuit diagram of the first type of gate circuit provided by the embodiment of the present application. Figure 6 Circuit diagram of the second type of gate circuit provided by the embodiment of the present application. Figure 7 Circuit diagram of the third type of gate circuit provided by the embodiment of the present application. Figure 8 Stacked diagram of the light-shielding layer, active layer, gate layer, and first source-drain layer of the display panel provided by the embodiment of the present application. Fig. 9 For Figure 8 Exploded view of the light-shielding layer of the display panel in Fig.10 For Figure 8 Exploded view of the active layer of the display panel in Fig.11 For Figure 8 Exploded view of the gate layer of the display panel in Fig.12 For Figure 8 Exploded view of the first source-drain layer of the display panel in Fig.13 For Figure 8 Stacked diagram of the light-shielding layer and active layer of the display panel in Fig.14 For Figure 8 Stacked diagram of the light-shielding layer, active layer, and gate layer of the display panel in Fig.15 For Figure 8 Stacked diagram of the light-shielding layer and the first via hole of the display panel in Fig.16 For Figure 8 Stacked diagram of the light-shielding layer and the first source-drain layer in Fig.17 For Figure 8 Stacked diagram of the gate layer and the second via hole of the display panel in Fig.18 For Figure 8 Stacked diagram of the gate layer and the first source-drain layer of the display panel in Fig.19 For Figure 8 Partial enlarged view of the area corresponding to the first type of gate circuit of the display panel in Fig. 20 For Fig.19 Exploded view of the light-shielding layer of the display panel in Fig.21 For Fig.19 Exploded view of the active layer of the display panel in Fig. 22 For Fig.19 Exploded view of the gate layer of the display panel in Fig.23 For Fig.19 Exploded view of the first source-drain layer of the display panel in Fig.24 For Figure 8 Partial enlarged view of the area corresponding to the second type of gate circuit of the display panel in

[0075] Fig.25 For Fig.24 Exploded view of the light-shielding layer of the display panel in Fig.26 is Fig.24 an exploded view of the active layer of the display panel in Fig. 27 is Fig.24 an exploded view of the gate layer of the display panel in Fig.28 is Fig.24 an exploded view of the first source-drain layer of the display panel in Fig.29 is Figure 8 a partially enlarged view of the corresponding region of the third type of gate circuit in the display panel in Fig.30 is Fig.29 an exploded view of the light-shielding layer of the display panel in Fig.31 is Fig.29 an exploded view of the active layer of the display panel in Fig.32 is Fig.29 an exploded view of the gate layer of the display panel in Fig.33 is Fig.29 an exploded view of the first source-drain layer of the display panel in

[0076] As Figure 2 shown, an embodiment of the present application provides a display panel 2, which includes a display area 201 and a non-display area 202. A plurality of pixels 23 are provided in the display area 201. The pixel 23 includes a light-emitting device LED and a pixel driving circuit 21 for driving the light-emitting device LED. A multi-stage gate driving circuit 22 is provided in the non-display area 202. The multi-stage gate driving circuit 22 can be arranged along the second direction Y. The gate driving circuit 22 outputs a scanning signal to the pixel driving circuit 21.

[0077] Specifically, as Figure 2 shown, the non-display area 202 can be arranged to surround the display area 201, but the embodiment of the present application is not limited thereto. The non-display area 202 can be arranged on one side, two sides or three sides of the display area 201, and the non-display area 202 can be bent to the back of the display area 201. The non-display area 202 can include an upper border area, a lower border area, a left border area and a right border area. The gate driving circuit 22 can be arranged in the left border area and / or the right border area. The gate driving circuit 22 can be arranged along the first direction X on one side or both sides of the display area 201.

[0078] As Figure 3As shown in the figure, as a specific structure of a display panel 2 in an embodiment of the present application, the display panel 2 includes a substrate 211, a light-shielding layer 212, a buffer layer 213, a semiconductor layer 214, a first gate insulating layer 215, an active layer 216, a second gate insulating layer 217, a gate layer 218, a first interlayer insulating layer 219, a first source-drain layer 221, a second interlayer insulating layer 222, a second source-drain layer 223, a passivation layer 224, a third source-drain layer 225, a first planarization layer 226, a second planarization layer 227, a pixel electrode layer 228, a first pixel definition layer 229, and a second pixel definition layer 231, which are arranged in sequence.

[0079] Specifically, the material of the semiconductor layer 214 includes an oxide semiconductor, specifically a metal oxide, and more specifically indium gallium zinc oxide.

[0080] Specifically, the material of the active layer 216 includes a silicon semiconductor material, specifically low-temperature polycrystalline silicon.

[0081] Specifically, as Figure 3 shown, Figure 3 it is shown in the figure that the display panel 2 includes a semiconductor layer 214 and an active layer 216, but the embodiment of the present application is not limited thereto. The display panel 2 may include only one of the semiconductor layer 214 and the active layer 216.

[0082] Specifically, as Figure 3 shown, Figure 3 it is shown in the figure that the display panel 2 includes a first source-drain layer 221, a second source-drain layer 223, and a third source-drain layer 225, but the embodiment of the present application is not limited thereto. The display panel 2 may include only one or two of the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225.

[0083] Specifically, as Figure 3 shown, Figure 3 it is shown in the figure that the light-shielding layer 212 is only disposed in the display area 201, but the embodiment of the present application is not limited thereto. The light-shielding layer 212 may be disposed in the non-display area 202.

[0084] Specifically, as Figure 3 shown, Figure 3 it is shown in the figure that the transistors in the display area 201 all use the semiconductor layer 214 as the active part, and the transistors in the non-display area 202 all use the active layer 216 as the active part, but the embodiment of the present application is not limited thereto. Some transistors in the display area 201 may use the semiconductor layer 214 as the active part, and some transistors in the display area 201 may use the active layer 216 as the active part. Similarly, some transistors in the non-display area 202 may use the semiconductor layer 214 as the active part, and some transistors in the non-display area 202 may use the active layer 216 as the active part.

[0085] Specifically, as Figure 3 shown, Figure 3 in which the display panel 2 is taken as an organic light-emitting diode display panel 2 as an example for illustration, but the embodiments of the present application are not limited thereto. The display panel 2 may be a liquid crystal display panel 2 or other types of display panels 2.

[0086] Specifically, as Figures 5 to 7 shown, each stage of the gate driving circuit 22 includes a first type of gate circuit 22a, a second type of gate circuit 22b, and a third type of gate circuit 22c arranged along the first direction.

[0087] As Figures 2 to 33 shown, the embodiments of the present application provide a display panel 2, which includes multiple rows of pixels 23 and multiple stages of gate driving circuits 22. The pixels 23 include light-emitting devices LED and pixel driving circuits 21. The multiple stages of gate driving circuits 22 are electrically connected to the corresponding pixel driving circuits 21 respectively. Each stage of the gate driving circuit 22 includes a first type of gate circuit 22a, a second type of gate circuit 22b, and a third type of gate circuit 22c. The first type of gate circuit 22a is electrically connected to at least a first clock signal line CKA, a second clock signal line CKB, a first high-potential signal line VGH1, a first low-potential signal line VGL1, a second low-potential signal line VGL2, a first reset control line VST1, and a low-frequency signal line LC. The second type of gate circuit 22b is electrically connected to at least the first high-potential signal line VGH1, the second low-potential signal line VGL2, a third clock signal line CKC of the display panel, and a second reset control line VST2 of the display panel. The third type of gate circuit 22c is electrically connected to at least the first high-potential signal line VGH1, a second high-potential signal line VGH2, the second low-potential signal line VGL2, and a third low-potential signal line VGL3.

[0088] Among them, the first reset control line VST1, the first type of gate circuit 22a, the second type of gate circuit 22b, the third type of gate circuit 22c, and the third low-potential signal line VGL3 are arranged along the first direction. In the first direction, at least one of the first clock signal line CKA, the second clock signal line CKB, the third clock signal line CKC, the first high-potential signal line VGH1, the second high-potential signal line VGH2, the first low-potential signal line VGL1, the second low-potential signal line VGL2, the second reset control line VST2, and the low-frequency signal line LC is arranged between the first reset control line VST1 and the third low-potential signal line VGL3.

[0089] An embodiment of the present application provides a display panel 2. By arranging at least one of the first clock signal line CKA, the second clock signal line CKB, the third clock signal line CKC, the first high potential signal line VGH1, the second high potential signal line VGH2, the first low potential signal line VGL1, the second low potential signal line VGL2, the second reset control line VST2, and the low frequency signal line LC between the first reset control line VST1 and the third low potential signal line VGL3 in a first direction, the signal lines arranged between the first reset control line VST1 and the third low potential signal line VGL3 can be directly connected to corresponding transistors, without occupying the space of the routing area of the gate driving circuit 22 to arrange signal lines, and the space of the transistor area of the gate driving circuit 22 occupied can be reduced, the space occupied by the gate driving circuit 22 can be reduced, and the border of the display panel 2 can be reduced.

[0090] In some embodiments, as Figures 8 to 18 shown, in the first direction, at least one of the first clock signal line CKA, the second clock signal line CKB, and the third clock signal line CKC is arranged between the first reset control line VST1 and the third low potential signal line VGL3. By arranging at least one of the first clock signal line CKA, the second clock signal line CKB, and the third clock signal line CKC between the first reset control line VST1 and the third low potential signal line VGL3, the connection line between at least one of the first clock signal line CKA, the second clock signal line CKB, and the third clock signal line CKC and the corresponding transistor can be shortened, and the space outside the transistor area of the gate driving circuit 22 does not need to be occupied, the lateral space occupied by at least one clock signal line can be reduced, the lateral space occupied by the gate driving circuit 22 can be reduced, and the border of the display panel 2 can be reduced.

[0091] Specifically, it can be understood that each clock signal line in the display panel 2 will include multiple clock lines. Arranging the multiple clock lines outside the transistor area and connecting them to the transistors by extending into the transistor area will occupy a large amount of space, resulting in a large lateral occupied space of the gate driving circuit 22 and a large border of the display panel 2. By arranging at least one of the first clock signal line CKA, the second clock signal line CKB, and the third clock signal line CKC between the first reset control line VST1 and the third low potential signal line VGL3 in the embodiment of the present application, the space occupied by the clock signal lines can be reduced, and the border of the display panel 2 can be reduced.

[0092] Specifically, the first clock signal line CKA can be arranged between the first reset control line VST1 and the third low potential signal line VGL3.

[0093] Specifically, the second clock signal line CKB can be disposed between the first reset control line VST1 and the third low potential signal line VGL3.

[0094] Specifically, the third clock signal line CKC can be disposed between the first reset control line VST1 and the third low potential signal line VGL3.

[0095] In some embodiments, as Figures 8 to 18 shown, in the first direction, the first clock signal line CKA and the second clock signal line CKB are disposed between the first reset control line VST1 and the third low potential signal line VGL3. By disposing the first clock signal line CKA and the second clock signal line CKB between the first reset control line VST1 and the third low potential signal line VGL3, the lateral space occupied by the first clock signal line CKA and the second clock signal line CKB can be reduced, thereby reducing the border of the display panel 2.

[0096] Specifically, both the first clock signal line CKA and the second clock signal line CKB will include multiple clock lines. Disposing the first clock signal line CKA and the second clock signal line CKB between the first reset control line VST1 and the third low potential signal line VGL3 can reduce the lateral space occupied by the gate driving circuit 22 and reduce the border of the display panel 2.

[0097] In some embodiments, as Figures 8 to 18 shown, in the first direction, the first clock signal line CKA and the second clock signal line CKB are disposed between the first reset control line VST1 and the second type of gate circuit 22b. By disposing the first clock signal line CKA and the second clock signal line CKB between the first reset control line VST1 and the second type of gate circuit 22b, the first clock signal line CKA and the second clock signal line CKB are closer to the transistors they are connected to, and the connection lines of each clock line are relatively short or even do not require connection lines, thereby further reducing the space occupied by the first clock signal line CKA and the second clock signal line CKB and reducing the border of the display panel 2.

[0098] Specifically, the first clock signal line CKA is connected to the transistors in the first type of gate circuit 22a, and the second clock signal line CKB is connected to the transistors in the second type of gate circuit 22b. Then, the first clock signal line CKA and the second clock signal line CKB can be arranged between the first reset control line VST1 and the second type of gate circuit 22b, so that the first clock signal line CKA and the second clock signal line CKB are closer to the transistors they are connected to, and the connection lines of each clock line are relatively short. Thus, the space occupied by the first clock signal line CKA and the second clock signal line CKB can be further reduced, and the border of the display panel 2 can be reduced.

[0099] In some embodiments, such as Figure 5 , Figures 8 to 18 , Figures 19 to 23 shown, the first type of gate circuit 22a includes a first pull-up control module 311 and a first pull-up module 312. The first pull-up control module 311 and the first pull-up module 312 are electrically connected to a first pull-up node Q1[n]. The second clock signal line CKB includes a first group of sub-lines CKBi and a second group of sub-lines CKBj. The first pull-up module 312 includes a first pull-up transistor T21j, a second pull-up transistor T22j, and a third pull-up transistor T23j. One electrode of the first pull-up transistor T21j is electrically connected to the first clock signal line CKA; one electrode of the second pull-up transistor T22j is electrically connected to the first group of sub-lines CKBi; one electrode of the third pull-up transistor T23j is electrically connected to the second group of sub-lines CKBj;

[0100] wherein, the first pull-up transistor T21j, the second pull-up transistor T22j, and the third pull-up transistor T23j are arranged in sequence along a first direction. In the first direction, the first clock signal line CKA is arranged between the first pull-up control module 311 and the first pull-up transistor T21j, the first group of sub-lines CKBi is arranged between the first pull-up transistor T21j and the second pull-up transistor T22j, and the second group of sub-lines CKBj is arranged between the second pull-up transistor T22j and the third pull-up transistor T23j. By arranging the first clock signal line CKA between the first pull-up control module 311 and the first pull-up transistor T21j, the first group of sub-lines CKBi between the first pull-up transistor T21j and the second pull-up transistor T22j, and the second group of sub-lines CKBj between the second pull-up transistor T22j and the third pull-up transistor T23j, each clock signal line is adjacent to the transistor it is connected to. Thus, the length of the connection line between each clock signal line and the transistor it is connected to can be shortened or even the connection line can be eliminated, the space occupied by each clock signal line can be reduced, and the border of the display panel 2 can be reduced.

[0101] In some embodiments, as Figures 8 to 18 shown, in the first direction, the third clock signal line CKC is disposed between the first reset control line VST1 and the third low potential signal line VGL3. By disposing the third clock signal line CKC between the first reset control line VST1 and the third low potential signal line VGL3, the third clock signal line CKC can be closer to the transistors connected thereto, and the connection lines of the third clock signal line CKC are relatively short or even do not require connection lines, thereby further reducing the space occupied by the third clock signal line CKC and reducing the border of the display panel 2.

[0102] In some embodiments, as Figures 8 to 18 shown, in the first direction, the third clock signal line CKC is disposed between the first type of gate circuit 22a and the third type of gate circuit 22c. By disposing the third clock signal line CKC between the first type of gate circuit 22a and the third type of gate circuit 22c, the third clock signal line CKC can be closer to the transistors connected thereto, and the connection lines of each clock line are relatively short or even do not require connection lines, thereby further reducing the space occupied by the third clock signal line CKC and reducing the border of the display panel 2.

[0103] Specifically, the third clock signal line CKC is connected to the transistors in the second type of gate circuit 22b, so that the third clock signal line CKC can be disposed between the first type of gate circuit 22a and the third type of gate circuit 22c, making the third clock signal line CKC closer to the transistors connected thereto, and the connection lines of each clock line are relatively short, thereby further reducing the space occupied by the third clock signal line CKC and reducing the border of the display panel 2.

[0104] In some embodiments, as Figure 6 、 Figures 8 to 18 、 Figures 24 to 28 shown, the second type of gate circuit 22b includes a second pull-up control module 321 and a second pull-up module 322. The second pull-up control module 321 and the second pull-up module 322 are electrically connected to a second pull-up node Q2[n], and the second pull-up module 322 is electrically connected to the third clock signal line CKC;

[0105] Among them, in the first direction, the third clock signal line CKC is disposed between the second pull-up control module 321 and the second pull-up module 322. By disposing the third clock signal line CKC between the second pull-up control module 321 and the second pull-up module 322, the third clock signal line CKC is adjacent to the transistor connected thereto, so that the length of the connection line between the third clock signal line CKC and the transistor connected thereto can be shortened or even the connection line can be eliminated, the space occupied by the third clock signal line CKC is reduced, and the border of the display panel 2 is reduced.

[0106] Specifically, the second pull-up module 322 includes a fourth pull-up transistor T21i. One electrode of the fourth pull-up transistor T21i is electrically connected to the third clock signal line CKC. The third clock signal line CKC is disposed between the fourth pull-up transistor T21i and the second pull-up control module 321 in the first direction.

[0107] In some embodiments, in the first direction, the first high potential signal line VGH1 is disposed between the first reset control line VST1 and the third low potential signal line VGL3. By disposing the first high potential signal line VGH1 between the first reset control line VST1 and the third low potential signal line VGL3, the first high potential signal line VGH1 is relatively close to the transistor connected thereto, and the connection line of the first high potential signal line VGH1 is relatively short or even no connection line is required, so that the space occupied by the first high potential signal line VGH1 can be further reduced, and the border of the display panel 2 is reduced. In some embodiments, as Figure 5 、 Figures 8 to 18 、 Figures 19 to 23 shown, the first type of gate circuit 22a includes a first pull-up control module 311, and the first pull-up control module 311 is electrically connected to the first high potential signal line VGH1;

[0108] Among them, in the first direction, the first high potential signal line VGH1 is disposed between the first reset control line VST1 and the first pull-up control module 311. By disposing the first high potential signal line VGH1 between the first reset control line VST1 and the first pull-up control module 311, the first high potential signal line VGH1 is adjacent to the transistor connected thereto, so that the length of the connection line between the first high potential signal line VGH1 and the transistor connected thereto can be shortened or even the connection line can be eliminated, the space occupied by the first high potential signal line VGH1 is reduced, and the border of the display panel 2 is reduced.

[0109] Specifically, for the case where the first high-potential signal line VGH1 is connected to the second type of gate circuit 22b and the third type of gate circuit 22c, the connection between each transistor and the first high-potential signal line VGH1 can be achieved by arranging connection lines on the upper side of each stage of gate driving circuit 22 or within each stage of gate driving circuit 22.

[0110] Specifically, the first pull-up control module 311 includes a first pull-up control transistor T11j. One electrode of the first pull-up control transistor T11j is electrically connected to the first high-potential signal line VGH1. The first high-potential signal line VGH1 is arranged between the first pull-up control transistor T11j and the first reset control line VST1 in the first direction.

[0111] In some embodiments, as Figures 8 to 18 shown, in the first direction, the second high-potential signal line VGH2 is arranged between the first reset control line VST1 and the third low-potential signal line VGL3. By arranging the second high-potential signal line VGH2 between the first reset control line VST1 and the third low-potential signal line VGL3, the second high-potential signal line VGH2 is closer to the transistors connected thereto, and the connection line of the second high-potential signal line VGH2 is relatively short or even no connection line is required, thereby further reducing the space occupied by the second high-potential signal line VGH2 and reducing the border of the display panel 2.

[0112] In some embodiments, as Figure 7 、 Figures 8 to 18 、 Figure 29 to Figure 33 shown, the third type of gate circuit 22c includes a third pull-up control module 331 and a third pull-up module 332. The third pull-up control module 331 and the third pull-up module 332 are electrically connected to a third pull-up node Q3[n]. The third pull-up module 332 is electrically connected to the second high-potential signal line VGH2;

[0113] Among them, in the first direction, the second high-potential signal line VGH2 is arranged between the third pull-up control module 331 and the third pull-up module 332. By arranging the second high-potential signal line VGH2 between the third pull-up control module 331 and the third pull-up module 332, the second high-potential signal line VGH2 and the transistors connected thereto are arranged adjacent to each other, thereby shortening the length of the connection line between the second high-potential signal line VGH2 and the transistors connected thereto or even eliminating the connection line, reducing the space occupied by the second high-potential signal line VGH2, and reducing the border of the display panel 2.

[0114] Specifically, the third pull-up module 332 includes a fifth pull-up transistor T21r. One electrode of the fifth pull-up transistor T21r is electrically connected to the second high-potential signal line VGH2. The second high-potential signal line VGH2 is disposed between the third pull-up control module 331 and the fifth pull-up transistor T21r along the first direction.

[0115] Specifically, the second high-potential signal line VGH2 is disposed between the second low-potential signal line VGL2 and the fifth pull-up transistor T21r along the first direction.

[0116] In some embodiments, as Figures 8 to 18 shown, in the first direction, the first low-potential signal line VGL1 is disposed between the first reset control line VST1 and the third low-potential signal line VGL3. By disposing the first low-potential signal line VGL1 between the first reset control line VST1 and the third low-potential signal line VGL3, the first low-potential signal line VGL1 is closer to the transistor connected thereto, and the connection line of the first low-potential signal line VGL1 is relatively short or even does not require a connection line, thereby further reducing the space occupied by the first low-potential signal line VGL1 and reducing the border of the display panel 2.

[0117] In some embodiments, as Figure 5 、 Figures 8 to 18 、 Figures 19 to 23 shown, the first type of gate circuit 22a includes a first pull-down maintenance module 314. The first pull-down maintenance module 314 is electrically connected to the first low-potential signal line VGL1;

[0118] Wherein, in the first direction, the first low-potential signal line VGL1 is disposed between the first pull-down maintenance module 314 and the second type of gate circuit 22b. By disposing the first low-potential signal line VGL1 between the first pull-down maintenance module 314 and the second type of gate circuit 22b, the first low-potential signal line VGL1 is adjacent to the transistor connected thereto, thereby shortening the connection line length between the first low-potential signal line VGL1 and the transistor connected thereto or even eliminating the connection line, reducing the space occupied by the first low-potential signal line VGL1, and reducing the border of the display panel 2.

[0119] Specifically, for the case where the first low-potential signal line VGL1 is connected to other modules, the connection between each transistor and the first low-potential signal line VGL1 can be achieved by disposing a connection line above each stage of the gate driving circuit 22 or within each stage of the gate driving circuit 22.

[0120] Specifically, the first pull-down maintenance module 314 includes a first pull-down maintenance transistor T42j. One electrode of the first pull-down maintenance transistor T42j is electrically connected to the first low potential signal line VGL1. The first low potential signal line VGL1 is arranged in the first direction between the first pull-down maintenance transistor T42j and the second type of gate circuit 22b.

[0121] Specifically, the first low potential signal line VGL1 is arranged in the first direction between the first pull-down maintenance transistor T42j and the first clock signal line CKA.

[0122] In some embodiments, as Figures 8 to 18 shown, in the first direction X, the second low potential signal line VGL2 is arranged between the first reset control line VST1 and the third low potential signal line VGL3. By arranging the second low potential signal line VGL2 between the first reset control line VST1 and the third low potential signal line VGL3, the second low potential signal line VGL2 is closer to the transistor it is connected to, and the connection line of the second low potential signal line VGL2 is relatively short or even does not require a connection line, so that the space occupied by the second low potential signal line VGL2 can be further reduced, and the border of the display panel 2 can be reduced.

[0123] In some embodiments, as Figures 8 to 18 shown, in the first direction X, the second low potential signal line VGL2 is arranged between the second type of gate circuit 22b and the third low potential signal line VGL3. By arranging the second low potential signal line VGL2 between the second type of gate circuit 22b and the third low potential signal line VGL3, the distance between the second low potential signal line VGL2 and the transistor it is connected to can be further shortened, and the connection line of the second low potential signal line VGL2 is relatively short or even does not require a connection line, so that the space occupied by the second low potential signal line VGL2 can be further reduced, and the border of the display panel 2 can be reduced.

[0124] In some embodiments, as Figure 7 、 Figures 8 to 18 、 Figure 29 to Figure 33 shown, the third type of gate circuit 22c includes a third pull-down maintenance module 334. The third pull-down maintenance module 334 is electrically connected to the second low potential signal line VGL2;

[0125] Among them, in the first direction, the second low potential signal line VGL2 is disposed between the third pull-down maintenance module 334 and the third low potential signal line VGL3. By disposing the second low potential signal line VGL2 between the third pull-down maintenance module 334 and the third low potential signal line VGL3, the second low potential signal line VGL2 is disposed adjacent to the transistor connected thereto, so that the length of the connection line between the second low potential signal line VGL2 and the transistor connected thereto can be shortened or even the connection line can be eliminated, the space occupied by the second low potential signal line VGL2 can be reduced, and the border of the display panel 2 can be reduced.

[0126] Specifically, for the case where the second low potential signal line VGL2 is connected to the first type of gate circuit 22a and the second type of gate circuit 22b, the connection between each transistor and the second low potential signal line VGL2 can be realized by disposing a connection line on the upper side of each stage of the gate driving circuit 22 or within each stage of the gate driving circuit 22.

[0127] Specifically, the third pull-down maintenance module 334 includes a third pull-down maintenance transistor T42r. One electrode of the third pull-down maintenance transistor T42r is electrically connected to the second low potential signal line VGL2. The second low potential signal line VGL2 is disposed between the third pull-down maintenance transistor T42r and the third low potential signal line VGL3 in the first direction.

[0128] Specifically, the second low potential signal line VGL2 is disposed between the third pull-down maintenance transistor T42r and the second high potential signal line VGH2 in the first direction.

[0129] In some embodiments, as Figures 8 to 18 shown, in the first direction, the second reset control line VST2 is disposed between the first reset control line VST1 and the third low potential signal line VGL3. By disposing the second reset control line VST2 between the first reset control line VST1 and the third low potential signal line VGL3, the second reset control line VST2 is closer to the transistor connected thereto, and the connection line of the second reset control line VST2 is relatively short or even no connection line is required, so that the space occupied by the second reset control line VST2 can be further reduced, and the border of the display panel 2 can be reduced.

[0130] In some embodiments, as Figures 8 to 18As shown, in the first direction, the second reset control line VST2 is disposed between the first type of gate circuit 22a and the third type of gate circuit 22c. By disposing the second reset control line VST2 between the first type of gate circuit 22a and the third type of gate circuit 22c, the distance between the second reset control line VST2 and the transistors connected thereto can be further shortened, and the connection lines of the second reset control line VST2 are relatively short or even no connection lines are needed, so that the space occupied by the second reset control line VST2 can be further reduced, and the border of the display panel 2 can be reduced.

[0131] In some embodiments, as Figure 6 , Figures 8 to 18 , Figures 24 to 28 shown, the second type of gate circuit 22b includes a second reset module 327, and the second reset module 327 is electrically connected to the second reset control line VST2;

[0132] Among them, in the first direction, the second reset control line VST2 is disposed between the second reset module 327 and the first type of gate circuit 22a. By disposing the second reset control line VST2 between the second reset module 327 and the first type of gate circuit 22a, the second reset control line VST2 and the transistors connected thereto are adjacent to each other, so that the length of the connection line between the second reset control line VST2 and the transistors connected thereto can be shortened or even the connection line can be eliminated, the space occupied by the second reset control line VST2 can be reduced, and the border of the display panel 2 can be reduced.

[0133] Specifically, the second reset module 327 includes a second reset transistor T43i, and the gate T43iG of the second reset transistor T43i is electrically connected to the second reset control line VST2, and the second reset control line VST2 is disposed between the second reset transistor T43i and the first type of gate circuit 22a along the first direction.

[0134] Specifically, the second reset control line VST2 is disposed between the second reset transistor T43i and the third pull-up transistor T23j along the first direction.

[0135] In some embodiments, as Figures 8 to 18 shown, in the first direction X, the low-frequency signal line LC is disposed between the first reset control line VST1 and the third low-potential signal line VGL3. By disposing the low-frequency signal line LC between the first reset control line VST1 and the third low-potential signal line VGL3, the low-frequency signal line LC is relatively close to the transistors connected thereto, and the connection lines of the low-frequency signal line LC are relatively short or even no connection lines are needed, so that the space occupied by the low-frequency signal line LC can be further reduced, and the border of the display panel 2 can be reduced.

[0136] In some embodiments, as Figures 8 to 18 shown, in the first direction, the low-frequency signal line LC is disposed between the first reset control line VST1 and the second type of gate circuit 22b. By disposing the low-frequency signal line LC between the first reset control line VST1 and the second type of gate circuit 22b, the distance between the low-frequency signal line LC and the transistor connected thereto can be further shortened, and the connection line of the low-frequency signal line LC is relatively short or even no connection line is required, so that the space occupied by the low-frequency signal line LC can be further reduced, and the border of the display panel 2 can be reduced.

[0137] In some embodiments, as Figure 5 , Figures 8 to 18 , Figures 19 to 23 shown, the first type of gate circuit 22a includes a first inverting module 315, and the first inverting module 315 is electrically connected to the low-frequency signal line LC;

[0138] Wherein, in the first direction, the low-frequency signal line LC is disposed between the first inverting module 315 and the second type of gate circuit 22b. By disposing the low-frequency signal line LC between the first inverting module 315 and the second type of gate circuit 22b, the low-frequency signal line LC and the transistor connected thereto are adjacently arranged, so that the length of the connection line between the low-frequency signal line LC and the transistor connected thereto can be shortened or even the connection line can be eliminated, the space occupied by the low-frequency signal line LC can be reduced, and the border of the display panel 2 can be reduced.

[0139] Specifically, for the case where the low-frequency signal line LC is connected to the second type of gate circuit 22b, the connection between each transistor and the low-frequency signal line LC can be realized by disposing a connection line on the upper side of each stage of gate driving circuit 22 or inside each stage of gate driving circuit 22.

[0140] Specifically, the first inverting module 315 includes a first inverting transistor T51j. One electrode of the first inverting transistor T51j is electrically connected to the low-frequency signal line LC, and the low-frequency signal line LC is disposed between the first inverting transistor T51j and the second type of gate circuit 22b along the first direction.

[0141] Specifically, the low-frequency signal line LC is disposed between the first low potential signal line VGL1 and the first clock signal line CKA along the first direction.

[0142] In some embodiments, as Figures 2 to 33As shown, the first type of gate circuit 22a includes a first pull-up control module 311 and a first pull-up module 312 that are electrically connected. The first pull-up module 312 includes a first pull-up transistor T21j, a second pull-up transistor T22j, and a third pull-up transistor T23j. The second type of gate circuit 22b includes a second pull-up control module 321 and a second pull-up module 322 that are electrically connected. The third type of gate circuit 22c includes a third pull-up control module 331 and a third pull-up module 332 that are electrically connected. The second clock signal line CKB includes a first group of sub-lines CKBi and a second group of sub-lines CKBj.

[0143] Wherein, in the first direction, the first reset control line VST1, the first high potential signal line VGH1, the first pull-up control module 311, the first low potential signal line VGL1, the low-frequency signal line LC, the first clock signal line CKA, the first pull-up transistor T21j, the first group of sub-lines CKBi, the second pull-up transistor T22j, the second group of sub-lines CKBj, the third pull-up transistor T23j, the second reset control line VST2, the second pull-up control module 321, the third clock signal line CKC, the second pull-up module 322, the third pull-up control module 331, the second low potential signal line VGL2, the second high potential signal line VGH2, the third pull-up module 332, and the third low potential signal line VGL3 are arranged in sequence. This enables each signal line to be close to the corresponding transistor, reducing the length of the connection lines of each signal line or even eliminating the connection lines of each signal line, reducing the lateral space occupied by the gate driving circuit 22, and reducing the border of the display panel 2.

[0144] In some embodiments, as Figures 2 to 33 shown, the display panel 2 further includes a substrate 211, a light-shielding layer 212, a gate layer 218, and a first source-drain layer 221. The light-shielding layer 212 is disposed on one side of the substrate 211. The gate layer 218 is disposed on a side of the light-shielding layer 212 away from the substrate 211. The first source-drain layer 221 is disposed on a side of the gate layer 218 away from the light-shielding layer 212.

[0145] Among them, the display panel 2 includes a multi-stage gate driving circuit 22, and at least one of the first clock signal line CKA, the second clock signal line CKB, the third clock signal line CKC, the first high potential signal line VGH1, the second high potential signal line VGH2, the first low potential signal line VGL1, the second low potential signal line VGL2, the third low potential signal line VGL3, the first reset control line VST1, the second reset control line VST2, and the low-frequency signal line LC includes a first part, a second part, and a third part. The first part is disposed on the light-shielding layer 212, the second part is disposed on the gate layer 218, the third part is disposed on the first source-drain layer, and the first part, the second part, and the third part all extend in the second direction;

[0146] The first parts in each stage of the gate driving circuit 22 are continuous, the second parts in each stage of the gate driving circuit 22 are discontinuously arranged, the third parts in each stage of the gate driving circuit 22 are discontinuously arranged, the first part is connected to the third part, and the second part is connected to the third part;

[0147] The included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. By forming the first part, the second part, and the third part by using the light-shielding layer 212, the gate layer 218, and the first source-drain layer 221 respectively, the impedance of each signal line can be made smaller, and each signal line can be cross-wired and connected through parts of different layers, so that each signal line can be connected to the corresponding transistor and occupies less space.

[0148] Specifically, as Fig. 9 shown, in the first direction, the first part VST1a of the first reset control line VST1, the first part VGH1a of the first high potential signal line VGH1, the first part VGL1a of the first low potential signal line VGL1, the first part LCa of the low-frequency signal line LC, the first part CKAa of the first clock signal line CKA, the first part CKBia of the first group of sub-lines CKBi, the first part CKBja of the second group of sub-lines CKBj, the first part VST2a of the second reset control line VST2, the first part CKCa of the third clock signal line CKC, the second low potential signal line VGL2, the second high potential signal line VGH2, and the third low potential signal line VGL3 are arranged in sequence.

[0149] Specifically, as Fig.10 shown, it can be seen that in the first direction, the active parts of the transistors in the first type of gate circuit 22a, the active parts of the transistors in the second type of gate circuit 22b, and the active parts of the transistors in the third type of gate circuit 22c are arranged in sequence. Fig.10 The active portions of the transistors in the first type of gate circuit 22a, the active portions of the transistors in the second type of gate circuit 22b, and the active portions of the transistors in the third type of gate circuit 22c are respectively identified by reference numerals 216a, 216b, and 216c.

[0150] Specifically, as Fig.11 shown, in the first direction, the second portion VST1b of the first reset control line VST1, the second portion VGH1b of the first high potential signal line VGH1, the second portion VGL1b of the first low potential signal line VGL1, the second portion LCb of the low frequency signal line LC, the second portion CKAb of the first clock signal line CKA, the second portion CKBib of the first group of sub-lines CKBi, the second portion CKBjb of the second group of sub-lines CKBj, the second portion VST2b of the second reset control line VST2, the second portion CKCb of the third clock signal line CKC, the second low potential signal line VGL2, the second high potential signal line VGH2, and the third low potential signal line VGL3 are arranged in sequence.

[0151] Specifically, as Fig.12 shown, in the first direction, the third portion VST1c of the first reset control line VST1, the third portion VGH1c of the first high potential signal line VGH1, the third portion VGL1c of the first low potential signal line VGL1, the third portion LCc of the low frequency signal line LC, the third portion CKAc of the first clock signal line CKA, the third portion CKBic of the first group of sub-lines CKBi, the third portion CKBjc of the second group of sub-lines CKBj, the third portion VST2c of the second reset control line VST2, the third portion CKCc of the third clock signal line CKC, the second low potential signal line VGL2, the second high potential signal line VGH2, and the third low potential signal line VGL3 are arranged in sequence.

[0152] Specifically, it can be understood that the third portion of the first group of sub-lines CKBi and the third portion of the second group of sub-lines CKBj form the third portion CKBc of the second clock signal line CKB, the second portion of the first group of sub-lines CKBi and the second portion of the second group of sub-lines CKBj form the second portion CKBb of the second clock signal line CKB, and the first portion of the first group of sub-lines CKBi and the first portion of the second group of sub-lines CKBj form the first portion CKBa of the second clock signal line CKB.

[0153] Meanwhile, in order to illustrate the corresponding relationship between different film layers, Figures 13 to 18 is provided, as Fig.13As shown, the relative positional relationship between the light-shielding layer 212 and the active layer 216 can be seen; as Fig.14 As shown, the relative positional relationship between the light-shielding layer 212, the active layer 216, and the gate layer 218 can be seen; as Figure 8 As shown, the relative positional relationship between the light-shielding layer 212, the active layer 216, the gate layer 218, and the first source-drain layer 221 can be seen; as Fig.15 As shown, the relative positional relationship between the light-shielding layer 212 and the first via 411 can be seen. The first via 411 refers to the via for connecting the first source-drain layer 221 and the light-shielding layer 212, including the via of the buffer layer 213; as Fig.16 As shown, the relative positional relationship between the light-shielding layer 212 and the first source-drain layer 221 and the connection position therebetween can be seen; as Fig.17 As shown, the relative positional relationship between the gate layer 218 and the second via 412 can be seen. The second via 412 refers to the via of the first interlayer insulating layer 219; as Fig.18 As shown, the relative positional relationship between the gate layer 218 and the first source-drain layer 221 and the connection position therebetween can be seen.

[0154] In some embodiments, as Figure 5 、 Figures 8 to 12 、 Figures 19 to 23 As shown, in the first direction, at least one of the first clock signal line CKA, the second clock signal line CKB, the first high-potential signal line VGH1, the first low-potential signal line VGL1, and the low-frequency signal line LC is disposed between the first reset control line VST1 and the second type of gate circuit 22b. By disposing at least one of the first clock signal line CKA, the second clock signal line CKB, the first high-potential signal line VGH1, the first low-potential signal line VGL1, and the low-frequency signal line LC between the first reset control line VST1 and the second type of gate circuit 22b, the length of the connection line that needs to be set when the signal line is connected to the corresponding transistor can be reduced. There is no need to dispose the signal line outside the transistor region and then extend it into the transistor region, reducing the space outside the transistor region and the space inside the transistor region occupied by the signal line. The lateral space occupied by the signal lines connected to the first type of gate circuit 22a can be reduced, the lateral space occupied by the first type of gate circuit 22a can be reduced, and the border of the display panel 2 can be reduced.

[0155] In some embodiments, as Figure 5 、 Figures 19 to 23As shown, the first type of gate circuit 22a includes a first pull-up control module 311. The first pull-up control module 311 is electrically connected to the first high-potential signal line VGH1. In the first direction, the first high-potential signal line VGH1 is disposed between the first reset control line VST1 and the first pull-up control module 311. By disposing the first high-potential signal line VGH1 between the first reset control line VST1 and the first pull-up control module 311, when the first high-potential signal line VGH1 is connected to the first pull-up control module 311, the lateral space occupied by the first high-potential signal line VGH1 (including the connection line for transmitting the signal of the first high-potential signal line VGH1. Similarly, other signal lines include their connection lines) can be reduced, the lateral space occupied by the first type of gate circuit 22a can be reduced, and the border can be reduced.

[0156] In some embodiments, as Figure 5 、 Figures 19 to 23 As shown, the first type of gate circuit 22a includes a first pull-down maintenance module 314. The first pull-down maintenance module 314 is electrically connected to the first low-potential signal line VGL1. In the first direction, the first low-potential signal line VGL1 is disposed between the first pull-down maintenance module 314 and the second type of gate circuit 22b. By disposing the first low-potential signal line VGL1 between the first pull-down maintenance module 314 and the second type of gate circuit 22b, when the first low-potential signal line VGL1 is connected to the first pull-down maintenance module 314, the lateral space occupied by the first low-potential signal line VGL1 can be reduced, the lateral space occupied by the first type of gate circuit 22a can be reduced, and the border can be reduced.

[0157] In some embodiments, as Figure 5 、 Figures 19 to 23 As shown, the first type of gate circuit 22a includes a first inverting module 315. The first inverting module 315 is electrically connected to the low-frequency signal line LC. In the first direction, the low-frequency signal line LC is disposed between the first low-potential signal line VGL1 and the second type of gate circuit 22b. By disposing the low-frequency signal line LC between the first low-potential signal line VGL1 and the second type of gate circuit 22b, the lateral space occupied by the low-frequency signal line LC can be reduced, the lateral space occupied by the first type of gate circuit 22a can be reduced, and the border can be reduced.

[0158] In some embodiments, as Figure 5 、 Figures 19 to 23 As shown, the first type of gate circuit 22a includes a first pull-up module 312. The second clock signal line CKB includes a first group of sub-lines CKBi and a second group of sub-lines CKBj. The first pull-up module 312 includes:

[0159] The first pull-up transistor T21j, one electrode of the first pull-up transistor T21j is electrically connected to the first clock signal line CKA;

[0160] The second pull-up transistor T22j, one electrode of the second pull-up transistor T22j is electrically connected to the first group of sub-lines CKBi;

[0161] The third pull-up transistor T23j, one electrode of the third pull-up transistor T23j is electrically connected to the second group of sub-lines CKBj;

[0162] Wherein, the first pull-up transistor T21j, the second pull-up transistor T22j, and the third pull-up transistor T23j are arranged in sequence along a first direction. In the first direction, the first clock signal line CKA is disposed between the low-frequency signal line LC and the first pull-up transistor T21j, the first group of sub-lines CKBi is disposed between the first pull-up transistor T21j and the second pull-up transistor T22j, and the second group of sub-lines CKBj is disposed between the second pull-up transistor T22j and the third pull-up transistor T23j. By disposing the first clock signal line CKA between the low-frequency signal line LC and the first pull-up transistor T21j, the first group of sub-lines CKBi between the first pull-up transistor T21j and the second pull-up transistor T22j, and the second group of sub-lines CKBj between the second pull-up transistor T22j and the third pull-up transistor T23j, the lateral space occupied by each clock signal line can be reduced, the lateral space occupied by the first type of gate circuit 22a can be reduced, and the border can be reduced.

[0163] In some embodiments, such as Figure 5As shown, the first type of gate circuit 22a includes a first pull-up control module 311, a first pull-up module 312, a first pull-down module 313, a first pull-down maintenance module 314, a first inverter module 315, a first negative-bias protection module 316, and a first reset module 317. The first pull-up control module 311 is electrically connected to the first pull-up module 312 at a first pull-up node Q1[n]. The first pull-down module 313 is electrically connected to the first pull-up node Q1[n] and a first signal output terminal Gn[n] of the first type of gate circuit 22a at the same stage. The first pull-down maintenance module 314 is electrically connected between the first pull-up node Q1[n] and a first low-potential signal line VGL1. The first inverter module 315 is electrically connected to the first pull-up node Q1[n], the first low-potential signal line VGL1, and a low-frequency signal line LC. The first negative-bias protection module 316 is electrically connected between a first high-potential signal line VGH1 and the first pull-up node Q1[n]. The first reset module 317 is electrically connected between the first pull-up node Q1[n] and the first low-potential signal line VGL1.

[0164] In some embodiments, as Figure 5 、 Fig.19 shown, at least two of the first pull-up control module 311, the first pull-up module 312, the first pull-down module 313, the first pull-down maintenance module 314, the first inverter module 315, the first negative-bias protection module 316, and the first reset module 317 are arranged along a second direction, and the included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. By arranging at least two of the first pull-up control module 311, the first pull-up module 312, the first pull-down module 313, the first pull-down maintenance module 314, the first inverter module 315, the first negative-bias protection module 316, and the first reset module 317 along the second direction, the lateral space occupied by the first type of gate circuit 22a can be shortened, thereby reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel 2.

[0165] Specifically, compared with the horizontal arrangement of each module in the comparative display device, in the embodiments of the present application, by arranging at least two modules in the first type of gate circuit 22a along the second direction, the lateral space occupied by the first type of gate circuit 22a can be reduced, the lateral space occupied by the gate driving circuit 22 can be reduced, and the border of the display panel 2 can be reduced.

[0166] In some embodiments, as Figure 5 、 Fig.19As shown, the first pull-up control module 311 and the first reset module 317 are arranged along the second direction. By arranging the first pull-up control module 311 and the first reset module 317 along the second direction, the lateral space occupied by the first pull-up control module 311 and the first reset module 317 can be reduced, the lateral space occupied by the first type of gate circuit 22a can be reduced, and the lateral space occupied by the gate driving circuit 22 can be reduced, thereby reducing the border of the display panel 2.

[0167] Specifically, as Fig.19 shown, it can be seen that in the second direction, the first pull-up control module 311 is arranged above the first reset module 317.

[0168] In some embodiments, as Figure 5 、 Fig.19 shown, at least part of the first pull-down module 313, the first pull-down maintenance module 314, and the first inverter module 315 are arranged along the second direction. By arranging at least part of the first pull-down module 313, the first pull-down maintenance module 314, and the first inverter module 315 along the second direction, the lateral space occupied by the first type of gate circuit 22a can be reduced, and the lateral space occupied by the gate driving circuit 22 can be reduced, thereby reducing the border of the display panel 2.

[0169] Specifically, as Fig.19 shown, it can be seen that in the second direction, the first inverter module 315 and the first pull-down maintenance module 314 are arranged in sequence, a part of the first pull-down module 313 is arranged between the first inverter module 315 and the first pull-down maintenance module 314, and another part of the first pull-down module 313 is arranged on the side of the first pull-down maintenance module 314 away from the first inverter module 315.

[0170] In some embodiments, as Figure 5 、 Fig.19 shown, a part of the first inverter module 315 and a part of the first pull-up control module 311 are arranged along the first direction, and a part of the first inverter module 315 and another part of the first pull-up control module 311 are arranged along the second direction. By arranging a part of the first inverter module 315 and a part of the first pull-up control module 311 along the second direction, the lateral space occupied by the gate driving circuit 22 can be further reduced, thereby reducing the border of the display panel 2.

[0171] Specifically, as Fig.19As shown, it can be seen that the widths of the various parts in the first pull-up control module 311 are different. A part of the first inverter module 315 is arranged along the first direction with a part of the first pull-up control module 311, and a part of the first inverter module 315 is arranged along the second direction with another part of the first pull-up control module 311.

[0172] In some embodiments, as Figure 5 , Figures 19 to 23 shown, the first pull-up control module 311 includes a first pull-up control transistor T11j, a second pull-up control transistor T12j, and a third pull-up control transistor T81j. The gate T11jG of the first pull-up control transistor T11j is electrically connected to the stage transmission output terminal Cout[n - 2] of the upper two-stage first type of gate circuit 22a. The first electrode T11jS of the first pull-up control transistor T11j is electrically connected to the first high potential signal line VGH1. The second electrode T11jD of the first pull-up control transistor T11j is electrically connected to the first electrode T12jS of the second pull-up control transistor T12j. The gate T12jG of the second pull-up control transistor T12j is electrically connected to the stage transmission output terminal Cout[n - 2] of the upper two-stage first type of gate circuit 22a. The second electrode T12jD of the second pull-up control transistor T12j is electrically connected to the first pull-up node Q1[n]. The gate T81jG of the third pull-up control transistor T81j is electrically connected to the first high potential signal line VGH1. The first electrode T81jS of the third pull-up control transistor T81j is electrically connected to the first high potential signal line VGH1. The second electrode T81jD of the third pull-up control transistor T81j is electrically connected to the second electrode T11jD of the first pull-up control transistor T11j;

[0173] Among them, in each stage of the gate driving circuit 22, the third pull-up control transistor T81j, the first pull-up control transistor T11j, and the second pull-up control transistor T12j are arranged in sequence along the second direction. By arranging the third pull-up control transistor T81j, the first pull-up control transistor T11j, and the second pull-up control transistor T12j in sequence along the second direction, the space occupied by the first pull-up module 312 can be reduced, thereby reducing the border of the display panel 2.

[0174] In some embodiments, as Figure 5 , Figures 19 to 23As shown, the third pull-up control transistor T81j includes a first pull-up control sub-transistor T81j1 and a second pull-up control sub-transistor T81j2. The gate T81j2G of the second pull-up control sub-transistor T81j2 and the first electrode T81j2S of the second pull-up control sub-transistor T81j2 are electrically connected to the first high-potential signal line VGH1. The second electrode T81j2D of the second pull-up control sub-transistor T81j2 is electrically connected to the first electrode of the first pull-up control sub-transistor T81j1. The gate T81j1G of the first pull-up control sub-transistor T81j1 is electrically connected to the first high-potential signal line VGH1. The second electrode T81j1D of the first pull-up control sub-transistor T81j1 is electrically connected to the second electrode T11jD of the first pull-up control transistor T11j;

[0175] Wherein, the first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2 are arranged along the second direction. By making the third pull-up control transistor T81j include the first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2, the performance of the third pull-up control transistor T81j can be improved, and the first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2 are arranged along the first direction, which can reduce the lateral area occupied by the third pull-up control transistor T81j and reduce the border of the display panel 2.

[0176] Specifically, the first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2 can be regarded as two independent transistors, or can be regarded as two sub-transistors in the third pull-up control transistor T81j. Similarly, the above description can also be referred to for other sub-transistors, and will not be elaborated in the following embodiments.

[0177] Specifically, when a transistor has multiple sub-transistors, the first electrode of the transistor is the electrode connected to the signal line. For example, the third pull-up control transistor T81j includes the first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2. Since the first electrode T81j2S of the second pull-up control sub-transistor T81j2 is electrically connected to the first high-potential signal line VGH1, the first electrode T81jS of the third pull-up control transistor T81j is the first electrode T81j2S of the second pull-up control sub-transistor T81j2. Similarly, the first electrodes of other transistors can be determined.

[0178] Specifically, the multi-stage gate driving circuit 22 includes a multi-stage first-type gate circuit 22a. In the first-stage first-type gate circuit 22a, the gate T11jG of the first pull-up control transistor T11j can be connected to the start signal line. In other stages of the first-type gate circuit 22a, the gate T11jG of the first pull-up control transistor T11j and the gate T12jG of the second pull-up control transistor T12j are connected to the first signal output ends of the first-type gate circuit 22a of the upper two stages, and the first electrode T11jS of the first pull-up control transistor T11j and the first electrode T12jS of the second pull-up control transistor T12j are electrically connected to the first high-potential signal line VGH1.

[0179] In some embodiments, Figure 5 , Figures 19 to 23 As shown, the first pull-down module 313 includes a first pull-down transistor T31j, a second pull-down transistor T32j, a third pull-down transistor T33j and a fourth pull-down transistor T41j, the gate T31jG of the first pull-down transistor T31j is electrically connected to the first pull-down node QB1[n], the first electrode T31jS of the first pull-down transistor T31j is electrically connected to the first low potential signal line VGL1, the second electrode T31jD of the first pull-down transistor T31j is electrically connected to the stage transmission output terminal Cout[n] of the first type gate circuit 22a of the same stage, the gate T32jG of the second pull-down transistor T32j is electrically connected to the first pull-down node QB1[n], the first electrode T32jS of the second pull-down transistor T32j is electrically connected to the second low potential signal line VGL2, the second electrode T32jD of the second pull-down transistor T32j is electrically connected to another The first signal output terminal Gn[m] of the first-stage first-type gate circuit 22a is electrically connected, the gate T33jG of the third pull-down transistor T33j is electrically connected to the first pull-down node QB1[n], the first electrode T33jS of the third pull-down transistor T33j is electrically connected to the second low-potential signal line VGL2, and the second electrode T33jD of the third pull-down transistor T33j is electrically connected to the first signal output terminal Gn[n] of the first-stage first-type gate circuit 22a; the gate T41jG of the fourth pull-down transistor T41j is electrically connected to the stage transmission output terminal Cout[n+2] of the lower two-stage first-type gate circuit 22a, the first electrode T41jS of the fourth pull-down transistor T41j is electrically connected to the first low-potential signal line VGL1, and the second electrode T41jD of the fourth pull-down transistor T41j is electrically connected to the first pull-up node Q1[n];

[0180] Among them, the first pull-down transistor T31j and the fourth pull-down transistor T41j are arranged along the second direction, and the second pull-down transistor T32j and the third pull-down transistor T33j are arranged along the second direction. By arranging the first pull-down transistor T31j and the fourth pull-down transistor T41j along the second direction, and the second pull-down transistor T32j and the third pull-down transistor T33j along the second direction, the space occupied by the first pull-down module 313 can be reduced, and the border of the display panel 2 can be reduced.

[0181] In some embodiments, such as Figure 5 , Figures 19 to 23 shown, the fourth pull-down transistor T41j includes a first pull-down sub-transistor T41j1 and a second pull-down sub-transistor T41j2. The gate T41j2G of the second pull-down sub-transistor T41j2 is electrically connected to the stage transmission output terminal Cout[n + 2] of the next two stages of the first type of gate circuit 22a. The first electrode T41j2S of the second pull-down sub-transistor T41j2 is electrically connected to the first low-potential signal line VGL1. The second electrode T41j2D of the second pull-down sub-transistor T41j2 is electrically connected to the first electrode T41j1S of the first pull-down sub-transistor T41j1 at a first internal node N1[n]. The gate T41j1G of the first pull-down sub-transistor T41j1 is electrically connected to the stage transmission output terminal Cout[n + 2] of the next two stages of the first type of gate circuit 22a. The second electrode T41j1D of the first pull-down sub-transistor T41j1 is electrically connected to the first pull-up node Q1[n];

[0182] Among them, the first pull-down sub-transistor T41j1 and the second pull-down sub-transistor T41j2 are arranged along the second direction. By making the fourth pull-down transistor T41j include the first pull-down sub-transistor T41j1 and the second pull-down sub-transistor T41j2, the performance of the fourth pull-down transistor T41j can be improved. Moreover, since the first pull-down sub-transistor T41j1 and the second pull-down sub-transistor T41j2 are arranged along the second direction, the lateral area occupied by the fourth pull-down transistor T41j can be reduced, and the border of the display panel 2 can be reduced.

[0183] In some embodiments, such as Figure 5 , Figures 19 to 23As shown, the first inverter module 315 includes a first inverter transistor T51j, a second inverter transistor T52j, a third inverter transistor T53j, a fourth inverter transistor T54j, and a fifth inverter transistor T55j. The gate T51jG of the first inverter transistor T51j and the first electrode T51jS of the first inverter transistor T51j are electrically connected to the low-frequency signal line LC. The second electrode T51jD of the first inverter transistor T51j is electrically connected to the second electrode T52jD of the second inverter transistor T52j. The gate T52jG of the second inverter transistor T52j is electrically connected to the first pull-up node Q1[n]. The first electrode T52jS of the second inverter transistor T52j is electrically connected to the first low-potential signal line VGL1. The gate T53jG of the third inverter transistor T53j is electrically connected to the second electrode T51jD of the first inverter transistor T51j. The first electrode T53jS of the third inverter transistor T53j is electrically connected to the low-frequency signal line LC. The second electrode T53jD of the third inverter transistor T53j is electrically connected to the first pull-down node QB1[n]. The gate T54jG of the fourth inverter transistor T54j is electrically connected to the first pull-up node Q1[n]. The first electrode T54jS of the fourth inverter transistor T54j is electrically connected to the first low-potential signal line VGL1. The second electrode T54jD of the fourth inverter transistor T54j is electrically connected to the first pull-down node QB1[n]. The gate T55jG of the fifth inverter transistor T55j is electrically connected to the stage transmission output terminal Cout[n-2] of the upper two-stage first-type gate circuit 22a. The first electrode T55jS of the fifth inverter transistor T55j is electrically connected to the first low-potential signal line VGL1. The second electrode T55jD of the fifth inverter transistor T55j is electrically connected to the first pull-down node QB1[n];

[0184] Wherein, the first inverter transistor T51j and the second inverter transistor T52j are arranged along the second direction. The third inverter transistor T53j, the fourth inverter transistor T54j, and the fifth inverter transistor T55j are arranged along the second direction. The first inverter transistor T51j and the third inverter transistor T53j are arranged along the first direction. By arranging the first inverter transistor T51j and the second inverter transistor T52j along the second direction, and arranging the third inverter transistor T53j, the fourth inverter transistor T54j, and the fifth inverter transistor T55j along the second direction, the lateral space occupied by the first inverter module 315 can be reduced, thereby reducing the border of the display panel 2.

[0185] In some embodiments, such as Figure 5 、 Figures 19 to 23As shown, the first inverter transistor T51j includes a first inverter sub-transistor T51j1 and a second inverter sub-transistor T51j2. The gate T51j1G of the first inverter sub-transistor T51j1 and the first electrode T51j1S of the first inverter sub-transistor T51j1 are electrically connected to the low-frequency signal line LC. The second electrode T51j1D of the first inverter sub-transistor T51j1 is electrically connected to the first electrode of the second inverter sub-transistor T51j2. The gate T51j2G of the second inverter sub-transistor T51j2 is electrically connected to the low-frequency signal line LC. The second electrode T51j2D of the second inverter sub-transistor T51j2 is electrically connected to the second electrode T52jD of the second inverter transistor T52j;

[0186] Wherein, the first inverter sub-transistor T51j1 and the second inverter sub-transistor T51j2 are arranged along a first direction. By making the first inverter transistor T51j include the first inverter sub-transistor T51j1 and the second inverter sub-transistor T51j2, the performance of the first inverter transistor T51j can be improved.

[0187] In some embodiments, as Figure 5 、 Figures 19 to 23 shown, the third inverter transistor T53j and the third pull-up control transistor T81j are arranged along the first direction, and the third inverter transistor T53j and the first pull-up control transistor T11j are arranged along the second direction; thereby, the lateral space occupied by the first inverter module 315 and the first pull-up control module 311 can be reduced, and the border of the display panel 2 can be reduced.

[0188] In some embodiments, as Figure 5 、 Figures 19 to 23 shown, the first pull-down maintenance module 314 includes a first pull-down maintenance transistor T42j. The gate T42jG of the first pull-down maintenance transistor T42j is electrically connected to the first pull-down node QB1[n]. The first electrode T42jS of the first pull-down maintenance transistor T42j is electrically connected to the first low-potential signal line VGL1. The second electrode T42jD of the first pull-down maintenance transistor T42j is electrically connected to the first pull-up node Q1[n];

[0189] Wherein, in the second direction, the first pull-down maintenance transistor T42j is arranged between the first pull-down transistor T31j and the fourth pull-down transistor T41j. Thereby, the lateral space occupied by the first pull-down maintenance transistor T42j, the first pull-down transistor T31j, and the fourth pull-down transistor T41j can be reduced, and the border of the display panel 2 can be reduced.

[0190] In some embodiments, as Figure 5 、 Figures 19 to 23As shown, the first pull-down holding transistor T42j includes a first pull-down holding sub-transistor T42j1 and a second pull-down holding sub-transistor T42j2. The gate T42j2G of the second pull-down holding sub-transistor T42j2 is electrically connected to the first pull-down node QB1[n]. The first electrode T42j2S of the second pull-down holding sub-transistor T42j2 is electrically connected to the first low potential signal line VGL1. The second electrode T42j2D of the second pull-down holding sub-transistor T42j2 is electrically connected to the first electrode T42j1S of the first pull-down holding sub-transistor T42j1 at a first internal node N1[n]. The gate T42j1G of the first pull-down holding sub-transistor T42j1 is electrically connected to the first pull-down node QB1[n]. The second electrode of the first pull-down holding sub-transistor T42j1 is electrically connected to the first pull-up node Q1[n].

[0191] Wherein, the first pull-down holding sub-transistor T42j1 and the second pull-down holding sub-transistor T42j2 are arranged along a second direction. By making the first pull-down holding transistor T42j include the first pull-down holding sub-transistor T42j1 and the second pull-down holding sub-transistor T42j2, the performance of the first pull-down holding transistor T42j can be improved. And since the first pull-down holding sub-transistor T42j1 and the second pull-down holding sub-transistor T42j2 are arranged along the second direction, the lateral space occupied by the first pull-down holding transistor T42j can be reduced, and the border of the display panel 2 can be reduced.

[0192] In some embodiments, as Figure 5 、 Figures 19 to 23 shown, the first reset module 317 includes a first reset transistor T43j. The gate T43jG of the first reset transistor T43j is electrically connected to the first reset control line VST1. The first electrode T43jS of the first reset transistor T43j is electrically connected to the first low potential signal line VGL1. The second electrode T43jD of the first reset transistor T43j is electrically connected to the first pull-up node Q1[n].

[0193] Wherein, the first reset transistor T43j is arranged on a side of the second pull-up control transistor T12j away from the first pull-up control transistor T11j. By making the first reset transistor T43j arranged on the side of the second pull-up control transistor T12j away from the first pull-up control transistor T11j, the lateral space occupied by the first reset transistor T43j and the first pull-up control module 311 is reduced, thereby reducing the border of the display panel 2, and the first reset transistor T43j is convenient to be connected to the first low potential signal line VGL1.

[0194] In some embodiments, as Figure 5 、 Figures 19 to 23As shown, the first reset transistor T43j includes a first reset sub-transistor T43j1 and a second reset sub-transistor T43j2. The gate T43j1G of the second reset sub-transistor T43j2 is electrically connected to the first reset control line VST1. The first electrode of the second reset sub-transistor T43j2 is electrically connected to the first low potential signal line VGL1. The second electrode T43j1D of the first reset sub-transistor T43j1 is electrically connected to the first electrode T43j1S of the first reset sub-transistor T43j1 at the first internal node N1[n]. The gate T43j1G of the first reset sub-transistor T43j1 is electrically connected to the first reset control line VST1. The second electrode T43j1D of the first reset sub-transistor T43j1 is electrically connected to the first pull-up node Q1[n].

[0195] Wherein, the first reset sub-transistor T43j1 and the second reset sub-transistor T43j2 are arranged along the second direction. By making the first reset transistor T43j include the first reset sub-transistor T43j1 and the second reset sub-transistor T43j2, the performance of the first reset transistor T43j can be improved. And since the first reset sub-transistor T43j1 and the second reset sub-transistor T43j2 are arranged along the second direction, the lateral space occupied by the first reset transistor T43j can be reduced, and the border of the display panel 2 can be reduced.

[0196] In some embodiments, as Figure 5 、 Figures 19 to 23 shown, the first negative bias protection module 316 includes a first negative bias protection transistor T71j. The gate T71jG of the first negative bias protection transistor T71j is electrically connected to the first pull-up node Q1[n]. The first electrode T71jS of the first negative bias protection transistor T71j is electrically connected to the first high potential signal line VGH1. The second electrode T71jD of the first negative bias protection transistor T71j is electrically connected to the first internal node N1[n].

[0197] Wherein, the first negative bias protection transistor T71j is arranged along the second direction between the second inverter transistor T52j and the first pull-down transistor T31j. By making the first negative bias protection transistor T71j be arranged along the second direction between the second inverter transistor T52j and the first pull-down transistor T31j, the lateral area occupied by the first negative bias protection module 316 can be reduced, and the border of the display panel 2 can be reduced.

[0198] In some embodiments, the first negative-bias protection transistor T71j includes a first negative-bias protection sub-transistor T71j1 and a second negative-bias protection sub-transistor T71j2. The gate T71j2G of the second negative-bias protection sub-transistor T71j2 is electrically connected to the first pull-up node Q1[n]. The first electrode T71j2S of the second negative-bias protection sub-transistor T71j2 is electrically connected to the first high-potential signal line. The second electrode T71j2D of the second negative-bias protection sub-transistor T71j2 is electrically connected to the first electrode of the first negative-bias protection sub-transistor T71j1. The gate T71j1G of the first negative-bias protection sub-transistor T71j1 is electrically connected to the first pull-up node Q1[n]. The second electrode T71j1D of the first negative-bias protection sub-transistor T71j1 is electrically connected to the first internal node N1[n].

[0199] Wherein, the first negative-bias protection sub-transistor T71j1 and the second negative-bias protection sub-transistor T71j2 are arranged along the second direction. By making the first negative-bias protection transistor T71j include the first negative-bias protection sub-transistor T71j1 and the second negative-bias protection sub-transistor T71j2, the performance of the first negative-bias protection transistor T71j can be improved. Moreover, since the first negative-bias protection sub-transistor T71j1 and the second negative-bias protection sub-transistor T71j2 are arranged along the second direction, the lateral space occupied by the first negative-bias protection transistor T71j can be reduced, and the border of the display panel 2 can be decreased.

[0200] In some embodiments, the second clock signal line CKB includes a first group of sub-lines CKBi and a second group of sub-lines CKBj. The first pull-up module 312 includes a first pull-up transistor T21j, a second pull-up transistor T22j, and a third pull-up transistor T23j. The gate T21jG of the first pull-up transistor T21j is electrically connected to the first pull-up node Q1[n]. The first electrode T21jS of the first pull-up transistor T21j is electrically connected to the first clock signal line CKA. The second electrode T21jD of the first pull-up transistor T21j is electrically connected to the stage output terminal Cout[n] of the first type of gate circuit 22a at the current stage. The gate T22jG of the second pull-up transistor T22j is electrically connected to the first pull-up node Q1[n]. The first electrode T22jS of the second pull-up transistor T22j is electrically connected to the first group of sub-lines CKBi. The second electrode T22jD of the second pull-up transistor T22j is electrically connected to the first signal output terminal Gn[m] of another stage of the first type of gate circuit 22a. The gate T23jG of the third pull-up transistor T23j is electrically connected to the first pull-up node Q1[n]. The first electrode T23jS of the third pull-up transistor T23j is electrically connected to the second group of sub-lines CKBj. The second electrode T23jD of the third pull-up transistor T23j is electrically connected to the first signal output terminal Gn[n] of the first type of gate circuit 22a at the current stage.

[0201] Among them, in the first direction, the first clock signal line CKA is disposed adjacent to the first pull-up transistor T21j, the first group of sub-lines CKBi is disposed adjacent to the second pull-up transistor T22j, and the second group of sub-lines CKBj is disposed adjacent to the third pull-up transistor T23j; thereby enabling the first clock signal line CKA and the second clock signal line CKB to be directly adjacent to the transistors they are connected to without routing outside the transistor region and then extending into the transistor region, reducing the number of crossover lines, minimizing the space occupied by each clock signal line, and reducing the border of the display panel 2.

[0202] Specifically, the first clock signal line CKA may include a first clock first line CKA1, a first clock second line CKA2, a first clock third line CKA3, and a first clock fourth line CKA4. Every four-stage first type of gate circuit 22a is cyclically connected to these four first clock signal lines CKA. For example, the first-stage to fourth-stage first type of gate circuits 22a are respectively connected to the first clock first line CKA1, the first clock second line CKA2, the first clock third line CKA3, and the first clock fourth line CKA4. The fifth-stage to eighth-stage first type of gate circuits 22a are respectively connected to the first clock first line CKA1, the first clock second line CKA2, the first clock third line CKA3, and the first clock fourth line CKA4. Similarly, the clock signal lines connected to other stages of the first type of gate circuit 22a can be determined.

[0203] Specifically, the above embodiment is described by taking the first clock signal line CKA including four clock lines as an example, but the embodiments of the present application are not limited thereto. The first clock signal line CKA may include other numbers of clock lines, for example, it may include 8 clock lines.

[0204] Specifically, the second clock signal line CKB may include a second clock first line CKB1, a second clock second line CKB2, a second clock third line CKB3, a second clock fourth line CKB4, a second clock fifth line CKB5, a second clock sixth line CKB6, a second clock seventh line CKB7, and a second clock eighth line CKB8. The second clock first line CKB1, the second clock third line CKB3, the second clock fifth line CKB5, and the second clock seventh line CKB7 in the second clock signal line CKB serve as the first group of sub-lines CKBi, and the second clock second line CKB2, the second clock fourth line CKB4, the second clock sixth line CKB6, and the second clock eighth line CKB8 serve as the second group of sub-lines CKBj. The second pull-up transistors T22j of every four levels of the first type of gate circuit 22a are connected to the first group of sub-lines CKBi in a cyclic manner, and the third pull-up transistors T23j of every four levels of the first type of gate circuit 22a are connected to the second group of sub-lines CKBj in a cyclic manner. For example, the second pull-up transistors T22j of the first to fourth levels of the first type of gate circuit 22a are respectively connected to the second clock first line CKB1, the second clock third line CKB3, the second clock fifth line CKB5, and the second clock seventh line CKB7, and the third pull-up transistors T23j of the first to fourth levels of the first type of gate circuit 22a are respectively connected to the second clock second line CKB2, the second clock fourth line CKB4, the second clock sixth line CKB6, and the second clock eighth line CKB8; the second pull-up transistors T22j of the fifth to eighth levels of the first type of gate circuit 22a are respectively connected to the second clock first line CKB1, the second clock third line CKB3, the second clock fifth line CKB5, and the second clock seventh line CKB7, and the third pull-up transistors T23j of the fifth to eighth levels of the first type of gate circuit 22a are respectively connected to the second clock second line CKB2, the second clock fourth line CKB4, the second clock sixth line CKB6, and the second clock eighth line CKB8; similarly, the clock signal lines connected to the first type of gate circuit 22a at other levels can be determined.

[0205] Specifically, the above embodiment is described by taking the second clock signal line CKB including eight clock lines as an example, but the embodiments of the present application are not limited thereto. The second clock signal line CKB may include other numbers of clock lines, for example, it may include 4 clock lines or 16 clock lines.

[0206] In some embodiments, as Figure 5 shown, the first type of gate circuit 22a further includes a first capacitor C1. One plate of the first capacitor C1 is electrically connected to the first pull-up node Q1[n], and the other plate of the first capacitor C1 is electrically connected to the stage output terminal Cout[n] of the first type of gate circuit 22a at this stage.

[0207] In some embodiments, Figure 5 , Figures 19 to 23 As shown, the first capacitor C1 includes a first sub-capacitor C11, a second sub-capacitor C12, a third sub-capacitor C13 and a fourth sub-capacitor C14. In the second direction, the first sub-capacitor C11 and the second sub-capacitor C12 are arranged on both sides of the first pull-up transistor T21j; the third sub-capacitor C13 is arranged on one side of the second pull-up transistor T22j; and the fourth sub-capacitor C14 is arranged on one side of the third pull-up transistor T23j. This can make the capacitance of the first capacitor C1 larger, and the first capacitor C1 does not occupy the lateral space.

[0208] Specifically, the first plate C11a of the first sub-capacitor C11, the first plate C12a of the second sub-capacitor C12, the first plate C13a of the third sub-capacitor C13 and the first plate C14a of the fourth sub-capacitor C14 can be connected together, and the second plate C11b of the first sub-capacitor C11, the second plate C12b of the second sub-capacitor C12, the second plate C13bC14b of the third sub-capacitor C14 can be connected together.

[0209] In some embodiments, Fig.19 , Fig. 20 As shown, the display panel 2 includes a light shielding layer 212, and the light shielding layer 212 includes a first portion VST1a of a first reset control line VST1, a first portion VGH1a of a first high potential signal line VGH1, a stage transmission output terminal Cout[n] of a first type gate circuit 22a of this stage, a first portion VGL1a of a first low potential signal line VGL1, a first portion LCa of a low frequency signal line LC, a first portion CKAa of a first clock signal line CKA, a first portion C11a1 of a first plate C11a of a first sub-capacitor C11, and a first portion C11a1 of a first sub-capacitor C11. The light shielding layer 212 further includes a first part C12a1 of the first plate C12a of the second sub-capacitor C12, and the first part C12a1 of the first plate C12a of the second sub-capacitor C12 and the first part C11a1 of the first plate C11a of the first sub-capacitor C11 are arranged along the second direction.

[0210] Specifically, the stage transmission output end of each stage of the first-type gate circuit 22 a passes through multiple stages of the first-type gate circuit 22 a to be connected to the corresponding transistor.

[0211] Specifically, Fig. 20As shown, the first part CKAa of the first clock signal line CKA includes the first part CKA4a of the fourth first clock line CKA4, the first part CKA3a of the third first clock line CKA3, the first part CKA2a of the second first clock line CKA2, and the first part CKA1a of the first first clock line CKA1, which are arranged in sequence along the first direction.

[0212] Specifically, as Fig. 20 shown, the first part CKBia of the first group of sub-lines CKBi includes the first part CKB7a of the seventh second clock line CKB7, the first part CKB5a of the fifth second clock line CKB5, the first part CKB3a of the third second clock line CKB3, and the first part CKB1a of the first second clock line CKB1, which are arranged in sequence along the first direction.

[0213] Specifically, as Fig. 20 shown, the first part CKBja of the second group of sub-lines CKBj includes the first part CKB8a of the eighth second clock line CKB8, the first part CKB6a of the sixth second clock line CKB6, the first part CKB4a of the fourth second clock line CKB4, and the first part CKB2a of the second second clock line CKB2, which are arranged in sequence along the first direction.

[0214] In some embodiments, as Fig.19 、 Fig.21 shown, the display panel 2 includes an active layer 216, and the active layer 216 includes the active part T11jA of the first pull-up control transistor T11j, the active part T12jA of the second pull-up control transistor T12j, the active part T81jA of the third pull-up control transistor T81j, the active part T21jA of the first pull-up transistor T21j, the active part T22jA of the second pull-up transistor T22j, the active part T23jA of the third pull-up transistor T23j, the active part T31jA of the first pull-down transistor T31j, the active part T32jA of the second pull-down transistor T32j, the active part T33jA of the third pull-down transistor T33j, the active part T41jA of the fourth pull-down transistor T41j, the active part T42jA of the first pull-down maintenance transistor T42j, the active part T51jA of the first inverter transistor T51j, the active part T52jA of the second inverter transistor T52j, the active part T53jA of the third inverter transistor T53j, the active part T54jA of the fourth inverter transistor T54j, the active part T55jA of the fifth inverter transistor T55j, the active part T43jA of the first reset transistor T43j, and the active part T71jA of the first negative bias protection transistor T71j;

[0215] Among them, the active part T81jA of the third pull-up control transistor T81j, the active part T11jA of the first pull-up control transistor T11j, the active part T12jA of the second pull-up control transistor T12j, and the active part T43jA of the first reset transistor T43j are arranged in sequence along the second direction. The active part T51jA of the first inverter transistor T51j, the active part T52jA of the second inverter transistor T52j, the active part T71jA of the first negative bias prevention transistor T71j, the active part T31jA of the first pull-down transistor T31j, the active part T42jA of the first pull-down maintenance transistor T42j, and the active part T41jA of the fourth pull-down transistor T41j are arranged in sequence along the second direction. The active part T53jA of the third inverter transistor T53j, the active part T54jA of the fourth inverter transistor T54j, and the active part T55jA of the fifth inverter transistor T55j are arranged in sequence along the second direction. The active part T32jA of the second pull-down transistor T32j and the active part T33jA of the third pull-down transistor T33j are arranged in sequence along the second direction. The active part T81jA of the third pull-up control transistor T81j, the active part T53jA of the third inverter transistor T53j, the active part T52jA of the second inverter transistor T52j, the active part T21jA of the first pull-up transistor T21j, the active part T32jA of the second pull-down transistor T32j, the active part T22jA of the second pull-up transistor T22j, and the active part T23jA of the third pull-up transistor T23j are arranged in sequence along the first direction.

[0216] Specifically, as Fig.21 shown, the active part T81jA of the third pull-up control transistor T81j includes the active part T81j1A of the first pull-up control sub-transistor T81j1 and the active part T81j2A of the second pull-up control sub-transistor T81j2. The active part T81j1A of the first pull-up control sub-transistor T81j1 and the active part T81j2A of the second pull-up control sub-transistor T81j2 are arranged in sequence along the second direction.

[0217] Specifically, as Fig.21 shown, the active part T41jA of the fourth pull-down transistor T41j includes the active part T41j1A of the first pull-down sub-transistor T41j1 and the active part T41j2A of the second pull-down sub-transistor T41j2. The active part T41j1A of the first pull-down sub-transistor T41j1 and the active part T41j2A of the second pull-down sub-transistor T41j2 are arranged along the second direction.

[0218] Specifically, as Fig.21As shown, the active part T42jA of the first pull-down holding transistor T42j includes the active part T42j1A of the first pull-down holding sub-transistor T42j1 and the active part T42j2A of the second pull-down holding sub-transistor T42j2. The active part T42j1A of the first pull-down holding sub-transistor T42j1 and the active part T42j2A of the second pull-down holding sub-transistor T42j2 are arranged along the second direction.

[0219] Specifically, as Fig.21 shown, the active part T43jA of the first reset transistor T43j includes the active part T43j1A of the first reset sub-transistor T43j1 and the active part T43j1A of the second reset sub-transistor T43j2. The active part T43j1A of the first reset sub-transistor T43j1 and the active part T43j1A of the second reset sub-transistor T43j2 are arranged along the second direction.

[0220] Specifically, as Fig.21 shown, the active part T51jA of the first inverter transistor T51j includes the active part T51j1A of the first inverter sub-transistor T51j1 and the active part T51j2A of the second inverter sub-transistor T51j2. The active part T51j1A of the first inverter sub-transistor T51j1 and the active part T51j2A of the second inverter sub-transistor T51j2 are arranged along the first direction.

[0221] Specifically, as Fig.21 shown, the active part T71jA of the first negative-bias protection transistor T71j includes the active part T71j1A of the first negative-bias protection sub-transistor T71j1 and the active part T71j2A of the second negative-bias protection sub-transistor T71j2. The active part T71j1A of the first negative-bias protection sub-transistor T71j1 and the active part T71j2A of the second negative-bias protection sub-transistor T71j2 are arranged along the first direction.

[0222] Specifically, for the convenience of identifying each sub-transistor, each sub-transistor is identified in the active layer of the display panel. It can be understood that the other electrodes of each sub-transistor can be determined according to the position of the active part of each sub-transistor.

[0223] In some embodiments, as Fig.19 、 Fig. 22As shown, the display panel 2 includes a gate layer 218, and the gate layer 218 includes a second part VST1b of a first reset control line VST1, a second part VGH1b of a first high potential signal line VGH1, a second part VGL1b of a first low potential signal line VGL1, a second part LCb of a low frequency signal line LC, a second part CKAb of a first clock signal line CKA, a second electrode plate C11b of a first sub-capacitor C11, a second electrode plate C12b of a second sub-capacitor C12, a second part CKBib of a first group of sub-lines CKBi, a second electrode plate of a third sub-capacitor C13, a second part CKBjb of a second group of sub-lines CKBj, a second electrode plate C14b of a fourth sub-capacitor C14, a gate T11jG of a first pull-up control transistor T11j, a gate T12jG of a second pull-up control transistor T12j, a gate T81jG of a third pull-up control transistor T81j, a gate T21jG of a first pull-up transistor T21j, a gate T22jG of a second pull-up transistor T22j, a gate T23jG of a third pull-up transistor T23j, a gate T31jG of a first pull-down transistor T31j, a gate T32jG of a second pull-down transistor T32j, a gate T33jG of a third pull-down transistor T33j, a gate T41jG of a fourth pull-down transistor T41j, a gate T42jG of a first pull-down maintenance transistor T42j, a gate T51jG of a first inverter transistor T51j, a gate T52jG of a second inverter transistor T52j, a gate T53jG of a third inverter transistor T53j, a gate T54jG of a fourth inverter transistor T54j, a gate T55jG of a fifth inverter transistor T55j, a gate T43jG of a first reset transistor T43j, and a gate T71jG of a first negative bias prevention transistor T71j;

[0224] Among them, the second electrode plate C11b of the first sub-capacitor C11 and the second electrode plate C12b of the second sub-capacitor C12 are arranged on both sides of the gate T21jG of the first pull-up transistor T21j along the second direction, the second electrode plate of the third sub-capacitor C13 and the gate T22jG of the second pull-up transistor T22j are arranged along the second direction, and the second electrode plate C13bC14b of the fourth sub-capacitor C14 and the gate T23jG of the third pull-up transistor T23j are arranged along the second direction; the gate T81jG of the third pull-up control transistor T81j, the gate T11jG of the first pull-up control transistor T11j, the gate T12jG of the second pull-up control transistor T12j and the gate T43jG of the first reset transistor T43j are arranged in sequence along the second direction, the gate T51jG of the first inverter transistor T51j, the gate T52jG of the second inverter transistor T52j, the gate T71jG of the first negative-bias protection transistor T71j, the gate T31jG of the first pull-down transistor T31j, the gate T42jG of the first pull-down holding transistor T42j, the gate T41jG of the fourth pull-down transistor T41j are arranged in sequence along the second direction, the gate T53jG of the third inverter transistor T53j, the gate T54jG of the fourth inverter transistor T54j, the gate T55jG of the fifth inverter transistor T55j are arranged in sequence along the second direction, the gate T32jG of the second pull-down transistor T32j and the gate T33jG of the third pull-down transistor T33j are arranged in sequence along the second direction, the second part VST1b of the first reset control line VST1, the second part VGH1b of the first high-potential signal line VGH1, the gate T81jG of the third pull-up control transistor T81j, the gate T53jG of the third inverter transistor T53j, the gate T52jG of the second inverter transistor T52j, the second part VGL1b of the first low-potential signal line VGL1, the second part LCb of the low-frequency signal line LC, the second part CKAb of the first clock signal line CKA, the gate T21jG of the first pull-up transistor T21j, the gate T32jG of the second pull-down transistor T32j, the second part CKBib of the first group of sub-lines CKBi, the gate T22jG of the second pull-up transistor T22j, the second part CKBjb of the second group of sub-lines CKBj, the gate T23jG of the third pull-up transistor T23j are arranged in sequence along the first direction.

[0225] Specifically, as Fig. 22 shown, the second part CKAb of the first clock signal line CKA includes the second part of the first clock fourth line CKA4, the second part CKA3b of the first clock third line CKA3, the second part CKA2b of the first clock second line CKA2, and the second part CKA1b of the first clock first line CKA1 arranged in sequence along the first direction.

[0226] Specifically, as Fig. 22 shown, the second part CKBib of the first group of sub-lines CKBi includes the second part CKB7b of the second clock seventh line CKB7, the second part CKB5b of the second clock fifth line CKB5, the second part CKB3b of the second clock third line CKB3, and the second part CKB1b of the second clock first line CKB1, which are arranged in sequence along the first direction.

[0227] Specifically, as Fig. 22 shown, the second part CKBjb of the second group of sub-lines CKBj includes the second part CKB8b of the second clock eighth line CKB8, the second part CKB6b of the second clock sixth line CKB6, the second part CKB4b of the second clock fourth line CKB4, and the second part CKB2b of the second clock second line CKB2, which are arranged in sequence along the first direction.

[0228] Specifically, as Fig. 22 shown, the gate T81jG of the third pull-up control transistor T81j includes the gate T81j1G of the first pull-up control sub-transistor T81j1 and the gate T81j2G of the second pull-up control sub-transistor T81j2. The gate T81j1G of the first pull-up control sub-transistor T81j1 and the gate T81j2G of the second pull-up control sub-transistor T81j2 are arranged in sequence along the second direction.

[0229] Specifically, as Fig. 22 shown, the gate T41jG of the fourth pull-down transistor T41j includes the gate T41j1G of the first pull-down sub-transistor T41j1 and the gate T41j2G of the second pull-down sub-transistor T41j2. The gate T41j1G of the first pull-down sub-transistor T41j1 and the gate T41j2G of the second pull-down sub-transistor T41j2 are arranged along the second direction.

[0230] Specifically, as Fig. 22 shown, the gate T42jG of the first pull-down maintenance transistor T42j includes the gate T42j1G of the first pull-down maintenance sub-transistor T42j1 and the gate T42j2G of the second pull-down maintenance sub-transistor T42j2. The gate T42j1G of the first pull-down maintenance sub-transistor T42j1 and the gate T42j2G of the second pull-down maintenance sub-transistor T42j2 are arranged along the second direction.

[0231] Specifically, as Fig. 22As shown, the gate T43jG of the first reset transistor T43j includes the gate T43j1G of the first reset sub-transistor T43j1 and the gate T43j1G of the second reset sub-transistor T43j2, and the gate T43j1G of the first reset sub-transistor T43j1 and the gate T43j1G of the second reset sub-transistor T43j2 are arranged along the second direction.

[0232] Specifically, as Fig. 22 As shown, the gate T51jG of the first inverter transistor T51j includes the gate T51j1G of the first inverter sub-transistor T51j1 and the gate T51j2G of the second inverter sub-transistor T51j2, and the gate T51j1G of the first inverter sub-transistor T51j1 and the gate T51j2G of the second inverter sub-transistor T51j2 are arranged along the first direction.

[0233] Specifically, as Fig. 22 As shown, the gate T71jG of the first negative-bias protection transistor T71j includes the gate T71j1G of the first negative-bias protection sub-transistor T71j1 and the gate T71j2G of the second negative-bias protection sub-transistor T71j2, and the gate T71j1G of the first negative-bias protection sub-transistor T71j1 and the gate T71j2G of the second negative-bias protection sub-transistor T71j2 are arranged along the first direction.

[0234] In some embodiments, as Fig.19 、 Fig.23As shown, the display panel 2 includes a first source-drain layer 221. The first source-drain layer 221 includes the third part VST1c of the first reset control line VST1, the third part VGH1c of the first high potential signal line VGH1, the third part VGL1c of the first low potential signal line VGL1, the third part LCc of the low-frequency signal line LC, the third part CKAc of the first clock signal line CKA, the second part C11a2 of the first plate C11a of the first sub-capacitor C11, the second part C12a2 of the first plate C12a of the second sub-capacitor C12, the third part CKBic of the first group of sub-lines CKBi, the second part C13a2 of the first plate C13a of the third sub-capacitor C13, the third part CKBjc of the second group of sub-lines CKBj, and the second part C14a2 of the first plate C14a of the fourth sub-capacitor C14, the first electrode T11jS of the first pull-up control transistor T11j, the first electrode T12jS of the second pull-up control transistor T12j, the first electrode T81jS of the third pull-up control transistor T81j, the first electrode T21jS of the first pull-up transistor T21j, the first electrode T22jS of the second pull-up transistor T22j, the first electrode T23jS of the third pull-up transistor T23j, the first electrode T31jS of the first pull-down transistor T31j, the first electrode T32jS of the second pull-down transistor T32j, the first electrode T33jS of the third pull-down transistor T33j, the first electrode T41jS of the fourth pull-down transistor T41j, the first electrode T42jS of the first pull-down holding transistor T42j, the first electrode T51jS of the first inverter transistor T51j, the first electrode T52jS of the second inverter transistor T52j, the first electrode T53jS of the third inverter transistor T53j, the first electrode T54jS of the fourth inverter transistor T54j, the first electrode T55jS of the fifth inverter transistor T55j, the first electrode T43jS of the first reset transistor T43j, the first electrode T71jS of the first negative bias protection transistor T71j, the second electrode T11jD of the first pull-up control transistor T11j, the second electrode T12jD of the second pull-up control transistor T12j, the second electrode T81jD of the third pull-up control transistor T81j, the second electrode T21jD of the first pull-up transistor T21j, the second electrode T22jD of the second pull-up transistor T22j, the second electrode T23jD of the third pull-up transistor T23j, the second electrode T31jD of the first pull-down transistor T31j, the second electrode T32jD of the second pull-down transistor T32j, the second electrode T33jD of the third pull-down transistor T33j, the second electrode T41jD of the fourth pull-down transistor T41j, the second electrode T42jD of the first pull-down holding transistor T42j, the second electrode T51jD of the first inverter transistor T51j, the second electrode T52jD of the second inverter transistor T52j,The second electrode T53jD of the third inverter transistor T53j, the second electrode T54jD of the fourth inverter transistor T54j, the second electrode T55jD of the fifth inverter transistor T55j, the second electrode T43jD of the first reset transistor T43j, the second electrode T71jD of the first negative bias prevention transistor T71j;

[0235] Among them, the second part C11a2 of the first plate C11a of the first sub-capacitor C11 and the second part C12a2 of the first plate C12a of the second sub-capacitor C12 are arranged on both sides of the first electrode T21jS of the first pull-up transistor T21j along the second direction. The second part C13a2 of the first plate C13a of the third sub-capacitor C13 and the first electrode T22jS of the second pull-up transistor T22j are arranged along the second direction. The second part C14a2 of the first plate C14a of the fourth sub-capacitor C14 and the first electrode T23jS of the third pull-up transistor T23j are arranged along the second direction. The first electrodes T81jS of the third pull-up control transistor T81j, the first electrodes T11jS of the first pull-up control transistor T11j, the first electrodes T12jS of the second pull-up control transistor T12j, and the first electrode T43jS of the first reset transistor T43j are arranged in sequence along the second direction. The first electrodes T51jS of the first inverter transistor T51j, the first electrodes T52jS of the second inverter transistor T52j, the first electrodes T71jS of the first negative-bias protection transistor T71j, the first electrode T31jS of the first pull-down transistor T31j, the first electrode T42jS of the first pull-down holding transistor T42j, and the first electrode T41jS of the fourth pull-down transistor T41j are arranged in sequence along the second direction. The first electrodes T53jS of the third inverter transistor T53j and the first electrodes T54jS of the fourth inverter transistor T54j are arranged in sequence along the second direction. The first electrode T32jS of the second pull-down transistor T32j and the first electrode T33jS of the third pull-down transistor T33j are arranged in sequence along the second direction. The third part VST1c of the first reset control line VST1, the third part VGH1c of the first high-potential signal line VGH1, the first electrode T81jS of the third pull-up control transistor T81j, the first electrode T53jS of the third inverter transistor T53j, the first electrode T52jS of the second inverter transistor T52j, the third part VGL1c of the first low-potential signal line VGL1, the third part LCc of the low-frequency signal line LC, the third part CKAc of the first clock signal line CKA, the first electrode T21jS of the first pull-up transistor T21j, the first electrode T32jS of the second pull-down transistor T32j, the third part CKBic of the first group of sub-lines CKBi, the first electrode T22jS of the second pull-up transistor T22j, the third part CKBjc of the second group of sub-lines CKBj, and the first electrode T23jS of the third pull-up transistor T23j are arranged in sequence along the first direction.

[0236] Specifically, in the circuit diagram of the embodiments of the present application, in order to illustrate the connection relationships of the transistors, each transistor has a gate, a first electrode, and a second electrode. However, in the actual design process, in order to reduce the occupied space of the transistors, the electrodes of some transistors are formed by the same structure. For example, the first electrode of the first pull-up control sub-transistor T81j1 and the second electrode T81j2D of the second pull-up control sub-transistor T81j2 can be formed by the same structure. Therefore, in the figure, only the second electrode T81j2D of the second pull-up control sub-transistor T81j2 is marked. It can be understood that this structure is also the first electrode of the first pull-up control sub-transistor T81j1. In another example, the first electrode T54jS of the fourth inverter transistor T54j and the first electrode T55jS of the fifth inverter transistor T55j share the same structure. Therefore, in the figure, only the first electrode T54jS of the fourth inverter transistor T54j is marked. It can be understood that this structure is also the first electrode T55jS of the fifth inverter transistor T55j. Similarly, the structures of the electrodes of other transistors can be determined.

[0237] Specifically, as Figures 19 to 23 shown, the first part of the first plate of the first capacitor C1 is connected to the second part of the first plate of the first capacitor C1. The second part C11a2 of the first plate C11a of the first sub-capacitor C11 is connected to the first part C11a1 of the first plate C11a of the first sub-capacitor C11. The second part C12a2 of the first plate C12a of the second sub-capacitor C12 is connected to the first part C12a1 of the first plate C12a of the second sub-capacitor C12. The second part C13a2 of the first plate C13a of the third sub-capacitor C13 is connected to the first part C13a1 of the first plate C13a of the third sub-capacitor C13. The second part C14a2 of the first plate C14a of the fourth sub-capacitor C14 is connected to the first part C14a1 of the first plate C14a of the fourth sub-capacitor C14.

[0238] Specifically, as Figures 19 to 23As shown, the third part VST1c of the first reset control line VST1 is connected to the second part VST1b and the first part VST1a of the first reset control line VST1. The third part VGH1c of the first high potential signal line VGH1 is connected to the second part VGH1b and the first part VGH1a of the first high potential signal line VGH1. The third part VGL1c of the first low potential signal line VGL1 is connected to the second part VGL1b and the first part VGL1a of the first low potential signal line VGL1. The third part LCc of the low frequency signal line LC is connected to the second part LCb and the first part LCa of the low frequency signal line LC. The third part CKAc of the first clock signal line CKA is connected to the second part CKAb and the first part CKAa of the first clock signal line CKA. The third part CKBic of the first group of sub-lines CKBi is connected to the second part CKBib and the first part CKBia of the first group of sub-lines CKBi. The third part CKBjc of the second group of sub-lines CKBj is connected to the second part CKBjb and the first part CKBja of the second group of sub-lines CKBj.

[0239] Specifically, as Fig.23 shown, the third part CKAc of the first clock signal line CKA includes the third part CKA4c of the first clock fourth line CKA4, the third part CKA3c of the first clock third line CKA3, the third part CKA2c of the first clock second line CKA2, and the third part CKA1c of the first clock first line CKA1, which are arranged in sequence along the first direction.

[0240] Specifically, as Figures 19 to 23 shown, the third part CKA1c of the first clock first line CKA1 is connected to the second part CKA1b and the first part CKA1a of the first clock first line CKA1. The third part CKA2c of the first clock second line CKA2 is connected to the second part CKA2b and the first part CKA2a of the first clock second line CKA2. The third part CKA3c of the first clock third line CKA3 is connected to the second part CKA3b and the first part CKA3a of the first clock third line CKA3. The third part CKA4c of the first clock fourth line CKA4 is connected to the second part and the first part CKA4a of the first clock fourth line CKA4.

[0241] Specifically, as Fig.23As shown, the third part CKBic of the first group of sub-lines CKBi includes the third part CKB7c of the second clock seventh line CKB7, the third part CKB5c of the second clock fifth line CKB5, the third part CKB3c of the second clock third line CKB3, and the third part CKB1c of the second clock first line CKB1, which are arranged in sequence along the first direction.

[0242] Specifically, as Figures 19 to 23 shown, the third part CKB1c of the second clock first line CKB1 is connected to the second part CKB1b and the first part CKB1a of the second clock first line CKB1. The third part CKB3c of the second clock third line CKB3 is connected to the second part CKB3b and the first part CKB3a of the second clock third line CKB3. The third part CKB5c of the second clock fifth line CKB5 is connected to the second part CKB5b and the first part CKB5a of the second clock fifth line CKB5. The third part CKB7c of the second clock seventh line CKB7 is connected to the second part CKB7b and the first part CKB7a of the second clock seventh line CKB7.

[0243] Specifically, as Fig.23 shown, the third part CKBjc of the second group of sub-lines CKBj includes the third part CKB8c of the second clock eighth line CKB8, the third part CKB6c of the second clock sixth line CKB6, the third part CKB4c of the second clock fourth line CKB4, and the third part of the second clock second line CKB2, which are arranged in sequence along the first direction.

[0244] Specifically, as Figures 19 to 23 shown, the third part of the second clock second line CKB2 is connected to the second part CKB2b and the first part CKB2a of the second clock second line CKB2. The third part CKB4c of the second clock fourth line CKB4 is connected to the second part CKB4b and the first part CKB4a of the second clock fourth line CKB4. The third part CKB6c of the second clock sixth line CKB6 is connected to the second part CKB6b and the first part CKB6a of the second clock sixth line CKB6. The third part CKB8c of the second clock eighth line CKB8 is connected to the second part CKB8b and the first part CKB8a of the second clock eighth line CKB8.

[0245] Specifically, as Fig.23As shown, the first source-drain layer 221 includes the first electrode of the first pull-up control sub-transistor T81j1, the second electrode T81j1D of the first pull-up control sub-transistor T81j1, the first electrode T81j2S of the second pull-up control sub-transistor T81j2, and the second electrode T81j2D of the second pull-up control sub-transistor T81j2. The first electrode T81j2S of the second pull-up control sub-transistor T81j2, the second electrode T81j2D of the second pull-up control sub-transistor T81j2, and the second electrode T81j1D of the first pull-up control sub-transistor T81j1 are arranged in sequence along the second direction.

[0246] Specifically, as Fig.23 As shown, the first source-drain layer 221 includes the first electrode T41j1S of the first pull-down sub-transistor T41j1, the second electrode T41j1D of the first pull-down sub-transistor T41j1, the first electrode T41j2S of the second pull-down sub-transistor T41j2, and the second electrode T41j2D of the second pull-down sub-transistor T41j2. The second electrode T41j2D of the second pull-down sub-transistor T41j2, the first electrode T41j2S of the second pull-down sub-transistor T41j2, and the second electrode T41j1D of the first pull-down sub-transistor T41j1 are arranged in sequence along the second direction.

[0247] Specifically, as Fig.23 As shown, the first source-drain layer 221 includes the first electrode T42j1S of the first pull-down maintaining sub-transistor T42j1, the second electrode of the first pull-down maintaining sub-transistor T42j1, the first electrode T42j2S of the second pull-down maintaining sub-transistor T42j2, and the second electrode T42j2D of the second pull-down maintaining sub-transistor T42j2. The second electrode T42j2D of the second pull-down maintaining sub-transistor T42j2, the first electrode T42j2S of the second pull-down maintaining sub-transistor T42j2, and the first electrode T42j1S of the first pull-down maintaining sub-transistor T42j1 are arranged in sequence along the second direction.

[0248] Specifically, as Fig.23 As shown, the first source-drain layer 221 includes the first electrode T43j1S of the first reset sub-transistor T43j1, the second electrode T43j1D of the first reset sub-transistor T43j1, the first electrode of the second reset sub-transistor T43j2, and the second electrode T43j1D of the second reset sub-transistor T43j2. The second electrode T43j1D of the second reset sub-transistor T43j2, the first electrode of the second reset sub-transistor T43j2, and the second electrode T43j1D of the first reset sub-transistor T43j1 are arranged in sequence along the second direction.

[0249] Specifically, as Fig.23As shown, the first source-drain layer 221 includes the first electrode T51j1S of the first inverter sub-transistor T51j1, the second electrode T51j1D of the first inverter sub-transistor T51j1, the first electrode of the second inverter sub-transistor T51j2, and the second electrode T51j2D of the second inverter sub-transistor T51j2. The first electrode T51j1S of the first inverter sub-transistor T51j1, the second electrode T51j1D of the first inverter sub-transistor T51j1, and the second electrode T51j2D of the second inverter sub-transistor T51j2 are arranged in sequence along the first direction.

[0250] Specifically, as Fig.23 shown, the first source-drain layer 221 includes the first electrode of the first negative-bias protection sub-transistor T71j1, the second electrode T71j1D of the first negative-bias protection sub-transistor T71j1, the first electrode T71j2S of the second negative-bias protection sub-transistor T71j2, and the second electrode T71j2D of the second negative-bias protection sub-transistor T71j2. The first electrode T71j2S of the second negative-bias protection sub-transistor T71j2, the second electrode T71j2D of the second negative-bias protection sub-transistor T71j2, and the second electrode T71j1D of the first negative-bias protection sub-transistor T71j1 are arranged in sequence along the first direction.

[0251] Specifically, the first plate of the first capacitor C1 includes a first part and a second part of the first plate of the first capacitor C1. The first plate C11a of the first sub-capacitor C11 includes a first part C11a1 and a second part C11a2 of the first plate C11a of the first sub-capacitor C11; the first plate C12a of the second sub-capacitor C12 includes a first part C12a1 and a second part C12a2 of the first plate C12a of the second sub-capacitor C12; the first plate C13a of the third sub-capacitor C13 includes a first part C13a1 and a second part C13a2 of the first plate C13a of the third sub-capacitor C13; the first plate C14a of the fourth sub-capacitor C14 includes a first part C14a1 and a second part C14a2 of the first plate C14a of the fourth sub-capacitor C14.

[0252] In some embodiments, such as Figure 6 、 Figures 8 to 12 、 Figures 24 to 28As shown, in the first direction, at least one of the second reset control line VST2 and the third clock signal line CKC is disposed between the first type of gate circuit 22a and the third type of gate circuit 22c. By disposing at least one of the second reset control line VST2 and the third clock signal line CKC between the first type of gate circuit 22a and the third type of gate circuit 22c, the length of the connection line that needs to be set when connecting the signal line to the corresponding transistor can be reduced. There is no need to dispose the signal line outside the transistor region and then extend it into the transistor region, reducing the space outside the transistor region and the space inside the transistor region occupied by the signal line. The lateral space occupied by the signal line connected to the second type of gate circuit 22b can be reduced, the lateral space occupied by the second type of gate circuit 22b can be reduced, and the border of the display panel 2 can be reduced.

[0253] In some embodiments, as Figure 6 , Figures 8 to 12 , Figures 24 to 28 shown, the second type of gate circuit 22b includes a second reset module 327. The second reset module 327 is electrically connected to the second reset control line VST2. The second reset control line VST2 is disposed between the first type of gate circuit 22a and the second reset module 327. By disposing the second reset control line VST2 between the first type of gate circuit 22a and the second reset module 327, the lateral space occupied by the second reset control line VST2 can be reduced, the lateral space occupied by the second type of gate circuit 22b can be reduced, and the border of the display panel 2 can be reduced.

[0254] In some embodiments, as Figure 6 , Figures 24 to 28 shown, the second type of gate circuit 22b includes a second pull-up module 322. The second pull-up module 322 includes a fourth pull-up transistor T21i. The fourth pull-up transistor T21i is electrically connected to the third clock signal line CKC;

[0255] Among them, in the first direction, the third clock signal line CKC is disposed between the second reset module 327 and the fourth pull-up transistor T21i. By disposing the third clock signal line CKC between the second reset module 327 and the fourth pull-up transistor T21i, the lateral space occupied by the third clock signal line CKC can be reduced, the lateral space occupied by the first type of gate circuit 22a can be reduced, and the border can be reduced.

[0256] In some embodiments, as Figure 6 , Figures 8 to 12 , Figures 24 to 28As shown, in the first direction, at least one of the second reset control line VST2 and the third clock signal line CKC is disposed between the first type of gate circuit 22a and the third type of gate circuit 22c. By disposing at least one of the second reset control line VST2 and the third clock signal line CKC between the first type of gate circuit 22a and the third type of gate circuit 22c, the length of the connection line that needs to be set when the signal line is connected to the corresponding transistor can be reduced. There is no need to dispose the signal line outside the transistor region and then extend it into the transistor region, reducing the space outside the transistor region and the space inside the transistor region occupied by the signal line, reducing the lateral space occupied by the signal lines connected to the second type of gate circuit 22b, reducing the lateral space occupied by the second type of gate circuit 22b, and reducing the border of the display panel 2.

[0257] In some embodiments, as Figure 6 、 Figures 8 to 12 、 Figures 24 to 28 shown, the second type of gate circuit 22b includes a second reset module 327. The second reset module 327 is electrically connected to the second reset control line VST2. The second reset control line VST2 is disposed between the first type of gate circuit 22a and the second reset module 327. By disposing the second reset control line VST2 between the first type of gate circuit 22a and the second reset module 327, the lateral space occupied by the second reset control line VST2 can be reduced, the lateral space occupied by the second type of gate circuit 22b can be reduced, and the border of the display panel 2 can be reduced.

[0258] In some embodiments, as Figure 6 、 Figures 24 to 28 shown, the second type of gate circuit 22b includes a second pull-up module 322. The second pull-up module 322 includes a fourth pull-up transistor T21i. The fourth pull-up transistor T21i is electrically connected to the third clock signal line CKC;

[0259] Wherein, in the first direction, the third clock signal line CKC is disposed between the second reset module 327 and the fourth pull-up transistor T21i. By disposing the third clock signal line CKC between the second reset module 327 and the fourth pull-up transistor T21i, the lateral space occupied by the third clock signal line CKC can be reduced, the lateral space occupied by the second type of gate circuit 22b can be reduced, and the border can be reduced.

[0260] In some embodiments, as Figure 6As shown, the second type of gate circuit 22b includes a second pull-up control module 321, a second pull-up module 322, a second pull-down module 323, a second pull-down maintenance module 324, a second inverter module 325, a second negative-bias prevention module 326, and a second reset module 327. The second pull-up control module 321 is electrically connected to the second pull-up module 322 at a second pull-up node Q2[n]. The second pull-down module 323 is electrically connected to the second pull-up node Q2[n] and a second signal output terminal INI[n] of the second type of gate circuit 22b at the same level. The second pull-down maintenance module 324 is electrically connected between the second pull-up node Q2[n] and a second low-potential signal line VGL2. The second inverter module 325 is electrically connected to the second pull-up node Q2[n], the second low-potential signal line VGL2, and a low-frequency signal line LC. The second negative-bias prevention module 326 is electrically connected between a first high-potential signal line VGH1 and the second pull-up node Q2[n]. The second reset module 327 is electrically connected between the second pull-up node Q2[n] and the second low-potential signal line VGL2.

[0261] In some embodiments, as Figure 6 , Figure 24 shown, at least two of the second pull-up control module 321, the second pull-up module 322, the second pull-down module 323, the second pull-down maintenance module 324, the second inverter module 325, the second negative-bias prevention module 326, and the second reset module 327 are arranged along a second direction, and the included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. By arranging at least two of the second pull-up control module 321, the second pull-up module 322, the second pull-down module 323, the second pull-down maintenance module 324, the second inverter module 325, the second negative-bias prevention module 326, and the second reset module 327 along the second direction, the lateral space occupied by the second type of gate circuit 22b can be shortened, thereby reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel 2.

[0262] Specifically, compared with the horizontal arrangement of each module in the comparative display device, in the embodiment of the present application, by arranging at least two modules in the second type of gate circuit 22b along the second direction, the lateral space occupied by the second type of gate circuit 22b can be reduced, the lateral space occupied by the gate driving circuit 22 can be reduced, and the border of the display panel 2 can be reduced.

[0263] In some embodiments, as Figure 6 , Figure 24As shown, the second pull-up control module 321 and the second reset module 327 are arranged along the second direction. By arranging the second pull-up control module 321 and the second reset module 327 along the second direction, the lateral space occupied by the second pull-up control module 321 and the second reset module 327 can be reduced, the lateral space occupied by the second type of gate circuit 22b can be reduced, and the lateral space occupied by the gate driving circuit 22 can be reduced, thereby reducing the border of the display panel 2.

[0264] Specifically, as Figure 24 shown, it can be seen that in the second direction, the second pull-up control module 321 is arranged above the second reset module 327.

[0265] In some embodiments, as Figure 6 、 Figure 24 shown, the second pull-down module 323, the second pull-down maintenance module 324, and the second inverting module 325 are arranged along the second direction. By arranging the second pull-down module 323, the second pull-down maintenance module 324, and the second inverting module 325 along the second direction, the lateral space occupied by the second type of gate circuit 22b can be reduced, and the lateral space occupied by the gate driving circuit 22 can be reduced, thereby reducing the border of the display panel 2.

[0266] Specifically, as Figure 24 shown, it can be seen that in the second direction, the second inverting module 325 and the second pull-down maintenance module 324 are arranged in sequence, a part of the second pull-down module 323 is arranged between the second inverting module 325 and the second pull-down maintenance module 324, and another part of the second pull-down module 323 is arranged on the side of the second pull-down maintenance module 324 away from the first inverting module 315.

[0267] In some embodiments, as Figure 6 、 Figure 24 shown, a part of the second inverting module 325, the second negative-bias protection module 326, and a part of the second pull-up control module 321 are arranged along the first direction, a part of the second inverting module 325 and another part of the second pull-up control module 321 are arranged along the second direction, and the second negative-bias protection module 326 and another part of the second pull-up control module 321 are arranged along the second direction. By arranging a part of the second inverting module 325, the second negative-bias protection module 326, and a part of the second pull-up control module 321 along the second direction, the lateral space occupied by the gate driving circuit 22 can be further reduced, thereby reducing the border of the display panel 2.

[0268] Specifically, as Figure 24As shown, it can be seen that the widths of the various parts in the second pull-up control module 321 are different. A part of the second inverter module 325 and the second negative bias prevention module 326 are arranged along a first direction with a part of the second pull-up control module 321, and a part of the second inverter module 325 and the second negative bias prevention module 326 are arranged along a second direction with another part of the second pull-up control module 321.

[0269] In some embodiments, as Figure 6 , Figures 24 to 28 shown, the second pull-up control module 321 includes a fourth pull-up control transistor T11i, a fifth pull-up control transistor T12i, and a sixth pull-up control transistor T81i. The gate T11iG of the fourth pull-up control transistor T11i is electrically connected to the second signal output terminal INI[n - 2] of the second-class gate circuit 22b of the previous two stages. The first electrode T11iS of the fourth pull-up control transistor T11i is electrically connected to the first high-potential signal line VGH1. The second electrode T11iD of the fourth pull-up control transistor T11i is electrically connected to the first electrode T12iS of the fifth pull-up control transistor T12i. The gate T12iG of the fifth pull-up control transistor T12i is electrically connected to the second signal output terminal INI[n - 2] of the second-class gate circuit 22b of the previous two stages. The second electrode T12iD of the fifth pull-up control transistor T12i is electrically connected to the second pull-up node Q2[n]. The gate T81iG of the sixth pull-up control transistor T81i is electrically connected to the first high-potential signal line VGH1. The first electrode T81iS of the sixth pull-up control transistor T81i is electrically connected to the first high-potential signal line VGH1. The second electrode T81iD of the sixth pull-up control transistor T81i is electrically connected to the second electrode T11iD of the fourth pull-up control transistor T11i;

[0270] Among them, in each stage of the gate driving circuit 22, the sixth pull-up control transistor T81i, the fourth pull-up control transistor T11i, and the fifth pull-up control transistor T12i are arranged in sequence along the second direction. By arranging the sixth pull-up control transistor T81i, the fourth pull-up control transistor T11i, and the fifth pull-up control transistor T12i in sequence along the second direction, the space occupied by the second pull-up control module 321 can be reduced, thereby reducing the border of the display panel 2.

[0271] In some embodiments, the sixth pull-up control transistor T81i includes a third pull-up control sub-transistor T81i1 and a fourth pull-up control sub-transistor T81i2. The gate T81i2G of the fourth pull-up control sub-transistor T81i2 and the first electrode T81i2S of the fourth pull-up control sub-transistor T81i2 are electrically connected to the first high-potential signal line VGH1. The second electrode T81i2D of the fourth pull-up control sub-transistor T81i2 is electrically connected to the first electrode of the third pull-up control sub-transistor T81i1. The gate T81i1G of the third pull-up control sub-transistor T81i1 is electrically connected to the first high-potential signal line VGH1. The second electrode T81i1D of the third pull-up control sub-transistor T81i1 is electrically connected to the second electrode T11iD of the fourth pull-up control transistor T11i;

[0272] Wherein, the third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2 are arranged along the second direction. By making the sixth pull-up control transistor T81i include the third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2, the performance of the sixth pull-up control transistor T81i can be improved, and the third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2 are arranged along the first direction, which can reduce the lateral area occupied by the sixth pull-up control transistor T81i and reduce the border of the display panel 2.

[0273] Specifically, the third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2 can be regarded as two independent transistors, or can be regarded as two sub-transistors in the sixth pull-up control transistor T81i. Similarly, for other sub-transistors, the above description can be referred to and will not be elaborated in the following embodiments.

[0274] Specifically, when a transistor has multiple sub-transistors, the first electrode of the transistor is the electrode connected to the signal line. For example, the sixth pull-up control transistor T81i includes the third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2. Since the first electrode T81i2S of the fourth pull-up control sub-transistor T81i2 is electrically connected to the first high-potential signal line VGH1, the first electrode T81iS of the sixth pull-up control transistor T81i is the first electrode T81i2S of the fourth pull-up control sub-transistor T81i2. Similarly, the first electrodes of other transistors can be determined.

[0275] Specifically, the multi-stage gate driving circuit 22 includes a multi-stage second-type gate circuit 22b. In the first-stage second-type gate circuit 22b, the gate T11iG of the fourth pull-up control transistor T11i can be connected to the start signal line. In other stages of the second-type gate circuit 22b, the gate T11iG of the fourth pull-up control transistor T11i and the gate T12iG of the fifth pull-up control transistor T12i are electrically connected to the second signal output terminal INI[n-2] of the upper two stages of the second-type gate circuit 22b, and the first electrode T11iS of the fourth pull-up control transistor T11i and the first electrode T12iS of the fifth pull-up control transistor T12i are electrically connected to the first high-potential signal line VGH1.

[0276] In some embodiments, Figure 6 , Figures 24 to 28 As shown, the second pull-down module 323 includes a fifth pull-down transistor T31i and a sixth pull-down transistor T41i, the gate T31iG of the fifth pull-down transistor T31i is electrically connected to the second pull-down node QB2[n], the first electrode T31iS of the fifth pull-down transistor T31i is electrically connected to the second low potential signal line VGL2, and the second electrode T31iD of the fifth pull-down transistor T31i is electrically connected to the second signal output terminal INI[n] of the second type gate circuit 22b of this level; the gate T41iG of the sixth pull-down transistor T41i is electrically connected to the second signal output terminal INI[n+2] of the second type gate circuit 22b of the next two levels, the first electrode T41iS of the sixth pull-down transistor T41i is connected to the second low potential signal line VGL2, and the second electrode T41iD of the sixth pull-down transistor T41i is electrically connected to the second pull-up node Q2[n];

[0277] The fifth pull-down transistor T31i and the sixth pull-down transistor T41i are arranged along the second direction. By arranging the fifth pull-down transistor T31i and the sixth pull-down transistor T41i along the second direction, the space occupied by the second pull-down module 323 can be reduced, and the frame of the display panel 2 can be reduced.

[0278] In some embodiments, Figure 6 , Figures 24 to 28As shown, the sixth pull-down transistor T41i includes a third pull-down sub-transistor T41i1 and a fourth pull-down sub-transistor T41i2. The gate T41i2G of the fourth pull-down sub-transistor T41i2 is electrically connected to the second signal output terminal INI[n + 2] of the next two-stage second type gate circuit 22b. The first electrode T41i2S of the fourth pull-down sub-transistor T41i2 is electrically connected to the second low potential signal line VGL2. The second electrode T41i2D of the fourth pull-down sub-transistor T41i2 is electrically connected to the first electrode T41i1S of the third pull-down sub-transistor T41i1 at the second internal node N2[n]. The gate T41i1G of the third pull-down sub-transistor T41i1 is electrically connected to the second signal output terminal INI[n + 2] of the next two-stage second type gate circuit 22b. The second electrode T41i1D of the third pull-down sub-transistor T41i1 is electrically connected to the second pull-up node Q2[n].

[0279] Wherein, the third pull-down sub-transistor T41i1 and the fourth pull-down sub-transistor T41i2 are arranged along the second direction. By making the sixth pull-down transistor T41i include the third pull-down sub-transistor T41i1 and the fourth pull-down sub-transistor T41i2, the performance of the sixth pull-down transistor T41i can be improved. Moreover, since the third pull-down sub-transistor T41i1 and the fourth pull-down sub-transistor T41i2 are arranged along the second direction, the lateral area occupied by the sixth pull-down transistor T41i can be reduced, and the border of the display panel 2 can be reduced.

[0280] In some embodiments, such as Figure 6 、 Figures 24 to 28As shown, the second inverting module 325 includes a sixth inverting transistor T51i, a seventh inverting transistor T52i, an eighth inverting transistor T53i, a ninth inverting transistor T54i, and a tenth inverting transistor T55i. The gate T51iG and the first electrode T51iS of the sixth inverting transistor T51i are electrically connected to the low-frequency signal line LC. The second electrode T51iD of the sixth inverting transistor T51i is electrically connected to the second electrode T52iD of the seventh inverting transistor T52i. The gate T52iG of the seventh inverting transistor T52i is electrically connected to the second pull-up node Q2[n]. The first electrode T52iS of the seventh inverting transistor T52i is electrically connected to the second low-potential signal line VGL2. The gate T53iG of the eighth inverting transistor T53i is electrically connected to the second electrode T51iD of the sixth inverting transistor T51i. The first electrode T53iS of the eighth inverting transistor T53i is electrically connected to the low-frequency signal line LC. The second electrode T53iD of the eighth inverting transistor T53i is electrically connected to the second pull-down node QB2[n]. The gate T54iG of the ninth inverting transistor T54i is electrically connected to the second pull-up node Q2[n]. The first electrode T54iS of the ninth inverting transistor T54i is electrically connected to the second low-potential signal line VGL2. The second electrode T54iD of the ninth inverting transistor T54i is electrically connected to the second pull-down node QB2[n]. The gate T55iG of the tenth inverting transistor T55i is electrically connected to the second signal output terminal INI[n - 2] of the upper two-stage second type gate circuit 22b. The first electrode T55iS of the tenth inverting transistor T55i is electrically connected to the second low-potential signal line VGL2. The second electrode T55iD of the tenth inverting transistor T55i is electrically connected to the second pull-down node QB2[n];

[0281] Among them, the sixth inverting transistor T51i and the seventh inverting transistor T52i are arranged along the second direction. The eighth inverting transistor T53i, the ninth inverting transistor T54i, and the tenth inverting transistor T55i are arranged along the second direction. The sixth inverting transistor T51i and the eighth inverting transistor T53i are arranged along the first direction. By arranging the sixth inverting transistor T51i and the seventh inverting transistor T52i along the second direction, and arranging the eighth inverting transistor T53i, the ninth inverting transistor T54i, and the tenth inverting transistor T55i along the second direction, the lateral space occupied by the second inverting module 325 can be reduced, thereby reducing the border of the display panel 2.

[0282] In some embodiments, such as Figure 6 、 Figures 24 to 28As shown, the sixth inverter transistor T51i includes a third inverter sub-transistor T51i1 and a fourth inverter sub-transistor T51i2. The gate T51i1G of the third inverter sub-transistor T51i1 and the first electrode T51i1S of the third inverter sub-transistor T51i1 are electrically connected to the low-frequency signal line LC. The second electrode T51i1D of the third inverter sub-transistor T51i1 is electrically connected to the first electrode of the fourth inverter sub-transistor T51i2. The gate T51i2G of the fourth inverter sub-transistor T51i2 is electrically connected to the low-frequency signal line LC. The second electrode T51i2D of the fourth inverter sub-transistor T51i2 is electrically connected to the second electrode T52iD of the seventh inverter transistor T52i;

[0283] Wherein, the third inverter sub-transistor T51i1 and the fourth inverter sub-transistor T51i2 are arranged along a first direction. By making the sixth inverter transistor T51i include the third inverter sub-transistor T51i1 and the fourth inverter sub-transistor T51i2, the performance of the sixth inverter transistor T51i can be improved.

[0284] In some embodiments, as Figure 6 、 Figures 24 to 28 shown, the eighth inverter transistor T53i and the sixth pull-up control transistor T81i are arranged along the first direction, and the eighth inverter transistor T53i and the fourth pull-up control transistor T11i are arranged along a second direction; thereby, the lateral space occupied by the second inverter module 325 and the second pull-up control module 321 can be reduced, and the border of the display panel 2 can be reduced.

[0285] In some embodiments, as Figure 6 、 Figures 24 to 28 shown, the second pull-down maintenance module 324 includes a second pull-down maintenance transistor T42i. The gate T42iG of the second pull-down maintenance transistor T42i is electrically connected to the second pull-down node QB2[n]. The first electrode T42iS of the second pull-down maintenance transistor T42i is electrically connected to the second low-potential signal line VGL2. The second electrode T42iD of the second pull-down maintenance transistor T42i is electrically connected to the second pull-up node Q2[n];

[0286] Wherein, in the second direction, the second pull-down maintenance transistor T42i is arranged between the fifth pull-down transistor T31i and the sixth pull-down transistor T41i. Thereby, the lateral space occupied by the second pull-down maintenance transistor T42i, the fifth pull-down transistor T31i, and the sixth pull-down transistor T41i can be reduced, and the border of the display panel 2 can be reduced.

[0287] In some embodiments, as Figure 6 、 Figures 24 to 28As shown, the second pull-down sustaining transistor T42i includes a third pull-down sustaining sub-transistor T42i1 and a fourth pull-down sustaining sub-transistor T42i2. The gate T42i2G of the fourth pull-down sustaining sub-transistor T42i2 is electrically connected to the second pull-down node QB2[n]. The first electrode T42i2S of the fourth pull-down sustaining sub-transistor T42i2 is electrically connected to the second low-potential signal line VGL2. The second electrode T42i2D of the fourth pull-down sustaining sub-transistor T42i2 is electrically connected to the first electrode T42i1S of the third pull-down sustaining sub-transistor T42i1 at a second internal node N2[n]. The gate of the third pull-down sustaining sub-transistor T42i1 is electrically connected to the second pull-down node QB2[n]. The second electrode of the third pull-down sustaining sub-transistor T42i1 is electrically connected to the second pull-up node Q2[n];

[0288] Wherein, the third pull-down sustaining sub-transistor T42i1 and the fourth pull-down sustaining sub-transistor T42i2 are arranged along a second direction. By making the second pull-down sustaining transistor T42i include the third pull-down sustaining sub-transistor T42i1 and the fourth pull-down sustaining sub-transistor T42i2, the performance of the second pull-down sustaining transistor T42i can be improved. And since the third pull-down sustaining sub-transistor T42i1 and the fourth pull-down sustaining sub-transistor T42i2 are arranged along the second direction, the lateral space occupied by the second pull-down sustaining transistor T42i can be reduced, and the border of the display panel 2 can be reduced.

[0289] In some embodiments, as Figure 6 、 Figures 24 to 28 shown, the second reset module 327 includes a second reset transistor T43i. The gate T43iG of the second reset transistor T43i is electrically connected to the second reset control line VST2. The first electrode T43iS of the second reset transistor T43i is electrically connected to the second low-potential signal line VGL2. The second electrode T43iD of the second reset transistor T43i is electrically connected to the second pull-up node Q2[n];

[0290] Wherein, the second reset transistor T43i is arranged on a side of the fifth pull-up control transistor T12i away from the fourth pull-up control transistor T11i. By making the second reset transistor T43i arranged on the side of the fifth pull-up control transistor T12i away from the fourth pull-up control transistor T11i, the lateral space occupied by the second reset transistor T43i and the second pull-up control module 321 is reduced, thereby reducing the border of the display panel 2, and the second reset transistor T43i is convenient to be connected to the second low-potential signal line VGL2.

[0291] In some embodiments, as Figure 6 、 Figures 24 to 28As shown, the second reset transistor T43i includes a third reset sub-transistor T43i1 and a fourth reset sub-transistor T43i2. The gate T43i1G of the fourth reset sub-transistor T43i2 is electrically connected to the second reset control line VST2. The first electrode of the fourth reset sub-transistor T43i2 is electrically connected to the second low potential signal line VGL2. The second electrode T43i1D of the third reset sub-transistor T43i1 is electrically connected to the first electrode T43i1S of the third reset sub-transistor T43i1 at the second internal node N2[n]. The gate T43i1G of the third reset sub-transistor T43i1 is electrically connected to the second reset control line VST2. The second electrode T43i1D of the third reset sub-transistor T43i1 is electrically connected to the second pull-up node Q2[n].

[0292] Wherein, the third reset sub-transistor T43i1 and the fourth reset sub-transistor T43i2 are arranged along the second direction. By making the second reset transistor T43i include the third reset sub-transistor T43i1 and the fourth reset sub-transistor T43i2, the performance of the second reset transistor T43i can be improved. And since the third reset sub-transistor T43i1 and the fourth reset sub-transistor T43i2 are arranged along the second direction, the lateral space occupied by the second reset transistor T43i can be reduced, and the border of the display panel 2 can be reduced.

[0293] In some embodiments, as Figure 6 、 Figures 24 to 28 shown, the second negative bias prevention module 326 includes a second negative bias prevention transistor T61i. The gate T61iG of the second negative bias prevention transistor T61i is electrically connected to the second pull-up node Q2[n]. The first electrode T61iS of the second negative bias prevention transistor T61i is electrically connected to the first high potential signal line VGH1. The second electrode T61iD of the second negative bias prevention transistor T61i is electrically connected to the second internal node N2[n].

[0294] Wherein, the second negative bias prevention transistor T61i is arranged along the first direction between the sixth pull-up control transistor T81i and the eighth inverter transistor T53i, and the second negative bias prevention transistor T61i is arranged along the second direction on the side of the fourth pull-up control transistor T11i away from the fifth pull-up control transistor T12i. By arranging the second negative bias prevention transistor T61i along the second direction on the side of the fourth pull-up control transistor T11i away from the fifth pull-up control transistor T12i, the lateral area occupied by the second negative bias prevention module 326 can be reduced, and the border of the display panel 2 can be reduced.

[0295] In some embodiments, as Figure 6 、 Figures 24 to 28As shown, the second negative bias prevention transistor T61i includes a third negative bias prevention transistor T61i1 and a fourth negative bias prevention transistor T61i2, the gate T61i2G of the fourth negative bias prevention transistor T61i2 is electrically connected to the second pull-up node Q2[n], the first electrode T61i2S of the fourth negative bias prevention transistor T61i2 is electrically connected to the first high potential signal line, the second electrode T61i2D of the fourth negative bias prevention transistor T61i2 is electrically connected to the first electrode of the third negative bias prevention transistor T61i1, the gate T61i1G of the third negative bias prevention transistor T61i1 is electrically connected to the second pull-up node Q2[n], and the second electrode T61i1D of the third negative bias prevention transistor T61i1 is electrically connected to the second internal node N2[n];

[0296] The third anti-negative bias transistor T61i1 and the fourth anti-negative bias transistor T61i2 are arranged along the second direction. By making the second anti-negative bias transistor T61i include the third anti-negative bias transistor T61i1 and the fourth anti-negative bias transistor T61i2, the performance of the second anti-negative bias transistor T61i can be improved, and the third anti-negative bias transistor T61i1 and the fourth anti-negative bias transistor T61i2 are arranged along the second direction, which can reduce the lateral space occupied by the second anti-negative bias transistor T61i and reduce the frame of the display panel 2.

[0297] In some embodiments, Figure 6 , Figures 24 to 28 As shown, the second pull-up module 322 includes a fourth pull-up transistor T21i, a gate T21iG of the fourth pull-up transistor T21i is electrically connected to the second pull-up node Q2[n], a first electrode T21iS of the fourth pull-up transistor T21i is electrically connected to the third clock signal line CKC, and a second electrode T21iD of the fourth pull-up transistor T21i is electrically connected to the second signal output terminal INI[n] of the second type gate circuit 22b of this stage;

[0298] Among them, in the first direction, the third clock signal line CKC is arranged adjacent to the fourth pull-up transistor T21i; thereby, the third clock signal line CKC does not need to be routed from outside the transistor area to extend into the transistor area, and the third clock signal line CKC is arranged adjacent to the transistor connected to it, with fewer cross-line, thereby reducing the space occupied by the third clock signal line CKC and reducing the border of the display panel 2.

[0299] Specifically, the third clock signal line CKC may include a third clock first line CKC1, a third clock second line CKC2, a third clock third line CKC3 and a third clock fourth line CKC4, and every four levels of the second-class gate circuit 22b are cyclically connected to the four third clock signal lines CKC. For example, the first-level second-class gate circuit 22b to the fourth-level second-class gate circuit 22b are respectively connected to the third clock first line CKC1, the third clock second line CKC2, the third clock third line CKC3 and the third clock fourth line CKC4, and the fifth-level second-class gate circuit 22b to the eighth-level second-class gate circuit 22b are respectively connected to the third clock first line CKC1, the third clock second line CKC2, the third clock third line CKC3 and the third clock fourth line CKC4. Similarly, the clock signal lines connected to the second-class gate circuits 22b of other levels can be determined.

[0300] Specifically, the above embodiment is described by taking the example that the third clock signal line CKC includes four clock lines, but the embodiment of the present application is not limited thereto, and the third clock signal line CKC may include other numbers of clock lines, for example, may include 8 clock lines.

[0301] In some embodiments, Figure 6 As shown, the second type gate circuit 22b also includes a second capacitor C2, one plate of the second capacitor C2 is electrically connected to the second pull-up node Q2[n], and the other plate of the second capacitor C2 is electrically connected to the second signal output terminal INI[n] of the second type gate circuit 22b at this level.

[0302] Specifically, the second capacitor C2 includes a first plate C2a and a second plate C2b of the second capacitor C2. The first plate C2a of the second capacitor C2 includes a first portion C2a1 and a second portion C2a2 of the first plate C2a of the second capacitor C2.

[0303] In some embodiments, Figure 24 , Figure 25 As shown, the display panel 2 includes a shading layer 212, and the shading layer 212 includes a first part VST2a of a second reset control line VST2, a second signal output terminal INI[n] of a second type of gate circuit 22b at this level, a first part CKCa of a third clock signal line CKC, and a first part C2a1 of a first plate C2a of a second capacitor C2, which are arranged in sequence along a first direction.

[0304] Specifically, Figure 25As shown, the first part CKCa of the third clock signal line CKC includes the first part CKC4a of the fourth third clock line CKC4, the first part CKC3a of the third third clock line CKC3, the first part CKC2a of the second third clock line CKC2, and the first part CKC1a of the first third clock line CKC1, which are arranged in sequence along the first direction.

[0305] In some embodiments, as Figure 24 , Figure 26 shown, the display panel 2 includes an active layer 216, and the active layer 216 includes the active part T11iA of the fourth pull-up control transistor T11i, the active part T12iA of the fifth pull-up control transistor T12i, the active part T81iA of the sixth pull-up control transistor T81i, the active part T21iA of the fourth pull-up transistor T21i, the active part T31iA of the fifth pull-down transistor T31i, the active part T41iA of the sixth pull-down transistor T41i, the active part T42iA of the second pull-down maintaining transistor T42i, the active part T51iA of the sixth inverter transistor T51i, the active part T52iA of the seventh inverter transistor T52i, the active part T53iA of the eighth inverter transistor T53i, the active part T54iA of the ninth inverter transistor T54i, the active part T55iA of the tenth inverter transistor T55i, the active part T43iA of the second reset transistor T43i, and the active part T61iA of the second negative-bias prevention transistor T61i;

[0306] Among them, the active part T81iA of the sixth pull-up control transistor T81i, the active part T11iA of the fourth pull-up control transistor T11i, the active part T12iA of the fifth pull-up control transistor T12i, and the active part T43iA of the second reset transistor T43i are arranged in sequence along the second direction. The active part T51iA of the sixth inverter transistor T51i, the active part T52iA of the seventh inverter transistor T52i, the active part T31iA of the fifth pull-down transistor T31i, the active part T42iA of the second pull-down maintaining transistor T42i, and the active part T41iA of the sixth pull-down transistor T41i are arranged in sequence along the second direction. The active part T53iA of the eighth inverter transistor T53i, the active part T54iA of the ninth inverter transistor T54i, and the active part T55iA of the tenth inverter transistor T55i are arranged in sequence along the second direction. The active part T81iA of the sixth pull-up control transistor T81i, the active part T61iA of the second negative-bias prevention transistor T61i, the active part T53iA of the eighth inverter transistor T53i, the active part T52iA of the seventh inverter transistor T52i, and the active part T21iA of the fourth pull-up transistor T21i are arranged in sequence along the first direction.

[0307] Specifically, as Figure 26 shown, the active part T81iA of the sixth pull-up control transistor T81i includes the active part T81i1A of the third pull-up control sub-transistor T81i1 and the active part T81i2A of the fourth pull-up control sub-transistor T81i2. The active part T81i1A of the third pull-up control sub-transistor T81i1 and the active part T81i2A of the fourth pull-up control sub-transistor T81i2 are arranged in sequence along the second direction.

[0308] Specifically, as Figure 26 shown, the active part T41iA of the sixth pull-down transistor T41i includes the active part T41i1A of the third pull-down sub-transistor T41i1 and the active part T41i2A of the fourth pull-down sub-transistor T41i2. The active part T41i1A of the third pull-down sub-transistor T41i1 and the active part T41i2A of the fourth pull-down sub-transistor T41i2 are arranged along the second direction.

[0309] Specifically, as Figure 26 shown, the active part T42iA of the second pull-down maintenance transistor T42i includes the active part of the third pull-down maintenance sub-transistor T42i1 and the active part T42i2A of the fourth pull-down maintenance sub-transistor T42i2. The active part of the third pull-down maintenance sub-transistor T42i1 and the active part T42i2A of the fourth pull-down maintenance sub-transistor T42i2 are arranged along the second direction.

[0310] Specifically, as Figure 26 shown, the active part T43iA of the second reset transistor T43i includes the active part T43i1A of the third reset sub-transistor T43i1 and the active part T43i1A of the fourth reset sub-transistor T43i2. The active part T43i1A of the third reset sub-transistor T43i1 and the active part T43i1A of the fourth reset sub-transistor T43i2 are arranged along the second direction.

[0311] Specifically, as Figure 26 shown, the active part T51iA of the sixth inverter transistor T51i includes the active part T51i1A of the third inverter sub-transistor T51i1 and the active part T51i2A of the fourth inverter sub-transistor T51i2. The active part T51i1A of the third inverter sub-transistor T51i1 and the active part T51i2A of the fourth inverter sub-transistor T51i2 are arranged along the first direction.

[0312] Specifically, as Figure 26 shown, the active part T61iA of the second negative-bias protection transistor T61i includes the active part T61i1A of the third negative-bias protection sub-transistor T61i1 and the active part T61i2A of the fourth negative-bias protection sub-transistor T61i2. The active part T61i1A of the third negative-bias protection sub-transistor T61i1 and the active part T61i2A of the fourth negative-bias protection sub-transistor T61i2 are arranged along the second direction.

[0313] In some embodiments, as Figure 24 , Figure 27 shown, the display panel 2 includes a gate layer 218. The gate layer 218 includes a second part VST2b of a second reset control line VST2, a second part CKCb of a third clock signal line CKC, a second electrode plate C2b of a second capacitor C2, a gate T11iG of a fourth pull-up control transistor T11i, a gate T12iG of a fifth pull-up control transistor T12i, a gate T81iG of a sixth pull-up control transistor T81i, a gate T21iG of a fourth pull-up transistor T21i, a gate T31iG of a fifth pull-down transistor T31i, a gate T41iG of a sixth pull-down transistor T41i, a gate T42iG of a second pull-down maintenance transistor T42i, a gate T51iG of a sixth inverter transistor T51i, a gate T52iG of a seventh inverter transistor T52i, a gate T53iG of an eighth inverter transistor T53i, a gate T54iG of a ninth inverter transistor T54i, a gate T55iG of a tenth inverter transistor T55i, a gate T43iG of a second reset transistor T43i, and a gate T61iG of a second negative-bias protection transistor T61i;

[0314] Among them, the gate T81iG of the sixth pull-up control transistor T81i, the gate T11iG of the fourth pull-up control transistor T11i, the gate T12iG of the fifth pull-up control transistor T12i, and the gate T43iG of the second reset transistor T43i are arranged in sequence along a second direction. The gate T51iG of the sixth inverter transistor T51i, the gate T52iG of the seventh inverter transistor T52i, the gate T31iG of the fifth pull-down transistor T31i, the gate T42iG of the second pull-down maintenance transistor T42i, and the gate T41iG of the sixth pull-down transistor T41i are arranged in sequence along the second direction. The gate T53iG of the eighth inverter transistor T53i, the gate T54iG of the ninth inverter transistor T54i, and the gate T55iG of the tenth inverter transistor T55i are arranged in sequence along the second direction. The gate T61iG of the second negative-bias protection transistor T61i is arranged on a side of the gate T11iG of the fourth pull-up control transistor T11i away from the gate T12iG of the fifth pull-up control transistor T12i. The second part VST2b of the second reset control line VST2, the gate T81iG of the sixth pull-up control transistor T81i, the gate T61iG of the second negative-bias protection transistor T61i, the gate T53iG of the eighth inverter transistor T53i, the gate T52iG of the seventh inverter transistor T52i, the second part CKCb of the third clock signal line CKC, the gate T21iG of the fourth pull-up transistor T21i, and the second electrode plate C2b of the second capacitor C2 are arranged in sequence along a first direction.

[0315] Specifically, as Figure 27 shown, the second part CKCb of the third clock signal line CKC includes the second part CKC4b of the fourth third clock line CKC4, the second part CKC3b of the third third clock line CKC3, the second part CKC2b of the second third clock line CKC2, and the second part CKC1b of the first third clock line CKC1, which are arranged in sequence along the first direction.

[0316] Specifically, as Figure 27 shown, the gate T81iG of the sixth pull-up control transistor T81i includes the gate T81i1G of the third pull-up control sub-transistor T81i1 and the gate T81i2G of the fourth pull-up control sub-transistor T81i2. The gate T81i1G of the third pull-up control sub-transistor T81i1 and the gate T81i2G of the fourth pull-up control sub-transistor T81i2 are arranged in sequence along the second direction.

[0317] Specifically, as Figure 27 shown, the gate T41iG of the sixth pull-down transistor T41i includes the gate T41i1G of the third pull-down sub-transistor T41i1 and the gate T41i2G of the fourth pull-down sub-transistor T41i2. The gate T41i1G of the third pull-down sub-transistor T41i1 and the gate T41i2G of the fourth pull-down sub-transistor T41i2 are arranged along the second direction.

[0318] Specifically, as Figure 27 shown, the gate T42iG of the second pull-down holding transistor T42i includes the gate of the third pull-down holding sub-transistor T42i1 and the gate T42i2G of the fourth pull-down holding sub-transistor T42i2. The gate of the third pull-down holding sub-transistor T42i1 and the gate T42i2G of the fourth pull-down holding sub-transistor T42i2 are arranged along the second direction.

[0319] Specifically, as Figure 27 shown, the gate T43iG of the second reset transistor T43i includes the gate T43i1G of the third reset sub-transistor T43i1 and the gate T43i1G of the fourth reset sub-transistor T43i2. The gate T43i1G of the third reset sub-transistor T43i1 and the gate T43i1G of the fourth reset sub-transistor T43i2 are arranged along the second direction.

[0320] Specifically, as Figure 27 shown, the gate T51iG of the sixth inverter transistor T51i includes the gate T51i1G of the third inverter sub-transistor T51i1 and the gate T51i2G of the fourth inverter sub-transistor T51i2. The gate T51i1G of the third inverter sub-transistor T51i1 and the gate T51i2G of the fourth inverter sub-transistor T51i2 are arranged along the first direction.

[0321] Specifically, as Figure 27 shown, the gate T61iG of the second negative-bias protection transistor T61i includes the gate T61i1G of the third negative-bias protection sub-transistor T61i1 and the gate T61i2G of the fourth negative-bias protection sub-transistor T61i2, and the gate T61i1G of the third negative-bias protection sub-transistor T61i1 and the gate T61i2G of the fourth negative-bias protection sub-transistor T61i2 are arranged along a first direction.

[0322] In some embodiments, as Figure 24 、 Figure 28 shown, the display panel 2 includes a first source-drain layer 221, and the first source-drain layer 221 includes a third part VST2c of a second reset control line VST2, a third part CKCc of a third clock signal line CKC, a second part C2a2 of a first electrode plate C2a of a second capacitor C2, a first electrode T11iS of a fourth pull-up control transistor T11i, a first electrode T12iS of a fifth pull-up control transistor T12i, a first electrode T81iS of a sixth pull-up control transistor T81i, a first electrode T21iS of a fourth pull-up transistor T21i, a first electrode T31iS of a fifth pull-down transistor T31i, a first electrode T41iS of a sixth pull-down transistor T41i, a first electrode T42iS of a second pull-down holding transistor T42i, a first electrode T51iS of a sixth inverter transistor T51i, a first electrode T52iS of a seventh inverter transistor T52i, a first electrode T53iS of an eighth inverter transistor T53i, a first electrode T54iS of a ninth inverter transistor T54i, a first electrode T55iS of a tenth inverter transistor T55i, a first electrode T43iS of a second reset transistor T43i, a first electrode T61iS of a second negative-bias protection transistor T61i, a second electrode T11iD of the fourth pull-up control transistor T11i, a second electrode T12iD of the fifth pull-up control transistor T12i, a second electrode T81iD of the sixth pull-up control transistor T81i, a second electrode T21iD of the fourth pull-up transistor T21i, a second electrode T31iD of the fifth pull-down transistor T31i, a second electrode T41iD of the sixth pull-down transistor T41i, a second electrode T42iD of the second pull-down holding transistor T42i, a second electrode T51iD of the sixth inverter transistor T51i, a second electrode T52iD of the seventh inverter transistor T52i, a second electrode T53iD of the eighth inverter transistor T53i, a second electrode T54iD of the ninth inverter transistor T54i, a second electrode T55iD of the tenth inverter transistor T55i, a second electrode T43iD of the second reset transistor T43i, and a second electrode T61iD of the second negative-bias protection transistor T61i;

[0323] Among them, the first electrode T81iS of the sixth pull-up control transistor T81i, the first electrode T11iS of the fourth pull-up control transistor T11i, the first electrode T12iS of the fifth pull-up control transistor T12i, and the first electrode T43iS of the second reset transistor T43i are arranged in sequence along the second direction. The first electrode T51iS of the sixth inverter transistor T51i, the first electrode T52iS of the seventh inverter transistor T52i, the first electrode T31iS of the fifth pull-down transistor T31i, the first electrode T42iS of the second pull-down maintenance transistor T42i, and the first electrode T41iS of the sixth pull-down transistor T41i are arranged in sequence along the second direction. The first electrode T53iS of the eighth inverter transistor T53i and the first electrode T54iS of the ninth inverter transistor T54i are arranged in sequence along the second direction. The first electrode T61iS of the second negative-bias prevention transistor T61i is arranged on one side of the first electrode T11iS of the fourth pull-up control transistor T11i away from the first electrode T12iS of the fifth pull-up control transistor T12i. The third part VST2c of the second reset control line VST2, the first electrode T81iS of the sixth pull-up control transistor T81i, the first electrode T61iS of the second negative-bias prevention transistor T61i, the first electrode T53iS of the eighth inverter transistor T53i, the first electrode T52iS of the seventh inverter transistor T52i, the third part CKCc of the third clock signal line CKC, the first electrode T21iS of the fourth pull-up transistor T21i, and the second part C2a2 of the first plate C2a of the second capacitor C2 are arranged in sequence along the first direction.

[0324] Specifically, in the circuit diagram of the embodiment of the present application, in order to illustrate the connection relationship of each transistor, each transistor has a gate, a first electrode, and a second electrode. However, in the actual design process, in order to reduce the occupied space of the transistor, the electrodes of some transistors are formed by the same structure. For example, the first electrode of the third pull-up control sub-transistor T81i1 and the second electrode T81i2D of the fourth pull-up control sub-transistor T81i2 can be formed by the same structure. Therefore, only the second electrode T81i2D of the fourth pull-up control sub-transistor T81i2 is marked in the figure. It can be understood that this structure is also the first electrode of the third pull-up control sub-transistor T81i1. Similarly, the structures of the electrodes of other transistors can be determined.

[0325] Specifically, as Figures 24 to 28 shown, the first part C2a1 of the first plate C2a of the second capacitor C2 is connected to the second part C2a2 of the first plate C2a of the second capacitor C2.

[0326] Specifically, as Figures 24 to 28As shown, the third part VST2c of the second reset control line VST2 is connected to the second part VST2b and the first part VST2a of the second reset control line VST2. The third part CKCc of the third clock signal line CKC is connected to the second part CKCb and the first part CKCa of the third clock signal line CKC.

[0327] Specifically, as Figure 28 shown, the third part CKCc of the third clock signal line CKC includes the third part CKC4c of the fourth third clock line CKC4, the third part CKC3c of the third third clock line CKC3, the third part CKC2c of the second third clock line CKC2, and the third part CKC1c of the first third clock line CKC1, which are arranged in sequence along the first direction.

[0328] Specifically, as Figures 24 to 28 shown, the third part CKC1c of the first third clock line CKC1 is connected to the second part CKC1b and the first part CKC1a of the first third clock line CKC1. The third part CKC2c of the second third clock line CKC2 is connected to the second part CKC2b and the first part CKC2a of the second third clock line CKC2. The third part CKC3c of the third third clock line CKC3 is connected to the second part CKC3b and the first part CKC3a of the third third clock line CKC3. The third part CKC4c of the fourth third clock line CKC4 is connected to the second part CKC4b and the first part CKC4a of the fourth third clock line CKC4.

[0329] Specifically, as Figure 28 shown, the first source-drain layer 221 includes the first electrode of the third pull-up control sub-transistor T81i1, the second electrode T81i1D of the third pull-up control sub-transistor T81i1, the first electrode T81i2S of the fourth pull-up control sub-transistor T81i2, and the second electrode T81i2D of the fourth pull-up control sub-transistor T81i2. The first electrode T81i2S of the fourth pull-up control sub-transistor T81i2, the second electrode T81i2D of the fourth pull-up control sub-transistor T81i2, and the second electrode T81i1D of the third pull-up control sub-transistor T81i1 are arranged in sequence along the second direction.

[0330] Specifically, as Figure 28As shown, the first source-drain layer 221 includes the first electrode T41i1S of the third pull-down transistor T41i1, the second electrode T41i1D of the third pull-down transistor T41i1, the first electrode T41i2S of the fourth pull-down transistor T41i2, and the second electrode T41i2D of the fourth pull-down transistor T41i2. The second electrode T41i2D of the fourth pull-down transistor T41i2, the first electrode T41i2S of the fourth pull-down transistor T41i2, and the second electrode T41i1D of the third pull-down transistor T41i1 are arranged in sequence along the second direction.

[0331] Specifically, as Figure 28 As shown, the first source-drain layer 221 includes the first electrode T42i1S of the third pull-down holding transistor T42i1, the second electrode of the third pull-down holding transistor T42i1, the first electrode T42i2S of the fourth pull-down holding transistor T42i2, and the second electrode T42i2D of the fourth pull-down holding transistor T42i2. The second electrode T42i2D of the fourth pull-down holding transistor T42i2, the first electrode T42i2S of the fourth pull-down holding transistor T42i2, and the first electrode T42i1S of the third pull-down holding transistor T42i1 are arranged in sequence along the second direction.

[0332] Specifically, as Figure 28 As shown, the first source-drain layer 221 includes the first electrode T43i1S of the third reset transistor T43i1, the second electrode T43i1D of the third reset transistor T43i1, the first electrode of the fourth reset transistor T43i2, and the second electrode T43i1D of the fourth reset transistor T43i2. The second electrode T43i1D of the fourth reset transistor T43i2, the first electrode of the fourth reset transistor T43i2, and the second electrode T43i1D of the third reset transistor T43i1 are arranged in sequence along the second direction.

[0333] Specifically, as Figure 28 As shown, the first source-drain layer 221 includes the first electrode T51i1S of the third inverter transistor T51i1, the second electrode T51i1D of the third inverter transistor T51i1, the first electrode of the fourth inverter transistor T51i2, and the second electrode T51i2D of the fourth inverter transistor T51i2. The first electrode T51i1S of the third inverter transistor T51i1, the second electrode T51i1D of the third inverter transistor T51i1, and the second electrode T51i2D of the fourth inverter transistor T51i2 are arranged in sequence along the first direction.

[0334] Specifically, as Figure 28As shown, the first source-drain layer 221 includes the first electrode of the third negative-bias protection transistor T61i1, the second electrode T61i1D of the third negative-bias protection transistor T61i1, the first electrode T61i2S of the fourth negative-bias protection transistor T61i2, and the second electrode T61i2D of the fourth negative-bias protection transistor T61i2. The first electrode T61i2S of the fourth negative-bias protection transistor T61i2, the second electrode T61i2D of the fourth negative-bias protection transistor T61i2, and the second electrode T61i1D of the third negative-bias protection transistor T61i1 are arranged in sequence along the first direction.

[0335] In some embodiments, as Figure 7 , Figures 8 to 12 , Figures 29 to 33 shown, in the first direction, at least one of the second low-potential signal line VGL2 and the second high-potential signal line VGH2 is disposed between the second type of gate circuit 22b and the third low-potential signal line VGL3. By disposing at least one of the second low-potential signal line VGL2 and the second high-potential signal line VGH2 between the second type of gate circuit 22b and the third low-potential signal line VGL3, the length of the connection line that needs to be set when connecting the signal line to the corresponding transistor can be reduced. There is no need to dispose the signal line outside the transistor region and then extend it into the transistor region, reducing the space outside the transistor region and the space inside the transistor region occupied by the signal line, reducing the lateral space occupied by the signal line connected to the third type of gate circuit 22c, reducing the lateral space occupied by the third type of gate circuit 22c, and reducing the border of the display panel 2.

[0336] In some embodiments, as Figure 7 , Figures 8 to 12 , Figures 29 to 33 shown, the third type of gate circuit 22c includes a third pull-down maintenance module 334. The third pull-down maintenance module 334 is electrically connected to the second low-potential signal line VGL2, and the second low-potential signal line VGL2 is disposed between the third pull-down maintenance module 334 and the third low-potential signal line VGL3. By disposing the second low-potential signal line VGL2 between the third pull-down maintenance module 334 and the third low-potential signal line VGL3, the lateral space occupied by the second low-potential signal line VGL2 can be reduced, the lateral space occupied by the third type of gate circuit 22c can be reduced, and the border of the display panel 2 can be reduced.

[0337] In some embodiments, as Figure 7 , Figures 8 to 12 , Figures 29 to 33 shown, the third type of gate circuit 22c includes a third pull-up module 332. The third pull-up module 332 is electrically connected to the second high-potential signal line VGH2;

[0338] In the first direction, the second high potential signal line VGH2 is arranged between the second low potential signal line VGL2 and the third pull-up module 332. By arranging the second high potential signal line VGH2 between the second low potential signal line VGL2 and the third pull-up module 332, the lateral space occupied by the second high potential signal line VGH2 can be reduced, the lateral space occupied by the third type of gate circuit 22c can be reduced, and the frame can be reduced.

[0339] In some embodiments, Figure 7 , Figures 8 to 12 , Figures 29 to 33 As shown, the third type gate circuit 22c includes a third pull-down module 333, and the third pull-down module 333 is electrically connected to the third low potential signal line VGL3;

[0340] Among them, in the first direction, the third low potential signal line VGL3 is arranged on a side of the third pull-down module 333 away from the third pull-up module 332. By arranging the third low potential signal line VGL3 on a side of the third pull-down module 333 away from the third pull-up module 332, the lateral space occupied by the third low potential signal line VGL3 can be reduced, the lateral space occupied by the third type of gate circuit 22c can be reduced, and the frame can be reduced.

[0341] In some embodiments, Figure 7 As shown, the third type gate circuit 22c includes a third pull-up control module 331, a third pull-up module 332, a third pull-down module 333, a third pull-down maintaining module 334, a third inverting module 335 and a third negative bias prevention module 336, wherein the third pull-up control module 331 and the third pull-up module 332 are electrically connected to the third pull-up node Q3[n], the third pull-down module 333 is electrically connected to the third pull-up node Q3[n] and the third signal output terminal REF[n] of the third type gate circuit 22c at this level; the third pull-down maintaining module 334 is electrically connected to the third pull-up node Q3[n]. [n] and the second low potential signal line VGL2; the third inverting module 335 is electrically connected to the third pull-up node Q3[n], the first high potential signal line VGH1, the second low potential signal line VGL2, the first signal output terminal Gn[n-1] of the first type gate circuit 22a of the previous level, the second signal output terminal INI[n] of the second type gate circuit 22b of this level, and the second signal output terminal INI[n+1] of the second type gate circuit 22b of the next level; the third negative bias prevention module 336 is electrically connected between the first high potential signal line VGH1 and the third pull-up node Q3[n].

[0342] In some embodiments, Figure 7 , Figure 29As shown, at least two of the third pull-up control module 331, the third pull-up module 332, the third pull-down module 333, the third pull-down maintenance module 334, the third inverter module 335, and the third negative-bias protection module 336 are arranged along the second direction, and the included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. By arranging at least two of the third pull-up control module 331, the third pull-up module 332, the third pull-down module 333, the third pull-down maintenance module 334, the third inverter module 335, and the third negative-bias protection module 336 along the second direction, the lateral space occupied by the third type of gate circuit 22c can be shortened, thereby reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel 2.

[0343] Specifically, compared with the horizontal arrangement of each module in the comparative display device, in the embodiment of the present application, by arranging at least two modules in the third type of gate circuit 22c along the second direction, the lateral space occupied by the third type of gate circuit 22c can be reduced, the lateral space occupied by the gate driving circuit 22 can be reduced, and the border of the display panel 2 can be reduced.

[0344] In some embodiments, as Figure 7 、 Figure 29 shown, a part of the third pull-up control module 331, the third pull-down maintenance module 334, a part of the third inverter module 335, and the third negative-bias protection module 336 are arranged along the second direction, and another part of the third pull-up control module 331, another part of the third inverter module 335, and a part of the third pull-down module 333 are arranged along the second direction. By arranging a part of the third pull-up control module 331, the third pull-down maintenance module 334, a part of the third inverter module 335, and the third negative-bias protection module 336 along the second direction, and another part of the third pull-up control module 331, another part of the third inverter module 335, and a part of the third pull-down module 333 along the second direction, the lateral space occupied by the third pull-up control module 331, the third pull-down maintenance module 334, the third inverter module 335, the third negative-bias protection module 336, and the third pull-down module 333 can be reduced, the lateral space occupied by the third type of gate circuit 22c can be reduced, the lateral space occupied by the gate driving circuit 22 can be reduced, and thus the border of the display panel 2 can be reduced.

[0345] Specifically, as Figure 29As shown, it can be seen that in the second direction, the third pull-up control module 331 is disposed below the third negative bias prevention module 336, the third negative bias prevention module 336 is disposed below the third pull-down maintenance module 334, and the third pull-down maintenance module 334 is disposed below a part of the third inverter module 335; the third pull-up control module 331 is disposed below a part of the third inverter module 335, a part of the third inverter module 335 is disposed below a part of the third pull-down module 333, and a part of the third inverter module 335 is disposed above a part of the third pull-down module 333.

[0346] In some embodiments, such as Figure 7 , Figures 29 to 33As shown, the third inversion module 335 includes an eleventh inversion transistor T51r, a twelfth inversion transistor T52r, a thirteenth inversion transistor T53r, a fourteenth inversion transistor T54r, a fifteenth inversion transistor T55r and a sixteenth inversion transistor T56r, the gate T51rG of the eleventh inversion transistor T51r and the first electrode T51rS of the eleventh inversion transistor T51r are electrically connected to the first signal output terminal Gn[n-1] of the first type gate circuit 22a of the previous stage, and the second electrode T51rD of the eleventh inversion transistor T51r is electrically connected to ... The second electrode T52rD of the twelfth inverting transistor T52r is electrically connected, the gate T52rG of the twelfth inverting transistor T52r is electrically connected to the second signal output terminal INI[n] of the second type gate circuit 22b of the same level, the first electrode T52rS of the twelfth inverting transistor T52r is electrically connected to the second low potential signal line VGL2, the gate T53rG of the thirteenth inverting transistor T53r is electrically connected to the second electrode T51rD of the eleventh inverting transistor T51r, the first electrode T53rS of the thirteenth inverting transistor T53r is electrically connected to the first high potential signal line VGH 1, a gate T54rG of the fourteenth inverting transistor T54r is electrically connected to the second electrode T51rD of the eleventh inverting transistor T51r, a first electrode T54rS of the fourteenth inverting transistor T54r is electrically connected to the first high potential signal line VGH1, a second electrode T54rD of the fourteenth inverting transistor T54r is electrically connected to the third pull-down node QB3[n], a gate T55rG of the fifteenth inverting transistor T55r is electrically connected to the third pull-up node Q3[n], and a first electrode T54rS of the fifteenth inverting transistor T55r is electrically connected to the first high potential signal line VGH1. 55rS is electrically connected to the second low potential signal line VGL2, the second electrode of the fifteenth inverting transistor T55r is electrically connected to the third pull-down node QB3[n]; the gate T56rG of the sixteenth inverting transistor T56r is electrically connected to the second signal output terminal INI[n+1] of the next-stage second-type gate circuit 22b, the first electrode T56rS of the sixteenth inverting transistor T56r is electrically connected to the second low potential signal line VGL2, and the second electrode T56rD of the sixteenth inverting transistor T56r is electrically connected to the third pull-down node QB3[n];

[0347] Among them, the thirteenth inverter transistor T53r, the eleventh inverter transistor T51r, and the twelfth inverter transistor T52r are arranged along the first direction, the thirteenth inverter transistor T53r and the fourteenth inverter transistor T54r are arranged along the second direction, and the eleventh inverter transistor T51r, the fifteenth inverter transistor T55r, and the sixteenth inverter transistor T56r are arranged along the second direction, which can reduce the lateral space occupied by the third inverter module 335, thereby reducing the border of the display panel 2.

[0348] In some embodiments, as Figure 7 , Figures 29 to 33 shown, the eleventh inverter transistor T51r includes a fifth inverter sub-transistor T51r1 and a sixth inverter sub-transistor T51r2. The gate T51r1G of the fifth inverter sub-transistor T51r1 and the first electrode T51r1S of the fifth inverter sub-transistor T51r1 are electrically connected to the first signal output terminal Gn[n - 1] of the previous-stage first-class gate circuit 22a. The second electrode T51r1D of the fifth inverter sub-transistor T51r1 is electrically connected to the first electrode of the sixth inverter sub-transistor T51r2. The gate T51r2G of the sixth inverter sub-transistor T51r2 is electrically connected to the first signal output terminal Gn[n - 1] of the previous-stage first-class gate circuit 22a. The second electrode T51r2D of the sixth inverter sub-transistor T51r2 is electrically connected to the second electrode T52rD of the twelfth inverter transistor T52r;

[0349] Among them, the fifth inverter sub-transistor T51r1 and the sixth inverter sub-transistor T51r2 are arranged along the second direction. By making the eleventh inverter transistor T51r include the fifth inverter sub-transistor T51r1 and the sixth inverter sub-transistor T51r2, the performance of the eleventh inverter transistor T51r can be improved, and the fifth inverter sub-transistor T51r1 and the sixth inverter sub-transistor T51r2 are arranged along the second direction, which can reduce the lateral space occupied by the eleventh inverter transistor T51r and reduce the border of the display panel 2.

[0350] In some embodiments, as Figure 7 , Figures 29 to 33As shown, the twelfth inverter transistor T52r includes a seventh inverter sub-transistor T52r1 and an eighth inverter sub-transistor T52r2. The gate T52r1G of the seventh inverter sub-transistor T52r1 and the first electrode T52r1S of the seventh inverter sub-transistor T52r1 are electrically connected to the second signal output terminal INI[n] of the second type of gate circuit 22b at this stage. The second electrode T52r1D of the seventh inverter sub-transistor T52r1 is electrically connected to the first electrode T52r2S of the eighth inverter sub-transistor T52r2. The gate T52r2G of the eighth inverter sub-transistor T52r2 is electrically connected to the second signal output terminal INI[n] of the second type of gate circuit 22b at this stage. The second electrode T52r2D of the eighth inverter sub-transistor T52r2 is electrically connected to the second electrode T51rD of the eleventh inverter transistor T51r;

[0351] Wherein, the seventh inverter sub-transistor T52r1 and the eighth inverter sub-transistor T52r2 are arranged along the second direction. By making the twelfth inverter transistor T52r include the seventh inverter sub-transistor T52r1 and the eighth inverter sub-transistor T52r2, the performance of the twelfth inverter transistor T52r can be improved, and the seventh inverter sub-transistor T52r1 and the eighth inverter sub-transistor T52r2 are arranged along the second direction, which can reduce the lateral space occupied by the twelfth inverter transistor T52r and reduce the border of the display panel 2.

[0352] In some embodiments, as Figure 7 、 Figures 29 to 33 shown, the third pull-up control module 331 includes a seventh pull-up control transistor T11r. The gate T11rG of the seventh pull-up control transistor T11r is electrically connected to the second signal output terminal INI[n + 1] of the second type of gate circuit 22b at the next stage. The first electrode T11rS of the seventh pull-up control transistor T11r is electrically connected to the first high potential signal line VGH1. The second electrode T11rD of the seventh pull-up control transistor T11r is electrically connected to the third pull-up node Q3[n];

[0353] Wherein, the seventh pull-up control transistor T11r and the eleventh inverter transistor T51r are arranged along the second direction. By making the seventh pull-up control transistor T11r and the eleventh inverter transistor T51r arranged along the second direction, the lateral space occupied by the third inverter module 335 and the seventh pull-up control transistor T81j can be reduced, and the border of the display panel 2 can be reduced.

[0354] In some embodiments, as Figure 7 、 Figures 29 to 33As shown, the third pull-down module 333 includes a seventh pull-down transistor T31r and an eighth pull-down transistor T41r. The gate T31rG of the seventh pull-down transistor T31r is electrically connected to the third pull-down node QB3[n]. The first electrode T31rS of the seventh pull-down transistor T31r is electrically connected to the third low-potential signal line VGL3. The second electrode T31rD of the seventh pull-down transistor T31r is electrically connected to the third signal output terminal REF[n] of the third type of gate circuit 22c at this stage. The gate T41rG of the eighth pull-down transistor T41r is electrically connected to the first signal output terminal of the first type of gate circuit 22a at the previous stage. The first electrode T41rS of the eighth pull-down transistor T41r is connected to the second low-potential signal line VGL2. The second electrode T41rD of the eighth pull-down transistor T41r is electrically connected to the third pull-up node Q3[n].

[0355] Wherein, the eighth pull-down transistor T41r is disposed between the eleventh inverter transistor T51r and the fifteenth inverter transistor T55r along the second direction. By disposing the eighth pull-down transistor T41r between the eleventh inverter transistor T51r and the fifteenth inverter transistor T55r along the second direction, the space occupied by the third pull-down module 333 and the third inverter module 335 can be reduced, and the border of the display panel 2 can be reduced.

[0356] In some embodiments, as Figure 7 、 Figures 29 to 33 shown, the eighth pull-down transistor T41r includes a fifth pull-down sub-transistor T41r1 and a sixth pull-down sub-transistor T41r2. The gate T41r1G of the fifth pull-down sub-transistor T41r1 is electrically connected to the first signal output terminal of the first type of gate circuit 22a at the previous stage. The first electrode T41r1S of the fifth pull-down sub-transistor T41r1 is electrically connected to the second low-potential signal line VGL2. The second electrode T41r1D of the fifth pull-down sub-transistor T41r1 is electrically connected to the first electrode of the sixth pull-down sub-transistor T41r2 at a third internal node N3[n]. The gate T41r2G of the sixth pull-down sub-transistor T41r2 is electrically connected to the first signal output terminal of the first type of gate circuit 22a at the previous stage. The second electrode T41r2D of the sixth pull-down sub-transistor T41r2 is electrically connected to the third pull-up node Q3[n].

[0357] Among them, the fifth pull-down sub-transistor T41r1 and the sixth pull-down sub-transistor T41r2 are arranged along the second direction. By making the eighth pull-down transistor T41r include the fifth pull-down sub-transistor T41r1 and the sixth pull-down sub-transistor T41r2, the performance of the eighth pull-down transistor T41r can be improved, and since the fifth pull-down sub-transistor T41r1 and the sixth pull-down sub-transistor T41r2 are arranged along the second direction, the lateral area occupied by the eighth pull-down transistor T41r can be reduced, and the border of the display panel 2 can be reduced.

[0358] In some embodiments, as Figure 7 , Figures 29 to 33 shown, the third pull-down sustain module 334 includes a third pull-down sustain transistor T42r. The gate T42rG of the third pull-down sustain transistor T42r is electrically connected to the third pull-down node QB3[n]. The first electrode T42rS of the third pull-down sustain transistor T42r is electrically connected to the second low potential signal line VGL2. The second electrode T42rD of the third pull-down sustain transistor T42r is electrically connected to the third pull-up node Q3[n].

[0359] Among them, in the second direction, the third pull-down sustain transistor T42r is arranged between the twelfth inverter transistor T52r and the seventh pull-up control transistor T11r; thereby, the lateral space occupied by the third pull-down sustain transistor T42r, the twelfth inverter transistor T52r, and the seventh pull-up control transistor T11r can be reduced, and the border of the display panel 2 can be reduced.

[0360] In some embodiments, as Figure 7 , Figures 29 to 33 shown, the third pull-down sustain transistor T42r includes a fifth pull-down sustain sub-transistor T42r1 and a sixth pull-down sustain sub-transistor T42r2. The gate T42r2G of the sixth pull-down sustain sub-transistor T42r2 is electrically connected to the third pull-down node QB3[n]. The first electrode T42r2S of the sixth pull-down sustain sub-transistor T42r2 is electrically connected to the second low potential signal line VGL2. The second electrode T42r2D of the sixth pull-down sustain sub-transistor T42r2 is electrically connected to the first electrode T42r1S of the fifth pull-down sustain sub-transistor T42r1 at a third internal node N3[n]. The gate T42r1G of the fifth pull-down sustain sub-transistor T42r1 is electrically connected to the third pull-down node QB3[n]. The second electrode T42r1D of the fifth pull-down sustain sub-transistor T42r1 is electrically connected to the third pull-up node Q3[n].

[0361] Among them, the fifth pull-down holding sub-transistor T42r1 and the sixth pull-down holding sub-transistor T42r2 are arranged along the second direction. By making the third pull-down holding transistor T42r include the fifth pull-down holding sub-transistor T42r1 and the sixth pull-down holding sub-transistor T42r2, the performance of the third pull-down holding transistor T42r can be improved, and since the fifth pull-down holding sub-transistor T42r1 and the sixth pull-down holding sub-transistor T42r2 are arranged along the second direction, the lateral space occupied by the third pull-down holding transistor T42r can be reduced, and the border of the display panel 2 can be reduced.

[0362] In some embodiments, as Figure 7 , Figures 29 to 33 shown, the third negative-bias protection module 336 includes a third negative-bias protection transistor T61r. The gate T61rG of the third negative-bias protection transistor T61r is electrically connected to the third pull-up node Q3[n]. The first electrode T61rS of the third negative-bias protection transistor T61r is electrically connected to the first high-potential signal line VGH1. The second electrode T61rD of the third negative-bias protection transistor T61r is electrically connected to the third internal node N3[n].

[0363] Among them, the third negative-bias protection transistor T61r is arranged between the seventh pull-up control transistor T11r and the third pull-down holding transistor T42r along the second direction, and the third negative-bias protection transistor T61r is arranged on the side of the eighth pull-down transistor T41r away from the fourteenth inverter transistor T54r along the first direction. By making the third negative-bias protection transistor T61r arranged between the seventh pull-up control transistor T11r and the third pull-down holding transistor T42r along the second direction, the lateral area occupied by the third negative-bias protection module 336 can be reduced, and the border of the display panel 2 can be reduced.

[0364] In some embodiments, as Figure 7 , Figures 29 to 33 shown, the third negative-bias protection transistor T61r includes a fifth negative-bias protection sub-transistor T61r1 and a sixth negative-bias protection sub-transistor T61r2. The gate T61r2G of the sixth negative-bias protection sub-transistor T61r2 is electrically connected to the third pull-up node Q3[n]. The first electrode T61r2S of the sixth negative-bias protection sub-transistor T61r2 is electrically connected to the first high-potential signal line. The second electrode T61r2D of the sixth negative-bias protection sub-transistor T61r2 is electrically connected to the first electrode of the fifth negative-bias protection sub-transistor T61r1. The gate T61r1G of the fifth negative-bias protection sub-transistor T61r1 is electrically connected to the third pull-up node Q3[n]. The second electrode T61r1D of the fifth negative-bias protection sub-transistor T61r1 is electrically connected to the third internal node N3[n].

[0365] Among them, the fifth negative-bias protection transistor T61r1 and the sixth negative-bias protection transistor T61r2 are arranged along the second direction. By making the third negative-bias protection transistor T61r include the fifth negative-bias protection transistor T61r1 and the sixth negative-bias protection transistor T61r2, the performance of the third negative-bias protection transistor T61r can be improved, and since the fifth negative-bias protection transistor T61r1 and the sixth negative-bias protection transistor T61r2 are arranged along the second direction, the lateral space occupied by the third negative-bias protection transistor T61r can be reduced, and the border of the display panel 2 can be reduced.

[0366] In some embodiments, the third pull-up module 332 includes a fifth pull-up transistor T21r. The gate T21rG of the fifth pull-up transistor T21r is electrically connected to the third pull-up node Q3[n]. The first electrode T21rS of the fifth pull-up transistor T21r is electrically connected to the second high-potential signal line VGH2. The second electrode T21rD of the fifth pull-up transistor T21r is electrically connected to the third signal output terminal REF[n] of the third type of gate circuit 22c at this stage.

[0367] Among them, in the first direction, the second high-potential signal line VGH2 is arranged adjacent to the fifth pull-up transistor T21r; thus, the second high-potential signal line VGH2 does not need to extend from outside the transistor region to inside the transistor region, and the second high-potential signal line VGH2 is arranged adjacent to the transistor it is connected to, with fewer cross lines, reducing the space occupied by the second high-potential signal line VGH2 and reducing the border of the display panel 2.

[0368] In some embodiments, as Figure 7 shown, the third type of gate circuit 22c further includes a third capacitor C3. One plate of the third capacitor C3 is electrically connected to the third pull-up node Q3[n], and the other plate of the third capacitor C3 is electrically connected to the third signal output terminal REF[n] of the third type of gate circuit 22c at this stage.

[0369] Specifically, the third capacitor C3 includes a first plate C3a of the third capacitor C3 and a second plate C3b of the third capacitor C3. The first plate C3a of the third capacitor C3 includes a first part C3a1 of the first plate C3a of the third capacitor C3 and a second part C3a2 of the first plate C3a of the third capacitor C3.

[0370] In some embodiments, as Figure 7 shown, the third type of gate circuit 22c further includes a fourth capacitor C4. One plate of the fourth capacitor C4 is electrically connected to the first high-potential signal line VGH1, and the other plate of the fourth capacitor C4 is electrically connected to the second electrode T51rD of the eleventh inverter transistor T51r.

[0371] Specifically, the fourth capacitor C4 includes a first electrode plate C4a of the fourth capacitor C4 and a second electrode plate C4b of the fourth capacitor C4.

[0372] In some embodiments, as Figure 29 , Figure 30 shown, the display panel 2 includes a light-shielding layer 212, and the light-shielding layer 212 includes a first portion VGL2a of a second low-potential signal line VGL2, a first portion VGH2a of a second high-potential signal line VGH2, a first portion C3a1 of a first electrode plate C3a of a third capacitor C3, and a first portion VGL3a of a third low-potential signal line VGL3, which are sequentially arranged in a first direction.

[0373] In some embodiments, as Figure 29 , Figure 31 shown, the display panel 2 includes an active layer 216, and the active layer 216 includes an active portion T11rA of a seventh pull-up control transistor T11r, an active portion T21rA of a fifth pull-up transistor T21r, an active portion T31rA of a seventh pull-down transistor T31r, an active portion T41rA of an eighth pull-down transistor T41r, an active portion T42rA of a third pull-down holding transistor T42r, an active portion T51rA of an eleventh inverter transistor T51r, an active portion T52rA of a twelfth inverter transistor T52r, an active portion T53rA of a thirteenth inverter transistor T53r, an active portion T54rA of a fourteenth inverter transistor T54r, an active portion T55rA of a fifteenth inverter transistor T55r, an active portion T56rA of a sixteenth inverter transistor T56r, and an active portion T61rA of a third negative-bias protection transistor T61r;

[0374] Among them, the active part T53rA of the thirteenth inverter transistor T53r and the active part T54rA of the fourteenth inverter transistor T54r are arranged in sequence along the second direction. The active part T51rA of the eleventh inverter transistor T51r, the active part T41rA of the eighth pull-down transistor T41r, the active part T55rA of the fifteenth inverter transistor T55r, the active part T56rA of the sixteenth inverter transistor T56r, and the active part T11rA of the seventh pull-up control transistor T11r are arranged in sequence along the second direction. The active part T52rA of the twelfth inverter transistor T52r, the active part T42rA of the third pull-down maintenance transistor T42r, the active part T61rA of the third negative-bias prevention transistor T61r, and the active part T11rA of the seventh pull-up control transistor T11r are arranged in sequence along the second direction. The active part T53rA of the thirteenth inverter transistor T53r, the active part T51rA of the eleventh inverter transistor T51r, the active part T52rA of the twelfth inverter transistor T52r, the active part T21rA of the fifth pull-up transistor T21r, and the active part T31rA of the seventh pull-down transistor T31r are arranged in sequence along the first direction.

[0375] Specifically, as Figure 31 shown, the active part T41rA of the eighth pull-down transistor T41r includes the active part T41r1A of the fifth pull-down sub-transistor T41r1 and the active part T41r2A of the sixth pull-down sub-transistor T41r2. The active part T41r1A of the fifth pull-down sub-transistor T41r1 and the active part T41r2A of the sixth pull-down sub-transistor T41r2 are arranged along the second direction.

[0376] Specifically, as Figure 31 shown, the active part of the fifth pull-down maintenance transistor includes the active part T42r1A of the fifth pull-down maintenance sub-transistor T42r1 and the active part T42r2A of the sixth pull-down maintenance sub-transistor T42r2. The active part T42r1A of the fifth pull-down maintenance sub-transistor T42r1 and the active part T42r2A of the sixth pull-down maintenance sub-transistor T42r2 are arranged along the second direction.

[0377] Specifically, as Figure 31 shown, the active part T51rA of the eleventh inverter transistor T51r includes the active part T51r1A of the fifth inverter sub-transistor T51r1 and the active part T51r2A of the sixth inverter sub-transistor T51r2. The active part T51r1A of the fifth inverter sub-transistor T51r1 and the active part T51r2A of the sixth inverter sub-transistor T51r2 are arranged along the second direction.

[0378] Specifically, as Figure 31As shown, the active part T52rA of the twelfth inverter transistor T52r includes the active part T52r1A of the seventh inverter sub-transistor T52r1 and the active part T52r2A of the eighth inverter sub-transistor T52r2. The active part T52r1A of the seventh inverter sub-transistor T52r1 and the active part T52r2A of the eighth inverter sub-transistor T52r2 are arranged along the second direction.

[0379] Specifically, as Figure 31 shown, the active part T61rA of the third negative-bias protection transistor T61r includes the active part T61r1A of the fifth negative-bias protection sub-transistor T61r1 and the active part T61r2A of the sixth negative-bias protection sub-transistor T61r2. The active part T61r1A of the fifth negative-bias protection sub-transistor T61r1 and the active part T61r2A of the sixth negative-bias protection sub-transistor T61r2 are arranged along the second direction.

[0380] In some embodiments, as Figure 29 、 Figure 32 shown, the display panel 2 includes a gate layer 218. The gate layer 218 includes the second part VGL2b of the second low-potential signal line VGL2, the second part VGH2b of the second high-potential signal line VGH2, the second electrode plate C3b of the third capacitor C3, the second electrode plate C4b of the fourth capacitor C4, the second part VGL3b of the third low-potential signal line VGL3, the gate T11rG of the seventh pull-up control transistor T11r, the gate T21rG of the fifth pull-up transistor T21r, the gate T31rG of the seventh pull-down transistor T31r, the gate T41rG of the eighth pull-down transistor T41r, the gate T42rG of the third pull-down maintenance transistor T42r, the gate T51rG of the eleventh inverter transistor T51r, the gate T52rG of the twelfth inverter transistor T52r, the gate T53rG of the thirteenth inverter transistor T53r, the gate T54rG of the fourteenth inverter transistor T54r, the gate T55rG of the fifteenth inverter transistor T55r, the gate T56rG of the sixteenth inverter transistor T56r, and the gate T61rG of the third negative-bias protection transistor T61r;

[0381] Among them, the gate T53rG of the thirteenth inverter transistor T53r and the gate T54rG of the fourteenth inverter transistor T54r are arranged in sequence along the second direction. The gate T51rG of the eleventh inverter transistor T51r, the gate T41rG of the eighth pull-down transistor T41r, the gate T55rG of the fifteenth inverter transistor T55r, the gate T56rG of the sixteenth inverter transistor T56r, and the gate T11rG of the seventh pull-up control transistor T11r are arranged in sequence along the second direction. The gate T52rG of the twelfth inverter transistor T52r, the gate T42rG of the third pull-down maintenance transistor T42r, the gate T61rG of the third negative-bias protection transistor T61r, and the gate T11rG of the seventh pull-up control transistor T11r are arranged in sequence along the second direction. The second plate C3b of the third capacitor C3 and the gate T21rG of the fifth pull-up transistor T21r are arranged along the second direction. The second plate C4b of the fourth capacitor C4, the gate T53rG of the thirteenth inverter transistor T53r, the gate T51rG of the eleventh inverter transistor T51r, the gate T52rG of the twelfth inverter transistor T52r, the second part VGL2b of the second low-potential signal line VGL2, the second part VGH2b of the second high-potential signal line VGH2, the gate T21rG of the fifth pull-up transistor T21r and the gate T31rG of the seventh pull-down transistor T31r, and the second part VGL3b of the third low-potential signal line VGL3 are arranged in sequence along the first direction.

[0382] Specifically, as Figure 32 shown, the gate T41rG of the eighth pull-down transistor T41r includes the gate T41r1G of the fifth pull-down sub-transistor T41r1 and the gate T41r2G of the sixth pull-down sub-transistor T41r2. The gate T41r1G of the fifth pull-down sub-transistor T41r1 and the gate T41r2G of the sixth pull-down sub-transistor T41r2 are arranged along the second direction.

[0383] Specifically, as Figure 32 shown, the gate of the fifth pull-down maintenance transistor includes the gate T42r1G of the fifth pull-down maintenance sub-transistor T42r1 and the gate T42r2G of the sixth pull-down maintenance sub-transistor T42r2. The gate T42r1G of the fifth pull-down maintenance sub-transistor T42r1 and the gate T42r2G of the sixth pull-down maintenance sub-transistor T42r2 are arranged along the second direction.

[0384] Specifically, as Figure 32As shown, the gate T51rG of the eleventh inverter transistor T51r includes the gate T51r1G of the fifth inverter sub-transistor T51r1 and the gate T51r2G of the sixth inverter sub-transistor T51r2, and the gate T51r1G of the fifth inverter sub-transistor T51r1 and the gate T51r2G of the sixth inverter sub-transistor T51r2 are arranged along the second direction.

[0385] Specifically, as Figure 32 shown, the gate T52rG of the twelfth inverter transistor T52r includes the gate T52r1G of the seventh inverter sub-transistor T52r1 and the gate T52r2G of the eighth inverter sub-transistor T52r2, and the gate T52r1G of the seventh inverter sub-transistor T52r1 and the gate T52r2G of the eighth inverter sub-transistor T52r2 are arranged along the second direction.

[0386] Specifically, as Figure 32 shown, the gate T61rG of the third negative-bias protection transistor T61r includes the gate T61r1G of the fifth negative-bias protection sub-transistor T61r1 and the gate T61r2G of the sixth negative-bias protection sub-transistor T61r2, and the gate T61r1G of the fifth negative-bias protection sub-transistor T61r1 and the gate T61r2G of the sixth negative-bias protection sub-transistor T61r2 are arranged along the second direction.

[0387] In some embodiments, as Figure 29 、 Figure 33As shown, the display panel 2 includes a first source-drain layer 221, and the first source-drain layer 221 includes a third part VGL2c of a second low potential signal line VGL2, a third part VGH2c of a second high potential signal line VGH2, a second part C3a2 of a first electrode C3a of a third capacitor C3, a first electrode C4a of a fourth capacitor C4, a third part VGL3c of a third low potential signal line VGL3, a first electrode T11rS of a seventh pull-up control transistor T11r, a first electrode T21rS of a fifth pull-up transistor T21r, a first electrode T31rS of a seventh pull-down transistor T31r, a first electrode T41rS of an eighth pull-down transistor T41r, a first electrode T42rS of a third pull-down maintenance transistor T42r, a first electrode T51rS of an eleventh inverter transistor T51r, a first electrode T52rS of a twelfth inverter transistor T52r, a first electrode T53rS of a thirteenth inverter transistor T53r, a first electrode T54rS of a fourteenth inverter transistor T54r, a first electrode T55rS of a fifteenth inverter transistor T55r, a first electrode T56rS of a sixteenth inverter transistor T56r, a first electrode T61rS of a third negative-bias protection transistor T61r, a second electrode T11rD of the seventh pull-up control transistor T11r, a second electrode T21rD of the fifth pull-up transistor T21r, a second electrode T31rD of the seventh pull-down transistor T31r, a second electrode T41rD of the eighth pull-down transistor T41r, a second electrode T42rD of the third pull-down maintenance transistor T42r, a second electrode T51rD of the eleventh inverter transistor T51r, a second electrode T52rD of the twelfth inverter transistor T52r, a second electrode T53rD of the thirteenth inverter transistor T53r, a second electrode T54rD of the fourteenth inverter transistor T54r, a second electrode of the fifteenth inverter transistor T55r, a second electrode T56rD of the sixteenth inverter transistor T56r, a second electrode T61rD of the third negative-bias protection transistor T61r;

[0388] Among them, the first electrode T53rS of the thirteenth inverter transistor T53r and the first electrode T54rS of the fourteenth inverter transistor T54r are arranged in sequence along the second direction. The first electrode T51rS of the eleventh inverter transistor T51r, the first electrode T41rS of the eighth pull-down transistor T41r, the first electrode T55rS of the fifteenth inverter transistor T55r, the first electrode T56rS of the sixteenth inverter transistor T56r, and the first electrode T11rS of the seventh pull-up control transistor T11r are arranged in sequence along the second direction. The first electrode T52rS of the twelfth inverter transistor T52r, the first electrode T42rS of the third pull-down maintenance transistor T42r, the first electrode T61rS of the third negative-bias prevention transistor T61r, and the first electrode T11rS of the seventh pull-up control transistor T11r are arranged in sequence along the second direction. The second part C3a2 of the first plate C3a of the third capacitor C3 and the first electrode T21rS of the fifth pull-up transistor T21r are arranged in the second direction. The second part C3a2 of the first plate C3a of the third capacitor C3 and the first electrode T21rS of the fifth pull-up transistor T21r are arranged in the second direction. The first plate C4a of the fourth capacitor C4, the first electrode T53rS of the thirteenth inverter transistor T53r, the first electrode T51rS of the eleventh inverter transistor T51r, the first electrode T52rS of the twelfth inverter transistor T52r, the third part VGL2c of the second low-potential signal line VGL2, the third part VGH2c of the second high-potential signal line VGH2, the first electrode T21rS of the fifth pull-up transistor T21r, the first electrode T31rS of the seventh pull-down transistor T31r, and the third part VGL3c of the third low-potential signal line VGL3 are arranged in sequence along the first direction.

[0389] Specifically, in the circuit diagram of the embodiment of the present application, in order to illustrate the connection relationship of each transistor, each transistor has a gate, a first electrode, and a second electrode. However, in the actual design process, in order to reduce the occupied space of the transistor, the electrodes of some transistors are formed by the same structure, and it can be understood that this structure can be regarded as the electrodes of two transistors. Similarly, the structures of the electrodes of other transistors can be determined.

[0390] Specifically, as Figures 29 to 33 shown, the first part C3a1 of the first plate C3a of the third capacitor C3 is connected to the second part C3a2 of the first plate C3a of the third capacitor C3.

[0391] Specifically, as Figures 29 to 33As shown, the third part VGL2c of the second low potential signal line VGL2 is connected to the second part VGL2b and the first part VGL2a of the second low potential signal line VGL2. The third part VGH2c of the second high potential signal line VGH2 is connected to the second part VGH2b and the first part VGH2a of the second high potential signal line VGH2. The third part VGL3c of the third low potential signal line VGL3 is connected to the second part VGL3b and the first part VGL3a of the third low potential signal line VGL3.

[0392] Specifically, as Figure 33 shown, the first source-drain layer 221 includes the first electrode T41r1S of the fifth pull-down transistor T41r1, the second electrode T41r1D of the fifth pull-down transistor T41r1, the first electrode of the sixth pull-down transistor T41r2, and the second electrode T41r2D of the sixth pull-down transistor T41r2. The first electrode T41r1S of the fifth pull-down transistor T41r1, the second electrode T41r1D of the fifth pull-down transistor T41r1, and the second electrode T41r2D of the sixth pull-down transistor T41r2 are arranged in sequence along the second direction.

[0393] Specifically, as Figure 33 shown, the first source-drain layer 221 includes the first electrode T42r1S of the fifth pull-down holding transistor T42r1, the second electrode T42r1D of the fifth pull-down holding transistor T42r1, the first electrode T42r2S of the sixth pull-down holding transistor T42r2, and the second electrode T42r2D of the sixth pull-down holding transistor T42r2. The second electrode T42r2D of the sixth pull-down holding transistor T42r2, the first electrode T42r2S of the sixth pull-down holding transistor T42r2, and the first electrode T42r1S of the fifth pull-down holding transistor T42r1 are arranged in sequence along the second direction.

[0394] Specifically, as Figure 33 shown, the first source-drain layer 221 includes the first electrode T51r1S of the fifth inverter transistor T51r1, the second electrode T51r1D of the fifth inverter transistor T51r1, the first electrode of the sixth inverter transistor T51r2, and the second electrode T51r2D of the sixth inverter transistor T51r2. The first electrode T51r1S of the fifth inverter transistor T51r1, the second electrode T51r1D of the fifth inverter transistor T51r1, and the first electrode of the sixth inverter transistor T51r2 are arranged in sequence along the second direction.

[0395] Specifically, as Figure 33As shown, the first source-drain layer 221 includes the first electrode T52r1S of the seventh inverter sub-transistor T52r1, the second electrode T52r1D of the seventh inverter sub-transistor T52r1, the first electrode T52r2S of the eighth inverter sub-transistor T52r2, and the second electrode T52r2D of the eighth inverter sub-transistor T52r2. The first electrode T52r1S of the seventh inverter sub-transistor T52r1, the second electrode T52r1D of the seventh inverter sub-transistor T52r1, and the first electrode T52r2S of the eighth inverter sub-transistor T52r2 are arranged in sequence along the second direction.

[0396] Specifically, as Figure 33 As shown, the first source-drain layer 221 includes the first electrode of the fifth negative-bias protection sub-transistor T61r1, the second electrode T61r1D of the fifth negative-bias protection sub-transistor T61r1, the first electrode T61r2S of the sixth negative-bias protection sub-transistor T61r2, and the second electrode T61r2D of the sixth negative-bias protection sub-transistor T61r2. The second electrode T61r1D of the fifth negative-bias protection sub-transistor T61r1, the second electrode T61r2D of the sixth negative-bias protection sub-transistor T61r2, and the first electrode T61r2S of the sixth negative-bias protection sub-transistor T61r2 are arranged in sequence along the second direction.

[0397] Specifically, the signals output on the first low-potential signal line VGL1, the second low-potential signal line VGL2, and the third low-potential signal line VGL3 can be different.

[0398] Specifically, the signals output on the first high-potential signal line VGH1 and the second high-potential signal line VGH2 can be different.

[0399] Specifically, in the embodiments of the present application, the first signal output terminal Gn[m] of another stage of the first type of gate circuit 22a can be the first signal output terminal of the next few stages of the first type of gate circuit 22a. For example, the first signal output terminal Gn[m] of another stage of the first type of gate circuit 22a can be the first signal output terminal of the next stage of the first type of gate circuit 22a. Taking n as 3 as an example, then m can be 4; however, the embodiments of the present application are not limited thereto. The first signal output terminal Gn[m] of another stage of the first type of gate circuit 22a can be the first signal output terminal of the next two stages of the first type of gate circuit 22a or the first signal output terminal of other stages of the first type of gate circuit 22a.

[0400] Specifically, the above embodiments are described by taking some transistors including two sub-transistors as an example, but the embodiments of the present application are not limited thereto, and each transistor can include only one sub-transistor.

[0401] Specifically, as Figure 4 shown Figure 4A pixel driving circuit 21 of a display panel 2 is provided, which includes a driving transistor T1, a switching transistor T2, a reset transistor T3, and an initialization transistor T4. The driving transistor T1, the switching transistor T2, and the reset transistor T3 are connected to a first pixel node g, and the driving transistor T1 and the initialization transistor T4 are connected to a second pixel node s;

[0402] Wherein, the gate of the switching transistor T2 is electrically connected to the first signal output terminal Gn[n] of the first type of gate circuit 22a of the current stage, the gate of the initialization transistor T4 is electrically connected to the second signal output terminal INI[n] of the second type of gate circuit 22b of the current stage, and the gate of the reset transistor T3 is electrically connected to the third signal output terminal REF[n] of the third type of gate circuit 22c of the current stage. By electrically connecting the gate of the switching transistor, the gate of the initialization transistor, and the gate of the reset transistor to the first signal output terminal Gn[n] of the first type of gate circuit 22a of the current stage, the second signal output terminal INI[n] of the second type of gate circuit 22b of the current stage, and the third signal output terminal REF[n] of the third type of gate circuit 22c of the current stage respectively, signals can be input into the pixel driving circuit 21 through the gate driving circuit 22, so that the pixel driving circuit 21 can work normally.

[0403] Specifically, as Figure 2 shown, the display panel 2 further includes a light-emitting device LED. The gate of the driving transistor T1 is connected to the first node g, the first electrode of the driving transistor T1 is connected to the high-potential power supply line VDD, the second electrode of the driving transistor T1 is connected to the second node s, the first electrode of the switching transistor T2 is connected to the data line Vdata, the second electrode of the switching transistor T2 is connected to the first node g, the first electrode of the reset transistor T3 is connected to the reference line Vref, the second electrode of the reset transistor T3 is connected to the first node g, the first electrode of the initialization transistor T4 is connected to the initialization signal line Vini, the second electrode of the initialization transistor T4 is connected to the positive electrode of the light-emitting device LED, and the negative electrode of the light-emitting device LED is connected to the low-potential power supply line VSS.

[0404] Specifically, it can be understood that the display panel 2 includes multiple rows of sub-pixels, and correspondingly, multiple levels of pixel driving circuits 21 are provided to drive each sub-pixel, and correspondingly, multiple levels of gate driving circuits 22 are provided. Each level of gate driving circuit 22 can be connected to one or two corresponding rows of pixel driving circuits 21.

[0405] Specifically, the types of the transistors in the gate driving circuit 22 in the embodiments of the present application can be N-type transistors or P-type transistors. The types of the transistors in the pixel driving circuit 21 in the embodiments of the present application can be N-type transistors or P-type transistors.

[0406] Specifically, the active portions of the transistors in the gate driving circuit 22 in the embodiments of the present application may be formed by the active layer 216. The active portions of the transistors in the pixel driving circuit 21 in the embodiments of the present application may be formed by the semiconductor layer 214, or may be partially formed by the semiconductor layer 214 and partially formed by the active layer 216.

[0407] Specifically, the first electrode may be the source electrode and the second electrode may be the drain electrode; or the first electrode may be the drain electrode and the second electrode may be the source electrode.

[0408] Specifically, the above embodiments have described the display panel 2 in detail from aspects such as the circuit, timing, and transistor design of the display panel 2. It can be understood that when there is no conflict among the embodiments, the embodiments can be combined. For example, in the first direction, the second reset control line is disposed between the first reset control line and the third low potential signal line, and the low frequency signal line is disposed between the first reset control line and the third low potential signal line.

[0409] Meanwhile, the embodiments of the present application provide a display device, and the display device includes the display panel 2 as described in any one of the above embodiments.

[0410] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes, and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0411] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0412] Among the embodiments, embodiments, and related technical features of the present application, they can be combined and replaced with each other without conflict.

[0413] The above are only the preferred embodiments of the present application, and do not impose any form of limitation on the present application. However, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: include: A plurality of rows of pixels, each pixel comprising a light emitting device and a pixel driving circuit; A multi-stage gate driving circuit, electrically connected to the corresponding pixel driving circuits, respectively, each stage of the gate driving circuit includes a first type of gate circuit, a second type of gate circuit and a third type of gate circuit, the first type of gate circuit is electrically connected to at least a first clock signal line, a second clock signal line, a first high potential signal line, a first low potential signal line, a second low potential signal line, a first reset control line and a low-frequency signal line, the second type of gate circuit is electrically connected to at least the first high potential signal line, the second low potential signal line, the third clock signal line of the display panel and the second reset control line of the display panel, and the third type of gate circuit is electrically connected to at least the first high potential signal line, the second high potential signal line, the second low potential signal line and the third low potential signal line; Among them, the first reset control line, the first type of gate circuit, the second type of gate circuit, the third type of gate circuit and the third low-potential signal line are arranged along a first direction, and in the first direction, at least one of the first clock signal line, the second clock signal line, the third clock signal line, the first high-potential signal line, the second high-potential signal line, the first low-potential signal line, the second low-potential signal line, the second reset control line and the low-frequency signal line is arranged between the first reset control line and the third low-potential signal line.

2. The display panel according to claim 1, characterized in that: In the first direction, at least one of the first clock signal line, the second clock signal line, and the third clock signal line is disposed between the first reset control line and the third low potential signal line.

3. The display panel according to claim 2, characterized in that: In the first direction, the first clock signal line and the second clock signal line are arranged between the first reset control line and the third low potential signal line.

4. The display panel according to claim 3, characterized in that: In the first direction, the first clock signal line and the second clock signal line are arranged between the first reset control line and the second type gate circuit.

5. The display panel according to claim 4, characterized in that: The first type of gate circuit includes a first pull-up control module and a first pull-up module, the first pull-up control module and the first pull-up module are electrically connected to a first pull-up node, the second clock signal line includes a first group of sub-lines and a second group of sub-lines, and the first pull-up module includes: a first pull-up transistor, wherein an electrode of the first pull-up transistor is electrically connected to the first clock signal line; a second pull-up transistor, wherein an electrode of the second pull-up transistor is electrically connected to the first group of sub-lines; a third pull-up transistor, wherein an electrode of the third pull-up transistor is electrically connected to the second group of sub-lines; Among them, the first pull-up transistor, the second pull-up transistor and the third pull-up transistor are arranged in sequence along the first direction. In the first direction, the first clock signal line is arranged between the first pull-up control module and the first pull-up transistor, the first group of sub-lines is arranged between the first pull-up transistor and the second pull-up transistor, and the second group of sub-lines is arranged between the second pull-up transistor and the third pull-up transistor.

6. The display panel according to claim 2, characterized in that: In the first direction, the third clock signal line is arranged between the first reset control line and the third low potential signal line.

7. The display panel according to claim 6, characterized in that: In the first direction, the third clock signal line is arranged between the first type gate circuit and the third type gate circuit.

8. The display panel according to claim 7, characterized in that: The second type gate circuit includes a second pull-up control module and a second pull-up module, the second pull-up control module and the second pull-up module are electrically connected to a second pull-up node, and the second pull-up module is electrically connected to the third clock signal line; Wherein, in the first direction, the third clock signal line is arranged between the second pull-up control module and the second pull-up module.

9. The display panel according to any one of claims 1 to 8, characterized in that: In the first direction, the first high potential signal line is arranged between the first reset control line and the third low potential signal line.

10. The display panel according to claim 9, characterized in that: The first type of gate circuit includes a first pull-up control module, and the first pull-up control module is electrically connected to the first high-potential signal line; Wherein, in the first direction, the first high potential signal line is arranged between the first reset control line and the first pull-up control module.

11. The display panel according to any one of claims 1 to 8, characterized in that: In the first direction, the second high potential signal line is arranged between the first reset control line and the third low potential signal line.

12. The display panel according to claim 11, characterized in that: The third type gate circuit comprises a third pull-up control module and a third pull-up module, the third pull-up control module and the third pull-up module are electrically connected to a third pull-up node, and the third pull-up module is electrically connected to the second high potential signal line; Wherein, in the first direction, the second high potential signal line is arranged between the third pull-up control module and the third pull-up module.

13. The display panel according to any one of claims 1 to 8, characterized in that: In the first direction, the first low potential signal line is arranged between the first reset control line and the third low potential signal line.

14. The display panel according to claim 13, characterized in that: The first type of gate circuit includes a first pull-down maintaining module, and the first pull-down maintaining module is electrically connected to the first low potential signal line; Wherein, in the first direction, the first low potential signal line is arranged between the first pull-down maintaining module and the second type gate circuit.

15. The display panel according to any one of claims 1 to 8, characterized in that: In the first direction, the second low potential signal line is arranged between the first reset control line and the third low potential signal line.

16. The display panel according to claim 15, characterized in that: In the first direction, the second low potential signal line is arranged between the second type gate circuit and the third low potential signal line.

17. The display panel according to claim 16, characterized in that: The third type of gate circuit includes a third pull-down maintaining module, and the third pull-down maintaining module is electrically connected to the second low potential signal line; Wherein, in the first direction, the second low potential signal line is arranged between the third pull-down maintaining module and the third low potential signal line.

18. The display panel according to any one of claims 1 to 8, characterized in that: In the first direction, the second reset control line is arranged between the first reset control line and the third low potential signal line.

19. The display panel according to claim 18, characterized in that: In the first direction, the second reset control line is arranged between the first type gate circuit and the third type gate circuit.

20. The display panel according to claim 19, characterized in that: The second type gate circuit includes a second reset module, and the second reset module is electrically connected to the second reset control line; Wherein, in the first direction, the second reset control line is arranged between the second reset module and the first type gate circuit.

21. The display panel according to any one of claims 1 to 8, characterized in that: In the first direction, the low-frequency signal line is arranged between the first reset control line and the third low-potential signal line.

22. The display panel according to claim 21, characterized in that: In the first direction, the low-frequency signal line is arranged between the first reset control line and the second-type gate circuit.

23. The display panel according to claim 22, characterized in that: The first type of gate circuit includes a first inversion module, and the first inversion module is electrically connected to the low-frequency signal line; Wherein, in the first direction, the low-frequency signal line is arranged between the first inversion module and the second type of gate circuit.

24. The display panel according to claim 1, characterized in that: The first type of gate circuit includes a first pull-up control module and a first pull-up module which are electrically connected, and the first pull-up module includes a first pull-up transistor, a second pull-up transistor and a third pull-up transistor; The second type of gate circuit includes a second pull-up control module and a second pull-up module which are electrically connected; The third type of gate circuit includes a third pull-up control module and a third pull-up module which are electrically connected; The second clock signal lines include a first group of sub-lines and a second group of sub-lines; Among them, in the first direction, the first reset control line, the first high-potential signal line, the first pull-up control module, the first low-potential signal line, the low-frequency signal line, the first clock signal line, the first pull-up transistor, the first group of sub-lines, the second pull-up transistor, the second group of sub-lines, the third pull-up transistor, the second reset control line, the second pull-up control module, the third clock signal line, the second pull-up module, the third pull-up control module, the second low-potential signal line, the second high-potential signal line, the third pull-up module and the third low-potential signal line are arranged in sequence.

25. The display panel according to claim 24, characterized in that: The display panel further includes: substrate; A light shielding layer, disposed on one side of the substrate; A gate layer, disposed on a side of the light shielding layer away from the substrate; A first source-drain electrode layer, disposed on a side of the gate layer away from the light shielding layer; Wherein, the display panel includes a multi-stage gate driving circuit, at least one of the first clock signal line, the second clock signal line, the third clock signal line, the first high potential signal line, the second high potential signal line, the first low potential signal line, the second low potential signal line, the third low potential signal line, the first reset control line, the second reset control line and the low-frequency signal line includes a first part, a second part and a third part, the first part is arranged on the light shielding layer, the second part is arranged on the gate layer, the third part is arranged on the first source and drain layer, and the first part, the second part and the third part all extend along the second direction; The first parts in the gate drive circuits of each level are continuous, the second parts in the gate drive circuits of each level are disconnected, the third parts in the gate drive circuits of each level are disconnected, the first part is connected to the third part, and the second part is connected to the third part; An included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

26. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 25.

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