Gate drive circuit and display panel

Abstract

The invention discloses a gate drive circuit and a display panel, and the gate drive circuit comprises a plurality of cascaded gate drive units, and each gate drive unit comprises a first output unit which is used for outputting a pulse signal of the gate drive unit of the current stage; the second output unit is used for outputting a pulse signal of the next-stage gate driving unit; and the control unit is connected with the first output unit and the second output unit and is used for controlling the work of the first output unit and / or the second output unit so as to realize the switching between a first driving mode and a second driving mode. Through the circuit, switching between the first driving mode and the second driving mode is realized.

Description

Technical Field

[0001] The present invention relates to the field of display panels, and particularly to a gate driving circuit and a display panel. Background Art

[0002] With the continuous development of TFT display technology, the market demand for higher refresh rates will be increasing, especially in the field of game displays. Some e-sports players will highly favor high-refresh-rate displays, which will make games smoother. However, at the same time, as the refresh rate increases, the power consumption will also become higher. To solve the problem of high power consumption in high-refresh-rate scenarios, based on some existing display technologies in the current industry such as Normal (conventional display mode), a frequency doubling display technology has been introduced. The frequency doubling display technology includes DLG (Dual Line Gate, dual-line gate technology) and HSR (Hardware Super Resolution, hardware super resolution). The DLG technology changes the original progressive scanning method to scanning two lines at a time, that is, two Gates are opened simultaneously, and the same data is output for two Source lines (the content of the two lines is the same), thereby doubling the pixel charging time and doubling the refresh rate. The HSR technology is also a type of frequency doubling technology, mainly achieving differential display through timing adjustment, that is, in each frame of image, only the pixels of odd rows or even rows are rendered, and the other row is displayed by fusing the information of adjacent two rows.

[0003] Taking a UHD (Ultra High Definition) 3840*2160 resolution 240Hz refresh rate product as an example, the frequency doubling display technology reduces the display resolution to half, that is, the same data is displayed for the pixels of two rows, and the refresh rate will increase to 480Hz, which is twice the original, but the total data transmission rate remains unchanged. These display technologies update all pixels simultaneously after one frame, and the simultaneous update may cause a flickering phenomenon. However, although the frequency doubling display technology reduces the total amount of data by half, the transfer stages and frequency of the GOA (gate driving circuit) still remain unchanged. Taking UHD (ultra high definition) as an example, after adopting the DLG technology, the Gate switches at least 2160 times within one frame, and the driving IC outputs data 2160 times, and there is still room for power consumption reduction. Another example is in the AOD (always on display) display of OLED (Organic Light Emitting Display), where there are a large number of black areas in the image. The GOA scans according to pixel rows, which can be regarded as a redundant frequency, which greatly affects the lifespan of the GOA.

[0004] Therefore, in order to solve the above problems of high refresh rate and high power consumption, as well as the reduction of lifespan caused by high-frequency use of GOA, it is urgent to provide a new design of the gate driving circuit. Summary of the Invention

[0005] The main technical problem to be solved by this application is to provide a gate driving circuit and a display panel, which can realize the switching between normal driving and frequency doubling driving, as well as the multiplexing of the gate driving circuit, and is suitable for high-refresh-rate panels.

[0006] To solve the above problems, in the first aspect, this application provides a gate driving circuit, where the gate driving circuit includes: a plurality of cascaded gate driving units, and each gate driving unit includes: a first output unit for outputting a pulse signal of the current stage of the gate driving unit; a second output unit for outputting a pulse signal of the next stage of the gate driving unit; a control unit connected to the first output unit and the second output unit, and used to control the operation of the first output unit and / or the second output unit to achieve the switching between a first driving mode and a second driving mode; wherein, in the first driving mode, the control unit controls the first output unit to operate, and the second output unit does not operate, so that each gate driving unit sequentially outputs the pulse signal; in the second driving mode, the control unit controls the first output unit and the second output unit to operate to output the same adjacent two-stage pulse signals.

[0007] Wherein, each gate driving unit further includes a first cascade control unit, and the control end of the first cascade control unit is connected to the previous stage of the gate driving unit or a high-potential signal line, and is used to control the output of the first output unit of the current stage according to the previous stage of the gate driving unit or the high-potential signal line, so that the odd-stage gate driving units simultaneously output the pulse signal of the current stage and the pulse signal of the next stage, and at the same time, the first output units of the even-stage gate driving units have no output.

[0008] Among them, the control unit includes: a first register, connected to the first signal line or the output end of the previous-stage gate driving unit, for receiving the first start signal output by the first signal line or the pulse signal output by the previous-stage gate driving unit, and controlling the output of a first control signal according to the first start signal or the previous-stage pulse signal; a second register, connected to the second signal line or the output ends of the previous two-stage gate driving units, for receiving the second start signal output by the second signal line or the pulse signals output by the previous two-stage gate driving units, and controlling the output of a second control signal according to the second start signal or the previous two-stage pulse signals; among them, the output end of the first register is connected to the control end of the first output unit, and the output end of the second register is connected to the control end of the second output unit, for controlling the first output unit and / or the second output unit to work according to the first control signal and the second control signal.

[0009] Among them, the control unit further includes: a first control unit, connected to the output end of the first register and the control end of the first output unit, for controlling the first output unit to output the pulse signal of this stage according to the first control signal; a second control unit, connected to the output end of the second register and the control end of the second output unit, for controlling the second output unit to output the pulse signal of the next stage according to the second control signal; the control end of the first output unit is further connected to the second control unit, for controlling the first output unit to output the pulse signal of this stage according to the control signals output by the first control unit and the second control unit.

[0010] Among them, the first control unit includes: a first sub-control unit, connected to the first register, a high-potential signal line, and the first output unit, for controlling the output of the first output unit according to the first control signal output by the first register; a second sub-control unit, connected to the first register, a low-potential signal line, and the first output unit, for controlling the output of the first output unit according to the first control signal output by the first register; the second control unit includes: a third sub-control unit, connected to the second register, the high-potential signal line, and the second output unit, for controlling the output of the second output unit according to the second control signal output by the second register; a fourth sub-control unit, connected to the second register, the low-potential signal line, and the second output unit, for controlling the output of the second output unit according to the second control signal output by the second register; among them, the first sub-control unit and the second sub-control unit include a group of transistors with opposite driving characteristics; the third sub-control unit and the fourth sub-control unit include a group of transistors with opposite driving characteristics.

[0011] Wherein, the control end of the second output unit is connected to the second register, and the input end is connected to the first output unit, and is configured to control the output of the next-stage pulse signal according to the cascade signal transmitted by the second register, so as to realize the switching between the first driving mode and the second driving mode.

[0012] Wherein, each of the gate driving units further includes: a second cascade control unit, the input end of which is connected to the first output unit, and the output end of which is connected to the input end of the next-stage gate driving unit, and is configured to drive the next-stage gate driving unit to work according to the pulse signal; a third cascade control unit, the input end of which is connected to the first output unit, and the output end of which is connected to the input ends of the next two-stage gate driving units, and is configured to drive the next two-stage gate driving units to work according to the pulse signal; the control end of the second cascade control unit is connected to the output end of the first register; the control end of the third cascade control unit is connected to the output end of the second register.

[0013] Wherein, the first register includes: a first cascade unit, the input end of which is connected to the first signal line or the output end of the previous-stage gate driving unit, and the control end of which is connected to the first control signal line, and is configured to receive the cascade signal transmitted by the previous-stage gate driving unit; a first storage unit, which is connected to the output end of the first cascade unit, and is configured to store the cascade signal transmitted by the previous-stage gate driving unit; the second register includes: a second cascade unit, the input end of which is connected to the second signal line or the output ends of the previous two-stage gate driving units, and the control end of which is connected to the first control signal line, and is configured to receive the cascade signals transmitted by the previous two-stage gate driving units; a second storage unit, which is connected to the output end of the second cascade unit, and is configured to store the cascade signals transmitted by the previous two-stage gate driving units.

[0014] Wherein, the first register further includes: a first delay control unit, the input end of which is connected to the output end of the first cascade unit and the first storage unit, and the control end of which is connected to the second control signal line, and is configured to delay the control effect of the cascade signal transmitted by the previous-stage gate driving unit on the first output unit; a third storage unit, which is connected to the output end of the first delay control unit, and is configured to store the cascade signal transmitted by the previous-stage gate driving unit; the second register further includes: a second delay control unit, the input end of which is connected to the output end of the second cascade unit and the second storage unit, and the control end of which is connected to the second control signal line, and is configured to delay the control effect of the cascade signals transmitted by the previous two-stage gate driving units on the second output unit and / or the first output unit; a fourth storage unit, which is connected to the output end of the second delay control unit, and is configured to store the cascade signals transmitted by the previous two-stage gate driving units.

[0015] To solve the above problems, in a second aspect, the present application provides a display panel, wherein the display panel includes the gate driving circuit described in any one of the embodiments in the first aspect.

[0016] The beneficial effects of the present application are as follows: By cascading the control unit with the upper-level gate driving unit or the upper two-level gate driving units, and controlling the outputs of the first output unit and / or the second output unit according to the cascading signal, the switching between the first driving mode and the second driving mode is realized, so as to solve the problems of high power consumption in the high refresh rate display mode and the reduction of the service life caused by the high-frequency use of the gate driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a schematic structural diagram of an embodiment of the gate driving unit provided by the present application; Figure 2 It is a timing diagram of an embodiment of the first driving mode provided by the present application; Figure 3 It is a timing diagram of an embodiment of the second driving mode provided by the present application; Figure 4 It is a schematic structural diagram of an embodiment of the gate driving circuit provided by the present application; Figure 5 It is a schematic structural diagram of the gate driving circuit driven according to the first driving mode provided by the present application; Figure 6 It is a schematic structural diagram of the gate driving circuit driven according to the second driving mode provided by the present application; Figure 7 It is a schematic structural diagram of the first specific embodiment of the gate driving unit provided by the present application; Figure 8 It is a schematic structural diagram of the second specific embodiment of the gate driving unit provided by the present application; Figure 9 It is a schematic structural diagram of the third specific embodiment of the gate driving circuit provided by the present application; Figure 10 It is a schematic structural diagram of the fourth specific embodiment of the gate driving circuit provided by the present application; Figure 11 It is a schematic structural diagram of the fifth specific embodiment of the gate driving unit provided by the present application; Figure 12Schematic diagram of the sixth specific embodiment of the gate driving unit provided by the present application; Figure 13 Schematic diagram of the seventh specific embodiment of the gate driving unit provided by the present application; Figure 14 Schematic diagram of the eighth specific embodiment of the gate driving unit provided by the present application; Figure 15 Schematic diagram of the ninth specific embodiment of the gate driving circuit provided by the present application; Figure 16 Schematic diagram of the circuit structure of the first specific embodiment of the gate driving unit provided by the present application; Figure 17 First driving circuit diagram of the gate driving unit provided by the present application in the first driving mode; Figure 18 Second driving circuit diagram of the gate driving unit provided by the present application in the first driving mode; Figure 19 Third driving circuit diagram of the gate driving unit provided by the present application in the first driving mode; Figure 20 Fourth driving circuit diagram of the gate driving unit provided by the present application in the first driving mode; Figure 21 Fifth driving circuit diagram of the gate driving unit provided by the present application in the first driving mode; Figure 22 First driving circuit diagram of the odd - level gate driving unit provided by the present application in the second driving mode; Figure 23 Second driving circuit diagram of the odd - level gate driving unit provided by the present application in the second driving mode; Figure 24 Third driving circuit diagram of the odd - level gate driving unit provided by the present application in the second driving mode; Figure 25 Fourth driving circuit diagram of the odd - level gate driving unit provided by the present application in the second driving mode; Figure 26 Fifth driving circuit diagram of the odd - level gate driving unit provided by the present application in the second driving mode; Figure 27 Driving circuit diagram of the even - level gate driving unit provided by the present application in the second driving mode; Figure 28 Schematic diagram of the structure of an embodiment of the display panel provided by the present application.

[0019] Symbol description: GOA gate driving unit; GOA(n) the Nth-stage gate driving unit; scan pulse signal; scan(n) the Nth-stage pulse signal; 11 first output unit; 12 second output unit; 20 control unit; 21 first register; 22 second register; Q output terminal of the first register; P output terminal of the second register; 23 first control unit; 24 second control unit; 231 first sub-control unit; 232 second sub-control unit; 241 third sub-control unit; 242 fourth sub-control unit; 111 first sub-output unit; 112 second sub-output unit; 113 third sub-output unit; 114 fourth sub-output unit; 211 first cascading unit; C1 first storage unit / first capacitor; 221 second cascading unit; C2 second storage unit / second capacitor; XCK first control signal line; 212 first delay control unit; C3 third storage unit / third capacitor; 222 second delay control unit; C4 fourth storage unit / fourth capacitor; CK second control signal line; T1 first transistor; T2 second transistor; T3 third transistor; T4 fourth transistor; T5 fifth transistor; T6 sixth transistor; T7 seventh transistor; T8 eighth transistor; T9 ninth transistor; T10 tenth transistor; T11 eleventh transistor; T12 twelfth transistor; T13 thirteenth transistor; T14 fourteenth transistor; T15 fifteenth transistor; T16 sixteenth transistor; 1000 display panel; 1001 display area; 1002 non-display area. Detailed implementation manners

[0020] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0021] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "the" and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless clearly stated otherwise in the context. "Plural" generally includes at least two, but does not exclude the case of including at least one.

[0022] It should be understood that the term "and / or" used herein is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the character " / " in this text generally indicates that the associated objects before and after are in an "or" relationship. Terms such as "first", "second", etc. in the specification, claims, and above-mentioned drawings of this application are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence.

[0023] It should be understood that the terms "comprising", "including", or any other variation are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements not only includes those elements but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article, or device. Without further limitation, the elements defined by the statement "comprising..." do not exclude the existence of additional identical elements in the process, method, article, or device comprising the said elements.

[0024] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of this application, then such directional indications are only used to explain the relative positional relationship, movement conditions, etc. between components in a specific posture (as shown in the drawings). If the specific posture changes, then the directional indications will also change accordingly.

[0025] Referring to "embodiments" in this text means that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of this application. The occurrence of this phrase at each position in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0026] This application provides a gate driving circuit. The gate driving circuit includes: a plurality of cascaded gate driving units. For details, please refer to Figure 1 , Figure 1 which is a schematic structural diagram of an embodiment of the gate driving unit provided by this application. As Figure 1 shown, each of the gate driving units GOA includes at least: a first output unit 11, a second output unit 12, and a control unit 20.

[0027] Taking the Nth-level gate driving unit GOA(n) as an example, where N and n are natural numbers.

[0028] The first output unit 11 is used to output the pulse signal scan(n) of the current gate driving unit GOA(n), and the second output unit 12 is used to output the pulse signal scan(n+1) of the next gate driving unit GOA(n+1).

[0029] The control unit 20 is connected to the first output unit 11 and the second output unit 12, and is used to control the operation of the first output unit 11 and / or the second output unit 12 to achieve switching between the first driving mode and the second driving mode.

[0030] Specifically, the control unit 20 includes two input terminals, which are respectively connected to the previous gate driving unit GOA (n-1) or the previous two-stage gate driving unit GOA (n-2). Specifically, the control unit 20 includes a first cascade terminal and a second cascade terminal, the first cascade terminal is connected to the previous gate driving unit GOA (n-1) or the first signal line STV1, the second cascade terminal is connected to the previous two-stage gate driving unit GOA (n-2) or the second signal line STV2, and the output terminal is connected to the control terminal of the first output unit 11 and the second output unit 12, and is used to determine whether the first output unit 11 and the second output unit 12 are working outputs.

[0031] It should be noted that the first cascade terminal of the control unit 20 in the first-stage gate driving unit GOA(1) is connected to the first signal line STV1, and the second cascade terminal is connected to the second signal line STV2. The first cascade terminal of the control unit 20 in the second-stage and N-stage gate driving units GOA(n) is connected to the previous-stage gate driving unit GOA(n-1). The second cascade terminal of the control unit 20 in the second-stage gate driving unit GOA(2) can be kept suspended or connected to a high-potential signal line VGH. The second cascade terminal of the control unit 20 in the N-stage gate driving unit GOA(n) is connected to the previous two-stage gate driving units GOA(n-2). Therefore, the "and / or" connection relationship in the cascade terminals of the gate driving units, in special cases (that is, when there is no cascade object, such as in the first-stage gate driving unit), selects the former connection relationship (such as connection with the first signal line and connection with the second signal line) for connection, and in non-special cases (there is a cascade object), the latter connection relationship (such as the previous-stage / previous two-stage gate driving unit) is preferentially selected for connection. This is applicable to all subsequent cascade units (such as the first cascade unit, the second cascade unit, the first cascade control unit, the second cascade control unit, and the third cascade control unit), and will not be described one by one here.

[0032] The first driving mode is also called the normal driving mode. Figure 2 , Figure 2It is a timing diagram of an embodiment of the first driving mode provided by this application. Among them, the first signal line STV1 is used to transmit a first turn-on signal, so that the gate driving unit is driven according to the first driving mode. G1 is the scan signal scan(1) output to the first row of pixel units in the panel, G2 is the scan signal scan(1) output to the second row of pixel units in the panel, and so on. In the first driving mode, each stage of the gate driving unit GOA outputs scan signals with different timings, so as to control the pixel units in the plane to be turned on row by row, thereby realizing progressive scanning and progressive display.

[0033] The second driving mode is also called the frequency doubling driving mode (DLG mode), and specific details can be referred to Figure 3 , Figure 3 It is a timing diagram of an embodiment of the second driving mode provided by this application. Among them, the second signal line STV2 is used to transmit a second turn-on signal, so that the gate driving unit is driven according to the second driving mode. As Figure 3 shown, in the second driving mode, the gate driving unit controls the output of adjacent two rows of scan signals to be the same, that is, controls adjacent two rows of pixel units to be turned on simultaneously, and charges the same data into the pixel units of every adjacent two rows, so that the pixel units of every adjacent two rows have the same display brightness. The second driving mode can reduce the display resolution to half of the relative value and double the refresh rate. For example, in the first driving mode, the refresh rate of the display panel is 240Hz, and in the second driving mode, the refresh rate of the display panel will rise to 480Hz, which is twice the original value, but the total data transmission rate remains unchanged.

[0034] Specific details can be further referred to Figure 4 , Figure 4 It is a schematic structural diagram of an embodiment of the gate driving circuit provided by this application. As Figure 4As shown, the Nth-stage gate driving unit GOA(n) is connected to the (N - 1)th-stage (previous stage) gate driving unit GOA(n - 1) or the first signal line STV1, and to the (N - 2)th-stage (two previous stages) gate driving unit GOA(n - 2) or the second signal line STV2, and is used to output the Nth-stage (this stage) pulse signal scan(n) and / or the (N + 1)th-stage (next stage) pulse signal scan(n + 1). The (N + 1)th-stage gate driving unit GOA(n + 1) is connected to the Nth-stage gate driving unit GOA(n), and to the second signal line STV2 or the (N - 1)th-stage gate driving unit GOA(n - 1), and is used to output the (N + 1)th-stage pulse signal scan(n + 1) and / or the (N + 2)th-stage pulse signal scan(n + 2). The (N + 2)th-stage gate driving unit GOA(n + 2) is connected to the (N + 1)th-stage gate driving unit GOA(n + 1), and to the Nth-stage gate driving unit GOA(n), and is used to output the (N + 2)th-stage pulse signal scan(n + 2) and / or the (N + 3)th-stage pulse signal scan(n + 3). The (N + 3)th-stage gate driving unit GOA(n + 3) is connected to the (N + 2)th-stage gate driving unit GOA(n + 2) and the (N + 1)th-stage gate driving unit GOA(n + 1), and is used to output the (N + 3)th-stage pulse signal scan(n + 3) and / or the (N + 4)th-stage pulse signal scan(n + 4). And so on, until all the gate driving units GOA are cascaded with each other.

[0035] Among them, the (N + 1)th-stage (next stage) pulse signal scan(n + 1) output by the Nth-stage gate driving unit GOA(n) and the (N + 1)th-stage (this stage) pulse signal scan(n + 1) output by the (N + 1)th-stage gate driving unit GOA(n + 1) are the same pulse signal. That is to say, the output end of the second output unit of the Nth-stage gate driving unit GOA(n) is connected to the output end of the first output unit of the (N + 1)th-stage gate driving unit GOA(n + 1).

[0036] It should be noted that the pulse signal scan is also called a scanning signal, which is used to output to the display panel to control the data writing in the display panel.

[0037] Specifically, when N = 1, the two input terminals of the first-stage gate driving unit GOA(1) are respectively connected to the first signal line STV1 and the second signal line STV2. When N = 2, the two input terminals of the second-stage gate driving unit GOA(2) are respectively connected to the output terminal of the first-stage gate driving unit GOA(1) and a high-potential signal line VGH (or left floating). When N = 3, the two input terminals of the third-stage gate driving unit GOA(3) are respectively connected to the output terminal of the second-stage gate driving unit GOA(2) and the output terminal of the first-stage gate driving unit GOA(1). When N = 4, the input terminals of the fourth-stage gate driving unit GOA(4) are respectively connected to the output terminal of the third-stage gate driving unit GOA(3) and the output terminal of the second-stage gate driving unit GOA(2), and so on.

[0038] For details, please refer to Figure 5 , Figure 5 FIG. is a schematic structural diagram of the gate driving circuit provided by the present application driven according to the first driving mode. In the first driving mode, the control unit 20 controls the first output unit 11 to work and the second output unit 12 not to work, so that each of the gate driving units GOA sequentially outputs a local pulse signal scan(n) corresponding to the local gate driving unit GOA(n).

[0039] As Figure 5 shown, the first-stage gate driving unit GOA(1) is driven to output a first-stage (row) pulse signal scan(1), the second-stage gate driving unit GOA(2) outputs a second-stage (row) pulse signal scan(2), the third-stage gate driving unit GOA(3) outputs a third-stage (row) pulse signal scan(3), and the fourth-stage gate driving unit GOA(4) outputs a fourth-stage (row) pulse signal scan(4), and so on. That is, each gate driving unit GOA(n) sequentially outputs pulse signals with different timings. That is, the pulse signal scans of adjacent two stages (rows) have different timings and the same duty cycle. For details, please refer to Figure 2 the timing diagram in.

[0040] It should be noted that the Nth-stage pulse signal scan(n) refers to the scan signal output by the gate driving circuit to the Nth row of pixels in the panel display area. The first-stage (row) pulse signal scan(1) is the scan signal output to the first row of pixels, which is used to control the data writing of the first row of pixels; the second-stage (row) pulse signal scan(2) is the scan signal output to the second row of pixels; the third-stage (row) pulse signal scan(3) is the scan signal output to the third row of pixels; the fourth-stage (row) pulse signal scan(4) is the scan signal output to the fourth row of pixels; and so on until the entire panel is scanned.

[0041] For details, please refer toFigure 6 , Figure 6 A schematic diagram of the structure of the gate drive circuit provided in the present application driven in accordance with the second drive mode. In the second drive mode, the control unit 20 controls the first output unit 11 and / or the second output unit 12 to work to output the same adjacent two-level pulse signal scan, and the adjacent two-level pulse signal scan specifically includes outputting the current level pulse signal scan(n) and the next level pulse signal scan(n+1). The same means that the timing and duty cycle of the current level pulse signal scan(n) and the next level pulse signal scan(n+1) are the same, which can be specifically referred to in Figure 3 The timing diagram in .

[0042] like Figure 6 As shown, the first-level gate driving unit GOA (1) is driven to output the same first-level pulse signal scan (1) and the second-level pulse signal scan (2), the second-level gate driving unit GOA (2) does not output, the third-level gate driving unit GOA (3) outputs the same third-level pulse signal scan (3), the fourth-level gate driving unit GOA (4) does not output, and so on, thereby outputting the same adjacent two-level pulse signal scan. In other words, the second output end of the first-level gate driving unit GOA (1) is connected to the first output end of the second-level gate driving unit GOA (2), and the second-level pulse signal scan (2) is output through the first-level gate driving unit GOA (1).

[0043] It should be noted that N starts counting from 1, the Nth gate driving unit GOA(n) is also called the odd-numbered gate driving unit, the N+1th gate driving unit GOA(n+1) is also called the even-numbered gate driving unit, and so on.

[0044] See further Figure 7 , Figure 7 This is a schematic diagram of the structure of the first specific embodiment of the gate driving unit provided in this application. Figure 7 As shown, each gate driving unit GOA also includes a first cascade control unit 101. Specifically, the control end of the first cascade control unit 101 is connected to the previous gate driving unit GOA(n-1) or the high potential signal line VGH, and the input end is connected to the output end of the first output unit 11, and is used to control the output of the first output unit 11 of the current gate driving unit GOA(n) according to the previous gate driving unit GOA(n-1) or the high potential signal line VGH, that is, to control whether the first output unit 11 outputs the pulse signal scan(n) of the current stage.

[0045] It should be noted that the first - stage cascade control unit 101 in the first - stage gate driving unit GOA(1) is connected to the high - potential signal line VGH, and the first - stage cascade control unit 101 in the second - stage and subsequent n - th stage gate driving units GOA(n) is connected to the previous - stage gate driving unit GOA(n - 1).

[0046] Specifically, in the first driving mode, the first - stage cascade control unit 101 in each stage of the gate driving unit GOA remains conducting. The gate driving unit GOA controls the output of the pulse signal of its own stage in sequence. Refer to Figure 5 .

[0047] In the second driving mode, the first - stage cascade control unit 101 in the odd - numbered stage gate driving units GOA remains conducting, and the first - stage cascade control unit 101 in the even - numbered stage gate driving units GOA is in an off state when the odd - numbered stage gate driving units GOA output a low potential, so that the even - numbered stage gate driving units GOA have no output. Refer to Figure 6 .

[0048] Specifically, the first - stage gate driving unit GOA(1) controls both the first output unit 11 and the second output unit 12 to work. At the same time, the first - stage cascade control unit 101 in the first - stage gate driving unit GOA(1) is connected to the high - potential signal line VGH and remains conducting under the action of the high - potential signal line VGH. Therefore, the first - stage gate driving unit GOA(1) outputs the same first - stage pulse signal scan(1) and second - stage pulse signal scan(2) simultaneously.

[0049] The second - stage gate driving unit GOA(2) controls the first output unit 11 to work and maintain the output of a high potential according to the cascade signal received by the control unit 20, and the second output unit 12 does not work (has no output). At this time, when the first - stage gate driving unit GOA(1) outputs a low potential, it controls the first - stage cascade control unit 101 in the second - stage gate driving unit GOA(2) to turn off, so as to control the first output unit 11 of the second - stage gate driving unit GOA(2) to have no output. Therefore, both the first output unit 11 and the second output unit 12 of the second - stage gate driving unit GOA(2) have no output.

[0050] The third - stage gate driving unit GOA(3) controls the first output unit 11 and the second output unit 12 to work and output a low potential according to the cascade signal received by the control unit 20. At this time, the second - stage gate driving unit GOA(2) controls the first - stage cascade control unit 101 in the third - stage gate driving unit GOA(3) to remain conducting. Therefore, the third - stage gate driving unit GOA(3) controls the first output unit 11 and the second output unit 12 to have output and outputs the same third - stage pulse signal scan(3) and fourth - stage pulse signal scan(4).

[0051] The first cascading control unit 101 of the fourth-stage gate driving unit GOA(4) is turned off, so that the first output unit 11 and the second output unit 12 of the fourth-stage gate driving unit GOA(4) have no output; and so on.

[0052] It should be noted that the first-stage gate driving unit GOA(1), the third-stage gate driving unit GOA(3), etc. are also called odd-stage gate driving units GOA, and the second-stage gate driving unit GOA(2), the fourth-stage gate driving unit GOA(4), etc. are also called even-stage gate driving units GOA. In this embodiment, when the odd-stage gate driving unit GOA outputs the pulse signal of its own stage and then the pulse signal of the next stage, the even-stage gate driving unit GOA does not work; when the odd-stage gate driving unit GOA outputs a high potential, the high potential of the next-stage pulse signal is controlled and output by the even-stage gate driving unit GOA. In other words, the pulse signal of the next stage is controlled by both the odd-stage gate driving unit and the even-stage gate driving unit. Specifically, the low potential of the next-stage pulse signal is controlled and output by the odd-stage gate driving unit, and the high potential of the next-stage pulse signal is controlled and output by the even-stage gate driving unit, so that the pulse signal of the next stage has the same timing and duty cycle as the pulse signal of its own stage.

[0053] That is to say, when the odd-stage gate driving unit GOA outputs the pulse signal of its own stage and the pulse signal of the next stage at the same time, it controls the first output unit of the even-stage gate driving unit GOA to have no output, so as to avoid the conflict between the low potential output by the odd-stage gate driving unit GOA and the high potential output by the even-stage gate driving unit GOA, which affects the output of the next-stage pulse signal. It should be noted that the output of the pulse signal means the output of a low potential, that is, the potential at which the transistor in the control plane is turned on. When the pulse signal maintains a high potential, the transistor in the plane is in an off state; that is, the pulse signal in this embodiment is a low-potential pulse with a normal high potential. In other embodiments, the high potential may also be the turn-on potential of the transistor in the plane, and the low potential is the turn-off potential of the transistor in the plane, that is, the transistor in the plane is an N-type transistor that conducts at a high potential. At this time, the pulse signal is a high-potential pulse with a normal low potential, which is not limited here.

[0054] It should be noted that in other embodiments, the first cascading control units in all even-stage gate driving units may also be connected by a switching signal line, which is not limited here.

[0055] For further reference, Figure 8 , Figure 8 is a schematic structural diagram of the second specific embodiment of the gate driving unit provided by this application. As Figure 8As shown, the control unit 20 includes a first register 21 and a second register 22. Specifically, the first register 21 is connected to the first signal line STV1 or the output terminal of the previous-stage gate driving unit GOA(n - 1), and is used to receive the first start signal output by the first signal line STV1 or the pulse signal scan(n - 1) output by the previous-stage gate driving unit GOA(n - 1), and control the output terminal Q(n) of the first register 21 to output a first control signal according to the first start signal or the previous-stage pulse signal scan(n - 1).

[0056] The second register 22 is connected to the second signal line STV2 or the output terminal of the two-previous-stage gate driving unit GOA(n - 2), and is used to receive the second start signal output by the second signal line STV2 or the pulse signal scan(n - 2) output by the two-previous-stage gate driving unit GOA(n - 2), and control the output terminal P(n) of the second register 22 to output a second control signal according to the second start signal or the two-previous-stage pulse signal scan(n - 2).

[0057] Wherein, both the first control signal and the second control signal include a low-potential pulse and a high-potential pulse of the pulse signal. The low-potential pulse is a low potential (signal / voltage), and the high-potential pulse is a high potential (signal / voltage).

[0058] In this embodiment, in the first driving mode, the first signal line STV1 outputs a low-potential pulse with a normal high potential, and the second signal line STV2 can either keep transmitting a high-potential pulse or have no output. In the second driving mode, the second signal line STV2 outputs a low-potential pulse with a normal high potential, and the first signal line STV1 can either keep transmitting a high-potential pulse or have no output. In this embodiment, the switching of the driving mode of the gate driving circuit is realized through the first signal line STV1 and the second signal line STV2, specifically by controlling the output signals of the first signal line STV1 and the second signal line STV2 to realize the switching between the first driving mode and the second driving mode of the gate driving circuit.

[0059] Specifically, the output terminal Q(n) of the first register 21 is also connected to the control terminal of the first output unit 11, and the output terminal P(n) of the second register 22 is connected to the control terminal of the second output unit 12, and is used to control the first output unit 11 and / or the second output unit 12 to work according to the first control signal and the second control signal, and further control the output of the first output unit 11 and / or the second output unit 12. It should be noted that Q(n) refers to the output terminal Q(n) of the first register 21 in the Nth-stage gate driving unit GOA(n), and P(n) refers to the output terminal P(n) of the second register 22 in the Nth-stage gate driving unit GOA(n). N / n represents which stage of the gate driving unit.

[0060] Furthermore, the control end of the first output unit 11 is also connected to the output end P(n) of the second register 22, and the first register 21 and the second register 22 simultaneously control the output of the first output unit 11; the input end of the second output unit 12 is also connected to the output end of the first output unit 11, so that in the second driving mode, the second output unit 12 and the first output unit 11 simultaneously output the same pulse signal.

[0061] See further Figure 9 , Figure 9 This is a schematic diagram of the structure of the third specific embodiment of the gate drive circuit provided by this application. Figure 9 As shown, the control unit 20 further includes a first control unit 23 and a second control unit 24 .

[0062] The first control unit 23 is connected to the first register 21 and the first output unit 11. Specifically, the control end of the first control unit 23 is connected to the output end Q(n) of the first register 21. The output end of the first control unit 23 is connected to the control end of the first output unit 11. The first control unit 23 is used to control whether the first output unit 11 outputs the current level pulse signal scan(n) according to the first control signal output by the first register 21. The second control unit 24 is connected to the second register 22 and the control end of the second output unit 12. Specifically, the control end of the second control unit 24 is connected to the output end P(n) of the second register 22. The output end of the second control unit 24 is connected to the control end of the second output unit 12. The second control unit 24 is used to control whether the second output unit 12 outputs the next level pulse signal scan(n+1) according to the second control signal output by the second register 22.

[0063] The first control unit 23 and the second control unit 24 are used to output a high potential or a low potential to control the output of the first output unit 11 and the second output unit 12 .

[0064] Furthermore, the output end of the second control unit 24 is also connected to the control end of the first output unit 11, and the output of the first output unit 11 is simultaneously controlled by the first control unit 23 and the second control unit 24. Furthermore, the output end of the first output unit 11 is also connected to the input end of the second output unit 12, and the second control unit 24 controls the second output unit 12 to output the same pulse signal as the first output unit 11.

[0065] See further Figure 10 , Figure 10 This is a schematic diagram of the structure of the fourth specific embodiment of the gate drive circuit provided by the present application.Figure 10 As shown, the first control unit 23 includes a first sub-control unit 231 and a second sub-control unit 232, and the second control unit 24 includes a third sub-control unit 241 and a fourth sub-control unit 242.

[0066] The first sub-control unit 231 is connected to the first register 21 and a high-potential signal line VGH. Specifically, the control terminal of the first sub-control unit 231 is connected to the first register 21, the input terminal is connected to the high-potential signal line VGH, and the output terminal is connected to the control terminal of the first output unit 11, and is used to control the output of a high-potential control signal according to the first control signal output by the first register 21, and further control the output of the first output unit 11.

[0067] The second sub-control unit 232 is connected to the first register 21 and a low-potential signal line VGL. Specifically, the control terminal of the first sub-control unit 231 is connected to the output terminal Q(n) of the first register 21, the input terminal is connected to the low-potential signal line VGL, and the output terminal is connected to the control terminal of the first output unit 11, and is used to control the output of a low-potential control signal according to the first control signal output by the first register 21, and further control the output of the first output unit 11.

[0068] The third sub-control unit 241 is connected to the second register 22, the high-potential signal line VGH, and the second output unit 12. Specifically, the control terminal of the third sub-control unit 241 is connected to the output terminal P(n) of the second register 22, the input terminal is connected to the high-potential signal line VGH, and the output terminal is connected to the control terminal of the second output unit 12, and is used to control the output of a high-potential control signal according to the second control signal output by the second register 22, and further control whether the second output unit 12 works, that is, control its output.

[0069] The fourth sub-control unit 242 is connected to the second register 22, the low-potential signal line VGL, and the second output unit 12. Specifically, the control terminal of the fourth sub-control unit 242 is connected to the output terminal P(n) of the second register 22, the input terminal is connected to the low-potential signal line VGL, and the output terminal is connected to the control terminal of the second output unit 12, and is used to control the output of a low-potential control signal according to the second control signal output by the second register 22, and further control whether the second output unit 12 works, that is, control its output.

[0070] Furthermore, the output terminals of the third sub-control unit 241 and the fourth sub-control unit 242 are also connected to the control terminal of the first output unit 11, and are used to control the first output unit 11 to be in a working state in both the first driving mode and the second driving mode, and control the first output unit 11 to output a pulse signal including a high potential and a low potential.

[0071] It should be noted that the above-mentioned high-potential signal line VGH and low-potential signal line VGL can be swapped, and no limitation is made here. Among them, the high-potential signal line VGH is used to transmit high-potential voltage (high-potential signal), and the low-potential signal line VGL is used to transmit low-potential voltage (high-potential signal).

[0072] Among them, the first sub-control unit 231 and the second sub-control unit 232 include a group of transistors with opposite driving characteristics, that is, when the first sub-control unit 231 works / conducts, the second sub-control unit 232 does not work; when the second sub-control unit 232 works, the first sub-control unit 231 does not work. The third sub-control unit 241 and the fourth sub-control unit 242 include a group of transistors with opposite driving characteristics.

[0073] Further, please refer to Figure 11 , Figure 11 which is a schematic structural diagram of the fifth specific embodiment of the gate driving unit provided by this application. As Figure 11 shown, in a specific embodiment, the first output unit 11 includes a first sub-output unit 111, a second sub-output unit 112, a third sub-output unit 113, and a fourth sub-output unit 114. Each sub-output unit includes a switching transistor, and no limitation is made here.

[0074] Among them, the first sub-output unit 111 is connected to the first control unit 23 and the high-potential signal line VGH. Specifically, the input end of the first sub-output unit 111 is connected to the high-potential signal line VGH, the control end is connected to the output end of the first control unit 23, and the output end is connected to the output end of the first output unit 11 through the second sub-output unit 112, and is used to control the output of the first output unit 11 according to the control signal (high potential or low potential) output by the first control unit 23.

[0075] The second sub-output unit 112 is connected to the first sub-output unit 111 and the second control unit 24. Specifically, the input end of the second sub-output unit 112 is connected to the first sub-output unit 111, the control end is connected to the output end of the second control unit 24, and the output end is connected to the output end of the first output unit 11, and is used to control the output of the first output unit 11 according to the control signal output by the second control unit 24. Among them, the first sub-output unit 111 and the second sub-output unit 112 are arranged in parallel and are used to control whether the first output unit 11 outputs a high-potential pulse.

[0076] The third sub-output unit 113 is connected to the first control unit 23 and the low potential signal line VGL. Specifically, the input terminal of the third sub-output unit 113 is connected to the low potential signal line VGL, the control terminal is connected to the output terminal of the first control unit 23, and the output terminal is connected to the output terminal of the first output unit 11, and is used to control the output of the first output unit 11 according to the control signal output by the first control unit 23.

[0077] The fourth sub-output unit 114 is connected to the second control unit 24 and the low potential signal line VGL. Specifically, the input terminal of the fourth sub-output unit 114 is connected to the low potential signal line VGL, the control terminal is connected to the output terminal of the second control unit 24, and the output terminal is connected to the output terminal of the first output unit 11, and is used to control the output of the first output unit 11 according to the control signal output by the second control unit 24.

[0078] Among them, the first sub-output unit 111 and the third sub-output unit 113 are used to control the first output unit 11 to output a pulse signal including a high potential and a low potential in the first driving mode; the second sub-output unit 112 and the fourth sub-output unit 114 are used to control the first output unit 11 to output a pulse signal including a high potential and a low potential in the second driving mode.

[0079] In this specific embodiment, the first sub-output unit 111 and the third sub-output unit 113 include a group of transistors with opposite driving characteristics, so that when the first control unit 23 controls the first sub-output unit 111 to conduct / work, the third sub-output unit 113 is turned off / does not work; when the third sub-output unit 113 is controlled to work, the first sub-output unit 111 does not work. Similarly, the second sub-output unit 112 and the fourth sub-output unit 114 include a group of transistors with opposite driving characteristics.

[0080] In other embodiments, the first output unit 11 may also adopt other connection structures, which are not limited herein.

[0081] Further, the control terminal of the second output unit 12 is also connected to the output terminal of the second register 22, and the input terminal is connected to the output terminal of the first output unit 11, and is used to control whether to output the next-stage pulse signal scan(n + 1) according to the second control signal transmitted by the second register 22, so as to realize the switching between the first driving mode and the second driving mode. Specifically, the second output unit 12 is controlled to work in the second driving mode and not to work in the first driving mode.

[0082] Specifically, in the second driving mode, the second output unit 12 in the odd-level gate driving unit GOA is controlled to work, and the second output unit 12 in the even-level gate driving unit GOA does not work. In a specific embodiment, when the odd-level gate driving unit GOA drives the second output unit 12 to work, the even-level gate driving unit GOA controls the first output unit 11 to have no output through the first cascading control unit 101; when the odd-level gate driving unit GOA drives the second output unit 12 to have no output, the even-level gate driving unit GOA controls the first output unit 11 to have an output through the first cascading control unit 101. Among them, the conduction / operation of the first cascading control unit 101 is related to the second control signal of the odd-level gate driving unit GOA.

[0083] In this embodiment, the first output unit 11 maintains the output of the local pulse signal scan(n) regardless of whether it is in the first driving mode or the second driving mode.

[0084] For further reference Figure 12 , Figure 12 is a schematic structural diagram of the sixth specific embodiment of the gate driving unit provided by the present application. As Figure 12 shown, each gate driving unit GOA further includes a second cascading control unit 102 and a third cascading control unit 103.

[0085] Taking the Nth-level gate driving unit GOA(n) as an example for description.

[0086] Specifically, the input end of the second cascading control unit 102 is connected to the first output unit 11, and the output end is connected to the input end of the next-level gate driving unit GOA(n + 1), and is used to drive the next-level gate driving unit GOA(n + 1) to work according to the local pulse signal scan(n).

[0087] The input end of the third cascading control unit 103 is connected to the first output unit 11, and the output daunt is connected to the input end of the next two-level gate driving unit GOA(n + 2), and is used to drive the next two-level gate driving unit GOA(n + 2) to work according to the local pulse signal scan(n).

[0088] Furthermore, the control end of the second cascading control unit 102 is connected to the output end of the first register 21, and is used to control the cascading of the local gate driving unit GOA(n) and the next-level gate driving unit GOA(n + 1) in the first driving mode. The control end of the third cascading control unit 103 is connected to the output end of the second register 22, and is used to control the cascading of the local gate driving unit GOA(n) and the next two-level gate driving unit GOA(n + 2) in the second driving mode.

[0089] Specifically, the output end of the second cascade control unit 102 is connected to the first register 21 in the next-stage gate driving unit GOA(n+1), that is, connected to the first cascade end of the next-stage gate driving unit GOA(n+1). The output end of the third cascade control unit 103 is connected to the second register 22 of the next two-stage gate driving unit GOA(n+2), that is, connected to the second cascade end of the next two-stage gate driving unit GOA(n+2).

[0090] In a preferred embodiment, the input ends of the second cascade control unit 102 and the third cascade control unit 103 are connected to the output end of the first cascade control unit 101, that is, the second cascade control unit 102 and the third cascade control unit 103 are arranged after the first cascade control unit 101, and the second cascade control unit 102 and the third cascade control unit 103 are connected to the output end of the first output unit 11 through the first cascade control unit 101. In another preferred embodiment, the first cascade control unit 101 may also be arranged after the input ends of the second cascade control unit 102 and the third cascade control unit 103, that is, the input ends of the second cascade control unit 102 and the third cascade control unit 103 are connected to the output end of the first output unit 11 and the input end of the first cascade control unit 101, respectively.

[0091] Please refer to the following for further details Figure 13 , Figure 13 This is a schematic diagram of the structure of the seventh specific embodiment of the gate driving unit provided in this application. Figure 13 As shown, the second cascade control unit 102 includes a first switch unit 1021 and a first pull-up unit 1022. The third cascade control unit 103 includes a second switch unit 1031 and a second pull-up unit 1032.

[0092] Specifically, the first switch unit 1021 includes a switch transistor, the control end of the first switch unit 1021 is connected to the output end Q of the first register 21, and the input end is connected to the first output unit 11, and is used to control the first output unit 11 of the current gate drive unit GOA(n) to be cascaded with the next gate drive unit GOA(n+1) according to the first control signal Q output by the first register 21. The first pull-up unit 1022 includes a high potential signal line VGH and a first resistor R1, and the first pull-up unit 1022 is connected to the output end of the first switch unit 1021, and is used to keep the cascade signal input to the next gate drive unit GOA(n+1) as a high potential signal when the first switch unit 1021 is not working.

[0093] The control end of the second switch unit 1031 is connected to the output end P of the second register 22, and the input end is connected to the first output unit 11, and is used to control the first output unit 11 of the current gate driving unit GOA(n) to be cascaded with the next two gate driving units GOA(n+2) according to the second control signal output by the second register 22.

[0094] The control end of the second pull-up unit 1032 includes a high-potential signal line VGH and a second resistor R2. The second pull-up unit 1032 is connected to the output end of the second switch unit 1031 and is used to keep the cascade signal input to the next two-stage gate drive unit GOA(n+2) as a high-potential signal when the second switch unit 1031 is not working.

[0095] Please read further Figure 14 , Figure 14 This is a schematic diagram of the structure of the eighth specific embodiment of the gate driving unit provided in this application. Figure 14 As shown, the first register 21 includes a first cascade unit 211 and a first storage unit C1, and the second register 22 includes a second cascade unit 221 and a second storage unit C2.

[0096] The input end of the first cascade unit 211 is connected to the first signal line STV1 or the output end of the previous gate driving unit GOA(n-1), and the control end is connected to the first control signal line XCK, and is used to receive the cascade signal transmitted by the previous gate driving unit GOA(n-1). Specifically, the first control signal line XCK is used to control whether the first cascade unit 211 is turned on, thereby controlling whether it receives the cascade signal transmitted by the previous gate driving unit GOA(n-1).

[0097] The first storage unit C1 is connected to the output end of the first cascade unit 211, and is used to store the cascade signal transmitted by the previous gate driving unit GOA(n-1). Specifically, the first plate of the first storage unit C1 is connected to the output end of the first cascade unit 211, and the second plate is connected to a low potential signal line VGL, or a ground line.

[0098] In this embodiment, the output terminal Q of the first register 21 is the output terminal of the first cascade unit 211 and the first plate of the first storage unit C1.

[0099] The input end of the second cascade unit 221 is connected to the second signal line STV2 or the output end of the upper two-stage gate driving unit GOA(n-2), and the control end is connected to the first control signal line XCK, for receiving the cascade signal transmitted by the upper two-stage gate driving unit GOA(n-2).

[0100] The second storage unit C2 is connected to the output terminal of the second cascading unit 221 and is used to store the cascading signal transmitted by the upper two-stage gate driving unit GOA(n - 2). Specifically, the first electrode plate of the second storage unit C2 is connected to the output terminal of the second cascading unit 221, and the second electrode plate is connected to a low-potential signal line VGL.

[0101] In this embodiment, the output terminal P of the second register 22 is the output terminal of the second cascading unit 221 and the first electrode plate of the second storage unit C2.

[0102] It should be noted that the cascading signal is a pulse signal scan, which specifically includes the high potential and the low potential of the pulse signal scan.

[0103] For further reference Figure 15 , Figure 15 is a schematic structural diagram of the ninth specific embodiment of the gate driving circuit provided by the present application. As Figure 15 shown, the first register 21 further includes a first delay control unit 212 and a third storage unit C3, and the second register 22 further includes a second delay control unit 222 and a fourth storage unit C4.

[0104] The input terminal of the first delay control unit 212 is connected to the output terminal of the first cascading unit 211 and the first storage unit C1, and the control terminal is connected to the second control signal line CK, and is used to delay the control / driving effect of the cascading signal transmitted by the upper-stage gate driving unit GOA(n - 1) on the first output unit 11 or the first control unit 23.

[0105] The third storage unit C3 is connected to the output terminal of the first delay control unit 212 and is used to store the cascading signal transmitted by the upper-stage gate driving unit GOA(n - 1).

[0106] The input terminal of the second delay control unit 222 is connected to the output terminal of the second cascading unit 221 and the second storage unit C2, and the control terminal is connected to the second control signal line CK, and is used to delay the control / driving effect of the cascading signal transmitted by the upper two-stage gate driving unit GOA(n - 2) on the second output unit 12 and / or the first output unit 11, or delay the control effect on the second control unit 24.

[0107] The fourth storage unit C4 is connected to the output terminal of the second delay control unit 222 and is used to store the cascading signal transmitted by the upper two-stage gate driving unit GOA(n - 2).

[0108] In this embodiment, the second electrode plates of the third storage unit C3 and the fourth storage unit C4 are also connected to a fixed signal line, specifically connected to a low-potential signal line VGL.

[0109] In this embodiment, the output terminal Q of the first register 21 is the output terminal of the first delay control unit 212 and the first electrode plate of the third storage unit C3. The output terminal P of the second register 22 is the output terminal of the second delay control unit 222 and the first electrode plate of the fourth storage unit C4.

[0110] For details, please refer to Figure 16 , Figure 16 , which is a schematic circuit diagram of a specific embodiment of the gate driving unit provided by this application. As Figure 16 shown.

[0111] The first register 21 includes a first transistor T1, a first capacitor C1, a second transistor T2, and a third capacitor C3.

[0112] The second register 22 includes a third transistor T3, a second capacitor C2, a fourth transistor T4, and a fourth capacitor C4.

[0113] The first control unit 23 includes a fifth transistor T5 and a sixth transistor T6.

[0114] The second control unit 24 includes a seventh transistor T7 and an eighth transistor T8.

[0115] The first output unit 11 includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12.

[0116] The second output unit 12 includes a thirteenth transistor T13.

[0117] The first cascade control unit 101 includes a fourteenth transistor T14.

[0118] The second cascade control unit 102 includes a fifteenth transistor T15.

[0119] The third cascade control unit 103 includes a sixteenth transistor T16.

[0120] For further details, please refer to Figures 17 - 21 , Figures 17 - 21 , which is a driving process diagram of the gate driving unit provided by this application in the first driving mode. Specifically, Figure 17 is the first driving circuit diagram of the gate driving unit provided by this application in the first driving mode. Figure 18 is the second driving circuit diagram of the gate driving unit provided by this application in the first driving mode. Figure 19 is the third driving circuit diagram of the gate driving unit provided by this application in the first driving mode. Figure 20 is the fourth driving circuit diagram of the gate driving unit provided by this application in the first driving mode. Figure 21The fifth driving circuit diagram of the gate driving unit provided by this application in the first driving mode.

[0121] The first driving mode includes a sampling stage, an output stage 1, an output stage 2, a holding stage 1, and a holding stage 2.

[0122] In the sampling stage, the first transistor T1 and the third transistor T3 are turned on, the first register 21 writes the cascading signal, and a low-potential pulse output by the previous-stage gate driving unit GOA(n - 1) is stored on the first capacitor C1. The third capacitor C3 in the first register 21 maintains the high-potential voltage of the previous timing, that is, the first control signal output by the output terminal Q(n) of the first register 21 remains high. The fourth capacitor C4 in the second register 22 maintains the high-potential voltage of the previous timing, that is, the second control signal output by the output terminal P(n) of the second register 22 also remains high. The fifth transistor T5 in the first control unit 23 is turned on, the first control unit 23 outputs a high potential, and further controls the ninth transistor T9 in the first output unit 11 to be turned on. The seventh transistor T7 in the second control unit 24 is turned on, the second control unit 24 outputs a high potential, and further controls the tenth transistor T10 in the first output unit 11 to be turned on. The output terminal P(n - 1) of the second register 22 in the previous-stage gate driving unit GOA(n - 1) remains outputting a high potential, thereby controlling the fourteenth transistor T14 in the first cascading control unit 101 to remain turned on. Therefore, the local pulse signal scan(n) output by the local gate driving unit GOA(n) is a high-potential pulse. The output terminal Q(n) of the first register 21 controls the fifteenth transistor T15 of the second cascading control unit 102 to turn off, so that the first cascading terminal output to the next-stage gate driving unit GOA(n + 1) is a high-potential signal. The output terminal P(n) of the second register 22 controls the sixteenth transistor T16 of the third cascading control unit 103 to turn off, so that the second cascading terminal output to the next two-stage gate driving unit GOA(n + 2) is a high-potential signal. The output terminal P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to turn off. Therefore, the local gate driving unit GOA(n) does not output the next-stage pulse signal scan(n + 1). For details, please refer to Figure 17 .

[0123] In the output stage 1, the first transistor T1 and the third transistor T3 are turned off, the second transistor T2 and the fourth transistor T4 are turned on. The low-potential voltage stored in the first capacitor C1 in the previous timing is transmitted through the second transistor T2 to the third capacitor C3 for storage, and the fourth capacitor C4 stores a high potential. Therefore, the first control signal output from the output terminal Q(n) of the first register 21 is at a low potential. The second control signal output from the output terminal P(n) of the second register 22 remains at a high potential. The sixth transistor T6 in the first control unit 23 is turned on, and the first control unit 23 outputs a low-potential signal to control the eleventh transistor T11 in the first output unit 11 to be turned on. The output terminal of the second register 22 controls the seventh transistor T7 in the second control unit 24 to be turned on, and the second control unit 24 outputs a high potential, thereby controlling the tenth transistor T10 in the first output unit 11 to be turned on. The output terminal P(n - 1) of the second register 22 in the upper-level gate driving unit GOA(n - 1) remains outputting a high potential, thereby controlling the fourteenth transistor T14 in the first cascade control unit 101 to remain turned on. Therefore, through the eleventh transistor T11 and the fourteenth transistor T14, the local pulse signal scan(n) output by the local gate driving unit GOA(n) is a low-potential pulse. The output terminal Q(n) of the first register 21 controls the fifteenth transistor T15 of the second cascade control unit 102 to be turned on, enabling the first output unit 11 of the local gate driving unit GOA(n) to be cascaded with the next-level gate driving unit GOA(n + 1), so that the first cascade terminal output to the next-level gate driving unit GOA(n + 1) is a low-potential signal. The output terminal P(n) of the second register 22 controls the sixteenth transistor T16 of the third cascade control unit 103 to be turned off, so that the second cascade terminal output to the next two-level gate driving unit GOA(n + 2) is a high-potential signal. The output terminal P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to be turned off. Therefore, the local gate driving unit GOA(n) does not output the next-level pulse signal scan(n + 1). For details, please refer to Figure 18 。

[0124] In the output stage 2, the first transistor T1 and the third transistor T3 are turned on, the second transistor T2 and the fourth transistor T4 are turned off, and the first capacitor C1 and the second capacitor C2 store a high potential. The third capacitor C3 maintains the low potential stored in the previous timing, and the fourth capacitor C4 maintains a high potential. Therefore, the first control signal output from the output terminal Q(n) of the first register 21 remains at a low potential. The second control signal output from the output terminal P(n) of the second register 22 remains at a high potential. The sixth transistor T6 in the first control unit 23 is turned on, and the first control unit 23 outputs a low potential signal, thereby controlling the eleventh transistor T11 in the first output unit 11 to be turned on. The output terminal of the second register 22 controls the seventh transistor T7 in the second control unit 24 to be turned on, and the second control unit 24 outputs a high potential, thereby controlling the tenth transistor T10 in the first output unit 11 to be turned on. The output terminal P(n - 1) of the second register 22 in the upper-level gate driving unit GOA(n - 1) remains outputting a high potential, thereby controlling the fourteenth transistor T14 in the first cascade control unit 101 to remain turned on. Therefore, through the eleventh transistor T11 and the fourteenth transistor T14, the local pulse signal scan(n) output by the local gate driving unit GOA(n) is a low potential pulse. The output terminal Q(n) of the first register 21 controls the fifteenth transistor T15 of the second cascade control unit 102 to be turned on, cascading the first output unit 11 of the local gate driving unit GOA(n) with the next-level gate driving unit GOA(n + 1), so that the first cascade terminal output to the next-level gate driving unit GOA(n + 1) is a low potential signal. The output terminal P(n) of the second register 22 controls the sixteenth transistor T16 of the third cascade control unit 103 to be turned off, so that the second cascade terminal output to the next two-level gate driving unit GOA(n + 2) is a high potential signal. The output terminal P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to be turned off. Therefore, the local gate driving unit GOA(n) does not output the next-level pulse signal scan(n + 1). For details, please refer to Figure 19 。

[0125] In the holding stage 1, the first transistor T1 and the third transistor T3 are turned off, and the second transistor T2 and the fourth transistor T4 are turned on. The high potential stored on the first capacitor C1 is transmitted through the second transistor T2 to the third capacitor C3 and stored. The fourth capacitor C4 maintains the storage of the high potential. Therefore, the first control signal output from the output terminal Q(n) of the first register 21 is at a high potential. The first control signal output from the output terminal Q(n) of the first register 21 is at a high potential. The fifth transistor T5 in the first control unit 23 is turned on, and the first control unit 23 outputs a high potential signal, thereby controlling the ninth transistor T9 in the first output unit 11 to be turned on. The output terminal P(n) of the second register 22 controls the seventh transistor T7 in the second control unit 24 to be turned on, and the second control unit 24 outputs a high potential, thereby controlling the tenth transistor T10 in the first output unit 11 to be turned on. The output terminal P(n - 1) of the second register 22 in the upper-level gate driving unit GOA(n - 1) maintains the output of a high potential, thereby controlling the fourteenth transistor T14 in the first cascade control unit 101 to remain turned on. Therefore, through the ninth transistor T9 and the tenth transistor T10, the local pulse signal scan(n) output from the local gate driving unit GOA(n) is a high potential pulse. The output terminal Q(n) of the first register 21 controls the fifteenth transistor T15 of the second cascade control unit 102 to be turned off, so that the first cascade terminal output to the next-level gate driving unit GOA(n + 1) is a high potential signal. The output terminal P(n) of the second register 22 controls the sixteenth transistor T16 of the third cascade control unit 103 to be turned off, so that the second cascade terminal output to the next two-level gate driving unit GOA(n + 2) is a high potential signal. The output terminal P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to be turned off. Therefore, the local gate driving unit GOA(n) does not output the next-level pulse signal scan(n + 1). For details, please refer to Figure 20 。

[0126] In the holding stage 2, the first transistor T1 and the third transistor T3 are turned on, the second transistor T2 and the fourth transistor T4 are turned off, and the first capacitor C1 and the second capacitor C2 store a high potential. The third capacitor C3 and the fourth capacitor C4 maintain the stored high potential. Therefore, the first control signal output from the output terminal Q(n) of the first register 21 is at a high potential. The second control signal output from the output terminal P(n) of the second register 22 is at a high potential. The fifth transistor T5 in the first control unit 23 is turned on, and the first control unit 23 outputs a high potential signal, thereby controlling the ninth transistor T9 in the first output unit 11 to be turned on. The output terminal of the second register 22 controls the seventh transistor T7 in the second control unit 24 to be turned on, and the second control unit 24 outputs a high potential, thereby controlling the tenth transistor T10 in the first output unit 11 to be turned on. The output terminal P(n - 1) of the second register 22 in the upper-stage gate driving unit GOA(n - 1) remains outputting a high potential, thereby controlling the fourteenth transistor T14 in the first cascade control unit 101 to remain turned on. Therefore, through the ninth transistor T9 and the tenth transistor T10, the local pulse signal scan(n) output by the local gate driving unit GOA(n) is a high potential pulse. The output terminal Q(n) of the first register 21 controls the fifteenth transistor T15 of the second cascade control unit 102 to be turned off, so that the first cascade terminal output to the next-stage gate driving unit GOA(n + 1) is a high potential signal. The output terminal P(n) of the second register 22 controls the sixteenth transistor T16 of the third cascade control unit 103 to be turned off, so that the second cascade terminal output to the next two-stage gate driving unit GOA(n + 2) is a high potential signal. The output terminal P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to be turned off. Therefore, the local gate driving unit GOA(n) does not output the next-stage pulse signal scan(n + 1). For details, please refer to Figure 21 。

[0127] In the holding stage 1 and the holding stage 2, the third capacitor C3 is covered by the high potential of the first capacitor C1, and the first register 21 will continuously maintain the output of a high potential. Therefore, the local GOA(n) maintains the output of the local pulse signal scan(n) at a high potential. It should be noted that in the first driving mode of this embodiment, the input terminal (i.e., the second cascade terminal) of the second register 22 is connected to the high potential signal line VGH. In other embodiments, the input terminal (i.e., the second cascade terminal) of the second register 22 can be set to be floating, which is not limited herein.

[0128] Each stage of the gate driving unit GOA (including the odd-stage gate driving unit and the even-stage gate driving unit) is as described above Figures 17 to 21It should be noted that the gate of the fourteenth transistor T14 in the first-stage gate driving unit GOA (1) is connected to a high-potential signal line VGH. In other embodiments, a 0th-stage gate driving unit GOA (0) may be provided, and the input terminal of the first-stage gate driving unit GOA (1) is cascaded with GOA (0), wherein the output terminal of the 0th-stage gate driving unit GOA (0) is suspended, that is, no output is provided.

[0129] For the second drive mode, please refer to Figures 22 - 26 , Figures 22 - 26 This is a driving process diagram of the odd-numbered gate driving unit provided in the present application in the second driving mode. Specifically, Figure 22 This is a first driving circuit diagram of an odd-numbered gate driving unit provided in the present application in a second driving mode. Figure 23 This is a second driving circuit diagram of the odd-numbered gate driving unit provided by the present application in the second driving mode. Figure 24 This is a third driving circuit diagram of the odd-numbered gate driving unit provided in the present application in the second driving mode. Figure 25 This is a fourth driving circuit diagram of the odd-numbered gate driving unit provided in the present application in the second driving mode. Figure 26 This is a fifth driving circuit diagram of the odd-numbered gate driving unit provided in the present application in the second driving mode.

[0130] The second driving mode is divided into odd-numbered gate driving units GOA and even-numbered gate driving units GOA.

[0131] The description is made by taking the current-stage (Nth-stage) gate driving unit GOA(n) as an odd-numbered-stage gate driving unit.

[0132] The odd-numbered gate driving unit GOA includes a sampling phase, an output phase 1, an output phase 2, a holding phase 1 and a holding phase 2.

[0133] In the sampling stage, the first transistor T1 and the third transistor T3 are turned on. The second register 22 writes the cascaded signal, and the low-potential pulse output by the gate driving unit GOA(n - 2) of the previous two stages (odd stages) is stored on the first capacitor C1. The third capacitor C3 in the first register 21 maintains the high-potential voltage of the previous timing, that is, the first control signal output by the output terminal Q(n) of the first register 21 remains high. The fourth capacitor C4 in the second register 22 maintains the high-potential voltage of the previous timing, that is, the second control signal output by the output terminal P(n) of the second register 22 also remains high. The fifth transistor T5 in the first control unit 23 is turned on, and the first control unit 23 outputs a high potential, thereby controlling the ninth transistor T9 in the first output unit 11 to be turned on. The seventh transistor T7 in the second control unit 24 is turned on, and the second control unit 24 outputs a high potential, thereby controlling the tenth transistor T10 in the first output unit 11 to be turned on. In the gate driving unit GOA(n) of this stage (odd stage), the output terminal P(n - 1) of the second register 22 in the gate driving unit GOA(n - 1) of the previous stage (even stage) remains outputting a high potential, thereby controlling the fourteenth transistor T14 in the first cascaded control unit 101 to remain turned on. Therefore, the pulse signal scan(n) of this stage output by the gate driving unit GOA(n) is a high-potential pulse. The output terminal Q(n) of the first register 21 controls the fifteenth transistor T15 of the second cascaded control unit 102 to turn off, so that the first cascaded terminal output to the next-stage gate driving unit GOA(n + 1) is a high-potential signal. The output terminal P(n) of the second register 22 controls the sixteenth transistor T16 of the third cascaded control unit 103 to turn off, so that the second cascaded terminal output to the gate driving units GOA(n + 2) of the next two stages is a high-potential signal. The output terminal P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to turn off. Therefore, the next-stage pulse signal scan(n + 1) is not output by the gate driving unit GOA(n) of this stage. For details, please refer to Figure 22 。

[0134] It should be noted that when the gate driving unit GOA(n) of this stage (odd stage) does not output the next-stage pulse signal scan(n + 1), the next-stage (even stage) gate driving unit GOA(n + 1) outputs the next-stage pulse signal scan(n + 1) with a high potential. As Figure 22 shown, the second control signal output by the output terminal P(n) of the second register 22 in the gate driving unit GOA(n) of this stage (odd stage) is high. At this time, the fourteenth transistor T14 in the next-stage (even stage) gate driving unit GOA(n + 1) can be controlled to be turned on, so that the pulse signal scan(n + 1) output by the next-stage (even stage) gate driving unit GOA(n + 1) at this timing stage is high.

[0135] In the output stage 1, the first transistor T1 and the third transistor T3 are turned off, the second transistor T2 and the fourth transistor T4 are turned on, and the low potential voltage stored by the second capacitor C2 in the previous timing is transmitted to the fourth capacitor C4 through the fourth transistor T4 for storage, and the fourth capacitor C4 stores a high potential, and the third capacitor C3 keeps storing a high potential. Therefore, the first control signal output by the output terminal Q(n) of the first register 21 is a high potential. The second control signal output by the output terminal P(n) of the second register 22 is a low potential. The fifth transistor T5 in the first control unit 23 is turned on, and the first control unit 23 outputs a high potential signal to control the ninth transistor T9 in the first output unit 11 to be turned on. The output terminal P(n) of the second register 22 controls the eighth transistor T8 in the second control unit 24 to be turned on, and the second control unit 24 outputs a low potential, thereby controlling the twelfth transistor T12 in the first output unit 11 to be turned on. The output terminal P(n-1) of the second register 22 in the previous stage (even-numbered stage) gate driving unit GOA(n-1) maintains a high potential output, thereby controlling the fourteenth transistor T14 in the first cascade control unit 101 in the current stage (odd-numbered stage) gate driving unit GOA(n) to remain turned on. Therefore, the current stage pulse signal scan(n) output by the current stage gate driving unit GOA(n) can be a low potential pulse through the twelfth transistor T12 and the fourteenth transistor T14. The output terminal Q(n) of the first register 21 also controls the fifteenth transistor T15 of the second cascade control unit 102 to be turned off, so that the first cascade terminal output to the next stage (even-numbered stage) gate driving unit GOA(n+1) is a high potential signal. The output terminal P(n) of the second register 22 controls the sixteenth transistor T16 of the third cascade control unit 103 to turn on, so that the first output unit 11 of the current gate driving unit GOA(n) is cascaded with the next two gate driving units GOA(n+2), so that the second cascade terminal output to the next two gate driving units GOA(n+2) is a low potential signal. The output terminal P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to turn on. Therefore, the current (odd-numbered) gate driving unit GOA(n) also outputs the next level pulse signal scan(n+1), and the output next level pulse signal scan(n+1) is a low potential pulse. For details, please refer to Figure 23 .

[0136] At this stage, the output terminal P(n) of the second register 22 in the current stage (odd stage) gate driving unit GOA(n) also controls the fourteenth transistor T14 in the first cascade control unit 101 of the next stage (even stage) gate driving unit GOA(n + 1) to be cut off, so that the next stage (even stage) gate driving unit GOA(n + 1) does not output the next stage pulse signal scan(n + 1), and at the same time, the next stage (even stage) gate driving unit GOA(n + 1) also does not output the next two stage pulse signals scan(n + 2).

[0137] In the output stage 2, the first transistor T1 and the third transistor T3 are turned on, the second transistor T2 and the fourth transistor T4 are turned off, and the first capacitor C1 and the second capacitor C2 store a high potential. The fourth capacitor C4 maintains the low potential stored in the previous timing, and the third capacitor C3 maintains the high potential. Therefore, the first control signal output from the output terminal Q(n) of the first register 21 remains at a high potential. The second control signal output from the output terminal P(n) of the second register 22 remains at a low potential. The fifth transistor T5 in the first control unit 23 is turned on, and the first control unit 23 outputs a high potential signal, which in turn controls the ninth transistor T9 in the first output unit 11 to be turned on. The output terminal of the second register 22 controls the eighth transistor T8 in the second control unit 24 to be turned on, and the second control unit 24 outputs a low potential, which in turn controls the twelfth transistor T12 in the first output unit 11 to be turned on. The output terminal P(n - 1) of the second register 22 in the previous stage (even stage) gate driving unit GOA(n - 1) remains outputting a high potential, so as to control the fourteenth transistor T14 in the first cascade control unit 101 of the current stage (odd stage) gate driving unit GOA(n) to remain turned on. Therefore, through the twelfth transistor T12 and the fourteenth transistor T14, the current stage pulse signal scan(n) output by the current stage gate driving unit GOA(n) is a low potential pulse. The output terminal Q(n) of the first register 21 also controls the fifteenth transistor T15 of the second cascade control unit 102 to be turned off, so that the first cascade terminal output to the next stage (even stage) gate driving unit GOA(n + 1) is a high potential signal. The output terminal P(n) of the second register 22 controls the sixteenth transistor T16 of the third cascade control unit 103 to be turned on, cascading the first output unit 11 of the current stage gate driving unit GOA(n) with the next two stage gate driving units GOA(n + 2), so that the second cascade terminal output to the next two stage gate driving units GOA(n + 2) is a low potential signal. The output terminal P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to be turned on. Therefore, the next stage pulse signal scan(n + 1) output by the current stage (odd stage) gate driving unit GOA(n) is a low potential pulse. For details, please refer to Figure 24 。

[0138] During the holding stage 1, the first transistor T1 and the third transistor T3 are turned off, and the second transistor T2 and the fourth transistor T4 are turned on. The high potential stored on the second capacitor C2 is transmitted through the fourth transistor T4 to the fourth capacitor C4 and stored. The third capacitor C3 maintains the storage of the high potential. Therefore, the first control signal output from the output terminal Q(n) of the first register 21 is at a high potential. The second control signal output from the output terminal P(n) of the second register 22 is at a high potential. The fifth transistor T5 in the first control unit 23 is turned on, and the first control unit 23 outputs a high potential signal, thereby controlling the ninth transistor T9 in the first output unit 11 to be turned on. The output terminal of the second register 22 controls the seventh transistor T7 in the second control unit 24 to be turned on, and the second control unit 24 outputs a high potential, thereby controlling the tenth transistor T10 in the first output unit 11 to be turned on. The output terminal P(n - 1) of the second register 22 in the upper-level (even-level) gate driving unit GOA(n - 1) maintains the output of a high potential, thereby controlling the fourteenth transistor T14 in the first cascade control unit 101 to remain turned on. Therefore, through the ninth transistor T9 and the tenth transistor T10, the local pulse signal scan(n) output by the local gate driving unit GOA(n) is a high potential pulse. The output terminal Q(n) of the first register 21 controls the fifteenth transistor T15 of the second cascade control unit 102 to be turned off, so that the first cascade terminal output to the next-level gate driving unit GOA(n + 1) is a high potential signal. The output terminal P(n) of the second register 22 controls the sixteenth transistor T16 of the third cascade control unit 103 to be turned off, so that the second cascade terminal output to the next two-level gate driving unit GOA(n + 2) is a high potential signal. The output terminal P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to be turned off. Therefore, the local gate driving unit GOA(n) does not output the next-level pulse signal scan(n + 1). For details, please refer to Figure 25 .

[0139] In the holding stage 2, the first transistor T1 and the third transistor T3 are turned on, the second transistor T2 and the fourth transistor T4 are turned off, and the first capacitor C1 and the second capacitor C2 store a high potential. The third capacitor C3 and the fourth capacitor C4 maintain the stored high potential. Therefore, the first control signal output from the output terminal Q(n) of the first register 21 is at a high potential. The second control signal output from the output terminal P(n) of the second register 22 is at a high potential. The fifth transistor T5 in the first control unit 23 is turned on, and the first control unit 23 outputs a high-potential signal, thereby controlling the ninth transistor T9 in the first output unit 11 to be turned on. The output terminal of the second register 22 controls the seventh transistor T7 in the second control unit 24 to be turned on, and the second control unit 24 outputs a high potential, thereby controlling the tenth transistor T10 in the first output unit 11 to be turned on. The output terminal P(n - 1) of the second register 22 in the upper-stage (even-stage) gate driving unit GOA(n - 1) maintains the output of a high potential, thereby controlling the fourteenth transistor T14 in the first cascade control unit 101 to remain turned on. Therefore, through the ninth transistor T9 and the tenth transistor T10, the local pulse signal scan(n) output by the local gate driving unit GOA(n) is a high-potential pulse. The output terminal Q(n) of the first register 21 controls the fifteenth transistor T15 of the second cascade control unit 102 to be turned off, so that the first cascade terminal output to the next-stage gate driving unit GOA(n + 1) is a high-potential signal. The output terminal P(n) of the second register 22 controls the sixteenth transistor T16 of the third cascade control unit 103 to be turned off, so that the second cascade terminal output to the next two-stage gate driving unit GOA(n + 2) is a high-potential signal. The output terminal P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to be turned off. Therefore, the local gate driving unit GOA(n) does not output the next-stage pulse signal scan(n + 1). For details, please refer to Figure 26 。

[0140] In the holding stage, the fourth capacitor C4 is covered by the high potential on the second capacitor C2, and the first register 21 will continuously maintain the output of a high potential. Therefore, regardless of whether the cascade unit (T1 / T3) is turned on or not, the local pulse signal scan(n) output by the local gate driving unit GOA(n) remains at a high potential.

[0141] Furthermore, the present application also provides a driving circuit diagram of the even-stage gate driving unit in the second driving mode. For details, please refer to Figure 27 , Figure 27 is the driving circuit diagram of the even-stage gate driving unit provided by the present application in the second driving mode, or rather, Figure 27This is the driving circuit diagram of the (N + 1)-th level gate driving unit provided by this application in the second driving mode. Taking the (N + 1)-th level gate driving unit GOA(n + 1) as an even-level gate driving unit as an example for description. As Figure 27 shown, the first cascade terminal of the (N + 1)-th level (even-level) gate driving unit GOA(n + 1) is connected to the N-th level (odd-level) gate driving unit. Please refer to Figures 22 - 26 the output terminal GOA(n + 1) shown in it. The GOA(n) output by the N-th level (odd-level) gate driving unit are all high-potential signals. The second cascade terminal of the (N + 1)-th level (even-level) gate driving unit GOA(n + 1) is connected to the upper two levels (the (N - 1)-th level / even-level) gate driving units. For the even-level gate driving unit, please refer to Figure 27 shown in it. The cascade signals output by the (N - 1)-th level (even-level) gate driving unit are also all high-potential signals. Therefore, both input terminals of the (N + 1)-th level (even-level) gate driving unit GOA(n + 1) input high-potential signals, enabling the (N + 1)-th level (even-level) gate driving unit GOA(n + 1) to be driven according to the Figures 25 - 26 gate driving circuit shown in it. When the output terminal P(n) of the second register 22 in the upper level (the N-th level / odd-level) gate driving unit GOA(n) outputs a low potential, it can control the fourteenth transistor T14 in the first cascade control unit 101 to turn off, thereby controlling the (N + 1)-th level (even-level) gate driving unit GOA(n + 1) not to output the pulse signal scan(n + 1) of this level. Therefore, the (N + 1)-th level (even-level) gate driving unit GOA(n + 1) does not output the pulse signal scan(n + 1) of the (N + 1)-th level (this level / even-level) and the pulse signal scan(n + 2) of the (N + 2)-th level (the next level / odd-level).

[0142] It should be noted that in the second driving mode, when the odd-level gate driving units output according to output stage 1 and output stage 2, the even-level gate driving units are driven according to Appendix Figure 27 and thus have no output. When the odd-level gate driving units are driven according to Figure 22 , Figure 25 , Figure 26 , the even-level gate driving units are driven according to Figures 25 - 26 shown in it. Thus, adjacent two-level gate driving units output the same pulse signals.

[0143] This application also provides a display panel. For details, please refer to Figure 28 , Figure 28 which is the structural schematic diagram of an embodiment of the display panel provided by this application. As Figure 28As shown in the figure, the display panel 1000 includes a display area 1001 and a non-display area 1002. The gate driving circuit described in any of the above embodiments is provided in the non-display area 1002 on one side or opposite sides of the display panel 1000. The gate driving circuit includes a plurality of cascaded gate driving units. The gate driving circuit sequentially transmits a scan signal scan(n), that is, a pulse signal scan(n), to each row of pixel units in the display area 1001. Among them, the pulse signal scan(n) is a low-potential pulse with a normal high potential.

[0144] In the above embodiment, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, and the fourteenth transistor T14 in the above gate driving circuit are N-type transistors, and the rest of the transistors are P-type transistors. In other embodiments, it may also be that the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, and the fourteenth transistor T14 are P-type transistors, and the rest of the transistors are N-type transistors, which is not limited herein.

[0145] In this application, the control unit in the above gate driving circuit is cascaded with the previous-stage gate driving unit or the previous two-stage gate driving units, and controls the output of the first output unit and / or the second output unit according to the cascaded signal, thereby realizing the switching between the first driving mode and the second driving mode to solve the problems of high power consumption in the high-frame rate display mode and the reduction of the service life caused by the high-frequency use of the gate driving circuit.

[0146] The above are only embodiments of this application, and do not limit the patent scope of this application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of this application, or directly or indirectly applied to other related technical fields, is equally included in the patent protection scope of this application.

Claims

1. A gate driving circuit, characterized in that, Including: A plurality of cascaded gate driving units, each of the gate driving units including: A first output unit for outputting a pulse signal of the current stage of the gate driving unit; A second output unit for outputting a pulse signal of the next stage of the gate driving unit; A control unit connected to the first output unit and the second output unit, for controlling the operation of the first output unit and / or the second output unit to achieve the switching between a first driving mode and a second driving mode; Wherein, in the first driving mode, the control unit controls the first output unit to operate, and the second output unit does not operate, so that each of the gate driving units sequentially outputs the pulse signal; In the second driving mode, the control unit controls the first output unit and the second output unit to operate to output the same adjacent two-stage pulse signals.

2. The gate driving circuit according to claim 1, wherein Each of the gate driving units further includes a first cascaded control unit, and a control end of the first cascaded control unit is connected to the previous-stage gate driving unit or a high-potential signal line, for controlling the output of the first output unit of the current stage according to the previous-stage gate driving unit or the high-potential signal line, so that the odd-stage gate driving units simultaneously output the pulse signal of the current stage and the pulse signal of the next stage, and at the same time, the first output units of the even-stage gate driving units have no output.

3. The gate driving circuit according to claim 1, wherein The control unit includes: A first register connected to a first signal line or an output end of the previous-stage gate driving unit, for receiving a first start signal output by the first signal line or a pulse signal output by the previous-stage gate driving unit, and controlling the output of a first control signal according to the first start signal or the previous-stage pulse signal; A second register connected to a second signal line or an output end of the two previous-stage gate driving units, for receiving a second start signal output by the second signal line or a pulse signal output by the two previous-stage gate driving units, and controlling the output of a second control signal according to the second start signal or the two previous-stage pulse signals; Wherein, an output end of the first register is connected to a control end of the first output unit, and an output end of the second register is connected to a control end of the second output unit, for controlling the operation of the first output unit and / or the second output unit according to the first control signal and the second control signal.

4. The gate driving circuit according to claim 3, wherein The control unit further includes: A first control unit connected to an output end of the first register and a control end of the first output unit, for controlling the first output unit to output the pulse signal of the current stage according to the first control signal; A second control unit connected to an output end of the second register and a control end of the second output unit, for controlling the second output unit to output the pulse signal of the next stage according to the second control signal; The control end of the first output unit is further connected to the second control unit, for controlling the first output unit to output the pulse signal of the current stage according to the control signals output by the first control unit and the second control unit.

5. The gate driving circuit according to claim 4, wherein the first control unit includes: a first sub-control unit, connected to the first register, a high-potential signal line, and the first output unit, for controlling the output of the first output unit according to a first control signal output by the first register; a second sub-control unit, connected to the first register, a low-potential signal line, and the first output unit, for controlling the output of the first output unit according to a first control signal output by the first register; the second control unit includes: a third sub-control unit, connected to the second register, the high-potential signal line, and the second output unit, for controlling the output of the second output unit according to a second control signal output by the second register; a fourth sub-control unit, connected to the second register, the low-potential signal line, and the second output unit, for controlling the output of the second output unit according to a second control signal output by the second register; wherein, the first sub-control unit and the second sub-control unit include a group of transistors with opposite driving characteristics; the third sub-control unit and the fourth sub-control unit include a group of transistors with opposite driving characteristics.

6. The gate driving circuit according to claim 5, characterized in that, The control terminal of the second output unit is connected to the second register, and the input terminal is connected to the first output unit, for controlling the output of the next-stage pulse signal according to the cascade signal transmitted by the second register, thereby realizing the switching between the first driving mode and the second driving mode.

7. The gate driving circuit according to claim 3, wherein Each of the gate driving units further includes: a second cascade control unit, with an input terminal connected to the first output unit and an output terminal connected to the input terminal of the next-stage gate driving unit, for driving the next-stage gate driving unit to work according to the pulse signal; a third cascade control unit, with an input terminal connected to the first output unit and an output terminal connected to the input terminals of the next two-stage gate driving units, for driving the next two-stage gate driving units to work according to the pulse signal; the control terminal of the second cascade control unit is connected to the output terminal of the first register; the control terminal of the third cascade control unit is connected to the output terminal of the second register.

8. The gate driving circuit according to claim 3, wherein The first register includes: a first cascade unit, with an input terminal connected to the first signal line or the output terminal of the previous-stage gate driving unit, and a control terminal connected to the first control signal line, for receiving the cascade signal transmitted by the previous-stage gate driving unit; a first storage unit, connected to the output terminal of the first cascade unit, for storing the cascade signal transmitted by the previous-stage gate driving unit; The second register includes: a second cascade unit, with an input terminal connected to the second signal line or the output terminals of the previous two-stage gate driving units, and a control terminal connected to the first control signal line, for receiving the cascade signals transmitted by the previous two-stage gate driving units; a second storage unit, connected to the output terminal of the second cascade unit, for storing the cascade signals transmitted by the previous two-stage gate driving units.

9. The gate driving circuit according to claim 8, wherein The first register further includes: The first delay control unit, with its input end connected to the output end of the first cascading unit and the first storage unit, and its control end connected to the second control signal line, is configured to delay the control effect of the cascading signal transmitted by the previous-stage gate driving unit on the first output unit; The third storage unit, connected to the output end of the first delay control unit, is configured to store the cascading signal transmitted by the previous-stage gate driving unit; The second register further includes: The second delay control unit, with its input end connected to the output end of the second cascading unit and the second storage unit, and its control end connected to the second control signal line, is configured to delay the control effect of the cascading signal transmitted by the two previous-stage gate driving units on the second output unit and / or the first output unit; The fourth storage unit, connected to the output end of the second delay control unit, is configured to store the cascading signal transmitted by the two previous-stage gate driving units.

10. A display panel, characterized in that, The display panel includes the gate driving circuit according to any one of claims 1 to 9.

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