Pixel circuit and display device including same

Abstract

The present disclosure relates to a pixel circuit and a display device including the same. The pixel circuit includes a compensation circuit connected to a data line, a first gate line, and a second gate line, the compensation circuit configured to alternately receive a first voltage and a second voltage through the data line, receive a first gate signal through the first gate line, and receive a second gate signal through the second gate line; a light-emitting element; a driving element including a gate electrode configured to receive the second voltage via the compensation circuit, the driving element configured to generate a current driving the light emitting element based on the second voltage; and a switching element including a gate electrode configured to receive the second gate signal via the compensation circuit, and configured to switch a path of a current between the driving element and the light emitting element based on the second gate signal. The light emitting element, the driving element, and the switching element may be connected in series between the first power supply line and the second power supply line.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0192176, filed on December 27, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a pixel circuit and a display device including the pixel circuit. Background art

[0004] Based on the materials of the light - emitting layer, electroluminescent display devices are roughly divided into inorganic light - emitting display devices and organic light - emitting display devices. An active - matrix organic light - emitting display device includes an organic light - emitting diode (hereinafter referred to as "OLED"), which emits light by itself, and has advantages such as a fast response speed, high luminous efficiency, high brightness, and a large viewing angle. In an organic light - emitting display device, an OLED is formed on each pixel. The organic light - emitting display device has a fast response speed, excellent luminous efficiency, brightness, and viewing angle, and has excellent contrast and color reproducibility because it can represent black grayscale with pure black.

[0005] In recent years, due to the progress of technologies enabling flexible bending or folding with the use of flexible displays, display devices are approaching the realization of next - generation displays, such as rollable displays, foldable displays, bendable displays, slidable displays, and stretchable displays. Such flexible display devices can be applied not only to mobile devices such as smart phones and tablet PCs, but also to televisions (TVs), vehicles, wearable devices, etc., and their application fields are expanding.

[0006] The screen size of a stretchable display device can be increased or decreased, and can be freely modified into various shapes. To improve the performance of a stretchable display, a pixel circuit that can operate stably even when the display panel is deformed, and a display panel with a high elongation rate are required. Summary of the invention

[0007] Accordingly, the present disclosure relates to a pixel circuit and a display device including the pixel circuit that eliminate one or more problems caused by the limitations and disadvantages of the related art.

[0008] The present disclosure provides a highly reliable pixel circuit applicable to a stretchable display device and a display device including the pixel circuit.

[0009] The object of the present disclosure is not limited to the above - mentioned object, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

[0010] To achieve these objects and other advantages of the present disclosure, as specifically implemented and broadly described herein, a pixel circuit may include: a compensation circuit connected to a data line, a first gate line, and a second gate line, the compensation circuit configured to alternately receive a first voltage and a second voltage through the data line, receive a first gate signal through the first gate line, and receive a second gate signal through the second gate line; a light-emitting element; a driving element including a gate electrode configured to receive the second voltage via the compensation circuit, the driving element configured to generate a current for driving the light-emitting element based on the second voltage; and a switching element including a gate electrode configured to receive the second gate signal via the compensation circuit, the switching element configured to switch a path of a current between the driving element and the light-emitting element based on the second gate signal. The light-emitting element, the driving element, and the switching element may be connected in series between a first power supply line and a second power supply line.

[0011] In some example embodiments, the compensation circuit may include: a capacitor coupled between a first node and a second node; a first switching element connected between the data line and the first node and configured to conduct in response to a gate conduction voltage of the first gate signal to electrically connect the data line to the first node; a second switching element connected between the second node and a third node and configured to conduct in response to the gate conduction voltage of the first gate signal to electrically connect the second node to the third node; a third switching element connected to the first node and configured to conduct in response to a gate conduction voltage of the second gate signal to apply the first voltage to the first node; and a fifth switching element connected to a fourth node and configured to conduct in response to the gate conduction voltage of the first gate signal to apply the first voltage to the fourth node. The switching element may include a fourth switching element connected between the third node and the fourth node and configured to conduct in response to the gate conduction voltage of the second gate signal to electrically connect the third node to the fourth node. The driving element may include a gate electrode connected to the second node, a first electrode connected to the first power supply line configured to receive a pixel driving voltage, and a second electrode connected to the third node. The light-emitting element may include an anode electrode connected to the fourth node and a cathode electrode connected to the second power supply line configured to receive a cathode voltage. The first voltage may be a reference voltage or the cathode voltage, and the second voltage is a data voltage of pixel data. The data line may be configured to receive the data voltage of the pixel data after receiving the reference voltage or the cathode voltage.

[0012] In some example embodiments, during a horizontal period, the first node may be configured to receive the reference voltage via the data line and the first switching element and via the third switching element simultaneously.

[0013] In some example embodiments, the second node, the third node, and the fourth node may be configured to receive the reference voltage when the reference voltage is applied to the first node.

[0014] In some example embodiments, a driving period of the pixel circuit may include a first stage in which the pixel circuit is configured to be initialized, a second stage in which the capacitor is configured to receive a threshold voltage of the driving element and the data voltage, and a third stage in which the light-emitting element is configured to emit light. The first gate signal may be configured to be at a gate-on voltage in the first stage and the second stage, and at a gate-off voltage in the third stage. The second gate signal may be configured to be at a gate-off voltage in the second stage, and at a gate-on voltage in the first stage and the third stage. The first switching element, the second switching element, and the fifth switching element may be configured to conduct in response to the gate-on voltage of the first gate signal and to cut off in response to the gate-off voltage of the first gate signal. The third switching element and the fourth switching element may be configured to conduct in response to the gate-on voltage of the second gate signal and to cut off in response to the gate-off voltage of the second gate signal. The horizontal period may include the periods of the first stage and the second stage. The data line may be configured to be at the reference voltage in the first stage and at the data voltage in the second stage.

[0015] In some example embodiments, the first switching element may include a gate electrode configured to receive the first gate signal, a first electrode connected to the data line, and a second electrode connected to the first node. The second switching element may include a gate electrode configured to receive the first gate signal, a first electrode connected to the second node, and a second electrode connected to the third node. The third switching element may include a gate electrode configured to receive the second gate signal, a first electrode connected to the first node, and a second electrode configured to receive the reference voltage. The fourth switching element includes a gate electrode configured to receive the second gate signal, a first electrode connected to the third node, and a second electrode connected to the fourth node. The fifth switching element may include a gate electrode configured to receive the first gate signal, a first electrode configured to receive the reference voltage, and a second electrode connected to the fourth node.

[0016] In some example embodiments, during a horizontal period, the first node may be configured to receive the cathode voltage via the data line and the first switching element and via the third switching element simultaneously.

[0017] In some example embodiments, the second node, the third node, and the fourth node may be configured to receive the cathode voltage when the cathode voltage is applied to the first node.

[0018] In some example embodiments, the driving period of the pixel circuit may include a first stage in which the pixel circuit is configured to be initialized, a second stage in which the capacitor is configured to receive the threshold voltage of the driving element and the data voltage, and a third stage in which the light-emitting element is configured to emit light. The first gate signal may be configured to be at a gate-on voltage in the first stage and the second stage, and at a gate-off voltage in the third stage. The second gate signal may be configured to be at a gate-off voltage in the second stage, and at a gate-on voltage in the first stage and the third stage. The first switching element, the second switching element, and the fifth switching element may be configured to conduct in response to the gate-on voltage of the first gate signal and to cut off in response to the gate-off voltage of the first gate signal. The third switching element and the fourth switching element may be configured to conduct in response to the gate-on voltage of the second gate signal and to cut off in response to the gate-off voltage of the second gate signal. The horizontal period may include the periods of the first stage and the second stage. The data line may be configured to be at the cathode voltage in the first stage and at the data voltage in the second stage.

[0019] In some example embodiments, the first switching element may include a gate electrode configured to receive the first gate signal, a first electrode connected to the data line, and a second electrode connected to the first node. The second switching element may include a gate electrode configured to receive the first gate signal, a first electrode connected to the second node, and a second electrode connected to the third node. The third switching element may include a gate electrode configured to receive the second gate signal, a first electrode connected to the first node, and a second electrode configured to receive the cathode voltage. The fourth switching element includes a gate electrode configured to receive the second gate signal, a first electrode connected to the third node, and a second electrode connected to the fourth node. The fifth switching element may include a gate electrode configured to receive the first gate signal, a first electrode configured to receive the cathode voltage, and a second electrode connected to the fourth node.

[0020] In some example embodiments, the first voltage may be a constant voltage, and the first voltage is a reference voltage or a cathode voltage. The second voltage may be a data voltage corresponding to pixel data. During one horizontal period, the compensation circuit may be further configured to receive the first voltage through the data line and then receive the second voltage through the data line.

[0021] In some example embodiments, the one horizontal period may include a horizontal blanking period and a horizontal active period. During the horizontal blanking period, the compensation circuit may be further configured to receive the first voltage rather than the second voltage through the data line to initialize the pixel circuit. During the horizontal active period, the compensation circuit may be further configured to receive the second voltage through the data line to write the pixel data into the pixel circuit.

[0022] In some example embodiments, the one horizontal period may include a horizontal blanking period and a horizontal active period. During the horizontal blanking period, the first gate signal and the second gate signal may be at a gate-on voltage. During the horizontal active period, the first gate signal may be at the gate-on voltage, and the second gate signal may be at a gate-off voltage.

[0023] In another aspect of the present disclosure, a display device may include: a display panel including a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of pixel circuits, at least one of the pixel circuits being the pixel circuit described above; a data driver configured to output the first voltage and the second voltage; a gate driver configured to provide at least one gate signal to the gate lines; and a control circuit configured to control the data driver and the gate driver. The plurality of data lines may include the data lines described above, the plurality of gate lines may include the first gate line and the second gate line described above, the at least one gate signal may include the first gate signal and the second gate signal described above, and the plurality of power lines may include the first power line and the second power line described above.

[0024] In some example embodiments, the control circuit may be configured to transmit initialization data as a digital signal to the data driver. The data driver may be configured to output the first voltage in response to the initialization data.

[0025] In some example embodiments, the control circuit may be configured to update the initialization data in each horizontal period. The first voltage may have a voltage level corresponding to the initialization data.

[0026] In some example embodiments, the display panel may include: a plurality of circuit portions provided with the pixel circuits; and a plurality of stretchable wirings electrically connecting the plurality of circuit portions. The stretchable wirings may include the data lines, the gate lines, and the power lines.

[0027] In some example embodiments, the display device may further include: a switching circuit configured to alternately select one of the first voltage and the second voltage and provide the selected one of the first voltage and the second voltage to the data line.

[0028] In some example embodiments, the switching circuit may be further configured to, within one horizontal period, select the first voltage and provide it to the data line, and then select the second voltage and provide it to the data line.

[0029] The pixel circuit according to an example embodiment of the present disclosure can stably drive a light-emitting element without being affected by the deviation of the threshold voltage of a driving element and the voltage drop of a power supply when being initialized, and without short-circuiting a data voltage and an initialization voltage. In addition, the pixel circuit according to an example embodiment of the present disclosure can perform initialization, threshold voltage sampling, and light emission with a relatively small number of gate signals, thereby reducing the number of wirings in a display panel.

[0030] Therefore, the example embodiments of the present disclosure can implement a highly reliable pixel circuit. The elongation rate of a stretchable display device can be improved by reducing the number of wirings that adversely affect the elongation rate in the stretchable display device.

[0031] The advantages and effects according to the present disclosure are not limited to those described above, and additional advantages and effects are included in the present disclosure or can be obtained from the present disclosure.

[0032] Additional features and aspects of the present disclosure will be set forth in the following description, and in part will become apparent from the description, or can be learned by practice of the inventive concept provided herein. Other features and aspects of the inventive concept can be realized and obtained by structures specifically pointed out in the written description, its claims, and the drawings or can be derived therefrom.

[0033] It should be understood that both the foregoing general description and the following detailed description of the present disclosure are by way of example and are intended to provide further explanation of the present disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] By referring to the accompanying drawings and describing in detail the exemplary embodiments of the present disclosure, the above and other objects, features, and advantages of the present disclosure will become clearer to those of ordinary skill in the art, where:

[0035] Figure 1 is a circuit diagram schematically illustrating a pixel circuit according to an embodiment of the present disclosure;

[0036] Figure 2 is a circuit diagram illustrating a pixel circuit according to an embodiment of the present disclosure;

[0037] Figure 3A and Figure 3B is a diagram showing a method of driving a pixel circuit;

[0038] Figures 4A to 4D is a diagram illustrating a method of driving a pixel circuit in stages;

[0039] Figure 5 is a circuit diagram schematically illustrating a pixel circuit according to another embodiment of the present disclosure;

[0040] Figure 6A and Figure 6B is a waveform diagram illustrating a method of driving a pixel circuit;

[0041] Figure 7 is a waveform diagram illustrating an output voltage from a data driver according to an embodiment of the present disclosure;

[0042] Figure 8A and Figure 8B is a diagram illustrating a switch circuit connected to a data line;

[0043] Figure 9 is a block diagram schematically illustrating a display device according to an embodiment of the present disclosure;

[0044] Figure 10A and Figure 10B is a diagram illustrating another example of a display device;

[0045] Figure 11 is a diagram illustrating an example of a circuit portion and a stretchable wiring of a stretchable display device;

[0046] Figure 12 is a diagram illustrating one frame period and one horizontal period;

[0047] Figure 13 is a diagram illustrating a transmission line connection structure between a timing controller and a source driver IC on an EPI interface;

[0048] Figure 14 is a waveform diagram illustrating an example of a multi-phase internal clock generated by a source driver IC;

[0049] Figure 15 is a waveform diagram illustrating a signal transmission protocol of an EPI interface;

[0050] Figure 16 is a diagram illustrating an example of a (1) data packet in the EPI interface; and

[0051] Figure 17 is a diagram illustrating an example of a signal transmitted during a horizontal blanking period. DETAILED DESCRIPTION

[0052] Advantages and features of the present disclosure and methods for achieving these advantages and features will be more clearly understood from the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in various different forms. On the contrary, these embodiments will make the disclosure of the present disclosure complete and enable those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is only limited within the scope of the appended claims.

[0053] The shapes, sizes, proportions, angles, quantities, etc. illustrated in the drawings for describing the embodiments of the present disclosure are only examples, and the present disclosure is not limited thereto. Throughout the present application, the same reference numerals generally denote the same elements. In addition, when describing the present disclosure, detailed descriptions of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0054] Terms such as "comprising", "including", "having", and "constituting" used herein generally intend to allow the addition of other components, unless these terms are used together with the term "only".

[0055] Even if not explicitly stated, components are interpreted as including a normal error range.

[0056] When describing the positional or interconnection relationship between two components, such as "on top", "above", "below", "next to", "connected or coupled", "crossed", "intersected", etc., one or more other components may be interposed between them, unless the terms "immediately" or "directly" are used.

[0057] When describing the relationship before and after in time, such as "after", "behind", "next", "before", etc., it may not be continuous on a time basis, unless the terms "immediately" or "directly" are used.

[0058] The terms "first", "second", etc. may be used to distinguish components from each other, but the functions or structures of the components are not limited by the serial numbers or component names in front of the components.

[0059] The following embodiments may be combined or combined with each other partially or wholly, and may be linked and operated in various technical manners. These embodiments may be implemented independently or in association with each other.

[0060] The pixel circuit and the gate driving circuit of the display device may include a plurality of transistors. The transistors may be implemented as thin film transistors (TFTs). The transistors may be implemented as oxide thin film transistors (TFTs) including oxide semiconductors, low temperature polysilicon TFTs (LTPS TFTs) including low temperature polysilicon, etc.

[0061] A transistor is a three - electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In a transistor, carriers start to flow from the source. The drain is an electrode from which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n - channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage so that electrons can flow from the source to the drain. The n - channel transistor has a direction of current flowing from the drain to the source. In the case of a P - channel transistor (P - channel metal - oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p - channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change according to the applied voltage. Therefore, the present disclosure is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0062] The gate signal swings between a gate - on voltage and a gate - off voltage. The transistor conducts in response to the gate - on voltage and cuts off in response to the gate - off voltage. In the case of an n - channel transistor, the gate - on voltage may be a gate high voltage VGH, and the gate - off voltage may be a gate low voltage VGL. In the case of a p - channel transistor, the gate - on voltage may be a gate low voltage VGL, and the gate - off voltage may be a gate high voltage VGH.

[0063] The pixel circuit according to an embodiment of the present disclosure may be initialized to an initialization voltage. The initialization voltage may be a reference voltage or a cathode voltage.

[0064] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0065] Figure 1 is a circuit diagram schematically illustrating a pixel circuit according to an embodiment of the present disclosure.

[0066] Referring to Figure 1 , the pixel circuit includes a light - emitting element EL, a driving element DT, a switching element ST, and a compensation circuit 10. The switching element ST and the driving element DT may be implemented as p - channel transistors, but are not limited thereto.

[0067] The light-emitting element EL can be, but is not limited to, a light-emitting element such as an OLED or a micro LED. The light-emitting element EL may include an anode electrode, a light-emitting layer, and a cathode electrode. The light-emitting element EL, the driving element DT, and the switching element ST may be connected in series between the VDD node P1 to which the pixel driving voltage VDD is applied and the VSS node P2 to which the cathode voltage VSS is applied. The VDD node P1 may be connected to a first power supply line commonly connected to all pixels on the display panel. The VSS node P2 may be connected to a second power supply line commonly connected to all pixels on the display panel.

[0068] The driving element DT drives the light-emitting element EL by generating a current required to drive the light-emitting element EL according to the gate-source voltage.

[0069] The switching element ST switches the current path between the pixel driving voltage VDD and the cathode voltage VSS in response to the second gate signal EM to adjust the light-emitting time of the light-emitting element EL. In Figure 2 FIG. 8, the switching element ST may be a fourth switching element T4.

[0070] The compensation circuit 10 may be connected to the data line DL to which the first voltage V1 and the second voltage V2 are alternately applied, the first gate line GL1 to which the first gate signal SCAN is applied, and the second gate line GL2 to which the second gate signal EM is applied. The first voltage V1 may be a reference voltage Vref, for example, a constant voltage, as Figures 2 to 8A shown. The reference voltage Vref may be interpreted as an initialization voltage. The second voltage V2 may be a data voltage Vdata of the pixel data, as Figures 2 to 8B shown. The compensation circuit 10 may be connected to a constant voltage node P3 to which a third voltage V3 is applied. The constant voltage node P3 may be connected to a third power supply line commonly connected to all pixels on the display panel. The third voltage V3 may be a constant voltage, for example, the reference voltage Vref or the cathode voltage VSS, as Figures 2 to 8B shown.

[0071] The compensation circuit 10 may include a plurality of switching elements and capacitors. The compensation circuit 10 receives the data voltage Vdata of the pixel data, the first gate signal SCAN, and the second gate signal EM, and applies the data voltage Vdata to the gate electrode of the driving element DT. In addition, the compensation circuit 10 may control the switching element ST by applying the second gate signal EM to the gate electrode of the switching element ST.

[0072] Figure 2 is a circuit diagram illustrating a pixel circuit according to an embodiment of the present disclosure.

[0073] Referring to Figure 2, a pixel circuit according to an embodiment of the present disclosure includes a light-emitting element EL, a compensation circuit 10, a fourth switching element T4, a driving element DT, and a capacitor Cst. The compensation circuit may include a plurality of switching elements T1, T2, T3, T5, and a capacitor Cst. The switching elements T1 to T5 and the driving element DT may be implemented as, but not limited to, p-channel transistors.

[0074] A data voltage Vdata, as well as gate signals SCAN and EM, are provided to the pixel circuit. The gate signals SCAN and EM include pulses that swing between a gate-on voltage VGL and a gate-off voltage VGH. The first switching element T1, the second switching element T2, and the fifth switching element T5 conduct / cut off in response to the voltage of the first gate signal SCAN. The third switching element T3 and the fourth switching element T4 conduct / cut off in response to the voltage of the second gate signal EM.

[0075] Constant voltages (or direct current (DC) voltages) such as a pixel driving voltage VDD, a cathode voltage VSS, a reference voltage Vref, etc. are applied to the pixel circuit. The reference voltage Vref may be interpreted as an initialization voltage. The constant voltages applied to the pixel circuit may be set as VDD > Vref > VSS, but are not limited thereto. The gate-off voltage VGH may be set as a voltage lower than the pixel driving voltage VDD and lower than the maximum voltage of the data voltage Vdata, but is not limited thereto. The gate-on voltage VGL may be set as a voltage lower than the cathode voltage VSS and the minimum voltage of the data voltage Vdata, but is not limited thereto. The data voltage Vdata has a dynamic range (DR) between a voltage equal to or higher than the cathode voltage VSS and a voltage lower than the pixel driving voltage VDD. The reference voltage Vref may be set as a specific voltage within the range of the data voltage. For example, the voltages applied to the pixel circuit may be set as, but not limited to, VDD = 12V, VSS = 0V, Vref = 2V, VGH = 10V, VGL = -10V, Vdata = 0V to 9V, etc.

[0076] The light-emitting element EL may be implemented as a light-emitting element such as an OLED, an inorganic LED such as a micro LED, etc. The OLED includes an organic compound layer formed between an anode electrode and a cathode electrode. The organic compound layer may include, but not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode electrode of the light-emitting element EL is connected to the fourth node D. The cathode electrode of the OLED is connected to the VSS node (or the second power supply node) P2 to which the cathode voltage VSS is applied. For a micro LED, it may have, but not limited to, a vertical structure with electrodes arranged above and below a semiconductor chip integrated with the light-emitting element EL. The semiconductor chip integrated with the light-emitting element EL may be implemented as a lateral structure or a flip-chip structure.

[0077] The driving element DT drives the light-emitting element EL by supplying a current generated based on the gate-source voltage Vgs to the light-emitting element EL. The driving element DT includes: a gate electrode connected to the second node B, a first electrode connected to the VDD node P1 to which the pixel driving voltage VDD is applied, and a second electrode connected to the third node C.

[0078] The capacitor Cst is connected between the first node A and the second node B. The first node A is connected to the second electrode of the first switching element T1, the first electrode of the third switching element T3, and the first electrode of the capacitor Cst. The second node B is connected to the second electrode of the capacitor Cst, the gate electrode of the driving element DT, and the first electrode of the second switching element T2. The capacitor Cst is charged with the data voltage Vdata compensated by an amount equal to the threshold voltage Vth of the driving element DT. Since the data voltage Vdata at each sub-pixel is compensated by the threshold voltage Vth of the driving element DT, the characteristic deviation of the driving element in each sub-pixel can be compensated, and thus driving can be performed with uniform driving characteristics.

[0079] The switching elements T1 to T5 are turned on in response to the gate conduction voltage VGL applied to their gate electrodes and turned off in response to the gate cut-off voltage VGH.

[0080] The first switching element T1 is turned on in response to the gate conduction voltage VGL of the first gate signal SCAN. When the first switching element T1 is turned on, the data voltage Vdata is applied to the first node A. The first switching element T1 includes: a gate electrode connected to the first gate line GL1 to which the first gate signal SCAN is applied, a first electrode connected to the data line DL, and a second electrode connected to the first node A. The first gate signal SCAN can be generated as a pulse of the gate conduction voltage VGL. The pulse width of the first gate signal SCAN can be set to approximately one horizontal period (1H).

[0081] The second switching element T2 is turned on in response to the gate conduction voltage VGL of the first gate signal SCAN. When the second switching element T2 is turned on, the second node B and the third node C are connected, such that the driving element DT is driven as a diode. The second switching element T2 includes: a gate electrode connected to the first gate line GL1, a first electrode connected to the second node B, and a second electrode connected to the third node C.

[0082] The third switching element T3 is turned on in response to the gate conduction voltage VGL of the second gate signal EM. When the third switching element T3 is turned on, the reference voltage Vref is applied to the first node A. The third switching element T3 includes: a gate electrode connected to the second gate line GL2 to which the second gate signal EM is applied, a first electrode connected to the first node A, and a second electrode connected to the Vref node P3.

[0083] The fourth switching element T4 is turned on in response to the gate conduction voltage VGL of the second gate signal EM. When the fourth switching element T4 is turned on, the third node C and the fourth node D are connected. The fourth switching element T4 includes: a gate electrode connected to the second gate line GL2, a first electrode connected to the third node C, and a second electrode connected to the fourth node D.

[0084] The fifth switching element T5 is turned on in response to the gate conduction voltage VGL of the first gate signal SCAN. When the fifth switching element T5 is turned on, the reference voltage Vref is supplied to the fourth node D. The fifth switching element T5 includes: a gate electrode connected to the first gate line GL1, a first electrode connected to the Vref node P3, and a second electrode connected to the fourth node D.

[0085] Figure 2 The driving period of the pixel circuit shown in can be divided into a first stage (or initialization stage, INI) in which the pixel circuit is initialized, a second stage (or sampling stage, SAM) in which pixel data is written into the pixel circuit and the threshold voltage Vth of the driving element DT is sampled, and a third stage (or light emitting stage, EMI) in which the light emitting element EL is driven, as Figure 3A and Figure 3B shown. One (1) horizontal period (1H) can be divided into a first stage INI1 / INI2 and a second stage SAM. The durations of the first stage INI1 / INI2 and the second stage SAM can be appropriately selected based on the results of the reliability experiment of the pixel circuit. For example, but not limited to as Figure 3A shown, the first stage INI1 and the second stage SAM can each be set to 1 / 2 of the horizontal duration, or as Figure 3B shown, the second stage SAM can be set to a longer duration than the first stage INI2. A hold stage HOLD can be provided between the second stage SAM and the third stage EMI, but the hold stage can be omitted.

[0086] As Figure 3A and Figure 3BAs shown, the voltage of the first gate signal SCAN is the gate-on voltage VGL in the first phases INI1 / INI2 and the second phase SAM, and is the gate-off voltage VGH in the third phase EMI. The voltage of the second gate signal EM is the gate-off voltage VGH in the second phase SAM, and is the gate-on voltage VGL in the first phases INI1 / INI2 and the third phase EMI. During the hold phase HOLD, the voltages of the first gate signal SCAN and the second gate signal EM are the gate-off voltage VGH.

[0087] The voltage on the data line DL is the reference voltage Vref in the first phase INI1 / INI2 of one horizontal period (1H), and is the data voltage Vdata in the second phase SAM. By repeating the first phase INI1 / INI2 and the second phase SAM in each horizontal period, the data voltage Vdata corresponding to the pixel data value can be provided to the pixel circuits in each pixel row.

[0088] Figure 4A is a circuit diagram illustrating the current flow in the pixel circuit and the voltages of the main nodes in the first phase INI1 / INI2.

[0089] Referring to Figure 3A 、 Figure 3B and Figure 4A , in the first phase INI1 / INI2, the voltages of the first gate signal SCAN and the second gate signal EM are the gate-on voltage VGL. Therefore, in the first phase INI1 / INI2, the second switching element T2 to the fifth switching element T5 and the driving element DT are turned on, thereby initializing the first node A to the fourth node D and the capacitor Cst.

[0090] In the first phase INI1 / INI2, the reference voltage Vref is applied to the data line DL. In the first phase INI1 / INI2, the voltages of the first node to the fourth node A, B, C, D are the reference voltage Vref. In this case, the data line DL and the Vref node P3 are short-circuited, and the capacitor Cst is initialized to 0V because the voltages of the first node A and the second node B are equal to the reference voltage Vref.

[0091] Because the voltage difference between the reference voltage Vref and the cathode voltage VSS in the first phase INI1 / INI2 is lower than the threshold voltage of the light-emitting element EL, the light-emitting element EL is in the off state in the first phase INI1 / INI2.

[0092] In addition, when the data voltage Vdata of the pixel data is applied to the data line DL in the first stage INI1 / INI2, the data voltage Vdata and the reference voltage Vref may be short-circuited at the first node A, so that the capacitor Cst may be initialized unstably. In the present disclosure, in the first stage INI1 / INI2, the reference voltage Vref may be applied to the data line DL such that the reference voltage Vref is applied to the capacitor Cst, so that the voltage of the capacitor Cst in all pixels is initialized to 0V identically.

[0093] Figure 4B is a circuit diagram illustrating the current flow in the pixel circuit and the voltages of the main nodes in the second stage SAM.

[0094] Referring to Figure 3A 、 Figure 3B and Figure 4B , in the second stage SAM, the threshold voltage Vth of the driving element DT and the data voltage Vdata of the pixel data are applied to the capacitor Cst. In the second stage SAM, the pixel data is written into the pixel circuit, the threshold voltage Vth of the driving element DT is sampled, and the data voltage Vdata compensated by the threshold voltage Vth is stored in the capacitor Cst.

[0095] In the second stage SAM, the data voltage Vdata of the pixel data is applied to the data line DL, and the voltage of the first gate signal SCAN is the gate-on voltage VGL. In this case, the voltage of the second gate signal EM is the gate-off voltage VGH. Therefore, in the second stage SAM, the first switching element T1, the second switching element T2, and the fifth switching element T5 are turned on, and the third switching element T3 and the fourth switching element T4 are turned off.

[0096] At the end of the second stage SAM, the voltage of the first node A is the data voltage Vdata of the pixel data, and the voltage of the third node B is the voltage of VDD - Vth. Here, "Vth" is the threshold voltage of the driving element DT. In the second stage SAM, the voltage of the third node C is VDD.

[0097] A hold stage HOLD may be provided between the second stage SAM and the third stage EMI. During the hold stage HOLD, the voltages of the gate signals SCAN and EM are the gate-off voltage VGH. In this case, since the first switching element T1 to the fifth switching element T5 are in the off state, the first node A, the second node B, and the fourth node D are floating, thus holding the previous voltages.

[0098] Figure 4D is a circuit diagram illustrating the current flow in the pixel circuit and the voltages of the main nodes in the third stage EMI.

[0099] Referring to Figure 3A , Figure 3B and Figure 4D , in the third-stage EMI, the voltage of the first gate signal SCAN is the gate cut-off voltage VGH, and the voltage of the second gate signal EM is the gate conduction voltage VGL. Therefore, in the third-stage EMI, the first switching element T1, the second switching element T2, and the fifth switching element T5 are turned off, and the third switching element T3 and the fourth switching element T4 are turned on.

[0100] In the third-stage EMI, the reference voltage Vref is applied to the first node A, so the data voltage Vdata is transferred to the second node B by capacitor coupling. In this case, the voltage of the first node A is the voltage of (Vref - Vth), and the voltage of the second node B is the voltage of VDD - Vth + (Vref - Vdata). In the third-stage EMI, the light-emitting element EL can emit light in response to the current from the driving element DT. In the third-stage EMI, the current (I) flowing through the light-emitting element EL is expressed as I = k(VDD - (VDD - Vth + (Vref - Vdata)) - Vth) 2 = k(Vdata - Vref) 2 . Where k is a constant value. Therefore, in the third-stage EMI, the light-emitting element EL can emit light with a brightness corresponding to the luminance value (or gray-scale value) of the pixel data, without being affected by the deviation of the threshold voltage Vth of the driving element DT and the deviations of the constant voltages VDD, VSS, and Vref.

[0101] Figure 5 is a circuit diagram illustrating a pixel circuit according to another embodiment of the present disclosure. In Figure 5 , components substantially the same as those in Figure 2 are given the same reference numerals, and their detailed descriptions will be omitted. The signals shown in Figure 6A and Figure 6B are applied to the pixel circuit shown in Figure 5 .

[0102] Referring to Figure 5 , Figure 6A and Figure 6B , the third to fifth switching elements T3, T4, and T5 use the cathode voltage VSS to initialize the main nodes A, B, C, and D and the capacitor Cst. Therefore, Figure 5 the pixel circuit shown in Figure 2 does not require the power supply line connected to the Vref node P3 shown in

[0103] In the first stage INI1 / INI2 and the third stage EMI, the third switching element T3 and the fourth switching element T4 are turned on in response to the gate conduction voltage VGL of the second gate signal EM. In the second stage SAM and the holding period HOLD, the third switching element T3 is turned off in response to the gate cut-off voltage VGL of the second gate signal EM. The third switching element T3 includes: a gate electrode connected to the second gate line GL2 to which the second gate signal EM is applied, a first electrode connected to the first node A, and a second electrode connected to the VSS node P2. The fourth switching element T4 includes: a gate electrode connected to the second gate line GL2, a first electrode connected to the third node C, and a second electrode connected to the fourth node D.

[0104] In the first stage INI1 / INI2 and the second stage SAM, the fifth switching element T5 is turned on in response to the gate conduction voltage VGL of the first gate signal SCAN. In the holding stage HOLD and the third stage EMI, the fifth switching element T5 is turned off in response to the gate cut-off voltage VGH of the first gate signal SCAN. The fifth switching element T5 includes: a gate electrode connected to the first gate line GL1 to which the first gate signal SCAN is applied, a first electrode connected to the VSS node P2, and a second electrode connected to the fourth node D.

[0105] In the first stage INI1 / INI2, the voltages of the first gate signal SCAN and the second gate signal EM are the gate conduction voltage VGL. Therefore, in the first stage INI1 / INI2, the second switching element T2 to the fifth switching element T5 and the driving element DT are turned on, so that the main nodes A to D and the capacitor Cst are initialized.

[0106] In Figure 5 the first stage INI1 / INI2 of the pixel circuit shown, the cathode voltage VSS is applied to the data line DL. In the first stage INI1 / INI2, the voltages of the first node to the fourth nodes A, B, C, D are initialized to the cathode voltage VSS.

[0107] Since the voltage difference between the reference voltage Vref and the cathode voltage VSS in the first stage INI1 / INI2 is lower than the threshold voltage of the light-emitting element EL, the light-emitting element EL is in the off state in the first stage INI1 / INI2. In Figure 5 the first stage INI1 / INI2 of the pixel circuit shown, the cathode voltage VSS is applied to the data line DL, so the cathode voltage VSS is applied to the capacitor Cst.

[0108] As can be seen from the above embodiments, in the first stage INI1 / INI2 of initializing the pixel circuit provided according to the embodiments of the present disclosure, the reference voltage Vref is applied to the first node A through the data line DL and the first switching element T1 and at the same time the reference voltage Vref is applied to the first node A through the third switching element T3, or the cathode voltage VSS is applied to the first node A through the data line DL and the first switching element T1 and at the same time the cathode voltage VSS is applied to the first node A through the third switching element T3. Therefore, when the pixel circuit is initialized, the same initialization voltage Vref / VSS is applied to the first node A via two paths.

[0109] As Figure 6A and Figure 6B shown in, the voltage of the first gate signal SCAN is the gate-on voltage VGL in the first stage INI1 / INI2 and the second stage SAM, and is the gate-off voltage VGH in the third stage EMI. The voltage of the second gate signal EM is the gate-off voltage VGH in the second stage SAM, and is the gate-on voltage VGL in the first stage INI1 / INI2 and the third stage EMI. During the hold stage HOLD, the voltages of the first gate signal SCAN and the second gate signal EM are the gate-off voltage VGH.

[0110] The voltage on the data line DL is the cathode voltage VSS in the first stage INI1 / INI2 of one horizontal period (1H), and is the data voltage Vdata in the second stage SAM. By repeating the first stage INI1 / INI2 and the second stage SAM in each horizontal period, the data voltage Vdata corresponding to the pixel data value can be provided to the pixel circuits in each pixel row.

[0111] Figure 7 is a waveform diagram illustrating the output voltage from the data driver according to an embodiment of the present disclosure.

[0112] Referring to Figure 7 , the data driver provides the initialization voltage Vref / VSS of the pixel circuit to the data line DL in each horizontal period, and then provides the data voltage Vdata to the data line.

[0113] The data driver can output an initialization voltage Vref / VSS and a data voltage Vdata to a data line DL synchronously with a timing signal (e.g., a source output enable signal SOE) having a cycle with one horizontal period. The data driver can output the initialization voltage Vref / VSS in response to a logic high voltage (H) of the source output enable signal SOE, and output the data voltage Vdata in response to a logic low voltage (L) of the source output enable signal SOE. The timing signal having a cycle with one horizontal period is not limited to the source output enable signal SOE.

[0114] Figure 8A and Figure 8B is a diagram showing a switching circuit connected to a data line.

[0115] Referring to Figure 8A and Figure 8B , the switching circuit SW can be connected to the data line DL. The switching circuit SW outputs the initialization voltage Vref / VSS and then outputs the data voltage Vdata. The initialization voltage Vref / VSS applied to the data line DL via the switching circuit SW can be the same voltage as the reference voltage Vref (or the cathode voltage VSS) applied to the pixel circuit, or it can be set to a voltage appropriately adjusted in consideration of the characteristics of the display panel. The switching circuit SW can operate in cycles such as one horizontal period, 1 / 2 horizontal period, 1 / 3 horizontal period, and 1 / 4 horizontal period synchronously with a timing control signal generated in the timing controller or the data driver, but is not limited thereto.

[0116] The switching circuit SW can be provided at each data output channel of an integrated circuit (IC) in which a data driver is integrated. The switching circuit SW can be provided outside the data driver. For example, the switching circuit SW can be provided in a non-display area of the display panel. The switching circuit SW can alternately select the initialization voltage Vref / VSS and the data voltage Vdata to supply them to the data line DL. During one horizontal period, after applying the initialization voltage Vref / VSS to the data line DL through the switching circuit SW, the data voltage Vdata can be applied to the data line DL.

[0117] Figure 9 is a block diagram showing a display device according to an embodiment of the present disclosure. Figure 10A and Figure 10B are diagrams showing other examples of the display device.

[0118] Referring to Figures 9 to 10B , a display device according to an embodiment of the present disclosure includes: a display panel 100, a display panel driving circuit for writing pixel data to pixels 101 of the display panel 100, and a power supply 140 for generating power required to drive the pixels 101 and the display panel driving circuit.

[0119] The substrate of the display panel 100 may be, but is not limited to, a plastic substrate, a thin glass substrate, or a metal substrate. In a stretchable display device, the substrate of the display panel may be made of a stretchable insulating material, for example, a silicone rubber such as polydimethylsiloxane (PDMS), polyurethane (PU), or an elastomer such as polytetrafluoroethylene (PTFE).

[0120] The display panel 100 may be, but is not limited to, a rectangular panel having a length in the X-axis direction (or the first direction), a width in the Y-axis direction (or the second direction), and a thickness in the Z-axis direction (or the third direction). For example, at least a part of the display panel 100 may have a curved outer periphery.

[0121] The display area AA of the display panel 100 includes a pixel array for displaying an input image thereon. The pixel array includes: a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels 101 arranged in a matrix form. The display panel 100 may further include a power supply line commonly connected to the pixels 101. The power supply line is connected to the constant voltage nodes P1, P2, and P3 of the pixel circuit to supply the constant voltages VDD, VSS, and Vref required to drive the pixels 101 to the pixels 101. The power supply line may be implemented as a long strip wiring in the first direction or the second direction, or may be implemented as a mesh wiring in which the wiring in the first direction and the wiring in the second direction are electrically connected. The power supply line may further include a VGL line and a VGH line connected to the gate driver 120. The gate-on voltage VGL may be applied to the VGL line and the gate-off voltage VGH may be applied to the VGH line.

[0122] Each of the pixels 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for realizing colors. Each pixel may further include a white sub-pixel. Each sub-pixel includes a pixel circuit for driving a light-emitting element. Each pixel circuit is connected to a data line, a gate line, and a power supply line. Hereinafter, "pixel" may be understood to have the same meaning as "sub-pixel". The pixel circuit may be implemented as Figures 1 to 8B the pixel circuit shown in

[0123] The pixels may be arranged in the form of true-color pixels and pentile pixels. By driving two sub-pixels having different colors as one pixel 101 via using a preset pixel rendering algorithm, the pentile pixels can achieve a higher resolution than the true-color pixels. The pixel rendering algorithm may utilize the colors of the light emitted from its adjacent pixels to compensate for the insufficient color representation in each pixel.

[0124] The pixel array includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged in the row direction (X-axis direction) in the pixel array of the display panel 100. The pixels arranged in one pixel row share the gate line 103. The sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. A horizontal period is the time obtained by dividing one frame period by the total number of the pixel rows L1 to Ln.

[0125] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel can be applied to a transparent display device that displays an image on the screen and the actual object in the background is visible. The display panel 100 can be manufactured as a flexible display panel.

[0126] The power supply 140 generates a constant voltage (or direct current (DC) voltage) required to drive the pixel array and the display panel driving circuit of the display panel 100 by using a DC-DC converter. The DC-DC converter can include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 140 can output a constant voltage, such as a gamma reference voltage, a gate-on voltage VGL, a gate-off voltage VGH, a pixel driving voltage VDD, a cathode voltage VSS, a reference voltage Vref, etc., by adjusting the level of the DC input voltage applied from the host system 200. The gamma reference voltage is provided to the data driver 110. The dynamic range of the data voltage output from the data driver 110 is determined by the voltage range of the gamma reference voltage. The dynamic range of the data voltage is the voltage range between the highest gray-level voltage and the lowest gray-level voltage.

[0127] The gate-on voltage VGL and the gate-off voltage VGH are provided to the level converter 150 and the gate driver 120. Constant voltages such as the pixel driving voltage VDD, the cathode voltage VSS, and the reference voltage Vref are provided to the pixel 101 via the power supply lines commonly connected to the pixel 101.

[0128] The pixel driving voltage VDD can be provided from the main power supply in the host system 200 to the display panel 100. In this case, the power supply 140 does not need to output the pixel driving voltage VDD.

[0129] Under the control of the timing controller 130, the display panel driving circuit writes the pixel data of the input image into the pixels of the display panel 100. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0130] The display panel driving circuit can further include a touch sensor driver for driving a touch sensor. From Figures 9 to 10BThe touch sensor driver is omitted. The data driver 110 and the touch sensor driver may be integrated into a single driving integrated circuit (IC). In a mobile terminal or a wearable terminal, the timing controller 130, the power supply 140, the level shifter 150, the data driver 110, the touch sensor driver, etc. may be integrated into one driving IC (DIC), as Figure 10A and 10B shown in

[0131] The data driver 110 receives the pixel data of the input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 outputs a data voltage by converting the pixel data of the input image into a gamma-compensated voltage using a digital-to-analog converter (DAC). The gamma reference voltage is divided by a voltage divider circuit in the data driver 110 into gamma-compensated voltages for each gray level that are provided to the DAC. The DAC generates a data voltage as the gamma-compensated voltage corresponding to the gray value of the pixel data. The data voltage output from the DAC is output to the data line 102 through the corresponding data output channel of the data driver 110 via an output buffer.

[0132] The initialization data REF may be sent as a digital signal from the timing controller 130 to the data driver 110. In this case, the data driver 110 may output an initialization voltage Vref / VSS in response to the initialization data REF. The initialization data may represent the voltage level of the initialization voltage Vref / VSS.

[0133] The gate driver 120 may be formed on the display panel 100 together with the TFT array and wirings of the pixel array. The gate driver 120 may be disposed in the non-display area NA outside the display area AA of the display panel 100, or at least a part thereof may be disposed in the display area AA.

[0134] The gate driver 120 may include a plurality of shift registers for sequentially shifting the pulses of the gate signal. The gate driver 120 may be disposed on either the left non-display area NA or the right non-display area NA outside the display area AA in the display panel 100, so as to provide the gate signal to the gate line 103 in a single-feed method. In the single-feed method, the gate signal is applied to one end of the gate line. The gate driver 120 may be disposed in the left non-display area NA and the right non-display area NA of the display panel 100, so as to apply the gate signal to the gate line 103 in a dual-feed method. In the dual-feed method, the gate signal is applied to both ends of the gate line 103 simultaneously. At least some circuits of the gate driver 120 may be disposed within the display area AA.

[0135] Under the control of the timing controller 130, the gate driver 120 sequentially outputs pulses of a gate signal to the gate lines 103. The gate driver 120 can shift the pulses of the gate signal by using a shift register to sequentially provide the gate signal to the gate lines 103. The gate driver 120 can utilize a plurality of shift registers to output a plurality of gate signals having different phases, pulse widths, etc. The gate signal includes the first gate signal SCAN and the second gate signal EM as described above.

[0136] The timing controller 130 receives pixel data of an input image and a timing signal synchronized with the pixel data from the host system 200. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The data enable signal DE has a period of one horizontal period (1H).

[0137] The timing controller 130 controls the data driver 110 and the gate driver 120 by generating signals or timing information for controlling the operation timings of the data driver 110 and the gate driver 120 based on the timing signals (e.g., Vsync, Hsync, and DE) received from the host system 200.

[0138] The gate timing control signal generated from the timing controller 130 may be input to the shift register of the gate driver 120 through the level shifter 150. The level shifter 150 can receive the gate timing control signal and generate a start pulse and a shift clock, and thus provide them to the shift register in the gate driver 120. The input signal to the level shifter 150 may be a signal having a digital voltage signal level, and the output signal from the level shifter 150 may be an analog voltage signal that swings between a gate-on voltage VGL and a gate-off voltage VGH. The data timing control signal generated from the timing controller 130 is sent to the data driver 110. The data driver 110 can generate a source output enable signal SOE from the received data timing control signal.

[0139] The host system 200 can scale an image signal from a video source to match the resolution of the display panel 100, and can transmit it to the timing controller 130 together with the timing signal. In a mobile system, the host system 200 can be implemented with an application processor (AP). The host system 200 can transmit pixel data of an input image to the Figure 10A and Figure 10B shown driving IC (DIC). As Figure 10AAs shown in the figure, the host system 200 can be electrically connected to the driving IC (DIC) through a flexible printed circuit (e.g., flexible printed circuit (FPC)). As Figure 10A As shown in the figure, in the chip on glass (COG) process, the driving IC (DIC) can be attached to the display panel 100. As Figure 10B As shown in the figure, the driving IC (DIC) can be electrically connected to the wiring on the display panel 100 as a chip on film (COF) structure mounted on a flexible circuit film.

[0140] When a still image or always-on display (AOD) data is input, the timing controller 130 or the host system 200 can enter a low power mode to reduce the power consumption of the display device. In the normal mode, the pixels 101 can have a refresh rate of 60 Hz, 144 Hz, 240 Hz, etc. The refresh rate is the frequency at which pixel data is written to the pixels 101. In the low power mode, the refresh rate of the pixels 101 is reduced to a frequency lower than 60 [Hz], for example, 1 [Hz] to 30 [Hz]. When the refresh rate is 1 [Hz], the first frame out of 60 frames per second can be a refresh frame, and the next 59 frames can be hold frames. After the data voltage Vdata of the pixel data is charged to the pixels 101 during the refresh frame period, the pixels 101 can hold the data voltage charged in the previous refresh frame without newly charging the data voltage Vdata during the consecutive hold frame periods to maintain the light emitting state.

[0141] Figure 8A and 8B As shown in the figure, the switch circuit SW can be provided in the non-display area NA of the display panel 100, or can be provided in the data output channel of the data driver 110.

[0142] Figure 11 is a diagram illustrating an example of a circuit portion and stretchable wirings of a stretchable display device.

[0143] Referring to Figure 11 , the display panel of the stretchable display device includes: a plurality of circuit portions 162 separated on a stretchable substrate, and stretchable wirings 164 and 166 that electrically connect the circuit portions 162.

[0144] The data lines 102, gate lines 103, power lines, and clock lines connected to the shift register of the gate driver 120 can be implemented as stretchable wirings 164 and 166 provided on the stretchable substrate.

[0145] The stretchable wirings 164 and 166 include a plurality of first-direction stretchable wirings 164 and a plurality of second-direction stretchable wirings 166. The first-direction stretchable wirings 164 extend along the first direction X to electrically connect the circuit portions 162 adjacent in the first direction X. The second-direction stretchable wirings 166 extend along the second direction Y to electrically connect the circuit portions 162 adjacent in the second direction Y. The stretchable wirings 164 and 166 can be implemented as a wiring pattern that can be sufficiently stretched, such as a zigzag wiring or a waveform wiring. For a mesh wiring, the first-direction stretchable wirings 164 and the second-direction stretchable wirings 166 can be connected at the circuit portions 162.

[0146] In the display area AA, each of the circuit portions 162 includes one or more pixel circuits. The circuits in the gate driver 120 can be distributed among the circuit portions 162 provided in the non-display area NA and / or the display area AA. When the switch circuit SW is provided in the non-display area NA of the display panel 100, the switch circuit SW can be provided in the circuit portion 162 in the non-display area NA.

[0147] Figure 12 is a diagram illustrating one frame period and one horizontal period. Figure 13 is a diagram illustrating a connection structure of transmission lines between a timing controller and a driving IC on an EPI interface. Figure 14 is a waveform diagram illustrating an example of a multi-phase internal clock generated by a driving IC. The driving IC can include a data driver 110. In Figure 13 ,"GIP" represents the gate driver 120.

[0148] Referring to Figure 12 、 Figure 13 and Figure 14 , the vertical synchronization signal (Vsync) defines one frame period. The horizontal synchronization signal Hsync defines a horizontal period (1H). The data enable signal DE defines a valid data portion including pixel data to be written to a pixel. The pulse of the data enable signal DE is synchronized with the pixel data to be written to the pixel 101 of the display panel 100. One pulse period of the data enable signal DE is one horizontal period (1H).

[0149] One frame period is divided into an active interval AT in which pixel data of an input image is written to the pixel 101, and a vertical blanking period VB in which there is no pixel data.

[0150] The timing controller TCON can send data to the data drivers 110 of the driving ICs SIC1 to SIC4 through an embedded clock point-to-point interface (EPI). Although four driving ICs are shown in Figure 13 , depending on the size and resolution of the display panel 100, additional driving ICs can be added as needed.

[0151] The EPI interface can connect the timing controller TCON and the driver ICs SIC1 to SIC4 in a point-to-point manner, as Figure 13 shown, thus minimizing the number of wirings required in the transmission lines between the timing controller TCON and the driver ICs SIC1 to SIC4. The transmission lines connecting the timing controller TCON and the driver ICs SIC1 to SIC4 in a point-to-point manner include data wiring pairs. In the EPI interface, signals with built-in clocks are transmitted through the data wiring pairs. The signals with built-in clocks include control data for controlling the data drivers and gate drivers GIP of the driver ICs SIC1 to SIC4, and pixel data to be written to the pixels to reproduce the input image on the display area AA. Therefore, the EPI interface does not require separate clock and control wirings because signals including the clock, control data, and pixel data are serially transmitted through the same wiring pairs.

[0152] For the EPI interface, each of the driver ICs SIC1 to SIC4 may include a clock recovery circuit for clock and data recovery (CDR). The timing controller TCON sends a clock training pattern (or preamble) signal to the driver ICs SIC1 to SIC4 so that the phase and frequency of the recovered clock can be locked in the driver ICs SIC1 to SIC4. As Figure 14 shown, when the clock training pattern signal and the clock bits of the serially received signal DATA are input through the data wiring pairs, the driver ICs SIC1 to SIC4 recover the clock from the clock bits to generate a multi-phase internal clock CDR CLK. In Figure 14 this, "0011" is an example of the clock bits serially transmitted to the driver ICs SIC1 to SIC4. The clock bits can be encoded between data packets.

[0153] When the internal clock CDR CLK is locked in phase and frequency, the driver ICs SIC1 to SIC4 feedback a high logic level lock signal LOCK indicating the stable state of the output to the timing controller TCON. The lock signal LOCK is sequentially transmitted from the first driver IC SIC1 to the fourth driver IC SIC4, and the lock signal LOCK is fed back to the timing controller TCON from the fourth driver IC SIC4 through the lock feedback wiring.

[0154] In the signal transmission protocol of the EPI interface, before the timing controller TCON transmits the control data and pixel data of the input image, it sends a clock training mode signal to the driver ICs SIC1 to SIC4. When receiving the clock training mode signal, the driver ICs SIC1 to SIC4 recover the clock from the signal DATA received on the data wiring pair by performing clock training to generate an internal clock, and when the phase and frequency of the internal clock are stably fixed in all the driver ICs SIC1 to SIC4, they send a lock signal LOCK to the timing controller TCON to allow the establishment of a data link with the timing controller TCON.

[0155] In response to the lock signal LOCK received from the last driver IC SIC4, the timing controller TCON encodes the control data and pixel data and starts transmitting them on the data wiring pair to the driver ICs SIC1 to SIC4. The signal DATA output by the timing controller TCON is converted into a differential signal by the transmitter buffer of the timing controller TCON and transmitted to the driver ICs SIC1 to SIC4 through the data wiring pair. The wiring pair includes: a first wiring for transmitting the positive-phase signal of the differential signal and a second wiring for transmitting the anti-phase signal of the differential signal.

[0156] The driver ICs SIC1 to SIC4 can recover the control data by sampling the control data bits from the signal DATA received via the data wiring pair to the internal clock timing, and recover data timing control signals, gate timing control signals, etc. from the recovered control data.

[0157] The driver ICs SIC1 to SIC4 sample the bits of the pixel data from the signal DATA received via the wiring pair according to the internal clock timing, and then use a latch to convert the sampled bits of the pixel data into parallel data. The driver ICs SIC1 to SIC4 convert the pixel data into a data voltage and output it through an output buffer. The data voltage is provided to the data lines of the display panel 100.

[0158] Figure 15 is a waveform diagram illustrating the signal transmission protocol of the EPI interface.

[0159] Refer to Figure 15, in the first stage, Phase-I, the timing controller TCON transmits a clock training mode signal C / T of a constant frequency to driving ICs SIC1 to SIC4, and when a high logic level (H) lock signal LOCK is input via a lock feedback wiring, it executes a second stage, Phase-II, to convert a signal DATA encoded in a signal format defined by an EPI interface protocol into a differential signal and start transmitting it via a wiring pair. In the second stage, Phase-II, a control data packet CTRL is sent to the driving ICs SIC1 to SIC4.

[0160] After the second stage, Phase-II, the timing controller TCON executes a third stage, Phase-III, while the lock signal LOCK remains at a high logic level to transmit a video data packet including pixel data DATA of an input image to the driving ICs SIC1 to SIC4.

[0161] In Figure 15 , "Tlock" is a delay time until the lock signal LOCK is inverted to a high logic level (H). During the delay time Tlock, the clock training mode signal C / T is sent to the driving ICs SIC1 to SIC4 to lock the frequency and phase of an internal clock recovered by performing clock training processing in the driving ICs SIC1 to SIC4.

[0162] When a low logic level (L) lock signal LOCK is input from the last driving IC SIC4, the timing controller TCON re-executes the first stage, Phase-I, to resume clock training of the driving ICs SIC1 to SIC4 and transmits the clock training mode signal C / T to the driving ICs SIC1 to SIC4. If, during the execution of the second stage, Phase-II, and the third stage, Phase-III, in an unexpected situation, the lock signal LOCK is inverted to a low logic level (L) in any one of the driving ICs SIC1 to SIC4, the timing controller TCON executes the first stage, Phase-I, and sends the clock training mode signal C / T to the driving ICs SIC1 to SIC4 even if Phase-II or Phase-III is being executed. In this case, the driving ICs SIC1 to SIC4 do not receive the control data CTRL and the pixel data DATA.

[0163] Figure 16 is a diagram showing an example of one (1) data packet in an EPI interface.

[0164] Refer to Figure 16, a data packet of the signal DATA sent to the driving ICs SIC1 to SIC4 includes data bits, and clock bits EPI CLK allocated before and after the data bits. One bit transfer time is one UI (unit interval) time. Depending on the resolution of the display panel 100 or the number of data bits, one UI can vary.

[0165] The clock bits EPI CLK are allocated 4 UIs between adjacent data packets, and their logic values can be set to, but not limited to, "0011 (or LLHH)". When the number of bits for each color in the 4 sub-color data is 10 bits, a data packet of a pixel data can include 40 UI data bits and 4 UI clock bits. When the number of data bits is 8 bits and the pixel data includes R, G, and B data without white data W, a data packet can include 24 UI data bits and 4 UI clock bits, and the 24 UI data bits include 8-bit R sub-pixel data, 8-bit G sub-pixel data, and 8-bit B sub-pixel data.

[0166] Figure 17 is a diagram showing an example of the signal transmitted during the horizontal blank period.

[0167] Refer to Figure 17 , a horizontal period (1H) can be divided into a horizontal blank period HB without pixel data and a horizontal active period HA for transmitting pixel data DATA. The control data packet can be transmitted to the driving ICs SIC1 to SIC4 during the horizontal blank period HB.

[0168] The first phase Phase-I and the second phase Phase-II can be executed during the horizontal blank period HB. The horizontal blank period HB corresponds to the low logic level interval of the data enable signal DE. During the horizontal blank period HB, one or more control data packets CTRL can be transmitted. As Figure 15 and Figure 17 shown in, the initialization data REF representing the voltage level of the initialization voltage Vref / VSS can be encoded in the control data packet CTRL.

[0169] The data drivers of the driving ICs SIC1 to SIC4 can sample and latch the initialization data REF, and supply the initialization data REF to a DAC that outputs an initialization voltage Vref / VSS having a voltage level represented by the initialization data REF. Since the initialization data REF is updated in each horizontal period, the initialization voltage Vref / VSS can be applied as the same or different voltages for each pixel row L1 to Ln. When the initialization data REF is 4-bit data, the initialization voltage Vref / VSS can be selected from voltages subdivided into 16 steps. By using this method, the initialization voltage Vref / VSS can be applied as an optimal voltage according to the position of the display panel 100. For example, considering the voltage drop of the power supply line applied to the display panel, the reference voltage Vref can increase as the distance from the driving IC increases.

[0170] According to one or more embodiments of the present disclosure, the display device can be applied to a mobile device, a video phone, a smart watch, a watch phone, a wearable device, a foldable device, a rollable device, a bendable device, a flexible device, a curved device, a sliding device, a variable device, an electronic organizer, an e-book, a portable multimedia player (PMP), a personal digital assistant (PDA), an MP3 player, a mobile medical device, a desktop PC, a laptop PC, a netbook, a workstation, a navigator, a vehicle-mounted navigator, a vehicle-mounted display device, a vehicle-mounted device, a theater device, a theater display device, a television, a wallpaper device, a sign device, a game device, a laptop computer, a monitor, a camera, a camcorder, and household appliances, etc. In addition, the display device according to one or more embodiments of the present disclosure can be applied to an organic light-emitting lighting device or an inorganic light-emitting lighting device.

[0171] The above objects to be achieved by the present disclosure, the means for achieving the objects, and the effects of the present disclosure do not specify the essential features of the claims. Therefore, the scope of the claims is not limited to the disclosure of the present disclosure.

[0172] Although the embodiments of the present disclosure have been described in more detail with reference to the drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided only for illustrative purposes and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are exemplary in all aspects and do not limit the present disclosure.

Claims

1. A pixel circuit, comprising: a compensation circuit connected to the data line, the first gate line and the second gate line, the compensation circuit being configured to alternately receive a first voltage and a second voltage through the data line, receive a first gate signal through the first gate line, and receive a second gate signal through the second gate line; Light emitting element; a driving element, the driving element comprising a gate electrode configured to receive the second voltage via the compensation circuit, the driving element being configured to generate a current for driving the light emitting element based on the second voltage; as well as a switching element, the switching element comprising a gate electrode configured to receive the second gate signal via the compensation circuit, the switching element configured to switch a path of a current between the driving element and the light emitting element based on the second gate signal, The light emitting element, the driving element and the switching element are connected in series between a first power line and a second power line.

2. The pixel circuit according to claim 1, wherein: The compensation circuit comprises: a capacitor coupled between the first node and the second node; a first switching element connected between the data line and the first node and configured to be turned on in response to a gate-on voltage of the first gate signal to electrically connect the data line to the first node; a second switching element connected between the second node and a third node and configured to be turned on in response to a gate-on voltage of the first gate signal to electrically connect the second node to the third node; a third switching element connected to the first node and configured to be turned on in response to a gate-on voltage of the second gate signal to apply the first voltage to the first node; and a fifth switching element connected to a fourth node and configured to be turned on in response to a gate-on voltage of the first gate signal to apply the first voltage to the fourth node; The switch element includes a fourth switch element connected between the third node and the fourth node and configured to be turned on in response to a gate-on voltage of the second gate signal to electrically connect the third node to the fourth node; The driving element includes a gate electrode connected to the second node, a first electrode connected to the first power line configured to receive a pixel driving voltage, and a second electrode connected to the third node; The light emitting element includes an anode electrode connected to the fourth node, and a cathode electrode connected to the second power line configured to receive a cathode voltage; The first voltage is a reference voltage or the cathode voltage, and the second voltage is a data voltage of pixel data; and The data line is configured to receive a data voltage of the pixel data after receiving the reference voltage or the cathode voltage. 3 . The pixel circuit according to claim 2 , wherein during one horizontal period, the first node is configured to simultaneously receive the reference voltage via the data line and the first switching element and via the third switching element. 4 . The pixel circuit according to claim 3 , wherein the second node, the third node, and the fourth node are configured to receive the reference voltage when the reference voltage is applied to the first node.

5. The pixel circuit according to claim 3, wherein: The driving period of the pixel circuit includes a first stage in which the pixel circuit is configured to be initialized, a second stage in which the capacitor is configured to receive the threshold voltage of the driving element and the data voltage, and a third stage in which the light emitting element is configured to emit light; The first gate signal is configured to be at a gate-on voltage in the first stage and the second stage, and to be at a gate-off voltage in the third stage; The second gate signal is configured to be at a gate-off voltage in the second stage, and at a gate-on voltage in the first stage and the third stage; The first switching element, the second switching element and the fifth switching element are configured to be turned on in response to a gate-on voltage of the first gate signal, and to be turned off in response to a gate-off voltage of the first gate signal; The third switching element and the fourth switching element are configured to be turned on in response to a gate-on voltage of the second gate signal, and to be turned off in response to a gate-off voltage of the second gate signal; The one horizontal period includes the periods of the first stage and the second stage; and The data line is configured to be at the reference voltage in the first phase and at the data voltage in the second phase.

6. The pixel circuit according to claim 5, wherein: The first switching element includes a gate electrode configured to receive the first gate signal, a first electrode connected to the data line, and a second electrode connected to the first node; The second switching element includes a gate electrode configured to receive the first gate signal, a first electrode connected to the second node, and a second electrode connected to the third node; The third switching element includes a gate electrode configured to receive the second gate signal, a first electrode connected to the first node, and a second electrode configured to receive the reference voltage; The fourth switching element includes a gate electrode configured to receive the second gate signal, a first electrode connected to the third node, and a second electrode connected to the fourth node; and The fifth switching element includes a gate electrode configured to receive the first gate signal, a first electrode configured to receive the reference voltage, and a second electrode connected to the fourth node. 7 . The pixel circuit according to claim 2 , wherein during one horizontal period, the first node is configured to simultaneously receive the cathode voltage via the data line and the first switching element and via the third switching element. 8 . The pixel circuit of claim 7 , wherein the second node, the third node, and the fourth node are configured to receive the cathode voltage when the cathode voltage is applied to the first node.

9. The pixel circuit according to claim 7, wherein: The driving period of the pixel circuit includes a first stage in which the pixel circuit is configured to be initialized, a second stage in which the capacitor is configured to receive the threshold voltage of the driving element and the data voltage, and a third stage in which the light emitting element is configured to emit light; The first gate signal is configured to be at a gate-on voltage in the first stage and the second stage, and to be at a gate-off voltage in the third stage; The second gate signal is configured to be at a gate-off voltage in the second stage, and at a gate-on voltage in the first stage and the third stage; The first switching element, the second switching element and the fifth switching element are configured to be turned on in response to a gate-on voltage of the first gate signal, and to be turned off in response to a gate-off voltage of the first gate signal; The third switching element and the fourth switching element are configured to be turned on in response to the gate-on voltage of the second gate signal, and to be turned off in response to the gate-off voltage of the second gate signal; The one horizontal period includes the periods of the first stage and the second stage; and The data line is configured to be at the cathode voltage in the first phase and at the data voltage in the second phase.

10. The pixel circuit according to claim 9, wherein: The first switching element includes a gate electrode configured to receive the first gate signal, a first electrode connected to the data line, and a second electrode connected to the first node; The second switching element includes a gate electrode configured to receive the first gate signal, a first electrode connected to the second node, and a second electrode connected to the third node; The third switching element includes a gate electrode configured to receive the second gate signal, a first electrode connected to the first node, and a second electrode configured to receive the cathode voltage; The fourth switching element includes a gate electrode configured to receive the second gate signal, a first electrode connected to the third node, and a second electrode connected to the fourth node; and The fifth switching element includes a gate electrode configured to receive the first gate signal, a first electrode configured to receive the cathode voltage, and a second electrode connected to the fourth node.

11. The pixel circuit according to claim 1, wherein: The first voltage is a constant voltage, and the first voltage is a reference voltage or a cathode voltage; The second voltage is a data voltage corresponding to pixel data; and During one horizontal period, the compensation circuit is further configured to receive the first voltage through the data line and then receive the second voltage through the data line.

12. The pixel circuit according to claim 11, wherein: The one horizontal period includes a horizontal blank period and a horizontal effective period; During the horizontal blank period, the compensation circuit is further configured to receive the first voltage instead of the second voltage through the data line to initialize the pixel circuit; and During the horizontal effective period, the compensation circuit is further configured to receive the second voltage through the data line to write the pixel data to the pixel circuit.

13. The pixel circuit according to claim 11, wherein: The one horizontal period includes a horizontal blank period and a horizontal effective period; During the horizontal blank period, the first gate signal and the second gate signal are at a gate-on voltage; and During the horizontal effective period, the first gate signal is at the gate-on voltage, and the second gate signal is at the gate-off voltage.

14. A display device, comprising: A display panel, the display panel comprising a plurality of data lines, a plurality of gate lines, a plurality of power lines and a plurality of pixel circuits, at least one of the pixel circuits being the pixel circuit according to claim 1; a data driver configured to output the first voltage and the second voltage; a gate driver configured to provide at least one gate signal to the gate line; as well as a control circuit configured to control the data driver and the gate driver, The plurality of data lines include the data line, the plurality of gate lines include the first gate line and the second gate line, the at least one gate signal includes the first gate signal and the second gate signal, and the plurality of power lines include the first power line and the second power line.

15. The display device according to claim 14, wherein: The compensation circuit comprises: a capacitor coupled between the first node and the second node; a first switching element connected between the data line and the first node and configured to be turned on in response to a gate-on voltage of the first gate signal to electrically connect the data line to the first node; a second switching element connected between the second node and a third node and configured to be turned on in response to a gate-on voltage of the first gate signal to electrically connect the second node to the third node; a third switching element connected to the first node and configured to be turned on in response to a gate-on voltage of the second gate signal to apply the first voltage to the first node; and a fifth switching element connected to a fourth node and configured to be turned on in response to a gate-on voltage of the first gate signal to apply the first voltage to the fourth node; The switch element includes a fourth switch element connected between the third node and the fourth node and configured to be turned on in response to a gate-on voltage of the second gate signal to electrically connect the third node to the fourth node; The driving element includes a gate electrode connected to the second node, a first electrode connected to the first power line configured to receive a pixel driving voltage, and a second electrode connected to the third node; and The light emitting element includes an anode electrode connected to the fourth node, and a cathode electrode connected to the second power line configured to receive a cathode voltage, and The first voltage includes a reference voltage or the cathode voltage, and the second voltage includes a data voltage of pixel data.

16. The display device according to claim 14, wherein the control circuit is configured to transmit initialization data to the data driver as a digital signal; and The data driver is configured to output the first voltage in response to the initialization data.

17. The display device according to claim 16, wherein: The control circuit is configured to update the initialization data in each horizontal period; and The first voltage has a voltage level corresponding to the initialization data.

18. The display device according to claim 14, wherein the display panel comprises: A plurality of circuit parts having the pixel circuits provided therein; and a plurality of stretchable wirings electrically connecting the plurality of circuit portions, and The stretchable wiring includes the data line, the gate line and the power line.

19. The display device according to claim 14, further comprising: A switch circuit is configured to alternately select one of the first voltage and the second voltage and provide the selected one of the first voltage and the second voltage to the data line. 20 . The display device according to claim 19 , wherein the switch circuit is further configured to select and supply the first voltage to the data line and then select and supply the second voltage to the data line within one horizontal period.

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