Amorphous silicon thin film transistor flexible display screen source electrode driving chip

Abstract

The invention discloses an amorphous silicon thin film transistor flexible display screen source electrode driving chip. According to the chip scheme, low-dropout differential signals are converted into single-end digital signals by introducing the LVDS receiver, the anti-interference capacity of the signals can be greatly improved, the signal transmission rate can be increased, and external input data signals can be stably received at a high speed. In order to cope with the challenge that the area of a chip is increased in an exponential level due to the main color depth of the resolution of a factor-to-analog converter, a two-level cascaded 6-bit DAC is introduced, and the occupied area of the chip is effectively reduced. In order to solve the problem of low screen brightness caused by insufficient driving output voltage range, the invention provides a 40V high-voltage operational amplifier, so that the driving of an electronic paper screen is realized, and the problem of low display brightness of amorphous silicon electronic paper is solved. Meanwhile, the circuit is compatible with the gamma correction function, the display effect is optimized through the gamma correction circuit, and the image quality is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a source driver chip for an amorphous silicon thin film transistor flexible display screen. Background Art

[0002] A display screen is a key medium for information interaction. Electronic paper display screens are unique for their excellent reading comfort and the inherent interactivity of electronic devices, making them a popular choice in this field.

[0003] The maturity of the amorphous silicon thin film transistor production chain, combined with its low cost and excellent product stability, makes it the main material for flexible display screens. Electro-wetting display technology controls the expansion and contraction of chromogenic ink by applying an electric field, thereby adjusting the gray scale, showing strong chromogenic ability and technological maturity.

[0004] However, electronic paper display screens using this technology face the problem of low brightness, which is due to insufficient light penetration caused by the limited output range of the driver. At the same time, the hydrophobic insulating layer in the display panel based on electro-wetting technology will undergo surface charge transfer under the action of an electric field. Over time, the accumulation of charges in this layer will change the electric field force driving the ink, resulting in ink backflow, manifested as a gradual decrease in the pixel aperture ratio, and thus having an adverse impact on the display performance. Summary of the Invention

[0005] In view of the problems and difficulties in the above-mentioned existing background, an embodiment of the present invention provides a source driver chip for an amorphous silicon thin film transistor flexible display screen.

[0006] The present invention provides a source driver chip for an amorphous silicon thin film transistor flexible display screen, including a digital circuit part and an analog circuit part; wherein, the digital circuit part specifically includes a serial interface, a voltage selector, a shift register, and a first latch; the analog circuit part includes a signal receiver, a gamma correction circuit, a first digital-to-analog converter, and a first operational amplifier;

[0007] Wherein, the signal receiver is used to receive a low-voltage differential signal input, demodulate the low-voltage differential signal into a single-ended digital signal, and store the single-ended digital signal in the first latch through the shift register;

[0008] The gamma correction circuit is used to perform gamma correction on the voltage signals of multiple nodes on the reference resistor string according to the linear voltage signal output by the voltage selector;

[0009] The first digital-to-analog converter is used to read the single-ended digital signal from the latch module, and select a node voltage signal from the reference resistor string as an analog voltage signal output according to the single-ended control signal;

[0010] The first operational amplifier is used to amplify and drive the analog voltage signal, and then output a driving voltage signal.

[0011] Further, the signal receiver is implemented by an LVDS receiver; it includes a preamplifier, a hysteresis comparator, a second latch, a current comparator, and an output buffer; the low-voltage differential signal input includes a positive low-voltage differential signal input and a negative low-voltage differential signal input;

[0012] Among them, the preamplifier includes a first PMOS transistor pair and a first NMOS transistor pair; the first PMOS transistor pair is used to receive the positive low-voltage differential signal input; the first NMOS transistor pair is used to receive the negative low-voltage differential signal input;

[0013] The hysteresis comparator includes a second NMOS transistor pair and a third NMOS transistor pair; the second NMOS transistor pair is used to set the hysteresis threshold; the third NMOS transistor pair is used to suppress the low-frequency noise of the low-voltage differential signal according to the hysteresis threshold;

[0014] The second latch includes a fourth NMOS transistor pair; the fourth NMOS transistor pair is used to suppress the high-frequency noise of the low-voltage differential signal;

[0015] The current comparator includes a first P-NMOS transistor pair and a second P-NMOS transistor pair; the first P-NMOS transistor pair is used to convert the low-voltage differential signal into a single-ended digital signal; the second P-NMOS transistor pair is used as an inverter to control the phase of the single-ended digital signal;

[0016] The output buffer includes a third P-NMOS transistor pair; the third P-NMOS transistor pair is used as a buffer.

[0017] Further, the gamma correction circuit is implemented by a 4-bit embedded DAC operational amplifier; the 4-bit embedded DAC operational amplifier is designed with a multi-layer structure. Each layer of the 4-bit embedded DAC operational amplifier corresponds to a set of linear voltage signal outputs of the voltage selector, and the node voltage signals at different voltage division positions of the reference resistor string are changed according to the voltage of the linear voltage signal within the 4-bit embedded DAC operational amplifier.

[0018] Further, each 4-bit embedded DAC operational amplifier includes a plurality of linear enhancement arrays and a second operational amplifier. Each linear enhancement array contains a plurality of linear enhancement differential pairs; the linear enhancement differential pairs are used to receive the linear voltage signals output by the voltage selector, and use the embedded DAC to perform non-linear transformation on the node voltage signals of the reference resistor string based on the linear voltage signals, so that the node voltage signals of the reference resistor string conform to the gamma correction curve.

[0019] Further, the 4-bit embedded DAC operational amplifier includes five linear enhancement arrays, and the corresponding tail current ratios of the linear enhancement arrays are 1:1:2:4:8.

[0020] Further, the first digital-to-analog converter is designed with a 6-bit two-stage cascade structure, including a first-stage structure and a second-stage structure; the first-stage structure is used to perform a tree topology conversion on the high three-bit input to form a high-voltage signal including high and low level signals; the second-stage structure is used to select from the low three-bit input, and perform digital-to-analog conversion within the high and low level ranges of the high-voltage signal according to the selection result to obtain an analog voltage signal output.

[0021] Further, in the first digital-to-analog converter, the first-stage structure is implemented using a tree digital-to-analog converter; the second-stage structure is implemented using a voltage selector and an embedded digital-to-analog converter.

[0022] Further, the first operational amplifier is a high-voltage rail-to-rail operational amplifier, including a differential pair input stage circuit and a folded cascode stage circuit; the differential pair input stage circuit is used to receive an analog voltage signal input and a feedback voltage signal input; the folded cascode stage circuit is used to amplify the analog voltage signal input to obtain a driving voltage signal output.

[0023] Further, the differential pair input stage circuit includes a fifth NMOS transistor pair and a second PMOS transistor pair; the second PMOS transistor pair is used to receive the low-level input of the analog voltage signal; the fifth NMOS transistor pair is used to receive the high-level input of the analog voltage signal;

[0024] The folded cascode stage circuit includes a third PMOS transistor pair, a fourth PMOS transistor pair, a sixth NMOS transistor pair, and a seventh NMOS transistor pair; the third PMOS transistor pair and the sixth NMOS transistor pair are used as the common gates in the folded cascode structure to output a first voltage signal and a second voltage signal; the fourth PMOS transistor pair and the seventh NMOS transistor pair are respectively used to stabilize the voltage ranges of the first voltage signal and the second voltage signal; the first operational amplifier further includes an output PMOS transistor and an output NMOS transistor, which are respectively used to receive the first voltage signal and the second voltage signal and convert them into a high-level signal and a low-level signal of the driving voltage signal for output.

[0025] Further, a feedback circuit is further included; the feedback circuit is connected to the output and the negative input terminal of the first operational amplifier; the feedback circuit is used to perform proportional amplification on the driving voltage signal.

[0026] Embodiments of the present invention have the following beneficial effects: The source driver chip for the amorphous silicon thin-film transistor flexible display screen proposed by the present invention uses an LVDS receiver as a signal receiver for data transmission. This can not only greatly improve the anti-interference ability of the signal, but also enhance the signal transmission rate, stably and rapidly receiving external input data signals. At the same time, the embodiments of the present invention implement compatibility with the gamma correction function through a gamma correction circuit, thereby optimizing the display effect and improving the image quality. The high-voltage rail-to-rail operational amplifier proposed by the present invention is used as the output stage of the chip, effectively amplifying and driving the output voltage to the corresponding pixel points, with a relatively high slew rate and driving ability. Through the chip design proposed by the embodiments of the present invention, the problem of low brightness of amorphous silicon electronic paper displays can be effectively solved.

[0027] Additional aspects and advantages of the present invention will be given in the following description section, some of which will become apparent from the following description, or can be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0029] Figure 1 It is a schematic diagram of the overall structure of the source driver chip for the amorphous silicon thin-film transistor flexible display screen provided by the present invention.

[0030] Figure 2 It is a schematic diagram of the structure of the LVDS receiver of the present invention.

[0031] Figure 3 It is a schematic diagram of the Monte Carlo simulation results of the LVDS receiver of the present invention at -20°C to 75°C.

[0032] Figure 4 It is a schematic diagram of the implementation process of the gamma correction circuit of the present invention.

[0033] Figure 5 It is a schematic diagram of the reference curve area range after gamma correction of the present invention.

[0034] Figure 6 It is a schematic diagram of the reference curve effect after gamma correction of the present invention.

[0035] Figure 7 It is a schematic diagram of the structure of the 6-bit two-stage digital-to-analog converter of the present invention.

[0036] Figure 8 It is a schematic diagram of the structure of the high-voltage rail-to-rail operational amplifier of the present invention.

[0037] Figure 9 It is a schematic diagram of the simulation result output by the driving chip of the present invention. Specific embodiments

[0038] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the following further details the present application in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0039] Aiming at the problems and difficulties in the above-mentioned existing background, the present invention provides a design solution for an amorphous silicon flexible display source driving chip. This solution realizes high-speed and stable signal reception by introducing an LVDS (Low-Voltage Differential Signaling) receiver to convert low-voltage differential signals into single-ended digital signals. To address the challenge of exponential growth of chip area due to the main color depth of the analog-to-digital converter resolution, a two-stage cascaded 6-bit DAC (Digital-to-Analog Converter) is introduced in this paper. To solve the problem of insufficient driving output voltage range resulting in low screen brightness, a 40V high-voltage operational amplifier is proposed in this design to drive the e-paper screen. At the same time, the designed circuit is compatible with the gamma correction function.

[0040] As Figure 1 shown, the amorphous silicon thin-film transistor flexible display source driving chip provided by the embodiment of the present invention includes a digital circuit part and an analog circuit part; among them, the digital circuit part specifically includes a serial interface, a voltage selector, a shift register, and a first latch; the analog circuit part includes a signal receiver, a gamma correction circuit, a first digital-to-analog converter, and a first operational amplifier;

[0041] Among them, the signal receiver is used to receive the input of low-voltage differential signals, demodulate the low-voltage differential signals into single-ended digital signals, and store the single-ended digital signals in the first latch through the shift register;

[0042] The gamma correction circuit is used to perform gamma correction on the voltage signals of multiple nodes on the reference resistor string according to the linear voltage signal output by the voltage selector;

[0043] The first digital-to-analog converter is used to read the single-ended digital signals from the latch module, and select the node voltage signals from the reference resistor string as analog voltage signals for output according to the single-ended control signals;

[0044] The first operational amplifier is used to amplify and drive the analog voltage signals, and then output the driving voltage signals.

[0045] Compared with traditional differential signal to single-ended digital signal receivers, the embodiments of the present invention can still maintain a high signal reception sensitivity in a low voltage difference environment, and can accurately identify tiny differential signal changes. Secondly, due to the optimized circuit structure, the power consumption of this receiver is significantly reduced, which has extremely high practical value in application scenarios with strict power consumption requirements such as portable devices. Moreover, through the carefully designed anti-interference circuit, this receiver has excellent electromagnetic interference resistance and can work stably in a complex electromagnetic environment.

[0046] The digital circuits included in the chip design of the embodiments of the present invention include a serial interface, a voltage selector, a shift register, and a first latch, which are connected to each other through an SPI communication bus. In the analog circuit part, the chip design of the embodiments of the present invention mainly includes a signal receiver, a gamma correction circuit, a first digital-to-analog converter, and a first operational amplifier.

[0047] The signal receiver of the embodiments of the present invention is implemented using an LVDS receiver. The circuit structure of the LVDS receiver is as Figure 2 shown, which includes a pre-amplifier, a hysteresis comparator, a second latch, a current comparator, and an output buffer. The low-voltage differential signal input includes a positive low-voltage differential signal input and a negative low-voltage differential signal input.

[0048] Among them, the pre-amplifier includes a first PMOS transistor pair (M1, M2) and a first NMOS transistor pair (M3, M4); the first PMOS transistor pair is used to receive the positive low-voltage differential signal input; the first NMOS transistor pair is used to receive the negative low-voltage differential signal input.

[0049] The hysteresis comparator includes a second NMOS transistor pair (M5, M6) and a third NMOS transistor pair (M7, M8); the second NMOS transistor pair is used to set the hysteresis threshold; the third NMOS transistor pair is used to suppress the low-frequency noise of the low-voltage differential signal according to the hysteresis threshold;

[0050] The second latch includes a fourth NMOS transistor pair (M9, M10); the fourth NMOS transistor pair is used to suppress the high-frequency noise of the low-voltage differential signal.

[0051] The current comparator includes a first P-NMOS transistor pair (M11, M12) and a second P-NMOS transistor pair (M13, M14); the first P-NMOS transistor pair is used to convert the low-voltage differential signal into a single-ended digital signal; the second P-NMOS transistor pair is used as an inverter to control the phase of the single-ended digital signal.

[0052] The output buffer includes a third P-NMOS transistor pair (M15, M16); the third P-NMOS transistor pair is used as a buffer.

[0053] The LVDS receiver provided in the embodiment of the present invention has a rail-to-rail input stage (covering the voltage range of VDD1-VSS1), which can ensure sufficient bandwidth and gain so as to effectively capture and amplify the signal regardless of whether the common-mode level of the input signal is a low signal bit or a high signal bit. In the LVDS receiver, a high-speed low-voltage differential signal can be demodulated into a single-ended digital signal to provide a clock and data, so as to convert the digital signal into a corresponding output gray-scale voltage value in a 6-bit DAC of an analog circuit. The Monte Carlo simulation results of the circuit under temperature change are as Figure 3 shown. Figure 3 In the simulation, 900 temperature values are randomly selected from -25°C to 75°C. It can be seen that the LVDS receiver designed in the embodiment of the present invention has good stability and is not easily affected by temperature and chip process corners.

[0054] The gamma correction circuit in the embodiment of the present invention is implemented by using a 4-bit embedded DAC operational amplifier. The 4-bit embedded DAC operational amplifier has both the ability of digital-to-analog conversion and driving. By changing the node voltage value of the reference resistor output curve, the linear output curve is changed into a non-linear output curve, thereby realizing the gamma correction function.

[0055] Specifically, as Figure 4 shown, in the embodiment of the present invention, a linear digital input signal is received through a serial interface and stored in the register 4-bit FVR1-7<3:0>. The register is read and written through a voltage selector, and a low-level signal VR1-7 and a voltage signal VINP0-3 are output. The output content of the voltage signal VINP0-3 is a high-level signal VH or a low-level signal VL, and VH and VL are two adjacent node voltage levels. The 4-bit embedded DAC operational amplifier is designed with a 7-layer structure, corresponding to the 7 groups of linear voltage signal outputs of the voltage selector respectively. Inside the 4-bit embedded DAC operational amplifier, the node voltage signals at different voltage-dividing positions of the reference resistor string are changed according to the voltage of the linear voltage signal.

[0056] In the embodiments of the present invention, each 4-bit embedded DAC operational amplifier includes five linear enhancement arrays and a second operational amplifier. The tail current ratios corresponding to the linear enhancement arrays are 1:1:2:4:8, and the second operational amplifier functions as an output buffer. Each linear enhancement array contains multiple linear enhancement differential pairs (M1, M2), (M3, M4), (M5, M6), and (M7, M8). Among them, (M1, M2) and (M3, M4) serve as the differential pair input stage to receive high-level input and low-level input, and (M5, M6) and (M7, M8) are the input differential pair linear enhancement structures. The embedded DAC performs a non-linear transformation on the node voltage signal of the reference resistor string based on a linear voltage signal, so that the node voltage signal of the reference resistor string conforms to the gamma correction curve. The node change region of the embedded DAC operational amplifier on the linear reference curve is as Figure 5 shown, Figure 5 and the gamut range of each color in it represents the change range of a node voltage. Figure 6 Four possible final gamma correction output effects are shown in it. Compared with the traditional gamma correction circuit, due to the high-precision characteristics of the embedded DAC, the embodiments of the present invention can achieve a more refined adjustment of the gamma correction curve and can meet the strict requirements of different display devices for gamma correction.

[0057] In the embodiments of the present invention, the first digital-to-analog converter is designed with a 6-bit two-stage cascaded structure, including a first-stage structure and a second-stage structure; the first-stage structure is used to perform a tree topology conversion on the high three bits of the input to form a high-voltage signal including high and low level signals; the second-stage structure is used to select among the low three bits of the input and perform digital-to-analog conversion within the high and low level ranges of the high-voltage signal according to the selection result to obtain an analog voltage signal output.

[0058] The structure of the 6-bit two-stage digital-to-analog converter is as Figure 7 shown. Figure 7 (a) shows the first-stage structure, which uses a dual-output tree digital-to-analog converter (DAC) to convert the high three bits D<5:3> of the 6-bit data input into two adjacent node voltages VH and VL. Figure 7 (b) is the second-stage structure, which is implemented using a voltage selector and an embedded digital-to-analog converter. Using a 1-of-2 voltage selector and a 3-bit embedded digital-to-analog converter operational amplifier, a voltage is selected between VH and VL according to the low three bits of the input for output. These low three bits are related to Figure 7(a)'s high three bits are combined to generate the final output voltage VOUT, which is the output of the 6-bit digital-to-analog converter. The 6-bit digital-to-analog converter in the embodiment of the present invention adopts a two-stage cascade design, effectively alleviating the problem of exponential growth of chip area caused by the increase in the number of input bits. While ensuring the overall accuracy, the manufacturing cost is reduced. The proposed two-stage DAC reduces 48 groups of switches compared with the single-stage DAC. Although the area reduction of a single channel is not significant, as the number of channels of the source driver chip increases to 768 channels, the design of the 6-bit two-stage digital-to-analog converter may reduce the area occupied by 48×768 groups of switches. Compared with the single-stage DAC, the area of the 6-bit two-stage DAC proposed in the embodiment of the present invention is approximately reduced by 75%.

[0059] In the embodiment of the present invention, the first operational amplifier is a high-voltage rail-to-rail operational amplifier, including a differential pair input stage circuit and a folded cascode stage circuit; the differential pair input stage circuit is used to receive the input of the analog voltage signal and the input of the feedback voltage signal; the folded cascode stage circuit is used to amplify the input of the analog voltage signal to obtain the output of the driving voltage signal.

[0060] Among them, the differential pair input stage circuit includes the fifth NMOS transistor pair (M1, M2) and the second PMOS transistor pair (M3, M4); the second PMOS transistor pair is used to receive the low-level input (VINP-, VINN-) of the analog voltage signal; the fifth NMOS transistor pair is used to receive the high-level input (VINP+, VINN+) of the analog voltage signal;

[0061] The folded cascode stage circuit includes the third PMOS transistor pair (M5, M6), the fourth PMOS transistor pair (M7, M8), the sixth NMOS transistor pair (M9, M10) and the seventh NMOS transistor pair (M11, M12); the third PMOS transistor pair and the sixth NMOS transistor pair are used as the common gates in the folded cascode structure to output the first voltage signal (Vo1) and the second voltage signal (Vo2); the fourth PMOS transistor pair and the seventh NMOS transistor pair are respectively used to stabilize the voltage ranges of the first voltage signal and the second voltage signal; the first operational amplifier further includes an output PMOS transistor (M13) and an output NMOS transistor (M14), which are respectively used to receive the first voltage signal and the second voltage signal and convert them into the high-level signal (Vout+) and the low-level signal (Vout-) of the driving voltage signal for output.

[0062] As Figure 8 shown, the high-voltage rail-to-rail operational amplifier proposed in the embodiment of the present invention adopts a folded cascode architecture design. The resistor shown by the red dotted line reduces the power consumption while adapting to a large voltage drop. Given that the gate-source voltage rating of the 40V high-voltage MOSFET is limited to 5.5V, it is crucial to limit the amplitudes of Vo1 and Vo2 at the output of the first stage of the operational amplifier. AsFigure 8 As shown, transistors M1, M2, M3, and M4 play key roles in stabilizing V GS,M5 and V GS,M6 respectively. When the MOSFETs in the load branch are operating normally, the operating voltage ranges of Vo1 and Vo2 are limited by the voltages of VB1, VB2, VB3, and VB4. Therefore, the following equations can be established: VB2 + V THP,M2 < Vo1 < VB1 + V THP,M1 and VB4 - V THN,M4 < VO2 < VB3 - V THN,M3 ; where V THP and V THN represent the threshold voltages of the corresponding MOS transistors M1 to M4.

[0063] The embodiment of the present invention uses a high-voltage rail-to-rail operational amplifier as the core processing component, enabling the circuit to have high linearity and fast response capabilities. When processing high-speed changing image signals, it can still maintain a good calibration effect. Specifically, the rail-to-rail input-output characteristics enable it to process signals close to the power supply rails, greatly improving the dynamic range of the signals and performing excellently in some applications with high requirements for the signal processing range. Secondly, due to the adoption of a special circuit structure design, the operational amplifier can still maintain good linearity and stability in a high-voltage environment, effectively reducing signal distortion. Thirdly, it provides a high slew rate in a high-voltage environment, effectively enhancing the driving voltage conversion rate.

[0064] The design of the high-voltage rail-to-rail operational amplifier in the embodiment of the present invention further includes a feedback circuit; the feedback circuit is connected to the output and the negative input terminal of the first operational amplifier; the feedback circuit is used to proportionally amplify the driving voltage signal. Through the design of the feedback network, the circuit of the embodiment of the present invention has strong anti-interference capabilities, can operate stably in a complex electrical environment, and ensures the accuracy of gamma calibration.

[0065] The output effect of the chip in the embodiment of the present invention is as Figure 9 shown. Assuming that the common potential of the pixels is 0V. When the input is all zero, the output is -20V; when the input is all one, the output is +20V driving voltage. The two-stage data latch ensures that the data is fully received before being output to the screen, ensuring that all channels can output simultaneously. A pair of LVDS input channels continuously input 6-bit data to determine the gray voltage of an output channel, effectively improving the sampling rate. In the embodiment of the present invention, under a large load composed of a 5-kiloohm resistor and a 75-picofarad capacitor, the time for one row reaches 23 microseconds, which makes it very suitable for amorphous silicon thin-film transistor displays. This single-chip solution can drive a mobile display with a resolution of 1360×768 at a frame rate of 30 Hz, and the time required for one row corresponding to this frame rate is 23.5 microseconds, fully meeting the design requirements.

[0066] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the embodiments of the present invention are all information and data that have been authorized by the user or fully authorized by all parties. And the collection, use, and processing of relevant data need to comply with the relevant laws, regulations, and standards of relevant countries and regions, and corresponding operation entrances are provided for users to choose to authorize or refuse.

[0067] Those skilled in the art can understand that the modules in the devices in the embodiments of the present invention can be adaptively changed and arranged in one or more devices different from this embodiment. The modules or units or components in the embodiments of the present invention can be combined into one module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, any combination can be adopted to combine all the features disclosed in this specification (including the corresponding claims, abstract, and drawings) and all the processes or units of any method or device so disclosed. Unless otherwise explicitly stated, each feature disclosed in this specification (including the corresponding claims, abstract, and drawings) can be replaced by an alternative feature that provides the same, equivalent, or similar purpose.

[0068] Through the description of the above embodiments, those skilled in the art can understand that for the convenience and conciseness of description, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

[0069] Moreover, each embodiment in this specification is described in a progressive manner, and the same or similar parts between each embodiment can be referred to each other. In particular, for embodiments such as devices and equipment, since they are basically similar to the method embodiments, the relevant parts can be referred to the partial description of the method embodiments. The above-described embodiments of devices, equipment, etc. are only illustrative. The modules, units, etc. described as separate components may or may not be physically separated, that is, they may be located in one place, or they may be distributed to multiple places, such as the nodes of a system network. Specifically, some or all of the modules and units can be selected according to actual needs to achieve the purpose of the above embodiment solutions. Those skilled in the art can understand and implement without creative labor.

[0070] It should be understood that each part of the present invention can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0071] In the description of this specification, the descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0072] In addition, the terms "first", "second", etc. used in the embodiments of the present invention are only for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated in this embodiment. Thus, the features defined with the terms "first", "second", etc. in the embodiments of the present invention can explicitly or implicitly indicate that at least one such feature is included in this embodiment. In the description of the present invention, the meaning of the word "plural" is at least two or more than two, such as two, three, four, etc., unless otherwise specifically defined in the embodiment.

[0073] In the embodiments of the present invention, the term "comprising", "including", or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, article, or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article, or device. Without further limitation, the element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article, or device including that element. In addition, components, features, and elements with the same name in different embodiments of the present invention may have the same meaning or may have different meanings, and their specific meanings need to be determined based on their explanations in the specific embodiment or further in combination with the context of the specific embodiment.

[0074] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention. After considering the specification and practicing the present invention, those skilled in the art will readily conceive of other embodiments of the present invention. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include known common general knowledge or conventional technical means in the technical field not disclosed by the present invention. The specification and embodiments are only to be considered as exemplary, and the true scope and spirit of the present invention are pointed out by the following claims.

Claims

1. An amorphous silicon thin film transistor flexible display screen source driver chip, characterized in that: It includes a digital circuit part and an analog circuit part; wherein the digital circuit part specifically includes a serial interface, a voltage selector, a shift register and a first latch; the analog circuit part includes a signal receiver, a gamma correction circuit, a first digital-to-analog converter and a first operational amplifier; The signal receiver is used to receive a low voltage differential signal input, demodulate the low voltage differential signal into a single-ended digital signal, and store the single-ended digital signal in a first latch through a shift register; The gamma correction circuit is used to perform gamma correction on multiple node voltage signals on the reference resistor string according to the linear voltage signal output by the voltage selector; The first digital-to-analog converter is used to read a single-ended digital signal from the latch module, and select a node voltage signal from the reference resistor string as an analog voltage signal output according to the single-ended control signal; The first operational amplifier is used to amplify and drive the analog voltage signal to obtain a driving voltage signal for external output.

2. The amorphous silicon thin film transistor flexible display screen source driver chip according to claim 1, characterized in that: The signal receiver is implemented using an LVDS receiver; it includes a preamplifier, a hysteresis comparator, a second latch, a current comparator and an output buffer; the low voltage differential signal input includes a positive low voltage differential signal input and a negative low voltage differential signal input; Wherein, the preamplifier includes a first PMOS tube pair and a first NMOS tube pair; the first PMOS tube pair is used to receive a positive low-voltage differential signal input; the first NMOS tube pair is used to receive a negative low-voltage differential signal input; The hysteresis comparator includes a second NMOS transistor pair and a third NMOS transistor pair; the second NMOS transistor pair is used to set a hysteresis threshold; the third NMOS transistor pair is used to suppress the low-frequency noise of the low-voltage differential signal according to the hysteresis threshold; The second latch includes a fourth NMOS transistor pair; the fourth NMOS transistor pair is used to suppress high-frequency noise of the low voltage differential signal; The current comparator includes a first P-NMOS transistor pair and a second P-NMOS transistor pair; the first P-NMOS transistor pair is used to convert the low voltage differential signal into a single-ended digital signal; the second P-NMOS transistor pair is used as an inverter to control the phase of the single-ended digital signal; The output buffer includes a third P-NMOS transistor pair; the third P-NMOS transistor pair is used as a buffer.

3. The amorphous silicon thin film transistor flexible display screen source driver chip according to claim 1, characterized in that: The gamma correction circuit is implemented using a 4-bit embedded DAC operational amplifier; the 4-bit embedded DAC operational amplifier is designed as a multi-layer structure, and the 4-bit embedded DAC operational amplifiers in each layer respectively correspond to a group of linear voltage signal outputs of a voltage selector, and the node voltage signals at different voltage division positions of the reference resistor string are changed in the 4-bit embedded DAC operational amplifier according to the voltage of the linear voltage signal.

4. The amorphous silicon thin film transistor flexible display screen source driver chip according to claim 3, characterized in that: Each of the 4-bit embedded DAC operational amplifiers includes multiple linear enhancement arrays and a second operational amplifier, each of the linear enhancement arrays includes multiple linear enhancement differential pairs; the linear enhancement differential pairs are used to receive the linear voltage signal output by the voltage selector, and the embedded DAC is used to perform nonlinear transformation on the node voltage signal of the reference resistor string based on the linear voltage signal, so that the node voltage signal of the reference resistor string conforms to the gamma correction curve.

5. The amorphous silicon thin film transistor flexible display screen source driver chip according to claim 4, characterized in that: The 4-bit embedded DAC operational amplifier includes five linear enhancement arrays, and the tail current ratios corresponding to the linear enhancement arrays are 1:1:2:4:

8.

6. The amorphous silicon thin film transistor flexible display screen source driver chip according to claim 1, characterized in that: The first digital-to-analog converter is designed as a 6-bit two-stage cascade structure, including a first-stage structure and a second-stage structure; the first-stage structure is used to perform a tree topology conversion on the upper three bits of input to form a high voltage signal including high and low level signals; The second-level structure is used to select among the lower three bits of input, and perform digital-to-analog conversion within the high and low level range of the high voltage signal according to the selection result to obtain an analog voltage signal output.

7. The amorphous silicon thin film transistor flexible display screen source driver chip according to claim 6, characterized in that: In the first digital-to-analog converter, the first-level structure is implemented using a tree-type digital-to-analog converter; and the second-level structure is implemented using a voltage selector and an embedded digital-to-analog converter.

8. The amorphous silicon thin film transistor flexible display screen source driver chip according to claim 1, characterized in that: The first operational amplifier is a high-voltage rail-to-rail operational amplifier, including a differential pair input stage circuit and a folded common-source common-gate stage circuit; the differential pair input stage circuit is used to receive an analog voltage signal input and a feedback voltage signal input; the folded common-source common-gate stage circuit is used to amplify the analog voltage signal input to obtain a driving voltage signal output.

9. The amorphous silicon thin film transistor flexible display screen source driver chip according to claim 8, characterized in that: The differential pair input stage circuit comprises a fifth NMOS transistor pair and a second PMOS transistor pair; the second PMOS transistor pair is used to receive a low level input of an analog voltage signal; the fifth NMOS transistor pair is used to receive a high level input of an analog voltage signal; The folded cascode stage circuit includes a third PMOS tube pair, a fourth PMOS tube pair, a sixth NMOS tube pair and a seventh NMOS tube pair; the third PMOS tube pair and the sixth NMOS tube pair are used as common gates in the folded cascode structure to output a first voltage signal and a second voltage signal; the fourth PMOS tube pair and the seventh NMOS tube pair are distributed to stabilize the voltage range of the first voltage signal and the second voltage signal; the first operational amplifier also includes an output PMOS tube and an output NMOS tube, which are respectively used to receive the first voltage signal and the second voltage signal, and convert them into a high-level signal and a low-level signal for outputting a driving voltage signal.

10. The amorphous silicon thin film transistor flexible display screen source driver chip according to claim 8, characterized in that: It also includes a feedback circuit; the feedback circuit is connected to the output and the negative input terminal of the first operational amplifier; the feedback circuit is used to proportionally amplify the driving voltage signal.

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