Source driving circuit control method, display panel driving circuit and display device

Abstract

The invention provides a control method of a source electrode driving circuit, a display panel driving circuit and a display device.In the control method of the source electrode driving circuit, a first charge sharing circuit in the source electrode driving circuit is controlled to share charges after driving of a corresponding frame is finished; gray scale voltage signals of the two data lines are compared with polarity reference voltage, when one voltage is larger than the polarity reference voltage, an input selection switch and an output selection switch in the source electrode driving circuit are controlled to be correspondingly switched in a next frame of display picture, a positive polarity gray scale voltage signal is output to the data line, and a negative polarity gray scale voltage signal is output to the data line; when the voltage is smaller than the polarity reference voltage, an input selection switch and an output selection switch in the source electrode driving circuit are controlled to be correspondingly switched in the next frame of display picture, so that a negative polarity gray scale voltage signal is output to the data line, the charging cross voltage is reduced, charging charges are reduced, and driving power consumption is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of display panels, and particularly relates to a control method for a source driver circuit, a display panel driving circuit, and a display device. Background Art

[0002] TFT-LCD (Thin Film Transistor Liquid Crystal Display) is one of the main varieties of current flat panel displays and has become an important display platform in modern IT and video products. Liquid crystals have the property of maintaining torque in an electric field. To avoid the problem of liquid crystal polarization, polarity inversion control is performed during the driving process, and the polarity of the grayscale voltage signal input in the next frame is opposite to that of the grayscale voltage signal in the current frame.

[0003] Furthermore, to reduce the power consumption of the display device, after a frame of the picture is displayed, by short-circuiting two adjacent data lines with different polarities, the charges with different polarities in the data lines cancel each other out, realizing charge sharing. When polarity inversion is performed in the next frame, charging starts from the potential in the middle of the polarity and charges the pixel unit, reducing the charging cross-voltage and lowering the power consumption of the display device.

[0004] Limited by the hardware performance in the past, the refresh rate of display panels was mostly around 30Hz to 60Hz. In the case of a low refresh rate, polarity inversion needs to be performed for each frame. With the development of technology, the current hardware performance can support the display panel to reach a refresh rate of more than 120Hz. In the case of a high refresh rate, performing polarity inversion for each frame affects the refresh efficiency, and because the voltage difference before and after charging during polarity inversion is large, the power consumption increases. Summary of the Invention

[0005] The purpose of the present invention is to provide a control method for a source driver circuit, aiming to solve the problem of high power consumption of the traditional polarity inversion method at high refresh rates.

[0006] The first aspect of the embodiment of the present invention proposes a control method for a source driver circuit. The source driver circuit includes a plurality of driving units, and the plurality of driving units are respectively connected to multiple groups of data lines of the display panel. Each group of data lines includes odd-numbered data lines and even-numbered data lines that are adjacent to each other. The driving unit at least includes a positive polarity digital-to-analog converter, a negative polarity digital-to-analog converter, an input selection switch, an output selection switch, and a first charge sharing circuit; The control method for the source driver circuit includes: After the end of the i-th frame, output a first channel selection signal to control the first charge sharing circuit to perform charge sharing on two data lines of the corresponding group, and compare the voltage signals on the two data lines after charge sharing with the polarity reference voltage respectively; When the grayscale voltage signal corresponding to one data line in each group is greater than the polarity reference voltage, in the (i + 1)-th frame, the first channel selection signal and the second channel selection signal are output successively to control the input selection switch and the output selection switch to switch to the first switch state and the second switch state successively, so as to convert the digital grayscale voltage signal input from the odd input terminal and / or the even input terminal into a positive-polarity grayscale voltage signal through the positive-polarity digital-to-analog converter and transmit it to the corresponding data line; When the grayscale voltage signal corresponding to one data line in each group is less than the polarity reference voltage, in the (i + 1)-th frame, the first channel selection signal and the second channel selection signal are output successively to control the input selection switch and the output selection switch to switch to the third switch state and the fourth switch state successively, so as to convert the digital grayscale voltage signal input from the odd input terminal and / or the even input terminal into a negative-polarity grayscale voltage signal through the negative-polarity digital-to-analog converter and transmit it to the corresponding data line.

[0007] Optionally, the control method of the source driver circuit further includes: In the first frame, a polarity switching control signal is output to control the input selection switch and the output selection switch to switch to the fifth switch state, so as to convert the digital grayscale voltage signals input from the odd input terminal and the even input terminal into a positive-polarity grayscale voltage signal and a negative-polarity grayscale voltage signal respectively through the positive-polarity digital-to-analog converter and the negative-polarity digital-to-analog converter and transmit them to the odd-numbered column data lines and the even-numbered column data lines; Every n1 frames, the polarity switching control signal is output at intervals to control the input selection switch and the output selection switch to switch between the sixth switch state and the fifth switch state, so as to switch the polarities of the grayscale voltage signals of the two data lines in each group at intervals and the polarities of the adjacent two data lines in each group are opposite, where n1 is a positive integer.

[0008] Optionally, the source driver circuit further includes a plurality of second charge sharing circuits, and each second charge sharing circuit is connected between two adjacent odd-numbered column data lines and even-numbered column data lines of two adjacent driving units; The control method of the source driver circuit further includes: After the end of the (i + 1)-th frame, the second channel selection signal is output to control the second charge sharing circuit to perform charge sharing on the two corresponding connected data lines, and compare the voltage signals on the two data lines after charge sharing with the polarity reference voltage respectively; When the grayscale voltage signal of a corresponding data line in the corresponding connection is greater than the polarity reference voltage, in the (i + 2)-th frame, the first channel selection signal and the second channel selection signal are sequentially output to control the input selection switch and the output selection switch to sequentially switch to the first switch state and the second switch state, so as to convert the digital grayscale voltage signal input from the odd input terminal and / or the even input terminal into a positive-polarity grayscale voltage signal through the positive-polarity digital-to-analog converter and transmit it to the corresponding data line; When the grayscale voltage signal of a corresponding data line in each group is less than the polarity reference voltage, in the (i + 2)-th frame, the first channel selection signal and the second channel selection signal are sequentially output to control the input selection switch and the output selection switch to sequentially switch to the third switch state and the fourth switch state, so as to convert the digital grayscale voltage signal input from the odd input terminal and / or the even input terminal into a negative-polarity grayscale voltage signal through the negative-polarity digital-to-analog converter and transmit it to the corresponding data line.

[0009] Optionally, before charge sharing the grayscale voltage signals of the corresponding two data lines after the corresponding frame ends, it further includes: Obtaining the grayscale voltage signals of the next frame of the corresponding two data lines, and comparing the voltage difference between the grayscale voltage signals of the adjacent frames of the two data lines in each group with a preset difference; When the voltage differences of the corresponding two data lines are both less than the preset difference, no charge sharing is performed, and the grayscale voltage signals of the next frame are output to the corresponding two data lines; When the voltage difference of at least one of the corresponding data lines is greater than the preset difference, the grayscale voltage signals of the corresponding two data lines are subjected to charge sharing.

[0010] Optionally, the preset difference is the difference between the grayscale voltage signal of the next frame and the polarity reference voltage.

[0011] A second aspect of the embodiments of the present invention provides a display panel driving circuit, including a timing control circuit and a source driver circuit connected to each other. The source driver circuit includes a plurality of driving units, and the plurality of driving units are connected to multiple groups of data lines of the display panel one by one. Each group of data lines includes an odd-numbered data line and an even-numbered data line adjacent to each other. The driving unit at least includes a positive-polarity digital-to-analog converter, a negative-polarity digital-to-analog converter, an input selection switch, an output selection switch, and a first charge sharing circuit. The first charge sharing circuit is connected between the adjacent odd-numbered data line and even-numbered data line in each group; The source driver circuit further includes a plurality of second charge sharing circuits, and each second charge sharing circuit is connected between the two adjacent odd-numbered data lines and even-numbered data lines of two adjacent driving units; The timing control circuit is used to implement the control method of the source driver circuit as described above.

[0012] Optionally, the source driver circuit further includes: The first charge sharing circuit includes a first switch, a second switch, and a third switch. The first end of the first switch is connected to the first output end of the output selection switch of the driving unit. The first end of the second switch is connected to the second output end of the output selection switch of the driving unit. The second end of the first switch, the first end of the third switch, and the odd-numbered data lines in a corresponding group of data lines are connected. The second end of the second switch, the second end of the third switch, and the even-numbered data lines in a corresponding group of data lines are connected; The second charge sharing circuit includes a fourth switch, and the fourth switch is connected between two adjacent odd-numbered data lines and even-numbered data lines of two adjacent driving units.

[0013] Optionally, the timing control circuit includes a multiplex comparison circuit and a timing controller; Each comparison circuit is respectively connected to two data lines in each group and the source driver circuit. The comparison circuit is configured to compare the voltage signals of the two data lines with the polarity reference voltage respectively, and output a comparison signal to control the source driver circuit to output a grayscale voltage signal with the corresponding polarity to two adjacent data lines in each group; The timing controller is respectively connected to the multiplex comparison circuit and the source driver circuit, and is configured to obtain the comparison signal and control the source driver circuit to implement the control method of the source driver circuit as described above.

[0014] Optionally, the comparison circuit includes a first comparator and a second comparator; The first comparator is connected to one of the data lines in each group, the second comparator is connected to the other data line in each group, the reference voltage terminals of the first comparator and the second comparator also input the polarity reference voltage, and the output terminals of the first comparator and the second comparator are connected to the timing controller.

[0015] A third aspect of the embodiments of the present invention provides a display device, including a display panel and the above display panel driving circuit, and the display panel is connected to the display panel driving circuit.

[0016] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: In the control method of the source driver circuit described above, after the corresponding frame driving is completed, the first charge sharing circuit in the source driver circuit is controlled to perform charge sharing, and the gray scale voltage signals of the two data lines are respectively compared with the polarity reference voltage. When the voltage of one of them is greater than the polarity reference voltage, in the next frame display screen, the input selection switch and the output selection switch in the source driver circuit are controlled to switch correspondingly, and a positive polarity gray scale voltage signal is output to this data line, so as to realize the same-polarity voltage switching from the neutralization voltage to the positive polarity gray scale voltage signal, reduce the magnitude of the charging cross voltage and the charging charge, reduce the driving power consumption, and when the voltage is less than the polarity reference voltage, in the next frame display screen, the input selection switch and the output selection switch in the source driver circuit are controlled to switch correspondingly to output a negative polarity gray scale voltage signal to this data line, so as to realize the same-polarity voltage switching from the neutralization voltage to the negative polarity gray scale voltage signal, reduce the magnitude of the charging cross voltage and the charging charge, and reduce the driving power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 FIG. is a schematic structural diagram of a display panel provided in Embodiment 1 and Embodiment 5 of the present invention; Figure 2 FIG. is a schematic structural diagram of a source driver circuit provided in Embodiment 1 and Embodiment 5 of the present invention; Figure 3 FIG. is a schematic circuit diagram of a digital-to-analog converter provided in Embodiment 1 and Embodiment 5 of the present invention; Figure 4 FIG. is a schematic circuit diagram of a selection switch provided in Embodiment 1 and Embodiment 5 of the present invention; Figure 5 FIG. is a schematic circuit diagram of a first charge sharing circuit provided in Embodiment 1 and Embodiment 5 of the present invention; Figure 6 FIG. is a schematic flow chart of a control method for a source driver circuit provided in Embodiment 1 of the present invention; Figure 7 FIG. is a schematic flow chart of a control method for a source driver circuit provided in Embodiment 2 of the present invention; Figure 8 FIG. is a schematic structural diagram of a source driver circuit provided in Embodiment 3 of the present invention; Figure 9Schematic diagram of the first charge sharing circuit and the second charge sharing circuit provided in Embodiment 3 of the present invention; Figure 10 Timing diagram of the first channel selection signal and the second channel selection signal provided in Embodiment 3 of the present invention; Figure 11 Flow chart of the control method of the source driver circuit provided in Embodiment 3 of the present invention; Figure 12 Flow chart of the control method of the source driver circuit provided in Embodiment 4 of the present invention; Figure 13 First structural diagram of the display panel driver circuit and the display device provided in Embodiments 5 and 6 of the present invention; Figure 14 Second structural diagram of the display panel driver circuit and the display device provided in Embodiment 5 of the present invention; Figure 15 Schematic diagram of the comparison circuit provided in Embodiment 5 of the present invention.

[0019] Among them, each reference numeral in the figure is: 1, display panel; 2, display panel driver circuit; 10, pixel unit; 100, timing control circuit; 200, source driver circuit; 300, gate driver circuit; 110, timing controller; 120, comparison circuit; 210, driving unit; 211, input selection switch; 212, positive polarity digital-to-analog converter; 213, negative polarity digital-to-analog converter; 214, output selection switch; 215, first charge sharing circuit; 220, second charge sharing circuit; U1, first comparator; U2, second comparator; TP1, first channel selection signal; TP2, second channel selection signal; S1, first data line; S2, second data line; K1, first switch; K2, second switch; K3, third switch; K4, fourth switch; K11, first sub-switch; K12, second sub-switch; K13, third sub-switch; K14, fourth sub-switch; OP1, signal amplifier. Detailed implementation manners

[0020] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0021] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined.

[0022] Embodiment 1 A first aspect of an embodiment of the present invention provides a control method for a source driver circuit 200.

[0023] Among them, the source driver circuit 200 is used to output a plurality of grayscale voltage signals to multiple data lines of the display panel 1 and the pixel units 10. As Figure 1 shown, the display panel 1 includes a plurality of data lines, a plurality of scan lines, and a plurality of pixel units 10 arranged in an array. The pixel units 10 are respectively connected to a data line and a scan line. The multiple data lines are sequentially divided into multiple groups. Each group of data lines includes an odd-numbered data line and an even-numbered data line that are adjacent to each other. The display panel 1 is connected to the source driver circuit 200 through the data lines. As Figure 2 and Figure 13 shown, the source driver circuit 200 includes a plurality of driving units 210. The plurality of driving units 210 are respectively connected to multiple groups of data lines of the display panel 1. The driving unit 210 at least includes a positive polarity digital-to-analog converter 212, a negative polarity digital-to-analog converter 213, an input selection switch 211, an output selection switch 214, and a first charge sharing circuit 215.

[0024] Among them, the first input terminal of the input selection switch 211 constitutes the odd-numbered data line input terminal Y2n-1 of the driving unit 210. The second input terminal of the input selection switch 211 constitutes the even-numbered data line input terminal Y2n of the driving unit 210. The first output terminal of the input selection switch 211 is connected to the input terminal of the positive polarity digital-to-analog converter 212. The second output terminal of the input selection switch 211 is connected to the input terminal of the negative polarity digital-to-analog converter 213. The output terminal of the positive polarity digital-to-analog converter 212 is connected to the first input terminal of the output selection switch 214. The output terminal of the negative polarity digital-to-analog converter 213 is connected to the second input terminal of the output selection switch 214. The first output terminal of the output selection switch 214 is connected to the first input terminal of the first charge sharing circuit 215. The second output terminal of the output selection switch 214 is connected to the second input terminal of the first charge sharing circuit 215. The first output terminal of the first charge sharing circuit 215 is connected to the odd-numbered data lines in each group of data lines. The second output terminal of the first charge sharing circuit 215 is connected to the even-numbered data lines in each group of data lines.

[0025] Among them, the positive digital-to-analog converter 212 is used to convert the input digital data signal into a positive grayscale voltage signal through digital-to-analog conversion. The negative digital-to-analog converter 213 is used to convert the input digital data signal into a negative grayscale voltage signal through digital-to-analog conversion. Positive polarity refers to a voltage signal greater than the polarity reference voltage, and negative polarity refers to a grayscale voltage signal less than the polarity reference voltage. For example, the polarity reference voltage is 7.5V. A voltage greater than 7.5V is a positive grayscale voltage signal, and a voltage less than 7.5V is a negative grayscale voltage signal. The interval range of the positive grayscale voltage signal can be 8V to 15V, and the voltage range of the negative grayscale voltage signal can be 0.2V to 6V.

[0026] Among them, the digital-to-analog converter includes multiple gated MOS transistors. The gated MOS transistor is composed of an NMOS transistor that is turned on by a corresponding high level and a PMOS transistor that is turned on by a corresponding low level. As Figure 4 shown, taking a 3-bit digital-to-analog converter as an example, if the digital data signal D2D1D0 input to the digital-to-analog converter is 011, then / D2 / D1 / D0 is 100. According to the 8421 coding principle, the selected switch selects and outputs the V3 voltage value. The V3 voltage value can be amplified by the backend signal amplifier OP1 and output to obtain the V3 grayscale voltage. This grayscale voltage corresponds to the analog-to-digital grayscale voltage signal corresponding to the digital signal 011.

[0027] The input selection switch 211 can correspondingly connect its first input terminal and second input terminal to its first output terminal and second output terminal according to the received control signal. The output selection switch 214 can correspondingly connect its first input terminal and second input terminal to its first output terminal and second output terminal according to the received control signal.

[0028] For example, assume that initially, a positive-polarity grayscale voltage signal needs to be output to the odd-numbered data lines in a corresponding group, and a negative-polarity grayscale voltage signal needs to be output to the even-numbered data lines in the same group. At this time, a first digital data signal is input to the first input terminal of the input selection switch 211, and a second digital data signal is input to the second input terminal of the input selection switch 211. A control signal can be output to control the input selection switch 211 to connect its first input terminal and the first output terminal, and to control the input selection switch 211 to connect its second input terminal and the second output terminal. The first digital data signal is transmitted through the input selection switch 211 to the positive-polarity digital-to-analog converter 212 and is converted into a positive-polarity grayscale voltage signal. The second digital data signal is transmitted through the input selection switch 211 to the negative-polarity digital-to-analog converter 213 and is converted into a negative-polarity grayscale voltage signal. While controlling the input selection switch 211, the output selection switch 214 is controlled to connect its first input terminal and the first output terminal, and to connect its second input terminal and the second output terminal. The positive-polarity grayscale voltage signal is transmitted through the output selection switch 214 and the first charge sharing circuit 215 to the odd-numbered data lines, and the negative-polarity grayscale voltage signal is transmitted through the output selection switch 214 and the first charge sharing circuit 215 to the even-numbered data lines, thus completing the output of the grayscale voltage of the current frame.

[0029] And in the next frame, assume that it is necessary to switch the grayscale voltage polarities of the odd-numbered data lines and the even-numbered data lines. At this time, the first digital data signal corresponding to the next frame is input to the first input terminal of the input selection switch 211, and the second digital data signal corresponding to the next frame is input to the second input terminal of the input selection switch 211. A control signal can be output to control the input selection switch 211 to connect its first input terminal and the second output terminal, and to control the input selection switch 211 to connect its second input terminal and the first output terminal. The first digital data signal is transmitted through the input selection switch 211 to the negative-polarity digital-to-analog converter 213 and is converted into a negative-polarity grayscale voltage signal. The second digital data signal is transmitted through the input selection switch 211 to the positive-polarity digital-to-analog converter 212 and is converted into a positive-polarity grayscale voltage signal. While controlling the input selection switch 211, the output selection switch 214 is controlled to connect its first input terminal and the second output terminal, and to connect its second input terminal and the first output terminal. The positive-polarity grayscale voltage signal is transmitted through the output selection switch 214 and the first charge sharing circuit 215 to the even-numbered data lines, and the negative-polarity grayscale voltage signal is transmitted through the output selection switch 214 and the first charge sharing circuit 215 to the odd-numbered data lines, thus completing the output of the grayscale voltage of the current frame and the polarity switching, which can solve the problem of liquid crystal polarization caused by the same polarity for a long time.

[0030] Among them, the input selection switch 211 and the output selection switch 214 can adopt a multi-input and multi-output terminal switch, for example Figure 4As shown, the input selection switch 211 and the output selection switch 214 can select the first sub-switch K11, the second sub-switch K12, the third sub-switch K13, and the fourth sub-switch K14. The first sub-switch K11 is connected to the first input terminal and the first output terminal of the corresponding selection switch. The second sub-switch K12 is connected to the first input terminal and the second output terminal of the corresponding selection switch. The third sub-switch K13 is connected to the second input terminal and the first output terminal of the corresponding selection switch. The fourth sub-switch K14 is connected to the second input terminal and the second output terminal of the corresponding selection switch. In each frame, by controlling the on / off states of the corresponding sub-switches among the first sub-switch K11, the second sub-switch K12, the third sub-switch K13, and the fourth sub-switch K14, the digital data signal can be selectively output to the positive polarity digital-to-analog converter 212 and the negative polarity digital-to-analog converter 213, and the obtained positive polarity grayscale voltage signal and negative polarity grayscale voltage signal can be correspondingly transmitted to the odd-numbered data lines and even-numbered data lines connected to the driving unit 210, and then transmitted to the pixel units 10 of two adjacent columns in the display panel 1 through the data lines, and the driving display of the pixel units 10 is realized.

[0031] When the grayscale voltage signal is normally output, the first input terminal and the first output terminal in the first charge sharing circuit 215 maintain a connected state, and the second input terminal and the second output terminal of the first charge sharing circuit 215 maintain a connected state. And when the charge sharing is performed at the end of the frame data output, the first input terminal and the first output terminal in the first charge sharing circuit 215 switch to an off state, the second input terminal and the second output terminal in the first charge sharing circuit 215 switch to an off state, and the first output terminal and the second output terminal in the first charge sharing circuit 215 switch to a connected state, that is, the connection is switched between adjacent data lines, and the grayscale voltage signals on the adjacent data lines are charge-shared and neutralized.

[0032] As Figure 5 shown, the first charge sharing circuit 215 includes a first switch K1, a second switch K2, and a third switch K3. When the grayscale voltage signal is normally transmitted, the first switch K1 and the second switch K2 are controlled to conduct, and the third switch K3 is controlled to turn off. The grayscale voltage signal of the corresponding polarity is output to the first data line S1 of the display panel 1 through the first switch K1 of the first charge sharing circuit 215, and the grayscale voltage signal of the corresponding polarity is output to the second data line S2 of the display panel 1 through the second switch K2 of the first charge sharing circuit 215.

[0033] And after the display screen of the current frame ends, the first switch K1 and the second switch K2 are controlled to turn off, and the third switch K3 is controlled to conduct. The charges of different or the same polarities on the first data line S1 and the second data line S2 of this group cancel each other out, realizing charge sharing.

[0034] Among them, in order to reduce the driving power consumption of the display panel 1 and the display device, as Figure 6 shown, the control method of the source driver circuit 200 includes: S10. After the end of the i-th frame, output the first channel selection signal TP1 to control the first charge sharing circuit 215 to perform charge sharing on two data lines of the corresponding group, and compare the voltage signals on the two data lines after charge sharing with the polarity reference voltage respectively.

[0035] In this embodiment, within the same frame, the polarities of the gray-scale voltage signals output to each data line are the same. That is, during the progressive scan of the display panel 1, the polarity of the gray-scale voltage signal on the same data line remains unchanged, and the magnitude of the gray-scale voltage signal on the same data line may change during the progressive scan of the same frame.

[0036] The voltage comparison may occur after the display panel 1 is powered on and after receiving the display control instruction and image information to control the corresponding circuit to output multiple gray-scale voltage signals to the display panel 1, or after the end of a corresponding frame display screen after the display panel 1 starts working. For example, after the end of the first frame, control the first charge sharing circuit 215 to perform charge sharing, and compare the gray-scale voltage signal at the first output terminal and the gray-scale voltage signal at the second output terminal of the first charge sharing circuit 215 with the polarity reference voltage respectively. Or after the end of the 4th frame, control the first charge sharing circuit 215 to perform charge sharing, and compare the gray-scale voltage signal at the first output terminal and the gray-scale voltage signal at the second output terminal of the first charge sharing circuit 215 with the polarity reference voltage respectively. The specific occurrence time is not limited.

[0037] Among them, in the first frame, control the source driver circuit 200 to normally output gray-scale voltage signals with opposite polarities to adjacent two data lines. Taking the first data line S1 and the second data line S2 of the display panel 1 as an example, in the control method, first output a control signal to control the input selection switch 211 and the output selection switch 214 to be correspondingly connected to the input terminal and the output terminal, and convert one digital data signal into a positive-polarity gray-scale voltage signal through the positive-polarity digital-to-analog converter 212, and convert the other digital data signal into a negative-polarity gray-scale voltage signal through the negative-polarity digital-to-analog converter 213. The positive-polarity gray-scale voltage signal and the negative-polarity gray-scale voltage signal are respectively output to the first data line S1 and the second data line S2.

[0038] After the end of the first frame, control the first charge sharing circuit 215 to perform charge sharing. For example, control the first switch K1 and the second switch K2 to turn off, and control the third switch K3 to turn on. The charges with different polarities on the first data line S1 and the second data line S2 of this group cancel each other out to achieve charge sharing.

[0039] For example, after the display screen of the current frame ends, the grayscale voltage signal finally output to the first data line is 10V, and the grayscale voltage signal output to the second data line is 4V. After the grayscale voltage signals on the two data lines perform charge sharing, when complete charge sharing is performed, the voltages on both data lines are 7V. Or, for example, after the display screen of the current frame ends, the grayscale voltage signal finally output to the first data line is 14V, and the grayscale voltage signal output to the second data line is 4V. After the grayscale voltage signals on the two data lines perform charge sharing, when complete charge charging is performed, the voltages on both data lines are 9V.

[0040] Among them, in the control method, the voltage comparison can be selected to be performed after the charge sharing of the first frame ends or after the charge sharing of subsequent frames according to the adjustment strategy.

[0041] Assume that it is selected not to perform voltage comparison in the initial stage of the second frame. Then, after the charge sharing ends, the control method normally outputs a control signal to control the input selection switch 211 and the output selection switch 214 to connect the input end and the output end correspondingly, and converts the digital data signal input in the second frame into a positive-polarity grayscale voltage signal through the positive-polarity digital-to-analog converter 212, and converts the other digital data signal input in the second frame into a negative-polarity grayscale voltage signal through the negative-polarity digital-to-analog converter 213. The positive-polarity grayscale voltage signal and the negative-polarity grayscale voltage signal are respectively output to the second data line S2 and the first data line S1, so as to complete the output of the grayscale voltage of the current frame and the polarity switching, and the problem of liquid crystal polarization caused by the same polarity for a long time can be solved.

[0042] In an alternative embodiment, i = 1, that is, the control method performs voltage comparison after the charge sharing of each frame ends, and selects the polarity switching and output of the grayscale voltage signal according to the comparison result.

[0043] That is, after the grayscale voltage signal of the first frame is output, the first channel selection signal TP1 is first output to the first charge sharing circuit 215 for charge sharing, and the charges of the positive-polarity grayscale voltage signal and the negative-polarity grayscale voltage signal cancel each other out to achieve charge sharing.

[0044] After the charge sharing ends, the voltages on the first data line S1 and the second data line S2 are obtained, and the grayscale voltage signal on the first data line S1 is compared with the polarity reference voltage, and the grayscale voltage signal on the second data line S2 is compared with the memory reference voltage signal. Among them, the voltage magnitudes can be directly obtained by connecting to the first data line S1 and the second data line S2, or the voltages on the first data line S1 and the second data line S2 can be indirectly obtained by selectively connecting the two output ends of the first charge sharing circuit 215.

[0045] The timing for specifically outputting grayscale voltage signals with opposite polarities can be set according to requirements. In an optional embodiment, the timing for outputting grayscale voltage signals with opposite polarities occurs at the initial moment of the first frame display screen in the power-on state.

[0046] S20. When the grayscale voltage signal corresponding to one data line in each group is greater than the polarity reference voltage, in the (i + 1)-th frame, the first channel selection signal TP1 and the second channel selection signal TP2 are successively output to control the input selection switch 211 and the output selection switch 214 to successively switch to the first switch K1 state and the second switch K2 state, so as to convert the digital grayscale voltage signals input from the odd-numbered input terminal and / or the even-numbered input terminal into positive-polarity grayscale voltage signals through the positive-polarity digital-to-analog converter 212 and transmit them to the corresponding data lines.

[0047] When the grayscale voltage signal on the data line is greater than the polarity reference voltage, for example, when the voltages on both data lines are 9V, at this time, it is greater than the polarity reference voltage of 7.5V. In the next frame display screen, the source driver circuit 200 is controlled to output positive-polarity grayscale voltage signals to the two data lines.

[0048] Among them, since there is only one positive-polarity digital-to-analog converter 212 in the source driver circuit 200, and in order to output two positive-polarity grayscale voltage signals, the positive-polarity digital-to-analog converter 212 needs to perform digital-to-analog conversion on the two input digital data signals successively. For this purpose, first, the first channel selection signal TP1 is output to control both the input selection switch 211 and the output selection switch 214 to switch to the first switch K1 state. The first switch K1 state is that the first input terminal and the first output terminal of the input selection switch 211 are connected, and the first input terminal and the first output terminal of the output selection switch 214 are connected, and the first digital data signal input from the odd-numbered column input terminal Y2n - 1 of the driving unit 210 is transmitted to the positive-polarity digital-to-analog converter 212, and is converted into the first positive-polarity grayscale voltage signal and transmitted to the first data line S1 through the output selection switch 214.

[0049] Then, the second channel selection signal TP2 is output to control the input selection switch 211 and the output selection switch 214 to switch to the second switch K2 state. The second switch K2 state is that the second input terminal and the first output terminal of the input selection switch 211 are connected, and the first input terminal and the second output terminal of the output selection switch 214 are connected, and the second digital data signal input from the even-numbered column input terminal Y2n of the driving unit 210 is transmitted to the positive-polarity digital-to-analog converter 212, and is converted into the second positive-polarity grayscale voltage signal and transmitted to the second data line S2 through the output selection switch 214, so as to output positive-polarity grayscale voltage signals with the same polarity to the two data lines. By outputting grayscale voltage signals with the same polarity in the front and back frames, the magnitude of the charging cross voltage can be reduced, thereby reducing the charging charge and charging power consumption.

[0050] For example, assume that after the charge sharing of the current frame ends, the voltages of the two data lines are 9V, and the negative gray-scale voltage signal of the first data line for which the polarity is to be switched in the next frame is 6V, and the positive gray-scale voltage signal of the second data line is 10V. When the polarity is switched, the voltage on the first data line S1 needs to be switched from 9V to 6V across the voltage, and the voltage of the second data line S2 needs to be switched from 9V to 10V across the voltage. The total voltage across the voltage is 4V, and the corresponding 4V of charge and power consumption need to be supplemented.

[0051] When the polarity is not switched, the positive gray-scale voltage signal output to the first data line in the next frame is 9V, and it has the same voltage difference as the original negative voltage of 6V and the polarity reference voltage, and has the same display effect. The voltage on the first data line S1 is maintained at 9V, and the voltage across it is 0. The positive gray-scale voltage signal output to the second data line in the next frame is 10V, and the voltage of the second data line S2 needs to be switched from 9V to 10V across the voltage, and the voltage across it is 1V. The total voltage across the voltage is 1V, and the voltage across it is reduced. The corresponding 1V of charge and power consumption need to be supplemented. Therefore, when it is determined that the voltage after the charge sharing is greater than the polarity reference voltage and the positive gray-scale voltage signal is selected to be output, the total voltage across the previous and next frames is reduced by 3V, and correspondingly, the charging power consumption is reduced.

[0052] S30. When the gray-scale voltage signal of one data line corresponding to each group is less than the polarity reference voltage, in the (i + 1)-th frame, the first channel selection signal TP1 and the second channel selection signal TP2 are sequentially output to control the input selection switch 211 and the output selection switch 214 to be sequentially switched to the states of the third switch K3 and the fourth switch K4, so as to convert the digital gray-scale voltage signal input from the odd input terminal and / or the even input terminal into a negative gray-scale voltage signal through the negative digital-to-analog converter 213 and transmit it to the corresponding data line.

[0053] When the gray-scale voltage signal on the data line is less than the polarity reference voltage, for example, when the voltages of both data lines are 7V, at this time, it is less than the polarity reference voltage of 7.5V. In the next frame display screen, the source driver circuit 200 is controlled to output a negative gray-scale voltage signal to the two data lines.

[0054] Among them, since there is only one negative digital-to-analog converter 213 in the source driver circuit 200, and in order to output two positive grayscale voltage signals, the negative digital-to-analog converter 213 needs to perform digital-to-analog conversion on the two input digital data signals successively. Therefore, first, the first channel selection signal TP1 is output to control the input selection switch 211 and the output selection switch 214 to switch to the state of the third switch K3. The state of the third switch K3 is that the first input terminal and the second output terminal of the input selection switch 211 are connected, the second input terminal and the first output terminal of the output selection switch 214 are connected, and the first digital data signal input from the odd-numbered column input terminal Y2n-1 of the driving unit 210 is transmitted to the negative digital-to-analog converter 213, and is converted into a first negative grayscale voltage signal and transmitted to the first data line S1 through the output selection switch 214.

[0055] Then, the second channel selection signal TP2 is output to control the input selection switch 211 and the output selection switch 214 to switch to the state of the fourth switch K4. The state of the fourth switch K4 is that the second input terminal and the second output terminal of the input selection switch 211 are connected, the second input terminal and the second output terminal of the output selection switch 214 are connected, and the second digital data signal input from the even-numbered column input terminal Y2n of the driving unit 210 is transmitted to the negative digital-to-analog converter 213, and is converted into a second negative grayscale voltage signal and transmitted to the second data line S2 through the output selection switch 214, so as to output negative grayscale voltage signals of the same polarity to the two data lines. By outputting grayscale voltage signals of the same polarity in the front and back frames, the magnitude of the charging cross-voltage can be reduced, thereby reducing the charging charge and charging power consumption.

[0056] For example, assume that the voltages of the two data lines after the charge sharing of the current frame are 7V, and the negative grayscale voltage signal of the first data line for the polarity switching in the next frame is 6V, and the positive grayscale voltage signal of the second data line is 10V. When the polarity is switched, the voltage on the first data line S1 needs to be cross-voltage switched from 7V to 6V, and the voltage of the second data line S2 needs to be cross-voltage switched from 7V to 10V. The total magnitude of the cross-voltage is 4V, and the corresponding 4V of charge and power consumption need to be supplemented.

[0057] When the polarity switching is not performed, the negative gray-scale voltage signal output to the first data line in the next frame is 6V. The voltage on the first data line S1 needs to be switched from 7V to 6V, and the voltage difference is 1V. The negative gray-scale voltage signal output to the second data line in the next frame is 5V, and it has the same voltage difference as the original positive voltage of 10V and the polarity reference voltage, resulting in the same display effect. The voltage on the second data line S2 needs to be switched from 7V to 5V, and the voltage difference is 2V. The total voltage difference is 3V. Since the voltage difference decreases, corresponding charges and power consumption of 3V need to be replenished. Therefore, when it is determined that the voltage after charge sharing is less than the polarity reference voltage and a negative gray-scale voltage signal is selected for output, the total voltage difference between the previous and next frames decreases by 1V, and correspondingly, the charging power consumption decreases.

[0058] Therefore, by comparing the voltage after charge sharing and controlling the polarity switching of the output gray-scale voltage signal, the purpose of reducing the charging power consumption can be achieved.

[0059] Moreover, due to incomplete neutralization during charge sharing, or when subsequent gray-scale voltage signals of the same polarity are output to adjacent data lines, due to leakage current and when the output gray-scale voltage signal is close to the polarity reference voltage, the voltage signal on one of the data lines is greater than the polarity reference voltage, and the voltage signal on the other data line is less than the polarity reference voltage. Then, when the same-polarity gray-scale voltage signal is continuously output to adjacent data lines, the large voltage difference leads to an increase in charging power consumption. In the control method, voltage comparison and polarity judgment output are performed after the charge sharing of each frame, thereby reducing the voltage difference of each frame.

[0060] For example, in the first frame, a positive gray-scale voltage signal is output to the first data line S1, and a negative gray-scale voltage signal is output to the second data line S2. After the display screen of the first frame ends, charge sharing and voltage comparison are performed. When the voltage signal on the first data line S1 and / or the second data line S2 is greater than the polarity reference voltage, a positive voltage signal is output to this data line at the initial moment of the second frame. When the voltage signal on the first data line S1 and / or the second data line S2 is less than the polarity reference voltage, a negative voltage signal is output at the initial moment of the second frame.

[0061] Then, during the line-by-line scanning of the second frame, the polarities of the grayscale voltage signals on the same data line remain unchanged. After the display screen of the second frame ends, charge sharing and voltage comparison are performed again, and grayscale voltage signals of corresponding polarities are output to the first data line S1 and the second data line S2 at the initial moment of the third frame. By analogy, charge sharing and voltage comparison can be performed after the display screen of each frame ends, and the source driver circuit 200 is controlled to output grayscale voltage signals of corresponding polarities to two adjacent data lines, reducing the excessive cross voltage caused by leakage or incomplete charge sharing and lowering the charging power consumption.

[0062] Embodiment 2 After voltage comparison and polarity switching control are performed, the polarities of two adjacent data lines in each group always remain positive or negative. To avoid the liquid crystal polarity, in an optional embodiment, as Figure 7 shown, the control method of the source driver circuit 200 further includes: S40: In the first frame, output a polarity switching control signal to control the input selection switch 211 and the output selection switch 214 to switch to the fifth switch state, so as to convert the digital grayscale voltage signals input from the odd-numbered input terminal and the even-numbered input terminal into a positive-polarity grayscale voltage signal and a negative-polarity grayscale voltage signal respectively through the positive-polarity digital-to-analog converter 212 and the negative-polarity digital-to-analog converter 213 and transmit them to the odd-numbered column data lines and the even-numbered column data lines; S50: Every n1 frames, intermittently output a polarity switching control signal to control the input selection switch 211 and the output selection switch 214 to switch between the sixth switch state and the fifth switch state, so as to intermittently switch the polarities of the grayscale voltage signals of the two data lines in each group and make the polarities of two adjacent data lines in each group opposite, where n1 is a positive integer.

[0063] In this embodiment, in the first frame, assuming that the source driver circuit 200 is controlled to normally output grayscale voltage signals of opposite polarities to two adjacent data lines, taking the first data line S1 and the second data line S2 of the display panel 1 as an example, assume that a positive-polarity grayscale voltage signal is initially output to the first data line S1 and a negative-polarity grayscale voltage signal is output to the second data line S2.

[0064] First, the polarity switching control signal is input to the input selection switch 211 and the output selection switch 214, and the input selection switch 211 and the output selection switch 214 are controlled to switch to the fifth switch state. Among them, the fifth switch state can be that the input selection switch 211 connects its first input terminal and first output terminal and connects its second input terminal and second output terminal, and the output selection switch 214 connects its first input terminal and first output terminal and connects its second input terminal and second output terminal. The first digital data signal input from the odd-numbered column input terminal Y2n - 1 of the driving unit 210 is converted into a positive-polarity grayscale voltage signal by the positive-polarity digital-to-analog converter 212 and transmitted to the first data line S1, and the second digital data signal input from the even-numbered column input terminal Y2n of the driving unit 210 is converted into a negative-polarity grayscale voltage signal by the negative-polarity digital-to-analog converter 213 and transmitted to the second data line S2.

[0065] After the end of the first frame and subsequent frames, charge sharing and voltage comparison are normally performed. In the (n1 + 1)-th frame, another polarity switching control signal is output to switch the polarities of the first data line S1 and the second data line S2. First, the polarity switching control signal is input to the input selection switch 211 and the output selection switch 214, and the input selection switch 211 and the output selection switch 214 are controlled to switch to the sixth switch state. Among them, the sixth switch state can be that the input selection switch 211 connects its first input terminal and second output terminal and connects its second input terminal and first output terminal, and the output selection switch 214 connects its first input terminal and second output terminal and connects its second input terminal and first output terminal. The first digital data signal input from the odd-numbered column input terminal Y2n - 1 of the driving unit 210 is converted into a negative-polarity grayscale voltage signal by the negative-polarity digital-to-analog converter 213 and transmitted to the first data line S1, and the second digital data signal input from the even-numbered column input terminal Y2n of the driving unit 210 is converted into a positive-polarity grayscale voltage signal by the positive-polarity digital-to-analog converter 212 and transmitted to the second data line S2, thereby switching the polarities of each data line and reducing the liquid crystal polarity.

[0066] After the (n1 + 1)-th frame and subsequent frames end, charge sharing and voltage comparison are performed normally. In the (2n1 + 1)-th frame, another polarity switching control signal is output to switch the polarities of the first data line S1 and the second data line S2, and the input selection switch 211 and the output selection switch 214 are controlled to switch to the fifth switch state again. The first digital data signal input to the odd-numbered column input terminal Y2n-1 of the driving unit 210 is converted into a positive-polarity grayscale voltage signal by the positive-polarity digital-to-analog converter 212 and transmitted to the first data line S1, and the second digital data signal input to the even-numbered column input terminal Y2n of the driving unit 210 is converted into a negative-polarity grayscale voltage signal by the negative-polarity digital-to-analog converter 213 and transmitted to the second data line S2, thereby switching the polarities on each data line and reducing the liquid crystal polarity.

[0067] And so on, so that the polarity of each data line can be switched every n1 frames, avoiding liquid crystal polarization caused by the same polarity.

[0068] Among them, the value of n1 can be set according to requirements. In an optional embodiment, in order to avoid invalidation of voltage comparison and subsequent polarity judgment caused by excessive switching, and considering high refresh rate, there is no need to perform polarity switching frequently. In an optional embodiment, n1 = 30, that is, the polarities of the grayscale voltage signals on each data line are switched every 30 frames.

[0069] Embodiment Three After voltage comparison and polarity switching control are performed, the polarities of two adjacent data lines in each group always remain positive or negative. In order to avoid liquid crystal polarity, in an optional embodiment, as Figure 8 shown, the source driver circuit 200 further includes a plurality of second charge sharing circuits 220. Each second charge sharing circuit 220 is connected between two adjacent odd-numbered column data lines and even-numbered column data lines of two adjacent driving units 210, and the second charge sharing circuit 220 can perform charge sharing on the adjacent data lines of two adjacent driving units 210.

[0070] Among them, as Figure 9 shown, the second charge sharing circuit 220 may include a fourth switch K4, and the fourth switch K4 is connected between two adjacent odd-numbered column data lines and even-numbered column data lines of two adjacent driving units 210.

[0071] As Figure 11 shown, the control method of the source driver circuit 200 further includes: S60. After the (i + 1)-th frame ends, output a second channel selection signal TP2 to control the second charge sharing circuit 220 to perform charge sharing on the corresponding two data lines, and compare the voltage signals on the two data lines after charge sharing with the polarity reference voltage respectively; S70. When the grayscale voltage signal of a corresponding data line in the corresponding connection is greater than the polarity reference voltage, in the (i + 2)-th frame, the first channel selection signal TP1 and the second channel selection signal TP2 are output successively to control the input selection switch 211 and the output selection switch 214 to switch to the first switch K1 state and the second switch K2 state successively, so as to convert the digital grayscale voltage signal input from the odd input terminal and / or the even input terminal into a positive-polarity grayscale voltage signal through the positive-polarity digital-to-analog converter 212 and transmit it to the corresponding data line; S80. When the grayscale voltage signal of a corresponding data line in each group is less than the polarity reference voltage, in the (i + 2)-th frame, the first channel selection signal TP1 and the second channel selection signal TP2 are output successively to control the input selection switch 211 and the output selection switch 214 to switch to the third switch K3 state and the fourth switch K4 state successively, so as to convert the digital grayscale voltage signal input from the odd input terminal and / or the even input terminal into a negative-polarity grayscale voltage signal through the negative-polarity digital-to-analog converter 213 and transmit it to the corresponding data line.

[0072] In this embodiment, referring to Figure 10 as shown, the first charge sharing circuit 215 triggers charge sharing based on the first channel selection signal TP1 output first, and the second charge sharing circuit 220 triggers charge sharing based on the second channel selection signal TP2 output first.

[0073] After the end of the i-th frame, according to S10, the first channel selection signal TP1 is output to the first charge sharing circuit 215 first. The first charge sharing circuit 215 performs charge sharing on two adjacent data lines in the same group. When the neutralization voltage is greater than the polarity reference voltage, in S20, the first channel selection signal TP1 and the second channel selection signal TP2 are output successively, and the first digital data signal and the second digital data signal input by the driving unit 210 are successively converted into positive-polarity grayscale voltage signals through the positive-polarity digital-to-analog converter 212 to two data lines in the same group. And when the neutralization voltage is greater than the polarity reference voltage, in S30, the first channel selection signal TP1 and the second channel selection signal TP2 are output successively, and the first digital data signal and the second digital data signal input by the driving unit 210 are successively converted into negative-polarity grayscale voltage signals through the negative-polarity digital-to-analog converter 213 to two data lines in the same group.

[0074] As Figure 9 shown, when S10, S20, and S30 are adopted, multiple data lines may be in a polarity state of positive, positive, negative, negative, positive, positive, negative, negative for multiple frames, resulting in the problem of liquid crystal polarization.

[0075] To this end, in this embodiment, it is assumed that i = 1. At the second frame, the second channel selection signal TP2 is selected and output to the second charge sharing circuit 220. The second charge sharing circuit 220 performs charge sharing on the adjacent data lines of two adjacent driving units 210, so that charge sharing can be performed on the gray-scale voltage signals of the positive and negative polarities of the adjacent two data lines in the adjacent driving units 210. For example, for Figure 9 the second data line S2 with positive polarity and the third data line with negative polarity in

[0076] charge sharing is performed. After the charge sharing of the gray-scale voltage signals of the positive and negative polarities of the adjacent two data lines, the neutralization voltage can be greater than or less than the polarity reference voltage.

[0077] Assume it is greater than the polarity reference voltage. Then, in the third frame, S70 can be the same as S20, and the first channel selection signal TP1 and the second channel selection signal TP2 are output successively to control the input selection switch 211 and the output selection switch 214 of the first driving unit 210 to switch to the first switch K1 state and the second switch K2 state. The first driving unit 210 is connected to the first data line S1 and the second data line S2, so as to output a positive-polarity gray-scale voltage signal to the second data line S2. And the first channel selection signal TP1 and the second channel selection signal TP2 are output successively to control the input selection switch 211 and the output selection switch 214 of the second driving unit 210 to switch to the first switch K1 state and the second switch K2 state. The second driving unit 210 is connected to the third data line and the fourth data line, so as to output a positive-polarity gray-scale voltage signal to the third data line, and so on. In the third frame, the polarities of each data line can be switched to negative, positive, negative, positive, negative, positive, negative, and half of the data lines among the multiple data lines can have their polarities switched. Figure 9 Assume it is less than the polarity reference voltage. Then, in the third frame, S80 can be the same as S30, and the first channel selection signal TP1 and the second channel selection signal TP2 are output successively to control the input selection switch 211 and the output selection switch 214 of the first driving unit 210 to switch to the third switch K3 state and the fourth switch K4 state, so as to output a negative-polarity gray-scale voltage signal to the second data line S2. And the first channel selection signal TP1 and the second channel selection signal TP2 are output successively to control the input selection switch 211 and the output selection switch 214 of the second driving unit 210 to switch to the first switch K1 state and the second switch K2 state, so as to output a negative-polarity gray-scale voltage signal to the third data line, and so on. In the third frame, as

[0078] Among them, the first channel selection signal TP1 and the second channel selection signal TP2 are alternately output in frame periods. That is, after the charge sharing in the first frame ends, the first channel selection signal TP1 is output to control the first charge sharing circuit 215 to perform charge sharing. After the charge sharing in the second frame ends, the second channel selection signal TP2 is output to control the second charge sharing circuit 220 to perform charge sharing. After the charge sharing in the third frame ends, the first channel selection signal TP1 is output to control the first charge sharing circuit 215 to perform charge sharing. After the charge sharing in the fourth frame ends, the second channel selection signal TP2 is output to control the second charge sharing circuit 220 to perform charge sharing, thereby correspondingly switching the polarities on different data lines, reducing the problem of liquid crystal polarization. At the same time, according to the comparison result, the grayscale voltage signal of the corresponding polarity is selected and output to the corresponding data line, which can reduce the charging cross-voltage between adjacent frames and reduce the charging drive power consumption.

[0079] Embodiment 4 When charge sharing is adopted, additional heat energy will be generated during the neutralization process of the positive and negative voltage polarities, affecting the temperature of the driving circuit. In order to avoid overheating, in an optional embodiment, after the corresponding frame ends and before the grayscale voltage signals of the corresponding two data lines are subjected to charge sharing, it further includes: S90. Obtain the grayscale voltage signals of the next frame of the corresponding two data lines, and compare the voltage difference between the grayscale voltage signals of the adjacent frames of the two data lines in each group with a preset difference; S100. When the voltage differences of the corresponding two data lines are both less than the preset difference, no charge sharing is performed, and the grayscale voltage signals of the next frame are output to the corresponding two data lines; S110. When the voltage difference of at least one of the corresponding data lines is greater than the preset difference, perform charge sharing on the grayscale voltage signals of the corresponding two data lines.

[0080] In this embodiment, the voltage difference between the grayscale voltage signals of the adjacent two frames of each group of adjacent two data lines is calculated and compared with the preset voltage difference. When the voltage difference change is small, no charge sharing is performed, and the grayscale voltage signal of the corresponding polarity is directly output in the next frame. When the voltage difference change is large, charge sharing is selected.

[0081] For example, assume that the voltage of a current frame of one of the data lines is 10V and the voltage of the next frame is 7V. Assume that the preset difference is 1V. At this time, the difference between the adjacent two frames is 3V, which is greater than the preset difference. At this time, charge sharing is selected, and after charge sharing, voltage comparison and output polarity control of the grayscale voltage signal of the data line are performed. The cross-voltage of the grayscale voltage signals of the two frames before and after charge sharing is smaller, reducing the charging power consumption.

[0082] Alternatively, assume that the voltage of the current frame of one of the data lines is 7.6V and the voltage of the next frame is 7V. Assume that the preset difference is 1V. At this time, the difference between two adjacent frames is 0.6V, which is less than the preset difference. At this time, charge sharing can be selected not to be performed, and a grayscale voltage signal with the opposite polarity can be directly output to this data line in the next frame. The cross-voltage of the grayscale voltage signals of the two consecutive frames is smaller, reducing the charging power consumption.

[0083] Among them, the preset difference can be judged according to requirements or set according to the magnitude of the grayscale voltage signal of the current frame. In an alternative embodiment, the preset difference is the difference between the grayscale voltage signal of the next frame and the polarity reference voltage.

[0084] For example, assume that the voltage of the current frame of one of the data lines is 10V and the voltage of the next frame is 7V. Assume that the polarity reference voltage is 7.5V and the preset difference is 0.5V. The difference between two adjacent frames is 3V, which is greater than the preset difference. At this time, charge sharing is selected to be performed, and after charge sharing, voltage comparison and output polarity control of the grayscale voltage signal of the data line are performed. The cross-voltage of the grayscale voltage signals of the two consecutive frames after charge sharing is smaller, reducing the charging power consumption.

[0085] Alternatively, assume that the voltage of the current frame of one of the data lines is 10V and the voltage of the next frame is 13V. The preset difference is 5.5V. At this time, the difference between two adjacent frames is 3V, which is less than the preset difference. At this time, charge sharing can be selected not to be performed, and a grayscale voltage signal with the opposite polarity can be directly output to this data line in the next frame. The cross-voltage of the grayscale voltage signals of the two consecutive frames is smaller, reducing the charging power consumption.

[0086] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution. The order of execution of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0087] Embodiment Five The second aspect of the embodiments of the present invention provides a display panel driving circuit 2, such as Figure 1 、 Figure 2 and Figure 13As shown, the display panel 1 includes a plurality of data lines, a plurality of scan lines, and a plurality of pixel units 10 arranged in an array. The pixel units 10 are correspondingly connected to a data line and a scan line. The multiple columns of data lines are sequentially divided into multiple groups. Each group of data lines includes adjacent odd-numbered column data lines and even-numbered column data lines. The display panel 1 is connected to the source driver circuit 200 through the data lines. The source driver circuit 200 includes a plurality of driving units 210. The plurality of driving units 210 are connected to the multiple groups of data lines of the display panel 1 one by one. The driving unit 210 at least includes a positive polarity digital-to-analog converter 212, a negative polarity digital-to-analog converter 213, an input selection switch 211, an output selection switch 214, and a first charge sharing circuit 215.

[0088] Among them, the first input terminal of the input selection switch 211 constitutes the odd-numbered column input terminal Y2n-1 of the driving unit 210, the second input terminal of the input selection switch 211 constitutes the even-numbered column input terminal Y2n of the driving unit 210. The first output terminal of the input selection switch 211 is connected to the input terminal of the positive polarity digital-to-analog converter 212, the second output terminal of the input selection switch 211 is connected to the input terminal of the negative polarity digital-to-analog converter 213. The output terminal of the positive polarity digital-to-analog converter 212 is connected to the first input terminal of the output selection switch 214, the output terminal of the negative polarity digital-to-analog converter 213 is connected to the second input terminal of the output selection switch 214. The first output terminal of the output selection switch 214 is connected to the first input terminal of the first charge sharing circuit 215, the second output terminal of the output selection switch 214 is connected to the second input terminal of the first charge sharing circuit 215. The first output terminal of the first charge sharing circuit 215 is connected to the odd-numbered column data lines in each group of data lines, and the second output terminal of the first charge sharing circuit 215 is connected to the even-numbered column data lines in each group of data lines.

[0089] The source driver circuit 200 further includes a plurality of second charge sharing circuits 220. Each second charge sharing circuit 220 is connected between two adjacent odd-numbered column data lines and even-numbered column data lines of two adjacent driving units 210. Among them, as Figure 9 shown, the second charge sharing circuit 220 may include a fourth switch K4. The fourth switch K4 is connected between two adjacent odd-numbered column data lines and even-numbered column data lines of two adjacent driving units 210.

[0090] The timing control circuit 100 is used to implement the control method of the above-mentioned source driver circuit 200.

[0091] In this embodiment, the display panel driving circuit 2 further includes a gate driver circuit 300. The gate driver circuit 300 is used to output a row scan signal line by line in each frame to turn on each row of pixel units 10 line by line, and display corresponding image information in combination with the input grayscale voltage signal.

[0092] Among them, the positive digital-to-analog converter 212 is used to convert the input digital data signal into a positive grayscale voltage signal through digital-to-analog conversion. The negative digital-to-analog converter 213 is used to convert the input digital data signal into a negative grayscale voltage signal through digital-to-analog conversion. Positive polarity refers to a voltage signal greater than the polarity reference voltage, and negative polarity refers to a grayscale voltage signal less than the polarity reference voltage. For example, the polarity reference voltage is 7.5V. A voltage greater than 7.5V is a positive grayscale voltage signal, and a voltage less than 7.5V is a negative grayscale voltage signal. The interval range of the positive grayscale voltage signal can be 8V to 15V, and the voltage range of the negative grayscale voltage signal can be 0.2V to 6V.

[0093] Among them, the digital-to-analog converter includes multiple gated MOS transistors. The gated MOS transistor is composed of an NMOS transistor that is turned on by a corresponding high level and a PMOS transistor that is turned on by a corresponding low level. As Figure 4 shown, taking a 3-bit digital-to-analog converter as an example, if the digital data signal D2D1D0 input to the digital-to-analog converter is 011, then / D2 / D1 / D0 is 100. According to the 8421 coding principle, the selected switch selects and outputs the V3 voltage value. The V3 voltage value can be amplified by a backend signal amplifier to obtain the V3 grayscale voltage. This grayscale voltage corresponds to the analog-to-digital grayscale voltage signal corresponding to the digital signal 011.

[0094] The input selection switch 211 can correspondingly connect its first input terminal and second input terminal to its first output terminal and second output terminal according to the received control signal. The output selection switch 214 can correspondingly connect its first input terminal and second input terminal to its first output terminal and second output terminal according to the received control signal.

[0095] For example, assume that initially, a positive grayscale voltage signal needs to be output to the odd-numbered data lines in a corresponding group, and a negative grayscale voltage signal needs to be output to the even-numbered data lines in the same group. At this time, a first digital data signal is input to the first input terminal of the input selection switch 211, a second digital data signal is input to the second input terminal of the input selection switch 211, and a control signal can be output to control the input selection switch 211 to connect its first input terminal and the first output terminal, and control the input selection switch 211 to connect its second input terminal and the second output terminal. The first digital data signal is transmitted to the positive digital-to-analog converter 212 through the input selection switch 211 and converted into a positive grayscale voltage signal. The second digital data signal is transmitted to the negative digital-to-analog converter 213 through the input selection switch 211 and converted into a negative grayscale voltage signal. While controlling the input selection switch 211, the output selection switch 214 is controlled to connect its first input terminal and the first output terminal, and connect its second input terminal and the second output terminal. The positive grayscale voltage signal is transmitted to the odd-numbered data lines through the output selection switch 214 and the first charge sharing circuit 215. The negative grayscale voltage signal is transmitted to the even-numbered data lines through the output selection switch 214 and the first charge sharing circuit 215, thereby completing the output of the grayscale voltage of the current frame.

[0096] And in the next frame, assume that it is necessary to switch the grayscale voltage polarities of the odd-numbered data lines and the even-numbered data lines. At this time, the first digital data signal corresponding to the next frame is input to the first input terminal of the input selection switch 211, and the second digital data signal corresponding to the next frame is input to the second input terminal of the input selection switch 211. A control signal can be output to control the input selection switch 211 to connect its first input terminal and the second output terminal, and control the input selection switch 211 to connect its second input terminal and the first output terminal. The first digital data signal is transmitted to the negative digital-to-analog converter 213 through the input selection switch 211 and converted into a negative grayscale voltage signal. The second digital data signal is transmitted to the positive digital-to-analog converter 212 through the input selection switch 211 and converted into a positive grayscale voltage signal. While controlling the input selection switch 211, the output selection switch 214 is controlled to connect its first input terminal and the second output terminal, and connect its second input terminal and the first output terminal. The positive grayscale voltage signal is transmitted to the even-numbered data lines through the output selection switch 214 and the first charge sharing circuit 215. The negative grayscale voltage signal is transmitted to the odd-numbered data lines through the output selection switch 214 and the first charge sharing circuit 215, thereby completing the output of the grayscale voltage of the current frame and the polarity switching, which can solve the problem of liquid crystal polarization caused by the same polarity for a long time.

[0097] Among them, the input selection switch 211 and the output selection switch 214 can adopt a multi-input and output terminal switch, for example Figure 4As shown, the input selection switch 211 and the output selection switch 214 can select the first sub-switch K11, the second sub-switch K12, the third sub-switch K13, and the fourth sub-switch K14. The first sub-switch K11 is connected to the first input terminal and the first output terminal of the corresponding selection switch. The second sub-switch K12 is connected to the first input terminal and the second output terminal of the corresponding selection switch. The third sub-switch K13 is connected to the second input terminal and the first output terminal of the corresponding selection switch. The fourth sub-switch K14 is connected to the second input terminal and the second output terminal of the corresponding selection switch. In each frame, by controlling the on / off states of the corresponding sub-switches among the first sub-switch K11, the second sub-switch K12, the third sub-switch K13, and the fourth sub-switch K14, the digital data signal can be selectively output to the positive polarity digital-to-analog converter 212 and the negative polarity digital-to-analog converter 213, and the obtained positive polarity grayscale voltage signal and negative polarity grayscale voltage signal can be correspondingly transmitted to the odd-numbered data lines and even-numbered data lines connected to the driving unit 210, and then transmitted to the pixel units 10 of two adjacent columns in the display panel 1 through the data lines, and the driving display of the pixel units 10 is realized.

[0098] When the grayscale voltage signal is normally output, the first input terminal and the first output terminal in the first charge sharing circuit 215 maintain a connected state, and the second input terminal and the second output terminal of the first charge sharing circuit 215 maintain a connected state. And when the charge sharing is performed at the end of the frame data output, the first input terminal and the first output terminal in the first charge sharing circuit 215 switch to an off state, the second input terminal and the second output terminal in the first charge sharing circuit 215 switch to an off state, and the first output terminal and the second output terminal in the first charge sharing circuit 215 switch to a connected state, that is, the adjacent data lines switch to a connected state, and the grayscale voltage signals on the adjacent data lines are charge shared and neutralized.

[0099] As Figure 5 shown, the first charge sharing circuit 215 includes a first switch K1, a second switch K2, and a third switch K3. When the grayscale voltage signal is normally transmitted, the first switch K1 and the second switch K2 are controlled to conduct, and the third switch K3 is controlled to turn off. The grayscale voltage signal of the corresponding polarity is output to the first data line S1 of the display panel 1 through the first switch K1 of the first charge sharing circuit 215, and the grayscale voltage signal of the corresponding polarity is output to the second data line S2 of the display panel 1 through the second switch K2 of the first charge sharing circuit 215.

[0100] And after the display screen of the current frame ends, the first switch K1 and the second switch K2 are controlled to turn off, and the third switch K3 is controlled to conduct, and the charges of different or the same polarities on the first data line S1 and the second data line S2 of this group cancel each other out, realizing charge sharing.

[0101] The timing control circuit 100 first controls the source driver circuit 200 to output grayscale voltage signals with opposite polarities, and transmits the grayscale voltage signals with opposite polarities to two adjacent data lines in each group of the display panel 1.

[0102] After the display screen of the current frame ends, it outputs a first channel selection signal TP1 to control the source driver circuit 200 to perform charge sharing. After the charge sharing ends, it obtains the grayscale voltage signals of two adjacent data lines in each group, compares them with the polarity reference voltage, and outputs grayscale voltage signals with corresponding polarities to two adjacent data lines in each group in the next frame according to the comparison results.

[0103] Then, the timing control circuit 100 can also switch the polarities on two adjacent data lines in each group every n1 frames to avoid liquid crystal polarization.

[0104] The timing control circuit 100 can also obtain the grayscale voltage signals of the next frame before charge sharing, calculate the voltage difference between the grayscale voltage signals of two adjacent frames of two adjacent data lines in each group, and compare it with a preset voltage difference. When the voltage difference change is small, no charge sharing is performed, and grayscale voltage signals with corresponding polarities are directly output in the next frame. When the voltage difference change is large, charge sharing is selected.

[0105] The timing control circuit 100 can also switch the output of the first channel selection signal TP1 and the second channel selection signal TP2 in adjacent frames to control the first charge sharing circuit 215 and the second charge sharing circuit 220 to perform charge sharing on different adjacent data lines in two adjacent frames respectively, so as to further reduce liquid crystal polarization and reduce power consumption.

[0106] The timing control circuit 100 can adopt a timing controller 110, or can also adopt a corresponding comparator, etc. In an alternative embodiment, as Figure 14 shown, the timing control circuit 100 includes a multiplex comparator circuit 120 and a timing controller 110; Each comparator circuit 120 is respectively connected to two data lines in each group and the source driver circuit 200. The comparator circuit 120 is used to compare the voltage signals of the two data lines with the polarity reference voltage respectively, and output a comparison signal to control the source driver circuit 200 to output grayscale voltage signals with corresponding polarities to two adjacent data lines in each group; The timing controller 110 is respectively connected to the multiplex comparator circuit 120 and the source driver circuit 200, and is used to obtain the comparison signal and control the source driver circuit 200 to implement the control method of the above-mentioned source driver circuit 200.

[0107] In this embodiment, each comparison circuit 120 is connected to two adjacent data lines in each group, and the timing controller 110 can control the operating timing of the comparison circuit 120.

[0108] The timing controller 110 first controls the source driver circuit 200 to output grayscale voltage signals with opposite polarities, and controls the first switch K1 and the second switch K2 in the first charge sharing circuit 215 to conduct, so as to transfer the grayscale voltage signals with opposite polarities to two adjacent data lines in each group of the display panel 1.

[0109] After the display of the current frame is completed, it controls the third switch K3 in the first charge sharing circuit 215 to conduct for charge sharing. After the charge sharing is completed, it controls the comparison circuit 120 to start. The comparison circuit 120 obtains the voltage signals of two adjacent data lines in each group, compares them with the polarity reference voltage, and outputs a comparison signal to the positive polarity output unit 21 and the negative polarity output unit 22 in the source driver circuit 200, so as to output grayscale voltage signals with corresponding polarities to two adjacent data lines in each group in the next frame.

[0110] Then the timing controller 110 can receive the comparison signal to determine the output states of the current positive polarity output unit 21 and the negative polarity output unit 22. The timing controller 110 can also output a polarity switching control signal to the positive polarity output unit 21 and the negative polarity output unit 22 in the source driver circuit 200 every n2 frames to switch the polarities of two adjacent data lines in each group to avoid liquid crystal polarization.

[0111] The timing controller 110 can also obtain the voltage signal of the next frame before charge sharing, calculate the voltage difference between the grayscale voltage signals of two adjacent frames of two adjacent data lines in each group, and compare it with the preset voltage difference. When the voltage difference change is small, charge sharing is not performed, and the source driver circuit 200 is directly controlled to output grayscale voltage signals with corresponding polarities in the next frame. When the voltage difference change is large, the first charge sharing circuit 215 is controlled to perform charge sharing.

[0112] Such as Figure 15As shown, each comparison circuit 120 may include a first comparator U1 connected to one data line of each group, a second comparator U2 connected to the other data line of each group. The reference voltage terminals of the first comparator U1 and the second comparator U2 are also input with a polarity reference voltage. The output terminals of the first comparator U1 and the second comparator U2 are connected to the timing controller 110. The first comparator U1 and the second comparator U2 respectively compare the voltages of the two data lines of each group and respectively output comparison signals to the timing controller 110. The timing controller 110 selects and outputs a first channel selection signal TP1 and a second channel selection signal TP2 according to the received comparison signals, and controls the input selection switch 211 and the output selection switch 214 to switch to different switch states correspondingly, so as to control the source driver circuit 200 to output grayscale voltage signals of corresponding polarities to each data line.

[0113] Embodiment Six The present invention also provides a display device, as Figure 14 shown, the display device includes a display panel 1 and a display panel driving circuit 2. The specific structure of the display panel driving circuit 2 refers to the above embodiments. Since this display device adopts all the technical solutions of the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, and will not be elaborated herein one by one. The display panel 1 is connected to the display panel driving circuit 2.

[0114] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A control method for a source drive circuit, characterized in that: The source driving circuit includes a plurality of driving units, the plurality of driving units are connected one by one with a plurality of groups of data lines of the display panel, each group of data lines includes two adjacent odd-numbered column data lines and even-numbered column data lines, and the driving unit includes at least a positive polarity digital-to-analog converter, a negative polarity digital-to-analog converter, an input selection switch, an output selection switch and a first charge sharing circuit; The control method of the source driving circuit comprises: After the i-th frame ends, outputting a first channel selection signal to control the first charge sharing circuit to perform charge sharing on two data lines of the corresponding group, and comparing the voltage signals on the two data lines after charge sharing with the polarity reference voltage respectively; When the grayscale voltage signal of a data line corresponding to each group is greater than the polarity reference voltage, in the (i+1)th frame, the first channel selection signal and the second channel selection signal are output successively to control the input selection switch and the output selection switch to switch to the first switch state and the second switch state successively, so as to convert the digital grayscale voltage signal input from the odd input terminal and / or the even input terminal into a positive polarity grayscale voltage signal through the positive polarity digital-to-analog converter and transmit it to the corresponding data line; When the grayscale voltage signal of a data line corresponding to each group is less than the polarity reference voltage, in the (i+1)th frame, the first channel selection signal and the second channel selection signal are output successively to control the input selection switch and the output selection switch to switch to the third switch state and the fourth switch state successively, so as to convert the digital grayscale voltage signal inputted at the odd input terminal and / or the even input terminal into a negative polarity grayscale voltage signal through a negative polarity digital-to-analog converter and transmit it to the corresponding data line.

2. The control method of the source driving circuit according to claim 1, characterized in that: The control method of the source driving circuit further includes: In the first frame, the output polarity switching control signal controls the input selection switch and the output selection switch to switch to the fifth switch state, so as to convert the digital grayscale voltage signals input from the odd input terminal and the even input terminal into positive polarity grayscale voltage signals and negative polarity grayscale voltage signals through the positive polarity digital-to-analog converter and the negative polarity digital-to-analog converter respectively, and transmit them to the odd column data lines and the even column data lines; Every n1 frames, the interval output polarity switching control signal controls the input selection switch and the output selection switch to switch between the sixth switch state and the fifth switch state, so as to switch the polarity of the grayscale voltage signals of the two data lines of each group and the polarities of the two adjacent data lines of each group are opposite, wherein n1 is a positive integer.

3. The control method of the source driving circuit according to claim 1, characterized in that: The source driving circuit further includes a plurality of second charge sharing circuits, each of which is connected between two adjacent odd-numbered column data lines and even-numbered column data lines of two adjacent driving units; The control method of the source driving circuit also includes: After the (i+1)th frame ends, a second channel selection signal is output to control the second charge sharing circuit to share charges between two correspondingly connected data lines, and the voltage signals on the two data lines after charge sharing are compared with the polarity reference voltage respectively; When the grayscale voltage signal of a corresponding data line connected to the corresponding connection is greater than the polarity reference voltage, in the (i+2)th frame, the first channel selection signal and the second channel selection signal are output successively to control the input selection switch and the output selection switch to switch to the first switch state and the second switch state successively, so as to convert the digital grayscale voltage signal input from the odd input terminal and / or the even input terminal into a positive polarity grayscale voltage signal through the positive polarity digital-to-analog converter and transmit it to the corresponding data line; When the grayscale voltage signal of a data line corresponding to each group is less than the polarity reference voltage, in the (i+2)th frame, the first channel selection signal and the second channel selection signal are output successively to control the input selection switch and the output selection switch to switch to the third switch state and the fourth switch state successively, so as to convert the digital grayscale voltage signal inputted at the odd input terminal and / or the even input terminal into a negative polarity grayscale voltage signal through a negative polarity digital-to-analog converter and transmit it to the corresponding data line.

4. The control method of the source driving circuit according to any one of claims 1 to 3, characterized in that: After the corresponding frame ends, before the grayscale voltage signals of the corresponding two data lines are charged and shared, the method further includes: Acquire the grayscale voltage signal of the next frame corresponding to the two data lines, and compare the voltage difference of the grayscale voltage signals of the adjacent frames of the two data lines of each group with the preset difference; When the voltage difference between the two corresponding data lines is less than the preset difference, no charge sharing is performed, and the grayscale voltage signal of the next frame is output to the two corresponding data lines; When the voltage difference corresponding to at least one data line is greater than a preset difference, the grayscale voltage signals corresponding to the two data lines are charge-shared.

5. The control method of the source driving circuit according to claim 4, characterized in that: The preset difference is the difference between the grayscale voltage signal of the next frame and the polarity reference voltage.

6. A display panel driving circuit, characterized in that: The device comprises a timing control circuit and a source driving circuit connected to each other, wherein the source driving circuit comprises a plurality of driving units, wherein the plurality of driving units are connected one by one to a plurality of groups of data lines of the display panel, wherein each group of data lines comprises two adjacent odd-numbered data lines and two adjacent even-numbered data lines, and wherein the driving unit comprises at least a positive polarity digital-to-analog converter, a negative polarity digital-to-analog converter, an input selection switch, an output selection switch, and a first charge sharing circuit, wherein the first charge sharing circuit is connected between two adjacent odd-numbered data lines and two adjacent even-numbered data lines in each group; The source driving circuit further includes a plurality of second charge sharing circuits, each of which is connected between two adjacent odd-numbered column data lines and even-numbered column data lines of two adjacent driving units; A timing control circuit, used to implement the control method of the source drive circuit as claimed in any one of claims 1 to 5.

7. The display panel driving circuit according to claim 6, wherein: The first charge sharing circuit includes a first switch, a second switch and a third switch, wherein a first end of the first switch is connected to a first output end of an output selection switch of a driving unit, a first end of the second switch is connected to a second output end of an output selection switch of a driving unit, a second end of the first switch and a first end of the third switch are connected to an odd-numbered column of a corresponding group of data lines, and a second end of the second switch and a second end of the third switch are connected to an even-numbered column of a corresponding group of data lines; The second charge sharing circuit includes a fourth switch connected between two adjacent odd-numbered column data lines and an even-numbered column data line of two adjacent driving units.

8. The display panel driving circuit according to claim 6 or 7, characterized in that: The timing control circuit includes a multi-channel comparison circuit and a timing controller; Each comparison circuit is connected to two data lines and a source driving circuit of each group, and the comparison circuit is used to compare the voltage signals of the two data lines with the polarity reference voltages, and output a comparison signal to control the source driving circuit to output a grayscale voltage signal of a corresponding polarity to two adjacent data lines of each group; The timing controller is connected to the multi-channel comparison circuit and the source driving circuit respectively, and is used to obtain the comparison signal and control the source driving circuit to implement the control method of the source driving circuit as claimed in any one of claims 1 to 5.

9. The display panel driving circuit according to claim 8, characterized in that: The comparison circuit includes a first comparator and a second comparator; The first comparator is connected to one of the data lines of each group, the second comparator is connected to the other data line of each group, the reference voltage ends of the first comparator and the second comparator also input polarity reference voltage, and the output end of the first comparator and the output end of the second comparator are connected to the timing controller.

10. A display device, characterized in that: The invention comprises a display panel and a display panel driving circuit as claimed in any one of claims 6 to 9, wherein the display panel is connected to the display panel driving circuit.

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