Shift register unit and display panel

Abstract

The invention relates to a shifting register unit and a display panel. The shifting register unit comprises a shifting register and a gating circuit which are electrically connected. The gating circuit comprises a first control module, a second control module and a first output module; wherein the first control module is used for responding to a primary scanning signal output by the shift register and controlling a signal of a first node according to a frequency control signal; the second control module is used for responding to a signal of the first node and controlling a signal of a third node according to a signal of a second node of the shift register, and the second control module comprises a bigrid transistor; and the first output module is used for responding to a signal of the third node and a signal of a fourth node of the shift register, and outputting a target scanning signal according to the first voltage signal and the second voltage signal. The shift register can improve the display performance of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a shift register unit and a display panel. Background Art

[0002] As an important part of the information industry, display technologies have played an important role in the development of information technologies. With the development of display technologies, display panels such as organic light-emitting diode display panels have been widely used.

[0003] Currently, the display performance of display panels is poor. Summary of the Invention

[0004] Based on this, it is necessary to provide a shift register unit and a display panel, aiming to improve the display performance of the display panel.

[0005] In a first aspect, an embodiment of this application provides a shift register unit, which includes:

[0006] A shift register for generating a primary scan signal;

[0007] A gating circuit electrically connected to the shift register, where the gating circuit is configured to generate a target scan signal according to the received primary scan signal and frequency control signal; the gating circuit includes a first control module, a second control module, and a first output module; wherein,

[0008] The control end of the first control module is connected to the output end of the shift register, and the first end of the first control module is configured to receive the frequency control signal, and is configured to respond to the primary scan signal and control the signal of the first node according to the frequency control signal;

[0009] The control end of the second control module is connected to the second end of the first control module, the first end of the second control module is connected to the second node of the shift register, and the second end of the second control module is connected to the third node, and is configured to respond to the signal of the first node and control the signal of the third node according to the signal of the second node;

[0010] The first output module is respectively connected to the fourth node of the shift register and the third node, and is configured to respond to the signal of the third node and the signal of the fourth node, and output a target scan signal according to a first voltage signal and a second voltage signal; wherein, the second control module includes a double-gate transistor.

[0011] In a second aspect, an embodiment of this application further provides a display panel, where the display panel includes the shift register unit provided in the first aspect.

[0012] The shift register unit and display panel provided by the embodiments of the present application include a shift register and a gating circuit. The shift register is used to generate a primary scan signal, and the gating circuit is electrically connected to the shift register. The gating circuit is used to generate a target scan signal according to the received primary scan signal and frequency control signal. The gating circuit includes a first control module, a second control module, and a first output module. Among them, the first control module is used to respond to the primary scan signal output by the shift register and control the signal of the first node according to the frequency control signal. The second control module is used to respond to the signal of the second node and control the signal of the third node according to the signal of the second node of the shift register. Furthermore, the first output module can respond to the signal of the third node and the signal of the fourth node of the shift register, and output the target scan signal according to the first voltage signal and the second voltage signal. In the present application, by setting the second control module to include a double-gate transistor, the stability of the second control module can be improved, preventing the second control module from being abnormally turned on, affecting the potential of the third node, and further preventing the first output module from outputting an abnormal target scan signal under the action of the abnormal potential of the third node, thereby improving the display performance of the display panel. Description of the Drawings

[0013] Figure 1 It is a timing diagram of a GOA circuit in the related art;

[0014] Figure 2 It is a structural diagram of a shift register unit provided by an embodiment of the present application;

[0015] Figure 3 It is another structural diagram of a shift register unit provided by an embodiment of the present application;

[0016] Figure 4 It is still another structural diagram of a shift register unit provided by an embodiment of the present application;

[0017] Figure 5 It is yet another structural diagram of a shift register unit provided by an embodiment of the present application;

[0018] Figure 6 It is yet another structural diagram of a shift register unit provided by an embodiment of the present application;

[0019] Figure 7 It is yet another structural diagram of a shift register unit provided by an embodiment of the present application;

[0020] Figure 8 It is a timing diagram of a shift register unit provided by an embodiment of the present application;

[0021] Figure 9 It is a schematic diagram of a display panel provided by an embodiment of the present application;

[0022] Figure 10 This is a schematic structural diagram of the display device provided by the embodiment of the present application.

[0023] Explanation of reference numerals: 11 - shift register, 111 - third control module, 112 - second output module, 1111 - third control unit, 1112 - fourth control unit, 12 - strobe circuit, 121 - first control module, 122 - second control module, 123 - first output module, 1231 - first output unit, 1232 - second output unit, 100 - display panel, 10 - shift register unit, 101 - first shift register unit, 1101 - first shift register, 1201 - first strobe circuit, 102 - second shift register unit, 1102 - second shift register, 1202 - second strobe circuit, 20 - first gate driving unit, 30 - second gate driving unit, 40 - light emission control driving unit, 50 - pixel circuit. Detailed implementation manners

[0024] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the description of the present application in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0026] When describing the positional relationship, unless otherwise specified, when an element such as a layer, film or substrate is referred to as being "on" another element, it can be directly on the other element or there can also be intermediate elements. Further, when a layer is referred to as being "under" another layer, it can be directly below or there can be one or more intermediate elements. It can also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there can also be one or more intermediate elements.

[0027] In the case of using "including", "having" and "comprising" described herein, unless a clear limiting term is used, such as "only", "consisting of", etc., another component can also be added. Unless otherwise mentioned, the singular form of a term can include the plural form and cannot be understood as having a quantity of one.

[0028] It should be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present application, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0029] It should also be understood that when interpreting an element, although not explicitly described, the element is interpreted as including an error range, and this error range should be within the acceptable deviation range of a specific value determined by those skilled in the art. For example, "about", "approximately" or "substantially" may mean within one or more standard deviations, which is not limited herein.

[0030] In addition, in the specification, the phrase "schematic diagram of planar distribution" refers to the drawing when observing the target part from above, and the phrase "schematic cross-sectional diagram" refers to the drawing when observing the cross-section intercepted by vertically cutting the target part from the side.

[0031] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the various elements are only drawn by way of example in the drawings and not necessarily to the true scale.

[0032] As described in the background art section, the display performance of the display panel in the related art is poor. The inventor found that the reason for the above phenomenon is that in the GOA (Gate On Array / Gate Driver On Array) circuit in the related art, cascaded multi-stage shift registers are usually provided, and a gating circuit is designed for each stage of the shift register. The shift register is responsible for outputting pulse scan signals of each stage under the action of an input signal, a first voltage signal, a second voltage signal, and a clock signal. The gating circuit is correspondingly connected to the output end of the shift register, and is used to receive the primary scan signal, and under the control of a frequency control signal, allows the output of the pulse scan signal only in the effective stage of the frequency control signal. Thus, the output frequency of the pulse scan signal can be controlled by the frequency control signal to change the refresh frequency of the display panel to adapt to different display scenarios. As Figure 1As shown, when the frequency control signal SN-Ctrl received by the strobe circuit in the GOA circuit of the display panel always remains at an invalid level, and the pulse scan signal SN-NEXT output by the shift register changes from low level to high level, the potential of the second node of the shift register becomes low, while the potential of the third node in the strobe circuit is at a high potential, which will cause leakage current in the second control module of the strobe circuit, pulling down the potential of the third node, and further causing leakage current in the first output module, resulting in glitches in the scan signal SN-OUT output by the first output module of the scan signal SN-OUT that should originally output a low level. Under the action of this abnormal scan signal SN-OUT, the pixel circuit will affect the display performance of the display panel.

[0033] Based on the above technical problems, the inventors have found through research that setting the second control module of the strobe circuit as a double-gate transistor can improve the stability of the strobe circuit and avoid abnormal output of the strobe circuit. Therefore, the inventors have further developed the technical solution of the embodiment of the present application. Specifically, the shift register unit provided in the embodiment of the present application includes: a shift register for generating a primary scan signal; a strobe circuit electrically connected to the shift register, and the strobe circuit is used to generate a target scan signal according to the received primary scan signal and frequency control signal; the strobe circuit includes a first control module, a second control module, and a first output module; wherein, the control end of the first control module is connected to the output end of the shift register, the first end of the first control module is used to receive the frequency control signal, and is used to respond to the primary scan signal and control the signal of the first node according to the frequency control signal; the control end of the second control module is connected to the second end of the first control module, the first end of the second control module is connected to the second node of the shift register, and the second end of the second control module is connected to the third node, and is used to respond to the signal of the first node and control the signal of the third node according to the signal of the second node; the first output module is respectively connected to the fourth node and the third node of the shift register, and is used to respond to the signal of the third node and the signal of the fourth node, and output a target scan signal according to the first voltage signal and the second voltage signal; wherein, the second control module includes a double-gate transistor. By adopting the above technical solution, by setting the second control module as a double-gate transistor, the stability of the second control module can be improved, and further the stability of the first output module can be improved, and the display performance of the display panel can be enhanced.

[0034] The above is the core idea of the present application. Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

[0035] In an exemplary embodiment, please refer to Figure 2, this application provides a shift register unit, which includes: a shift register 11 for generating a primary scan signal Next, and a gating circuit 12 electrically connected to the shift register 11 for generating a target scan signal Out according to the received primary scan signal Next and a frequency control signal Ctrl;

[0036] The gating circuit 12 includes a first control module 121, a second control module 122, and a first output module 123; wherein, the control end of the first control module 121 is connected to the output end of the shift register 11, the first end of the first control module 121 is used to receive the frequency control signal Ctrl, and is used to respond to the primary scan signal Next and control the signal of the first node N1 according to the frequency control signal Ctrl. The control end of the second control module 122 is connected to the second end of the first control module 121, the first end of the second control module 122 is connected to the second node N2 of the shift register 11, and the second end of the second control module 122 is connected to the third node N3, and is used to respond to the signal of the first node N1 and control the signal of the third node N3 according to the signal of the second node N2. The first output module 123 is respectively connected to the fourth node N4 and the third node N3 of the shift register 11, and is used to respond to the signals of the third node N3 and the fourth node N4, and output the target scan signal according to the first voltage signal VGH and the second voltage signal VGL; wherein, the second control module 122 includes a double-gate transistor.

[0037] It can be understood that when the frequencies of the target scan signals Out output by each gating circuit 12 in the display panel are all equal to the frequency of the primary scan signal Next, the refresh frequencies of each area in the display panel are the same, and the display panel performs normal display. When it is necessary to perform sub-region frequency division display on the display panel, the frequency control signal Ctrl can be used to control the frequencies of the target scan signals Out of some gating circuits 12 in the display panel to be less than the frequency of the primary scan signal Next, so that the display panel can achieve different refresh frequencies in different areas, that is, the display panel can perform sub-region frequency division display. When the frequency control signal Ctrl is always in an invalid level state, that is, the target scan signal Out controlled by the frequency control signal Ctrl always remains at an invalid level, and when the primary scan signal Next jumps from a low level to a high level, the second node N2 of the shift register 11 jumps from a low potential to a high potential, while the third node N3 of the gating circuit 12 always remains at a high potential. The too large voltage difference between the second node N2 and the third node N3 will cause serious leakage current in the second control module 122. Furthermore, the low potential of the second node N2 is transmitted to the third node N3 through the second control module 122, so that the first output module 123 leaks current under the control of the third node N3 at a low potential, resulting in an abnormal output target scan signal Out.

[0038] In this application, in order to avoid the abnormal activation of the second control module 122, when designing the gating circuit 12, a dual-gate transistor is selected as the second control module 122. The dual-gate transistor has higher stability compared to the single-gate transistor. When there is a large voltage difference between the source and drain of the transistor, the dual-gate transistor is not easily abnormally activated compared to the single-gate transistor. Therefore, in this application, a dual-gate transistor is used as the second control module 122, which can improve the stability of the second control module 122 when the voltage difference between the second node N2 and the third node N3 is large, avoid the abnormal activation of the second control module 122, and further avoid the abnormal target scan signal Out output by the first output module 123.

[0039] The shift register unit provided by the embodiment of this application includes a shift register and a gating circuit. The shift register is used to generate a primary scan signal. The gating circuit is electrically connected to the shift register and is used to generate a target scan signal according to the received primary scan signal and frequency control signal. The gating circuit includes a first control module, a second control module, and a first output module. Among them, the first control module is used to respond to the primary scan signal output by the shift register and control the signal of the first node according to the frequency control signal. The second control module is used to respond to the signal of the second node and control the signal of the third node according to the signal of the second node of the shift register. Furthermore, the first output module can respond to the signal of the third node and the signal of the fourth node of the shift register and output the target scan signal according to the first voltage signal and the second voltage signal. In this application, setting the second control module to include a dual-gate transistor can improve the stability of the second control module, avoid the abnormal activation of the second control module, affect the potential of the third node, and further avoid the abnormal target scan signal output by the first output module under the action of the abnormal potential of the third node, thereby improving the display performance of the display panel.

[0040] In an exemplary embodiment, please refer to Figure 3 , the dual-gate transistor includes: a first transistor T1 and a second transistor T2.

[0041] The gate of the first transistor T1 is connected to the first node N1, and the first pole of the first transistor T1 is connected to the second node N2; the gate of the second transistor T2 is connected to the gate of the first transistor T1, the first pole of the second transistor T2 is connected to the second pole of the first transistor T1, and the second pole of the second transistor T2 is connected to the third node N3.

[0042] It can be understood that the channel length L of a transistor refers to the physical length of the conductive channel between the source and drain in the transistor. The channel length L determines the control accuracy and efficiency when current passes through the transistor and is one of the key parameters of the transistor performance. The shorter the channel length, the stronger the control ability of the transistor over current and the faster the switching speed. However, this will lead to an increase in the power consumption of the transistor and an increase in leakage current. In this application, by setting the second control module 122 to include two series-connected single-gate transistors: the first transistor T1 and the second transistor T2, the channel length L of the second control module 122 can be equivalently increased. Furthermore, the gate control ability of the second control module 122 can be enhanced, abnormal turn-on of the second control module 122 can be avoided, and the leakage current of the second control module 122 can be reduced.

[0043] In an exemplary embodiment, please refer to Figure 4 , the double-gate transistor includes: a third transistor T3. The top gate and the bottom gate of the third transistor T3 are respectively connected to the first node N1. The first pole of the third transistor T3 is connected to the second node N2, and the second pole of the third transistor T3 is connected to the third node N3.

[0044] In another example, the second control module 122 may not use two series-connected single-gate transistors, but directly use a double-gate transistor: the third transistor T3. The third transistor T3 has a double-gate structure, which can better control current and suppress leakage current. Compared with single-gate transistors, under stress, double-gate transistors have higher stability and reliability. The shielding gate of the double-gate transistor can also provide additional protection to reduce the impact of stress on transistor performance. Therefore, in this application, by connecting both the top gate and the bottom gate of the third transistor T3 to the first node N1, the stability of the second control module 122 can be improved, the leakage current of the second control module 122 can be reduced, and abnormal turn-on of the second control module 122 can be avoided.

[0045] In an exemplary embodiment, please refer to Figure 5 , the first control module 121 includes: a fourth transistor T4. The gate of the fourth transistor T4 is connected to the output terminal of the shift register 11. The first pole of the fourth transistor T4 is used to receive the frequency control signal Ctrl, and the second pole of the fourth transistor T4 is connected to the first node N1.

[0046] In this embodiment, when it is necessary to control the frequency of the target scan signal Out of the gating circuit 12 to be less than the frequency of the primary scan signal Next, the frequency control signal Ctrl can be controlled to always maintain a high level. Furthermore, in the previous stage when the primary scan signal Next jumps from a low level to a high level, the high-potential frequency control signal Ctrl is transmitted to the first node N1 through the fourth transistor T4. The first transistor T1 and the second transistor T2 are turned off under the action of the high-potential first node N1. The first output module 123 outputs a low-potential, that is, an invalid-level target scan signal Out under the action of the low-potential fourth node N4. In the stage when the primary scan signal Next jumps from a low level to a high level, the fourth transistor T4 is turned off under the action of the high-level primary scan signal Next, and the first node N1 maintains a high potential. Furthermore, the first transistor T1 and the second transistor T2 remain turned off, and the first output module 123 remains outputting a low-potential target scan signal Out. In this application, since the second control module 122 uses a double-gate transistor, when the primary scan signal Next jumps from a low level to a high level, it has good stability and is not easily turned on.

[0047] In an exemplary embodiment, please refer to Figure 6 , the first output module includes: a first output unit 1231 and a second output unit 1232.

[0048] The first control end of the first output unit 1231 is connected to the second end of the second control module 122. The second control end of the first output unit 1231 is connected to the fourth node N4. The first end of the first output unit 1231 is used to receive the first voltage signal VGH, and the second end of the first output unit 1231 is used to output the target scan signal Out; the control end of the second output unit 1232 is connected to the fourth node N4. The first end of the second output unit 1232 is used to receive the second voltage signal VGL, and the second end of the second output unit 1232 is used to output the target scan signal Out.

[0049] In one example, the first output unit 1231 may include a fifth transistor T5, a first capacitor C1, and a sixth transistor T6.

[0050] The gate of the fifth transistor T5 is connected to the third node. The first pole of the fifth transistor T5 is used to receive the first voltage signal. The second pole of the fifth transistor T5 is connected to the fourth node N4; the first plate of the first capacitor C1 is respectively connected to the second pole of the fifth transistor T5 and the fourth node N4; the gate of the sixth transistor T6 is respectively connected to the first plate of the first capacitor C1, the second pole of the fifth transistor T5, and the fourth node N4. The first pole of the sixth transistor T6 is connected to the second plate of the first capacitor C1 and is used to receive the first voltage signal, and the second pole of the sixth transistor T6 is used to output the target scan signal Out.

[0051] In the present application, the first output unit 1231 is responsible for outputting a high level, that is, the target scan signal Out of the valid level. In one example, when the frequency control signal Ctrl is at a low level, the target scan signal Out output by the first output module 123 is consistent with the primary scan signal Next, that is, when the frequency control signal Ctrl is at a low level, if the primary scan signal Next is at the valid level, the target scan signal Out is at the valid level, and if the primary scan signal Next is at the invalid level, the target scan signal Out is at the invalid level.

[0052] Exemplarily, when the frequency control signal Ctrl is at a low level and the primary scan signal Next is at an invalid level, that is, at a low level, the second node N2 of the shift register 11 is at a high potential, the fourth node N4 of the shift register 11 is at a low potential, the fourth transistor T4 is turned on, and the low-level frequency control signal Ctrl is transmitted to the first node N1 through the fourth transistor T4. Then, the first transistor T1 and the second transistor T2 are turned on, and the high level of the second node N2 is transmitted to the third node N3 through the first transistor T1 and the second transistor T2, and the sixth transistor T6 is turned off under the control of the high-level third node N3; when the primary scan signal Next jumps from a low level to a high level, the second node N2 of the shift register 11 jumps to a low potential, the fourth node N4 of the shift register 11 jumps to a high potential, the fourth transistor T4 is turned off, the first node N1 remains at a low level, the first transistor T1 and the second transistor T2 are turned on, the low level of the second node N2 is transmitted to the third node N3 through the first transistor T1 and the second transistor T2, the sixth transistor T6 is turned on under the control of the low-level third node N3, and the first output unit 1231 outputs the target scan signal Out of the high level.

[0053] In one example, the second output unit 1232 may include a seventh transistor T7. The gate of the seventh transistor T7 is connected to the first node. The first pole of the seventh transistor T7 is used to receive the second voltage signal. The second pole of the seventh transistor T7 is connected to the second pole of the sixth transistor T6 and is used to output the target scan signal.

[0054] In the present application, the first output unit 1231 is responsible for outputting a low level, that is, the target scan signal Out of the invalid level. When the frequency control signal Ctrl is at a high level, the target scan signal Out output by the first output module 123 is always at the invalid level, that is, when the frequency control signal Ctrl is at a high level, regardless of whether the primary scan signal Next is at the valid level or the invalid level, the target scan signal Out is always at the invalid level.

[0055] For example, when the frequency control signal Ctrl is at a high level and the primary scan signal Next is at an invalid level, i.e., a low level, the second node N2 of the shift register 11 is at a high potential, the fourth node N4 of the shift register 11 is at a low potential, the fourth transistor T4 and the fifth transistor T5 are turned on, and the high-level frequency control signal Ctrl is transmitted to the first node N1 through the fourth transistor T4. Consequently, the first transistor T1 and the second transistor T2 are turned off, and the high-level first voltage signal VGH is transmitted to the third node N3 through the fifth transistor T5. The sixth transistor T6 is turned off under the control of the high-level third node N3, and the seventh transistor T7 is turned on under the influence of the low-potential fourth node N4. The second voltage signal VGL is output through the seventh transistor T7, and the first output module 123 outputs a low-level target scan signal Out. When the primary scan signal Next jumps from a low level to a high level, the second node N2 of the shift register 11 jumps to a low potential, and the fourth node N4 of the shift register 11 jumps to a high potential. Consequently, the fourth transistor T4, the fifth transistor T5, and the seventh transistor are turned off, the first node N1 remains at a low potential in a floating state, the first transistor T1 and the second transistor T2 remain turned off, and the third node N3 remains at a high potential in a floating state. In this application, since the second control module 122 is a double-gate transistor, the second control module 122 will not have leakage current due to a large voltage difference between the second node N2 and the third node N3. The sixth transistor T6 remains turned off under the influence of the high-potential third node N3. Consequently, the second pole of the seventh transistor T7 and the second pole of the sixth transistor T6 remain outputting a low-level target scan signal Out in a floating state.

[0056] In an exemplary embodiment, when the primary scan signal Next is at a valid level and the time period of the valid level is within the time period of the valid level of the frequency control signal Crtl, the target scan signal Out is at a valid level.

[0057] It can be understood that in this application, the valid level of the primary scan signal Next and the target scan signal Out is a high level, the invalid level of the primary scan signal Next and the target scan signal Out is a low level, the valid level of the frequency control signal Crtl is a low level, and the invalid level of the frequency control signal Crtl is a high level. When the frequency control signal Crtl is at a low level, the level state of the target scan signal Out can be consistent with the level state of the primary scan signal Next; when the frequency control signal Crtl is at a high level, regardless of whether the primary scan signal Next is at a valid level or an invalid level, the target scan signal Out is always at an invalid level.

[0058] In an exemplary embodiment, please refer to Figure 7 , the shift register 11 includes: a third control module 111 and a second output module 112.

[0059] The third control module 111 is configured to receive an input signal STV, a first voltage signal VGH, and a second voltage signal VGL, and in response to a first clock signal CK and a second clock signal XCK, control the signals of a fourth node N4 and a second node N2; the second output module is configured to receive the first voltage signal VGH and the second voltage signal VGL, and in response to the signals of the fourth node N4 and the second node N2, output a primary scan signal Next.

[0060] Among them, the third control module 111 includes a third control unit 1111 and a fourth control unit 1112. The third control unit 1111 is configured to receive the first voltage signal VGH and the second voltage signal VGL, and in response to the first clock signal CK and the second clock signal XCK, control the signal of the second node N2. The fourth control unit 1112 is configured to receive the input signal STV, and in response to the first clock signal CK, control the signal of the fourth node N4.

[0061] Specifically, the third control unit 1111 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, a second capacitor C2, and a third capacitor C3. The fourth control unit 1112 includes a twentieth transistor T20 and a twenty-first transistor T21. The second output module 112 includes a twenty-second transistor T22, a twenty-third transistor T23, and a fourth capacitor C4.

[0062] In a detailed embodiment, please refer to Figure 7 and Figure 8 , Figure 8 which is a timing diagram of the shift register unit when the frequency control signal Ctrl always maintains a high level state in an example.

[0063] In Figure 8In the t1 stage, in the shift register 11, the eighth transistor T8, the ninth transistor T9, the twentieth transistor T20, the twenty-first transistor T21, the fourteenth transistor T14, and the twenty-third transistor T23 are turned on, the eleventh transistor T11 and the twenty-second transistor T22 are turned off, the fourth node N4 is at a low potential, the second node N2 is at a high potential, and the shift register 11 outputs a primary scan signal Next with a low level; in the gating circuit 12, the fourth transistor T4 is turned on under the action of the primary scan signal Next with a low level, and the high-level frequency control signal Ctrl is transmitted to the first node N1 through the fourth transistor, the first transistor T1 and the second transistor T2 are turned off, the seventh transistor T7 and the fifth transistor T5 are turned on under the action of the low-potential fourth node N4, the third node N3 becomes a high potential, the sixth transistor T6 is turned off, and the gating circuit outputs a target scan signal Out with a low level through the seventh transistor T7.

[0064] In Figure 8 In the t2 stage, in the shift register 11, the eighth transistor T8, the twelfth transistor T12, the twentieth transistor T20, and the twenty-first transistor T21 are turned off, the second node N2 maintains a high potential, the fourth node N4 maintains a low potential, the twenty-second transistor T22 is turned off, the twenty-third transistor T23 is turned on, and the shift register 11 outputs a primary scan signal Next with a low level; in the gating circuit 12, the fourth transistor T4 is turned on under the action of the primary scan signal Next with a low level, and the high-level frequency control signal Ctrl is transmitted to the first node N1 through the fourth transistor, the first transistor T1 and the second transistor T2 are turned off, the seventh transistor T7 and the fifth transistor T5 are turned on under the action of the low-potential fourth node N4, the third node N3 becomes a high potential, the sixth transistor T6 is turned off, and the gating circuit 12 outputs a target scan signal Out with a low level through the seventh transistor T7.

[0065] In Figure 8In the t3 stage, in the shift register 11, the eighth transistor T8, the ninth transistor T9, the twentieth transistor T20, and the twenty-first transistor T21 are turned on, the fourth node N4 becomes high potential, the N5 node and the N6 node become low potential, the twelfth transistor T12 is turned on, the second node N2 maintains high potential, the twenty-third transistor T23 and the twenty-second transistor T22 are turned off, and the shift register 11 outputs a low-level primary scan signal Next in a floating state; in the gating circuit 12, the fourth transistor T4 is turned on under the action of the low-level primary scan signal Next, the high-level frequency control signal Ctrl is transmitted to the first node N1 through the fourth transistor T4, the first transistor T1 and the second transistor T2 are turned off, the seventh transistor T7 and the fifth transistor T5 are turned off under the action of the high-potential fourth node N4, the third node N3 maintains high potential, the sixth transistor T6 is turned off, and the gating circuit 12 outputs a low-level target scan signal Out in a floating state.

[0066] In Figure 8 In the t4 stage, in the shift register 11, the eighth transistor T8, the twelfth transistor T12, the twentieth transistor T20, and the twenty-first transistor T21 are turned off, the second node N2 becomes low potential, the fourth node N4 maintains high potential, the twenty-second transistor T22 is turned on, the twenty-third transistor T23 is turned off, and the shift register 11 outputs a high-level primary scan signal Next through the twenty-second transistor T22; in the gating circuit 12, the fourth transistor T4 is turned off under the action of the high-level primary scan signal Next, the first node N1 remains high potential, and thus the first transistor T1 and the second transistor T2 remain turned off, the fourth transistor T4 is turned off under the action of the high-potential fourth node N4, the third node N3 remains high potential in a floating state. In this embodiment, by setting the second control module 122 to include two serially connected first transistors T1 and second transistors T2, the channel length L of the second control module 122 can be equivalently increased, and thus the gate control ability of the second control module 122 can be enhanced, avoiding abnormal turn-on of the second control module 122, reducing or eliminating the leakage current of the second control module 122, and thus avoiding the leakage current of the sixth transistor T6, so that the first output module 123 maintains the output of the low-potential target scan signal Out in a floating state.

[0067] In an exemplary embodiment, the embodiment of the present application further provides a display panel. In one example, please refer to Figure 9, the display panel 100 of the present application includes a display area AA and a non-display area FA surrounding at least part of the display area AA. The pixel circuit 50 is located in the display area AA, and the shift register unit 10 in any of the above embodiments is located in the non-display area FA. Specifically, the display panel 100 includes a first shift register unit 101 and a second shift register unit 102. The first shift register unit 101 includes a first shift register 1101 and a first gating circuit 1201. The first shift register unit 101 is configured to provide a first target scan signal to adjacent two rows of pixel circuits 50 through two first signal transmission lines respectively, and the first target scan signal is used to control the threshold compensation process of the pixel circuit 50; the second shift register unit 102 includes a second shift register 1102 and a second gating circuit 1202. The second shift register unit 102 is configured to provide a second target scan signal to adjacent two rows of pixel circuits 50 through two second signal transmission lines respectively, and the first target scan signal is used to control the gate reset process of the driving transistor in the pixel circuit 50. The display panel 100 further includes a first gate driving unit 20, a second gate driving unit 30, and a light emission control driving unit 40. The first gate driving unit 20, the second gate driving unit 30, and the light emission control driving unit 40 are all located in the non-display area FA. Two first gate driving units 20 arranged at the same level provide a first scan signal to the pixel circuits 50 in the same row through a third signal transmission line, and the first scan signal is used to control the source reset process of the driving transistor and the reset process of the anode of the light emitting element; the second gate driving unit 30 provides a second scan signal to adjacent two rows of pixel circuits 50 through two fourth signal transmission lines respectively, and the second scan signal is used to control the data writing process of the pixel circuit; the light emission control driving unit 40 provides a light emission control signal to adjacent two rows of pixel circuits 50 through two fifth signal transmission lines respectively, and the light emission control signal is used to control the pixel circuit to provide a driving current to the light emitting element.

[0068] The display panel of the present application also has the beneficial effects of the shift register unit in the above embodiments. For the same parts, reference can be made to the explanation of the shift register unit above for understanding, and details will not be repeated below.

[0069] Based on the same inventive concept, an embodiment of the present application also provides a display device. Figure 10 is a schematic structural diagram of the display device 200 provided by an embodiment of the present application. As Figure 10 shown, the display device 200 includes the display panel 100 in the above embodiment. Exemplarily, as Figure 10 shown, the display device 200 includes the display panel 100. Therefore, the display device 200 also has the beneficial effects of the display panel 100 in the above embodiments. For the same parts, reference can be made to the explanation of the display panel 100 above for understanding, and details will not be repeated below.

[0070] The display device 200 provided by the embodiments of the present application may be Figure 10 the mobile phone shown in the figure, or any electronic product with a display function, including but not limited to the following categories: televisions, laptop computers, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, industrial control devices, medical display screens, touch interaction terminals, etc. The embodiments of the present application do not make special limitations in this regard.

[0071] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0072] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A shift register unit, characterized in that: The shift register unit comprises: A shift register for generating a primary scanning signal; A gating circuit is electrically connected to the shift register, and is used to generate a target scanning signal according to the received primary scanning signal and frequency control signal; the gating circuit includes a first control module, a second control module and a first output module; wherein, The control end of the first control module is connected to the output end of the shift register, and the first end of the first control module is used to receive a frequency control signal, and is used to respond to the primary scanning signal and control the signal of the first node according to the frequency control signal; The control end of the second control module is connected to the second end of the first control module, the first end of the second control module is connected to the second node of the shift register, and the second end of the second control module is connected to the third node, and is used to respond to the signal of the first node and control the signal of the third node according to the signal of the second node; The first output module is connected to the fourth node and the third node of the shift register respectively, and is used to respond to the signal of the third node and the signal of the fourth node, and output the target scanning signal according to the first voltage signal and the second voltage signal; wherein the second control module includes a dual-gate transistor.

2. The shift register unit according to claim 1, characterized in that: The dual-gate transistor comprises: a first transistor, wherein a gate of the first transistor is connected to the first node, and a first electrode of the first transistor is connected to the second node; A second transistor, wherein a gate of the second transistor is connected to the gate of the first transistor, a first electrode of the second transistor is connected to the second electrode of the first transistor, and a second electrode of the second transistor is connected to the third node.

3. The shift register unit according to claim 1, characterized in that: The dual-gate transistor comprises: A third transistor, wherein a top gate and a bottom gate of the third transistor are respectively connected to the first node, a first electrode of the third transistor is connected to the second node, and a second electrode of the third transistor is connected to the third node.

4. The shift register unit according to claim 1, characterized in that: The first control module comprises: A fourth transistor, wherein a gate of the fourth transistor is connected to the output end of the shift register, a first electrode of the fourth transistor is used to receive the frequency control signal, and a second electrode of the fourth transistor is connected to the first node.

5. The shift register unit according to claim 1, characterized in that: The first output module comprises: a first output unit, wherein a first control end of the first output unit is connected to a second end of the second control module, a second control end of the first output unit is connected to the fourth node, a first end of the first output unit is used to receive a first voltage signal, and a second end of the first output unit is used to output a target scanning signal; A second output unit, wherein a control end of the second output unit is connected to the fourth node, a first end of the second output unit is used to receive a second voltage signal, and a second end of the second output unit is used to output a target scanning signal.

6. The shift register unit according to claim 5, characterized in that: The first output unit comprises: a fifth transistor, wherein a gate of the fifth transistor is connected to the third node, a first electrode of the fifth transistor is used to receive a first voltage signal, and a second electrode of the fifth transistor is connected to the fourth node; a first capacitor, wherein a first electrode plate of the first capacitor is respectively connected to the second electrode of the fifth transistor and the fourth node; A sixth transistor, wherein the gate of the sixth transistor is connected to the first plate of the first capacitor, the second plate of the fifth transistor, and the fourth node respectively, the first plate of the sixth transistor is connected to the second plate of the first capacitor and is used to receive a first voltage signal, and the second plate of the sixth transistor is used to output a target scanning signal.

7. The shift register unit according to claim 6, characterized in that: The second output unit comprises: A seventh transistor, wherein the gate of the seventh transistor is connected to the first node, the first electrode of the seventh transistor is used to receive a second voltage signal, the second electrode of the seventh transistor is connected to the second electrode of the sixth transistor, and is used to output a target scanning signal.

8. The shift register unit according to claim 1, characterized in that: When the primary scanning signal is at an effective level and the time period of the effective level is within the time period of the effective level of the frequency control signal, the target scanning signal is at an effective level.

9. The shift register unit according to claim 1, characterized in that: The shift register comprises: a third control module, the third control module being used to receive the input signal, the first voltage signal and the second voltage signal, and to control the signal of the fourth node and the signal of the second node in response to the first clock signal and the second clock signal; The second output module is used to receive the first voltage signal and the second voltage signal, and output the primary scanning signal in response to the signal of the fourth node and the signal of the second node.

10. A display panel, characterized in that: The invention comprises the shift register unit according to any one of claims 1 to 9.

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