Ldpc decoder and method, device, medium for early aborting decoding thereof

Abstract

The application discloses an LDPC decoder and a method and device for early termination of decoding of the LDPC decoder and a medium, and relates to the technical field of LDPC code decoding. The method comprises the following steps: performing multiple decoding iteration processes on to-be-decoded data, and obtaining a corresponding error code word at the end of each decoding iteration process; calculating the to-be-decoded data and the error code word based on a preset bit inversion number calculation formula to obtain a bit inversion number at the end of each decoding iteration process; when a first discriminant weight value obtained at the end of the first decoding iteration process is located in a preset transition interval and the third decoding iteration process ends, obtaining an original error bit number estimation value by estimation according to the first bit inversion number, the second bit inversion number and the third bit inversion number; and when the original error bit number estimation value is greater than a preset threshold, early termination of decoding is performed. The early termination of decoding strategy can be optimized based on the original error bit number estimation value, and the early termination of decoding can be more flexibly and efficiently realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of LDPC code decoding, in particular to an LDPC decoder and a method, device and medium for early aborting decoding. BACKGROUND

[0002] In order to correct data errors in the flash memory, an ECC (Error Correction Code) module needs to be designed in the flash memory controller chip to encode the original data written into the flash memory and decode the data read from the flash memory. The ECC module in the mainstream flash memory controller chip currently uses LDPC (Low-density Parity-check) code. The data unit processed during LDPC code decoding is called a code word with errors, and the decoding algorithm used needs to perform iterative operations. Each round of iterative operation attempts to reverse a part of the original error bits in the code word with errors read from the flash memory. After each round of iterative operation, the determinants (syndromes) of the rows of the check matrix are checked to determine whether the conditions are met. If all conditions are met, it is considered that the decoding is successful. If all conditions are not met, the next round of iterative operation is performed. Among them, the number of original error bits is an important indicator in the state of the flash memory, and has a guiding reference value for analysis of the characteristics of the flash memory.

[0003] In theory, when the number of original error bits in the code word with errors is too large, the LDPC decoding operation needs to be continuously performed to complete the decoding, which is easy to cause the data path to be stuck. Therefore, the LDPC decoding algorithm generally uses a decoding abort strategy based on the upper limit of the number of iterations, but setting the upper limit of the number of iterations can only ensure that the data path of the LDPC module is not stuck. After the LDPC decoding fails, the flash memory controller needs to change the read threshold voltage parameter to perform a re-reading operation and decoding again until the decoding is successful. In order to further save the time consumed by multiple iterations of the LDPC decoder, the LDPC decoder introduces an early abort decoding strategy. The current early abort decoding strategy mainly determines whether to abort the decoding early by calculating whether the determinant weight of the LDPC decoding at a certain moment exceeds a certain threshold, and does not involve the estimation of the number of original error bits. The value of the determinant weight in the early abort decoding strategy fluctuates greatly, and a complex control strategy and a long time are needed to achieve a more accurate prediction. Therefore, how to optimize the early abort decoding strategy is a technical problem to be solved. SUMMARY

[0004] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application provides an LDPC decoder and a method, device and medium for early termination of decoding thereof, which can quickly calculate an original error bit number estimate, and optimize the early termination of decoding strategy based on the original error bit number estimate, so that the LDPC decoder can more flexibly and efficiently realize early termination of decoding.

[0005] In a first aspect, the embodiments of the present application provide a method for early termination of decoding of an LDPC decoder, applied to the LDPC decoder, and the method comprises:

[0006] obtaining to-be-decoded data from a flash memory;

[0007] performing multiple decoding iteration processes on the to-be-decoded data, and obtaining a corresponding error-containing codeword at the end of each decoding iteration process;

[0008] calculating the to-be-decoded data and the error-containing codeword obtained at the end of each decoding iteration process based on a preset bit reversal number calculation formula, to obtain a bit reversal number at the end of each decoding iteration process;

[0009] when the first discriminant weight value obtained at the end of the first decoding iteration process is located in a preset transition interval and the third decoding iteration process ends, obtaining a first bit reversal number at the end of the first decoding iteration process, a second bit reversal number at the end of the second decoding iteration process, and a third bit reversal number at the end of the third decoding iteration process;

[0010] performing original error bit number estimation processing according to the first bit reversal number, the second bit reversal number and the third bit reversal number, to obtain an original error bit number estimate;

[0011] when the original error bit number estimate is greater than a preset threshold, early termination of decoding is performed, and a flash memory re-reading operation is performed.

[0012] In a second aspect, the embodiments of the present application provide an LDPC decoder, comprising:

[0013] a data acquisition unit configured to obtain to-be-decoded data from a flash memory;

[0014] an iteration calculation unit configured to perform multiple decoding iteration processes on the to-be-decoded data, and obtain a corresponding error-containing codeword at the end of each decoding iteration process;

[0015] a bit reversal number calculation unit configured to calculate the to-be-decoded data and the error-containing codeword obtained at the end of each decoding iteration process based on a preset bit reversal number calculation formula, to obtain a bit reversal number at the end of each decoding iteration process;

[0016] The original error bit number estimation unit is configured to, when the first decision threshold weight value obtained at the end of the first decoding iteration processing is located in a preset transition interval and in the case that the third decoding iteration processing ends, acquire a first bit inversion number at the end of the first decoding iteration processing, a second bit inversion number at the end of the second decoding iteration processing, and a third bit inversion number at the end of the third decoding iteration processing; and perform original error bit number estimation processing according to the first bit inversion number, the second bit inversion number, and the third bit inversion number to obtain an original error bit number estimation value.

[0017] The early termination decoding control unit is configured to, when the original error bit number estimation value is greater than a preset threshold value, terminate the decoding early.

[0018] In a third aspect, an embodiment of the present application provides an electronic device, including the LDPC decoder as described in the second aspect.

[0019] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are used to make a computer execute the method for early termination decoding of the LDPC decoder as described in any one of the embodiments of the first aspect.

[0020] The embodiment of the present application comprises the following steps: when the LDPC decoder needs to perform LDPC decoding, firstly, obtaining the to-be-decoded data from the flash memory; secondly, performing multiple decoding iteration processes on the to-be-decoded data, obtaining the corresponding error code word at the end of each decoding iteration process; then, calculating the to-be-decoded data and the error code word obtained at the end of each decoding iteration process based on a preset bit inversion number calculation formula, obtaining the bit inversion number at the end of each decoding iteration process; laying a data foundation for subsequent calculation of the original error bit number estimate; then, when the first decoding iteration process ends, obtaining the first bit inversion number at the end of the first decoding iteration process, the second bit inversion number at the end of the second decoding iteration process, and the third bit inversion number at the end of the third decoding iteration process, provided that the first discriminant weight value at the end of the first decoding iteration process is located in a preset transition interval and the third decoding iteration process ends; then, performing original error bit number estimation processing according to the first bit inversion number, the second bit inversion number, and the third bit inversion number, and obtaining the original error bit number estimate; the original error bit number estimate can be calculated relatively quickly, and a reliable reference is provided for subsequent execution of the early termination decoding strategy; finally, when the original error bit number estimate is greater than a preset threshold, early termination decoding is performed, and a flash memory re-reading operation is performed; the original error bit number estimate is used for judging early termination decoding, the early termination decoding strategy is optimized, and the LDPC decoder can more flexibly and efficiently realize early termination decoding. That is, the embodiment of the present application can calculate the original error bit number estimate relatively quickly, and the early termination decoding strategy is optimized based on the original error bit number estimate, so that the LDPC decoder can more flexibly and efficiently realize early termination decoding. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a functional module schematic diagram of an LDPC decoder provided by an embodiment of the present application;

[0022] Figure 2 is a flowchart of an early termination decoding method of an LDPC decoder provided by an embodiment of the present application;

[0023] Figure 3 is a specific flowchart of calculating the first three bit inversion numbers provided by an embodiment of the present application;

[0024] Figure 4 is a whole flowchart of an early termination decoding method of an LDPC decoder provided by another embodiment of the present application;

[0025] Figure 5 is a specific flowchart of an early termination decoding strategy based on an upper limit of the number of decoding iterations;

[0026] Figure 6is a schematic diagram of the relationship between the number of iterations of the data to be decoded and the number of original error bits in the abort-decoding strategy based on the upper limit of the number of decoding iterations;

[0027] Figure 7 is a specific flowchart of the early abort-decoding strategy based on the discriminant weight. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments.

[0029] It should be understood that, in the description of the present application, the orientation description, such as the orientation or position relationship indicated by up, down, front, back, left, right, etc., is based on the orientation or position relationship shown in the drawings, and is only for the purpose of facilitating the description of the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0030] It should be noted that, in the description of the present application, although a logical sequence is shown in the flowchart, in some cases, the steps shown or described can be performed in an order different from that in the flowchart. In the description of the present application, the meaning of "one or more" is one or more, and the meaning of "multiple" is two or more. The description of "first", "second" is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implying the number of indicated technical features or the order of indicated technical features.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0032] First, some terms involved in the present application are explained:

[0033] LDPC code (Low-Density Parity-Check Code) is a kind of linear block code. The core of LDPC code is its sparse parity-check matrix (H matrix). Sparse means that most elements in the matrix are zero, and only a small number of elements are 1. This sparse structure enables LDPC code to use an efficient iterative algorithm for decoding, reducing the computational complexity. LDPC code, with its sparse check matrix structure and efficient decoding algorithm, plays an important role in modern communication and storage fields.

[0034] This application provides a method for early termination of decoding in an LDPC decoder, an LDPC decoder, an electronic device, and a computer-readable storage medium, relating to the field of LDPC code decoding technology. The method includes: performing multiple decoding iterations on the data to be decoded, obtaining a corresponding erroneous codeword at the end of each decoding iteration; calculating the bit inversion number at the end of each decoding iteration based on a preset bit inversion number calculation formula for the data to be decoded and the erroneous codeword; when the first discriminant weight value obtained at the end of the first decoding iteration is within a preset transition range, and the third decoding iteration ends, estimating the original number of erroneous bits based on the obtained first, second, and third bit inversion numbers; and prematurely terminating decoding when the original number of erroneous bits is greater than a preset threshold. This method can optimize the early termination decoding strategy based on the original number of erroneous bits, enabling more flexible and efficient implementation of early termination decoding.

[0035] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0036] like Figure 1 As shown, the LDPC decoder 100 includes: a data acquisition unit 110, an iterative calculation unit 120, a bit inversion number calculation unit 130, an original error bit number estimation unit 140, and a decoding termination control unit 150.

[0037] The data acquisition unit 110 is used to acquire the data to be decoded from the flash memory, thereby laying the data foundation for subsequent decoding iteration processing.

[0038] The iterative calculation unit 120 is used to perform multiple decoding iterations on the data to be decoded, and obtain the corresponding error codeword at the end of each decoding iteration; thus laying the data foundation for subsequent calculation of the bit reversal number at the end of each decoding iteration.

[0039] The bit reversal number calculation unit 130 is used to calculate the bit reversal number at the end of each decoding iteration based on the preset bit reversal number calculation formula, and to obtain the bit reversal number at the end of each decoding iteration; thus laying the data foundation for subsequent calculation of the original error bit number estimation value.

[0040] The original error bit number estimation unit 140 is configured to obtain the first bit inversion number at the end of the first decoding iteration processing, the second bit inversion number at the end of the second decoding iteration processing, and the third bit inversion number at the end of the third decoding iteration processing when the first decision weight value obtained at the end of the first decoding iteration processing is located in the preset transition interval and the third decoding iteration processing ends; perform original error bit number estimation processing according to the first bit inversion number, the second bit inversion number, and the third bit inversion number to obtain an original error bit number estimation value; and the original error bit number estimation value can be calculated relatively quickly, thereby providing a reliable reference for subsequent early termination decoding strategies.

[0041] The early termination decoding control unit 150 is configured to early terminate decoding when the original error bit number estimation value is greater than a preset threshold value; thus, early termination decoding is determined based on the original error bit number estimation value, the early termination decoding strategy is optimized, and the LDPC decoder can more flexibly and efficiently realize early termination decoding.

[0042] The LDPC decoder provided by the embodiment of the present application can calculate the original error bit number estimation value relatively quickly through the mutual cooperation and matching of the data acquisition unit 110, the iteration calculation unit 120, the bit inversion number calculation unit 130, the original error bit number estimation unit 140, and the early termination decoding control unit 150 when LDPC decoding is needed, and the early termination decoding strategy is optimized based on the original error bit number estimation value, so that the LDPC decoder can more flexibly and efficiently realize early termination decoding.

[0043] Those skilled in the art can understand that the system structure shown in the figure does not constitute a limitation on the embodiment of the present application, and can include more or fewer components than the figure, or combine certain components, or different component arrangements.

[0044] The system embodiments described above are only schematic, and the units described as separate components can be or can not be physically separated, that is, can be located in one place or can be distributed on multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment of the present application.

[0045] Those skilled in the art can understand that the system architecture and application scenarios described in the embodiment of the present application are used to more clearly illustrate the technical solutions of the embodiment of the present application, and do not constitute a limitation on the technical solutions provided by the embodiment of the present application. Those skilled in the art can know that, with the evolution of system architecture and the appearance of new application scenarios, the technical solutions provided by the embodiment of the present application are also applicable to similar technical problems.

[0046] Based on the above system structure, the following presents various embodiments of the method of early termination decoding of the LDPC decoder of the present application.

[0047] As shown in Figure 2 The method of early termination decoding of the LDPC decoder can be applied in the system framework as shown in Figure 1 The method of early termination decoding of the LDPC decoder can include, but is not limited to, steps S110 to S160.

[0048] Step S110: Obtain the to-be-decoded data from the flash memory.

[0049] Step S120: Perform multiple decoding iteration processes on the to-be-decoded data, and obtain the corresponding error-containing codeword at the end of each decoding iteration process.

[0050] Step S130: Calculate the to-be-decoded data and the corresponding error-containing codeword obtained at the end of each decoding iteration process based on a preset bit reversal number calculation formula, to obtain the bit reversal number at the end of each decoding iteration process.

[0051] Step S140: When the first discriminant weight value obtained at the end of the first decoding iteration process is located in the preset transition interval and the third decoding iteration process ends, obtain the first bit reversal number at the end of the first decoding iteration process, the second bit reversal number at the end of the second decoding iteration process, and the third bit reversal number at the end of the third decoding iteration process.

[0052] Step S150: Perform original error bit number estimation processing according to the first bit reversal number, the second bit reversal number, and the third bit reversal number, to obtain an original error bit number estimation value.

[0053] Step S160: When the original error bit number estimation value is greater than a preset threshold, early termination decoding is performed, and a flash memory re-reading operation is performed.

[0054] Further explanation of step S110: by obtaining the to-be-decoded data from the flash memory, a data foundation is laid for subsequent decoding iteration processing.

[0055] Further explanation of step S120: after obtaining the corresponding error-containing codeword at the end of each decoding iteration process, the error-containing codeword is saved, laying a data foundation for subsequent calculation of the bit reversal number at the end of each decoding iteration process.

[0056] According to some embodiments of the present application, further explanation of step S130, wherein the preset bit reversal number calculation formula is:

[0057] Wherein, b nis the estimated bit flipping number at the end of each decoding iteration processing; HW() is a Hamming weight calculation function; is an XOR operation; v0 is the data to be decoded; n is the error code word obtained at the end of the n-th decoding iteration processing.

[0058] Specifically, the Hamming weight calculation function is used to count the number of "1"s in a binary number. For example, the binary number 1011 includes three "1"s, and the Hamming weight of the binary number 1011 is 3.

[0059] Specifically, as shown in Figure 3 First, the LDPC decoder obtains the data to be decoded v0. When the first decoding iteration processing ends, the error code word v1 at the end of the first decoding iteration processing is obtained, and the error code word v1 is substituted into the preset bit flipping number calculation formula to obtain the first bit flipping number b1. When the second decoding iteration processing continues, when the second decoding iteration processing ends, the error code word v2 at the end of the second decoding iteration processing is obtained, and the error code word v2 is substituted into the preset bit flipping number calculation formula to obtain the second bit flipping number b2. When the third decoding iteration processing continues, when the third decoding iteration processing ends, the error code word v3 at the end of the third decoding iteration processing is obtained, and the error code word v3 is substituted into the preset bit flipping number calculation formula to obtain the second bit flipping number b3.

[0060] Through steps S110 to S160, when the LDPC decoder needs to perform LDPC decoding, firstly, the to-be-decoded data is obtained from the flash memory; secondly, the to-be-decoded data is subjected to multiple decoding iteration processes, and a corresponding error code word is obtained at the end of each decoding iteration process; then, the to-be-decoded data and the error code word obtained at the end of each decoding iteration process are calculated based on a preset bit inversion number calculation formula to obtain the bit inversion number at the end of each decoding iteration process, thereby laying a data foundation for subsequent calculation of an original error bit number estimate; then, when the first decision weight value obtained at the end of the first decoding iteration process is located in the preset transition interval and the third decoding iteration process ends, the first bit inversion number obtained at the end of the first decoding iteration process, the second bit inversion number obtained at the end of the second decoding iteration process, and the third bit inversion number obtained at the end of the third decoding iteration process are obtained; then, the original error bit number estimate is obtained through original error bit number estimation processing according to the first bit inversion number, the second bit inversion number, and the third bit inversion number; the original error bit number estimate can be calculated relatively quickly, thereby providing a reliable reference for subsequent execution of the early termination decoding strategy; finally, when the original error bit number estimate is greater than a preset threshold, the decoding is early terminated, and a flash memory re-reading operation is performed; the original error bit number estimate is used for judging early termination of decoding, thereby optimizing the early termination decoding strategy and enabling the LDPC decoder to more flexibly and efficiently realize early termination of decoding. That is, the original error bit number estimate can be calculated relatively quickly according to the embodiments of the application, and the early termination decoding strategy is optimized based on the original error bit number estimate, thereby enabling the LDPC decoder to more flexibly and efficiently realize early termination of decoding.

[0061] Step S140 is further described. The calculation method of the decision weight value is as follows: at a certain moment in the decoding process, the current code word is subjected to parity check with each check row of the LDPC check matrix, and the number of check rows that do not satisfy the parity check is the decision weight. In the present application, the first decision weight value is calculated at the end of the first decoding iteration process, and the first decision weight value is used to provide a reference for whether to start the early termination decoding strategy of the present application subsequently.

[0062] According to some embodiments of the present application, the method for early termination decoding of the LDPC decoder further includes but is not limited to steps S170 to S180.

[0063] Step S170: when the first decision weight value obtained at the end of the first decoding iteration process is located in the preset determination early termination interval, the decoding is early terminated, and a flash memory re-reading operation is performed.

[0064] Step S180: When the first discriminant weight value obtained at the end of the first decoding iteration processing is located in the preset determined non-early abort interval, the decoding iteration processing is continued until the iteration number reaches the number threshold.

[0065] Specifically, the determined early abort interval, the transition interval, and the determined non-early abort interval in the embodiments of the present application are preset according to experience. As an example, the process of setting the determined early abort interval, the transition interval, and the determined non-early abort interval according to experience is described. It is assumed that the LDPC check matrix has 2048 rows, and the discriminant weight value obtained after the first decoding iteration processing is W1. It is found in the actual measurement of the LDPC controller that the decoding always fails when the discriminant weight value W1 is greater than 800, and the decoding always succeeds when the discriminant weight value W1 is less than 600. Therefore, the determined early abort interval is (800, +∞), the determined non-early abort interval is (-∞, 600), and the transition interval is [600, 800]. The determined early abort interval, the transition interval, and the determined non-early abort interval are affected by the type of flash memory used, the working conditions of the controller, and other factors. The above is only an example for illustration. The present application does not specifically limit the value range of the determined early abort interval, the transition interval, and the determined non-early abort interval.

[0066] Through steps S140, S170, and S180, after the first discriminant weight value is calculated when the first decoding iteration processing ends, it is determined whether the first discriminant weight value is located in the determined early abort interval, the transition interval, or the determined non-early abort interval. When the first discriminant weight value is located in the determined early abort interval, the decoding is aborted in advance by executing step S170, and the flash memory is read again, which is beneficial to reducing the overall decoding time. When the first discriminant weight value is located in the determined non-early abort interval, it is confirmed that the early abort decoding strategy based on the original error bit number estimate value provided in the embodiments of the present application is not triggered, and the decoding iteration processing is continued until the iteration number reaches the number threshold; in the case where the decoding is determined to be successful, the early abort decoding strategy is not triggered, which is beneficial to ensuring high decoding efficiency. When the first discriminant weight value is located in the transition interval and the third decoding iteration processing ends, the early abort decoding strategy based on the original error bit number estimate value provided in the embodiments of the present application is triggered. Through steps S170 and S180, the LDPC decoder can more flexibly select not to trigger the early abort decoding strategy based on the original error bit number estimate value by taking the first discriminant weight value as a reference.

[0067] According to some embodiments of the present application, the method of the LDPC decoder for early stopping decoding further comprises: when the original error bit number estimation value is less than or equal to the preset threshold, not stopping decoding early; and continuing decoding iteration processing until the iteration number reaches the number threshold. In this way, the LDPC decoder can more flexibly and efficiently select not to stop decoding early.

[0068] In combination Figure 4 For example, the overall flow of the method of the LDPC decoder for early stopping decoding in the embodiments of the present application is described.

[0069] Step S401: The LDPC controller obtains the data to be decoded from the flash memory and starts decoding.

[0070] Step S402: After the first decoding iteration processing ends, a first discriminant weight value is calculated.

[0071] Step S403: It is determined whether the first discriminant weight value is located in the interval of not stopping early; if yes, step S404 is executed; if no, step S405 is executed.

[0072] Step S404: The decoding iteration processing is continued until the iteration number reaches the number threshold.

[0073] Step S405: It is determined whether the first discriminant weight value is located in the interval of stopping early; if yes, step S408 (i.e., re-reading the flash memory and re-executing step S401) is executed; if no, it is not determined whether to trigger early stopping, and step S406 is continued to be executed.

[0074] Step S406: After the third decoding iteration processing ends, an original error bit number estimation value is calculated.

[0075] Step S407: It is determined whether the original error bit number estimation value is greater than the preset threshold; if yes, step S408 is executed; if no, step S409 is executed.

[0076] Step S408: It is confirmed that early stopping decoding is triggered, the flash memory is re-read, and step S401 is re-executed.

[0077] Step S409: It is confirmed that early stopping decoding is not triggered, and decoding is not stopped early; step S404 is continued to be executed.

[0078] In this embodiment of the application, through steps S401 to S409, the LDPC decoder can use the first discriminant weight value obtained at the end of the first decoding iteration as a reference to select whether to trigger the early termination decoding strategy based on the original error bit number estimation value; and when the early termination decoding strategy based on the original error bit number estimation value is triggered, the LDPC decoder can more flexibly and efficiently select whether to terminate decoding early.

[0079] Understandably, when the number of original error bits in the erroneous codeword is too large, the LDPC decoding operation needs to continue indefinitely to complete the decoding, which can easily cause the data path to become blocked. Therefore, the LDPC decoding algorithm generally uses a decoding termination strategy based on the upper limit of the decoding iteration number.

[0080] like Figure 5 As shown, the specific process of the decoding termination strategy based on the upper limit of the decoding iteration number is as follows:

[0081] Step S501: Obtain the data to be decoded from the flash memory.

[0082] Step S502: Perform one decoding iteration.

[0083] Step S503: Determine whether the calculation result of one decoding iteration satisfies the verification formula. If yes, the decoding is successful; otherwise, proceed to step S504.

[0084] Step S504: Determine if the maximum number of iterations has been reached. If yes, proceed to step S505. If no, return to step S502.

[0085] Step S505: If decoding fails, change the read threshold voltage parameter, reread the flash memory, and re-execute step S501. This process repeats until decoding is successful.

[0086] As can be seen from steps S501 to S505, the decoding process requires repeated iterative calculations, and the number of iterations required is roughly positively correlated with the number of original error bits in the data to be decoded. Figure 6As shown. It's understandable that when the number of original error bits exceeds the decoding capability limit of the LDPC module, the LDPC decoding operation needs to continue indefinitely to complete the decoding, which can easily cause the data path to become blocked. Therefore, the LDPC module needs to set an upper limit on the number of decoding iterations. However, setting an upper limit on the number of iterations only ensures that the LDPC module's data path does not become blocked. After an LDPC decoding failure, the flash memory controller still needs to change the read threshold voltage parameter to reread and decode again until successful. To further save the time consumed by multiple iterations of calculation in the LDPC decoder, the LDPC decoder introduces an early termination decoding strategy. During the decoding of each piece of data, if the number of error bits is predicted to be too high (low decoding success rate), the iteration calculation is terminated early, as shown below. Figure 7 As shown. Compared to Figure 6 , Figure 7 The flowchart shown differs in that step S506 is added between steps S503 and S504: determining whether the discriminant weights meet the early termination decoding condition. Specifically, if step S503 is executed and it is determined that the maximum number of iterations has not been reached, then step S506 is executed: determining whether the discriminant weights meet the early termination decoding condition. If yes, then step S505 is executed; otherwise, step S504 is continued. It is evident that the current early termination decoding strategy primarily determines whether to terminate decoding early by calculating whether the discriminant weights at a certain moment in LDPC decoding exceed a predetermined threshold, without involving the estimation of the original number of error bits. Furthermore, the numerical fluctuation of the discriminant weights in this early termination decoding strategy is significant, requiring complex control strategies and a long time to achieve accurate prediction.

[0087] It is understood that determining whether to prematurely terminate decoding at the end of the first iteration based on the interval of the discriminant weight value W1 at the end of the first iteration is an existing technique. The limitation of this technique is that the discriminant weight value W1 may be located in a transitional interval. When the discriminant weight value W1 is in a transitional interval, the probability of successful or failed decoding is relatively high (e.g., 50% success, 50% failure). In this case, directly terminating decoding may result in the loss of data that could have been successfully decoded, while not terminating decoding may waste decoding time. Therefore, the embodiments of this application can calculate the estimated number of original error bits at the end of the third iteration of decoding, and then determine whether to terminate decoding again based on the estimated number of original error bits; thus improving the accuracy of the decoding termination strategy.

[0088] The complete flowchart of the early termination decoding strategy based on the original error bit number estimation provided in the embodiments of this application is shown below. Figure 4 As shown, compared to Figure 7The early termination decoding strategy shown in the application embodiment does not depend on the discriminant weight, and is a new early termination decoding strategy which can be used as a supplement to the existing strategy. The early termination decoding strategy based on the original error bit number estimation value provided in the application embodiment makes the early termination decoding of the LDPC decoder more flexible and efficient.

[0089] The early termination decoding strategy based on the original error bit number estimation value of the application is further described as follows.

[0090] It can be understood that when decoding using an LDPC code, hard decision decoding is usually used first. If the hard decision decoding fails to reach the iteration upper limit, the read threshold voltage of the flash memory needs to be replaced for re-reading and re-hard decision decoding, or the soft decision decoding with stronger decoding capability needs to be switched to. Before soft decision decoding, the flash memory also needs to be re-read several times to obtain the necessary soft information for soft decision decoding. Since the iteration calculation of the LDPC and the time consumption of the flash memory re-reading operation are both relatively large, they have a great impact on the bandwidth of the system. Therefore, it is necessary to predict the failure probability of the current decoding in advance, and if the failure probability is high, the decoding operation is terminated in advance before reaching the iteration upper limit. The decoding failure probability of the LDPC is positively correlated with the original error bit number, and therefore the original error bit number estimation value is used as a reference quantity for determining whether to terminate the decoding in advance. Based on this, the application provides an original error bit number estimation formula.

[0091] According to some embodiments of the application, step S150 is further described as follows: step S150: performing original error bit number estimation processing according to the first bit inversion number, the second bit inversion number, and the third bit inversion number to obtain an original error bit number estimation value, including but not limited to steps S151 to S152.

[0092] Step S151: performing coefficient determination processing according to the first bit inversion number, the second bit inversion number, and the third bit inversion number to obtain a first coefficient, a second coefficient, and a third coefficient.

[0093] Step S152: performing calculation processing according to the first bit inversion number, the second bit inversion number, the third bit inversion number, the first coefficient, the second coefficient, and the third coefficient based on a preset estimation formula to obtain the original error bit number estimation value.

[0094] According to some embodiments of the present application, step S151 is further illustrated as follows: step S151: performing coefficient determination processing according to the first bit inversion number, the second bit inversion number, and the third bit inversion number to obtain the first coefficient, the second coefficient, and the third coefficient, including: determining a first target interval in which the first bit inversion number is located, and determining the first coefficient according to the first target interval; determining a second target interval in which the second bit inversion number is located, and determining the second coefficient according to the second target interval; determining a third target interval in which the third bit inversion number is located, and determining the third coefficient according to the third target interval.

[0095] For example, step S151 is further illustrated as follows: the intervals are divided in advance, and the corresponding coefficient values are set; if the first target interval in which the first bit inversion number b1 is located is 0-100, the corresponding first coefficient k1 is determined to be 0.8 based on the interval 0-100; if the second target interval in which the second bit inversion number b2 is located is 101-200, the corresponding second coefficient k2 is determined to be 0.9 based on the interval 101-200. Similarly, the third coefficient k3 can be obtained. It should be noted that there are various intervals obtained by dividing in advance, and there are various possibilities of setting corresponding coefficient values, which need to be based on the simulation experiment performed in advance to divide the intervals and set the coefficient values. The present application does not make specific limitations on the divided intervals and the coefficient values.

[0096] Although the early termination decoding strategy based on the original error bit number estimation value of the present application can be extrapolated to be performed at the end of the fourth or fifth or more iteration decoding processing. However, with the increase of the number of iterations, the subsequent iteration decoding processing has less effect on the prediction success rate, and the benefit is reduced. Therefore, the embodiments of the present application only judge whether to trigger the early termination decoding strategy based on the original error bit number estimation value at the end of the third iteration decoding processing; if the early termination decoding strategy based on the original error bit number estimation value is triggered, the decoding can be terminated early at the end of the third iteration decoding processing, and the effect is best.

[0097] According to some embodiments of the present application, step S152 is further illustrated as follows: the preset estimation formula is:

[0098] B E =k1b1+k2b2+k3b3; B E is the original error bit number estimation value; k1 is the first coefficient; k2 is the second coefficient; k3 is the third coefficient; b1 is the first bit inversion number, b2 is the second bit inversion number, and b3 is the third bit inversion number.

[0099] It can be understood that the original error bit number is an important indicator in the flash memory state, and has a guiding reference value for flash memory characteristic analysis. The flash memory characteristic analysis needs to collect the states of the flash memory in different use scenarios to better develop the software strategy of the flash memory controller.

[0100] In a conventional abort-decoding strategy based on an upper limit of the number of decoding iterations, when the LDPC decoding is successful, the total number of reversed bits is the original error bit number of the current error code word; when the LDPC decoding is stopped due to reaching the upper limit of the number of decoding iterations, the original error bit number of the current error code word cannot be directly obtained. In an abort-decoding strategy based on the discriminant weight, whether the discriminant weight of the LDPC decoding at a certain moment exceeds a predetermined threshold is mainly used to determine whether to abort the decoding in advance, and the estimation of the original error bit number is not involved. The embodiment of the present application can estimate the original error bit number of the data input into the LDPC module by using the number of reversed bits after the first three rounds of iterative decoding of the LDPC code to obtain the estimated value of the original error bit number. Similarly, the embodiment of the present application can estimate the original error bit number of the data input into the LDPC module by using the number of reversed bits after each round of iterative decoding of the LDPC module through the preset estimation formula.

[0101] The embodiment of the present application can quickly calculate the estimated value of the original error bit number through steps S151 to S152, and provide a reliable reference for subsequent execution of the abort-decoding strategy.

[0102] The embodiment of the present application also provides an electronic device comprising the LDPC decoder.

[0103] The embodiment of the present application also provides a storage medium, which is a computer-readable storage medium. The storage medium stores a computer program, and the computer program is executed by a processor to implement the abort-decoding method of the LDPC decoder.

[0104] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory can include a high-speed random access memory and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some embodiments, the memory can optionally include a memory disposed remotely with respect to the processor, which can be connected to the processor through a network. Examples of the above network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The above-described device embodiments are merely illustrative, and units described as separate components can or can not be physically separated, implemented in one place, or can also be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the present embodiment.

[0105] Those of ordinary skill in the art can understand that all or some steps in the above disclosed method and system can be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on a computer readable medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, as known to those of ordinary skill in the art, communication media generally includes computer readable instructions, data structures, program modules or other data in modulated data signals such as carrier waves or other transport mechanisms, and can include any information delivery medium.

[0106] The above is a specific description of the preferred embodiments of the present application, but the present application is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the present application, and these equivalent modifications or replacements are all included in the scope defined by the present application.

Claims

1. A method of early aborting decoding of an LDPC decoder, the method comprising: The method applied to the LDPC decoder comprises: obtaining to-be-decoded data from a flash memory; performing multiple decoding iteration processes on the to-be-decoded data, and obtaining a corresponding error code word at the end of each decoding iteration process; calculating the to-be-decoded data and the error code word obtained at the end of each decoding iteration process based on a preset bit reversal number calculation formula to obtain a bit reversal number at the end of each decoding iteration process; when the first discriminant weight value obtained at the end of the first decoding iteration process is located in a preset transition interval and the third decoding iteration process ends, obtaining a first bit reversal number at the end of the first decoding iteration process, a second bit reversal number at the end of the second decoding iteration process, and a third bit reversal number at the end of the third decoding iteration process; performing original error bit number estimation processing according to the first bit reversal number, the second bit reversal number, and the third bit reversal number to obtain an original error bit number estimation value; when the original error bit number estimation value is greater than a preset threshold, prematurely terminating the decoding and performing a flash memory re-reading operation.

2. The method of early aborting decoding of an LDPC decoder according to claim 1, wherein, The preset bit reversal number calculation formula is: wherein b n is the estimated number of bit flips at the end of each decoding iteration; HW() is a Hamming weight calculation function; is an XOR operation; v0is the data to be decoded; v n is the error code word obtained at the end of the n-th decoding iteration.

3. The method of early aborting decoding of an LDPC decoder according to claim 1, wherein, The original error bit number estimation processing according to the first bit reversal number, the second bit reversal number, and the third bit reversal number to obtain an original error bit number estimation value comprises: performing coefficient determination processing according to the first bit reversal number, the second bit reversal number, and the third bit reversal number to obtain a first coefficient, a second coefficient, and a third coefficient; performing calculation processing according to the first bit reversal number, the second bit reversal number, the third bit reversal number, the first coefficient, the second coefficient, and the third coefficient based on a preset estimation formula to obtain the original error bit number estimation value.

4. The method of early aborting decoding of an LDPC decoder according to claim 3, wherein, The coefficient determination processing according to the first bit reversal number, the second bit reversal number, and the third bit reversal number to obtain a first coefficient, a second coefficient, and a third coefficient comprises: determining a first target interval in which the first bit reversal number is located, and determining the first coefficient according to the first target interval; determining a second target interval in which the second bit reversal number is located, and determining the second coefficient according to the second target interval; determining a third target interval in which the third bit reversal number is located, and determining the third coefficient according to the third target interval.

5. The method of early aborting decoding of an LDPC decoder according to claim 3, wherein, The preset estimation formula is: B E = k1b1 + k2b2 + k3b3;B E is the original error bit number estimate; k1 is the first coefficient; k2 is the second coefficient; k3 is the third coefficient; b1 is the first bit inversion number, b2 is the second bit inversion number, b3 is the third bit inversion number.

6. The method of early aborting decoding of an LDPC decoder according to claim 1, wherein, After obtaining the original error bit number estimation value, the method further comprises: when the original error bit number estimation value is less than or equal to a preset threshold, not prematurely terminating the decoding; continuing the decoding iteration process until the number of iterations reaches a number threshold.

7. The method of early aborting decoding of an LDPC decoder according to claim 1, wherein, The method further comprises: when the first discriminant weight value obtained at the end of the first decoding iteration process is located in a preset determined premature termination interval, prematurely terminating the decoding and performing a flash memory re-reading operation; when the first discriminant weight value obtained at the end of the first decoding iteration process is located in a preset determined non-premature termination interval, continuing the decoding iteration process until the number of iterations reaches a number threshold.

8. An LDPC decoder, characterized in that, comprises: The data acquisition unit is configured to acquire to-be-decoded data from the flash memory. The iteration calculation unit is configured to perform multiple decoding iteration processes on the to-be-decoded data, and obtain a corresponding error code word at the end of each decoding iteration process. The bit inversion number calculation unit is configured to calculate the to-be-decoded data and the error code word obtained at the end of each decoding iteration process based on a preset bit inversion number calculation formula, and obtain a bit inversion number at the end of each decoding iteration process. The original error bit number estimation unit is configured to, when the first discriminant weight value obtained at the end of the first decoding iteration process is located in a preset transition interval and the third decoding iteration process ends, acquire a first bit inversion number obtained at the end of the first decoding iteration process, a second bit inversion number obtained at the end of the second decoding iteration process, and a third bit inversion number obtained at the end of the third decoding iteration process; and perform original error bit number estimation processing based on the first bit inversion number, the second bit inversion number, and the third bit inversion number to obtain an original error bit number estimation value. The decoding termination control unit is configured to terminate the decoding in advance when the original error bit number estimation value is greater than a preset threshold.

9. An electronic device, comprising: The LDPC decoder includes the LDPC decoder as claimed in claim 8.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer executable instructions for causing a computer to execute the method for early termination of decoding of the LDPC decoder as claimed in any one of claims 1 to 7.

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