Optical fiber main and standby non-inductive switching protection method based on FPGA

Abstract

The invention discloses an optical fiber main and standby non-inductive switching protection method based on an FPGA. The method comprises the following steps that S1, a fault detection module is installed; s2, setting a buffer area; s3, emergency switching: after the fault detection module triggers a switching mechanism triggering condition, starting a switching mechanism, immediately adjusting output by the FPGA control unit, and switching to a standby channel to continue to receive the video data; s4, synchronization and recovery: after the switching is completed, the FPGA control unit keeps the synchronization and integrity of the video data through the technical means of timestamps and frame counting; and S5, data decoding and displaying: decoding the received data, and displaying the decoded data on a front-end display screen through an HDMI (High Definition Multimedia Interface). According to the application, the fault detection module and the FPGA control unit are arranged, so that the state of the data transmission channel is detected at any time, and after the switching condition is triggered, the transmission channel can be replaced in real time, and the problems of black screen, splash screen and the like are avoided.

Description

Technical Field

[0001] This application belongs to the technical field of video transmission, and particularly relates to a fiber optic primary and standby seamless switching protection method based on FPGA. Background Art

[0002] With the development of video transmission technology, fiber optic communication has been rising day by day. Fiber optic communication has the advantages of high bandwidth, anti-electromagnetic interference, long transmission distance, small size, low price, etc., and is very suitable for the miniaturization and integration design optimization of infrared imaging devices. At the same time, it is used in various complex application environments such as missile-borne, airborne, and vehicle-borne.

[0003] Field Programmable Gate Array (FPGA) is a programmable logic device based on lookup table technology. It is a further developed product based on programmable devices such as PAL, GAL, and CPLD. It appears as a semi-custom circuit in the field of Application Specific Integrated Circuit (ASIC). It not only solves the deficiencies of custom circuits but also overcomes the shortcomings of limited gate circuits in the original programmable devices. It consists of several independent programmable logic blocks. Users can flexibly implement extremely complex circuit functions inside it through Hardware Description Language (HDL) and dedicated design tools, and it is suitable for the field of high-speed and high-density sequential logic circuit design.

[0004] The prior art discloses a video signal transmission method, storage medium, and smart TV based on FPGA. The method includes: a first FPGA module connected to the TV end receives a video signal sent by the TV end and obtains the signal type of the video signal; when the signal type of the video signal is the first signal type, synchronize the video signal into first multiple-channel parallel data, convert the first multiple-channel parallel data into a first optical signal, and transmit the first optical signal to the screen end connected with a second FPGA module through an optical fiber. The present invention converts the video signal output by the TV end into an optical fiber signal through the first FPGA module, and then converts the optical fiber signal into video information through the second FPGA module and transmits it to the screen end, thereby realizing the optical fiber transmission between the TV end and the screen end.

[0005] In the existing video transmission system, an HDMI interface is usually used as the sending end and the receiving end, and the video signal is transmitted through an optical fiber. However, when a device at one end fails, the front display screen often shows a black screen or a flashing screen phenomenon, seriously affecting the user experience. To solve this problem, the present invention proposes a fiber optic primary and standby seamless switching protection method based on FPGA. Summary of the Invention

[0006] This application provides a fiber optic primary and standby seamless switching protection method based on FPGA, aiming to solve the problems of black screen and flashing screen caused by equipment failure at one end during video transmission in the prior art.

[0007] A fiber optic primary and standby seamless switching protection method based on FPGA, the method comprising the following steps:

[0008] S1: Install a fault detection module: Set up fault detection modules at the sending end and the receiving end respectively to monitor the status of the fiber optic channel in real time, and set the trigger conditions for the switching mechanism. Once a main fiber optic channel fault is detected, the switching mechanism is immediately activated;

[0009] S2: Set up a buffer: The FPGA control unit pre-caches a certain length of video data in the internal RAM or external memory as a switching buffer;

[0010] S3: Emergency switching: After the fault detection module triggers the trigger conditions for the switching mechanism, the switching mechanism is activated, and the FPGA control unit immediately adjusts the output and switches to the standby channel to continue receiving video data;

[0011] S4: Synchronization and recovery: After the switching is completed, the FPGA control unit maintains the synchronization and integrity of the video data through technical means such as timestamps and frame counts;

[0012] S5: Data decoding and display: The received data is decoded and then displayed on the front-end display screen through the HDMI interface.

[0013] In the above solution, optionally, the trigger conditions include: a fault detection threshold and a switching delay time.

[0014] In the above solution, optionally, the fault detection threshold includes: a signal quality threshold, a performance parameter threshold, a time-related threshold, and a comprehensive judgment threshold.

[0015] In the above solution, optionally, the output steps of the emergency switching include:

[0016] S3.1: The switching mechanism switches the transmission path of the video data from the main transmission channel to the backup transmission channel;

[0017] S3.2: The FPGA control unit buffers the video data using the buffer.

[0018] In the above solution, optionally, the steps to achieve video data synchronization include:

[0019] S4.1: At the sending end, each frame of video data is attached with a timestamp to mark the specific sending time of the frame data;

[0020] S4.2: Record the current number of frames being transmitted at the sending end and the receiving end respectively;

[0021] S4.3: After triggering the channel switch, match the received video data with the timestamps to ensure that each frame of data can be corresponding to the correct time point;

[0022] S4.4: Adjust the decoding progress according to the latest frame count information to ensure consistency with the number of frames at the sending end.

[0023] In the above solution, optionally, the FPGA-based fiber optic primary and standby seamless switching protection method further includes:

[0024] Backup transmission channel status monitoring: After the switching is completed, the logic control unit will continue to monitor the status information of the backup transmission channel. When the backup transmission channel also fails, the FPGA control unit will attempt other recovery measures.

[0025] In the above solution, optionally, other recovery measures include: restarting the system, alarming, and switching to another standby transmission channel.

[0026] In the above solution, optionally, the FPGA-based fiber optic primary and standby seamless switching protection method further includes:

[0027] When the fault of the primary transmission channel is repaired, the logic control unit will re-enable the primary transmission channel to transmit video data and monitor the primary transmission channel again.

[0028] Compared with the prior art, the present application has at least the following beneficial effects:

[0029] By setting up a fault detection module and an FPGA control unit, the present application enables the status of the data transmission channel to be detected at all times, and can replace the transmission channel in real time after the switching condition is triggered, avoiding problems such as black screens and flashing screens.

[0030] In order to ensure the continuity and stability of video data before and after switching, the FPGA control unit will buffer and process the video data during the switching process. When the primary transmission channel fails, the FPGA control unit will immediately read the video data from the buffer for transmission until the backup transmission channel is stable and then start transmitting new video data. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the application environment of an FPGA-based fiber optic primary and standby seamless switching protection method provided by an embodiment of the present application.

[0032] Figure 2 It is a schematic flowchart of an FPGA-based fiber optic primary and standby seamless switching protection method provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] In order to make the purpose, technical solution and advantages of this application clearer and more understandable, the following further elaborates on this application in combination with the accompanying drawings and embodiments.

[0034] A fiber optic primary and standby non-intrusive switching protection method based on FPGA provided by this application can be applied to an application environment as Figure 1 shown. Among them, it includes a primary and standby fiber optic channel: one fiber is used as the primary channel, and several fibers are used as standby channels; an FPGA control unit: the primary and standby fiber optic channels are uniformly managed and scheduled through the FPGA control unit, and the FPGA control unit monitors the status of the primary and standby fiber optic channels in real time; a video encoding and decoding module: video encoding and decoding modules are respectively set at the sending end and the receiving end to convert the input video signal into a data format suitable for fiber optic transmission.

[0035] In one embodiment, referring to Figure 2 , a fiber optic primary and standby non-intrusive switching protection method based on FPGA is provided. Taking the application of this method to the environment in Figure 1 as an example for illustration, it includes the following steps:

[0036] S1: Install a fault detection module: Fault detection modules are respectively set at the sending end and the receiving end to monitor the status of the fiber optic channel in real time and set the trigger conditions for the switching mechanism. Once a fault in the primary fiber optic channel is detected, the switching mechanism is immediately activated. The trigger conditions include: a fault detection threshold, a switching delay time, where the fault detection threshold includes: a signal quality threshold, a performance parameter threshold, a time-related threshold, and a comprehensive judgment threshold;

[0037] S2: Set up a buffer: The FPGA control unit pre-caches a certain length of video data in the internal RAM or external memory as a switching buffer;

[0038] S3: Emergency switching: After the fault detection module triggers the trigger conditions for the switching mechanism, the switching mechanism is activated. The FPGA control unit immediately adjusts the output to ensure that data is sent to the standby channel simultaneously. In this way, even if there is a problem with the primary channel, video transmission can still continue. At the same time, when receiving data, the receiving end selects to receive data from the standby channel through the FPGA control unit. Once a fault in the primary channel is detected, it automatically switches to the standby channel to continue receiving video data. At the same time, the FPGA control unit at the receiving end will maintain the synchronization and integrity of the video data to ensure normal display on the front-end display screen;

[0039] And a smaller label of the transmission channel will be displayed at the display end to be able to remind the sending end that a fault has occurred during the transmission process for timely repair after the non-intrusive switching is completed. The label reminder can be selected to be always on or briefly displayed after the switching;

[0040] To ensure the continuity and stability of video data before and after switching, the FPGA buffers and processes the video data during the switching process. When the primary transmission channel fails, the FPGA immediately reads the video data from the buffer for transmission until the backup transmission channel stabilizes and starts transmitting new video data;

[0041] Among them, the steps of emergency switching output include:

[0042] S3.1: The switching mechanism switches the transmission path of the video data from the primary transmission channel to the backup transmission channel;

[0043] S3.2: The FPGA control unit uses the buffer to buffer the video data to prevent data loss or interruption.

[0044] S4: Synchronization and recovery: After the switching is completed, the FPGA control unit maintains the synchronization and integrity of the video data through technical means such as timestamps and frame counts to ensure that the front-end display screen does not go black or freeze during the switching process;

[0045] Specifically, the steps to achieve video data synchronization include:

[0046] S4.1: At the sending end, each frame of video data is attached with a timestamp to mark the specific sending time of the frame data. Based on these timestamps, the receiving end can accurately map the data frames to the correct playback time;

[0047] S4.2: Record the current number of frames being transmitted at the sending end and the receiving end respectively. When a channel switch occurs, the receiving end adjusts the decoding progress according to the latest frame count information to ensure consistency with the number of frames at the sending end;

[0048] S4.3: After triggering the channel switch, match the received video data with the timestamps to ensure that each frame of data can be mapped to the correct time point;

[0049] S4.4: Adjust the decoding progress according to the latest frame count information to ensure consistency with the number of frames at the sending end;

[0050] S5: Data decoding and display: The received data is decoded and then displayed on the front-end display screen through the HDMI interface. The entire process requires no manual intervention, achieving a truly seamless switch.

[0051] The FPGA-based fiber optic primary and backup seamless switching protection method further includes:

[0052] Backup transmission channel status monitoring: After the switching is completed, the logic control unit will continue to monitor the status information of the backup transmission channel. When the backup transmission channel also fails, the FPGA control unit will attempt other recovery measures, such as restarting the system, alarming, switching to another backup transmission channel, etc.;

[0053] When the fault of the main transmission channel is repaired, the logic control unit will re-enable the main transmission channel to transmit video data and monitor the main transmission channel again to ensure the stability and reliability of the system.

[0054] The FPGA control unit is configured with:

[0055] Programmable Logic Unit (PLU): As the most basic building block of the FPGA, it is responsible for implementing various logic functions. It usually includes key components such as Look-Up Table (LUT) and Register;

[0056] 1. Look-Up Table (LUT): The LUT is the main component in the FPGA for implementing combinational logic functions. It is similar to a ROM, which looks up and outputs corresponding data through the input address. In the FPGA, the inputs of the LUT are usually used as address lines, and the outputs are used to implement specific logic functions. For example, a 6-input LUT can implement 64 different logic combinations.

[0057] 2. Register: Registers in the FPGA are used to store data and can update their values when triggered by the clock edge. They are usually used together with the LUT to implement synchronous sequential logic design;

[0058] Configurable Logic Block (CLB): The CLB is a larger logic function unit in the FPGA, which consists of multiple programmable logic units (such as LUT and register) and additional connection and control resources. The CLB can be configured to implement various complex logic functions, such as adders, multipliers, etc.;

[0059] Embedded Block RAM: The FPGA usually contains embedded Block RAMs for storing data and programs. These Block RAMs can be configured as single-port RAM, dual-port RAM, pseudo-dual-port RAM, Content Addressable Memory (CAM), and FIFO storage structures. The presence of Block RAM enables the FPGA to efficiently process large amounts of data and quickly access this data when needed;

[0060] Routing Resources: The routing resources are the "wires" that connect various logic units and modules inside the FPGA. They are responsible for transmitting signals from one logic unit to another, thus realizing the interconnection of the entire FPGA. The optimization of routing resources is crucial for the performance and power consumption of the FPGA;

[0061] Underlying Embedded Functional Units: The FPGA contains some underlying embedded functional units, such as Phase Locked Loops (PLLs), Digital Clock Managers (DCMs), multipliers, etc. These functional units provide additional clock management, signal processing, and data operation capabilities, enabling the FPGA to be applicable to a wider range of application scenarios;

[0062] Programmable Input / Output Blocks (IOBs): IOBs are the interfaces between the FPGA and external circuits, responsible for signal input and output. They are usually programmable and can adapt to different electrical standards and I / O physical characteristics. For example, IOBs can be configured to support interface standards such as LVTTL, LVCMOS, PCI, and LVDS.

[0063] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

Claims

1. A fiber optic master-slave non-sensing switching protection method based on FPGA, characterized in that: The method comprises the following steps: S1: Install fault detection module: Fault detection modules are installed at both the sending end and the receiving end to monitor the status of the fiber channel in real time and set the triggering conditions of the switching mechanism. Once a fault in the main fiber channel is detected, the switching mechanism is immediately started; S2: Set up a buffer: The FPGA control unit pre-caches the video data in the internal RAM or external memory as a switching buffer; S3: Emergency switching: After the fault detection module triggers the switching mechanism triggering condition, the switching mechanism is started, and the FPGA control unit immediately adjusts the output and switches to the backup channel to continue receiving video data; S4: Synchronization and recovery: After the switching is completed, the FPGA control unit maintains the synchronization and integrity of the video data through timestamps and frame counts; S5: Data decoding and display: After being decoded, the received data is displayed on the front-end display screen through the HDMI interface.

2. The FPGA-based optical fiber active / standby non-sensing switching protection method according to claim 1 is characterized in that: The switching mechanism triggering conditions include: a fault detection threshold and a switching delay time.

3. The FPGA-based optical fiber active / standby non-sensing switching protection method according to claim 2 is characterized in that: The fault detection thresholds include: a signal quality threshold, a performance parameter threshold, a time-related threshold, and a comprehensive judgment threshold.

4. The FPGA-based optical fiber active / standby non-sensing switching protection method according to claim 1 is characterized in that: The output step of the emergency switching includes: S3.1: The switching mechanism switches the transmission path of the video data from the main transmission channel to the backup transmission channel; S3.2: The FPGA control unit uses the buffer to buffer the video data.

5. The FPGA-based optical fiber active / standby non-sensing switching protection method according to claim 1 is characterized in that: The steps of realizing the video data synchronization include: S4.1: At the sending end, each frame of video data is accompanied by a timestamp to mark the specific sending time of each frame of video data; S4.2: Record the number of frames currently transmitted at the sending end and the receiving end respectively; S4.3: After the channel switching is triggered, the received video data is matched with the timestamp to ensure that each frame of data corresponds to the correct time point; S4.4: Adjust the decoding progress according to the latest frame count information to ensure that the frame count is consistent with that of the sender.

6. The FPGA-based optical fiber active / standby non-sensing switching protection method according to claim 1, characterized in that: The method further comprises: Backup transmission channel status monitoring: After the switch is completed, the logic control unit will continue to monitor the status information of the backup transmission channel. When the backup transmission channel also fails, the FPGA control unit will try other recovery measures.

7. The FPGA-based optical fiber active / standby non-sensing switching protection method according to claim 6 is characterized in that: The other recovery measures include: restarting the system, issuing an alarm, and switching to another backup transmission channel.

8. The FPGA-based optical fiber active / standby non-sensing switching protection method according to claim 6 is characterized in that: The method further comprises: When the fault of the main transmission channel is repaired, the logic control unit will re-enable the main transmission channel to transmit video data and monitor the main transmission channel again.

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