Thin film transistor substrate and display device using the same

Abstract

Disclosed are a thin film transistor substrate and a display device including the same. The thin film substrate includes a substrate; a buffer layer having a buffer groove, the buffer layer being disposed on the substrate, where the buffer groove includes an inclined surface; an active layer disposed on the buffer layer; and a gate electrode disposed on the active layer, in which the active layer is disposed in a stepped shape on the buffer groove, and one end of the gate electrode overlaps an inclined surface of the buffer groove.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2023 - 0191622, filed on December 26, 2023, which is incorporated herein by reference in its entirety as if fully set forth herein. Technical field

[0003] The present disclosure relates to a thin - film transistor substrate and a display device using the thin - film transistor substrate. Background art

[0004] Since thin - film transistors can be fabricated on glass or plastic substrates, they are widely used as switching or driving elements in display devices such as liquid - crystal display devices or organic - light - emitting devices.

[0005] Various types of thin - film transistors, such as driving thin - film transistors for emitting respective pixels, switching thin - film transistors for adjusting the amount of voltage applied to the driving thin - film transistors, logic GIP thin - film transistors for controlling thin - film transistors disposed in a display area, and buffer GIP thin - film transistors for controlling the total power supply, can be used in a display panel for driving an organic - light - emitting device (OLED).

[0006] To implement a device with high mobility, in a thin - film transistor having a top - gate structure, a process of making an oxide semiconductor layer conductive can be performed by using a gate electrode as a mask. However, during the process of making the oxide semiconductor layer conductive, the conductive region may be over - penetrated, so that the channel region may be formed smaller than the set region. Therefore, the channel length may be reduced and the threshold voltage Vth may shift in the negative (-) direction. In particular, when the width of the oxide semiconductor layer is large, the degree of penetration of the region to be made conductive may increase, whereby the channel length may be further shortened.

[0007] When the threshold voltage Vth shifts in the negative (-) direction, leakage current may occur in an initial image. As a result, a display panel including the thin - film transistor may be poorly driven due to the leakage current, and a problem of increased power consumption of the panel may occur. Summary of the invention

[0008] The present disclosure has been made in view of the above problems, and an object of the present disclosure is to provide a thin - film transistor substrate in which an active layer is disposed on a buffer groove provided in a buffer layer, thereby preventing deep penetration of oxygen vacancies diffused into the channel of the active layer during the conductive process, thereby preventing a negative shift of the threshold voltage Vth of the thin - film transistor, and a display device including the thin - film transistor substrate.

[0009] According to one aspect of the present disclosure, the above and other objects can be achieved by providing a thin film transistor substrate and a display device including the thin film transistor substrate. The thin film transistor substrate includes a substrate, a buffer layer having buffer grooves disposed on the substrate, wherein the buffer grooves include inclined surfaces, an active layer disposed on the buffer layer, and a gate electrode disposed on the active layer. The active layer is disposed in a stepped manner on the buffer grooves, and one end of the gate electrode overlaps with the inclined surface of the buffer grooves.

[0010] In one aspect, one end of the gate electrode may overlap with a part of the active layer disposed on the inclined surface of the buffer grooves.

[0011] In another aspect, the thin film transistor substrate may further include: a gate insulating layer disposed between the active layer and the gate electrode, wherein the gate insulating layer overlaps with the buffer grooves, and one end of the gate insulating layer corresponds to one end of the gate electrode.

[0012] In still another aspect, the thin film transistor substrate may further include: a gate insulating layer disposed between the active layer and the gate electrode, wherein the gate insulating layer overlaps with the buffer grooves, and one end of the gate insulating layer is disposed between one end of the active layer and one end of the gate electrode.

[0013] In another aspect, the gate insulating layer may have a first width, the gate electrode may have a second width, the active layer may have a first length, and the first width of the gate insulating layer is greater than the second width of the gate electrode and less than the first length of the active layer.

[0014] In still another aspect, the active layer may include a channel portion, a connection portion disposed on one side of the channel portion, and a diffusion portion disposed between the channel portion and the connection portion, and the channel portion may include a first region in contact with the bottom surface of the buffer grooves and a second region in contact with the inclined surface of the buffer grooves.

[0015] In another aspect, one end of the second region of the channel portion may be disposed in the inclined surface.

[0016] In still another aspect, one end of the second region of the channel portion may correspond to one end of the gate electrode.

[0017] In another aspect, one end of the diffusion portion may be disposed on the inclined surface of the buffer grooves.

[0018] In another aspect, the other end of the diffusion portion may correspond to one end of the gate electrode.

[0019] In yet another aspect, the other end of the diffusion portion may be disposed between one end of the gate electrode and one end of the active layer.

[0020] In another aspect, the active layer may include a channel portion, a connection portion disposed on one side of the channel portion, and a diffusion portion disposed between the channel portion and the connection portion. One end of the channel portion may be disposed on the bottom surface of the buffer groove, and one end of the diffusion portion may be disposed on the inclined surface of the buffer groove. One end of the channel portion and one end of the diffusion portion may be in contact with each other at the boundary between the bottom surface of the buffer groove and the inclined surface of the buffer groove.

[0021] In yet another aspect, the buffer groove may further include a bottom surface connected to the inclined surface, and an angle formed between the bottom surface and the inclined surface may be equal to or greater than 30 degrees and equal to or less than 45 degrees.

[0022] In another aspect, the buffer groove may further include a bottom surface connected to the inclined surface, and a depth of the bottom surface of the buffer groove may be equal to or greater than 1.41 μm and equal to or less than 2 μm.

[0023] Furthermore, the above and other objects can be achieved by providing a thin film transistor substrate and a display device including the thin film transistor substrate. The thin film transistor substrate includes a substrate, a buffer layer having a buffer groove, the buffer layer being disposed on the substrate, an active layer disposed on the buffer layer, and a gate electrode disposed on the active layer. Wherein, the buffer groove includes a bottom surface and an inclined surface connected to the bottom surface, the active layer includes a channel portion, a connection portion disposed on one side of the channel portion, and a diffusion portion disposed between the channel portion and the connection portion, and the channel portion overlaps with the bottom surface and the inclined surface, and one end of the channel portion is disposed on the inclined surface of the buffer groove.

[0024] A width of the bottom surface of the buffer groove may be smaller than a width of the gate electrode, and a width of the entire bottom surface and the inclined surface of the buffer groove may be greater than the width of the gate electrode.

[0025] The thin film transistor substrate may further include: a gate insulating layer disposed between the active layer and the gate electrode, wherein an entire region of the diffusion portion overlaps with the gate insulating layer.

[0026] A part of the diffusion portion may not overlap with the gate electrode.

[0027] One end of the channel portion may correspond to one end of the gate electrode. Description of the Drawings

[0028] The above and other objects, features, and other advantages of the present disclosure will be more clearly understood from the following specific embodiments in conjunction with the accompanying drawings, where:

[0029] Figure 1 is a plan view of a thin film transistor substrate according to an embodiment of the present disclosure.

[0030] Figure 2A is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present disclosure. In this case, Figure 2A corresponds to Figure 1 cross-sectional view I-I'.

[0031] Figure 2B is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Figure 2B corresponds to Figure 1 cross-sectional view I-I'.

[0032] Figure 3A and 3B are schematic views showing cross-sections of a thin film transistor substrate according to an embodiment of the present disclosure and a thin film transistor substrate according to a comparative example, respectively.

[0033] Figure 3C is a carrier concentration graph of the distance of the diffusion part of a thin film transistor substrate according to an embodiment of the present disclosure and a thin film transistor substrate according to a comparative example.

[0034] Figures 4A to 4E is a cross-sectional view of a process for manufacturing a thin film transistor substrate according to an embodiment of the present disclosure.

[0035] Figure 5 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Figure 5 corresponds to Figure 1 cross-sectional view I-I'.

[0036] Figures 6A to 6F is a cross-sectional view of a process for manufacturing a thin film transistor substrate according to another embodiment of the present disclosure.

[0037] Figure 7 is a cross-sectional view of a display device including a thin film transistor substrate according to an embodiment of the present disclosure.

[0038] Figure 8 is a schematic view of a display device according to an embodiment of the present disclosure.

[0039] Figure 9It is a circuit diagram of a pixel included in a display device according to an embodiment of the present disclosure. Detailed implementation

[0040] Through the following embodiments described with reference to the accompanying drawings, the advantages and features of the present disclosure and their implementation methods will be clarified. However, the present disclosure can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is only defined by the scope of the claims.

[0041] The shapes, sizes, ratios, angles, and quantities used to describe the embodiments of the present disclosure disclosed in the drawings are merely examples, so the present disclosure is not limited to the details shown. The same reference numerals always denote the same elements. In the following description, when the detailed description of related known functions or configurations is determined to unnecessarily obscure the focus of the present disclosure, the detailed description will be omitted.

[0042] In the case of using "including", "having", and "containing" described in this specification, unless "only" is used, there may also be another part. Unless otherwise stated, terms in the singular form may include the plural form.

[0043] When interpreting an element, the element is interpreted as including an error region even though it is not explicitly described.

[0044] When describing positional relationships, for example, when the positional order is described as "on", "above", "below", "beneath", and "next", unless "just" or "directly" is used, cases where there is no contact between them may be included.

[0045] If it is mentioned that the first element is positioned "on" the second element, this does not mean that the first element is substantially positioned above the second element in the drawing. The upper and lower parts of the object involved may change according to the orientation of the object. Therefore, in the drawing or in the actual configuration, the case where the first element is positioned "on" the second element includes the case where the first element is positioned "below" the second element and the case where the first element is positioned "above" the second element.

[0046] When describing temporal relationships, for example, when the temporal order is described as "after", "subsequently", "next", and "before", unless "just" or "directly" is used, discontinuous cases may be included.

[0047] It should be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0048] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of the first element, the second element, and the third element" may include two or more elements selected from the first element, the second element, and the third element, as well as all combinations of each of the first element, the second element, and the third element.

[0049] The features of various embodiments of the present disclosure may be partially or fully coupled or combined with each other, and may operate differently from each other and be technically driven. The embodiments of the present disclosure may be executed independently of each other, or may be executed together in a mutually dependent relationship.

[0050] In the drawings, the same or similar elements are denoted by the same reference numerals, even if they are shown in different drawings.

[0051] In an embodiment of the present disclosure, for ease of explanation, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode may be used interchangeably. Thus, the source electrode may be the drain electrode, and the drain electrode may be the source electrode. In addition, the source electrode in any one embodiment of the present disclosure may be the drain electrode in another embodiment of the present disclosure, and the drain electrode in any one embodiment of the present disclosure may be the source electrode in another embodiment of the present disclosure.

[0052] In one or more embodiments of the present disclosure, for ease of explanation, the source region is distinguished from the source electrode, and the drain region is distinguished from the drain electrode. However, the embodiments of the present disclosure are not limited to this structure. For example, the source region may be the source electrode, and the drain region may be the drain electrode. In addition, the source region may be the drain electrode, and the drain region may be the source electrode.

[0053] Figure 1 is a plan view of a thin film transistor substrate according to an embodiment of the present disclosure.

[0054] As Figure 1 shown, a thin film transistor substrate according to an embodiment of the present disclosure may include a buffer layer 110, an active layer 120, a gate electrode 140, a source electrode 161, and a drain electrode 162.

[0055] The active layer 120 may extend in a first direction (e.g., in a horizontal direction). The source electrode 161 may be disposed on one side of the active layer 120, e.g., on the left side, and the drain electrode 162 may be disposed on the other side of the active layer 120, e.g., on the right side.

[0056] The gate electrode 140 may extend in a second direction (e.g., a vertical direction). In this case, the second direction may correspond to a direction perpendicular to the first direction. The gate electrode 140 overlaps the active layer 120.

[0057] The source electrode 161 may be electrically connected to one side of the active layer 120 through a first contact hole CH1, and the drain electrode 162 may be electrically connected to the other side of the active layer 120 through a second contact hole CH2.

[0058] According to an embodiment of the present disclosure, the buffer layer 110 may be formed on the entire surface of the thin film transistor substrate according to an embodiment of the present disclosure to overlap the active layer 120, the gate electrode 140, the source electrode 161, and the drain electrode 162. In this case, since the buffer groove BG is provided in the buffer layer 110, the length of the channel portion provided in the active layer 120 can be prevented from being excessively shortened, which will be described in detail below with reference to Figure 2A Detailed description.

[0059] The buffer groove BG may overlap the active layer 120 and the gate electrode 140 in a region where the active layer 120 and the gate electrode 140 overlap each other. In this case, the buffer groove BG may have a first width W in the horizontal direction BG , the gate electrode 140 may have a second width W in the horizontal direction GE , and the active layer 120 may have a first length L in the horizontal direction ACT .

[0060] According to an embodiment of the present disclosure, the first width W of the buffer groove BG BG may be formed to be greater than the second width W of the gate electrode 140 GE , and the first width W of the buffer groove BG BG may be formed to be less than the first length L of the active layer 120 ACT .

[0061] Figure 2A is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present disclosure. In this case, Figure 2A corresponds to Figure 1 Cross-sectional view I-I'.

[0062] As Figure 2AAs shown, the thin film transistor substrate according to an embodiment of the present disclosure may include a substrate 100, a buffer layer 110, an active layer 120, a gate insulating layer 130, a gate electrode 140, an interlayer insulating layer 150, a source electrode 161, and a drain electrode 162.

[0063] The substrate 100 may be made of glass or plastic. In particular, the substrate 100 may be made of a transparent plastic having flexible characteristics, such as polyimide. When polyimide is used as the substrate 100, considering the high-temperature deposition process performed on the substrate 100, heat-resistant polyimide capable of withstanding high temperatures may be used.

[0064] The buffer layer 110 may be formed on the substrate 100. The buffer layer 110 may protect the active layer 120 by blocking air and moisture. The buffer layer 110 may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or metal oxide, but is not limited thereto, and may be made of an organic insulating material.

[0065] According to an embodiment of the present disclosure, the buffer layer 110 may be provided with a buffer groove BG formed recessed from the upper surface US of the buffer layer 110. The buffer groove BG is formed by removing a partial region of the upper surface of the buffer layer 110.

[0066] The buffer groove BG includes a bottom surface BS provided at a portion deepest from the upper surface US of the buffer layer 110, and an inclined surface IS connected to the bottom surface BS and forming a first angle θ1 with the bottom surface.

[0067] The first angle θ1 formed by the bottom surface BS and the inclined surface IS of the buffer groove BG may be equal to or greater than 30 degrees and equal to or less than 45 degrees. When the first angle θ1 formed by the bottom surface BS and the inclined surface IS is less than 30 degrees, the length of the channel portion 121 may be excessively shortened due to oxygen vacancies diffusing from the first connection portion 122a or the second connection portion 122b, and when the first angle θ1 formed by the bottom surface BS and the inclined surface IS exceeds 45 degrees, the thickness of the active layer 120 deposited on the inclined surface IS and the thickness of the active layer 120 deposited on the bottom surface BS and the upper surface US may become different from each other, resulting in a problem of non-uniform device characteristics.

[0068] By adjusting a first height H1 of the bottom surface BS of the buffer groove BG and a second height H2 of the upper surface US of the buffer layer 110, the first angle θ1 of the inclined surface IS can be controlled. In this case, each of the first height H1 and the second height H2 may be defined as the distance from the lower surface of the buffer layer 110 to the bottom surface BS of the buffer groove BG or the distance from the lower surface of the buffer layer 110 to the upper surface US of the buffer layer 110.

[0069] According to an embodiment of the present disclosure, the depth H2 - H1 of the bottom surface BS of the buffer groove BG may be equal to or greater than 1.41 μm and equal to or less than 2 μm. When the depth H2 - H1 of the bottom surface BS of the buffer groove BG is less than 1.41 μm, the length of the channel portion 121 may be excessively shortened due to oxygen vacancies diffused from the first connection portion 122a or the second connection portion 122b, and when the depth H2 - H1 of the bottom surface BS of the buffer groove BG exceeds 2 μm, the thickness of the active layer 120 deposited on the inclined surface IS and the thickness of the active layer 120 deposited on the bottom surface BS and the upper surface US may become different from each other, thereby causing a problem of non-uniform device characteristics.

[0070] The active layer 120 may be disposed on the buffer layer 110 to overlap with the buffer groove BG. Specifically, the active layer 120 may be disposed on the upper surface of the buffer layer 110, the inclined surface IS of the buffer groove BG, and a part of the bottom surface BS of the buffer groove BG. The active layer 120 may be disposed in a stepped manner on the buffer groove BG. In this case, the active layer 120 may have a first length L in the horizontal direction ACT .

[0071] The active layer 120 may include a semiconductor material, such as an oxide semiconductor material. The oxide semiconductor material may include, for example, at least one of an oxide semiconductor material based on IZO (InZnO), an oxide semiconductor material based on IGO (InGaO), an oxide semiconductor material based on ITO (InSnO), an oxide semiconductor material based on IGZO (InGaZnO), an oxide semiconductor material based on IGZTO (InGaZnSnO), an oxide semiconductor material based on GZTO (GaZnSnO), an oxide semiconductor material based on GZO (GaZnO), an oxide semiconductor material based on ITZO (InSnZnO), and an oxide semiconductor material based on FIZO (FeInZnO).

[0072] The active layer 120 may include a channel portion 121, a first connection portion 122a, a second connection portion 122b, a first diffusion portion 123a, and a second diffusion portion 123b. In this case, the first connection portion 122a is disposed on one side of the channel portion 121, for example, on the left side, the second connection portion 122b is disposed on the other side of the channel portion 121, for example, on the right side, the first diffusion portion 123a is disposed between the channel portion 121 and the first connection portion 122a, and the second diffusion portion 123b may be disposed between the channel portion 121 and the second connection portion 122b.

[0073] The channel portion 121 is disposed inside the buffer groove BG. Specifically, a central portion of the channel portion 121 may be disposed on the bottom surface BS of the buffer groove BG, and one end and the other end of the channel portion 121 may be disposed on the inclined surface IS of the buffer groove BG.

[0074] The channel portion 121 includes a first region connected to the bottom surface BS and a second region connected to the first region and in contact with the inclined surface IS. In this case, the first region and the second region may form a first angle θ1 like the bottom surface BS and the inclined surface IS of the buffer groove BG.

[0075] The channel portion 121 overlaps with the gate electrode 140. According to an embodiment of the present disclosure, one end (e.g., the left end) of the channel portion 121 corresponds to one end (e.g., the left end) of the gate electrode 140, and the other end (e.g., the right end) of the channel portion 121 may correspond to the other end of the gate electrode 140. However, the present disclosure is not limited thereto.

[0076] The first connection portion 122a and the second connection portion 122b may have conductive characteristics, for example, through a conductive process of performing plasma processing on a semiconductor material using the gate electrode 140 as a mask. For example, in the first connection portion 122a and the second connection portion 122b, during the process of patterning the gate insulating layer 130 disposed on the active layer 120, a partial region of the active layer 120 may be conductive. The gate insulating layer 130 may be formed on the entire surface of the active layer 120 and then patterned by plasma etching. In this case, a partial region of the active layer 120 exposed when a part of the gate insulating layer 130 formed on the entire surface is etched during the process of patterning the gate insulating layer 130 may be conductive to form the first connection portion 122a and the second connection portion 122b.

[0077] The conductive process may be defined as a process of imparting conductive characteristics to an oxide semiconductor material. The oxide semiconductor material to which the conductive process has been performed may have conductive characteristics. The conductive process may include, for example, a plasma process in which plasma is applied to become a conductor, but is not limited thereto. More specifically, when plasma is applied to an oxide semiconductor material, oxygen contained in the oxide semiconductor is released and oxygen vacancies are formed, and electrons move through the oxygen vacancies. As a result, the oxide semiconductor material has conductive characteristics due to the oxygen vacancies. When plasma is used for the conductive process, the plasma may contain, for example, fluorine F. Specifically, the fluorine F-containing plasma may be, for example, sulfur hexafluoride SF6 and nitrogen trifluoride NF3. However, the plasma used to make the first connection portion 122a and the second connection portion 122b conductive is not limited thereto and may include various materials known in the art.

[0078] Through the conductive process, partial regions of the active layer 120 (e.g., the first connection part 122a and the second connection part 122b) can be conductive to have conductive characteristics. Accordingly, the first connection part 122a and the second connection part 122b can have better conductivity than the channel part 121, and each of them can be used as a wiring or a source / drain electrode.

[0079] The first diffusion part 123a and the second diffusion part 123b can be respectively formed during the formation of the first connection part 122a or the second connection part 122b. Specifically, the oxygen vacancies formed in the first connection part 122a or the second connection part 122b can diffuse toward the center of the channel part 121 through the conductive process, and the first diffusion part 123a and the second diffusion part 123b are formed by the oxygen vacancies diffusing toward the center of the channel part 121.

[0080] For example, when the oxygen vacancies formed in the first connection part 122a diffuse in the direction of the channel part 121, the first diffusion part 123a can be formed. Similarly, when the oxygen vacancies formed in the second connection part 122b diffuse, the second diffusion part 123b can be formed.

[0081] Since the first diffusion part 123a and the second diffusion part 123b are conductive by the oxygen vacancies diffusing from the first connection part 122a and the second connection part 122b, their conductive characteristics are relatively lower than those of the first connection part 122a and the second connection part 122b, but are relatively higher than those of the channel part 121.

[0082] According to an embodiment of the present disclosure, the first diffusion part 123a and the second diffusion part 123b can be disposed within the inclined surface IS of the buffer trench BG. Specifically, either one of one end and the other end of the first diffusion part 123a or the second diffusion part 123b can be disposed within the inclined surface IS. By forming in this way, even if the oxygen vacancies diffuse from the first connection part 122a or the second connection part 122b, the length of the designed channel part 121 can be ensured. Since the length of the channel part 121 can be ensured as designed, a thin film transistor substrate having a short channel can be realized without the threshold voltage Vth shifting in the negative (-) direction.

[0083] According to an embodiment of the present disclosure, one end (e.g., the left end) of the first diffusion portion 123a corresponds to one end of the gate insulating layer 130 and one end of the gate electrode 140, and the other end (e.g., the right end) of the first diffusion portion 123a is located within the inclined surface IS of the buffer trench BG. Similarly, one end (e.g., the right end) of the second diffusion portion 123b corresponds to the other end of the gate insulating layer 130 and the other end of the gate electrode 140, and the other end (e.g., the left end) of the second diffusion portion 123b is located within the inclined surface IS of the buffer trench BG. Meanwhile, in this specification, the corresponding meaning refers to being located on a straight line or any one plane.

[0084] The gate insulating layer 130 is disposed on the active layer 120. In this case, the top surface of the gate insulating layer 130 may have a third width W in the horizontal direction GIa , and the third width W GIa may be smaller than the first length L of the active layer 120 ACT .

[0085] The gate insulating layer 130 is etched using the gate electrode 140 as a mask, so that the gate insulating layer 130 can be formed to have the same dimensions as the gate electrode 140. However, the present disclosure is not limited thereto.

[0086] One end (e.g., the left end) of the gate insulating layer 130 may correspond to one end of the gate electrode 140, and the other end (e.g., the right end) of the gate insulating layer 130 may correspond to the other end of the gate electrode 140. Therefore, the third width W of the gate insulating layer 130 GIa may be equal to the second width W of the gate electrode 140 GE .

[0087] The gate insulating layer 130 may be disposed in a stepped manner on the buffer trench BG. Specifically, the height of the central portion of the gate insulating layer 130 may be lower than the height of the edge portion.

[0088] The gate insulating layer 130 may include a silicon nitride layer SiNx or a silicon oxide layer SiOx, but is not limited thereto. The gate insulating layer 130 may be formed of a single layer or multiple layers including an inorganic insulating material and / or an organic insulating material.

[0089] The gate electrode 140 is disposed on the gate insulating layer 130. The width of the gate electrode 140 in the horizontal direction is set to be longer than the width of the bottom surface BS of the buffer trench BG in the horizontal direction and is set to be smaller than the width of the entire buffer trench BG.

[0090] The gate electrode 140 overlaps with the buffer trench BG. Specifically, one end and the other end of the gate electrode 140 are formed to overlap with the inclined surface IS of the buffer trench BG.

[0091] According to an embodiment of the present disclosure, one end and the other end of the gate electrode 140 overlap with the inclined surfaces IS of the buffer trench BG, respectively, such that the channel portion 121 of the active layer 120 can be disposed in the buffer trench BG. That is, the channel portion 121 is formed as a short channel to enhance the on-current characteristics of the thin-film transistor substrate according to an embodiment of the present disclosure, and further prevent the channel portion 121 from being too short such that the threshold voltage Vth of the thin-film transistor substrate according to an embodiment of the present disclosure does not shift in the negative (-) direction.

[0092] The gate electrode 140 may be stepped on the buffer trench BG. Specifically, the height of the central portion of the gate electrode 140 may be lower than the height of the edge portion. In this case, the height of the gate electrode 140 may be defined as the height from the upper surface of the substrate 100 to the upper surface of the central portion of the gate electrode 140 or the height from the upper surface of the substrate 100 to the upper surface of the edge portion of the gate electrode 140.

[0093] The gate electrode 140 may include at least one of an aluminum-based metal (such as aluminum (Al) or an aluminum alloy), a silver-based metal (such as silver (Ag) or a silver alloy), a copper-based metal (such as copper (Cu) or a copper alloy), a molybdenum-based metal (such as molybdenum (Mo) or a molybdenum alloy), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 140 may have a structure including one metal layer or a multi-layer structure including at least two metal layers each having different physical properties.

[0094] The interlayer insulating layer 150 isolates between the gate electrode 140 and the source electrode 161, and also isolates between the gate electrode 140 and the drain electrode 162. The interlayer insulating layer 150 may be formed of a single layer or multiple layers including an inorganic insulating material and / or an organic insulating material.

[0095] The first contact hole CH1 and the second contact hole CH2 may be provided in the interlayer insulating layer 150. Accordingly, a part of the upper surface of the first connection portion 122a of the active layer 120 may be exposed through the first contact hole CH1, and in addition, a part of the upper surface of the second connection portion 122b of the active layer 120 may be exposed through the second contact hole CH2.

[0096] The source electrode 161 and the drain electrode 162 may be provided on the interlayer insulating layer 150.

[0097] The source electrode 161 may be electrically connected to the first connection portion 122a of the active layer 120 through the first contact hole CH1, and the drain electrode 162 may be electrically connected to the second connection portion 122b of the active layer 120 through the second contact hole CH2.

[0098] The source electrode 161 and the drain electrode 162 may be formed of the same material as the gate electrode 140, but are not limited thereto and may be formed of materials according to the knowledge in the art.

[0099] Figure 2B FIG. is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Figure 2B corresponds to Figure 1 cross-sectional view I-I'. Meanwhile, except for the configurations of the channel portion and the diffusion portion, Figure 2B the embodiment of Figure 2A is the same, and thus the different configurations will be mainly described below.

[0100] As Figure 2B shown, a thin film transistor substrate according to another embodiment of the present disclosure may include a substrate 100, a buffer layer 110, an active layer 120, a gate insulating layer 130, a gate electrode 140, an interlayer insulating layer 150, a source electrode 161, and a drain electrode 162. Meanwhile, in Figure 2B the embodiment of Figure 2A the first height H1 of the bottom surface BS of the buffer trench BG is the same as that in Figure 2A the embodiment of

[0101] However, different from the embodiment of

[0102] the upper surface US of the buffer layer 110 has a third height H3 from the bottom surface BS of the buffer layer 110. Accordingly, the inclined surface IS of the buffer trench BG may be formed at a second angle θ2 different from the first angle θ1.

[0103] According to another embodiment of the present disclosure, since the oxygen vacancies diffused from the first connection portion 122a and the second connection portion 122b do not reach a part of the active layer 120 provided on the bottom surface BS of the buffer groove BG, the length of the channel portion 121 provided on the bottom surface BS of the buffer groove BG is not excessively shortened. In addition, since the length of the channel portion 121 is not too short, a thin film transistor substrate having a short channel can be realized without a negative shift in the threshold voltage Vth in the negative (-) direction.

[0104] Figure 3A and 3B are schematic cross-sectional views showing a thin film transistor substrate according to an embodiment of the present disclosure and a thin film transistor substrate according to a comparative example. For ease of description of the thin film transistor substrate according to Figure 2A the embodiment or the thin film transistor substrate according to the comparative example, Figure 3A and 3B are cross-sectional views showing only the substrate, buffer layer, active layer, gate insulating layer, and gate electrode.

[0105] First, since the thin film transistor substrate of Figure 3A is the same as the thin film transistor substrate of Figure 2A , its repeated description will be omitted. In addition, since the thin film transistor substrate according to the comparative example of Figure 3B has the same configuration except for the configuration of the buffer groove, the same reference numerals will be used to describe the remaining configurations, and their repeated description will be omitted.

[0106] The thin film transistor substrate according to the comparative example includes a substrate 100, a buffer layer 110, an active layer 120, a gate insulating layer 130, and a gate electrode 140, as Figure 3B shown. However, according to the comparative example, no separate buffer groove is provided in the buffer layer 110 of the thin film transistor substrate.

[0107] Figure 3C is a graph showing the carrier concentration with respect to the distance to the diffusion portion of the thin film transistor substrate according to an embodiment and a comparative example of the present disclosure. In this case, Figure 3C relates to a graph of the carrier concentration with respect to the distance to the thin film transistor substrate according to the embodiment of Figure 3A and the comparative example of Figure 3B , each including an active layer having a length of 20 μm and a width of 10 μm (20 μm × 10 μm). In addition, this distance refers to the distance measured from one end of the first connection portion 122a in the direction along the active layer 120 to the channel portion 121.

[0108] Figure 3C Point a of Figure 3A relates to the embodiment ofFigure 3B the carrier concentration at one end (e.g., the left end) of the thin film transistor substrate of the comparative example, and Figure 3C point b of relates to according to Figure 3A the embodiment of Figure 3B the carrier concentration at the other end (e.g., the right end) of the thin film transistor substrate of the comparative example.

[0109] From Figure 3C it can be seen that at point a, it can be seen that the carrier concentration is relatively high because one end of the first diffusion portion 123a is in contact with the first connection portion 122a. On the other hand, at point b, the other end of the first diffusion portion 123a is spaced apart from the first connection portion 122a. In this case, it can be seen that when the carrier concentration faces from point a to point b, the carrier concentration gradually decreases. On the other hand, it can be seen that the carrier concentration at point b is about 0.28 times different from the carrier concentration at point a. Therefore, since the diffusion of oxygen vacancies is significantly reduced from the point (e.g., point b) spaced about 1 μm from the first connection portion 122a, the carrier concentration is relatively low, and it can be used as the channel portion 121 starting from point b.

[0110] Return to reference Figure 3A , since the first diffusion portion 123a is provided on the inclined surface IS, the oxygen vacancies from the first connection portion 122a only diffuse from point a to point b. In this case, since one end (e.g., the right end) of the first diffusion portion 123a only diffuses to the point (point b) corresponding to the gate electrode 140, the designed length of the channel portion 121 can be ensured without being too short.

[0111] On the other hand, referring to Figure 3B , since according to Figure 3B the comparative example does not include a separate buffer trench BG, the first diffusion portion 123a is provided on a plane. Therefore, different from the case of Figure 3A , when the oxygen vacancies extend from the first connection portion 122a from point a to point b, one end (e.g., the right end) of the first diffusion portion 123a is located inside the gate electrode 140. As a result, the width of the channel portion 121 in the horizontal direction is formed to be shorter than the width of the gate electrode 140 in the horizontal direction. As a result, according to Figure 3B the comparative example, a channel portion 121 with a length shorter than the designed one is obtained.

[0112] As a result, as in the Figure 3A embodiment, when the buffer layer 110 is provided with a buffer trench BG and the active layer 120 is provided on the buffer trench BG, the first diffusion portion 123a and the second diffusion portion 123b are provided on the inclined surface IS of the buffer trench BG, so that the length of the channel portion 121 can be ensured by the designed length.

[0113] Meanwhile, in Figures 3A to 3C , the carrier concentration according to the distance has been described, with emphasis on the case where the length of the active layer 120 is 20 μm and the width is 10 μm. However, the length and width of the active layer 120 are not limited thereto and can be formed in various sizes according to the knowledge in the art.

[0114] Figures 4A to 4E is a cross-sectional view of a process for manufacturing a thin-film transistor substrate according to an embodiment of the present disclosure. Meanwhile, Figures 4A to 4E The cross-sectional view of the process relates to the process of an embodiment for manufacturing Figure 2A The same reference numerals are assigned to the same configurations, and repeated descriptions will be omitted.

[0115] First, as Figure 4A shown, a substrate 100 is prepared, and a buffer layer 110 is formed on the substrate 100. Then, a buffer groove BG is formed in the buffer layer 110. In this case, the buffer groove BG is formed such that the bottom surface BS and the inclined surface IS of the buffer groove BG form a first angle θ1.

[0116] Next, as Figure 4B shown, an active layer 120 is formed on the buffer layer 110. In this case, the active layer 120 can be formed to cover the entire buffer groove BG. Thus, the active layer 120 can cover the bottom surface BS and the inclined surface IS of the buffer groove BG and a part of the upper surface US of the buffer layer 110.

[0117] Since the active layer 120 is formed to cover the buffer groove BG and a part of the upper surface US of the buffer layer 110, the active layer 120 can be arranged to be stepped on the buffer layer 110.

[0118] Next, as Figure 4C shown, a gate insulating film layer 130a is formed on the buffer layer 110 and the active layer 120, and a gate electrode 140 is patterned on the gate insulating film layer 130a. In this case, the gate insulating film layer 130a can be formed on the entire surface of the substrate 100.

[0119] Since the gate insulating film layer 130a and the gate electrode 140 are formed to overlap the buffer groove BG, the gate insulating film layer 130a and the gate electrode 140 are formed such that the height of the central portion is stepped lower than the height of the edge portion.

[0120] Regarding the gate electrode 140, although not shown in detail, a metal material layer for forming the gate electrode 140 is deposited on the entire surface of the substrate 100, and then the metal material layer is patterned according to the design to form the gate electrode 140. Meanwhile, the present disclosure is not limited thereto.

[0121] Next, asFigure 4D As shown, by using the gate electrode 140 as a mask, the gate insulating film layer 130a can be patterned to form the gate insulating layer 130. In this case, dry etching can be used to form the pattern of the gate insulating layer 130. However, the present disclosure is not limited thereto, and various methods widely known in the art can be used according to the level of those skilled in the art.

[0122] In addition, during the formation of the gate insulating layer 130, a part of the active layer 120 (e.g., the part covered by the gate insulating film layer 130a and then exposed when being etched) can be exposed to the plasma applied during the etching process. In this case, since a part of the active layer 120 is made of an oxide semiconductor material, oxygen vacancies are generated and conductive characteristics are provided. As a result, the part of the active layer 120 covered by the gate insulating film layer 130a and then exposed while being etched becomes the first connection part 122a and the second connection part 122b.

[0123] In addition, another part of the active layer 120 covered by the gate insulating layer 130 can be conductive because the oxygen vacancies formed in the first connection part 122a and / or the second connection part 122b diffuse in the direction of the channel part 121. Another part of the conductive active layer 120 becomes the first diffusion part 123a and the second diffusion part 123b.

[0124] Finally, as Figure 4E shown, an interlayer insulating layer 150 is formed to cover the buffer layer 110, the active layer 120, the gate insulating layer 130, and the gate electrode 140. In this case, a first contact hole CH1 and a second contact hole CH2 are provided in the interlayer insulating layer 150 to expose a part of the upper surface of the first connection part 122a and a part of the upper surface of the second connection part 122b, respectively, and when the source electrode 161 and the drain electrode 162 are formed on the interlayer insulating layer 150, the source electrode 161 is electrically connected to the first connection part 122a through the first contact hole CH1, and the drain electrode 162 is electrically connected to the second connection part 122b through the second contact hole CH2.

[0125] Figure 5 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Figure 5 corresponds to Figure 1 cross-sectional view I-I'. Meanwhile, except for the configuration of the gate insulating layer, Figure 5 the embodiment of Figure 2A is the same as the embodiment of

[0126] such as Figure 5As shown, a thin film transistor substrate according to another embodiment of the present disclosure includes a substrate 100, a buffer layer 110, an active layer 120, a gate insulating layer 130, a gate electrode 140, an interlayer insulating layer 150, a source electrode 161, and a drain electrode 162.

[0127] According to another embodiment of the present disclosure, the gate insulating layer 130 is formed to have a size greater than that of the gate electrode 140. Specifically, the upper surface of the gate insulating layer 130 may have a fourth width WGIb in the horizontal direction, and the fourth width WGIb of the gate insulating layer 130 may be shorter than the first length L of the active layer 120 ACT and greater than the second width WGE of the gate electrode 140. Accordingly, one end and the other end of the gate insulating layer 130 are disposed outside the gate electrode 140 and do not correspond to one end and the other end of the gate electrode 140.

[0128] Since the gate insulating layer 130 is formed to be larger than the gate electrode 140, a part of the upper surface of the gate insulating layer 130 may be exposed to the outside and not covered by the gate electrode 140.

[0129] The gate insulating layer 130 overlaps with a part of the upper surface US of the buffer trench BG and the buffer layer 110. The gate insulating layer 130 may be disposed on the buffer trench BG, and one end (e.g., the left end) and the other end (e.g., the right end) may be respectively disposed on the upper surface US of the buffer layer 110.

[0130] In this case, one end of the gate insulating layer 130 may be disposed between one end of the gate electrode 140 and one end of the active layer 120, and the other end of the gate insulating layer 130 may be disposed between the other end of the gate electrode 140 and the other end of the active layer 120.

[0131] According to another embodiment of the present disclosure, a first diffusion portion 123a and a second diffusion portion 123b may be disposed under the gate insulating layer 130. Specifically, the first diffusion portion 123a and the second diffusion portion 123b may be disposed under a portion of the gate insulating layer 130 not covered by the gate electrode 140.

[0132] In addition, the first diffusion portion 123a and the second diffusion portion 123b may be formed above a region from the upper surface US of the buffer layer 110 to the inclined surface IS of the buffer trench BG. Accordingly, one end (e.g., the left end) of the first diffusion portion 123a and one end (e.g., the right end) of the second diffusion portion 123a are disposed on the upper surface US of the buffer layer 110, and the other end (e.g., the right end) of the first diffusion portion 123a and the other end (e.g., the left end) of the second diffusion portion 123b are disposed on the inclined surface IS of the buffer trench BG.

[0133] By forming in this way, since the lengths from the first connection portion 122a and the second connection portion 122b toward the channel portion 121 increase, even if oxygen vacancies diffuse from the first connection portion 122a or the second connection portion 122b in the direction of the channel portion 121, the designed length of the channel portion 121 can be ensured. As a result, since the length of the channel portion 121 can be ensured as designed, a thin film transistor substrate with a short channel can be realized without shifting the threshold voltage Vth in the negative (-) direction.

[0134] Meanwhile, although not specifically shown in Figure 5 , in another embodiment of the present disclosure, the gate insulating layer 130 is formed to be larger than the gate electrode 140 such that a part of the upper surface of the gate insulating layer 130 is exposed to the outside without being covered by the gate electrode 140. Further, as shown in the above Figure 2B embodiment, the oxygen vacancies diffusing from the first connection portion 122a and the second connection portion 122b reach the inclined surface IS of the buffer groove BG, such that the first diffusion portion 123a and the second diffusion portion 123b are formed to cover the entire inclined surface IS of the buffer groove BG, and the channel portion 121 can be provided only on the bottom surface BS of the buffer groove BG.

[0135] Figures 6A to 6F is a cross-sectional view of a process of manufacturing a thin film transistor substrate according to another embodiment of the present disclosure. Meanwhile, Figures 6A to 6F the process cross-sectional view relates to the process of manufacturing Figure 5 the embodiment, the same reference numerals are assigned to the same configurations, and repeated descriptions are omitted.

[0136] First, as Figure 6A shown, a substrate 100 is prepared, a buffer layer 110 is formed on the substrate 100, and then a buffer groove BG is formed in the buffer layer 110. Meanwhile, since Figure 6A the manufacturing process of Figure 4A is the same as the manufacturing process of

[0137] Next, as Figure 6B shown, an active layer 120 is formed on the buffer layer 110. Meanwhile, since Figure 6B the manufacturing process of Figure 4B is the same as the manufacturing process of

[0138] Next, as Figure 6C shown, a gate insulating film layer 130a is formed on the buffer layer 110 and the active layer 120, and the gate electrode 140 is patterned on the gate insulating film layer 130a. In this case, the gate insulating film layer 130a can be formed on the entire surface of the substrate 100.

[0139] A resist pattern 200 for patterning the gate electrode 140 is formed on the gate electrode 140. The gate electrode 140 is patterned using the resist pattern 200 as a mask.

[0140] The resist pattern 200 may be formed to have a width wider than the width of the gate electrode 140 in a first direction. In addition, the resist pattern 200 may be formed to have a width wider than the width of the buffer trench BG in the first direction.

[0141] Since the gate insulating film layer 130a and the gate electrode 140 are formed to overlap the buffer trench BG, the gate insulating film layer 130a and the gate electrode 140 are formed such that the height of the central portion is stepped lower than the height of the edge portion.

[0142] Next, as Figure 6D shown, by using the resist pattern 200 as a mask, the gate insulating film layer 130a can be patterned to form the gate insulating layer 130. In this case, a dry etching process may be used to form the gate insulating layer 130 pattern. However, the present disclosure is not limited thereto, and various methods widely known in the art may be used according to the level of those skilled in the art.

[0143] According to another embodiment of the present disclosure, since the gate insulating layer 130 is formed using the resist pattern 200 as a mask, the gate insulating layer 130 may be formed to have a width greater than that of the gate electrode 140. Accordingly, one end and the other end of the gate insulating layer 130 are disposed outside the gate electrode 140 and are formed on the upper surface US of the buffer layer 110.

[0144] During the formation of the gate insulating layer 130, a part of the active layer 120 (for example, a part covered by the gate insulating film layer 130a and then exposed while being etched) may be exposed to the plasma applied during the etching process. In this case, since a part of the active layer 120 is made of an oxide semiconductor material, oxygen vacancies are generated and conductive characteristics are provided. As a result, the part of the active layer 120 covered by the gate insulating film layer 130a and exposed when being etched becomes the first connection part 122a and the second connection part 122b.

[0145] In addition, another part of the active layer 120 covered by the gate insulating layer 130 may be conductive because the oxygen vacancies formed in the first connection part 122a and / or the second connection part 122b diffuse in the direction of the channel part 121. The other part of the conductive active layer 120 becomes the first diffusion part 123a and the second diffusion part 123b.

[0146] According to another embodiment of the present disclosure, since the gate insulating layer 130 is disposed on the upper surface US of the buffer layer 110, the first diffusion portion 123a and the second diffusion portion 123b may also be disposed on the upper surface US of the buffer layer 110. Formed in this way, the distance in the direction from the first connection portion 122a or the second connection portion 122b to the channel portion 121 is increased, so that the designed length of the channel portion 121 can be ensured.

[0147] Next, as Figure 6E shown, the resist pattern 200 can be removed by a stripping process.

[0148] Finally, as Figure 6F shown, an interlayer insulating layer 150, a source electrode 161, and a drain electrode 162 are formed. At the same time, since Figure 6F the manufacturing process of Figure 4E is the same as that of

[0149] Figure 7 its repeated description is omitted.

[0150] As Figure 7 shown, a display device according to an embodiment of the present disclosure may include a substrate 100, a buffer layer 110, an active layer 120, a gate insulating layer 130, a gate electrode 140, an interlayer insulating layer 150, a source electrode 161, a drain electrode 162, a planarization layer 170, a first electrode 300, a bank layer 310, a light-emitting layer 320, and a second electrode 330.

[0151] Since the substrate 100, the buffer layer 110, the active layer 120, the gate insulating layer 130, the gate electrode 140, the interlayer insulating layer 150, the source electrode 161, and the drain electrode 162 are the same as those in the above embodiment, only the different configurations will be described below.

[0152] The planarization layer 170 is disposed on the source electrode 161 and the drain electrode 162. A third contact hole CH3 is formed in the planarization layer 170, and the drain electrode 162 is exposed through the third contact hole CH3. However, in some cases, the source electrode 161 may be exposed through the third contact hole CH3.

[0153] The first electrode 300 is formed on the planarization layer 170 and is connected to the source electrode 161 or the drain electrode 162 through the third contact hole CH3. The first electrode 300 may be used as an anode.

[0154] The bank layer 310 may be disposed to cover the edge of the first electrode 300 to define a light-emitting region. Therefore, the upper surface region of the first electrode 300 that is exposed and not covered by the bank layer 310 becomes the light-emitting region.

[0155] The light-emitting layer 320 may be disposed on the first electrode 300. The light-emitting layer 320 may include red, green, and blue light-emitting layers patterned for each pixel, or may be formed of a white light-emitting layer connected to all pixels. When the light-emitting layer 320 is formed of a white emission layer, the light-emitting layer 320 may include, for example, a first stack including a blue emission layer, a second stack including a yellow-green emission layer, and a charge generation layer disposed between the first stack and the second stack, but is not limited thereto.

[0156] The second electrode 330 may be disposed on the light-emitting layer 320. The second electrode 330 may serve as a cathode.

[0157] Although not shown, an encapsulation layer for preventing moisture or oxygen from permeating may be additionally formed on the second electrode 330.

[0158] Figure 8 is a schematic diagram of a display device according to an embodiment of the present disclosure.

[0159] As Figure 8 shown, a display device according to an embodiment of the present disclosure may include a display panel 410, a gate driver 420, a data driver 430, and a controller 440.

[0160] The display panel 410 includes gate lines GL and data lines DL, and pixels P are disposed in corresponding crossing regions of the gate lines GL and the data lines DL. An image is displayed by driving the pixels P. The gate lines GL, the data lines DL, and the pixels P may be disposed on a substrate 100.

[0161] The controller 440 controls the gate driver 420 and the data driver 430. The controller 440 outputs a gate control signal GCS for controlling the gate driver 420 and a data control signal DCS for controlling the data driver 430 by using signals provided from an external system (not shown). In addition, the controller 440 samples input video data input from the external system, rearranges the sampled input video data, and provides the rearranged digital video data RGB to the data driver 430.

[0162] The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal VST, and a gate clock GCLK. In addition, control signals for controlling a shift register may be included in the gate control signal GCS.

[0163] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

[0164] The data driver 430 supplies data voltages to the data lines DL of the display panel 410. Specifically, the data driver 430 converts the video data RGB input from the controller 440 into analog data voltages and supplies the data voltages to the data lines DL.

[0165] The gate driver 420 may be mounted on the display panel 410. As described above, the structure in which the gate driver 420 is directly mounted on the display panel 410 is referred to as a gate-in-panel (GIP) structure. Specifically, in the gate-in-panel (GIP) structure, the gate driver 420 may be disposed on the substrate 100.

[0166] The gate driver 420 may include a shift register 350.

[0167] The shift register 350 sequentially supplies gate pulses to the gate lines GL during one frame by using a start signal and a gate clock transmitted from the controller 440. Herein, one frame refers to a period during which one image is output through the display panel 410. The gate pulse has a turn-on voltage capable of turning on a switching device (thin film transistor) provided in the pixel P.

[0168] In addition, during the remaining period of one frame in which no gate pulse is provided, the shift register 350 supplies a gate cut-off signal capable of turning off the switching device to the gate lines GL. Hereinafter, both the gate pulse and the gate cut-off signal are referred to as a scan signal GS.

[0169] Figure 9 is a circuit diagram of a pixel included in a display device according to an embodiment of the present disclosure.

[0170] As Figure 9 shown, a display device according to an embodiment of the present disclosure may include a first thin film transistor T1 to a second thin film transistor T2 and a capacitor Cst.

[0171] The first thin film transistor T1 is a driving thin film transistor, and the second thin film transistor T2 is a switching thin film transistor. At least one of the first thin film transistor T1 and the second thin film transistor T2 may be formed of the various thin film transistors described above.

[0172] The first thin film transistor T1 is switched according to the data voltage Vdata provided from the second thin film transistor T2, generates a data current according to the driving voltage VDD provided from the power line PL, and supplies it to the organic light emitting diode OLED.

[0173] The second thin film transistor T2 is switched according to the gate signal GS provided to the gate line GL and supplies the data voltage Vdata provided from the data line DL to the first thin film transistor T1.

[0174] According to an embodiment of the present disclosure, the thin film transistor substrate according to the above embodiment can be used as a thin film transistor substrate including any one of a first thin film transistor T1 and a second thin film transistor T2.

[0175] A capacitor Cst is used to hold a data voltage supplied to the first thin film transistor T1 within one frame, and is disposed between a gate electrode and a source electrode of the first thin film transistor T1.

[0176] An organic light emitting diode OLED emits predetermined light according to a data current supplied from the first thin film transistor T1.

[0177] Therefore, the present disclosure can have the following advantages.

[0178] According to an embodiment of the present disclosure, both ends of the gate electrode overlap with inclined surfaces of buffer grooves provided in a buffer layer, and a channel portion of an active layer is disposed inside the buffer grooves, that is, the channel portion is formed to have a short length, thereby improving the on-current characteristics of the thin film transistor substrate according to the embodiment of the present disclosure.

[0179] Furthermore, according to an embodiment of the present disclosure, by disposing the active layer on the inclined surfaces of the buffer grooves, the length of the channel portion is not too short during the conduction process, such that the threshold voltage Vth of the thin film transistor substrate according to the embodiment of the present disclosure does not shift in the negative (-) direction.

[0180] It will be apparent to those skilled in the art that various substitutions, modifications, and variations are possible within the scope of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the scope of the present disclosure is represented by the appended claims, and all changes or modifications derived from the meaning, scope, and equivalent concepts of the claims should be construed as being included within the scope of the present disclosure.

Claims

1. A thin film transistor substrate, comprising: substrate; a buffer layer having a buffer groove, the buffer layer being disposed on the substrate, wherein the buffer groove comprises an inclined surface; an active layer, the active layer being disposed on the buffer layer; as well as a gate electrode, the gate electrode being disposed on the active layer, Wherein, the active layer is arranged in a stepped shape on the buffer groove, And one end of the gate electrode overlaps the inclined surface of the buffer groove.

2. The thin film transistor substrate according to claim 1, in, One end of the gate electrode overlaps a portion of the active layer disposed on the inclined surface of the buffer groove.

3. The thin film transistor substrate according to claim 1, further comprising: a gate insulating layer, the gate insulating layer being disposed between the active layer and the gate electrode, The gate insulating layer overlaps with the buffer groove, and one end of the gate insulating layer corresponds to one end of the gate electrode.

4. The thin film transistor substrate according to claim 1, further comprising: a gate insulating layer, the gate insulating layer being disposed between the active layer and the gate electrode, The gate insulating layer overlaps with the buffer groove, and one end of the gate insulating layer is arranged between one end of the active layer and one end of the gate electrode.

5. The thin film transistor substrate according to claim 4, in, The gate insulating layer has a first width, the gate electrode has a second width, and the active layer has a first length. And the first width of the gate insulating layer is greater than the second width of the gate electrode and less than the first length of the active layer.

6. The thin film transistor substrate according to claim 1, in, The active layer includes a channel portion, a connection portion provided on one side of the channel portion, and a diffusion portion provided between the channel portion and the connection portion, And the channel portion includes a first region contacting a bottom surface of the buffer groove and a second region contacting the inclined surface of the buffer groove.

7. The thin film transistor substrate according to claim 6, in, One end of the second region of the channel portion is disposed in the inclined surface.

8. The thin film transistor substrate according to claim 6, in, One end of the second region of the channel portion corresponds to one end of the gate electrode.

9. The thin film transistor substrate according to claim 6, in, One end of the diffusion portion is disposed on the inclined surface of the buffer groove.

10. The thin film transistor substrate according to claim 9, in, The other end of the diffusion portion corresponds to one end of the gate electrode.

11. The thin film transistor substrate according to claim 9, in, The other end of the diffusion portion is disposed between one end of the gate electrode and one end of the active layer.

12. The thin film transistor substrate according to claim 1, in, The active layer includes a channel portion, a connection portion provided on one side of the channel portion, and a diffusion portion provided between the channel portion and the connection portion, One end of the channel portion is disposed on the bottom surface of the buffer groove, and one end of the diffusion portion is disposed on the inclined surface of the buffer groove, And one end of the channel portion and one end of the diffusion portion contact each other at a boundary between a bottom surface of the buffer groove and the inclined surface of the buffer groove.

13. The thin film transistor substrate according to claim 1, in, The buffer tank further includes a bottom surface connected to the inclined surface, And an angle formed between the bottom surface and the inclined surface is equal to or greater than 30 degrees and equal to or less than 45 degrees.

14. The thin film transistor substrate according to claim 1, in, The buffer tank further includes a bottom surface connected to the inclined surface, And a depth of the bottom surface of the buffer groove is equal to or greater than 1.41 μm and equal to or less than 2 μm.

15. A thin film transistor substrate, comprising: substrate; A buffer layer having a buffer groove, wherein the buffer layer is disposed on the substrate; an active layer, the active layer being disposed on the buffer layer; as well as a gate electrode, the gate electrode being disposed on the active layer, wherein the buffer groove comprises a bottom surface and an inclined surface connected to the bottom surface, The active layer includes a channel portion, a connection portion provided on one side of the channel portion, and a diffusion portion provided between the channel portion and the connection portion, And the channel portion overlaps the bottom surface and the inclined surface, and one end of the channel portion is disposed on the inclined surface of the buffer groove.

16. The thin film transistor substrate according to claim 15, in, The width of the bottom surface of the buffer groove is smaller than the width of the gate electrode, And the width of the entire bottom surface and the inclined surface of the buffer groove is greater than the width of the gate electrode.

17. The thin film transistor substrate according to claim 15, further comprising: a gate insulating layer, the gate insulating layer being disposed between the active layer and the gate electrode, Wherein, the entire area of ​​the diffusion portion overlaps with the gate insulating layer.

18. The thin film transistor substrate according to claim 15, in, A portion of the diffusion portion does not overlap the gate electrode.

19. The thin film transistor substrate according to claim 15, in, One end of the channel portion corresponds to one end of the gate electrode.

20. A display device comprising the thin film transistor substrate according to any one of claims 1 to 19.

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