Thin film transistor and display device including the same

Abstract

A thin film transistor and a display device including the same are provided. The thin film transistor includes an active layer on a substrate and a gate electrode spaced apart from the active layer and overlapping at least a portion of the active layer, where the active layer includes a main active layer and a carrier control layer in contact with the main active layer, and where the carrier control layer includes an oxide semiconductor material and an element of Group 15 of the Periodic Table of Elements.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit and priority of Korean Patent Application No. 10 - 2023 - 0192588, filed on December 27, 2023, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein. Technical field

[0003] The present disclosure relates to a thin - film transistor and a display device including the thin - film transistor. Background art

[0004] Transistors are widely used as switching devices or driving devices in the electronic field. In particular, since thin - film transistors can be fabricated on glass or plastic substrates, they are widely used as switching elements in display devices (e.g., liquid - crystal display devices or organic light - emitting devices).

[0005] Based on the material constituting the active material layer, thin - film transistors can be classified as: amorphous silicon thin - film transistors, in which amorphous silicon is used as the active material layer; polycrystalline silicon thin - film transistors, in which polycrystalline silicon is used as the active material layer; and oxide semiconductor thin - film transistors, in which an oxide semiconductor is used as the active material layer.

[0006] Among them, oxide semiconductor thin - film transistors (oxide semiconductor TFTs), which have high mobility and can have a large resistance change depending on the oxygen content, have the advantage that desired properties can be easily obtained. In addition, the manufacturing cost of oxide semiconductor thin - film transistors is low because, during the manufacturing process of oxide semiconductor thin - film transistors, the oxide constituting the active layer can be formed at a relatively low temperature. Due to the properties of oxides, oxide semiconductors are transparent, so oxide semiconductor thin - film transistors are advantageous for realizing transparent display devices.

[0007] Oxide semiconductor thin - film transistors have many uses and can be used in various environments. However, the reliability of oxide semiconductor thin - film transistors may decrease in high - temperature environments.

[0008] Recently, in order to maximize the advantages of oxide semiconductor thin - film transistors, research is being conducted to improve the stability and electrical characteristics of oxide thin - film transistors and to improve the reliability of oxide semiconductor thin - film transistors. Summary of the invention

[0009] One aspect of the present disclosure is to provide a thin - film transistor having excellent stability and reliability.

[0010] One aspect of the present disclosure is to provide a thin film transistor capable of suppressing a change in threshold voltage (Vth) caused by a change in the Fermi energy (Ef) level of an oxide semiconductor layer at high temperatures. One aspect of the present disclosure is to provide a thin film transistor having a carrier control layer and having a small change in threshold voltage (Vth) even when driven at high temperatures.

[0011] One aspect of the present disclosure is to provide a thin film transistor including a carrier control layer capable of capturing excited electrons in a channel portion. One aspect of the present disclosure is to provide a thin film transistor that can ensure temperature stability of the Fermi energy (Ef) level by having a carrier control layer that can capture carriers having high temperature variability.

[0012] One aspect of the present disclosure is to provide a thin film transistor that has excellent driving stability and reliability by minimizing the change in the Fermi energy (Ef) level with temperature by a carrier control layer.

[0013] Another aspect of the present disclosure is to provide a display device including the thin film transistor as described above and having excellent reliability.

[0014] According to one aspect of the present disclosure, the above and other objects can be achieved by providing a thin film transistor including an active layer on a substrate and a gate electrode spaced apart from the active layer and overlapping at least a part of the active layer, wherein the active layer includes a main active layer and a carrier control layer in contact with the main active layer, the main active layer includes an oxide semiconductor layer, and the carrier control layer includes an oxide semiconductor material and an element of Group 15 of the periodic table.

[0015] The element of Group 15 of the periodic table may include at least one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

[0016] The oxide semiconductor material may include at least one of IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, ITZO (InSnZnO)-based, InO (InO)-based, ZnO-based, IWZO (InWZnO)-based, and FIZO (FeInZnO)-based oxide semiconductor materials.

[0017] The carrier control layer may have a thickness ranging from 1 nm to 5 nm.

[0018] In the carrier control layer, the concentration of the element of Group 15 of the periodic table may be adjusted to 1×10 15 / cm 3 to 1×10 17 / cm 3 range.

[0019] The carrier control layer can capture excited electrons.

[0020] The carrier control layer can have a thickness less than that of the main active layer and can be set closer to the gate electrode than the main active layer.

[0021] The carrier control layer can have a thickness less than that of the main active layer and can be set farther from the gate electrode than the main active layer.

[0022] The carrier control layer can include a first carrier control layer and a second carrier control layer. Each of the first carrier control layer and the second carrier control layer can have a thickness less than that of the main active layer, and the main active layer can be disposed between the first carrier control layer and the second carrier control layer.

[0023] The main active layer can include a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer. The second oxide semiconductor layer can have a carrier concentration higher than that of the first oxide semiconductor layer and can be in contact with the carrier control layer.

[0024] The active layer can include a channel portion overlapping with the gate electrode, a source connection portion connected to one side of the channel portion, and a drain connection portion connected to the other side of the channel portion. The source connection portion and the drain connection portion disposed in the carrier control layer can include an element of Group 15 of the periodic table and at least one of boron (B), fluorine (F), and hydrogen (H).

[0025] The active layer can be disposed between the substrate and the gate electrode.

[0026] The gate electrode can be disposed between the substrate and the active layer.

[0027] Another embodiment of the present disclosure provides a display device including a thin film transistor and a light emitting element.

[0028] Technical effects of the present disclosure

[0029] According to an embodiment of the present disclosure, the carrier control layer containing an element of Group 15 of the periodic table can capture the excited electrons in the channel portion. In addition, carriers having high volatility or varying with temperature can be captured into the carrier control layer. Therefore, temperature stability of the Fermi energy (Ef) level can be ensured in the semiconductor layer or in the channel portion, and the stability and reliability of the thin film transistor can be improved.

[0030] According to an embodiment of the present disclosure, since the carrier control layer can capture carriers that have high volatility at high temperatures, temperature stability of the Fermi energy (Ef) level in the thin film transistor can be ensured.

[0031] The thin film transistor according to an embodiment of the present disclosure can have excellent driving stability and reliability. A display device according to another embodiment of the present disclosure including the thin film transistor as described above can have excellent reliability.

[0032] In addition to the above effects, other features and advantages of the present disclosure are described below. Through the description and explanation, those skilled in the art to which the present disclosure pertains will clearly understand the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings included to provide a further understanding of the present disclosure and incorporated in and constituting a part of this application illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the drawings.

[0034] Figure 1 is a cross-sectional view of a thin film transistor according to an embodiment of the present disclosure.

[0035] Figure 2A is a schematic diagram illustrating a change in the threshold voltage (Vth) of a conventional oxide semiconductor thin film transistor under PBTS (Positive Bias Temperature Stress) conditions.

[0036] Figure 2B is a schematic diagram of the energy band of an oxide semiconductor.

[0037] Figure 3 is a view showing the bonding state of elements of Group 15 (M15) of the periodic table doped in an oxide semiconductor material.

[0038] Figure 4 is a schematic diagram illustrating a change in the bandgap caused by elements of Group 15 (M15) of the periodic table.

[0039] Figure 5 is a schematic energy band diagram of the active layer of a thin film transistor according to an embodiment of the present disclosure.

[0040] Figure 6 is a cross-sectional view of a thin film transistor according to another embodiment of the present disclosure.

[0041] Figure 7 is a cross-sectional view of a thin film transistor according to another embodiment of the present disclosure.

[0042] Figure 8A cross-sectional view of a thin-film transistor according to another embodiment of the present disclosure.

[0043] Figure 9 A cross-sectional view of a thin-film transistor according to another embodiment of the present disclosure.

[0044] Figure 10 A cross-sectional view of a thin-film transistor according to another embodiment of the present disclosure.

[0045] Figure 11 A cross-sectional view of a thin-film transistor according to another embodiment of the present disclosure.

[0046] Figure 12 A graph showing the change in the threshold voltage (Vth) of thin-film transistors according to examples and comparative examples under PBTS (positive bias temperature stress) conditions is shown.

[0047] Figures 13A to 13D A graph of the voltage-current change of a thin-film transistor according to the thickness of the carrier control layer.

[0048] Figures 14A to 14C A graph of the voltage-current change of a thin-film transistor according to the type of element in Group 15 of the periodic table.

[0049] Figure 15 A graph showing the change in the threshold voltage (Vth) of a thin-film transistor with the change in the concentration of the element in Group 15 of the periodic table under a heating state of 100°C.

[0050] Figure 16 A schematic diagram of a display device according to another embodiment of the present disclosure.

[0051] Figure 17 Is Figure 16 The circuit diagram of the pixel of.

[0052] Figure 18 Is Figure 17 The plan view of the pixel of.

[0053] Figure 19 Is along Figure 18 The cross-sectional view of I-I' of. Detailed Description of the Invention

[0054] The advantages and features of the present disclosure and the method of realizing them will be clarified by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the present disclosure to those skilled in the art.

[0055] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings used to describe the embodiments of the present disclosure are merely examples, and thus the present disclosure is not limited to the details shown. Throughout the specification, the same reference numerals denote the same elements. In the following description, when a detailed description of a related known function or configuration is determined to unnecessarily obscure the focus of the present disclosure, the detailed description will be omitted.

[0056] When using the terms "comprising", "having", and "including" described in this specification, unless "only~" is used, other components can be added. Unless otherwise stated, terms in the singular form can include the plural form.

[0057] When interpreting an element, the element is interpreted as including a range of errors, although not explicitly described.

[0058] When describing a positional relationship, for example, when the positional relationship is described as "on", "above", "below", and "next to", unless "exactly" or "directly" is used, one or more other components can be arranged between the two described components.

[0059] Spatial relative terms such as "below", "beneath", "lower", "above", and "upper" can be used herein to easily describe the relationship of one or more elements shown in the figures to one or more other elements. It should be understood that these terms are intended to cover different orientations of the device in addition to the orientation shown in the figures. For example, if the device shown in the figure is inverted, a device described as being "below" or "beneath" another device can be arranged "above" the other device. Thus, the exemplary terms "below or beneath" can include both the "below or beneath" and "above" orientations. Similarly, the exemplary terms "above" or "upper" can include both the "above" and "below or beneath" orientations.

[0060] When describing a temporal relationship, for example, when the chronological order is described as "after", "subsequently", "next", and "before", unless "exactly" or "directly" is used, discontinuous cases can be included.

[0061] It should be understood that although terms such as "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element.

[0062] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first item, the second item, and the third item" means all combinations of two or more items selected from the first item, the second item, and the third item, as well as the first item, the second item, or the third item.

[0063] The features of various embodiments of the present disclosure may be partially or wholly coupled or combined with each other, and may operate with each other in different ways and be technically driven, as can be fully understood by those skilled in the art. The embodiments of the present disclosure may be executed independently of each other, or may be executed together in a mutually dependent relationship.

[0064] Hereinafter, a thin film transistor according to an embodiment of the present disclosure and a display device including the thin film transistor will be described in detail with reference to the accompanying drawings. In the drawings, the same or similar elements are denoted by the same reference numerals, even if they are shown in different drawings.

[0065] In an embodiment of the present disclosure, for convenience of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode may be used interchangeably. The source electrode may be the drain electrode, and the drain electrode may be the source electrode. In addition, the source electrode in any embodiment of the present disclosure may be the drain electrode in another embodiment of the present disclosure, and the drain electrode in any embodiment of the present disclosure may be the source electrode in another embodiment of the present disclosure.

[0066] In some embodiments of the present disclosure, for convenience of explanation, the source region and the source electrode are distinguished, and the drain region and the drain electrode are distinguished, but the embodiments of the present disclosure are not limited thereto. The source region may be the source electrode, and the drain region may be the drain electrode. Additionally, the source region may be the drain electrode, and the drain region may be the source electrode.

[0067] Figure 1 is a cross-sectional view of a thin film transistor 100 according to an embodiment of the present disclosure.

[0068] Referring to Figure 1 , a thin film transistor 100 according to an embodiment of the present disclosure includes an active layer 201 on a substrate 110, and a gate electrode 150 spaced apart from the active layer 201 and overlapping at least a part of the active layer 201. Additionally, the thin film transistor 100 may include a source electrode 160 and a drain electrode 170 spaced apart from each other and electrically connected to the active layer 201 respectively.

[0069] The active layer 201 includes a channel portion CN overlapping with the gate electrode 150, a source connection portion SA connected to one side of the channel portion CN, and a drain connection portion DA connected to the other side of the channel portion CN.

[0070] According to an embodiment of the present disclosure, the thin film transistor 100 may be formed of an active layer 201, a gate electrode 150, a source electrode 160, and a drain electrode 170. Alternatively, it can be said that the thin film transistor 100 includes a channel portion CN, a source connection portion SA, a drain connection portion DA, and a gate electrode 150.

[0071] The thin film transistor 100 may be disposed on a substrate 110.

[0072] The substrate 110 supports other components of the thin film transistor 100. If it supports the thin film transistor 100, it may be referred to as the substrate 110 without limitation.

[0073] Glass or plastic may be used as the substrate 110. Transparent plastic having a flexible property (e.g., polyimide) may be used as the plastic. When polyimide is used as the substrate 110, a heat-resistant polyimide capable of withstanding high temperatures may be used in consideration of performing a high-temperature deposition process on the substrate 110.

[0074] A light-shielding layer may be disposed on the substrate 110 (see Figure 7 ). The light-shielding layer may be omitted.

[0075] Reference Figure 1 , a buffer layer 120 may be disposed on the substrate 110. The buffer layer 120 may be made of an insulating material. For example, the buffer layer 120 may include at least one insulating material selected from the group consisting of silicon oxide, silicon nitride, and metal-based oxides. The buffer layer 120 may have a single-layer structure or a multi-layer structure.

[0076] The buffer layer 120 blocks air and moisture to protect the channel portion CN. In addition, the surface of the upper portion of the substrate 110 may be flattened by the buffer layer 120.

[0077] The active layer 201 is disposed on the substrate 110. Reference Figure 1 , the active layer 201 may be disposed on the buffer layer 120, and the buffer layer 120 is located on the substrate 110.

[0078] According to an embodiment of the present disclosure, the active layer 201 may include an oxide semiconductor material. Specifically, the channel portion CN, the source connection portion SA, and the drain connection portion DA may include an oxide semiconductor material.

[0079] For example, the oxide semiconductor material may include at least one of an IGZO (InGaZnO)-based, IGZTO (InGaZnSNO)-based, IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, ITZO (InSnZnO)-based, InO (InO)-based, ZnO-based, IWZO (InWZnO)-based, and FIZO (FeInZnO)-based oxide semiconductor material. However, embodiments of the present disclosure are not limited thereto, and the active layer 201 may include other oxide semiconductor materials conventionally known in the art.

[0080] The channel portion CN overlaps with the gate electrode 150. The channel portion CN has semiconductor properties. Depending on the voltage applied to the gate electrode 150, the channel portion CN may have electrical characteristics similar to those of a conductor or characteristics similar to those of an insulator.

[0081] According to an embodiment of the present disclosure, the source connection portion SA and the drain connection portion DA may each have electrical characteristics similar to those of a conductor. For example, the source connection portion SA and the drain connection portion DA may each have a -4 resistivity of 10 Ω·cm or less. Whether the thin film transistor 100 is on or off, the source connection portion SA and the drain connection portion DA may each have a constant resistivity.

[0082] According to an embodiment of the present disclosure, the source connection portion SA and the drain connection portion DA may be referred to as a conductor region or a conductive region.

[0083] For example, the source connection portion SA and the drain connection portion DA may be formed by selectively making the active layer 201 conductive. Specifically, the source connection portion SA and the drain connection portion DA may be formed by selectively making the oxide semiconductor material constituting the active layer 201 conductive.

[0084] The selectively conductive portion of the active layer 201 has excellent conductivity and may be used as a wiring portion. A part of the active layer 201 may be selectively made conductive by selective conduction.

[0085] According to an embodiment of the present disclosure, selective conduction means improving the conductivity of a selected portion of the active layer 201 or providing conductivity to the selected portion. According to an embodiment of the present disclosure, selective conduction may be achieved by doping a dopant in a selected region. The source connection portion SA and the drain connection portion DA may include a dopant. According to an embodiment of the present disclosure, doping may be achieved by injecting ions of a conductive element.

[0086] According to an embodiment of the present disclosure, the dopant may include at least one of boron (B), fluorine (F), and hydrogen (H).

[0087] According to an embodiment of the present disclosure, the active layer 201 is formed of an oxide semiconductor material, and selected portions of the active layer 201 are doped with a dopant, so that a source connection portion SA and a drain connection portion DA can be formed.

[0088] However, embodiments of the present disclosure are not limited thereto, and conductivity can be provided or imparted to the source connection portion SA and the drain connection portion DA by other methods. According to an embodiment of the present disclosure, conductivity can be imparted to the source connection portion SA and the drain connection portion DA by plasma treatment. For example, during the patterning process of the gate insulating layer 140 or the gate electrode 150, selective conductivity is performed by plasma treatment, so that the source connection portion SA and the drain connection portion DA can be formed.

[0089] According to an embodiment of the present disclosure, a region of the active layer 201 that is not doped with a dopant and is not conductive can become a channel portion CN.

[0090] Reference Figure 1 , based on the stacked structure, the active layer 201 can include a main active layer 210 and a carrier control layer 220 that contacts the main active layer 210. The main active layer 210 and the carrier control layer 220 will be described later.

[0091] Reference Figure 1 , the gate insulating layer 140 is disposed on the active layer 201. The gate insulating layer 140 can include at least one of silicon oxide, silicon nitride, and metal-based oxide. The gate insulating layer 140 can have a single-layer structure or a multi-layer structure. The gate insulating layer 140 protects the channel portion CN.

[0092] Reference Figure 1 , the gate insulating layer 140 can be patterned. For example, the gate insulating layer 140 can be patterned to correspond to the shape of the gate electrode 150.

[0093] According to an embodiment of the present disclosure, during the patterning process of the gate insulating layer 140 and the gate electrode 150, selective conductivity can be performed to form the source connection portion SA and the drain connection portion DA. Specifically, during the patterning process of the gate insulating layer 140 and the gate electrode 150, selective conductivity can be performed during the plasma treatment process to form the source connection portion SA and the drain connection portion DA.

[0094] However, embodiments of the present disclosure are not limited thereto, and the gate insulating layer 140 can be formed on the entire upper surface of the substrate 110. For example, the gate insulating layer 140 can cover all the channel portions CN, the source connection portion SA, and the drain connection portion DA except for the contact regions.

[0095] The gate electrode 150 is disposed on the gate insulating layer 140. The gate electrode 150 is formed to overlap with the channel portion CN of the active layer 201. Refer to Figure 1 , the active layer 201 may be disposed between the substrate 110 and the gate electrode 150.

[0096] The gate electrode 150 may include at least one of an aluminum-based metal (e.g., aluminum (Al) or an aluminum alloy), a silver-based metal (e.g., silver (Ag) or a silver alloy), a copper-based metal (e.g., copper (Cu) or a copper alloy), a molybdenum-based metal (e.g., molybdenum (Mo) or a molybdenum alloy), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 150 may have a multilayer structure including at least two conductive layers having different physical properties.

[0097] Refer to Figure 1 , the interlayer insulating film 145 is disposed on the gate insulating layer 140 and the gate electrode 150. The interlayer insulating film 145 is an insulating layer made of an insulating material. The interlayer insulating film 145 may be made of an organic material or an inorganic material, or may be a laminate of an organic material layer and an inorganic material layer.

[0098] The source electrode 160 and the drain electrode 170 may be disposed on the interlayer insulating film 145.

[0099] Each of the source electrode 160 and the drain electrode 170 may include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys. Each of the source electrode 160 and the drain electrode 170 may be made of a single-layer structure or a multilayer having two or more layers formed of a metal or a metal alloy.

[0100] According to an embodiment of the present disclosure, the source electrode 160 may be connected to the source connection portion SA. Specifically, the source electrode 160 may be electrically connected to the source connection portion SA through a contact hole and may transmit an electrical signal to the channel portion CN.

[0101] The drain electrode 170 is spaced apart from the source electrode 160 and may be connected to the drain connection portion DA. Specifically, the drain electrode 170 may be electrically connected to the drain connection portion DA through a contact hole and may transmit an electrical signal to the channel portion CN.

[0102] According to an embodiment of the present disclosure, the source connection portion SA may serve as a source electrode, and the drain connection portion DA may serve as a drain electrode. The source connection portion SA and the drain connection portion DA may be interchangeable with each other.

[0103] The source electrode 160 and the drain electrode 170 may be omitted. When the source electrode 160 and the drain electrode 170 are omitted, the source connection portion SA may serve as the source electrode, and the drain connection portion DA may serve as the drain electrode.

[0104] Hereinafter, with reference to Figure 1 , the stacked structure of the active layer 201 will be described in more detail.

[0105] According to an embodiment of the present disclosure, the active layer 201 may include a main active layer 210 and a carrier control layer 220 that contacts the main active layer 210.

[0106] The main active layer 210 may include an oxide semiconductor layer. According to an embodiment of the present disclosure, the main active layer 210 may be made of an oxide semiconductor layer.

[0107] For example, the oxide semiconductor layer included in the main active layer 210 may include at least one of oxide semiconductor materials such as IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, ITZO (InSnZnO)-based, InO (InO)-based, ZnO-based, IWZO (InWZnO)-based, and FIZO (FeInZnO)-based oxide semiconductor materials.

[0108] The main active layer 210 includes a channel portion CN that overlaps with the gate electrode 150, a source connection portion SA connected to one side of the channel portion CN, and a drain connection portion DA connected to the other side of the channel portion CN. When the source connection portion SA and the drain connection portion DA are made conductive by doping with a dopant, the source connection portion SA and the drain connection portion DA of the main active layer 210 may each include at least one of boron (B), fluorine (F), and hydrogen (H).

[0109] The carrier control layer 220 may include an oxide semiconductor material and an element of Group 15 of the periodic table. The carrier control layer 220 may be referred to as having a structure in which the oxide semiconductor material is doped with an element of Group 15 of the periodic table. Specifically, the carrier control layer 220 may have a structure in which a layer made of an oxide semiconductor material is doped with an element of Group 15 of the periodic table.

[0110] According to an embodiment of the present disclosure, the carrier control layer 220 may have a thickness less than that of the main active layer 210. Additionally, with reference to Figure 1 , the carrier control layer 220 may be disposed closer to the gate electrode 150 than the main active layer 210. With reference to Figure 1, the main active layer 210 may be disposed farther from the gate electrode 150 than the carrier control layer 220. More specifically, the main active layer 210, the carrier control layer 220, the gate insulator 140, and the gate electrode 150 may be disposed in sequence. However, embodiments of the present disclosure are not limited thereto, and the main active layer 210 may be disposed closer to the gate electrode 150 than the carrier control layer 220.

[0111] The carrier control layer 220 may include a channel portion CN overlapping with the gate electrode 150, a source connection portion SA connected to one side of the channel portion CN, and a drain connection portion DA connected to the other side of the channel portion CN.

[0112] When the source connection portion SA and the drain connection portion DA are made conductive by doping with a dopant, each of the source connection portion SA and the drain connection portion DA provided in the carrier control layer 220 may include an element of Group 15 of the periodic table of elements, and include at least one of boron (B), fluorine (F), and hydrogen (H).

[0113] According to an embodiment of the present disclosure, the carrier control layer 220 may include an oxide semiconductor layer and an element of Group 15 of the periodic table of elements doped into the oxide semiconductor layer.

[0114] The oxide semiconductor material included in the carrier control layer 220 may include at least one of an IGZO (InGaZnO)-based, an IGZTO (InGaZnSnO)-based, an IZO (InZnO)-based, an IGO (InGaO)-based, an ITO (InSnO)-based, an ITZO (InSnZnO)-based, an InO (InO)-based, a ZnO-based, an IWZO (InWZnO)-based, and a FIZO (FeInZnO)-based oxide semiconductor material.

[0115] The element of Group 15 of the periodic table of elements may include at least one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

[0116] According to an embodiment of the present disclosure, the carrier control layer 220 including the oxide semiconductor material and the element of Group 15 of the periodic table of elements may generate an electronic state to capture carriers. Herein, the carriers may be electrons.

[0117] Specifically, the carrier control layer 220 can form energy gap states and capture excited electrons in the channel portion. Accordingly, the carrier control layer 220 can capture excited electrons, which are carriers having high variation and mobility with temperature. By capturing carriers having high variation and mobility with temperature, the Fermi energy (Ef) level of the thin film transistor 100 can be maintained stable regardless of temperature variations. In an embodiment of the present disclosure, carriers having high variation and mobility with temperature refer to electrons whose capture states have high volatility according to temperature variations.

[0118] Generally, it is known that oxide semiconductor thin film transistors have reduced reliability at high temperatures. Oxide semiconductors generally have an amorphous structure, and thus local non-uniformity may occur. Accordingly, it is known that when an oxide semiconductor is affected by hydrogen or the like, non-uniformity may occur in the Fermi energy (Ef) level of the oxide semiconductor. When an oxide semiconductor thin film transistor is exposed to a high temperature environment, non-uniformity may occur in the Fermi energy (Ef) level, and thus the reliability of the oxide semiconductor thin film transistor may be reduced at high temperatures.

[0119] For this reason, depending on the use environment of a device including an oxide semiconductor thin film transistor, a change in the current of the oxide semiconductor thin film transistor may occur, and a change in the amount of electron capture may occur. This phenomenon may occur significantly in a high temperature environment.

[0120] Figure 2A is a schematic diagram illustrating a change in the threshold voltage (Vth) of a conventional oxide semiconductor thin film transistor under PBTS (positive bias temperature stress) conditions.

[0121] Reference Figure 2A , when a high temperature stress of 100 °C is applied, the change (ΔVth) in the threshold voltage (Vth) over time (seconds, s) is greater than the change when a temperature stress of 60 °C is applied.

[0122] Figure 2B is a schematic diagram of the energy band of an oxide semiconductor.

[0123] Electron capture states of an oxide semiconductor exist in the conduction band, and it is known that electron capture occurs when a bias stress is applied to the oxide semiconductor. In this case, there is no electron capture in the initial state, and thus it should be understood that when a stress (e.g., voltage) is applied, the threshold voltage (Vth) of the device changes or deteriorates.

[0124] According to an embodiment of the present disclosure, in order to prevent or minimize a change (ΔVth) in the threshold voltage (Vth), a carrier control layer 220 including an element of Group 15 of the periodic table is provided on a main active layer 210 including an oxide semiconductor layer.

[0125] Figure 3is a view showing the bonding state of an element of Group 15 (M15) of the periodic table doped in an oxide semiconductor material. In Figure 3 the oxide semiconductor material is included in the carrier control layer 220.

[0126] Reference Figure 3 , in the carrier control layer 220, the element of Group 15 (M15) of the periodic table doped in the oxide semiconductor material can form bonds with other metal atoms (M1, M2, M3) and oxygen atoms (O). Moreover, energy gap states can be formed in the bandgap of the oxide semiconductor by the element of Group 15 (M15) included in the carrier control layer 220.

[0127] Figure 4 is a schematic diagram illustrating the bandgap change caused by the element of Group 15 (M15) of the periodic table.

[0128] Reference Figure 4 , due to the element of Group 15 (M15) of the periodic table, energy gap states may be formed in the bandgap of the oxide semiconductor. The energy gap states formed in the bandgap can be used as electron trapping states. Therefore, the excited electrons in the channel portion can be trapped in the energy gap states.

[0129] Figure 5 is a schematic energy band diagram of the active layer 201 of the thin film transistor 100 according to an embodiment of the present disclosure.

[0130] According to an embodiment of the present disclosure, the carrier control layer 220 can be disposed in contact with the main active layer 210. Due to the element of Group 15 (M15) of the periodic table, energy gap states are formed in the carrier control layer 220 including the oxide semiconductor material, and electron trapping can be achieved through the energy gap states. Specifically, the energy gap states formed in the carrier control layer 220 can trap the excited electrons of the main active layer 210. In particular, the energy gap states formed in the carrier control layer 220 can trap the excited electrons in the channel portion.

[0131] The excited electrons in the channel portion are highly temperature-dependent and correspond to carriers that reduce the stability of the Fermi energy (Ef) level in the channel portion. According to an embodiment of the present disclosure, the carrier control layer 220 can trap the excited electrons. Therefore, the instability of the Fermi energy (Ef) level of the thin film transistor 100 with respect to temperature change can be eliminated, and the driving stability of the thin film transistor 100 can be ensured.

[0132] Accordingly, the thin-film transistor according to an embodiment of the present disclosure can have excellent driving stability, and can minimize the change in the threshold voltage even in a high-temperature environment. As described above, the thin-film transistor according to an embodiment of the present disclosure can have excellent driving stability, especially in an environment where the temperature changes.

[0133] According to an embodiment of the present disclosure, the carrier control layer 220 may have a thickness ranging from 1 nm to 5 nm. If the thickness of the carrier control layer 220 is less than 1 nm, the effect of the energy gap state of the carrier control layer 220 is small, and the effect of ensuring the driving stability of the thin-film transistor 100 under high-temperature stress conditions will not be significant. On the other hand, when the thickness of the carrier control layer 220 exceeds 5 nm, due to the increase in the energy gap state, electrons other than the excited electrons in the initial state are trapped, thereby reducing the carriers, and as a result, the mobility and current of the thin-film transistor can be reduced. According to an embodiment of the present disclosure, the thickness of the carrier control layer 220 is less than the thickness of the main active layer 210.

[0134] Figure 6 is a cross-sectional view of a thin-film transistor 200 according to another embodiment of the present disclosure. Hereinafter, in order to avoid repeated description, components that have been described will be briefly described, or the description of components that have been described will be omitted.

[0135] Reference Figure 6 , the gate insulating layer 140 may be provided on the entire upper surface of the substrate 110 without patterning. The gate insulating layer 140 may cover all channel portions CN, source connection portions SA, and drain connection portions DA except for the contact regions.

[0136] Figure 7 is a cross-sectional view of a thin-film transistor 300 according to another embodiment of the present disclosure.

[0137] Reference Figure 7 , the main active layer 210 may have a multilayer structure.

[0138] According to another embodiment of the present disclosure, the main active layer 210 may include a first oxide semiconductor layer 211 and a second oxide semiconductor layer 212 on the first oxide semiconductor layer 211. Specifically, the main active layer 210 may include an oxide semiconductor layer, and the oxide semiconductor layer of the main active layer 210 may include a first oxide semiconductor layer 211 and a second oxide semiconductor layer 212.

[0139] The first oxide semiconductor layer 211 supports the second oxide semiconductor layer 212. Thus, the first oxide semiconductor layer 211 may be referred to as a support layer. According to an embodiment of the present disclosure, the second oxide semiconductor layer 212 may have a higher carrier concentration than the first oxide semiconductor layer 211 and may be in contact with the carrier control layer 220. The main channel may be formed in the second oxide semiconductor layer 212. According to an embodiment of the present disclosure, when the main active layer 210 has a multilayer structure, the layer serving as the main channel may be in contact with the carrier control layer 220.

[0140] Meanwhile, another embodiment of the present disclosure is not limited to Figure 7 the structure, and the main channel may be formed in the first oxide semiconductor layer 211. In this case, the first oxide semiconductor layer 211 may have a higher carrier concentration than the second oxide semiconductor layer 212 and may be in contact with the carrier control layer 220.

[0141] The thin film transistor 300 according to another embodiment of the present disclosure may further include a light-shielding layer 111 overlapping with the channel portion CN.

[0142] The light-shielding layer 111 is disposed between the substrate 110 and the active layer 201. Specifically, the light-shielding layer 111 may be disposed between the substrate 110 and the buffer layer 120.

[0143] The light-shielding layer 111 blocks light incident from the outside to protect the channel portion CN. The light-shielding layer 111 may be made of a material having a light-blocking property. The light-shielding layer 111 may include at least one of an aluminum-based metal (e.g., aluminum (Al) or an aluminum alloy), a molybdenum-based metal (e.g., molybdenum (Mo) or a molybdenum alloy), chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), and iron (Fe).

[0144] According to an embodiment of the present disclosure, the light-shielding layer 111 may have conductivity. The light-shielding layer 111 may be electrically connected to the source electrode 160 or the drain electrode 170.

[0145] Referring to Figure 7 , the light-shielding layer 111 is connected to the source electrode 160 and thus may be electrically connected to the source connection portion SA. The light-shielding layer 111 may be in direct contact with the source connection portion SA. However, another embodiment of the present disclosure is not limited thereto, and the light-shielding layer 111 may be in contact with the drain connection portion DA or may be connected to the drain electrode 170.

[0146] Figure 8 is a cross-sectional view of a thin film transistor 400 according to another embodiment of the present disclosure.

[0147] According to another embodiment of the present disclosure, the carrier control layer 220 may be disposed farther from the gate electrode 150 than the main active layer 210. Referring toFigure 8 , in the main active layer 210 and the carrier control layer 220, the main active layer 210 may be disposed closer to the gate electrode 150 than the carrier control layer 220. Specifically, the carrier control layer 220 may have a thickness smaller than that of the main active layer 210 and may be disposed farther from the gate electrode 150 than the main active layer 210.

[0148] Figure 9 is a cross-sectional view of a thin film transistor 500 according to another embodiment of the present disclosure. Refer to Figure 9 , carrier control layers 221 and 222 may be disposed on both sides of the main active layer 210.

[0149] Specifically, according to another embodiment of the present disclosure, the carrier control layer 220 includes a first carrier control layer 221 and a second carrier control layer 222, and the main active layer 210 may be disposed between the first carrier control layer 221 and the second carrier control layer 222. According to another embodiment of the present disclosure, each of the first carrier control layer 221 and the second carrier control layer 222 has a thickness smaller than that of the main active layer 210, and the main active layer 210 may be disposed between the first carrier control layer 221 and the second carrier control layer 222.

[0150] In Figure 9 the thin film transistor 500, energy gap states may be formed on both sides of the channel portion CN of the main active layer 210, and excited electrons may be trapped on both sides of the main active layer 210 through the energy gap states.

[0151] Figure 1 , 6 , 7, 8, and 9 illustrate thin film transistors 100, 200, 300, 400, and 500 of a top gate structure, in which the gate electrode 150 is disposed on top of the active layer 201. However, the embodiments of the present disclosure are not limited thereto, and the thin film transistor may have a double gate structure or a bottom gate structure.

[0152] Figure 10 is a cross-sectional view of a thin film transistor 600 according to another embodiment of the present disclosure.

[0153] Refer to Figure 10 , the thin film transistor 600 according to another embodiment of the present disclosure may have a double gate structure. Specifically, the thin film transistor 600 may include gate electrodes 151 and 152 disposed on both sides of the active layer 201.

[0154] According to another embodiment of the present disclosure, the gate electrode 150 may include a first gate electrode 151 and a second gate electrode 152. The first gate electrode 151 is disposed between the substrate 110 and the active layer 201. The second gate electrode 152 is disposed on the opposite side of the first gate electrode 151 centered on the active layer 201. Accordingly, the active layer 201 may be disposed between the first gate electrode 151 and the second gate electrode 152.

[0155] Figure 11 is a cross-sectional view of a thin film transistor 700 according to another embodiment of the present disclosure.

[0156] According to another embodiment of the present disclosure, the gate electrode 150 is disposed on the substrate 110, the active layer 201 is disposed on the gate electrode 150, and the source electrode 160 and the drain electrode 170 are respectively disposed on the active layer 201. The gate insulating layer 140 is disposed between the gate electrode 150 and the active layer 201. The active layer 201 includes a main active layer 210 and a carrier control layer 220 in contact with the main active layer 210.

[0157] Reference Figure 11 , the gate electrode 150 is disposed between the substrate 110 and the active layer 201. As Figure 11 shown, the structure of the thin film transistor 700 in which the gate electrode 150 is disposed below the active layer 201 is referred to as a bottom gate structure.

[0158] Figure 12 shows a graph illustrating changes in the threshold voltage (Vth) of thin film transistors according to examples and comparative examples under PBTS (positive bias temperature stress) conditions.

[0159] Figure 12 The curve in

[0160] shows the result of measuring the change (ΔVth) in the threshold voltage of the thin film transistor over time (seconds, s) under the condition of applying a high temperature stress of 100 °C to the thin film transistors according to examples and comparative examples. Figure 12 In Figure 1 shown, the thin film transistor according to an example of the present disclosure includes a main channel layer 210 and a carrier control layer 220, and the carrier control layer 220 includes an IGZO (InGaZnO) oxide semiconductor material and bismuth (Bi) doped into the IGZO (InGaZnO) oxide semiconductor material. The thin film transistor according to an example of the present disclosure has

[0161] shown in Figure 12 In, the thin film transistor according to the comparative example has the same structure as the example, but does not include the carrier control layer 220.

[0162] Reference Figure 12, in the thin film transistor according to the comparative example that does not include the carrier control layer 220, the threshold voltage (Vth) continuously increases with the passage of time (seconds, s) under the temperature condition of 100 °C. It can be confirmed that, compared with the thin film transistor according to the example, the change in the threshold voltage over time (ΔVth) in the thin film transistor according to the comparative example is relatively large.

[0163] In the thin film transistor according to the example, it can be confirmed that even under the temperature condition of 100 °C, the change in the threshold voltage over time (ΔVth) is not large. In particular, it can be confirmed that, compared with the thin film transistor according to the comparative example, the thin film transistor according to the example has a relatively small change in the threshold voltage over time (ΔVth).

[0164] Figures 13A to 13D is a graph of the voltage-current change of the thin film transistor according to the thickness of the carrier control layer 220.

[0165] In Figures 13A to 13D In the graph, the thin film transistor including the main channel layer 210 and the carrier control layer 220 is measured. The main channel layer 210 includes an IGZO (InGaZnO) oxide semiconductor layer, and the carrier control layer 220 is made of an IGZO (InGaZnO) oxide semiconductor material doped with bismuth (Bi).

[0166] Figure 13A is a graph of the voltage-current change measured for the thin film transistor with the carrier control layer 220 having a thickness of 1 nm. Figure 13B is a graph of the voltage-current change measured for the thin film transistor with the carrier control layer 220 having a thickness of 3 nm. Figure 13C is a graph of the voltage-current change measured for the thin film transistor with the carrier control layer 220 having a thickness of 5 nm. Figure 13D is a graph of the voltage-current change measured for the thin film transistor with the carrier control layer 220 having a thickness of 10 nm.

[0167] Referring to Figures 13A to 13D , it can be seen that when the thickness of the carrier control layer 220 is 1 to 5 nm, the thin film transistor has effective switching characteristics. In addition, when the thickness of the carrier control layer 220 is 1 to 5 nm, even when high-temperature stress is applied, the change in the threshold voltage (Vth) of the thin film transistor over time (seconds, s) is not significant.

[0168] When the thickness of the carrier control layer 220 is less than 1 nm, the effect of forming the energy gap state of the carrier control layer 220 is not significant. Therefore, under the condition of applying high-temperature stress, the effect of maintaining the driving stability of the thin-film transistor may not be significant. On the other hand, when the thickness of the carrier control layer 220 is greater than 5 nm, due to the increase in the energy gap state, electrons other than those in the excited state are captured in the initial state, and the carriers are reduced. Therefore, the mobility and current of the thin-film transistor may decrease.

[0169] Therefore, according to an embodiment of the present disclosure, the carrier control layer 220 may be designed to have a thickness ranging from 1 nm to 5 nm. Specifically, the carrier control layer 220 may have a thickness ranging from 1 nm to 3 nm.

[0170] Figures 14A to 14C is a voltage-current change curve graph of a thin-film transistor according to the type of element in Group 15 of the periodic table.

[0171] Specifically, Figure 14A is for a thin-film transistor having the same structure as the thin-film transistor applied in Figure 13A , where the element in Group 15 of the periodic table included in the carrier control layer 220 is bismuth (Bi). Referring to Figure 14A , it can be seen that the threshold voltage of the thin-film transistor using bismuth (Bi) as the element in Group 15 of the periodic table is close to 0 V. In addition, even when the thin-film transistor is exposed to high-temperature conditions for a long time, the change in the threshold voltage (ΔVth) is not significant.

[0172] Figure 14B is for a thin-film transistor having the same structure as the thin-film transistor applied in Figure 13A , where the element in Group 15 of the periodic table included in the carrier control layer 220 is arsenic (As). Referring to Figure 14B , it shows that the threshold voltage of the thin-film transistor using arsenic (As) as the element in Group 15 of the periodic table is close to 2.5 V. In addition, even when the thin-film transistor is exposed to high-temperature conditions for a long time, the change in the threshold voltage (ΔVth) is not significant.

[0173] Figure 14C is for a thin-film transistor having the same structure as the thin-film transistor applied in Figure 13A , where the element in Group 15 of the periodic table included in the carrier control layer 220 is phosphorus (P). Referring to Figure 14C, it is shown that the threshold voltage of a thin film transistor using phosphorus (P) as an element of Group 15 of the periodic table is close to 4.5 V. Additionally, even when the thin film transistor is exposed to high temperature conditions for a long time, the change in the threshold voltage (ΔVth) is not significant.

[0174] Reference Figures 14A to 14C , it can be seen that as the atomic weight of the element of Group 15 of the periodic table included in the carrier control layer 220 decreases, the depth of the energy gap state becomes deeper, and the threshold voltage (Vth) moves in the positive direction. When using an element of Group 15 of the periodic table with a low atomic weight in the carrier control layer 220, it can be seen that the mobility of the thin film transistor decreases and the thermal stability increases. On the other hand, when using an element of Group 15 of the periodic table with a large atomic weight in the carrier control layer 220, it can be seen that the decrease in the mobility of the thin film transistor is suppressed.

[0175] Figure 15 is a graph showing the change in the threshold voltage (Vth) of the thin film transistor with the change in the concentration of the element of Group 15 of the periodic table under the heating state of 100 °C.

[0176] Reference Figure 15 , it can be seen that when the concentration of the element of Group 15 of the periodic table included in the carrier control layer 220 is 1×10 15 / cm 3 to 1×10 17 / cm 3 , under the high temperature condition of 100 °C, the change in the threshold voltage (ΔVth) in the thin film transistor can be maintained below about 1 V.

[0177] Therefore, according to an embodiment of the present disclosure, the concentration of the element of Group 15 of the periodic table included in the carrier control layer 220 can be adjusted to be in the range of 1×10 15 / cm 3 to 1×10 17 / cm 3 .

[0178] When the concentration of the element of Group 15 of the periodic table included in the carrier control layer 220 is less than 1×10 15 / cm 3 , the effect of forming the energy gap state of the carrier control layer 220 is not significant, such that under the condition of applying high temperature stress, the effect of ensuring the driving stability of the thin film transistor may not be significant. On the other hand, when the concentration of the element of Group 15 of the periodic table included in the carrier control layer 220 is greater than 1×10 17 / cm 3When a high temperature stress is applied, a change (ΔVth) in a threshold voltage of a thin film transistor may increase, and thus driving stability of the thin film transistor may deteriorate.

[0179] Hereinafter, a display device including the above-described thin film transistor will be described in detail.

[0180] Figure 16 is a schematic view of a display device 800 according to another embodiment of the present disclosure.

[0181] A display device 800 according to another embodiment of the present disclosure may include a display panel 310, a gate driver 320, a data driver 330, and a controller 340.

[0182] Gate lines GL and data lines DL are disposed in the display panel 310, and pixels P are disposed at intersections of the gate lines GL and the data lines DL. An image is displayed by driving the pixels P.

[0183] The controller 340 controls the gate driver 320 and the data driver 330.

[0184] The controller 340 generates a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 using, for example, signals provided from an external system (not shown). In addition, the controller 340 samples input image data input from the external system, realigns it, and provides the realigned digital image data RGB to the data driver 330.

[0185] The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. In addition, the gate control signal GCS may include a control signal for controlling the shift register 350.

[0186] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

[0187] The data driver 330 supplies a data voltage to the data lines DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into an analog data voltage and supplies the data voltage to the data lines DL.

[0188] The gate driver 320 may include a shift register 350. The shift register 350 sequentially supplies gate pulses to the gate lines GL within one frame using a start signal and a gate clock transmitted from the controller 340.

[0189] Using the shift register 350, the gate driver 320 can sequentially supply gate pulses GP to the gate lines GL during one frame. Here, one frame refers to the period during which an image is output through the display panel. In addition, during the remaining period of one frame when the gate pulse GP is not supplied, the gate driver 320 supplies a gate cut-off signal Goff that can turn off the switching element to the gate lines GL. Hereinafter, the gate pulse GP and the gate cut-off signal Goff are collectively referred to as the scan signal SS.

[0190] According to an embodiment of the present disclosure, the gate driver 320 can be mounted in the display panel 310. In this way, the structure in which the gate driver 320 is directly mounted in the display panel 310 is referred to as a gate-in-panel (GIP) structure.

[0191] Figure 17 is Figure 16 a circuit diagram of the pixel P of Figure 18 is Figure 17 a plan view of the pixel P of Figure 19 and is Figure 18 a cross-sectional view taken along I-I' of

[0192] Figure 17 The circuit diagram of

[0193] is an equivalent circuit diagram of the pixel P of the display device 800 including an organic light-emitting diode OLED as the display element 710.

[0194] The pixel P includes a display element 710 and a pixel driving circuit PDC that drives the display element 710.

[0195] The data line DL supplies a data voltage Vdata to the pixel driving circuit PDC, and the first thin-film transistor TR1 controls the application of the data voltage Vdata.

[0196] The driving power supply line PL supplies a driving voltage Vdd to the display element 710, and the second thin-film transistor TR2 controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving the organic light-emitting diode OLED as the display element 710.

[0197] The above thin-film transistors 100, 200, 300, 400, 500, 600, and 700 can be used as Figure 17 the first thin-film transistor TR1 or the second thin-film transistor TR2 of

[0198] When the first thin-film transistor TR1 is turned on by a scan signal SS applied from a gate driver 320 through a gate line GL, a data voltage Vdata provided from a data line DL is supplied to a gate electrode of a second thin-film transistor TR2 connected to a display element 710. The data voltage Vdata is charged in a capacitor Ct formed between the gate electrode and a source electrode of the second thin-film transistor TR2. Figure 17 The capacitor Ct is a storage capacitor.

[0199] The amount of current supplied to an organic light-emitting diode OLED serving as the display element 710 through the second thin-film transistor TR2 is controlled according to the data voltage Vdata, whereby the gray level of light emitted from the display element 710 can be controlled.

[0200] Reference Figure 18 and 19 The first thin-film transistor TR1 and the second thin-film transistor TR2 are provided on a substrate 110.

[0201] The substrate 110 may be made of glass or plastic. As the substrate 110, a plastic having a flexible property, such as polyimide (PI), may be used.

[0202] A light-shielding layer 111 is provided on the substrate 110. The light-shielding layer 111 may have a light-blocking property. The light-shielding layer 111 can protect an active material layer and a channel portion A2 by blocking light incident from the outside. A part of the light-shielding layer 111 may become a first capacitor electrode CE1. Reference Figure 18 and 19 The light-shielding layer 111 and the first capacitor electrode CE1 may be integrally formed as one body.

[0203] In addition, the data line DL, a driving power line PL, and a first bridging electrode BR21 are provided on the substrate 110.

[0204] A buffer layer 120 is provided on the light-shielding layer 111, the first capacitor electrode CE1, the data line DL, the driving power line PL, and the first bridging electrode BR21. The buffer layer 120 may be made of an insulating material and protect the channel portions A1 and A2 from moisture or oxygen introduced from the outside.

[0205] An active layer 201 is provided on the buffer layer 120. The active layer 201 may include an oxide semiconductor material. The active layer 201 may include an oxide semiconductor layer made of an oxide semiconductor material. The active layer 201 includes a main active layer 210 and a carrier control layer 220 in contact with the main active layer 210.

[0206] The active layer 201 includes a first channel portion A1, a first source connection portion, a first drain connection portion, a second channel portion A2, a second source connection portion, and a second drain connection portion. Refer to Figure 18 and 19 , the first source connection can become the first source electrode S1, the first drain connection can become the first drain electrode D1, the second source connection can become the second source electrode S2, and the second drain connection can become the second drain electrode D2.

[0207] In addition, a part of the active layer 201 can be made conductive to become the second capacitor electrode CE2.

[0208] The first source electrode S1 of the first thin film transistor TR1 is connected to the data line DL through a contact hole. The first drain electrode D1 of the first thin film transistor TR1 is connected to the first bridge electrode BR21 through a contact hole.

[0209] The second source electrode S2 of the second thin film transistor TR2 is connected to the light shielding layer 111 through a contact hole. Therefore, the same voltage as that of the second source electrode S2 can be applied to the first capacitor electrode CE1 formed integrally with the light shielding layer 111.

[0210] The gate insulating layer 140 is disposed on the active layer 201 and the second capacitor electrode CE2. The gate insulating layer 140 has insulating properties and separates the active layer 201 from the gate electrodes G1 and G2. The gate insulating layer 140 can cover the entire upper surface of the active layer 201.

[0211] The first gate electrode G1 of the first thin film transistor TR1 and the second gate electrode G2 of the second thin film transistor TR2 are disposed on the gate insulating layer 140.

[0212] Refer to Figure 18 and 19 , an interlayer insulating film 145 can be disposed on the gate electrodes G1 and G2, and a third capacitor electrode CE3 can be disposed on the interlayer insulating film 145. The third capacitor electrode CE3 overlaps with the first capacitor C1 and the second capacitor C2.

[0213] A passivation layer 180 can be disposed on the third capacitor electrode CE3. The passivation layer 180 protects the thin film transistors TR1 and TR2.

[0214] On the passivation layer 180, gate lines GL and bridge electrodes BR22, BR23, and BR24 are disposed.

[0215] The gate line (GL) is connected to the first gate electrode G1 of the first thin film transistor TR1 through a contact hole. Therefore, a scan signal SS can be applied to the first gate electrode G1 of the first thin film transistor TR1.

[0216] The second bridging electrode BR22 is disposed on the passivation layer 180 and connects the driving power line PL and the second drain electrode D2 of the second thin film transistor TR2. Refer to Figure 18 , one side of the second bridging electrode BR22 is connected to the driving power line PL through a contact hole. The other side of the second bridging electrode BR22 is connected to the second drain electrode D2 of the second thin film transistor TR2 through a contact hole. Therefore, the driving voltage Vdd can be applied to the second drain electrode D2 of the second thin film transistor TR2.

[0217] The third bridging electrode BR23 is disposed on the passivation layer 180 and connects the first bridging electrode BR21, the second gate electrode G2 of the second thin film transistor TR2, and the second capacitor electrode CE2 to each other.

[0218] The first bridging electrode BR21 is connected to the first drain electrode D1 of the first thin film transistor, so the data voltage Vdata transmitted to the first drain electrode D1 through the first thin film transistor TR1 can be applied to the second gate electrode G2 of the second thin film transistor TR2 through the first bridging electrode BR21 and the third bridging electrode BR23.

[0219] In addition, through the third bridging electrode BR23, a voltage identical to the voltage of the second gate electrode G2 can be applied to the second capacitor electrode CE2.

[0220] Therefore, the same voltage can be applied to the first drain electrode D1 of the first thin film transistor TR1, the second gate electrode G2 of the second thin film transistor TR2, and the second capacitor electrode CE2.

[0221] The fourth bridging electrode BR24 is disposed on the passivation layer 180 to connect the light shielding layer 111 and the third capacitor electrode CE3. Therefore, a voltage identical to the voltage of the first capacitor electrode CE1 can be applied to the third capacitor electrode CE3. Refer to Figure 18 and 19 , the same voltage can be applied to the third capacitor electrode CE3 and the second source electrode S2 of the second thin film transistor TR2.

[0222] The first capacitor C1 can be formed by overlapping the first capacitor electrode CE1 and the second capacitor electrode CE2. The second capacitor C2 can be formed by overlapping the second capacitor electrode CE2 and the third capacitor electrode CE3. The entire capacitor Ct is formed by the first capacitor C1 and the second capacitor C2.

[0223] The planarization layer 190 is disposed on the gate line GL and the bridge electrodes BR22, BR23, and BR24. The planarization layer 190 planarizes the upper portions of the first thin film transistor TR1 and the second thin film transistor TR2 and protects the first thin film transistor TR1 and the second thin film transistor TR2.

[0224] The first electrode 711 of the display element 710 is disposed on the planarization layer 190. The first electrode 711 of the display element 710 may contact the fourth bridge electrode BR24 through a contact hole formed in the planarization layer 190. Accordingly, the first electrode 711 may be connected to the second source electrode S2 of the second thin film transistor TR2.

[0225] The bank layer 750 is disposed at an edge of the first electrode 711. The bank layer 750 defines a light emitting region of the display element 710.

[0226] The organic light emitting layer 712 is disposed on the first electrode 711, and the second electrode 713 is disposed on the organic light emitting layer 712. Accordingly, the display element 710 is completed. Figure 19 The illustrated display element 710 is an organic light emitting diode (OLED). Accordingly, the display device 100 according to another embodiment of the present disclosure is an organic light emitting display device.

[0227] In Figures 17 to 19 it is described that the pixel driving circuit PDC has a 2TR1C structure in which there are two transistors and one capacitor. However, another embodiment of the present disclosure is not limited thereto. The pixel driving circuit PDC according to another embodiment of the present disclosure may be formed in various structures other than the above structure. The pixel driving circuit PDC may include, for example, three or more thin film transistors and may include, for example, two or more capacitors.

[0228] The above present disclosure is not limited to the above embodiments and drawings, and it is known to those of ordinary skill in the art that various substitutions, modifications, and changes may be made within the scope of the technical details of the present disclosure.

Claims

1. A thin film transistor, comprising: an active layer on a substrate; as well as a gate electrode spaced apart from the active layer and overlapping at least a portion of the active layer, Wherein, the active layer comprises: a main active layer, the main active layer comprising an oxide semiconductor layer; and a carrier control layer, the carrier control layer being in contact with the main active layer, Wherein, the carrier control layer comprises: Oxide semiconductor materials; and An element of Group 15 of the periodic table.

2. The thin film transistor according to claim 1, wherein: The element of Group 15 of the periodic table includes at least one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

3. The thin film transistor according to claim 1, wherein: The oxide semiconductor material includes at least one of an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, an IZO (InZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an ITO (InSnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, an InO (InO)-based oxide semiconductor material, a ZnO-based oxide semiconductor material, an IWZO (InWZnO)-based oxide semiconductor material and a FIZO (FeInZnO)-based oxide semiconductor material.

4. The thin film transistor according to claim 1, wherein: The carrier control layer has a thickness ranging from 1 nm to 5 nm.

5. The thin film transistor according to claim 1, wherein: In the carrier control layer, the element of Group 15 of the periodic table has a range of 1×10 15 / cm 3 Up to 1×10 17 / cm 3 concentration.

6. The thin film transistor according to claim 1, wherein: The carrier control layer captures excited electrons.

7. The thin film transistor according to claim 1, wherein: The carrier control layer has a thickness smaller than that of the main active layer, and The carrier control layer is disposed closer to the gate electrode than the main active layer.

8. The thin film transistor according to claim 1, wherein: The carrier control layer has a thickness smaller than that of the main active layer, and The carrier control layer is arranged to be farther away from the gate electrode than the main active layer.

9. The thin film transistor according to claim 1, wherein: The carrier control layer includes a first carrier control layer and a second carrier control layer, The first carrier control layer and the second carrier control layer each have a thickness smaller than that of the main active layer, and The main active layer is disposed between the first carrier controlling layer and the second carrier controlling layer.

10. The thin film transistor according to claim 1, wherein: The main active layer comprises: a first oxide semiconductor layer; and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein the second oxide semiconductor layer has a carrier concentration higher than that of the first oxide semiconductor layer, and The second oxide semiconductor layer contacts the carrier control layer.

11. The thin film transistor according to claim 1, wherein: The active layer comprises: a channel portion, the channel portion overlapping the gate electrode; a source connection portion connected to one side of the channel portion; and a drain connection portion connected to the other side of the channel portion, and Wherein, each of the source connection portion and the drain connection portion provided in the carrier control layer comprises: Elements of Group 15 of the Periodic Table; and At least one of boron (B), fluorine (F) and hydrogen (H).

12. The thin film transistor according to claim 1, wherein: The active layer is disposed between the substrate and the gate electrode.

13. The thin film transistor according to claim 1, wherein: The gate electrode is disposed between the substrate and the active layer.

14. A display device, comprising: The thin film transistor according to any one of claims 1 to 13; as well as Light-emitting element.

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