Display device and method for manufacturing display device

Abstract

The invention relates to a display device and a method for manufacturing the same. The display device includes: a substrate; a light emitting element over the substrate and including a first semiconductor layer, an active layer, and a second semiconductor layer having a lens-shaped upper surface spaced apart from the active layer; and a common electrode over the light emitting element in which a side surface of the active layer and a side surface of the second semiconductor layer are aligned.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority and the benefit of Korean Patent Application No. 10 - 2023 - 0192782, filed with the Korean Intellectual Property Office on December 27, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display device and a method of manufacturing a display device. Background art

[0004] With the development of the information society, the demand for display devices for displaying images has increased in various forms. The display device may be a flat panel display device, such as a liquid crystal display, a field emission display, or a light - emitting display.

[0005] The light - emitting display device may be implemented as an organic light - emitting display device including an organic light - emitting diode element as a light - emitting element, an inorganic light - emitting display device including an inorganic semiconductor element as a light - emitting element, or a micro - light - emitting diode display device including an ultra - small light - emitting diode element (or a micro - light - emitting diode element) as a light - emitting element. At this time, in the micro - light - emitting diode display device, the micro - light - emitting diode element is bonded to the pixel electrode, and thus it can be suitable for reducing the resistance of the pixel electrode. Summary of the invention

[0006] Aspects of embodiments of the present disclosure provide a light - emitting element integrated with a lens structure.

[0007] However, the aspects of the present disclosure are not limited to the aspects described herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to one or more embodiments, a display device includes: a substrate; a light - emitting element above the substrate, and including a first semiconductor layer, an active layer, and a second semiconductor layer, the second semiconductor layer having an upper surface in a lens shape spaced apart from the active layer; and a common electrode above the light - emitting element, wherein side surfaces of the active layer and the second semiconductor layer are aligned.

[0009] The lens - shaped upper surface may be recessed downward or protruded upward.

[0010] The second semiconductor layer may include a lens portion and a body portion, the lens portion having an upper surface in a lens shape in contact with the common electrode, the body portion being below the lower surface of the lens portion, wherein side surfaces of the lens portion and the body portion are aligned.

[0011] The display device may further include a connection electrode between the substrate and the light-emitting element, and the diameter of the connection electrode is larger than the diameter of the light-emitting element.

[0012] The diameter of the connection electrode may be larger than the diameter of the lens portion.

[0013] The display device may further include an insulating layer that partially surrounds the light-emitting element.

[0014] The insulating layer may be on one side of the light-emitting element and on a portion of the substrate where no light-emitting element is located.

[0015] The display device may further include a reflective layer on the insulating layer and partially surrounding the light-emitting element.

[0016] The display device may further include a connection electrode between the substrate and the light-emitting element, and the diameter of the connection electrode is the same as the diameter of the light-emitting element and the diameter of the lens portion.

[0017] The display device may further include: a connection electrode between the substrate and the light-emitting element; and a pixel electrode between the substrate and the connection electrode.

[0018] The display device may further include a convex lens-shaped microlens above the common electrode, overlapping with the light-emitting element, and protruding downward.

[0019] The lower surface of the convex lens-shaped microlens may contact the common electrode.

[0020] The second semiconductor layer may have a plurality of downwardly recessed lens shapes.

[0021] According to one or more embodiments, a method of manufacturing a display device includes: stacking a first connection electrode layer on a second substrate on which a second semiconductor layer, an active layer, and a first semiconductor layer are sequentially grown; bonding the second substrate to a first substrate on which a pixel circuit is formed by melting the first connection electrode layer; removing the second substrate; forming a first mask pattern having a lens shape on the upper surface of the second semiconductor layer; etching the second semiconductor layer, the active layer, and the first semiconductor layer using the first mask pattern having a lens shape to form a light-emitting element including a second semiconductor layer having an upper surface with a lens shape; forming a second mask pattern surrounding the light-emitting element; etching the first connection electrode layer; and forming a common electrode on the light-emitting element, wherein the side surfaces of the active layer and the second semiconductor layer are aligned.

[0022] The lens-shaped upper surface may be recessed downward or protrude upward.

[0023] The method may further include: stacking a second connection electrode layer on a portion of the first substrate on which a pixel circuit is formed; and forming a connection electrode by melting and bonding the first connection electrode layer and the second connection electrode layer.

[0024] The method may further include: depositing an insulating layer on the light-emitting element and on a portion of the first substrate where the light-emitting element is not located; forming a planarization layer on a portion of the first substrate on which the insulating layer is formed, the planarization layer being lower than the height of the light-emitting element; and removing a portion of the insulating layer from a portion of the light-emitting element not covered by the planarization layer.

[0025] The method may further include: depositing a reflective material layer on a portion of the first substrate on which the insulating layer is stacked; and removing a portion of the reflective material layer from the horizontal surface of the first substrate to form a reflective layer partially surrounding one side of the light-emitting element.

[0026] According to one or more embodiments, a method of manufacturing a display device includes: stacking a connection electrode layer on a second substrate on which a second semiconductor layer, an active layer, and a first semiconductor layer are located; forming a light-emitting element by etching the active layer, the first semiconductor layer, and the connection electrode layer; bonding the second substrate on which the light-emitting element is formed to a carrier substrate; removing the second substrate; forming a lens-shaped mask pattern on the upper surface of the second semiconductor layer; etching the upper surface of the second semiconductor layer into a lens shape using the lens-shaped mask pattern, wherein the side portion of the active layer is aligned with the side portion of the second semiconductor layer; transferring the light-emitting element on the carrier substrate to a first substrate on which a pixel electrode is formed using an intermediate layer substrate; removing the intermediate layer substrate; and forming a common electrode on the light-emitting element.

[0027] The lens shape may be concave downward or convex upward.

[0028] The carrier substrate may include a transparent and mechanically stable support layer, and an adhesive layer on the support layer.

[0029] The intermediate layer substrate may include a transparent and mechanically stable support layer, and an adhesive layer on the support layer.

[0030] The method may further include: depositing an insulating layer on the light-emitting element and on a portion of the first substrate where the light-emitting element is not located; depositing a reflective material layer on a portion of the first substrate on which the insulating layer is stacked; forming a reflective layer surrounding one side of the light-emitting element by removing a portion of the reflective material layer above the horizontal surface of the first substrate; forming a planarization layer on the first substrate on which the insulating layer is formed, the planarization layer being lower than the height of the light-emitting element; and removing a portion of the insulating layer from the light-emitting element not covered by the planarization layer.

[0031] According to the display device according to the embodiment, the amount of light emitted from the active layer can be improved by adjusting the divergence angle or viewing angle of the light emitted from the active layer.

[0032] In addition, there is no need to add a lens structure formed of a separate organic layer or the like, thereby simplifying the manufacturing process of the display device.

[0033] In addition, there is no need for collimation between the light-emitting element and a separate lens structure.

[0034] In addition, during this process, there is no need to consider the stability, refractive index, transmittance, etc. of the material of the separately formed lens structure.

[0035] However, aspects of the present disclosure are not limited to the foregoing aspects, and various other aspects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a perspective view showing a display device according to one or more embodiments.

[0037] Figure 2 and Figure 3 is a plan view showing a display device according to one or more embodiments.

[0038] Figure 4 is a circuit diagram showing a first sub-pixel of a display panel according to one or more embodiments.

[0039] Figure 5 is a circuit diagram showing a first sub-pixel of a display panel according to one or more other embodiments.

[0040] Figure 6 is a cross-sectional view schematically showing a display area of a display device according to one or more embodiments.

[0041] Figure 7 is a detailed illustration of Figure 6 an enlarged view of the common electrode and the light-emitting element shown.

[0042] Figure 8 is a cross-sectional view schematically showing a display area of a display device according to one or more other embodiments.

[0043] Figure 9 is a detailed illustration of Figure 8 an enlarged view of the common electrode and the light-emitting element shown.

[0044] Figure 10A is a cross-sectional view schematically showing a display area of a display device according to one or more other embodiments, and Figure 10B is a detailed illustration of Figure 10AAn enlarged view of a common electrode and a light-emitting element shown therein.

[0045] Figure 11A and Figure 11B is a cross-sectional view schematically showing a display area of a display device according to one or more other embodiments.

[0046] Figure 12 is a cross-sectional view schematically showing a display area of a display device according to one or more other embodiments.

[0047] Figure 13 is a detailed illustration of Figure 12 an enlarged view of the common electrode and the light-emitting element shown.

[0048] Figure 14 is a cross-sectional view schematically showing a display area of a display device according to one or more other embodiments.

[0049] Figure 15 is a detailed illustration of Figure 14 an enlarged view of the common electrode and the light-emitting element shown.

[0050] Figure 16 is a cross-sectional view schematically showing a display device including a wavelength conversion layer and a color filter layer according to one or more other embodiments.

[0051] Figures 17 to 26 is a cross-sectional view showing a method of manufacturing a display device according to one or more embodiments.

[0052] Figures 27 to 30 is a cross-sectional view showing a method of manufacturing a display device according to one or more other embodiments.

[0053] Figures 31 to 43 is a cross-sectional view showing a method of manufacturing a display device according to one or more other embodiments.

[0054] Figure 44 is a diagram schematically showing a virtual reality device including a display device according to one or more embodiments.

[0055] Figure 45 is a diagram schematically showing a smart device including a display device according to one or more embodiments.

[0056] Figure 46 is a diagram schematically showing a vehicle including a display device according to one or more embodiments.

[0057] Figure 47 is a diagram schematically showing a transparent display device including a display device according to one or more embodiments. Detailed Description

[0058] Aspects of some embodiments of the present disclosure and methods of implementing the same can be more easily understood by referring to the detailed description of the embodiments and the accompanying drawings. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are redundant, not relevant or unrelated to the description of the embodiments, or unnecessary for those of ordinary skill in the art to fully understand the aspects of the present disclosure may be omitted. Unless otherwise stated, in all the drawings and the written description, the same reference numerals, characters, or combinations thereof represent the same elements, and thus, their repeated description may be omitted.

[0059] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as limited to the embodiments shown herein. The use of "can", "may", or "may not" when describing the embodiments corresponds to one or more embodiments of the present disclosure.

[0060] Considering the overall content of the present disclosure, those of ordinary skill in the art will understand that the present disclosure covers all modifications, equivalents, and substitutions within the concept and technical scope of the present disclosure. Each of the features of the embodiments of the present disclosure may be partially or wholly combined with each other, and various close combinations and operations are technically possible, and each embodiment may be implemented independently of each other, or may be implemented in association with each other, unless otherwise stated or implied.

[0061] In the drawings, for clarity and / or for the purpose of description, the relative dimensions of elements, layers, and regions may be exaggerated. Additionally, cross-hatching and / or shading are generally used in the drawings to make the boundaries between adjacent elements clear. Thus, unless otherwise stated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, dimension, ratio, commonality between the illustrated elements, and / or any other characteristic, attribute, property, etc. of the elements.

[0062] Various embodiments are described herein with reference to cross-sectional views that are schematic illustrations of embodiments and / or intermediate structures. As such, deviations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Additionally, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of the present disclosure. Accordingly, the embodiments disclosed herein should not be construed as limited to the shown shapes of the elements, layers, or regions, but will include, for example, shape deviations resulting from manufacturing.

[0063] For example, an implantation region shown as rectangular will typically have rounded or curved features and / or a gradient of implantation concentration at its edges, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs.

[0064] For ease of explanation, spatial relative terms such as "below", "beneath", "lower", "bottom", "under", "above", "upper", "top" etc. may be used herein to describe the relationship of one element or feature shown in the figures to another element or feature. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as "below", "beneath" or "under" another element or feature will then be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "beneath" can encompass both an upper and a lower orientation. The device may have additional orientations (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first portion is described as being disposed "on" a second portion, this indicates that the first portion is disposed at the upper or lower side of the second portion, and is not limited to the upper side based on the direction of gravity.

[0065] In addition, the phrase "in a plan view" means when the object portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section obtained by vertically cutting the object portion is viewed from the side. The term "overlap" or "overlapping" means that a first object can be above or below, or on one side of, a second object, and means that the second object can be above or below, or on one side of, the first object. Additionally, the term "overlap" can include stacking, facing or facing towards, extending throughout, covering or partially covering, or any other suitable term as would be understood and appreciated by a person of ordinary skill in the art. The expression "not overlapping" can include meanings such as "separate from", "set beside", "offset from", and any other suitable equivalents as would be understood and appreciated by a person of ordinary skill in the art. The terms "face" and "face towards" can mean that a first object can be directly or indirectly opposite a second object. In the case where a third object is interposed between a first object and a second object, the first object and the second object can be understood to be indirectly opposite each other but still face each other.

[0066] It will be understood that when an element, layer, region or component is referred to as being "formed on", "on", "connected to" or "(operatively or communicatively) coupled to" another element, layer, region or component, it can be formed directly on the other element, layer, region or component, or directly on the other element, layer, region or component, or directly connected to or directly coupled to the other element, layer, region or component, or it can be formed indirectly on the other element, layer, region or component, or indirectly on the other element, layer, region or component, or indirectly connected to or indirectly coupled to the other element, layer, region or component such that there can be one or more intervening elements, layers, regions or components. Additionally, this can generally mean a direct or indirect connection or coupling, and an integral or non-integral connection or coupling. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, it can be directly electrically connected or directly electrically coupled to the other layer, region and / or component, or there can be one or more intervening layers, regions or components. One or more intervening components can include switches, resistors, capacitors, etc. When describing an embodiment, unless explicitly described as a direct connection, the expression of connection indicates an electrical connection, and "direct connection / direct coupling" or "directly on" means that one component is directly connected or coupled to another component or directly on another component without an intermediate component.

[0067] Furthermore, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the forming direction is not limited to the upward direction, but includes forming the part on a side surface or in the downward direction. Conversely, when a part of a layer, film, region, plate, etc. is formed "below" another part, this includes not only the case where the part is "directly under" the other part, but also the case where there is another part between the part and the other part. Meanwhile, other expressions describing the relationship between components, such as "between" and "directly between" or "adjacent to" and "directly adjacent to", can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0068] For the purposes of this disclosure, when following a list of elements, expressions such as “at least one of...,” or “any one of...,” or “one or more of...” modify the elements of the entire list rather than individual elements of the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, or only Y, or only Z, or any combination of two or more of X, Y, and Z (such as, by way of example, XYZ, XY, YZ, and XZ), or any variation thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or,” and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, when preceding or following a list of elements, expressions such as “at least one of...,” “a plurality of,” “one of...,” and other prepositional phrases modify the elements of the entire list rather than individual elements of the list.

[0069] It will be understood that although the terms “first,” “second,” “third,” etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms do not correspond to a particular order, position, or priority, but are only used to distinguish one element, member, component, region, zone, layer, section, or part from another element, member, component, region, zone, layer, section, or part. Thus, without departing from the spirit and scope of this disclosure, a first element, first component, first region, first layer, or first section described below can be referred to as a second element, second component, second region, second layer, or second section. Designating an element as a “first” element may not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc. may also be used herein to distinguish different categories or different groups of elements. For the sake of brevity, the terms “first,” “second,” etc. may respectively denote “first category (or first group),” “second category (or second group),” etc.

[0070] In an example, the first direction DR1, the second direction DR2, and / or the third direction DR3 are not limited to the three axes of a rectangular coordinate system (such as, the x-axis, the y-axis, and the z-axis), and can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0071] The terms used herein are for the purpose of describing embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to also include the plural forms, and the plural forms are intended to also include the singular form, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "comprises," "comprising," "have," "having," "includes," and "including" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0072] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order.

[0073] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as approximating terms and not as terms of degree, and are intended to account for the inherent deviations in the values being measured or calculated that would be recognized by a person of ordinary skill in the art. For example, "substantially" can include a range of + / - 5% of the corresponding value. Given the measurements being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "about" or "approximately" includes the stated value and means within an acceptable deviation of the particular value determined by a person of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within + / - 30%, + / - 20%, + / - 10%, + / - 5% of the stated value. Additionally, "may" when used in describing embodiments of the present disclosure means "one or more embodiments of the present disclosure."

[0074] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0075] Figure 1 is a perspective view showing a display device according to one or more embodiments.

[0076] Reference Figure 1, the display device 10 is a device for displaying videos or still images, such as mobile phones, smart phones, tablet personal computers, and portable electronic devices (such as smart watches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigators, and ultra-mobile personal computers (UMPCs)), and is a display screen for various products such as televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices.

[0077] The display device 10 may be a light-emitting display device, such as an organic light-emitting display device using organic light-emitting diodes, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a miniaturized light-emitting display device using micro or nano light-emitting diodes (micro LED or nano LED). Hereinafter, the description focuses on the case where the display device 10 is a micro light-emitting display device, but the present disclosure is not limited thereto. On the other hand, for ease of explanation, ultra-small light-emitting diodes are described as micro light-emitting diodes herein.

[0078] The display device 10 includes a display panel 100, a display driving circuit 200, and a circuit board 300.

[0079] The display panel 100 may be formed as a rectangular plane having short side edges in a first direction DR1 and long side edges in a second direction DR2 intersecting the first direction DR1. The corners where the short side edges in the first direction DR1 and the long side edges in the second direction DR2 meet may be rounded to have a curvature (e.g., a predetermined curvature), or may be formed as right angles. The planar shape of the display panel 100 is not limited to a rectangle and may be formed as other polygonal shapes, circular shapes, or elliptical shapes. The display panel 100 may be flat, but is not limited thereto. For example, the display panel 100 may include curved portions having a constant curvature or a varying curvature formed at the left and right ends of the display panel 100. Additionally, the display panel 100 may be formed to be flexible so as to be bendable, curvable, foldable, or rollable.

[0080] The display panel 100 may include a main area MA and a sub-area SBA.

[0081] The main area MA may include a display area DA for displaying an image and a non-display area NDA that is a peripheral area of the display area DA. The display area DA may include a plurality of pixels for displaying an image. For example, a pixel may include a first sub-pixel that emits a first light, a second sub-pixel that emits a second light, and a third sub-pixel that emits a third light.

[0082] The sub-area SBA may protrude from one side of the main area MA in the second direction DR2. Although Figure 1The sub-region SBA is shown expanded, but the sub-region SBA can be bent, and in this case, the sub-region SBA can be located on the bottom surface of the display panel 100. When the sub-region SBA is bent, it can overlap with the main region MA in the third direction DR3, which is the thickness direction of the display panel 100. The display driving circuit 200 can be located in the sub-region SBA.

[0083] The display driving circuit 200 can generate signals and voltages for driving the display panel 100. The display driving circuit 200 can be formed as an integrated circuit (IC), and can be attached to the display panel 100 using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit 200 can be connected to the circuit board 300 using a chip on film (COF) method.

[0084] The circuit board 300 can be attached to one end of the sub-region SBA of the display panel 100. In this way, the circuit board 300 can be electrically connected to the display panel 100 and the display driving circuit 200. The display panel 100 and the display driving circuit 200 can receive digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 can be a flexible film such as a flexible printed circuit board, a rigid printed circuit board, or a chip on film.

[0085] Figure 2 and Figure 3 are plan views showing a display device according to one or more embodiments. Figure 2 The sub-region SBA is shown expanded without being bent. Figure 3 The sub-region SBA is shown bent.

[0086] Reference Figure 2 and Figure 3 , the display panel 100 can include a main region MA and a sub-region SBA.

[0087] The main region MA can include a display region DA for displaying an image, and a non-display region NDA that is a peripheral region of the display region DA. The display region DA can occupy most of the main region MA. The display region DA can be located at the center of the main region MA.

[0088] The non-display region NDA can be placed adjacent to the display region DA. The non-display region NDA can be a region outside the display region DA. The non-display region NDA can be arranged to surround the display region DA. The non-display region NDA can be an edge region of the display panel 100.

[0089] The first scan driving part SDC1 and the second scan driving part SDC2 may be located in the non-display area NDA. The first scan driving part SDC1 is located on one side (e.g., the left side) of the display panel 100, and the second scan driving part SDC2 is located on the other side (e.g., the right side) of the display panel 100. However, the present disclosure is not limited thereto. Each of the first scan driving part SDC1 and the second scan driving part SDC2 may be electrically connected to the display driving circuit 200 through scan fan-out lines. Each of the first scan driving part SDC1 and the second scan driving part SDC2 may receive a scan control signal from the display driving circuit 200, may generate a scan signal according to the scan control signal, and may output them to the scan lines.

[0090] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. The length of the sub-region SBA in the second direction DR2 may be less than the length of the main region MA in the second direction DR2. The length of the sub-region SBA in the first direction DR1 is less than the length of the main region MA in the first direction DR1, or may be substantially equal to the length of the main region MA in the first direction DR1. The sub-region SBA may be curved and may be located at the lower part of the display panel 100. In this case, the sub-region SBA may overlap the main region MA in the third direction DR3.

[0091] The sub-region SBA may include a connection region CA, a pad region PA, and a bending region BA.

[0092] The connection region CA is a region that protrudes from one side of the main region MA in the second direction DR2. One side of the connection region CA may contact the non-display area NDA of the main region MA, and the other side of the connection region CA may contact the bending region BA.

[0093] The pad region PA is a region where the pads PD and the display driving circuit 200 are arranged. The display driving circuit 200 may be attached to the driving pads of the pad region PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be attached to the pads PD of the pad region PA using a conductive adhesive member such as an anisotropic conductive film. One side of the pad region PA may contact the bending region BA.

[0094] The bending region BA is a region that is bent. When the bending region BA is bent, the pad region PA may be located below the connection region CA and below the main region MA. The bending region BA may be located between the connection region CA and the pad region PA. One side of the bending region BA may contact the connection region CA, and the other side of the bending region BA may contact the pad region PA.

[0095] Figure 4It is a circuit diagram showing the first sub-pixel of a display panel according to one or more embodiments.

[0096] Reference Figure 4 , the first sub-pixel SPX1 according to one or more embodiments may be connected to scan lines GWL, GIL, GCL, and GBL, a light-emitting line EL, and a data line DL. For example, the first sub-pixel SPX1 may be connected to a write scan line GWL, an initialization scan line GIL, a control scan line GCL, a bias scan line GBL, a light-emitting line EL, and a data line DL.

[0097] The first sub-pixel SPX1 according to one or more embodiments includes a driving transistor DT, a switching element, a capacitor C1, and a first light-emitting element LE1. The switching element includes a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, and a sixth transistor ST6.

[0098] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls the drain-source current (hereinafter referred to as "driving current") flowing between the first electrode and the second electrode according to the data voltage applied to the gate electrode.

[0099] The first light-emitting element LE1 may be a micro light-emitting diode. The first light-emitting element LE1 emits light according to the driving current. The amount of light emitted from the first light-emitting element LE1 may be proportional to the driving current. The anode electrode of the first light-emitting element LE1 may be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode electrode of the first light-emitting element LE1 may be connected to a second power supply line VSL to which a second power supply voltage is applied.

[0100] The capacitor C1 is formed between the gate electrode of the driving transistor DT and a first power supply line VDL to which a first power supply voltage is applied. The first power supply voltage may be at a level higher than the second power supply voltage. One electrode of the capacitor C1 may be connected to the gate electrode of the driving transistor DT, and the other electrode may be connected to the first power supply line VDL.

[0101] As Figure 4 shown, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT may all be formed as p-type MOSFETs. In this case, the active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT may be formed of polysilicon or an oxide semiconductor.

[0102] The gate electrode of the second transistor ST2 may be connected to the write scan line GWL, and the gate electrode of the first transistor ST1 may be connected to the control scan line GCL. The gate electrode of the third transistor ST3 may be connected to the initialization scan line GIL, and the gate electrode of the fourth transistor ST4 may be connected to the bias scan line GBL. Since the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, they can be turned on when a scan signal with a low gate voltage and an emission signal with a low gate voltage are respectively applied to the control scan line GCL, the initialization scan line GIL, the write scan line GWL, the bias scan line GBL, and the emission line EL. One electrode of the third transistor ST3 and one electrode of the fourth transistor ST4 may be connected to the initialization voltage line VIL.

[0103] Figure 5 is a circuit diagram showing a first sub-pixel of a display panel according to one or more other embodiments.

[0104] Reference Figure 5 , the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed of p-type MOSFETs, and the first transistor ST1 and the third transistor ST3 may be formed as n-type MOSFETs. The active layer of each of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 formed as p-type MOSFETs may be formed of polysilicon, and the active layer of each of the first transistor ST1 and the third transistor ST3 formed as n-type MOSFETs may be formed of an oxide semiconductor. In this case, the transistors formed of polysilicon and the transistors formed of an oxide semiconductor may be arranged in different layers.

[0105] Since the first transistor ST1 and the third transistor ST3 are formed as n-type MOSFETs, the first transistor ST1 can be turned on when a control scan signal with a high gate voltage is applied to the control scan line GCL, and the third transistor ST3 can be turned on when an initialization scan signal with a high gate voltage is applied to the initialization scan line GIL. In comparison, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, so they can be turned on when a scan signal with a low gate voltage and an emission signal with a low gate voltage are respectively applied to the write scan line GWL, the bias scan line GBL, and the emission line EL.

[0106] Optionally, Figure 4The fourth transistor ST4 therein may be formed of an n-type MOSFET. In this case, the active layer of each fourth transistor ST4 may be formed of an oxide semiconductor. When the fourth transistor ST4 is formed of an n-type MOSFET, it may be turned on when a gate high voltage bias scan signal is applied to the bias scan line GBL.

[0107] Optionally, in one or more embodiments, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT may all be formed as n-type MOSFETs.

[0108] Meanwhile, the circuit diagrams of the second sub-pixel and the third sub-pixel according to one or more embodiments are substantially the same as the circuit diagram of the first sub-pixel SPX1 described in conjunction with Figure 4 and Figure 5 and thus the description thereof will be omitted.

[0109] Figure 6 is a cross-sectional view schematically showing a display area of a display device according to one or more embodiments. Figure 7 is a detailed illustration of Figure 6 an enlarged view of the common electrode and the light-emitting element shown.

[0110] Referring to Figure 6 and Figure 7 , the display panel 100 may include a semiconductor circuit board 110 and a light-emitting element layer 120.

[0111] The semiconductor circuit board 110 may include a plurality of pixel circuit portions PXC, pixel electrodes PE, and an interlayer insulating layer 111.

[0112] The first substrate SUB1 may be a silicon wafer substrate. The first substrate SUB1 may be made of single crystal silicon.

[0113] Each of the plurality of pixel circuit portions PXC may be located on the first substrate SUB1 (as used herein, "located on..." may mean "above..."). Each of the plurality of pixel circuit portions PXC may include a complementary metal oxide semiconductor (CMOS) circuit formed using a semiconductor process. Each of the plurality of pixel circuit portions PXC may include at least one transistor formed by a semiconductor process. In addition, each of the plurality of pixel circuit portions PXC may further include at least one capacitor formed by a semiconductor process.

[0114] A plurality of pixel circuit portions PXC may be located in the display area DA. Each of the plurality of pixel circuit portions PXC may be connected to a corresponding pixel electrode PE. Each of the plurality of pixel circuit portions PXC may apply a pixel voltage or an anode voltage to the pixel electrode PE.

[0115] Each of the pixel electrodes PE may be located on a corresponding pixel circuit portion PXC. Each of the pixel electrodes PE may be an exposed electrode exposed from the pixel circuit portion PXC. That is, each of the pixel electrodes PE may protrude from the top surface of the pixel circuit portion PXC. Each of the pixel electrodes PE may be formed integrally with the pixel circuit portion PXC. Each of the pixel electrodes PE may receive a pixel voltage or an anode voltage from the pixel circuit portion PXC. The pixel electrode PE may include copper (Cu), titanium (Ti), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof. Additionally, the pixel electrode PE may have a multi-layer structure in which two or more metal layers are stacked. For example, the pixel electrode PE may have a two-layer structure in which a copper layer is stacked on a titanium layer, but is not limited thereto.

[0116] The interlayer insulating layer 111 may be located on the first substrate SUB1 on which the pixel electrode PE is not located. The interlayer insulating layer 111 is located between the pixel electrodes PE, and the interlayer insulating layer 111 may be formed in a multi-step structure.

[0117] The interlayer insulating layer 111 may be formed of an inorganic film such as a silicon oxide film (SiO2), an aluminum oxide film (Al2O3), or a hafnium oxide film (HfO x )

[0118] The connection electrode 112 may be located on the pixel electrode PE. The connection electrode 112 may be used as a bonding metal for bonding the pixel electrode PE and the light-emitting element LE during the manufacturing process. The connection electrode 112 may be used to apply a light-emitting signal to the light-emitting element LE by bonding to the pixel electrode PE. The light-emitting element LE may be connected to at least one connection electrode 112.

[0119] According to one or more embodiments, when the light-emitting element LE is electrically connected to the pixel electrode PE in the display panel 100, the connection electrode 112 may reduce the resistance between the light-emitting element LE and the contact electrode. The connection electrode 112 may include a conductive metal. For example, the connection electrode 112 may include at least one of gold (Au), copper (Cu), tin (Sn), titanium (Ti), aluminum (Al), and silver (Ag). For example, the connection electrode 112 may include an alloy of gold and tin in a ratio of 9:1, 8:2, or 7:3, or may include an alloy of copper, silver, and tin (SAC305).

[0120] In one or more embodiments, the ohmic contact layer may further be located on the connection electrode 112. The ohmic contact layer may be located between the connection electrode 112 and the first semiconductor layer SEM1. The ohmic contact layer may be an ohmic connection electrode. However, the electrode is not limited thereto, and may be a Schottky connection electrode. The ohmic contact layer may include ITO. However, the present disclosure is not limited thereto, and the ohmic contact layer may include at least one selected from gold (Au), copper (Cu), tin (Sn), titanium (Ti), aluminum (Al), and silver (Ag), and may be formed of an alloy thereof or a multi-layer structure thereof.

[0121] The connection electrode 112 may have a diameter W2 larger than the diameter W1 of the light-emitting element LE. For example, the connection electrode 112 may protrude beyond the light-emitting element LE located on the connection electrode 112.

[0122] The light-emitting element layer 120 may include a light-emitting element LE, an insulating layer INS, a planarization layer 113, and a common electrode CE.

[0123] Each of the light-emitting elements LE may be located on the connection electrode 112. The light-emitting element LE may overlap with the pixel electrode PE. The light-emitting element LE may be a vertical light-emitting diode element extending in the third direction DR3. That is, the length of the light-emitting element LE in the third direction DR3 may be longer than the length in the horizontal direction. The length in the horizontal direction indicates the length in the first direction DR1 or the length in the second direction DR2. For example, the length of the light-emitting element LE in the third direction DR3 may be about 1 μm to about 5 μm. The light-emitting element LE may have a top surface formed in a lens shape. The lens shape may bulge upward.

[0124] Reference Figure 7 , the light-emitting element LE may be a micro light-emitting diode element or a nano light-emitting diode. The light-emitting element LE includes a first semiconductor layer SEM1, an electron blocking layer EBL, an active layer MQW, a superlattice layer SLT, and a second semiconductor layer SEM2 in the third direction DR3. The first semiconductor layer SEM1, the electron blocking layer EBL, the active layer MQW, the superlattice layer SLT, and the second semiconductor layer SEM2 may be sequentially stacked in the third direction DR3. The side surfaces of the first semiconductor layer SEM1, the electron blocking layer EBL, the active layer MQW, the superlattice layer SLT, and the second semiconductor layer SEM2 may be located on the same line.

[0125] The light-emitting element LE may have a cylindrical shape, a disk shape, or a rod shape in which the width is longer than the height. However, the present disclosure is not limited thereto, and the light-emitting element LE may have a shape such as a rod, a wire, a tube, etc., or a polygonal shape such as a cube, a rectangular cube, a hexagonal column, etc.

[0126] The first semiconductor layer SEM1 may be located on the connection electrode 112. The first semiconductor layer SEM1 may be doped with a dopant of a first conductivity type, such as Mg, Zn, Ca, or Ba. For example, the first semiconductor layer SEM1 may be p-GaN doped with p-type Mg. The thickness of the first semiconductor layer SEM1 may be from about 30 nm to about 200 nm.

[0127] The electron blocking layer EBL may be located on the first semiconductor layer SEM1. The electron blocking layer EBL may be a layer that inhibits or prevents too many electrons from flowing into the active layer MQW. For example, the electron blocking layer EBL may be p-AlGaN doped with p-type Mg. The thickness of the electron blocking layer EBL may be from about 10 nm to about 50 nm. The electron blocking layer EBL may be omitted.

[0128] The active layer MQW may be located on the electron blocking layer EBL. The active layer MQW may emit light by recombining electron-hole pairs according to an electrical signal applied via the first semiconductor layer SEM1 and the second semiconductor layer SEM2. The active layer MQW may emit first light having a central wavelength range of from about 450 nm to about 495 nm, that is, light in the blue wavelength band, but is not limited thereto.

[0129] The active layer MQW may include a single quantum well structure or a multi-quantum well structure. If the active layer MQW includes a material having a multi-quantum well structure, it may be a stacked structure having a plurality of well layers and barrier layers alternating with each other. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto. The thickness of the well layer may be from about 1 nm to about 4 nm, and the thickness of the barrier layer may be from about 3 nm to about 10 nm.

[0130] Optionally, the active layer MQW may be in a structure in which a semiconductor material having a large bandgap and a semiconductor material having a small bandgap are alternately stacked, and depending on the wavelength band of the emitted light, the active layer MQW may include other group III-V semiconductor materials. The light emitted by the active layer MQW is not limited to the first light (light in the blue wavelength band), but may be second light (light in the green wavelength band) or third light (light in the red wavelength band) in some cases.

[0131] The superlattice layer SLT may be located on the active layer MQW. The superlattice layer SLT may be a layer for relieving stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer SLT may be formed of InGaN or GaN. The thickness of the superlattice layer SLT may be from about 50 nm to about 200 nm. The superlattice layer SLT may be omitted.

[0132] The second semiconductor layer SEM2 may be located on the superlattice layer SLT. The second semiconductor layer SEM2 may be doped with dopants of a second conductivity type, such as Si, Ge, Sn, Se, etc. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si. The thickness of the second semiconductor layer SEM2 may be about 500 nm to about 1 μm.

[0133] The top surface of the second semiconductor layer SEM2 may have a lens shape. For example, the lens shape may bulge upward. The top surface of the second semiconductor layer SEM2 may contact the common electrode CE and be spaced apart from the active layer MQW.

[0134] For ease of explanation, the upper portion of the top surface of the second semiconductor layer SEM2 that defines the lens shape may be referred to as the lens portion SEM2-1, and the lower portion of the second semiconductor layer SEM2 that supports the lens portion SEM2-1 below its lower surface may be referred to as the body portion SEM2-2. The diameter of the lens portion SEM2-1 may be the same as the diameter of the body portion SEM2-2. The lens portion SEM2-1 and the body portion SEM2-2 may be arranged in a third direction DR3 such that their side surfaces are in the same line (e.g., aligned), but are not limited thereto. In addition, the material of the lens portion SEM2-1 may be the same as the material of the body portion SEM2-2.

[0135] The second semiconductor layer SEM2 has a lens-shaped top surface, thereby reducing the divergence angle or viewing angle of the light emitted from the active layer MQW. Since the top surface of the second semiconductor layer SEM2 is formed in a lens shape, a lens structure formed of a separate organic layer or the like is not required. This simplifies the manufacturing process of the display device. Therefore, forming the top surface of the second semiconductor layer SEM2 in a lens shape is advantageous in terms of process time and cost compared to forming a separate lens structure. In addition, since the second semiconductor layer SEM2 has a lens-shaped top surface, collimation between the light-emitting element LE and a separate lens structure is not required. Furthermore, forming the top surface of the second semiconductor layer SEM2 in a lens shape does not require consideration of the stability, refractive index, transmittance, etc. of the material of the separately formed lens structure.

[0136] Referring again to Figure 6 and Figure 7 , the insulating layer INS may be located on one side of each of the light-emitting elements LE and on a part of the top surface and the side portion of the connection electrode 112. In addition, the insulating layer INS may be located on the interlayer insulating layer 111 on which no light-emitting element LE is located.

[0137] In addition, the insulating layer INS may be made of, such as, a silicon oxide film (SiO2), an aluminum oxide film (Al2O3), or a hafnium oxide film (HfOx formation of an inorganic film, but not limited thereto.

[0138] The planarization layer 113 may be located on each side of the light-emitting element LE. The planarization layer 113 may be a layer for planarizing the steps caused by the light-emitting element LE. The top surface of the planarization layer 113 may be flat. The planarization layer 113 may be formed of an organic film such as an acrylic resin film, an epoxy resin film, a phenolic resin film, a polyamide resin film, a polyimide resin film, or the like.

[0139] Since the common electrode CE is entirely located on the first substrate SUB1 and a common voltage is applied, it may include a material having a low resistance. The common electrode CE may be located on the top surface of each of the light-emitting elements LE and on the top surface of the planarization layer 113. The common electrode CE may directly contact the lens-shaped second semiconductor layer SEM2.

[0140] In addition, the common electrode CE may be formed thin to facilitate light transmission. The common electrode CE may include a transparent conductive material. For example, the common electrode CE may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO). The thickness of the common electrode CE may be about 10 Å to about 200 Å, but not limited thereto.

[0141] Figure 8 is a cross-sectional view schematically showing a display area of a display device according to one or more other embodiments. Figure 9 is shown in detail Figure 8 an enlarged view of the common electrode and the light-emitting element shown.

[0142] Figure 8 and Figure 9 and Figure 6 and Figure 7 The embodiment of is different in that the light-emitting element LE further includes a reflective layer REF. Hereinafter, with reference to Figure 8 and Figure 9 the description will focus on the differences from the embodiments of Figure 6 and Figure 7 the embodiment of.

[0143] The reflective layer REF may be located on the insulating layer INS on each side of the light-emitting element LE, on the top surface / above the connection electrode 112 that does not overlap with the light-emitting element LE, and on one side of the connection electrode 112 (for example, and the insulating layer INS is between the reflective layer REF and each side of the light-emitting element LE, the top surface of the connection electrode 112, and one side of the connection electrode 112).

[0144] The reflective layer REF is used to reflect the light emitted from the light-emitting element LE that travels downward, leftward, and laterally but not upward. The reflective layer REF may include a highly reflective metal material such as aluminum (Al). The thickness of the reflective layer REF may be about 0.1 μm, but is not limited thereto.

[0145] Figure 10A is a cross-sectional view schematically showing a display area of a display device according to one or more other embodiments, and Figure 10B shows in detail Figure 10A an enlarged view of the common electrode and the light-emitting element shown in

[0146] Figure 10A and Figure 10B and Figure 6 and Figure 7 The embodiments of Figure 10A and Figure 10B differ in that the lens shape on the top surface of the light-emitting element LE is recessed downward. Hereinafter, with reference to Figure 6 and Figure 7 the description will focus on the differences from the embodiments of

[0147] With reference to Figure 10A and Figure 10B the top surface of the light-emitting element LE may be lens-shaped. The top surface of the light-emitting element LE has a recessed shape toward the first substrate SUB1. The common electrode CE has a recessed shape that is recessed downward along the top surface of the light-emitting element LE.

[0148] The light-emitting element LE may include a first semiconductor layer SEM1, an electron blocking layer EBL, an active layer MQW, a superlattice layer SLT, and a second semiconductor layer SEM2.

[0149] The second semiconductor layer SEM2 may have a top surface with a recessed lens shape, thereby converging the light emitted from the active layer MQW and improving the forward light emission effect. In another variation, the reflective layer may be located on the insulating layer INS on one side of each of the light-emitting elements LE, on the top surface of the connection electrode 112 that does not overlap with the light-emitting element LE, and on one side of the connection electrode 112. As described with reference to Figure 9 the reflective layer may reflect the light emitted from the light-emitting element LE that travels downward, leftward, and laterally but not upward.

[0150] Figure 11A and Figure 11B are cross-sectional views schematically showing a display area of a display device according to one or more other embodiments.

[0151] Figure 11A corresponding to Figure 10A andFigure 10B One or more embodiments differ in that the microlens MLA is located on the top surface of the light-emitting element LE.

[0152] Hereinafter, the description with reference to Figure 11A will focus on the differences from the Figure 10A and Figure 10B embodiments.

[0153] Figure 11A The top surface of the light-emitting element LE in can be lens-shaped. The top surface of the light-emitting element LE has a concave shape facing the first substrate SUB1. The common electrode CE has a concave shape that is recessed downward along the top surface of the light-emitting element LE. The microlens MLA can be located on the common electrode CE. The microlens MLA can have a curvature corresponding to the curvature of the common electrode CE. The curvature of the microlens MLA can be the same as the curvature of the common electrode CE. The microlens MLA can be in direct contact with the common electrode CE on the common electrode CE. By adjusting the radius of curvature and height of each microlens MLA, the focal point of each microlens MLA can be focused on the corresponding pixel.

[0154] The microlens MLA can be formed to fill the recessed groove of the common electrode CE on the top surface of the light-emitting element LE and can protrude upwardly. The microlens MLA can have a convex lens shape that protrudes convexly on the top surface of the light-emitting element LE.

[0155] The microlens MLA can include an organic or inorganic material such as polydimethylsiloxane (PDMS), polymethyl methacrylate (PMMA), photoresist, silicon dioxide (SiO2), etc.

[0156] Figure 11B Differences from Figure 11A are that a bent portion is formed on the top surface of the light-emitting element LE.

[0157] In Figure 11B it is shown that two concave lens shapes are formed on the top surface of the light-emitting element LE, but the present disclosure is not limited thereto, and more downwardly recessed lens shapes can be formed on the top surface of the light-emitting element LE. Each of the plurality of concave lens shapes has a curvature, and the curvature of each of the plurality of concave lens shapes can be the same, but is not limited thereto, and lens shapes with different curvatures can be formed. For example, when there are three downwardly recessed lens shapes, the curvature of the lens shape located at the center can be the largest, and the curvatures of the lens shapes located on both sides can be relatively small.

[0158] Together with the downwardly recessed lens shape on the top surface of the light-emitting element LE, the common electrode CE may also have a downwardly recessed lens shape on the light-emitting element LE. Further, the microlens MLA may be formed to fill the recessed groove on the common electrode CE that overlaps with the top surface of the light-emitting element LE, and may protrude upwardly.

[0159] As Figure 11A and Figure 11B shown, adding a separate microlens MLA to the top surface of the light-emitting element LE may have the effect of controlling the direction of light emission.

[0160] Figure 12 is a cross-sectional view schematically showing a display area of a display device according to one or more other embodiments. Figure 13 is a detailed illustration of Figure 12 the enlarged view of the common electrode and the light-emitting element shown.

[0161] Figure 12 and Figure 13 In contrast to Figure 8 and Figure 9 the embodiment, the diameter W2 of the connection electrode 112 is the same as the diameter W1 of the light-emitting element LE. Hereinafter, with reference to Figure 12 and Figure 13 the description will focus on the differences from Figure 8 and Figure 9 the embodiment.

[0162] With reference to Figure 12 and Figure 13 , the diameter W1 of the light-emitting element LE and the diameter W2 of the connection electrode 112 may be the same. The side surface of the light-emitting element LE and the side surface of the connection electrode 112 may be completely aligned in the third direction DR3.

[0163] The light-emitting element LE may include a first semiconductor layer SEM1, an electron blocking layer EBL, an active layer MQW, a superlattice layer SLT, and a second semiconductor layer SEM2.

[0164] The side portions of the first semiconductor layer SEM1, the electron blocking layer EBL, the active layer MQW, the superlattice layer SLT, the second semiconductor layer SEM2, and the connection electrode 112 may be located on the same line.

[0165] The side portions of the first semiconductor layer SEM1, the electron blocking layer EBL, the active layer MQW, the superlattice layer SLT, the second semiconductor layer SEM2, and the connection electrode 112 may be arranged on a line in the third direction DR3.

[0166] The second semiconductor layer SEM2 may include a lens portion SEM2-1 and a body portion SEM2-2. The diameter of the lens portion SEM2-1 may be the same as the diameter of the body portion SEM2-2. The lens portion SEM2-1 and the body portion SEM2-2 may be arranged in a line in the third direction DR3, but not limited thereto. In addition, the side surface of the lens portion SEM2-1 may be arranged in a line with the side portion of the connection electrode 112 in the third direction DR3.

[0167] The height of the reflective layer REF may be lower than the height of the planarization layer 113. The height of the reflective layer REF may be defined as the distance from the top surface of the interlayer insulating layer 111 to the top surface of the reflective layer REF, and the height of the planarization layer 113 may be defined as the distance from the top surface of the interlayer insulating layer 111 to the top surface of the planarization layer 113. Accordingly, the common electrode CE and the reflective layer REF may not contact each other.

[0168] Figure 14 is a cross-sectional view schematically showing a display area of a display device according to one or more other embodiments. Figure 15 is shown in detail Figure 14 an enlarged view of the common electrode and the light-emitting element shown.

[0169] Figure 14 and Figure 15 with Figure 12 and Figure 13 The embodiment of is different in that the lens shape of the top surface of the light-emitting element LE is recessed in the downward direction. In addition, Figure 14 and Figure 15 The embodiment of is different from the embodiments of FIGS. 10 and 11 in that the diameter of the connection electrode 112 is the same as the diameter of the light-emitting element LE.

[0170] Hereinafter, with reference to Figure 14 and Figure 15 the description will focus on the differences from Figure 12 and Figure 13 the embodiments of.

[0171] With reference to Figure 14 and Figure 15 the top surface of the light-emitting element LE may have a lens shape. The top surface of the light-emitting element LE has a recessed shape toward the first substrate SUB1. The common electrode CE has a shape that is recessed downward along the top surface of the light-emitting element LE.

[0172] The light-emitting element LE may include a first semiconductor layer SEM1, an electron blocking layer EBL, an active layer MQW, a superlattice layer SLT, and a second semiconductor layer SEM2.

[0173] The top surface of the second semiconductor layer SEM2 may have a downwardly concave lens shape, so as to converge the light emitted from the active layer MQW and improve the forward light emission effect. In another variation, the reflective layer may be located on the insulating layer INS on one side of each of the light-emitting elements LE and on one side of the connection electrode 112. As described in reference Figure 13 , the height of the reflective layer may be lower than the height of the planarization layer 113. Therefore, the common electrode CE and the reflective layer may not contact each other.

[0174] Figure 16 is a cross-sectional view schematically showing a display device including a wavelength conversion layer and a color filter layer according to one or more other embodiments.

[0175] Reference Figure 16 , the display device 10 may further include a semiconductor circuit board 110, a light-emitting element layer 120, a wavelength conversion layer QDL, and a color filter layer.

[0176] Since the semiconductor circuit board 110 and the light-emitting element layer 120 are the same as the semiconductor circuit board 110 and the light-emitting element layer 120 described in Figure 6 and Figure 7 , the overlapping description will be omitted.

[0177] The light-emitting element layer 120 may include a light-emitting element LE, an insulating layer INS, a common electrode CE, and a planarization layer 113.

[0178] Each of the plurality of pixels may include a plurality of light-emitting regions EA1, EA2, and EA3 that emit light. Each of the plurality of light-emitting regions EA1, EA2, and EA3 may include a light-emitting element LE that emits first light.

[0179] Each of the first light-emitting regions EA1 represents a region that emits first light. Each of the first light-emitting regions EA1 may output the first light output from the light-emitting element LE as it is. The first light may be light in the blue wavelength band. The blue wavelength band may be from about 370 nm to about 460 nm, but the embodiments of the present specification are not limited thereto.

[0180] In each of the first light-emitting regions EA1, a light-emitting element LE, a light-transmitting layer TPL, and a first color filter CF1 may be provided. The light-emitting element LE, the light-transmitting layer TPL, and the first color filter CF1 may overlap in the third direction DR3. The light-transmitting layer TPL may transmit the first light output from the light-emitting element LE as it is, and the first color filter CF1 may transmit the first light. Therefore, each of the first light-emitting regions EA1 may emit first light.

[0181] In each of the second light-emitting regions EA2, a light-emitting element LE, a wavelength conversion layer QDL, and a second color filter CF2 may be provided. The light-emitting element LE, the wavelength conversion layer QDL, and the second color filter CF2 may overlap in a third direction DR3. The wavelength conversion layer QDL may convert a part of the first light output from the light-emitting element LE into a fourth light. For example, the fourth light may be light in a yellow wavelength band. The fourth light may be light including both a green wavelength band and a red wavelength band. That is, the fourth light may be a mixture of the second light and the third light. The second color filter CF2 may transmit the second light. Accordingly, each of the second light-emitting regions EA2 may emit the second light.

[0182] In each of the third light-emitting regions EA3, a light-emitting element LE, a wavelength conversion layer QDL, and a third color filter CF3 may be provided. The light-emitting element LE, the wavelength conversion layer QDL, and the third color filter CF3 may overlap in a third direction DR3. The wavelength conversion layer QDL may convert a part of the first light output from the light-emitting element LE into a fourth light. The third color filter CF3 may transmit the third light. Accordingly, each of the third light-emitting regions EA3 may emit the third light.

[0183] The area of the light-transmitting layer TPL and the area of the wavelength conversion layer QDL may each be larger than the area of the light-emitting element LE. The area of each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be larger than the area of the light-emitting element LE. In addition, the area of each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 is respectively larger than the area of the light-transmitting layer TPL and the area of the wavelength conversion layer QDL.

[0184] In the first light-emitting region EA1, the light-emitting element LE may be completely covered by the light-transmitting layer TPL, and the light-transmitting layer TPL may be completely covered by the first color filter CF1. In addition, in the second light-emitting region EA2, the light-emitting element LE may be completely covered by the wavelength conversion layer QDL, and the wavelength conversion layer QDL may be completely covered by the second color filter CF2. In addition, in the third light-emitting region EA3, the light-emitting element LE may be completely covered by the wavelength conversion layer QDL, and the wavelength conversion layer QDL may be completely covered by the third color filter CF3.

[0185] The planar shape of the light-transmitting layer TPL, the planar shape of the wavelength conversion layer QDL, the planar shape of the first color filter CF1, the planar shape of the second color filter CF2, and the planar shape of the third color filter CF3 are the same as the planar shape of the light-emitting element LE. For example, when the light-emitting element LE has a rectangular planar shape, the light-transmitting layer TPL, the wavelength conversion layer QDL, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may each have a rectangular planar shape. Optionally, the light-emitting element LE may have a polygonal shape, a circular shape, an elliptical shape, or an irregular shape other than a square or a rectangle. In this case, the light-transmitting layer TPL, the wavelength conversion layer QDL, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may also have a polygonal shape, a circular shape, an elliptical shape, or an irregular shape other than a square or a rectangle.

[0186] Optionally, the planar shape of the light-transmitting layer TPL, the planar shape of the wavelength conversion layer QDL, the planar shape of the first color filter CF1, the planar shape of the second color filter CF2, and the planar shape of the third color filter CF3 may not be the same as the planar shape of the light-emitting element LE. In this case, the planar shape of the light-transmitting layer TPL, the planar shape of the wavelength conversion layer QDL, the planar shape of the first color filter CF1, the planar shape of the second color filter CF2, and the planar shape of the third color filter CF3 may each be different from the planar shape of the light-emitting element LE. In addition, the planar shape of the light-transmitting layer TPL and the planar shape of the wavelength conversion layer QDL may each be different from the planar shape of the first color filter CF1, the planar shape of the second color filter CF2, and the planar shape of the third color filter CF3.

[0187] The light-transmitting layer TPL may include a light-transmitting organic material. For example, the light-transmitting layer TPL may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin.

[0188] The wavelength conversion layer QDL may completely cover the light-emitting element LE in each of the second light-emitting region EA2 and the third light-emitting region EA3.

[0189] The wavelength conversion layer QDL may include a base resin BRS and wavelength conversion particles WCP. The wavelength conversion particles WCP may convert the first light emitted from the light-emitting element LE into fourth light. For example, the first wavelength conversion particles may convert light in the blue wavelength band into light in the yellow wavelength band. The first wavelength conversion particles may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials. The quantum dots may include group-IV nanocrystals, group-II-VI compound nanocrystals, group-III-V compound nanocrystals, group-IV-VI compound nanocrystals, or combinations thereof.

[0190] Quantum dots may include a core and a shell that coats the core. The core may be, for example, at least one of CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InP, InAs, InSb, SiC, Ca, Se, In, P, Fe, Pt, Ni, Co, Al, Ag, Au, Cu, FePt, Fe2O3, Fe3O4, Si, and Ge, but is not limited thereto. The shell may be, for example, at least one of ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, HgSe, HgTe, AlN, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, GaSe, InN, InP, InAs, InSb, TlN, TlP, TlAs, TlSb, PbS, PbSe, and PbTe, but is not limited thereto.

[0191] The wavelength conversion layer QDL may further include a scatterer configured to scatter light from the light-emitting element LE in random directions. In this case, the scatterer may include metal oxide particles or organic particles. For example, the metal oxide may be titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), or tin oxide (SnO2). The scatterer may also include silicon dioxide (SiO2). In addition, the organic particles may include an acrylic resin or a urethane resin. The diameter of the scatterer may be about several nanometers to several tens of nanometers.

[0192] The partition wall PW is located on the common electrode CE in the display area DA and may divide the plurality of light-emitting areas EA1, EA2, and EA3 and the non-light-emitting area NEA. The partition wall PW is arranged to extend in a first direction DR1 and a second direction DR2 and may form a lattice pattern throughout the display area DA. In addition, the partition wall PW may not overlap with the plurality of light-emitting areas EA1, EA2, and EA3 and may overlap with the non-light-emitting area NEA.

[0193] The partition wall PW may include a plurality of openings that define the light-emitting areas EA1, EA2, and EA2. The plurality of openings may include a first opening that overlaps with the first light-emitting area EA1, a second opening that overlaps with the second light-emitting area EA2, and a third opening that overlaps with the third light-emitting area EA3. Here, the plurality of openings may correspond to the plurality of light-emitting areas EA1, EA2, and EA3. That is, the first opening corresponds to the first light-emitting area EA1, the second opening corresponds to the second light-emitting area EA2, and the third opening corresponds to the third light-emitting area EA3.

[0194] The partition wall PW may be used to provide a space for the wavelength conversion layer QDL and / or the light-transmitting layer TPL to be formed. To this end, the partition wall PW may be made to have a thickness (e.g., a predetermined thickness), for example, the thickness of the partition wall PW may be in the range of about 1 μm to about 10 μm. The partition wall PW may include an organic insulating material having a thickness (e.g., a predetermined thickness). The organic insulating material may include, for example, an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin.

[0195] The reflective layer RF may be located in a space formed by the partition wall PW. The reflective layer RF may be referred to as a partition wall reflective layer RF to distinguish it from the partition wall PW. Figure 8 and Figure 9 The reflective layer REF located on one side of the light emitting element LE is separated.

[0196] The partition wall reflective layer RF may directly contact the partition wall PW, the wavelength conversion layer QDL, and the light-transmitting layer TPL. The partition wall reflective layer RF is used to reflect light emitted from the light-emitting element LE that travels in the lateral direction and does not travel in the upward direction. The partition wall reflective layer RF may include a highly reflective metal material such as aluminum (Al). A plurality of color filters CF1, CF2, and CF3 may be located on the partition wall PW, the light-transmitting layer TPL, and the wavelength conversion layer QDL. A plurality of color filters CF1, CF2, and CF3 may be arranged to overlap with a plurality of pixel circuit portions PXC, the light-transmitting layer TPL, and the wavelength conversion layer QDL.

[0197] The plurality of color filters CF1 , CF2 , and CF3 may include a first color filter CF1 , a second color filter CF2 , and a third color filter CF3 .

[0198] Each of the first color filters CF1 may be located on the light-transmitting layer TPL in the first light-emitting area EA1. Each of the first color filters CF1 may transmit the first light and absorb or block the second light and the third light. For example, each of the first color filters CF1 may transmit light in a blue wavelength band and absorb or block light in a green wavelength band and a red wavelength band. Therefore, each of the first color filters CF1 may transmit the first light emitted from the light-emitting element LE. That is, the first light emitted from the light-emitting element LE in the first light-emitting area EA1 is not converted by a separate wavelength conversion layer, and may be transmitted through the light-transmitting layer TPL and the first color filter CF1. Therefore, each of the first light-emitting areas EA1 may emit the first light.

[0199] Each of the second color filters CF2 may be located on the wavelength conversion layer QDL in the second light emitting region EA2. Each of the second color filters CF2 may transmit the second light and absorb or block the first light and the third light. For example, each of the second color filters CF2 may transmit light in the green wavelength band and absorb or block light in the blue wavelength band and the red wavelength band. Thus, each of the second color filters CF2 may absorb or block the first light among the first lights emitted from the light emitting element LE that is not converted by the wavelength conversion layer QDL. In addition, each of the second color filters CF2 may transmit the second light corresponding to the green wavelength band among the fourth lights converted by the wavelength conversion layer QDL, and absorb or block the third light corresponding to the red wavelength band among the fourth lights converted by the wavelength conversion layer QDL. Thus, each of the second light emitting regions EA2 may emit the second light.

[0200] Each of the third color filters CF3 may be located on the wavelength conversion layer QDL in the third light emitting region EA3. Each of the third color filters CF3 may transmit the third light and absorb or block the first light and the second light. For example, each of the third color filters CF3 may transmit light in the red wavelength band and absorb or block light in the blue wavelength band and the green wavelength band. Thus, each of the third color filters CF3 may absorb or block the first light among the first lights emitted from the light emitting element LE that is not converted by the wavelength conversion layer QDL. In addition, each of the third color filters CF3 may transmit the third light corresponding to the red wavelength band among the fourth lights converted by the wavelength conversion layer QDL, and absorb the second light corresponding to the green wavelength band among the fourth lights converted by the wavelength conversion layer QDL. Thus, each of the third light emitting regions EA3 may emit the third light.

[0201] The light blocking member BM (also referred to as a black matrix) may be located between the plurality of color filters CF1, CF2, and CF3. For example, the light blocking member BM may be located between the first color filter CF1 and the second color filter CF2, between the second color filter CF2 and the third color filter CF3, and between the first color filter CF1 and the third color filter CF3. The light blocking member BM may include an inorganic black pigment such as carbon black, or an organic black pigment.

[0202] In addition, the plurality of color filters CF1, CF2, and CF3 may partially overlap with adjacent color filters. For example, the first color filter CF1 may have an area that partially overlaps with the adjacent second color filter CF2, and the second color filter CF2 may have an area that partially overlaps with the adjacent first color filter CF1 or the third color filter CF3, and the third color filter CF3 may have an area that partially overlaps with the adjacent first color filter CF1 or the second color filter CF2. In this way, the area formed by overlapping the plurality of color filters CF1, CF2, and CF3 can be used as a light-blocking member BM for blocking light leakage due to the overlap, so the light-blocking member BM can be omitted.

[0203] The light-blocking member BM (also referred to as a black matrix) may be located on the partition wall PW. The light-blocking member BM can block the transmission of light by overlapping with the non-emitting region NEA. The light-blocking member BM can be arranged in a substantially lattice pattern on the plane similar to the partition wall PW. The light-blocking member BM can overlap with the partition wall PW and can not overlap with the light-emitting regions EA1, EA2, and EA3.

[0204] In one or more embodiments, the light-blocking member BM may include an organic light-blocking material and may be formed by a coating and exposure process of the organic light-blocking material. The light-blocking member BM may include a dye or pigment having light-blocking properties and may be a black matrix. The light-blocking member BM can at least partially overlap with the adjacent color filters CF1, CF2, and CF3, and the color filters CF1, CF2, and CF3 can overlap with at least a part of the light-blocking member BM.

[0205] When the light-blocking member BM is located on the partition wall PW, at least a part of the external light is absorbed by the light-blocking member BM. Therefore, color distortion caused by external light reflection can be reduced. In addition, the light-blocking member BM can reduce or prevent light intrusion between adjacent light-emitting regions and cause color mixing, thereby further improving the color reproduction rate.

[0206] The protective layer BFL may be located below the plurality of color filters CF1, CF2, and CF3 and the light-blocking member BM. The protective layer BFL may be located on the partition wall PW, the light-transmitting layer TPL, and the wavelength conversion layer QDL. One surface (e.g., the top surface) of the protective layer BFL may respectively contact the lower surfaces of the plurality of color filters CF1, CF2, and CF3 and the light-blocking member BM. In addition, the other surface (e.g., the lower surface) of the protective layer BFL opposite to one surface of the protective layer BFL may respectively contact the top surfaces of the partition wall PW, the light-transmitting layer TPL, and the wavelength conversion layer QDL. The protective layer BFL may include an inorganic insulating material. For example, the protective layer BFL may include, but is not limited to, silicon oxide (SiO x ), silicon nitride (SiN x), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ), aluminum nitride (AlN), etc. The protective layer BFL may have a thickness in the range of, for example, 0.01 to 1 μm (e.g., a predetermined thickness). However, the present disclosure is not limited thereto.

[0207] Hereinafter, a manufacturing process of the display device 10 according to one or more embodiments will be described with reference to other drawings.

[0208] Figures 17 to 26 is a cross-sectional view showing a method of manufacturing a display device according to one or more embodiments.

[0209] Figures 17 to 26 Cross-sectional views respectively showing the structure according to the formation order of each layer of the display device 10 are shown. Figures 17 to 26 Mainly shows a manufacturing process of the light-emitting main body portion, and can respectively correspond substantially to Figure 6 the cross-sectional views.

[0210] As Figure 17 and Figure 18 shown, the first substrate SUB1 on which the pixel electrode PE is formed and the second substrate SUB2 on which the light-emitting material layer LEML is formed are bonded by the connection electrode layer 112L, and the second substrate SUB2 is removed.

[0211] First, referring to Figure 17 , a first connection electrode layer 112L_1 is formed on the pixel electrode PE on the first substrate SUB1, and a second connection electrode layer 112L_2 is formed on the light-emitting material layer LEML on the second substrate SUB2.

[0212] For example, first, an interlayer insulating layer 111 is formed on the first substrate SUB1 on which the pixel electrode PE is not positioned. The top surface of the interlayer insulating layer 111 and the top surface of each of the pixel electrodes PE may be flat. That is, the height difference between the top surface of the first substrate SUB1 and the top surface of the pixel electrode PE can be substantially eliminated by the interlayer insulating layer 111. The interlayer insulating layer 111 may be formed of an inorganic film such as a silicon oxide film (SiO2), an aluminum oxide film (Al2O3), or a hafnium oxide film (HfO x ).

[0213] Then, a first connection electrode layer 112L_1 is deposited on the pixel electrode PE and the interlayer insulating layer 111. The first connection electrode layer 112L_1 may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the first connection electrode layer 112L_1 may include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin, or may include an alloy of copper, silver, and tin (SAC305).

[0214] In addition, a buffer film BF may be formed on one surface of the second substrate SUB2. The second substrate SUB2 may be a silicon substrate or a sapphire substrate. The buffer film BF may be formed of an inorganic film such as a silicon oxide film (SiO2), an aluminum oxide film (Al2O3), or a hafnium oxide film (HfO x )

[0215] The light-emitting material layer LEML may be located on the buffer film BF. The light-emitting material layer LEML may include a first semiconductor material layer LEMD and a second semiconductor material layer LEMU. The second semiconductor material layer LEMU may be located on the buffer film BF, and the first semiconductor material layer LEMD may be located on the second semiconductor material layer LEMU.

[0216] The first semiconductor material layer LEMD may include a first semiconductor layer SEM1, an electron blocking layer EBL, an active layer MQW, a superlattice layer SLT, and a second semiconductor layer SEM2 as Figure 7 shown. The second semiconductor material layer LEMU may be a semiconductor layer not doped with a dopant, i.e., an undoped semiconductor layer. For example, the second semiconductor material layer LEMU may be undoped GaN, which is not doped with a dopant.

[0217] A second connection electrode layer 112L_2 may be deposited on the first semiconductor material layer LEMD. The second connection electrode layer 112L_2 may include the same materials as the first connection electrode layer 112L_1, but is not limited thereto.

[0218] The second connection electrode layer 112L_2 may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the second connection electrode layer 112L_2 may include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin, or may include an alloy of copper, silver, and tin (SAC305).

[0219] Next, as Figure 18 shown, the first connection electrode layer 112L_1 and the second connection electrode layer 112L_2 are bonded, and the second substrate SUB2 is removed.

[0220] For example, the first connection electrode layer 112L_1 of the first substrate SUB1 is brought into contact with the second connection electrode layer 112L_2 of the second substrate SUB2. Then, a connection electrode layer 112L is formed by melting and bonding the first connection electrode layer 112L_1 and the second connection electrode layer 112L_2 at a temperature (e.g., a predetermined temperature). That is, the connection electrode layer 112L is located between the pixel electrode PE on the first substrate SUB1 and the light-emitting material layer LEML on the second substrate SUB2, and can be used as a bonding metal layer to bond the pixel electrode PE on the first substrate SUB1 and the light-emitting material layer LEML on the second substrate SUB2. In one or more embodiments, a plurality of connection electrodes are formed on the first substrate SUB1 and the second substrate SUB2 and bonded to each other. However, the first substrate SUB1 and the second substrate SUB2 can be bonded by forming connection electrodes only on the first substrate SUB1 or the second substrate SUB2.

[0221] After bonding the first connection electrode layer 112L_1 and the second connection electrode layer 112L_2, the second substrate SUB2 and the buffer film BF can be removed by a polishing process (such as a chemical mechanical polishing (CMP) process and / or an etching process). In addition, the second semiconductor material layer LEMU of the light-emitting material layer LEML can be removed by a polishing process (such as a CMP process).

[0222] As Figure 19 and Figure 20 shown, a lens-shaped first mask pattern MP1 is patterned on the light-emitting material layer LEML. For this purpose, first, as Figure 19 shown, a photosensitive polymer mask pattern MP is patterned by a photolithography process. Thereafter, the first mask pattern MP1 is formed in a lens shape using a reflow process.

[0223] By heating the patterned photosensitive polymer mask to a temperature above the melting point of the polymer material for a period of time (e.g., a predetermined period of time), the reflow process melts the polymer material into a liquefied state. At this time, the surface tension of the liquefied material will cause it to form into a lens shape with a smooth curved surface. After the reflow process, the patterned photosensitive polymer mask pattern MP as Figure 19 shown can be molded into the lens-shaped first mask pattern MP1 as Figure 20 shown.

[0224] Next, referring to Figure 21 , a light-emitting element LE having a lens-shaped top surface is formed using the lens-shaped first mask pattern MP1.

[0225] For example, first, etch the region of the first semiconductor material layer LEMD where the first mask pattern MP1 is not located until the connection electrode layer 112L is exposed. Thus, the top surface of the first semiconductor material layer LEMD can be in the shape of a lens having a smooth curved surface like the first mask pattern MP1.

[0226] Next, referring to Figure 22 and Figure 23 , form the connection electrode 112 through a photolithography process and an etching process.

[0227] For example, pattern the second mask pattern MP2 surrounding the light-emitting element LE through a photolithography process. Thereafter, form the connection electrode 112 by etching the connection electrode layer 112L until the interlayer insulating layer 111 is exposed. At this time, the upper edge of the connection electrode 112 can have a curvature.

[0228] Next, referring to Figure 24 and Figure 25 , form the insulating layer INS and the planarization layer 113 on the side of the light-emitting element LE.

[0229] For example, referring to Figure 24 , deposit the insulating layer INS to cover the entire surface of the first substrate SUB1 on which the light-emitting element LE is located. The insulating layer INS can be formed of an inorganic film such as a silicon oxide film (SiO2), an aluminum oxide film (Al2O3), or a hafnium oxide film (HfO x ), but is not limited thereto.

[0230] The insulating layer INS is formed on the top surface and the side surface of each light-emitting element LE and on a part of the side surface and the top surface of the connection electrode 112 on the interlayer insulating layer 111.

[0231] As Figure 25 shown, form the planarization layer 113 on the first substrate SUB1 on which the insulating layer INS is formed. The planarization layer 113 can be located in a region other than the region where the insulating layer INS will be opened on the top surface of the light-emitting element LE. The planarization layer 113 can be formed of an organic film such as an acrylic resin film, an epoxy resin film, a phenolic resin film, a polyamide resin film, a polyimide resin film, etc., but is not limited thereto.

[0232] Then, remove the insulating layer INS located on the top surface of the light-emitting element LE that is not covered by the planarization layer 113. That is, form an opening OP in the upper region of the light-emitting element LE by etching the insulating layer INS, thereby exposing the top surface of the light-emitting element LE.

[0233] Next, as Figure 26 shown, form the common electrode CE on the top surface of the light-emitting element LE and the planarization layer 113 exposed by the opening OP.

[0234] The common electrode CE may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0235] Figures 27 to 30 is a cross-sectional view showing a method of manufacturing a display device according to one or more other embodiments.

[0236] Figures 27 to 30 Cross-sectional views respectively showing the structure according to the formation order of each layer of the display device 10. Figures 27 to 30 Mainly shows after the manufacturing process described in Figures 17 to 24 the manufacturing process according to other embodiments, and each of these may correspond generally to the cross-sectional view of Figure 8 .

[0237] As Figure 27 and Figure 28 shown, a reflective material layer REFL is deposited on the insulating layer INS to cover the first substrate SUB1.

[0238] Then, a large voltage difference is formed in the third direction DR3 without a separate mask, and the reflective material layer REFL is etched using an etching material. In this case, the etching material moves in the third direction DR3 by voltage control, that is, from the top to the bottom, and the reflective material layer REFL can be etched. As a result, as Figure 28 shown, the reflective material layer REFL located on the horizontal plane defined by the first direction DR1 and the second direction DR2 can be removed, while the reflective material layer REFL located on the vertical plane defined by the third direction DR3 can be not removed. Therefore, the reflective material layer REFL located on the top surface of the light-emitting element LE and on the top surface of the insulating layer INS that does not overlap with the light-emitting element LE can be removed. The reflective material layer REFL located on the side surface of the light-emitting element LE can be retained. The reflective material layer REFL that is not removed and retained on the side surface of the light-emitting element LE can be referred to as a reflective layer REF. The reflective layer REF can be formed to surround one side of the light-emitting element LE on the insulating layer INS.

[0239] Next, as Figure 29As shown, a planarization layer 113 is formed on a first substrate SUB1 on which an insulating layer INS and a reflective layer REF are formed. The planarization layer 113 may be located in a region on the top surface of the light-emitting element LE except for the region where the insulating layer INS will be opened. The planarization layer 113 may be formed to be lower than the height of the light-emitting element LE. The planarization layer 113 may be formed to be higher than the reflective layer REF. Thus, the common electrode CE and the reflective layer REF to be formed later may not contact each other. The planarization layer 113 may be formed of an organic film such as an acrylic resin film, an epoxy resin film, a phenolic resin film, a polyamide resin film, a polyimide resin film, etc., but is not limited thereto.

[0240] Then, the insulating layer INS located on the top surface of the light-emitting element LE not covered by the planarization layer 113 is removed. That is, an opening OP is formed in the upper region of the light-emitting element LE by etching the insulating layer INS, thereby exposing the top surface of the light-emitting element LE.

[0241] Next, as Figure 30 shown, a common electrode CE is formed on the top surface of the light-emitting element LE and the planarization layer 113 exposed by the opening OP.

[0242] Figures 31 to 43 is a cross-sectional view showing a method of manufacturing a display device according to one or more other embodiments.

[0243] Figures 31 to 43 Cross-sectional views showing the structure according to the formation order of each layer of the display device 10 are respectively shown. Figures 31 to 43 Mainly shows the manufacturing process of the light-emitting main body part, and each can correspond substantially to the Figure 12 cross-sectional view.

[0244] Refer to Figure 31 , a light-emitting material layer LEML and a connection electrode layer 112L are formed on a second substrate SUB2.

[0245] First, a second substrate SUB2 is prepared. The second substrate SUB2 may be a sapphire substrate (Al2O3) or a silicon wafer containing silicon. However, the present disclosure is not limited thereto, and the case where the second substrate SUB2 is a sapphire substrate will be described in one or more embodiments.

[0246] A second semiconductor material layer LEMU and a first semiconductor material layer LEMD are sequentially formed on the second substrate SUB2.

[0247] As Figure 13 shown, the first semiconductor material layer LEMD may include a first semiconductor layer SEM1, an electron blocking layer EBL, an active layer MQW, a superlattice layer SLT, and a second semiconductor layer SEM2.

[0248] The light-emitting material layer LEML grown by an epitaxial method can be formed by a growth seed crystal. Here, the method of forming the light-emitting material layer LEML can include electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual hot gas deposition, dual-type thermal evaporation, sputtering, metalorganic chemical vapor deposition (MOCVD), etc., and the light-emitting material layer LEML can be formed by metalorganic chemical vapor deposition (MOCVD). However, the present disclosure is not limited thereto.

[0249] Within the range that can be conventionally selected to form a target material, the precursor material for forming the light-emitting material layer LEML is not particularly limited. In one example, the precursor material can be a metal precursor containing an alkyl group (such as a methyl group or an ethyl group). For example, it can be a compound such as trimethylgallium (Ga(CH3)3), trimethylaluminum (Al(CH3)3), or triethyl phosphate ((C2H5)3PO4), but is not limited thereto.

[0250] For example, the second semiconductor material layer LEMU is formed on the second substrate SUB2. In the drawings, the second semiconductor material layer LEMU is shown as a single layer, but the present disclosure is not limited thereto, and the second semiconductor material layer LEMU can be formed of multiple layers. The second semiconductor material layer LEMU can reduce the lattice constant difference between the first semiconductor material layer LEMD and the second substrate SUB2. In one example, the second semiconductor material layer LEMU can include an undoped semiconductor and can be a material that is not doped as n-type or p-type. In one or more embodiments, the second semiconductor material layer LEMU can be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0251] The first semiconductor material layer LEMD is formed on the second semiconductor material layer LEMU using the method described above. The first semiconductor material layer LEMD is formed of a second semiconductor forming material layer, a superlattice material layer, an active material layer, an electron blocking material layer, and a first semiconductor forming material layer formed in sequence.

[0252] Then, a connection electrode layer 112L is formed on the first semiconductor material layer LEMD. The connection electrode layer 112L can include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the connection electrode layer 112L can include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin, or an alloy of copper, silver, and tin (SAC305).

[0253] Next, refer to Figure 32, etch a part of the connection electrode layer 112L and the first semiconductor material layer LEMD. The superlattice material layer, the active material layer, the electron blocking material layer, and the first semiconductor forming material layer of the first semiconductor material layer LEMD can be etched.

[0254] For example, a photosensitive polymer mask pattern MP is formed on the first semiconductor material layer LEMD. The photosensitive polymer mask pattern MP can be a hard mask containing inorganic materials or a photoresist mask containing organic materials. The photosensitive polymer mask pattern MP reduces or prevents the possibility of the underlying first semiconductor material layer LEMD from being etched. Next, the first semiconductor material layer LEMD is etched (first etching) using the photosensitive polymer mask pattern MP until the second semiconductor forming material layer SEM2L of the first semiconductor material layer LEMD is exposed.

[0255] The semiconductor material layer can be etched by conventional methods. For example, the process for etching the semiconductor material layer can be dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE), or inductively coupled plasma reactive ion etching (ICP-RIE), etc. In the case of dry etching, anisotropic etching can be performed, and the anisotropic etching can be adapted for vertical etching. When using the etching methods described above, the etchant can be Cl2 or O2. However, the present disclosure is not limited thereto.

[0256] The light-emitting material layer LEML overlapping with the photosensitive polymer mask pattern MP is not etched.

[0257] Reference Figure 33 , attach the second substrate SUB2 to the carrier substrate CSUB. For example, the etched first semiconductor material layer LEMD on the second substrate SUB2 is attached to the carrier substrate CSUB.

[0258] The carrier substrate CSUB can be composed of a first support layer CSUB-1 and a first adhesive layer CSUB-2 located on the first support layer CSUB-1. The first support layer CSUB-1 can be made of a transparent and mechanically stable material that allows light to penetrate. For example, the support layer can include transparent polymers such as polyester, polyacrylic acid, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, etc. The first adhesive layer CSUB-2 can include an adhesive material for bonding the light-emitting element LE. For example, the adhesive material can include urethane acrylate, epoxy acrylate, polyester acrylate, etc. The adhesive material can be a material whose bonding strength changes with the application of ultraviolet (UV) light or heat, and thus the first adhesive layer CSUB-2 can be appropriately separated from the light-emitting element LE.

[0259] Next, reference Figure 34, a laser (first laser) is irradiated onto the second substrate SUB2 to separate the light-emitting material layer LEML from the second substrate SUB2.

[0260] A process of separating the second substrate SUB2 can be performed using a laser lift-off (LLO) process. The laser lift-off process can use a laser. For example, a KrF excimer laser (e.g., having a wavelength of about 248 nm) can be used as a source. The energy density of the excimer laser is irradiated in the range of about 550 mJ / cm 2 to about 950 mJ / cm 2 , and the incident area can be in the range of about 50×50 μm 2 to about 1×1 cm 2 , but not limited thereto. By irradiating the laser onto the second substrate SUB2, the second substrate SUB2 can be separated from the light-emitting material layer LEML.

[0261] Thereafter, the second semiconductor material layer LEMU can be removed by a polishing process (such as a CMP process).

[0262] Next, referring to Figure 35 and Figure 36 , after a photosensitive polymer mask PR is formed on the first semiconductor material layer LEMD by a photolithography process, the photosensitive polymer mask PR is processed using a reflow process to be molded into a lens shape. Since the reflow process has been described above, the repeated description is omitted.

[0263] Next, referring to Figure 37 , a light-emitting element LE having a lens-shaped top surface is formed using the lens-shaped photosensitive polymer mask PR.

[0264] For example, the second semiconductor forming material layer SEM2L and the first adhesive layer CSUB-2 can be etched in a region on the first semiconductor material layer LEMD where the photosensitive polymer mask PR is not located. Thus, the top surface of the first semiconductor material layer LEMD can be in the shape of a lens having a smooth curved surface like the photosensitive polymer mask PR. In other words, the top surface of the second semiconductor forming material layer SEM2L is molded into a lens shape, thereby forming a second semiconductor layer SEM2 having a lens-shaped top surface. A light-emitting element LE having a lens-shaped top surface is formed.

[0265] Referring to Figure 38 , the carrier substrate CSUB is aligned on an interposer substrate ISUB.

[0266] Similar to the carrier substrate CSUB, the intermediate layer substrate ISUB may include a second support layer ISUB-1 and a second adhesive layer ISUB-2 located on the second support layer ISUB-1.

[0267] The second support layer ISUB-1 may be made of a transparent and mechanically stable material that allows light to penetrate. For example, the support layer may include a transparent polymer such as polyester, polyacrylic acid, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, etc. The second adhesive layer ISUB-2 may include an adhesive material for bonding the light-emitting element LE. For example, the adhesive material may include urethane acrylate, epoxy acrylate, polyester acrylate, etc. The adhesive material may be a material whose bonding strength changes with the application of ultraviolet (UV) light or heat, and thus the second adhesive layer ISUB-2 can be appropriately separated from the light-emitting element LE.

[0268] The lens-shaped top surface of the light-emitting element LE may be located on the second adhesive layer ISUB-2.

[0269] Thereafter, referring to Figure 39 and Figure 40 , a laser is irradiated onto the corresponding light-emitting element LE to selectively transfer it to the intermediate layer substrate ISUB, and the carrier substrate CSUB is separated.

[0270] For example, by irradiating a laser onto the first light-emitting element LE1 and the third light-emitting element LE3, only the first light-emitting element LE1 and the third light-emitting element LE3 can be attached to the intermediate layer substrate ISUB (for example, the second light-emitting element LE2 may not be attached to the intermediate layer substrate ISUB). Thereafter, ultraviolet light or heat may be applied to the carrier substrate CSUB to reduce the bonding strength of the adhesive layer of the carrier substrate CSUB, and then the carrier substrate CSUB can be physically or naturally separated.

[0271] Next, referring to Figures 41 to 43 , the light-emitting element LE attached to the intermediate layer substrate ISUB is bonded to the first substrate SUB1, and the intermediate layer substrate ISUB is separated.

[0272] For this purpose, the first substrate SUB1 may be prepared. A plurality of pixel circuit portions PXC and pixel electrodes PE may be formed on the first substrate SUB1.

[0273] For example, the pixel electrode PE is formed on the first substrate SUB1 on which a plurality of pixel circuit portions PXC are formed. Next, the intermediate layer substrate ISUB is aligned on the first substrate SUB1. Alignment keys are respectively placed on the first substrate SUB1 and the intermediate layer substrate ISUB, so that alignment can be performed through these alignment keys. Next, the first substrate SUB1 and the intermediate layer substrate ISUB are bonded together.

[0274] Thereafter, the pixel electrode PE on the first substrate SUB1 is brought into contact with the connection electrodes 112 on each of the light-emitting elements LE1 and LE3. Next, each of the light-emitting elements LE1 and LE3 is bonded to the first substrate SUB1 by melting and bonding the pixel electrode PE and the connection electrodes 112 at a temperature (e.g., a predetermined temperature).

[0275] As described in the reference Figures 23 to 26 an insulating layer INS, a planarization layer 113, and a common electrode CE may be formed on the first substrate SUB1. A method of forming the insulating layer INS, the planarization layer 113, and the common electrode CE has been described in the reference Figures 23 to 26 and thus redundant description will be omitted.

[0276] In another variation, as described in the reference Figures 27 to 30 an insulating layer INS, a planarization layer 113, a reflective layer REF, and a common electrode CE may be formed on the first substrate SUB1. A method of forming the insulating layer INS, the planarization layer 113, the reflective layer REF, and the common electrode CE has been described in the reference Figures 27 to 30 and thus redundant description will be omitted.

[0277] Figure 44 FIG. is a diagram of a virtual reality device including a display device according to one or more embodiments. Figure 44 FIG. shows a virtual reality device 1 in which a display device 10 according to one or more embodiments is used.

[0278] Reference Figure 44 , the virtual reality device 1 according to one or more embodiments may be a device in the form of glasses. The virtual reality device 1 according to one or more embodiments may include a display device 10, a left lens 10a, a right lens 10b, a support frame 20, a left temple 30a and a right temple 30b, a reflective member 40, and a display device housing 50.

[0279] Figure 44 FIG. shows the virtual reality device 1 including two temples 30a and 30b. However, the present disclosure is not limited thereto. The virtual reality device 1 according to one or more embodiments may be used in a head-mounted display including a head-mounted band that can be worn on the head instead of the temples 30a and 30b. For example, the virtual reality device 1 according to one or more embodiments may not be particularly limited to the illustrated example and may be applied in various forms and applied to various electronic devices.

[0280] The display device housing 50 can accommodate the display device 10 and the reflection member 40. An image displayed on the display device 10 can be reflected from the reflection member 40 and provided to the user's right eye through the right eyepiece 10b. Accordingly, the user can view a virtual reality image displayed on the display device 10 via the right eye.

[0281] Figure 44 It is shown that the display device housing 50 is located at the right end of the support frame 20. However, one or more embodiments of the present disclosure are not limited thereto. For example, the display device housing 50 can be located at the left end of the support frame 20. In this case, an image displayed on the display device 10 can be reflected from the reflection member 40 and provided to the user's left eye via the left eyepiece 10a. Accordingly, the user can view a virtual reality image displayed on the display device 10 via the left eye. As another example, the display device housing 50 can be located at each of the left and right ends of the support frame 20. In this case, the user can view a virtual reality image displayed on the display device 10 via both the left and right eyes.

[0282] Figure 45 FIG. is a diagram showing an intelligent device including a display device according to one or more embodiments.

[0283] Reference Figure 45 , the display device 10 according to one or more embodiments can be applied to the smart watch 2 which is one of the intelligent devices.

[0284] Figure 46 FIG. is a diagram showing a vehicle including a display device according to one or more embodiments. Figure 46 It shows a vehicle in which a display device according to one or more embodiments is used.

[0285] Reference Figure 46 , the display devices 10_a, 10_b, and 10_c according to one or more embodiments can be applied to the dashboard of a vehicle, to the center instrument panel of a vehicle, or to a CID (Center Information Display) located on the dashboard of a vehicle. In addition, each of the display devices 10_d and 10_e according to one or more embodiments can be applied to each interior mirror display, which replaces each of the side mirrors of a vehicle.

[0286] Figure 47 FIG. is a diagram showing a transparent display device including a display device according to one or more embodiments.

[0287] Reference Figure 47, a display device according to one or more embodiments can be applied to a transparent display device. The transparent display device can transmit light therethrough while displaying an image IM thereon. Thus, a user located in front of the transparent display device can not only view the image IM displayed on the display device 10, but also view an object RS or a background located behind the transparent display device. In the case where the display device 10 is applied to the transparent display device, Figure 47 the first substrate of the display device 10 shown may include a light-transmitting portion that can transmit light therethrough or may be made of a material that can transmit light therethrough.

[0288] At the end of the detailed description, those skilled in the art will understand that many changes and modifications can be made to the embodiments without substantially departing from the aspects of the present disclosure. Therefore, the embodiments of the present disclosure are used only in an overview and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, comprising: substrate; a light emitting element over the substrate and including a first semiconductor layer, an active layer, and a second semiconductor layer, the second semiconductor layer having a lens-shaped upper surface spaced apart from the active layer; as well as A common electrode, above the light emitting element, Wherein, a side surface of the active layer and a side surface of the second semiconductor layer are aligned.

2. The display device according to claim 1, wherein: The upper surface of the lens shape is concave downward or convex upward.

3. The display device according to claim 1, wherein: The second semiconductor layer includes a lens portion and a body portion, the lens portion having an upper surface in a lens shape in contact with the common electrode, and the body portion being below a lower surface of the lens portion, Wherein, a side surface of the lens portion is aligned with a side surface of the body portion. 4 . The display device according to claim 3 , further comprising a connection electrode between the substrate and the light emitting element, wherein a diameter of the connection electrode is larger than a diameter of the light emitting element.

5. The display device according to claim 4, wherein: The diameter of the connection electrode is larger than a diameter of the lens portion. The display device according to claim 4 , further comprising an insulating layer partially surrounding the light emitting element.

7. The display device according to claim 6, wherein: The insulating layer is on one side of the light emitting element and on a portion of the substrate on which the light emitting element is not positioned. 8 . The display device according to claim 6 , further comprising a reflective layer on the insulating layer and partially surrounding the light emitting element. 9 . The display device according to claim 3 , further comprising a connection electrode between the substrate and the light emitting element, and having a diameter that is the same as a diameter of the light emitting element and a diameter of the lens portion.

10. The display device according to claim 1, further comprising: A connecting electrode between the substrate and the light emitting element; as well as A pixel electrode is between the substrate and the connecting electrode. 11 . The display device according to claim 1 , further comprising a convex lens-shaped microlens, the convex lens-shaped microlens being above the common electrode, overlapping the light emitting element, and protruding downward.

12. The display device according to claim 11, wherein: A lower surface of the convex lens-shaped microlens contacts the common electrode.

13. The display device according to claim 1, wherein: The second semiconductor layer has a plurality of lens shapes concave downward.

14. A method for manufacturing a display device, the method comprising: stacking a first connection electrode layer on a second substrate on which a second semiconductor layer, an active layer, and a first semiconductor layer are sequentially grown; combining the second substrate with the first substrate on which the pixel circuit is formed by melting the first connection electrode layer; removing the second substrate; forming a first mask pattern in a lens shape on an upper surface of the second semiconductor layer; etching the second semiconductor layer, the active layer, and the first semiconductor layer using the first mask pattern in the lens shape to form a light emitting element including the second semiconductor layer having an upper surface in the lens shape; forming a second mask pattern surrounding the light emitting element; etching the first connecting electrode layer; as well as forming a common electrode on the light emitting element, Wherein, a side surface of the active layer and a side surface of the second semiconductor layer are aligned.

15. The method according to claim 14, wherein: The upper surface of the lens shape is concave downward or convex upward.

16. The method according to claim 14, further comprising: stacking a second connection electrode layer on a portion of the first substrate on which the pixel circuit is formed; as well as A connection electrode is formed by melting and bonding the first connection electrode layer and the second connection electrode layer.

17. The method according to claim 14, further comprising: depositing an insulating layer on the light emitting element and on a portion of the first substrate on which the light emitting element is not positioned; forming a planarization layer on a portion of the first substrate on which the insulating layer is formed, the planarization layer being lower than a height of the light emitting element; as well as A portion of the insulating layer is removed from a portion of the light emitting element not covered by the planarization layer.

18. The method according to claim 17, further comprising: depositing a reflective material layer on a portion of the first substrate on which the insulating layer is stacked; as well as A portion of the reflective material layer is removed from a horizontal surface of the first substrate to form a reflective layer partially surrounding one side of the light emitting element.

19. A method for manufacturing a display device, the method comprising: stacking a connecting electrode layer on a second substrate on which the second semiconductor layer, the active layer, and the first semiconductor layer are positioned; forming a light emitting element by etching the active layer, the first semiconductor layer and the connection electrode layer; bonding the second substrate on which the light emitting element is formed to a carrier substrate; removing the second substrate; forming a lens-shaped mask pattern on an upper surface of the second semiconductor layer; etching the upper surface of the second semiconductor layer to have a lens shape using the lens-shaped mask pattern, wherein a side of the active layer is aligned with a side of the second semiconductor layer; transferring the light emitting element on the carrier substrate to a first substrate on which a pixel electrode is formed using an intermediate substrate; removing the intermediate substrate; and A common electrode is formed on the light emitting element.

20. The method according to claim 19, wherein: The lens shape is concave downward or convex upward.

21. The method according to claim 20, wherein: The carrier substrate comprises a transparent and mechanically stable support layer, and an adhesive layer on the support layer.

22. The method according to claim 20, wherein: The interlayer substrate comprises a transparent and mechanically stable support layer, and an adhesive layer on the support layer.

23. The method of claim 20, further comprising: depositing an insulating layer on the light emitting element and on a portion of the first substrate on which the light emitting element is not positioned; depositing a reflective material layer on a portion of the first substrate on which the insulating layer is stacked; forming a reflective layer surrounding one side of the light emitting element by removing a portion of the reflective material layer above the horizontal surface of the first substrate; forming a planarization layer on the first substrate on which the insulating layer is formed, the planarization layer being lower than a height of the light emitting element; and A portion of the insulating layer not covered by the planarization layer is removed from the light emitting element.

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