Display device

Abstract

A display device is disclosed. The display device includes: a substrate on which a plurality of sub-pixels are disposed, each of the plurality of sub-pixels including a light emitting area and a non-light emitting area surrounding the light emitting area; a plurality of light emitting diodes disposed in the light emitting area on the substrate; the planarization layer is arranged on the light emitting diode, and the planarization layer is provided with an opening; and a plurality of optical layers disposed on the planarization layer, in which the planarization layer includes a central portion covering each of the plurality of light emitting diodes and an outer portion surrounding the central portion, the central portion and the outer portion are spaced apart by an opening, and each of the plurality of optical layers covers the central portion of the planarization layer and fills an interior of the opening.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, for example, but not limited to, a display device using light emitting diodes. Background Art

[0002] In addition to the display screens of televisions or monitors, display devices are also widely used as display screens for laptop computers, tablet computers, smart phones, portable display devices, and portable information devices. Liquid crystal display devices and organic light emitting display devices use thin film transistors as switching elements to display images. Since liquid crystal display devices do not adopt a self-emitting method, light irradiated from a backlight unit provided below the liquid crystal display panel is used to display images. Since such liquid crystal display devices have a backlight unit, the design is limited, and the brightness and response speed may deteriorate. Since organic light emitting display devices include organic materials, they are vulnerable to moisture, so the reliability and lifespan may deteriorate.

[0003] In recent years, due to their high quality and high reliability, the research and development of light emitting diode display devices using micro light emitting diodes have become the focus of next-generation displays. In particular, research is being conducted to further improve the light efficiency of light emitting diode display devices.

[0004] The descriptions provided in the description of the background art section should not be assumed to be prior art merely because they are mentioned in the description of the background art section or are associated with the description of the background art section. The description of the background art section may include information describing one or more aspects of the subject technology, and the description in this section does not limit the present invention. Summary of the Invention

[0005] The inventors have recognized the requirements and limitations in terms of the light efficiency of display devices. Therefore, in view of the above problems, the present disclosure is proposed, and the object of the present disclosure is to provide a display device having improved light efficiency.

[0006] According to one aspect of the present disclosure, the above and other objects can be achieved by providing a display device including: a substrate on which a plurality of sub-pixels are provided, each of the plurality of sub-pixels including a light emitting region and a non-light emitting region surrounding the light emitting region; a plurality of light emitting diodes provided on the substrate in the light emitting regions; a planarization layer provided on the light emitting diodes, the planarization layer having an opening; and a plurality of optical layers provided on the planarization layer; wherein the planarization layer includes a central portion covering each of the plurality of light emitting diodes and an outer portion surrounding the central portion, the central portion and the outer portion being spaced apart by the opening, and each of the plurality of optical layers covers the central portion of the planarization layer and fills the interior of the opening.

[0007] Other details of the example embodiments are included in the detailed description and the drawings.

[0008] According to the present disclosure, by forming an opening in the planarization layer, the optical layer can be formed to cover the upper surface and the side surface of the light-emitting diode. Accordingly, the light efficiency of the light-emitting diode can be improved.

[0009] In addition, according to the present disclosure, by disposing a scattering material inside the planarization layer, the light guided to the planarization layer can be scattered. Accordingly, light leakage toward the side surface of the sub-pixel can be prevented, and thus the light efficiency of the light-emitting diode can be further improved.

[0010] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in the present disclosure.

[0011] By examining the following drawings and the detailed description, other systems, methods, features, and advantages will be or will become apparent to those skilled in the art. It is intended that all such additional systems, methods, features, and advantages be included within this specification, within the scope of the present disclosure, and be protected by the claims. Nothing in this section shall be taken as a limitation on these claims. Further aspects and advantages are discussed below in conjunction with the embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the drawings, in which:

[0013] Figure 1 is a plan view of a display device according to an example embodiment of the present disclosure.

[0014] Figure 2A and Figure 2B is a plan view of a pixel according to an example embodiment of the present disclosure.

[0015] Figure 3 is a cross-sectional view of a first sub-pixel according to a first example embodiment of the present disclosure.

[0016] Figure 4 is a cross-sectional view of a first sub-pixel according to a second example embodiment of the present disclosure.

[0017] Figure 5 is a cross-sectional view of a first sub-pixel according to a third example embodiment of the present disclosure.

[0018] Figure 6 is a cross-sectional view of a first sub-pixel according to a fourth example embodiment of the present disclosure.

[0019] Figure 7A , Figure 7B ,Figure 7C , Figure 7D , Figure 7E , Figure 7F and Figure 7G are diagrams showing the process of manufacturing a display device according to a second exemplary embodiment of the present disclosure.

[0020] Figure 8 is a cross-sectional view of a first sub-pixel according to an exemplary embodiment of the present disclosure.

[0021] Throughout the drawings and the detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and descriptions of these elements may be exaggerated. Detailed Description

[0022] Now, embodiments of the present disclosure will be described in detail, examples of which are illustrated in the drawings. In the following description, when it is determined that a detailed description of well-known functions or configurations related to this document unnecessarily obscures the gist of the inventive concept, the detailed description thereof will be omitted. The progress of the described processing steps and / or operations is an example; however, the order of the steps and / or operations is not limited to the order described herein and may be changed as known in the art, except for steps and / or operations that must occur in a specific order. The names of the respective elements used in the following description may be selected only for the convenience of writing the specification, and thus may be different from the names used in actual products.

[0023] By the following exemplary embodiments described with reference to the drawings, the advantages and features of the present disclosure and the method of implementing them will be clarified. However, the present disclosure may be implemented in different forms and should not be construed as limited to the exemplary embodiments set forth herein. On the contrary, these exemplary embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is defined only by the scope of the claims.

[0024] The shapes, sizes, areas, ratios, angles, and quantities disclosed in the drawings for describing the exemplary embodiments of the present disclosure are only examples, and thus the present disclosure is not limited to the details shown. Throughout the specification, like reference numerals represent like elements. In the following description, when it is determined that a detailed description of a related known function or configuration unnecessarily obscures the gist of the present disclosure, the detailed description thereof will be omitted. When using "comprising", "having", "including", "containing", "constituting", "made of", "formed by", "composed of" described in the present disclosure, another part may be added unless "only ~" is used. Unless otherwise specified, singular terms may include plural forms.

[0025] Any embodiment described herein as an "example" is not necessarily to be construed as more preferred or advantageous than other embodiments.

[0026] When interpreting an element, the element is also interpreted as including an error band even though not explicitly described.

[0027] When describing positional relationships, for example, when the positional order is described as "on", "above", "over", "under", "below", "beside", "beneath", "near", "close to", "adjacent to", "on the side of", "proximate to", unless "exactly" or "directly" is used, one or more parts may be disposed between two other parts.

[0028] Spatial relative terms such as "under", "below", "beneath", "lower", "above", "upper", etc. may be used herein to facilitate the description of the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relative terms may also include different orientations of an element during use or operation. For example, if an element in the figure is inverted, an element described as "under" or "below" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary term "under" may include both an orientation of under and above. Similarly, the exemplary terms "above" or "over" may include orientations of "above" and "below".

[0029] When describing temporal relationships, terms such as "after", "subsequently", "next", "then", "before", etc. may include cases where any two events are not consecutive, unless terms such as "immediately", "exactly" or "directly" are explicitly used.

[0030] It should be understood that although terms such as "first", "second", "A", "B", "a" and "b" etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0031] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used herein. Each of these terms is not used to define the essence, order, or sequence of the corresponding component, but only to distinguish the corresponding component from other components. In the case where a certain structural element or layer is described as being "connected", "coupled", "adhered", or "joined" to another structural element or layer, it is generally interpreted that the other structural element or layer can be "connected", "coupled", "adhered", or "joined" to the structural element or layer directly or indirectly.

[0032] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first item, the second item, and the third item" represents all combinations of two or more of the first item, the second item, and the third item, as well as the first item, the second item, or the third item.

[0033] The term "device" used herein may refer to a display device including a display panel and a driver for driving the display panel. Examples of the display device may include light-emitting diodes (LEDs), etc. In addition, examples of the device may include a laptop computer, a television, a computer monitor, an automotive device, a wearable device, and an automotive equipment device, and complete product or final product sets of electronic devices (or equipment) or sets of devices (or equipment) respectively including LEDs, etc., such as mobile electronic devices such as smartphones or electronic tablets, but the embodiments of the present disclosure are not limited thereto.

[0034] Throughout the specification, like reference numerals generally denote like elements.

[0035] For ease of description, the dimensions and thicknesses of each component shown in the figures are illustrated, and the present disclosure is not limited to the dimensions and thicknesses of the components shown.

[0036] As can be fully understood by those skilled in the art, the features of the various exemplary embodiments of the present disclosure can be partially or fully coupled or combined with each other, and can interact with each other in various ways and be technically driven. The exemplary embodiments of the present disclosure can be implemented independently of each other, or can be implemented together in a mutually dependent relationship.

[0037] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the exemplary embodiments belong. It will be further understood that terms, such as those defined in a common dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0038] In aspects of the present disclosure, for ease of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode may be used interchangeably. The source electrode may be the drain electrode, and the drain electrode may be the source electrode. In addition, the source electrode in any aspect of the present disclosure may be the drain electrode in another aspect of the present disclosure, and the drain electrode in any aspect of the present disclosure may be the source electrode in another aspect of the present disclosure.

[0039] Hereinafter, preferred exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. For ease of description, the scale of each element shown in the drawings is different from the actual scale and is thus not limited to the scale illustrated in the drawings.

[0040] Figure 1 is a plan view of a display device 10 according to an exemplary embodiment of the present disclosure.

[0041] Referring to Figure 1 , a display device 10 according to an exemplary embodiment of the present disclosure may include a display area DA and a non-display area DNA provided near, surrounding, or around the display area DA. The display area DA is an area where an image can be displayed, and the non-display area NDA is an area where no image is displayed.

[0042] The display area DA may include a plurality of pixels P. The plurality of pixels P may be arranged in a matrix form composed of a plurality of rows and columns. In addition, the non-display area NDA may include a plurality of wirings, pads, driving circuits, etc. for driving the plurality of pixels P.

[0043] For example, the display device 10 may include: a display panel PN including a plurality of sub-pixels SP; a gate driver GD and a data driver DD that supply various signals to the display panel PN; and a timing controller TC that controls the timing of the gate driver GD and the data driver DD.

[0044] The gate driver GD supplies a plurality of scan signals to a plurality of scan lines SL according to a plurality of gate control signals supplied from the timing controller TC. For example, one gate driver GD is provided at a distance from one side of the display panel PN, but the number and arrangement of the gate drivers GD are not limited thereto. For example, two gate drivers GD may be respectively provided on both sides of the display panel PN and spaced apart from the display panel PN.

[0045] The data driver DD converts the image data input from the timing controller TC into a data voltage using a reference gamma voltage according to a plurality of data control signals supplied from the timing controller TC. The data driver DD may supply the converted data voltage to a plurality of data lines DL.

[0046] The timing controller TC aligns the image data input from the outside to supply the image data to the data driver DD. The timing controller TC may generate a gate control signal and a data control signal using the synchronization signals (such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal) input from the outside. Here, the horizontal synchronization signal is a signal indicating the time taken for one horizontal line of the display screen, and the vertical synchronization signal is a signal indicating the time taken for displaying one frame of the screen. The data enable signal may correspond to a signal indicating a period for supplying a data voltage to the pixel PX. In addition, the timing controller TC supplies the generated gate control signal and data control signal to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0047] However, the components of the display device 10 of the present disclosure are not limited thereto. In addition, all components of each display device according to all embodiments of the present disclosure are operably coupled and configured.

[0048] Figure 2A and Figure 2B is a plan view of a pixel P according to an exemplary embodiment of the present disclosure. Figure 2B shows that Figure 2A In the structure of, a bank 170 and an optical layer 400 are further formed.

[0049] Referring to Figure 2A and Figure 2B , each of the plurality of pixels P may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may emit lights different from each other. For example, the first sub-pixel SP1 may emit red light, the second sub-pixel SP2 may emit green light, and the third sub-pixel SP3 may emit blue light, but it is not limited thereto. In addition, although Figure 2A illustrates that one pixel P includes three sub-pixels SP1, SP2, and SP3, one pixel P is not limited thereto, and one pixel P may include a larger number of sub-pixels. For example, a white sub-pixel SP4 that emits white light may be further included, but it is not limited thereto.

[0050] For example, the plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and the red sub-pixel, the green sub-pixel, and the blue sub-pixel may be arranged in a repeating manner. Alternatively, the plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, and the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a repeating manner, or the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a quadrilateral type. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel may be sequentially arranged along the row direction, or the red sub-pixel, the blue sub-pixel, the green sub-pixel, and the white sub-pixel may be sequentially arranged along the row direction. However, in the exemplary embodiments of the present disclosure, the color type, the arrangement type, and the arrangement order of the sub-pixels are not limited, and may be configured in various forms according to the light-emitting characteristics, the device lifetime, and the device specifications.

[0051] In addition, according to the light-emitting characteristics, the sub-pixels may have different light-emitting areas. For example, a sub-pixel that emits light of a color different from that of the blue sub-pixel may have a light-emitting area different from that of the blue sub-pixel. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel, or the red sub-pixel, the blue sub-pixel, the white sub-pixel, and the green sub-pixel may each have a different light-emitting area.

[0052] Referring to Figure 2A , each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include a light-emitting region EA and a non-light-emitting region NEA surrounding the light-emitting region EA. The light-emitting region EA is a region capable of emitting light, and the non-light-emitting region NEA is a region that does not emit light. However, the configurations of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 of the present disclosure are not limited thereto.

[0053] Referring to Figure 2A , a light-emitting diode 300 may be provided in the light-emitting region EA of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The light-emitting diode 300 may be provided at the center of the light-emitting region EA of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, and alternatively, may not be provided at the center of the light-emitting region EA of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The light-emitting diode 300 can emit light.

[0054] A planarization layer 160 may be disposed in each of the light-emitting regions EA and non-light-emitting regions NEA of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The planarization layer 160 may cover the light-emitting diode 300. In addition, the planarization layer 160 may include an opening OP surrounding the light-emitting diode 300. The opening OP may have an annular shape centered on the light-emitting diode 300. In addition, the inside of the opening OP may be the central portion 160a of the planarization layer 160, and the outside of the opening OP may be the outer portion 160b of the planarization layer 160. That is, the central portion 160a and the outer portion 160b of the planarization layer 160 may be spaced apart from each other. In addition, the central portion 160a of the planarization layer 160 may be disposed in the light-emitting region EA, and the outer portion 160b of the planarization layer 160 may be disposed in the light-emitting region EA and the non-light-emitting region NEA. The planarization layer 160 may be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0055] Referring Figure 2B , an optical layer 400 may be disposed in each of the light-emitting regions EA of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The optical layer 400 may cover the light-emitting diode 300, the central portion 160a of the planarization layer 160, and the opening OP. In addition, the optical layer 400 may include a first optical layer 410 disposed in the first sub-pixel SP1, a second optical layer 420 disposed in the second sub-pixel SP2, and a third optical layer 430 disposed in the third sub-pixel SP3. The optical layer 400 may convert the color of the light emitted from the light-emitting diode 300, or may scatter the light emitted from the light-emitting diode 300 and emit the light. A detailed description thereof will be provided later.

[0056] The optical layer 400 may have a form in which one or more functional layers are stacked, but is not limited thereto. For example, the optical layer 400 may include an antireflection layer, such as a polarization layer, which may improve the outdoor visibility and contrast of the image displayed on the display panel PN by preventing reflection of external light.

[0057] In addition, the optical layer 400 may further include, for example, a barrier layer for preventing penetration of moisture or oxygen, and the barrier layer may be made of a material having low moisture permeability, such as a polymer material.

[0058] In addition, a bank 170 may be disposed in each of the non-light-emitting regions NEA of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The bank 170 may be disposed in the boundary region of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0059] Figure 3It is a cross-sectional view of a first sub-pixel SP1 according to a first exemplary embodiment of the present disclosure. That is, Figure 3 is a cross-sectional view taken along line I-I' of Figure 2A and Figure 2B .

[0060] Referring to Figure 3 , the first sub-pixel SP1 according to the first exemplary embodiment of the present disclosure may include a substrate 100, a thin film transistor 110, an interlayer insulating layer 120, a passivation layer 130, an under insulating layer 140, an adhesive layer 150, a planarization layer 160, a bank 170, a packaging layer 180, connection electrodes 200 (e.g., a first connection electrode 210, a second connection electrode 220, and a third connection electrode 230), a light emitting diode 300, a first optical layer 410, a black matrix 600, a first color filter 710, and a common voltage line CL.

[0061] The substrate 100 may be made of glass or plastic, but is not limited thereto. The display device according to the exemplary embodiment of the present disclosure may be configured by a top emission method in which the emitted light is emitted upward. Therefore, as the material of the substrate 100, not only a transparent material but also an opaque material may be used. For example, the substrate 100 may be configured to include a polymer or plastic or may be formed of a flexible material. For example, the substrate 100 may be made of a flexible polymer film, and the flexible polymer film may be made of any one of polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), cycloolefin copolymer (COC), triacetyl cellulose (TAC), polyvinyl alcohol (PVA), and polystyrene (PS), and the present disclosure is not limited thereto.

[0062] The thin film transistor 110 may be disposed on the substrate 100. The thin film transistor 110 may include a gate electrode 111, a semiconductor layer 112, a gate insulating layer 113, a source electrode 114, and a drain electrode 115.

[0063] The gate electrode 111 of the thin film transistor 110 may be disposed on the substrate 100. In addition, the semiconductor layer 112 may be disposed on the gate electrode 111. The semiconductor layer 112 may include an oxide semiconductor, an amorphous semiconductor, or a polycrystalline semiconductor.

[0064] Oxide semiconductor materials can have excellent effects in preventing leakage current and relatively low manufacturing costs. Oxide semiconductors can be made of metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or combinations of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and their oxides. Specifically, oxide semiconductors can include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO), but are not limited thereto. For example, when the semiconductor layer 112 includes an oxide semiconductor, it can include at least one of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO).

[0065] Polycrystalline semiconductor materials have fast moving speeds of carriers such as electrons and holes, and thus have high mobilities, and have low energy consumption and excellent reliability. Polycrystalline semiconductors can be made of polycrystalline silicon (poly-Si), but are not limited thereto.

[0066] Amorphous semiconductor materials can be made of amorphous silicon (a-Si), but are not limited thereto.

[0067] A gate insulating layer 113 can be provided between the gate electrode 111 and the semiconductor layer 112 for insulating the gate electrode 111 from the semiconductor layer 112. The gate insulating layer 113 can be composed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). For example, the gate insulating layer 113 can be formed by a single layer or multiple layers of inorganic films. For example, the single layer of inorganic film can be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layers of inorganic films can be formed by alternately laminating one or more layers of silicon oxide (SiOx) films, one or more layers of silicon nitride (SiNx) films, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. In addition, although Figure 3 a bottom gate structure in which the semiconductor layer 112 is provided on the gate electrode 111 is disclosed, the present disclosure is not limited thereto. For example, the gate electrode 111 can be disclosed as a top gate structure provided on the semiconductor layer 112.

[0068] The source electrode 114 and the drain electrode 115 can be provided facing each other on the semiconductor layer 112. In addition, a common voltage line CL can be provided on the gate insulating layer 113. The common voltage line CL can apply a common voltage. In addition, the common voltage line CL can be formed of the same material as the source electrode 114 and the drain electrode 115, but is not limited thereto.

[0069] The interlayer insulating layer 120 may be disposed on the source electrode 114, the drain electrode 115, and the common voltage line CL. A contact hole exposing a part of the common voltage line CL and the source electrode 114 may be formed in the interlayer insulating layer 120. In addition, the interlayer insulating layer 120 may be formed of an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy). For example, the interlayer insulating layer 120 may be formed by a single layer or multiple layers of inorganic films. For example, the single layer inorganic film may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiOxNy) film, and the multiple layer inorganic film may be formed by alternately laminating at least one of one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of silicon oxynitride (SiOxNy) film and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0070] The passivation layer 130 may be disposed on the thin film transistor 110. The passivation layer 130 may compensate for the step difference caused by the thin film transistor 110 to planarize the upper region of the thin film transistor 110. In addition, the passivation layer 130 may be formed of an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0071] The first connection electrode 210 and the third connection electrode 230 are disposed on the passivation layer 130 and may be spaced apart from each other. The first connection electrode 210 may be electrically connected to the source electrode 114 of the thin film transistor 110 through a contact hole formed in the passivation layer 130. In addition, the third connection electrode 230 may be electrically connected to the common voltage line CL through a contact hole formed in the passivation layer 130.

[0072] The first connection electrode 210 and the third connection electrode 230 may include a metal material such as Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti, or Cr and alloys thereof. Alternatively, the first connection electrode 210 and the third connection electrode 230 may include a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0073] The lower insulating layer 140 may be disposed on the first connection electrode 210 and the third connection electrode 230. The lower insulating layer 140 may expose a part of the upper surface of each of the first connection electrode 210 and the third connection electrode 230. The lower insulating layer 140 may be formed of an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy). For example, the lower insulating layer 140 may be formed by a single-layer or multi-layer inorganic film. For example, the single-layer inorganic film may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiOxNy) film, and the multi-layer inorganic film may be formed by alternately laminating at least one of one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of silicon oxynitride (SiOxNy) film and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0074] The adhesive layer 150 is disposed in the light-emitting region EA and may fix the light-emitting diode 300. The adhesive layer 150 may be disposed on the first connection electrode 210. That is, the adhesive layer 150 may be disposed on the upper surface of the first connection electrode 210 exposed by the lower insulating layer 140. In addition, the adhesive layer 150 may be formed of a conductive material to electrically connect the first connection electrode 210 and the light-emitting diode 300. For example, the adhesive layer 150 may be formed of a metal material such as indium, lead, etc., but is not limited thereto.

[0075] The light-emitting diode 300 may be disposed on the adhesive layer 150. The light-emitting diode 300 may include a first electrode 310, a first semiconductor layer 320, an active layer 330, a second semiconductor layer 340, and a second electrode 350. In addition, the light-emitting diode 300 may have a vertical structure in which the first electrode 310, the first semiconductor layer 320, the active layer 330, the second semiconductor layer 340, and the second electrode 350 are sequentially laminated. However, the embodiments of the present disclosure are not limited thereto.

[0076] The first electrode 310 may be disposed on the adhesive layer 150. Since the adhesive layer 150 is made of a conductive material, the first electrode 310 may be electrically connected to the first connection electrode 210 through the adhesive layer 150. Therefore, the first electrode 310 may be electrically connected to the source electrode 114 of the thin-film transistor 110 through the first connection electrode 210.

[0077] The first semiconductor layer 320 may be disposed on the first electrode 310 to supply holes to the active layer 330. The first semiconductor layer 320 may be formed of a p-GaN-based semiconductor material such as GaN, AlGaN, InGaN, or AlInGaN. In addition, Mg, Zn, Be, etc. may be used as impurities for doping the first semiconductor layer 320.

[0078] The active layer 330 may be disposed on the first semiconductor layer 320 and may be a light-emitting layer that emits light. The active layer 330 may have a multi-quantum well (MQW) structure, which includes well layers and barrier layers having a bandgap higher than that of the well layers. For example, the active layer 330 may have a multi-quantum well structure such as InGaN / GaN, but is not limited thereto.

[0079] The second semiconductor layer 340 may be disposed on the active layer 330 to supply electrons to the active layer 330. The second semiconductor layer 340 may be formed of an n-GaN-based semiconductor material such as GaN, AlGaN, InGaN, or AlInGaN. In addition, Si, Ge, Se, Te, C, etc. may be used as impurities for doping the second semiconductor layer 340.

[0080] The second electrode 350 may be disposed on the second semiconductor layer 340 and may be electrically connected to the common voltage line CL through the second connection electrode 220. Accordingly, the voltage applied to the source electrode 114 of the thin-film transistor 110 may be transmitted to the first electrode 310 through the first connection electrode 210, and the voltage applied to the common voltage line CL may be transmitted to the second electrode 350 through the second connection electrode 220. That is, the light-emitting diode 300 may emit light due to different voltage levels of the source electrode 114 of the thin-film transistor 110 and the common voltage line CL.

[0081] Each of the first electrode 310 and the second electrode 350 may include a metal material such as Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti, or Cr and alloys thereof. Alternatively, each of the first electrode 310 and the second electrode 350 may include a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0082] The planarization layer 160 may be disposed on the lower insulating layer 140 and may be disposed in the light-emitting region EA and the non-light-emitting region NEA. In addition, the planarization layer 160 may have an opening OP and may include a first planarization layer 161 and a second planarization layer 162.

[0083] The first planarization layer 161 may be disposed on the lower insulating layer 140. In addition, the first planarization layer 161 may include a central portion 161a disposed in the light-emitting region EA and an outer portion 161b disposed in the non-light-emitting region NEA.

[0084] The central portion 161a of the first planarization layer 161 may cover the side surface and the top surface of the adhesive layer 150 and may surround the side surface of the light-emitting diode 300. Accordingly, the central portion 161a of the first planarization layer 161 may stably fix the light-emitting diode 300 to the lower insulating layer 140 by using the adhesive layer 150. In addition, Figure 3In [description], the central portion 161a of the first planarization layer 161 surrounds the first electrode 310 of the light-emitting diode 300, the entire side surface of the first semiconductor layer 320, and a part of the side surface of the active layer 330, but is not limited thereto.

[0085] The outer portion 161b of the first planarization layer 161 may surround the central portion 161a of the first planarization layer 161. In this case, the central portion 161a and the outer portion 161b of the first planarization layer 161 may be spaced apart from each other through the first opening OP1. The first opening OP1 may be provided in the light-emitting region EA. In addition, the first opening OP1 may be formed by removing a partial region of the first planarization layer 161, and may expose a part of the lower insulating layer 140 to the outside. In addition, the first opening OP1 may be provided in an annular shape centered on the light-emitting diode 300, but is not limited thereto. In addition, the central portion 161a and the outer portion 161b of the first planarization layer 161 may be formed to have the same thickness. However, the present disclosure is not limited thereto. For example, the central portion 161a and the outer portion 161b of the first planarization layer 161 may be formed to have different thicknesses.

[0086] The second planarization layer 162 may be provided on the first planarization layer 161. In addition, the second planarization layer 162 may include a central portion 162a provided in the light-emitting region EA and an outer portion 162b provided in the non-light-emitting region NEA.

[0087] The central portion 162a of the second planarization layer 162 may cover the side surface and the top surface of the light-emitting diode 300 that are not covered by the central portion 161a of the first planarization layer 161. In Figure 3 [description], since the central portion 161a of the first planarization layer 161 surrounds the first electrode 310, the entire side surface of the first semiconductor layer 320, and a part of the side surface of the active layer 330, the central portion 162a of the second planarization layer 162 may surround a part of the side surface of the active layer 330, the entire side surface of the second semiconductor layer 340, and the entire side surface of the second electrode 350. In addition, the central portion 162a of the second planarization layer 162 may cover the top surface of the light-emitting diode 300, and compensate for the step difference caused by the light-emitting diode 300 to planarize the upper region of the light-emitting diode 300. In this case, the top surface of the second electrode 350 of the light-emitting diode 300 may be exposed by the central portion 162a of the second planarization layer 162. Therefore, the second electrode 350 of the light-emitting diode 300 may be in contact with the second connection electrode 220.

[0088] The outer portion 162b of the second planarization layer 162 may surround the central portion 162a of the second planarization layer 162. In this case, the central portion 162a and the outer portion 162b of the second planarization layer 162 may be spaced apart from each other through the second opening OP2. The second opening OP2 may overlap with the first opening OP1. In addition, the second opening OP2 is formed by removing a partial region of the second planarization layer 162 and may expose a portion of the lower insulating layer 140 having the first opening OP1. In addition, the central portion 162a and the outer portion 162b of the second planarization layer 162 may be formed to have the same thickness. However, the present disclosure is not limited thereto. For example, the central portion 162a and the outer portion 162b of the second planarization layer 162 may be formed to have different thicknesses.

[0089] The angle formed by the side surface of the first planarization layer 161 exposed by the first opening OP1 and the upper surface of the lower insulating layer 140 may be an acute angle. Similarly, the angle formed by the side surface of the second planarization layer 162 exposed by the second opening OP2 and the upper surface of the lower insulating layer may be an acute angle. For example, each of the side surfaces of the first planarization layer exposed by the first opening OP1 and the second planarization layer exposed by the second opening OP2 may have a tapered shape. However, the present disclosure is not limited thereto.

[0090] Each of the first planarization layer 161 and the second planarization layer 162 may be formed of an inorganic insulating material or an organic insulating material. In addition, each of the first planarization layer 161 and the second planarization layer 162 may be formed to include different materials, or may be formed to include the same materials.

[0091] Each of the first planarization layer 161 and the second planarization layer 162 may include scattering materials 161a and 162b. The scattering materials 161a and 162b may scatter the light emitted from the light-emitting diode 300, thereby changing the optical path. Accordingly, the light guided to the planarization layer 160 may be scattered, thereby blocking the light leakage toward the side surface of the sub-pixel and improving the light efficiency of the light-emitting diode 300. The scattering materials 161a and 162b may include metal oxides such as titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), zinc oxide (ZnO2), silicon dioxide (SiO2), or tin oxide (SnO2). Alternatively, the scattering materials 161a and 162b may include organic materials such as polystyrene or polymethyl methacrylate (PMMA).

[0092] The second connection electrode 220 may be disposed on the lower insulating layer 140 and the planarization layer 160, and may be continuously disposed in the light-emitting region EA and the non-light-emitting region NEA. In this case, since the side surfaces of the first planarization layer 161 and the second planarization layer 162 are formed in a tapered shape, the second connection electrode 220 may be disposed on a gentle slope. In particular, since the central portions 161a of the first planarization layer 161 and 162a of the second planarization layer cover the light-emitting diode 300, the step difference in the side surface of the light-emitting diode 300 is compensated. Therefore, the second connection electrode 220 may be formed on the gentle slope in the side surface of the light-emitting diode 300. In addition, since the central portions 161a of the first planarization layer 161 and 162a of the second planarization layer compensate the step difference in the upper surface of the light-emitting diode 300, the second connection electrode 220 may be formed in the flat upper region of the light-emitting diode 300. Therefore, the second connection electrode 220 may be stably deposited.

[0093] The second connection electrode 220 may be electrically connected to the third connection electrode 230 through a contact hole formed in the planarization layer 160. Since the third connection electrode 230 receives a common voltage from the common voltage line CL, the second connection electrode 220 may also receive the common voltage. In addition, the second connection electrode 220 may contact and be electrically connected to the second electrode 350 of the light-emitting diode 300 on the planarization layer 160. Therefore, the second electrode 350 may be electrically connected to the common voltage line CL through the second connection electrode 220. Accordingly, the voltage applied to the source electrode 114 of the thin-film transistor 110 may be transmitted to the first electrode 310 through the first connection electrode 210, and the voltage applied to the common voltage line CL may be transmitted to the second electrode 350 through the second connection electrode 220. That is, the light-emitting diode 300 may emit light due to different voltage levels of the source electrode 114 of the thin-film transistor 110 and the common voltage line CL.

[0094] The bank 170 may be disposed on the second connection electrode 220 and may be disposed in the non-light-emitting region NEA. The bank 170 may be made of an inorganic insulating material and may include a light-absorbing material. In addition, the bank 170 overlaps with the planarization layer 160 such that the thickness of the bank 170 may be minimized. Therefore, light leakage between adjacent sub-pixels may be prevented while minimizing the light absorption of the bank 170. For example, the bank 170 may be formed of an opaque material to reduce color mixing between a plurality of sub-pixels SP, and may be formed of a black resin, for example, but is not limited thereto.

[0095] The first optical layer 410 may be disposed on the second connection electrode 220 and may be disposed in the light-emitting region EA. In addition, the first optical layer 410 covers the light-emitting diode 300 and may fill the entire interiors of the first opening OP1 and the second opening OP2. For example, the first optical layer 410 may also be in contact with the second connection electrode 220 deposited on the side surfaces of the planarization layer 160 and the bank 170.

[0096] The first optical layer 410 may include a first base layer 411 and a first wavelength conversion material 412 distributed inside the first base layer 411. The first base layer 411 may transmit the light emitted from the light-emitting diode 300. The first base layer 411 may include a transparent organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0097] The first wavelength conversion material 412 may be a quantum dot. The quantum dot may absorb light in a specific wavelength band, convert the absorbed light into light in a wavelength band different from the absorbed light, and emit the light. For example, the first wavelength conversion material 412 may absorb blue light, convert the blue light into red light, and emit red light. Accordingly, the first wavelength conversion material 412 may convert the blue light incident from the light-emitting diode 300 into red light, but the present disclosure is not limited thereto.

[0098] In this case, since the first optical layer 410 covers the upper surface and the side surfaces of the light-emitting diode 300, the first optical layer 410 may convert all the light emitted from the upper surface and the side surface directions of the light-emitting diode 300. In particular, since the first optical layer 410 fills the interiors of the first opening OP1 and the second opening OP2, the first optical layer 410 may be disposed on the same layer as the active layer 330 of the light-emitting diode 300. Accordingly, compared with a structure in which the wavelength conversion material is only formed on the upper portion of the light-emitting diode, the light emitted from the side surface of the light-emitting diode 300 may be converted more effectively, thereby improving the light efficiency.

[0099] The encapsulation layer 180 may be disposed on the bank 170 and the first optical layer 410 and may be disposed in the light-emitting region EA and the non-light-emitting region NEA. The encapsulation layer 180 may compensate for the step difference caused by the bank 170 and the first optical layer 410 to planarize the upper regions of the bank 170 and the first optical layer 410.

[0100] The encapsulation layer 180 may transmit the light converted by the first optical layer 410. The encapsulation layer 180 may include a transparent organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

[0101] For example, the encapsulation layer 180 may include a first inorganic encapsulation layer, a second organic encapsulation layer, and a third inorganic encapsulation layer that are sequentially stacked. The first inorganic encapsulation layer and the third inorganic encapsulation layer may be made of inorganic materials such as silicon oxide (SiOx) or silicon nitride (SiNx). The second organic encapsulation layer may be made of organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. The materials of the first inorganic encapsulation layer, the second organic encapsulation layer, and the third inorganic encapsulation layer are not limited thereto. In addition, the encapsulation layer is not limited to three layers. For example, it may include n layers (where n is an integer greater than 3) in which inorganic encapsulation layers and organic encapsulation layers are alternately stacked.

[0102] The black matrix 600 may be disposed on the encapsulation layer 180 and may be disposed in the non-emitting area NEA. The black matrix 600 may be formed of an inorganic insulating material and may include a light-absorbing material.

[0103] The first color filter 710 may be disposed on the encapsulation layer 180 and may be disposed in the emitting area EA. In addition, the first color filter 710 may be surrounded by the black matrix 600. The first color filter 710 may include a dye that transmits light of a specific wavelength band. For example, the first color filter 710 may transmit red light and block or absorb green light and blue light. That is, the red light converted by the first optical layer 410 may pass through the first color filter 710. Therefore, the first sub-pixel SP1 may emit red light.

[0104] In summary, in the first exemplary embodiment of the present disclosure, by forming the opening OP in the planarization layer 160, the optical layer 410 including the wavelength conversion material 412 can be formed to cover the upper surface and the side surface of the light-emitting diode 300. Therefore, the light efficiency of the light-emitting diode 300 can be improved. In addition, by disposing the scattering materials 161c and 162c inside the planarization layer 160, the light guided to the planarization layer 160 can be scattered. Therefore, light leakage toward the side surface of the sub-pixel can be prevented, and thus the light efficiency of the light-emitting diode 300 can be further improved.

[0105] Figure 4 is a cross-sectional view of the first sub-pixel SP1 according to the second exemplary embodiment of the present disclosure. Compared with Figure 3 except for the structures of the passivation layer 130, the planarization layer 160, and the reflective layer 800, Figure 4 basically the same structure is disclosed. Therefore, the same reference numerals are used for the components that are the same as those of the first sub-pixel SP1 shown in Figure 3 and repeated descriptions are omitted.

[0106] As described above with reference to Figure 3As described above, a passivation layer 130 may be disposed on the thin film transistor 110. In this case, the passivation layer 130 may include a first passivation layer 131 and a second passivation layer 132.

[0107] The first passivation layer 131 may be disposed on the thin film transistor 110. The first passivation layer 131 may compensate for the step difference caused by the thin film transistor 110 to flatten the upper region of the thin film transistor 110.

[0108] In this case, a lower reflective layer 810 may also be disposed on the first passivation layer 131. When the light generated by the light emitting diode 300 is emitted facing the substrate 100, the lower reflective layer 810 may reflect the light directed towards the substrate 100 upwards towards the substrate 100. Therefore, the light extraction efficiency of the light emitting diode 300 can be improved. The lower reflective layer 810 may overlap with the light emitting diode 300. In addition, the width of the lower reflective layer 810 may be greater than the width of the light emitting diode 300, but is not limited thereto.

[0109] The second passivation layer 132 may be disposed on the lower reflective layer 810. The second passivation layer 132 may compensate for the step difference caused by the lower reflective layer 810 to flatten the upper region of the lower reflective layer 810.

[0110] As described above Figure 3 As described above, an adhesive layer 150 may be disposed on the first connection electrode 210. For example, the adhesive layer 150 may be disposed on the upper surface of the first connection electrode 210 exposed by the lower insulating layer 140. In addition, the adhesive layer 150 may be formed of a conductive material to electrically connect the first connection electrode 210 to the light emitting diode 300. For example, the adhesive layer 150 may be formed of a metal material such as indium, lead, etc., but is not limited thereto. In this case, referring to Figure 4 , and Figure 3 different from the first exemplary embodiment disclosed therein, the planarization layer 160 may not include a scattering material.

[0111] As described above Figure 3 As described above, the planarization layer 160 may include a first planarization layer 161 and a second planarization layer 162. The first planarization layer 161 may include a central portion 161a disposed in the light emitting region EA and an outer portion 161b disposed in the non-light emitting region NEA. In addition, the second planarization layer 162 may include a central portion 162a disposed in the light emitting region EA and an outer portion 162b disposed in the non-light emitting region NEA.

[0112] In this case, a side surface reflection layer 820 may also be provided on an outer portion 161b of the first planarization layer 161 and an outer portion 162b of the second planarization layer 162. The side surface reflection layer 820 may cover a side surface of the outer portion 161b of the first planarization layer 161. In addition, the side surface reflection layer 820 may cover a top surface and a side surface of the outer portion 162b of the second planarization layer 162.

[0113] When light generated by the light emitting diode 300 is emitted to face the side surface of the sub-pixel SP, the side surface reflection layer 820 may reflect light guided to the outer portion 161b of the first planarization layer 161 and the outer portion 162b of the second planarization layer 162 upward toward the substrate 100. Accordingly, the light extraction efficiency of the light emitting diode 300 may be improved. The side surface reflection layer 820 may be provided to face the side surface of the light emitting diode 300. In particular, the side surface reflection layer 820 may face the side surface of the active layer 330 of the light emitting diode 300.

[0114] Each of the lower reflection layer 810 and the side surface reflection layer 820 may include a metal material such as Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti, or Cr and alloys thereof. Alternatively, each of the lower reflection layer 810 and the side surface reflection layer 820 may include a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto. In addition, each of the lower reflection layer 810 and the side surface reflection layer 820 may be formed as a single layer or a multi-layer. For example, each of the lower reflection layer 810 and the side surface reflection layer 820 may be formed as a three-layer structure in which a transparent conductive material, a metal material, and a transparent conductive material are sequentially stacked, but is not limited thereto. For example, each of the lower reflection layer 810 and the side surface reflection layer 820 may be formed as an n-layer structure in which a transparent conductive material and a metal material are sequentially stacked, where n is an integer.

[0115] The second connection electrode 220 is provided on the lower insulating layer 140, the planarization layer 160, and the side surface reflection layer 820, and may be continuously provided in the light emitting region EA and the non-light emitting region NEA. In this case, since the side surfaces of the first planarization layer 161 and the second planarization layer 162 are formed in a tapered shape, even if the side surface reflection layer 820 is deposited on the side surfaces of the first planarization layer 161 and the second planarization layer 162, the side surface reflection layer 820 may maintain the tapered shape. Accordingly, since the second connection electrode 220 is formed on a gentle slope, the second connection electrode 220 may be stably deposited.

[0116] In summary, the second exemplary embodiment of the present disclosure discloses an additional formation of the reflective layer 800 including the lower reflective layer 810 and the side surface reflective layer 820. Specifically, the lower reflective layer 810 may be disposed below the light-emitting diode 300 and may reflect the light of the guiding substrate 100 toward the upper side of the substrate 100. In addition, the side surface reflective layer 820 may reflect the light on the side surface of the guiding sub-pixel SP to the upper side of the substrate 100. Therefore, the light efficiency of the light-emitting diode 300 can be improved.

[0117] Figure 5 is a cross-sectional view of the first sub-pixel SP1 according to the third exemplary embodiment of the present disclosure. Compared with Figure 3 except for the structure of the light-emitting diode 300, Figure 5 the same structure is disclosed. Therefore, the same reference numerals are used for the same components as those of the first sub-pixel SP1 shown in Figure 3 and the repeated description is omitted.

[0118] As described above Figure 3 the light-emitting diode 300 may be disposed on the adhesive layer 150. In this case, the adhesive layer 151 fixes the light-emitting diode 300 and may be formed of a curing material or a photocuring material, but is not limited thereto. In addition, Figure 3 the light-emitting diode 300 disclosed in Figure 5 and the light-emitting diode 300 disclosed in Figure 3 have different stacked structures. That is, Figure 5 the light-emitting diode 300 disclosed in Figure 5 may have a vertical structure, while Figure 3 the light-emitting diode 300 disclosed in

[0119] the light-emitting diode 300 may have a horizontal structure. In addition, since

[0120] each component of the light-emitting diode 300 disclosed in

[0121] As described above, the light-emitting diode 300 can be manufactured by sequentially stacking a second semiconductor layer 340, an active layer 330, and a first semiconductor layer 320, and then etching a predetermined portion to form a first electrode 310 and a second electrode 350. In this case, the etching region is a region for separating the first electrode 310 and the second electrode 350, and a predetermined portion can be etched to expose a part of the second semiconductor layer 340. For example, the active layer 330, the first semiconductor layer 320, and the first electrode 310 can be stacked on one side of the upper surface of the second semiconductor layer 340, and the second electrode 350 can be stacked on the other side of the upper surface of the second semiconductor layer 340. Therefore, the first electrode 310 and the second electrode 350 can be formed at different heights.

[0122] The first electrode 310 is disposed on the first semiconductor layer 320 and can be electrically connected to the source electrode 114 of the thin-film transistor 110 through the first connection electrode 210. In addition, the second electrode 350 can be disposed on the exposed second semiconductor layer 340 and can be electrically connected to the common voltage line CL through the second connection electrode 220. Therefore, the voltage applied to the source electrode 114 of the thin-film transistor 110 can be transmitted to the first electrode 310 through the first connection electrode 210, and the voltage applied to the common voltage line CL can be transmitted to the second electrode 350 through the second connection electrode 220. That is, the light-emitting diode 300 can emit light due to different voltage levels of the source electrode 114 of the thin-film transistor 110 and the common voltage line CL.

[0123] In this case, the upper surfaces of the first electrode 310 and the second electrode 350 can be exposed by the central portion 162a of the second planarization layer 162. Therefore, the first electrode 310 can be in contact with the first connection electrode 210, and the second electrode 350 can be in contact with the second connection electrode 220. In addition, a passivation layer 130 and a lower insulating layer 140 are disposed on the thin-film transistor 110, and the first connection electrode 210 can be in contact with the source electrode 114 of the thin-film transistor 110 through a contact hole formed in the passivation layer 130 and the lower insulating layer 140.

[0124] Therefore, as in the first exemplary embodiment, in the third exemplary embodiment, an opening OP can be formed in the planarization layer 160 such that the optical layer 410 including the wavelength conversion material 412 covers the upper surface and the side surface of the light-emitting diode 300. Therefore, the light efficiency of the light-emitting diode 300 can be improved. In addition, by disposing the scattering materials 161c and 162c inside the planarization layer 160, the light guided to the planarization layer 160 can be scattered. Therefore, light leakage to the side surface of the sub-pixel can be prevented, and thus the light efficiency of the light-emitting diode 300 can be further improved.

[0125] Figure 6is a cross-sectional view of a first sub-pixel according to a fourth exemplary embodiment of the present disclosure. Compared with Figure 5 , except for the structures of the lower insulating layer 140, the planarization layer 160, and the reflective layer 800, Figure 6 basically the same structures are disclosed. Therefore, the same reference numerals are used to denote components identical to those of the first sub-pixel SP1 shown in Figure 5 , and redundant descriptions are omitted.

[0126] As Figure 5 shown, the lower insulating layer 140 may be disposed on the passivation layer 130. In this case, the lower insulating layer 140 may include a first lower insulating layer 141 and a second lower insulating layer 142. Further, as Figure 6 shown, the first sub-pixel SP1 may further include a reflective layer 800, and the reflective layer 800 may include a lower reflective layer 810 and a side surface reflective layer 820.

[0127] The first lower insulating layer 141 may be disposed on the first connection electrode 210. The first lower insulating layer 141 may compensate for the step difference caused by the first connection electrode 210 to planarize the upper region of the first connection electrode 210.

[0128] The lower reflective layer 810 may be disposed on the first lower insulating layer 141. Further, the second lower insulating layer 142 may be disposed on the lower reflective layer 810. The second lower insulating layer 142 may compensate for the step difference caused by the lower reflective layer 810 to planarize the upper region of the lower reflective layer 810.

[0129] Therefore, like the second exemplary embodiment of the present disclosure, the fourth exemplary embodiment discloses an additional formation of the reflective layer 800 including the lower reflective layer 810 and the side surface reflective layer 820. Specifically, the lower reflective layer 810 may be disposed below the light emitting diode 300 and may reflect the light directed to the substrate 100 toward the upper side of the substrate 100. Further, the side surface reflective layer 820 may reflect the light on the side surface of the guiding sub-pixel SP toward the upper side of the substrate 100. Therefore, the light efficiency of the light emitting diode 300 can be improved.

[0130] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , Figure 7F and Figure 7G are diagrams illustrating a process of manufacturing a display device according to the second exemplary embodiment of the present disclosure. In particular, Figures 7A to 7G illustrates a process of manufacturing the first sub-pixel SP1.

[0131] Referring to Figure 7A, a thin film transistor 110, a common voltage line CL, an interlayer insulating layer 120, a first passivation layer 131, a lower reflective layer 810, a second passivation layer 132, a first connection electrode 210, a third connection electrode 230, a lower insulating layer 140, an adhesive layer 150, and a light emitting diode 300 may be sequentially formed on a substrate 100.

[0132] The lower reflective layer 810, the adhesive layer 150, and the light emitting diode 300 may be formed at the center of the light emitting region EA. In addition, the lower reflective layer 810, the adhesive layer 150, and the light emitting diode 300 may be formed to overlap each other.

[0133] The adhesive layer 150 fixes the light emitting diode 300 on the first connection electrode 210 and may electrically connect the light emitting diode 300 to the first connection electrode 210.

[0134] Referring to Figure 7B , a first planarization layer 160 may be formed on the lower insulating layer 140. After depositing a planarization material on the entire surface of the substrate 100, a partial region of the deposited planarization material may be removed to form a first opening OP1. Through the first opening OP1, the first planarization layer 161 may include a central portion 161a and an outer portion 161b surrounding the central portion 161a. That is, the removed region may become the first opening OP1, and the remaining planarization material may be the first planarization layer 161. In this case, since the central portion 161a of the first planarization layer 161 covers the side surface and the top surface of the adhesive layer 150 and surrounds the side surface of the light emitting diode 300, the light emitting diode 300 may be stably fixed on the second lower insulating layer 142.

[0135] Referring to Figure 7C , a second planarization layer 162 may be formed on the first planarization layer 161. After depositing a planarization material on the entire surface of the substrate 100, a partial region of the deposited planarization material may be removed to form a second opening OP2. The second opening OP2 may overlap with the first opening OP1. Through the second opening OP2, the second planarization layer 162 may include a central portion 162a and an outer portion 162b surrounding the central portion 162a. That is, the removed region may become the second opening OP2, and the remaining planarization material may become the second planarization layer 162. Since the central portion 162a of the second planarization layer 162 covers the upper surface and the side surface of the light emitting diode 300, the upper surface and the side surface region of the light emitting diode 300 may be planarized by compensating for the step difference caused by the light emitting diode 300. In this case, the upper surface of the second electrode 350 of the light emitting diode 300 may be exposed by the central portion 162a of the second planarization layer 162.

[0136] Referring to Figure 7D, a side surface reflective layer 820 may be formed on the second planarization layer 162. After depositing a metal material or a transparent conductive material on the entire surface of the substrate 100, a partial region of the deposited metal material or the deposited transparent conductive material may be removed to form the side surface reflective layer 820. Specifically, a region overlapping with the light emitting diode 300 and the opening OP may be removed from the metal material or the transparent conductive material deposited on the entire surface of the substrate 100. That is, the side surface reflective layer 820 may be formed to cover the side surface of the outer portion 161b of the first planarization layer 161 and the top surface and the side surface of the outer portion 162b of the second planarization layer 162. When the side surface reflective layer 820 includes multiple layers, the side surface reflective layer 820 may be formed by sequentially depositing multiple materials on the entire surface of the substrate 100 and then removing a partial region of the deposited multiple materials. For example, after depositing a transparent conductive material, a metal material, and a transparent conductive material on the entire surface of the substrate 100, a partial region of these materials may be removed to form the side surface reflective layer 820 including three layers. However, the present disclosure is not limited thereto. For example, when each of the bottom reflective layer 810 and the side surface reflective layer 820 is formed as n layers in which a transparent conductive material and a metal material are sequentially stacked and n is an integer, after depositing n layers of a transparent conductive material and a metal material on the entire surface of the substrate 100, a partial region of these materials may be removed to form the side surface reflective layer 820 including n layers.

[0137] Referring to Figure 7E , a second connection electrode 220 may be formed on the entire surface of the substrate 100. That is, the second connection electrode 220 may be formed on the lower insulating layer 140, the planarization layer 160, and the side surface reflective layer 820. In this case, the side surface of the light emitting diode 300 has a gentle slope through the central portion 161a of the first planarization layer 161 and the central portion 162a of the second planarization layer 162, so that the second connection electrode 220 may be stably deposited on the side surface of the light emitting diode 300. In addition, since the upper region of the light emitting diode 300 is planarized by the central portion 161a of the first planarization layer 161 and the central portion 162a of the second planarization layer 162, the second connection electrode 220 may be stably deposited on the upper region of the light emitting diode 300. In addition, since the side surface reflective layer 820 deposited on the side surfaces of the first planarization layer 161 and the second planarization layer 162 has a tapered shape, the second connection electrode 220 may be stably deposited on the side surface reflective layer 820. Therefore, the second connection electrode 220 may be stably deposited on the entire surface of the substrate 100 and may contact the second electrode 350 of the light emitting diode 300.

[0138] Referring to Figure 7F, a bank 170 may be formed on the second connection electrode 220. After depositing an inorganic insulating material on the entire surface of the substrate 100, the bank 170 may be formed by removing a partial region of the deposited inorganic insulating material. In addition, the bank 170 has hydrophobicity and may include black particles. Specifically, a region overlapping with the light-emitting region EA may be removed from the inorganic insulating material deposited on the entire surface of the substrate 100. For example, the bank 170 may be formed on the planarization layer 160 and the second connection electrode 220 in the non-light-emitting region NEA.

[0139] Referring to Figure 7G , a first optical layer 410, an encapsulation layer 180, a black matrix 600, and a first color filter 710 may be sequentially formed on the substrate 100.

[0140] The first optical layer 410 may include a first base layer 411 and first wavelength conversion materials 412 distributed inside the first base layer 411. As described above, the first base layer 411 includes a transparent organic insulating material, and the first wavelength conversion materials 412 may be quantum dots, but are not limited thereto. In addition, the first optical layer 410 may completely cover the top surface and the side surface of the light-emitting diode 300 and fill the inside of the first opening OP1 and the second opening OP2. In addition, the first optical layer 410 may be formed by an inkjet process, and embodiments of the present disclosure are not limited thereto.

[0141] The encapsulation layer 180 may be formed on the entire surface of the substrate 100 and may be disposed in the light-emitting region EA and the non-light-emitting region NEA. The black matrix 600 and the first color filter 710 may be formed on the encapsulation layer 180. The black matrix 600 may be disposed in the non-light-emitting region NEA, and the first color filter 710 may be disposed in the light-emitting region EA.

[0142] Figure 8 is a cross-sectional view of a pixel P according to an exemplary embodiment of the present disclosure. That is, Figure 8 is a cross-sectional view taken along line II-II' in FIG. 2.

[0143] Referring to Figure 8 , a pixel SP according to an exemplary embodiment of the present disclosure may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. Since the first sub-pixel SP1 has the same structure as the structure of the second exemplary embodiment disclosed in Figure 4 , the same reference numerals are used, and repeated descriptions are omitted. In addition, except for the configurations of the optical layer 400 and the color filter 700, the second sub-pixel SP2 and the third sub-pixel SP3 have substantially the same structure as the first sub-pixel SP1. Therefore, the same reference numerals are used for the same components as those of the first sub-pixel SP1, and repeated descriptions are omitted.

[0144] As Figure 8 shown, the first sub-pixel SP1 may include a first optical layer 410. In addition, the first optical layer 410 may include a first base layer 411 and a first wavelength conversion material 412 distributed inside the first base layer 411. The first base layer 411 may include a transparent organic insulating material, and the first wavelength conversion material 412 may be a quantum dot, but the present disclosure is not limited thereto.

[0145] The first wavelength conversion material 412 may absorb blue light, convert the blue light into red light, and emit red light. Therefore, the first wavelength conversion material 412 may convert the blue light incident from the light emitting diode 300 into red light.

[0146] In addition, the first sub-pixel SP1 may include a first color filter 710. The first color filter 710 may transmit red light and block or absorb green light and blue light. That is, the red light converted by the first optical layer 410 may transmit through the first color filter 710. Therefore, the first sub-pixel SP may emit red light.

[0147] The second sub-pixel SP2 may include a second optical layer 420. In addition, the second optical layer 420 may include a second base layer 421 and a second wavelength conversion material 422 distributed inside the second base layer 421. The second base layer 421 may be formed of the same material as the first base layer 411. In addition, the second wavelength conversion material 422 may be a quantum dot. The diameter of the quantum dots of the second wavelength conversion material 422 may be different from the diameter of the quantum dots of the first wavelength conversion material 412. However, the present disclosure is not limited thereto, and the second base layer 421 may be formed of a material different from the first base layer 411.

[0148] The second wavelength conversion material 422 may absorb blue light, convert the blue light into green light, and emit green light. Therefore, the second wavelength conversion material 422 may convert the blue light incident from the light emitting diode 300 into green light.

[0149] In addition, the second sub-pixel SP2 may include a second color filter 720. The second color filter 720 may transmit green light and block or absorb red light and blue light. That is, the green light converted by the second optical layer 420 may transmit through the second color filter 720. Therefore, the second sub-pixel SP2 may emit green light.

[0150] The third sub-pixel SP3 may include a third optical layer 430. In addition, the third optical layer 430 may include a third base layer 431 and a scattering material 433 distributed inside the third base layer 431. The third base layer 431 may be formed of the same material as the first base layer 411 and the second base layer 421. However, the present disclosure is not limited thereto, and the third base layer 431 may be formed of a material different from the first base layer 411 and the second base layer 421.

[0151] When the third sub-pixel SP3 is a blue sub-pixel, the third sub-pixel SP3 may include a scattering material 433 instead of a wavelength conversion material. Specifically, since the light emitting diode 300 emits blue light, the third sub-pixel SP3 does not convert the wavelength of the light emitted from the light emitting diode 300. Therefore, the third sub-pixel SP3 may not include a wavelength conversion material.

[0152] The scattering material 433 scatters the light emitted from the light emitting diode 300, thereby changing the path of the light. Therefore, the light efficiency of the third sub-pixel SP3 can be improved. The scattering material 433 may include metal oxides such as titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), silicon dioxide (SiO2), zinc oxide (ZnO2), barium sulfate (BaSO4), or tin oxide (SnO2). Alternatively, the scattering material 433 may include an organic material such as polystyrene or polymethyl methacrylate (PMMA). However, the present disclosure is not limited thereto.

[0153] In addition, the third sub-pixel SP3 may include a third color filter 730. The third color filter 730 may transmit blue light and block or absorb red light and green light. That is, the blue light scattered by the third optical layer 430 may pass through the third color filter 730. Therefore, the third sub-pixel SP3 may emit blue light.

[0154] In summary, in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, each of the first optical layer 410 to the third optical layer 430 including the wavelength conversion materials 412 and 422 or the scattering material 432 may cover the top surface and the side surface of the light emitting diode 300. Therefore, the light efficiency of the light emitting diode 300 can be improved in each sub-pixel SP.

[0155] According to the present disclosure, the following advantageous effects can be obtained.

[0156] According to the present disclosure, a plurality of light conversion layers can be formed, so that the light efficiency can be improved and the reflectance caused by external light can be reduced.

[0157] Example embodiments of the present disclosure may also be described as follows:

[0158] According to an exemplary embodiment of the present disclosure, the display device may include: a substrate on which a plurality of sub-pixels are provided, each of the plurality of sub-pixels including a light-emitting region and a non-light-emitting region surrounding the light-emitting region; a plurality of light-emitting diodes provided in the light-emitting region on the substrate; a planarization layer provided on the light-emitting diodes, the planarization layer having an opening; and a plurality of optical layers provided on the planarization layer; wherein the planarization layer includes a central portion covering each of the plurality of light-emitting diodes and an outer portion surrounding the central portion, the central portion and the outer portion being spaced apart by the opening, and each of the plurality of optical layers covers the central portion of the planarization layer and fills the interior of the opening.

[0159] According to an exemplary embodiment of the present disclosure, at least one of the plurality of optical layers may include a base layer and a wavelength conversion material distributed inside the base layer.

[0160] According to an exemplary embodiment of the present disclosure, at least one of the plurality of optical layers may include a base layer and a scattering material distributed inside the base layer.

[0161] According to an exemplary embodiment of the present disclosure, an angle formed by a side surface of each of the central portion and the outer portion of the planarization layer with the substrate may be an acute angle.

[0162] According to an exemplary embodiment of the present disclosure, each of the central portion and the outer portion of the planarization layer may have a tapered shape with a slanted side surface.

[0163] According to an exemplary embodiment of the present disclosure, the planarization layer may include a first planarization layer provided on the substrate and a second planarization layer provided on the first planarization layer.

[0164] According to an exemplary embodiment of the present disclosure, the first planarization layer may include a first central portion covering the side surface of the light-emitting diode and a first outer portion surrounding the first central portion.

[0165] According to an exemplary embodiment of the present disclosure, the second planarization layer may include a second central portion covering the upper surface of the light-emitting diode and a second outer portion surrounding the second central portion.

[0166] According to an exemplary embodiment of the present disclosure, an angle formed by a side surface of the first central portion with the substrate and an angle formed by a side surface of the second central portion with the substrate may be different.

[0167] According to an exemplary embodiment of the present disclosure, the opening may include a first opening and a second opening overlapping the first opening. The first central portion and the first outer portion are spaced apart by the first opening, and the second central portion and the second outer portion are spaced apart by the second opening.

[0168] According to an exemplary embodiment of the present disclosure, the size of the second opening may be larger than the size of the first opening.

[0169] According to an exemplary embodiment of the present disclosure, each of the first planarization layer and the second planarization layer may include a scattering material.

[0170] According to an exemplary embodiment of the present disclosure, each of the plurality of sub-pixels may include a reflective layer, and the reflective layer includes a lower reflective layer disposed below the light-emitting diode and a side surface reflective layer disposed on the first planarization layer and the second planarization layer.

[0171] According to an exemplary embodiment of the present disclosure, the lower reflective layer overlaps the light-emitting diode.

[0172] According to an exemplary embodiment of the present disclosure, the side surface reflective layer faces the side surface of the light-emitting diode and is disposed on the side surface of the outer portion of the planarization layer.

[0173] According to an exemplary embodiment of the present disclosure, the plurality of sub-pixels includes a first sub-pixel that emits red light. The plurality of optical layers includes a first optical layer disposed in the first sub-pixel, and the first optical layer includes a first base layer and a first wavelength conversion material distributed inside the first base layer.

[0174] According to an exemplary embodiment of the present disclosure, the first wavelength conversion material is a quantum dot that absorbs blue light and converts the blue light into red light.

[0175] According to an exemplary embodiment of the present disclosure, the plurality of sub-pixels includes a third sub-pixel that emits blue light. The plurality of optical layers includes a third optical layer disposed in the third sub-pixel, and the third optical layer includes a third base layer and a scattering material distributed inside the third base layer.

[0176] According to an exemplary embodiment of the present disclosure, each of the plurality of light-emitting diodes includes: a first electrode connected to the source electrode of the thin-film transistor; a second electrode connected to the common voltage line; an active layer that emits light; a first semiconductor layer that provides holes to the active layer; and a second semiconductor layer that provides electrons to the active layer.

[0177] According to an exemplary embodiment of the present disclosure, each of the plurality of light-emitting diodes has a vertical structure in which the first electrode, the first semiconductor layer, the active layer, the second semiconductor layer, and the second electrode are sequentially stacked.

[0178] According to an exemplary embodiment of the present disclosure, each of the plurality of light-emitting diodes has a horizontal structure in which the active layer, the first semiconductor layer, and the first electrode are stacked on one side of the upper surface of the second semiconductor layer and the second electrode is stacked on the other side of the upper surface of the second semiconductor layer.

[0179] According to an exemplary embodiment of the present disclosure, the active layer, the first semiconductor layer, and the first electrode are spaced apart from the second electrode by the planarization layer.

[0180] According to an exemplary embodiment of the present disclosure, the display device may further include a bank disposed on the outside of the planarization layer, and wherein the bank is hydrophobic and includes a light-absorbing material.

[0181] According to an exemplary embodiment of the present disclosure, the display device may include: a substrate on which a plurality of sub-pixels are disposed, each of the plurality of sub-pixels including a light-emitting region and a non-light-emitting region surrounding the light-emitting region; a plurality of light-emitting diodes disposed on the substrate in the light-emitting region; a planarization layer disposed on the light-emitting diodes; and a plurality of optical layers disposed on the planarization layer; wherein the planarization layer includes an opening surrounding the light-emitting diodes, the planarization layer includes a central portion and an outside, and the central portion is surrounded by the opening, and the outside is located outside the opening.

[0182] According to an exemplary embodiment of the present disclosure, the opening has an annular shape centered on the light-emitting diode.

[0183] According to an exemplary embodiment of the present disclosure, the central portion and the outside of the planarization layer are spaced apart by the opening.

[0184] According to an exemplary embodiment of the present disclosure, the display device may further include a plurality of optical layers disposed on the planarization layer, and wherein each of the plurality of optical layers covers the light-emitting diodes, the central portion of the planarization layer, and the opening.

[0185] According to an exemplary embodiment of the present disclosure, the plurality of sub-pixels include a first sub-pixel that emits red light, a second sub-pixel that emits green light, and a third sub-pixel that emits blue light.

[0186] According to an exemplary embodiment of the present disclosure, the light-emitting diode emits blue light, the plurality of optical layers include a first optical layer disposed in the first sub-pixel, a second optical layer disposed in the second sub-pixel, and a third optical layer disposed in the third sub-pixel, the first optical layer includes quantum dots that absorb the first blue light and convert the first blue light into red light, the second optical layer includes quantum dots that absorb the second blue light and convert the second blue light into green light, and the third optical layer includes a scattering material.

[0187] According to an exemplary embodiment of the present disclosure, the display device may further include a bank disposed on the outside of the planarization layer, and wherein the bank is hydrophobic and includes a light-absorbing material.

[0188] It will be apparent to those skilled in the art that the above present disclosure is not limited by the above exemplary embodiments and the drawings, and various substitutions, modifications, and variations can be made in the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the scope of the present disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims fall within the scope of the present disclosure.

[0189] Cross-reference to related applications

[0190] This application claims the priority and benefits of Korean Patent Application No. 10-2023-0188381, filed on December 21, 2023, the entire content of which is hereby incorporated herein by reference for all purposes.

Claims

1. A display device, comprising: A substrate, on which a plurality of sub-pixels are arranged, each of the plurality of sub-pixels comprising a light-emitting region and a non-light-emitting region surrounding the light-emitting region; a plurality of light emitting diodes, wherein the plurality of light emitting diodes are arranged on the substrate in the light emitting area; A planarization layer, wherein the planarization layer is disposed on the light emitting diode and has an opening; as well as a plurality of optical layers, the plurality of optical layers being disposed on the planarization layer, wherein the planarization layer includes a central portion covering each of the plurality of light emitting diodes and an outer portion surrounding the central portion, The central portion and the outer portion are separated by the opening, and Each of the plurality of optical layers covers the central portion of the planarization layer and fills the inside of the opening.

2. The display device according to claim 1, wherein: At least one of the plurality of optical layers includes a base layer and a wavelength conversion material distributed inside the base layer.

3. The display device according to claim 1, wherein: At least one of the plurality of optical layers includes a base layer and a scattering material distributed inside the base layer.

4. The display device according to claim 1, wherein: An angle formed by a side surface of each of the central portion and the outer portion of the planarization layer and the substrate is an acute angle.

5. The display device according to claim 1, wherein: Each of the central portion and the outer portion of the planarization layer has a tapered shape with an inclined side surface.

6. The display device according to claim 1, wherein: The planarization layer includes a first planarization layer disposed on the substrate and a second planarization layer disposed on the first planarization layer. The first planarization layer includes a first central portion covering a side surface of the light emitting diode and a first outer portion surrounding the first central portion, and The second planarization layer includes a second central portion covering an upper surface of the light emitting diode and a second outer portion surrounding the second central portion.

7. The display device according to claim 6, wherein: An angle formed by a side surface of the first center portion and the substrate is different from an angle formed by a side surface of the second center portion and the substrate.

8. The display device according to claim 6, wherein: The opening includes a first opening and a second opening overlapping the first opening, The first central portion and the first outer portion are separated by the first opening, and The second central portion and the second outer portion are separated by the second opening.

9. The display device according to claim 8, wherein: The size of the second opening is larger than the size of the first opening.

10. The display device according to claim 6, wherein: Each of the first planarization layer and the second planarization layer includes a scattering material.

11. The display device according to claim 6, wherein: Each of the plurality of sub-pixels includes a reflective layer, and The reflective layer includes a lower reflective layer disposed under the light emitting diode and a side surface reflective layer disposed on the first planarization layer and the second planarization layer.

12. The display device according to claim 11, wherein: The low reflection layer overlaps the light emitting diode.

13. The display device according to claim 11, wherein: The side surface reflective layer faces a side surface of the light emitting diode and is disposed on the outer side surface of the planarization layer.

14. The display device according to claim 1, wherein: The plurality of sub-pixels include a first sub-pixel that emits red light, The plurality of optical layers include a first optical layer disposed in the first sub-pixel, and The first optical layer includes a first base layer and a first wavelength conversion material distributed inside the first base layer.

15. The display device according to claim 14, wherein: The first wavelength conversion material is a quantum dot that absorbs blue light and converts the blue light into red light.

16. The display device according to claim 1, wherein: The plurality of sub-pixels include a third sub-pixel emitting blue light, The plurality of optical layers include a third optical layer disposed in the third sub-pixel, and The third optical layer includes a third substrate and a scattering material distributed inside the third substrate.

17. The display device according to claim 1, wherein: Each of the plurality of light emitting diodes comprises: A first electrode connected to a source electrode of the thin film transistor; a second electrode, the second electrode being connected to a common voltage line; an active layer, the active layer emitting light; a first semiconductor layer providing holes to the active layer; and A second semiconductor layer provides electrons to the active layer.

18. The display device according to claim 17, wherein: Each of the plurality of light emitting diodes has a vertical structure in which the first electrode, the first semiconductor layer, the active layer, the second semiconductor layer, and the second electrode are sequentially stacked.

19. The display device according to claim 17, wherein: Each of the plurality of light emitting diodes has a horizontal structure in which the active layer, the first semiconductor layer, and the first electrode are stacked on one side of an upper surface of the second semiconductor layer, and the second electrode is stacked on the other side of the upper surface of the second semiconductor layer.

20. The display device according to claim 19, wherein: The active layer, the first semiconductor layer, and the first electrode are spaced apart from the second electrode by the planarization layer.

21. The display device according to claim 1, further comprising a bank provided on the outer portion of the planarization layer, and in, The banks are hydrophobic and include a light absorbing material.

22. A display device, comprising: A substrate, on which a plurality of sub-pixels are arranged, each of the plurality of sub-pixels comprising a light-emitting region and a non-light-emitting region surrounding the light-emitting region; a plurality of light emitting diodes, wherein the plurality of light emitting diodes are arranged on the substrate in the light emitting area; A planarization layer, wherein the planarization layer is disposed on the light emitting diode; as well as a plurality of optical layers, the plurality of optical layers being disposed on the planarization layer, wherein the planarization layer comprises an opening surrounding the light emitting diode, The planarization layer includes a central portion and an outer portion, and The central portion is surrounded by the opening, and the outer portion is located outside the opening.

23. The display device according to claim 22, wherein: The opening has a ring shape centered on the light emitting diode.

24. The display device according to claim 22, wherein: The central portion and the outer portion of the planarization layer are separated by the opening.

25. The display device according to claim 22, further comprising a plurality of optical layers disposed on the planarization layer, and in, Each of the plurality of optical layers covers the light emitting diode, the central portion of the planarization layer, and the opening.

26. The display device according to claim 25, wherein: The plurality of sub-pixels include a first sub-pixel emitting red light, a second sub-pixel emitting green light, and a third sub-pixel emitting blue light.

27. The display device according to claim 26, wherein: The light emitting diode emits blue light, The plurality of optical layers include a first optical layer disposed in the first sub-pixel, a second optical layer disposed in the second sub-pixel, and a third optical layer disposed in the third sub-pixel, The first optical layer includes quantum dots that absorb first blue light and convert the first blue light into red light, The second optical layer includes quantum dots that absorb the second blue light and convert the second blue light into green light, and The third optical layer includes a scattering material.

28. The display device according to claim 22, further comprising a bank provided on the outer portion of the planarization layer, and in, The banks are hydrophobic and include a light absorbing material.

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