Display panel and display device

Abstract

The invention relates to a display panel and a display device, and relates to the technical field of display. The display panel comprises a substrate, a driving layer, a pixel layer and a thin film packaging layer which are sequentially stacked, the thin film packaging layer comprises a first inorganic packaging layer, an organic packaging layer, an insertion layer and a second inorganic packaging layer which are sequentially arranged on one side of the pixel layer in a stacked mode. And the stability of the intercalation layer under the bombardment of the plasma gas is greater than that of the organic encapsulation layer under the bombardment of the plasma gas. The insertion layer is additionally arranged between the organic packaging layer and the second inorganic packaging layer of the thin film packaging layer, so that the influence on the organic packaging layer when the second inorganic packaging layer is formed is avoided, and the display performance of the display panel is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and more particularly, to a display panel and a display device. Background Art

[0002] With the application of flexible OLED displays in the automotive field, the reliability requirements for products are getting higher and higher. In the original film encapsulation structure for automotive reliability, there are problems such as mini GDS (Mini Global Dark Spot), which are small black spots or dark spots formed due to local pixel failure. As Figure 1 shown, the mechanism of mini GDS is as follows: foreign particles that are inevitable during the evaporation process of the materials in the pixel layer PXL will cause gaps to appear when the first inorganic encapsulation layer CVD1 is formed. When the second inorganic encapsulation layer CVD2 is formed, plasma with a certain energy bombards the surface of the organic encapsulation layer IJP, generating outgas. This gas can enter the pixel layer PXL along the encapsulation gaps of the first inorganic encapsulation layer CVD1, resulting in mini GDS defects. Currently, the general encapsulation structure is the first inorganic encapsulation layer CVD1, the organic encapsulation layer IJP, and the second inorganic encapsulation layer CVD2 arranged in a stacked manner. It is inevitable that when the second inorganic encapsulation layer CVD2 is formed, the plasma directly contacts the organic encapsulation layer IJP, generating outgas.

[0003] Automotive products are mostly large-sized products, and the number of foreign particles (Particles) in a single display panel is almost 2 - 3 times that of small-sized products (mobile phones). Due to the evaporation process, it is very difficult to completely improve the number of foreign particles.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] An object of the present disclosure is to overcome the above-mentioned deficiencies of the prior art, and to provide a display panel and a display device, which can improve the yield and reliability of the display panel by adding an interlayer in the thin film encapsulation layer.

[0006] According to one aspect of the present disclosure, there is provided a display panel, including a display area and a peripheral area located on at least one side of the display area. The display panel includes:

[0007] A substrate;

[0008] A driving layer disposed on one side of the substrate;

[0009] A pixel layer disposed on the side of the driving layer away from the substrate;

[0010] The thin film encapsulation layer is disposed on the side of the pixel layer away from the substrate; the thin film encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, an interlayer, and a second inorganic encapsulation layer that are sequentially stacked on one side of the pixel layer;

[0011] The stability of the interlayer under plasma gas bombardment is greater than the stability of the organic encapsulation layer under plasma gas bombardment.

[0012] In an exemplary embodiment of the present disclosure, the orthographic projection of the display area on the substrate is located within the orthographic projection of the interlayer on the substrate.

[0013] In an exemplary embodiment of the present disclosure, the display panel further includes a first barrier wall surrounding the display area and a second barrier wall surrounding the first barrier wall;

[0014] The edge of the organic encapsulation layer is located between the display area and the first barrier wall;

[0015] The edge of the interlayer is located between the first barrier wall and the second barrier wall.

[0016] In an exemplary embodiment of the present disclosure, the edge of the interlayer is located within the edge of the first inorganic encapsulation layer and within the edge of the second inorganic encapsulation layer; the edge regions of the first inorganic encapsulation layer and the second inorganic encapsulation layer directly overlap each other.

[0017] In an exemplary embodiment of the present disclosure, the material of the interlayer is a transparent inorganic material.

[0018] In an exemplary embodiment of the present disclosure, the interlayer is a transparent conductive layer, and at least one side of the transparent conductive layer is provided with a conductive lead for performing a power-on test on the interlayer.

[0019] In an exemplary embodiment of the present disclosure, the interlayer is a film layer formed by an evaporation process or a coating process.

[0020] In an exemplary embodiment of the present disclosure, the interlayer includes a lithium fluoride interlayer, a silicon nitride interlayer, an indium tin oxide interlayer, or a graphene interlayer.

[0021] In an exemplary embodiment of the present disclosure, there is at least one foreign particle on the surface of the pixel layer, and there is a crack in the first inorganic encapsulation layer at the foreign particle.

[0022] According to another aspect of the present disclosure, there is also provided a display device including the above display panel.

[0023] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. Description of the Drawings

[0024] The accompanying drawings here are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0025] Figure 1 In the related art, it is a schematic partial cross-sectional view of a display panel.

[0026] Figure 2 In one embodiment of the present disclosure, it is a top view of a display panel.

[0027] Figure 3 In one embodiment of the present disclosure, it is a schematic cross-sectional view of a thin film encapsulation layer of a display panel.

[0028] Figure 4 In one embodiment of the present disclosure, it is a schematic partial cross-sectional view of a display panel.

[0029] Figure 5 In one embodiment of the present disclosure, it is a schematic cross-sectional view of a display panel.

[0030] Figure 6 In one embodiment of the present disclosure, it is a top view of a display panel.

[0031] Figure 7 In one embodiment of the present disclosure, it is a top view of a display panel.

[0032] Figure 8 In one embodiment of the present disclosure, it is a top view of a display panel.

[0033] Figure 9 In one embodiment of the present disclosure, it is a top view of a display panel.

[0034] The reference numerals are as follows:

[0035] AA, Display area; BB, Peripheral area; BM, Black matrix layer; BUF, Inorganic buffer layer; CFL, Color film layer; CFU, Color film unit; COML, Common electrode layer; CVD1, First inorganic encapsulation layer; CVD2, Second inorganic encapsulation layer; DAM1, First barrier wall; DAM2, Second barrier wall; DH, Row direction; DL, Data line; DPL, Display layer; DRL, Driver layer; DU, Display unit; DV, Column direction; EFL, Light-emitting functional layer; GI, Gate insulating layer; GI1, First gate insulating layer; GI2, Second gate insulating layer; GI3, Third gate insulating layer; GL, Scan line; GT, Gate metal layer; GT1, First gate metal layer; GT2, Second gate metal layer; IJP, Organic encapsulation layer; ILD, Interlayer dielectric layer; INC, Intercalation layer; MF, Wiring unit layer; MF1, First wiring unit layer; MF2, Second wiring unit layer; MRL, Wiring layer; OC, Protective layer; OSCL, Metal oxide semiconductor layer; PDC, Pixel driving circuit; PDL, Pixel definition layer; PEL, Pixel electrode layer; PLN, Planarization layer; PLN1, First planarization layer; PLN2, Second planarization layer; PNL, Display panel; PSCL, Polysilicon semiconductor layer; PX, Sub-pixel; PXL, Pixel layer; SBT, Substrate; SCL, Semiconductor layer; SD, Source-drain metal layer; SD1, First source-drain metal layer; SD2, Second source-drain metal layer; TFE, Thin film encapsulation layer; TFTL, Transistor layer; TLD, Touch insulating layer; TMA, First touch metal layer; TMB, Second touch metal layer; TSL, Touch functional layer; CL, Conductive lead. Detailed implementation manners

[0036] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0037] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component described as "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0038] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", "third", etc. are used only as labels and are not a limitation on the quantity of their objects.

[0039] In the present disclosure, when it is described that structure A and structure B are stacked, it means that structure A and structure B are respectively in different film layers, but the orthographic projection of structure A on the substrate and the orthographic projection of structure B on the substrate at least partially overlap.

[0040] In the present disclosure, when it is described that structure C covers structure D, it means that structure C is located on the side of structure D away from the substrate, and the orthographic projection of structure D on the substrate is located within the orthographic projection of structure C on the substrate.

[0041] In the related art, such as Figure 1As shown in the figure, the display panel includes a substrate substrate SBT, a driving circuit layer DRL, a pixel layer PXL, and a packaging structure which are sequentially stacked. Sub-pixels PX are provided in the pixel layer PXL. The packaging structure is disposed on the side of the pixel layer PXL away from the substrate substrate SBT, and includes a first inorganic packaging layer CVD1, an organic packaging layer IJP, and a second inorganic packaging layer CVD2 which are sequentially stacked. During the preparation of the pixel layer PXL, foreign particles are inevitably introduced on the surface, resulting in incomplete coating of the foreign particles by the first inorganic packaging layer CVD1 when forming the first inorganic packaging layer CVD1, so that there are gaps in the film layer of the first inorganic packaging layer CVD1. Thus, when the second inorganic packaging layer CVD2 is formed by chemical vapor deposition, the plasma of the chemical vapor deposition bombards the surface of the organic packaging layer IJP, and the organic packaging layer IJP generates an outgas phenomenon. The generated gas enters the pixel layer PXL through the gaps in the film layer of the first inorganic packaging layer CVD1, causing small black spots to appear in the corresponding sub-pixels PX, resulting in the reliability failure of the display panel. Through the reliability verification of thousands of products, it is found that the size and height of the foreign objects causing the film formation gaps in the first inorganic packaging layer CVD1 have no obvious rules. According to the causes of mini GDS, improving mini GDS can be considered from the following three aspects: 1. Reduce foreign particles; 2. Make the first inorganic packaging layer CVD1 completely cover the foreign particles; 3. Reduce the outgas phenomenon of the organic packaging layer IJP. However, due to the limitations of the evaporation process characteristics of the light-emitting functional layer in the pixel layer PXL and the process characteristics of the first inorganic packaging layer CVD1 and the second inorganic packaging layer CVD2, the possibility of achieving zero foreign particles or complete coverage of the foreign particles by the first inorganic packaging layer CVD1 is extremely low.

[0042] To solve the above problems, the present disclosure provides a display panel, as Figure 2 shown, the display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA. As Figure 3 shown, the display panel PNL includes a substrate substrate SBT, a driving circuit layer DRL, a pixel layer PXL, and a thin film encapsulation layer TFE. The driving circuit layer DRL is disposed on one side of the substrate substrate SBT. The pixel layer PXL is disposed on the side of the driving circuit layer DRL away from the substrate substrate SBT. The thin film encapsulation layer TFE is disposed on the side of the pixel layer PXL away from the substrate substrate SBT. The thin film encapsulation layer TFE includes a first inorganic packaging layer CVD1, an organic packaging layer IJP, an interlayer INC, and a second inorganic packaging layer CVD2 which are sequentially stacked on one side of the pixel layer PXL. The stability of the interlayer INC under plasma gas bombardment is greater than the stability of the organic packaging layer IJP under plasma gas bombardment.

[0043] In this embodiment, an interlayer INC is disposed between the organic encapsulation layer IJP and the second inorganic encapsulation layer CVD2. On the one hand, the stability of the interlayer INC under the bombardment of plasma gas is greater than that of the organic encapsulation layer IJP under the bombardment of plasma gas, reducing the influence of the outgas phenomenon on the light-emitting functional layer. On the other hand, the second inorganic encapsulation layer CVD2 is formed on the side of the interlayer INC away from the substrate SBT, which can avoid the outgas phenomenon caused by the bombardment of the plasma on the organic encapsulation layer IJP when the second inorganic encapsulation layer CVD2 is formed, thereby preventing gas from entering the pixel layer PXL and affecting the display effect of the sub-pixels. Thus, by setting the interlayer INC, the influence of the process of preparing the second inorganic encapsulation layer CVD2 on the organic encapsulation layer IJP can be significantly reduced, the occurrence of mini GDS can be reduced, and the yield and reliability of the display panel can be improved.

[0044] In one embodiment of the present disclosure, as Figure 2 shown, the display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA. In the display area AA, the display panel PNL is provided with display units DU arranged in an array, and the display unit DU includes a sub-pixel PX and a pixel driving circuit PDC for driving the sub-pixel PX. The display panel PNL does not provide display units DU in the peripheral area BB, or the provided display units DU are not used for displaying images. In Figure 2 the example, the display panel PNL is provided with a plurality of scan lines GL extending in the row direction DH in the display area AA, and each scan line GL is correspondingly arranged with each display unit row. The pixel driving circuits PDC of each display unit DU in the display unit row are all electrically connected to the corresponding scan line GL. The display panel PNL is further provided with a plurality of data lines DL extending in the column direction DV in the display area AA, and each data line DL is correspondingly arranged with each display unit column. The pixel driving circuits PDC of each display unit DU in the display unit column are all electrically connected to the corresponding data line DL. Thus, the pixel driving circuit PDC of each display unit DU is connected to a scan line GL and a data line DL. When a scan signal is loaded on the scan line GL, the driving voltage loaded on the data line DL can be written into the pixel driving circuit PDC, and then the pixel driving circuit PDC can control the brightness of the sub-pixel PX according to the written driving voltage. It can be understood that in other embodiments of the present disclosure, the arrangement manner of the display units DU and the connection manner with the wiring such as the data lines DL and the scan lines GL may also be different from Figure 2 the example.

[0045] Figure 4 In one embodiment of the present disclosure, it is a partial cross-sectional schematic diagram of the display panel PNL. In Figure 4In an example, the display panel PNL may include a substrate SBT, a display layer DPL, a thin film encapsulation layer TFE, and a touch function layer TSL that are sequentially stacked. Among them, sub-pixels PX and a pixel driving circuit PDC for driving the sub-pixels PX are provided in the display layer DPL. The thin film encapsulation layer TFE is used to encapsulate and protect the sub-pixels PX, and the touch function layer TSL is used to implement the touch function.

[0046] In one example, referring to Figure 4 , the display layer DPL may include a driving circuit layer DRL and a pixel layer PXL that are sequentially stacked on one side of the substrate SBT; sub-pixels PX are provided in the pixel layer PXL, and a pixel driving circuit PDC for driving the sub-pixels PX is provided in the driving circuit layer DRL. Each sub-pixel PX can emit light under the drive of the pixel driving circuit PDC to display an image.

[0047] Optionally, the substrate SBT may be a substrate of an inorganic material or a substrate of an organic material; of course, it may also be a composite substrate formed by laminating a substrate of an inorganic material and a substrate of an organic material. For example, in some embodiments of the present disclosure, the material of the substrate SBT may be glass materials such as soda-lime glass, quartz glass, and sapphire glass. In some other embodiments of the present disclosure, the material of the substrate SBT may be polymethyl methacrylate, polyvinyl alcohol, polyvinylphenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In some other embodiments of the present disclosure, the substrate SBT may also be a flexible substrate, for example, the material of the substrate SBT may be polyimide.

[0048] Optionally, in the driving circuit layer DRL, any one pixel driving circuit PDC may include a transistor (such as a thin film transistor) and a storage capacitor. Further, the transistor may be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a double-gate thin film transistor; the material of the active layer of the thin film transistor may be an amorphous silicon semiconductor material, a low-temperature polycrystalline silicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material, or other types of semiconductor materials; the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

[0049] It can be understood that among the various transistors in the pixel driving circuit, the types of any two transistors can be the same or different. Exemplarily, in some embodiments, in a pixel driving circuit, some transistors can be N-type transistors and some transistors can be P-type transistors. Further exemplarily, in some other embodiments, in a pixel driving circuit, the material of the active layer of some transistors can be a low-temperature polycrystalline silicon semiconductor material, and the material of the active layer of some transistors can be a metal oxide semiconductor material. In some embodiments of the present disclosure, the thin-film transistor is a low-temperature polycrystalline silicon transistor. In some other embodiments of the present disclosure, some thin-film transistors are low-temperature polycrystalline silicon transistors and some thin-film transistors are metal oxide transistors.

[0050] Optionally, the driving circuit layer DRL may include a semiconductor layer SCL, a gate insulating layer GI, a gate metal layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, a planarization layer PLN, etc., which are stacked between the substrate SBT and the pixel layer PXL. Each thin-film transistor and storage capacitor can be formed by film layers such as the semiconductor layer SCL, the gate insulating layer GI, the gate metal layer GT, the interlayer dielectric layer ILD, and the source-drain metal layer SD. Among them, the positional relationship of each film layer can be determined according to the film layer structure of the thin-film transistor. Further, the semiconductor layer SCL can be used to form the channel region of the transistor, and in necessary cases, it can also form part of the traces or conductive structures through conductorization. The gate layer can be used to form one or more of the gate layer traces such as the scan trace, the reset control trace, and the light emission control trace, and can also be used to form the gate of the transistor and part or all of the electrode plates of the storage capacitor. The source-drain metal layer can be used to form the source-drain metal layer traces such as the data trace and the driving power supply voltage trace, and can also be used to form part of the electrode plates of the storage capacitor. Of course, in other embodiments of the present disclosure, the driving circuit layer DRL may also include other film layers according to needs, for example, it may also include a light-shielding layer located between the semiconductor layer SCL and the substrate SBT. According to needs, any one of the above film layers such as the semiconductor layer SCL, the gate metal layer GT, and the source-drain metal layer SD can also be multi-layered. For example, the driving circuit layer DRL may include two different semiconductor layers SCL, or include two or three source-drain metal layers SD, or include two or three gate metal layers GT; correspondingly, the insulating film layers (such as the gate insulating layer GI, the interlayer dielectric layer ILD, the planarization layer PLN, etc.) in the driving circuit layer DRL can be increased or decreased adaptively, or new insulating film layers can be added according to needs. Optionally, the driving circuit layer DRL may further include a passivation layer, and the passivation layer can be disposed on the surface of the source-drain metal layer SD away from the substrate SBT to protect the source-drain metal layer SD.

[0051] In an embodiment of the present disclosure, the film layer between the substrate SBT and the first source-drain metal layer SD1 can be regarded as a whole and referred to as the transistor layer TFTL. The transistor layer TFTL has a semiconductor layer SCL, a gate insulating layer GI, and a gate metal layer GT required for forming a thin-film transistor. For example, in Figure 4 's example, the transistor layer TFTL includes an inorganic buffer layer BUF, a polysilicon semiconductor layer PSCL, a first gate insulating layer GI1, a first gate metal layer GT1, a second gate insulating layer GI2, a metal oxide semiconductor layer OSCL, a third gate insulating layer GI3, a second gate metal layer GT2, and an interlayer dielectric layer ILD, which are sequentially stacked on one side of the substrate SBT. In Figure 4 's example, the driving circuit layer DRL includes two semiconductor layers SCL (a polysilicon semiconductor layer PSCL and a metal oxide semiconductor layer OSCL), three gate insulating layers GI (a first gate insulating layer GI1, a second gate insulating layer GI2, and a third gate insulating layer GI3), two gate metal layers GT (a first gate metal layer GT1 and a second gate metal layer GT2), two source-drain metal layers SD (a first source-drain metal layer SD1 and a second source-drain metal layer SD2), and two planarization layers PLN (a first planarization layer PLN1 and a second planarization layer PLN2). Among them, the polysilicon semiconductor layer PSCL, the first gate insulating layer GI1, and the first gate metal layer GT1 can form a low-temperature polysilicon thin-film transistor, and the first gate metal layer GT1, the second gate insulating layer GI2, the metal oxide semiconductor layer OSCL, the third gate insulating layer GI3, and the second gate metal layer GT2 can form a metal oxide thin-film transistor. Thus, the display panel PNL is a display panel adopting the LTPO technology.

[0052] In an embodiment of the present disclosure, the structure between the transistor layer TFTL and the pixel layer PXL can be referred to as the wiring layer MRL. One of the important functions of the wiring layer MRL is to realize the electrical connection between different devices, such as realizing the electrical connection between thin-film transistors, storage capacitors, and sub-pixels PX. Optionally, the wiring layer MRL can include one or more wiring unit layers MF, and each wiring unit layer MF can include a source-drain metal layer SD and a planarization layer PLN located on the side of the source-drain metal layer SD away from the substrate SBT. It can be understood that in some examples, the wiring unit layer MF can further include a passivation layer, and the passivation layer can be disposed between the source-drain metal layer SD and the planarization layer PLN to protect the source-drain metal layer SD.

[0053] For example, in Figure 4In the example, the wiring layer MRL includes a first source-drain metal layer SD1, a first planarization layer PLN1, a second source-drain metal layer SD2, and a second planarization layer PLN2 that are sequentially stacked on the side of the transistor layer TFTL away from the substrate SBT. Thus, the wiring layer MRL includes two wiring unit layers MF, namely, a first wiring unit layer MF1 (including the first source-drain metal layer SD1 and the first planarization layer PLN1) and a second wiring unit layer MF2 (including the second source-drain metal layer SD2 and the second planarization layer PLN2). When the display panel PNL requires more source-drain metal layers SD, the number of wiring unit layers MF can be adaptively increased (i.e., the source-drain metal layer SD and the planarization layer PLN are increased synchronously). For example, when the display panel PNL is provided with three source-drain metal layers SD, the wiring layer MRL includes a first source-drain metal layer SD1, a first planarization layer PLN1, a second source-drain metal layer SD2, a second planarization layer PLN2, a third source-drain metal layer, and a third planarization layer (the third source-drain metal layer and the third planarization layer serve as the third wiring unit layer) that are sequentially stacked.

[0054] In an embodiment of the present disclosure, referring to Figure 4 , the sub-pixel PX in the pixel layer PXL is a thin-film light-emitting element, which may include two electrodes stacked and a light-emitting functional unit sandwiched between the two electrodes. In Figure 4 's example, the pixel layer PXL may include a pixel electrode layer PEL, a pixel definition layer PDL, a light-emitting functional layer EFL, and a common electrode layer COML that are sequentially stacked. Among them, the pixel electrode layer PEL has a plurality of pixel electrodes in the display area of the display panel. The pixel definition layer PDL has a plurality of through pixel openings corresponding to the plurality of pixel electrodes one by one, and any one pixel opening exposes at least a partial area of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edge of the pixel electrode and exposes at least a partial internal area of the pixel electrode, so that the pixel definition layer PDL can effectively define the actual effective area of the pixel electrode (the area directly connected to the light-emitting functional layer EFL), and further define the light-emitting area and light-emitting area of the sub-pixel PX. The light-emitting functional layer EFL covers at least the pixel electrode exposed by the pixel definition layer PDL. The common electrode layer COML can cover the light-emitting functional layer EFL in the display area. The pixel electrode and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer EFL, so that the light-emitting functional layer EFL emits light. The portion of the light-emitting functional layer EFL located between the pixel electrode and the common electrode layer COML can serve as the light-emitting functional unit. The pixel electrode, the common electrode layer COML, and the light-emitting functional unit form the sub-pixel PX. Among them, one of the pixel electrode and the common electrode layer COML serves as the anode of the sub-pixel PX, and the other serves as the cathode of the sub-pixel PX.

[0055] In one embodiment of the present disclosure, the display panel further includes a support pillar layer (not shown in Figure 4 ) located on the side of the pixel definition layer PDL away from the substrate. The support pillar layer is used to form a plurality of support pillars to support a fine metal mask plate during the evaporation process. In one example, the support pillar layer and the pixel definition layer PDL can be made of the same material and prepared in the same process. For example, a grayscale mask process can be used on the same organic material layer to form the pixel definition layer and the support pillar layer simultaneously. In another example, after forming the pixel definition layer, a new organic material layer can be coated and patterned to form the respective support pillars of the support pillar layer. Figure 4 In one example, the pixel electrode serves as the anode of the sub-pixel PX, and the common electrode layer COML serves as the cathode of the sub-pixel PX.

[0056] In one example, the pixel electrode serves as the anode of the sub-pixel PX, and the common electrode layer COML serves as the cathode of the sub-pixel PX.

[0057] In Figure 4 the example of Figure 4 , the sub-pixel PX is an organic light-emitting diode (OLED). It can be understood that in other embodiments of the present disclosure, the sub-pixel can also be other types of light-emitting elements, such as current-driven light-emitting elements like QLED, PLED, Micro LED, Mini LED, etc.

[0058] In Figure 4 the example of Figure 4 , the thin film encapsulation layer TFE can be disposed on the surface of the pixel layer PXL away from the substrate SBT. It can include a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, an interlayer INC, and a second inorganic encapsulation layer CVD2 that are sequentially stacked on the side of the pixel layer PXL away from the substrate SBT. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PXL and causing the materials in the pixel layer PXL to age. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce the stress between the inorganic encapsulation layers. The interlayer INC is located between the organic encapsulation layer IJP and the second inorganic encapsulation layer CVD2, and is used to protect the surface of the organic encapsulation layer IJP away from SBT, avoiding the influence of plasma on the organic encapsulation layer IJP when preparing the second inorganic encapsulation layer CVD2.

[0059] In another embodiment of the present disclosure, it includes a plurality of inorganic encapsulation layers and organic encapsulation layers that are alternately stacked. An interlayer INC can be provided on the side of the organic encapsulation layer away from the substrate SBT. For example, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer CVD1, a first organic encapsulation layer IJP1, a second inorganic encapsulation layer CVD2, a second organic encapsulation layer IJP2, and a third inorganic encapsulation layer CVD3. An interlayer INC can be provided on the side of the first organic encapsulation layer IJP1 away from the substrate SBT and on the side of the second organic encapsulation layer IJP2 away from the substrate SBT.

[0060] In Figure 4 the example of, the touch function layer TSL can be disposed on a side of the thin film encapsulation layer TFE away from the pixel layer PXL, so that the display panel PNL has a touch function. In Figure 4 the example of, the touch function layer TSL includes a first touch metal layer TMA, a touch insulation layer TLD, and a second touch metal layer TMB that are sequentially stacked on the surface of the thin film encapsulation layer TFE. It can be understood that, in other examples, the touch function layer TSL may further include an insulating layer or an organic layer covering the second touch metal layer TMB.

[0061] In Figure 4 the example of, the touch function layer TSL includes two metal layers. It can be understood that, in other embodiments of the present disclosure, the touch function layer TSL may also include more metal layers or use fewer metal layers.

[0062] In an embodiment of the present disclosure, referring to Figure 4 , the display panel PNL may further include a color filter layer CFL located on a side of the touch function layer TSL away from the substrate SBT. The color filter layer CFL has color filter units CFU corresponding to the sub-pixels PX. For example, a red color filter unit is disposed above the red sub-pixel, a green color filter unit is disposed above the green sub-pixel, and a blue color filter unit is disposed above the blue sub-pixel. In this way, the light emission color purity of the display panel PNL can be improved, thereby facilitating the improvement of the color gamut of the display panel PNL, and the interference of ambient light on normal display can also be reduced. In one example, referring to Figure 4 , the color filter layer CFL further has a black matrix layer BM. The black matrix layer BM can be located between the sub-pixels PX to reduce light emission crosstalk, and can further reduce the reflection of ambient light.

[0063] In an embodiment of the present disclosure, referring to Figure 4 , the display panel PNL may further include a protective layer OC. The protective layer OC can be disposed on the surface of the display panel PNL away from the substrate SBT to protect the display panel PNL. In Figure 4 the example of, the protective layer OC is disposed on the surface of the color filter layer CFL away from the substrate SBT.

[0064] In an embodiment of the present disclosure, the orthographic projection of the display area AA on the substrate SBT is located within the orthographic projection of the interlayer INC on the substrate SBT. That is to say, the edge of the interlayer INC can coincide with the edge of the display area AA, or the edge of the interlayer INC can be located in the peripheral area BB. In this way, the interlayer INC can at least cover the display area AA, avoiding the influence of outgas generated by the organic encapsulation layer IJP stacked corresponding to the display area AA on the sub-pixels PX on the display panel PNL.

[0065] In one example, as Figure 5 and Figure 6 shown, the edge of the interlayer INC can be located between the display area AA and the first dam DAM1. It can be understood that the organic encapsulation layer IJP is stacked between two film layers of the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2, which can relieve the stress of the inorganic encapsulation layer and prevent cracks caused by mechanical bending or thermal expansion of the inorganic encapsulation layer; it can also provide a deposition plane for the second inorganic encapsulation layer CVD2 through the leveling of the organic encapsulation layer. However, the barrier effect of the organic encapsulation layer IJP on water and oxygen penetration is weak. Therefore, the overlapping width of the edge of the first inorganic encapsulation layer CVD1 and the edge of the second inorganic encapsulation layer CVD2 should be maximized as much as possible. In this example, by extending the edge of the interlayer INC to be arranged between the display area AA and the first dam DAM1, while ensuring the overlapping width of the edge of the first inorganic encapsulation layer CVD1 and the edge of the second inorganic encapsulation layer CVD2, the interlayer INC covers the organic encapsulation layer IJP as much as possible, further reducing the influence of outgas of the organic encapsulation layer IJP on the light-emitting functional layer EFL of the pixel layer PXL.

[0066] In an embodiment of the present disclosure, as Figure 8 shown, the display panel PNL further includes a first dam DAM1 surrounding the display area AA and a second dam DAM2 surrounding the first dam DAM1; the edge of the organic encapsulation layer IJP is located between the display area AA and the first dam DAM1; the edge of the interlayer INC is located between the first dam DAM1 and the second dam DAM2. In this way, the interlayer INC can completely cover the organic encapsulation layer IJP, avoiding the influence of the plasma of the second inorganic encapsulation layer CVD2 on the organic encapsulation layer IJP, and further improving the reliability of the display panel. At the same time, the edge of the interlayer INC does not exceed the second dam DAM2, reserving enough overlapping width for the edge of the first inorganic encapsulation layer CVD1 and the edge of the second inorganic encapsulation layer CVD2, without affecting the water and oxygen barrier ability of the inorganic encapsulation layer.

[0067] In an embodiment of the present disclosure, the edge of the interlayer INC is located within the edge of the first inorganic encapsulation layer CVD1 and within the edge of the second inorganic encapsulation layer CVD2; the edge region of the first inorganic encapsulation layer CVD1 directly overlaps with the edge region of the second inorganic encapsulation layer CVD2.

[0068] In an embodiment of the present disclosure, the material of the interlayer INC can be a transparent inorganic material. When using an organic material, during the process of forming the second inorganic encapsulation layer CVD2, the plasma bombardment on the surface of the organic material interlayer generates gas, and the gas penetrates into the light-emitting functional layer EFL through the gaps in the first inorganic encapsulation layer CVD1 film layer, resulting in mini GDS in local sub-pixels PX, affecting the display effect and reliability of the display panel. By using an inorganic material for the interlayer INC, the sensitivity to plasma bombardment is reduced, and the occurrence of outgas can be significantly reduced.

[0069] In an embodiment of the present disclosure, as Figure 7 and Figure 9 shown, the interlayer INC can be a transparent conductive layer, and at least one side of the transparent conductive layer is provided with a conductive lead CL, and the conductive lead CL is used for conducting a power-on test on the interlayer. That is to say, a transparent and conductive material can be used to prepare and form the interlayer INC, so that the interlayer INC has a conductive function. In this way, by leading out the conductive lead CL on the transparent conductive layer, after the encapsulation is completed, a power-on test can be carried out, and the presence or absence of gaps in the encapsulation can be judged by the change in the resistance value. Compared with the conventional oven detection of the display module, the abnormality of the product can be detected in the display panel process stage, saving the materials of the display module and screening out abnormal products in advance, simplifying the process, and improving the efficiency and product yield.

[0070] In an embodiment of the present disclosure, the interlayer INC can include a lithium fluoride (LiF) interlayer, a silicon nitride (SiNx) interlayer, an indium tin oxide (ITO) interlayer, or a graphene interlayer.

[0071] Exemplarily, lithium fluoride (LiF) is used to form the interlayer INC. The LiF interlayer has a low refractive index and a high transmittance. As an interlayer, it can improve the light efficiency and broaden the adjustment range for optics without affecting the reliability of the display panel. For example, silicon nitride has a good effect of blocking the penetration of water and oxygen, and silicon nitride (SiNx) is often used as the inorganic encapsulation layer. The refractive index of the second inorganic encapsulation layer CVD2 formed by silicon nitride is about 1.83. If the refractive index of the second inorganic encapsulation layer CVD2 is to be reduced, the oxygen content in the second inorganic encapsulation layer CVD2 can be increased. However, while increasing the oxygen content in the second inorganic encapsulation layer CVD2 reduces the refractive index, it also increases the risk of water and oxygen intrusion. In this example, by using the LiF interlayer and taking advantage of the low refractive index and high transmittance characteristics of the LiF interlayer, the optical performance of the thin film encapsulation layer TFE can be improved without affecting the water and oxygen barrier ability of the second inorganic encapsulation layer CVD2, thereby improving the display effect of the display panel.

[0072] Exemplarily, indium tin oxide (ITO) is used to form the interlayer INC. The ITO interlayer has a high light transmittance and a high conductivity. In this way, a conductive lead CL can be led out from at least one side of the ITO interlayer. After the encapsulation is completed, a power-on test is performed. By observing the change in the resistance value, the encapsulation effect can be judged, abnormal products can be screened out in advance, the process efficiency can be improved, and the material cost and time cost can be reduced.

[0073] Exemplarily, graphene is used to form the interlayer. The graphene interlayer has the characteristics of high transmittance, high conductivity, and strong water and oxygen barrier, and can all be used as the interlayer to improve the optical performance of the display panel, reduce mini GDS, and improve the yield and reliability of the display panel.

[0074] Exemplarily, silicon nitride is used to form the interlayer. For example, a SiNx interlayer is formed on the side of the inorganic encapsulation layer IJP away from the substrate SBT by a non-plasma process, which can improve the compactness of the inorganic encapsulation layer IJP.

[0075] In an embodiment of the present disclosure, the interlayer INC can be a film layer formed by an evaporation process or a coating process. In this way, when preparing the interlayer INC, the bombardment effect on the organic encapsulation layer IJP is avoided, and the outgas phenomenon of the organic encapsulation layer IJP is prevented.

[0076] In an embodiment of the present disclosure, at least one foreign particle exists on the surface of the pixel layer PXL, and cracks exist in the first inorganic encapsulation layer CVD1 at the position of the foreign particle. In other words, the display panel PNL of the embodiment of the present disclosure is insensitive to foreign particles. During the preparation process of the pixel layer PXL, even if foreign particles (such as Practicles) appear, and the first inorganic encapsulation layer CVD1 fails to completely wrap the foreign particles and cracks exist at the position of the foreign particle, the encapsulation performance of the display panel PNL of the embodiment of the present disclosure can still meet the performance requirements. This is because an interlayer INC is provided on the surface of the organic encapsulation layer IJP, and the organic encapsulation layer IJP can be protected from bombardment and outgas will not occur. Furthermore, the problem that outgas damages the sub-pixels from the cracks of the first inorganic encapsulation layer CVD1 will not occur, thereby avoiding the problem of mini GDS defects in the sub-pixels of the display area AA. In addition, the thin film encapsulation structure provided by the embodiment of the present disclosure can improve the poor reliability of the display panel caused by foreign particles. By adopting this thin film encapsulation structure, the control standard for foreign particles can be appropriately relaxed, the loss of product yield caused by the number of foreign particles can be reduced, the output rate of the display panel can be increased, and thus the shipping cost can be reduced.

[0077] The embodiment of the present disclosure further provides a display device, including the display panel disclosed in any of the above embodiments. The display device may be an in-vehicle display device, a mobile phone, a tablet, or other electronic devices with a display function, which will not be enumerated one by one here.

[0078] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A display panel comprising a display area and a peripheral area located at at least one side of the display area, characterized in that: The display panel comprises: substrate substrate; A driving layer is provided on one side of the substrate; The pixel layer is arranged on a side of the driving layer away from the base substrate; A thin film encapsulation layer is arranged on a side of the pixel layer away from the base substrate; the thin film encapsulation layer comprises a first inorganic encapsulation layer, an organic encapsulation layer, an intercalation layer, and a second inorganic encapsulation layer which are sequentially stacked on one side of the pixel layer; The stability of the intercalation layer under plasma gas bombardment is greater than the stability of the organic encapsulation layer under plasma gas bombardment.

2. The display panel according to claim 1, characterized in that: The orthographic projection of the display area on the base substrate is located within the orthographic projection of the intercalation layer on the base substrate.

3. The display panel according to claim 1, characterized in that: The display panel further includes a first retaining wall surrounding the display area and a second retaining wall surrounding the first retaining wall; The edge of the organic encapsulation layer is located between the display area and the first barrier wall; The edge of the intercalation layer is located between the first retaining wall and the second retaining wall.

4. The display panel according to claim 3, characterized in that: The edge of the intercalation layer is located within the edge of the first inorganic encapsulation layer and within the edge of the second inorganic encapsulation layer; the edge region of the first inorganic encapsulation layer and the edge region of the second inorganic encapsulation layer directly overlap each other.

5. The display panel according to any one of claims 1 to 4, characterized in that: The material of the intercalation layer is a transparent inorganic material.

6. The display panel according to claim 5, characterized in that: The intercalation layer is a transparent conductive layer, and at least one side of the transparent conductive layer is provided with a conductive lead, and the conductive lead is used to perform a power-on test on the intercalation layer.

7. The display panel according to claim 5, characterized in that: The intercalation layer is a film layer formed by an evaporation process or a coating process.

8. The display panel according to claim 5, characterized in that: The intercalation layer includes a lithium fluoride intercalation layer, a silicon nitride intercalation layer, an indium tin oxide intercalation layer or a graphene intercalation layer.

9. The display panel according to claim 1, characterized in that: The surface of the pixel layer has at least one foreign particle, and the first inorganic encapsulation layer has a crack at the foreign particle.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 9.

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