Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device. The array substrate comprises a plurality of pixel driving circuits. Each pixel driving circuit comprises a first transistor and a driving transistor. The array substrate comprises: a substrate; the semiconductor layer is located on one side of the substrate, and the semiconductor layer comprises a first active layer pattern of the first transistor and a second active layer pattern of the driving transistor; the first active layer pattern and the second active layer pattern are in image mirror symmetry; the first metal layer is located on the side, away from the substrate, of the semiconductor layer, the first metal layer comprises a first gate layer pattern, and at least part of the first gate layer pattern is overlapped with the first active layer pattern and the second active layer pattern. According to the invention, the first transistor T1 and the driving transistor T2 share the first gate layer pattern as the gate, so that the process of preparing the pixel driving circuit is simplified.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to an array substrate, a display panel, and a display device. Background Art

[0002] Organic Light Emitting Display (OLED) has many advantages such as all-solid state, self-luminescence, wide viewing angle, wide color gamut, fast response speed, high luminous efficiency, high brightness, high contrast ratio, ultra-thin, ultra-light, low power consumption, wide operating temperature range, ability to fabricate large-size and flexible panels, and simple manufacturing process, and can achieve true flexible display, and has been increasingly concerned and valued in the market in recent years.

[0003] The organic light emitting display device lights up the light-emitting pixels through a pixel driving circuit to realize the corresponding picture display. Figure 1 An equivalent schematic diagram of a pixel driving circuit is shown. In the prior art, according to Figure 1 The pixel driving circuit arranged on the display panel has a complex layout structure and high process difficulty. Summary of the Invention

[0004] Aiming at the problems in the prior art, the purpose of the present invention is to provide an array substrate, a display panel, and a display device.

[0005] An embodiment of the present invention provides an array substrate, including a plurality of pixel driving circuits, and the pixel driving circuit includes a first transistor and a driving transistor; the array substrate includes:

[0006] A substrate;

[0007] A semiconductor layer, located on one side of the substrate, and the semiconductor layer includes a first active layer pattern of the first transistor and a second active layer pattern of the driving transistor; the first active layer pattern and the second active layer pattern are mirror-symmetrical;

[0008] A first metal layer, located on the side of the semiconductor layer away from the substrate, and the first metal layer includes a first gate layer pattern, and at least a part of the first gate layer pattern overlaps with the first active layer pattern and the second active layer pattern.

[0009] In some embodiments, the overlapping part of the first gate layer pattern and the first active layer pattern is the first channel of the first transistor, and the overlapping part of the first gate layer pattern and the second active layer pattern is the second channel of the driving transistor, and the first channel and the second channel are bent.

[0010] In some embodiments, the first transistor and the driving transistor share a part of the channel.

[0011] In some embodiments, the pixel driving circuit further includes an initialization transistor, a data writing transistor, and a compensation transistor;

[0012] The semiconductor layer further includes a third active layer pattern of the initialization transistor, a fourth active layer pattern of the data writing transistor, and a fifth active layer pattern of the compensation transistor;

[0013] The first metal layer further includes a third gate layer pattern of the initialization transistor, a fourth gate layer pattern of the data writing transistor, and a fifth gate layer pattern of the compensation transistor;

[0014] Wherein, the third gate layer pattern overlaps with the third active layer pattern, the fourth gate layer pattern overlaps with the fourth active layer pattern; the fifth gate layer pattern overlaps with the fifth active layer pattern.

[0015] In some embodiments, the pixel driving circuit further includes a reset transistor, a first light-emitting control transistor, and a second light-emitting control transistor;

[0016] The semiconductor layer further includes a sixth active layer pattern of the reset transistor, a seventh active layer pattern of the first light-emitting control transistor, and an eighth active layer pattern of the second light-emitting control transistor;

[0017] The first metal layer further includes a sixth gate layer pattern of the reset transistor, a seventh gate layer pattern of the first light-emitting control transistor, and an eighth gate layer pattern of the second light-emitting control transistor;

[0018] Wherein, the sixth active layer pattern overlaps with the sixth gate layer pattern, the seventh active layer pattern overlaps with the seventh gate layer pattern, and the eighth active layer pattern overlaps with the eighth gate layer pattern.

[0019] In some embodiments, the pixel driving circuit further includes a storage capacitor;

[0020] The array substrate further includes a second metal layer on a side of the first metal layer away from the substrate; the second metal layer includes a second electrode plate pattern of the storage capacitor, an initialization voltage signal line, and a reset voltage signal line;

[0021] The second electrode plate pattern overlaps with the first gate layer pattern, and an overlapping portion of the first gate layer pattern and a vertical projection of the second electrode plate pattern on the substrate forms the storage capacitor;

[0022] The semiconductor layer further includes a ninth active layer pattern and a tenth active layer pattern arranged along the first direction, and the initialization voltage signal line overlaps with the ninth active layer pattern;

[0023] The reset voltage signal line overlaps with the tenth active layer pattern.

[0024] In some embodiments, it further includes a third metal layer arranged along the first direction, located on the side of the second metal layer away from the substrate; the third metal layer includes a first scan signal line, a second scan signal line, and a third scan signal line;

[0025] The first scan signal line overlaps with the third gate layer pattern of the initialization transistor;

[0026] The second scan signal line overlaps with the fourth gate layer pattern of the write transistor and the fifth gate layer pattern of the compensation transistor;

[0027] The third scan signal line overlaps with the sixth gate layer pattern of the reset transistor.

[0028] In some embodiments, the third metal layer further includes a first positive power supply voltage signal line, and the first electrode plate of the storage capacitor overlaps with the first positive power supply voltage signal line.

[0029] In some embodiments, it further includes a fourth metal layer arranged along the second direction, located on the side of the third metal layer away from the substrate.

[0030] In some embodiments, the fourth metal layer includes a data line and a second positive power supply voltage signal line; the data line overlaps with the fourth active layer pattern of the data write transistor; the second positive power supply voltage signal line overlaps with the first positive power supply voltage signal line.

[0031] An embodiment of the present invention further provides a display panel, including the array substrate as described above.

[0032] An embodiment of the present invention further provides a display device, including the array substrate as described above.

[0033] The array substrate, display panel, and display device provided by the present invention have the following advantages:

[0034] The array substrate includes a plurality of pixel driving circuits, and each pixel driving circuit includes a first transistor and a driving transistor. The array substrate includes: a substrate; a semiconductor layer located on one side of the substrate, and the semiconductor layer includes a first active layer pattern of the first transistor and a second active layer pattern of the driving transistor; the first active layer pattern and the second active layer pattern are mirror-symmetrical; a first metal layer located on the side of the semiconductor layer away from the substrate, and the first metal layer includes a first gate layer pattern, and at least part of the first gate layer pattern overlaps with the first active layer pattern and the second active layer pattern. In the present invention, the first transistor and the driving transistor share the first gate layer pattern as the gate, which simplifies the process of manufacturing the pixel driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Other features, objects, and advantages of the present invention will become more apparent by reading the detailed description of the non-limiting embodiments with reference to the following drawings.

[0036] Figure 1 is an equivalent schematic diagram of a pixel driving circuit;

[0037] Figure 2 is a layout schematic diagram of the array substrate provided with the semiconductor layer and the first metal layer according to an embodiment of the present invention;

[0038] Figure 3 is a layout schematic diagram of the first transistor and the driving transistor of the array substrate provided by another embodiment of the present invention;

[0039] Figure 4 is a layout schematic diagram of the first transistor and the driving transistor of the array substrate provided by another embodiment of the present invention;

[0040] Figure 5 is a layout schematic diagram of the first transistor and the driving transistor of the array substrate provided by another embodiment of the present invention;

[0041] Figure 6 is a layout schematic diagram of the first transistor and the driving transistor of the array substrate provided by another embodiment of the present invention;

[0042] Figure 7 is a layout schematic diagram of the first transistor and the driving transistor of the array substrate provided by another embodiment of the present invention;

[0043] Figure 8 is a layout schematic diagram of the first transistor and the driving transistor of the array substrate provided by another embodiment of the present invention;

[0044] Figure 9 is a layout schematic diagram of the array substrate provided with the semiconductor layer and the first metal layer according to another embodiment of the present invention;

[0045] Figure 10 It is a schematic layout diagram of the array substrate provided by another embodiment of the present invention, showing the semiconductor layer and the first metal layer;

[0046] Figure 11 It is a schematic layout diagram of the array substrate provided by another embodiment of the present invention, showing the semiconductor layer and the first metal layer;

[0047] Figure 12 It is a schematic layout diagram of the array substrate provided by an embodiment of the present invention after setting the second metal layer;

[0048] Figure 13 It is a schematic layout diagram of the array substrate provided by another embodiment of the present invention after setting the second metal layer;

[0049] Figure 14 It is a schematic layout diagram of the array substrate provided by an embodiment of the present invention after setting the third metal layer;

[0050] Figure 15 It is a schematic layout diagram of the array substrate provided by an embodiment of the present invention after setting the third metal layer;

[0051] Figure 16 It is a schematic layout diagram of the array substrate provided by an embodiment of the present invention after setting the fourth metal layer;

[0052] Figure 17 It is Figure 16 the cross-sectional view taken along the cutting line AA' in;

[0053] Figure 18 It is Figure 16 the cross-sectional view taken along the cutting line BB' in;

[0054] Figure 19 It is Figure 16 the cross-sectional view taken along the cutting line CC' in. Detailed Embodiments

[0055] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Identical reference numerals in the figures denote identical or similar structures, and thus their repeated description will be omitted. "Or" or "either...or" in the specification may mean "and" or "or".

[0056] The following specific examples illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in the present application. The present application can also be implemented or applied through other different specific implementation manners. Various details in the present application can also be modified or changed according to different viewpoints and application systems without departing from the spirit of the present application. It should be noted that, without conflict, the embodiments and features in the embodiments of the present application can be combined with each other.

[0057] To solve the problems in the prior art, an embodiment of the present invention provides an array substrate. Figure 1 The equivalent schematic diagram of the pixel driving circuit in the array substrate provided by the embodiment of the present invention is shown. As Figure 1 shown, the pixel driving circuit includes a first transistor T1, a driving transistor T2, an initialization transistor T3, a data writing transistor T4, a compensation transistor T5, a reset transistor T6, a first light-emitting control transistor T7, and a second light-emitting control transistor T8.

[0058] The first transistor T1 and the driving transistor T2 respond to the potential of the first node n1 to achieve conduction and cutoff; the control ends of the first transistor T1 and the driving transistor T2 are electrically connected to the first node n1.

[0059] The initialization transistor T3 responds to the first scan signal to transmit the initialization voltage to the first node n1. The first end of the initialization transistor T3 is electrically connected to the initialization voltage signal line Vint, the second end of the initialization transistor T3 is electrically connected to the first node n1, and the control end of the initialization transistor T3 is electrically connected to the first scan signal line Sn-1.

[0060] The data writing transistor T4 and the compensation transistor T5 respond to the second scan signal to transmit the data voltage and the threshold voltage Vth of the first transistor T1 to the first node n1 and store them in the storage capacitor Cs. The control end of the data writing transistor T4 is electrically connected to the second scan signal line Sn, the first end of the data writing transistor T4 is electrically connected to the data line Data, and the second end of the data writing transistor T4 is electrically connected to the first end of the first transistor T1. The control end of the compensation transistor T5 is electrically connected to the second scan signal line Sn, the first end of the compensation transistor T5 is electrically connected to the second end of the first transistor T1, and the second end of the compensation transistor T5 is electrically connected to the first node n1. Since the sizes of the first transistor T1 and the driving transistor T2 are exactly the same, the threshold voltage of the driving transistor T2 is the same as the threshold voltage of the first transistor T1. The first plate of the storage capacitor Cs is electrically connected to the first node n1, and the second plate of the storage capacitor Cs is electrically connected to the first power supply voltage signal line ELVDD.

[0061] The reset transistor T6 responds to the third scan signal to write a reference voltage to the first end of the light-emitting element OLED, so as to reset the potential of the first end of the light-emitting element OLED. The control end of the reset transistor T6 is electrically connected to the third scan signal line Sn+1, the first end of the reset transistor T6 is electrically connected to the reset voltage signal line Vres, and the second end of the reset transistor T6 is electrically connected to the anode of the light-emitting element OLED. Here, the anode of the light-emitting element OLED is the anode of the light-emitting element.

[0062] The first light-emitting control transistor T7 and the second light-emitting control transistor T8 respond to the light-emitting control signal to drive the light-emitting element OLED to emit light. The control end of the first light-emitting control transistor T7 is electrically connected to the light-emitting control signal line En, the first end of the first light-emitting control transistor T7 is electrically connected to the first power supply voltage signal line ELVDD, and the second end of the first light-emitting control transistor T7 is electrically connected to the first end of the driving transistor T2. The control end of the second light-emitting control transistor T8 is electrically connected to the light-emitting control signal line En, the first end of the second light-emitting control transistor T8 is electrically connected to the second end of the driving transistor T2, and the second end of the second light-emitting control transistor T8 is electrically connected to the anode of the light-emitting element OLED.

[0063] It should be noted that in the circuit provided by the embodiment of the present application, the nodes do not represent actual existing components, but represent the convergence points of relevant electrical connections in the circuit diagram. That is to say, these nodes are nodes equivalent to the convergence points of relevant associated electrical connections in the circuit diagram. The control end of the transistor refers to the gate of the transistor, the first end of the transistor refers to one of the source or drain of the transistor, and the second end of the transistor refers to the other of the source or drain. The transistor includes a P-type transistor and an N-type transistor. In this embodiment, the P-type transistor is taken as an example for illustration.

[0064] The array substrate provided by the embodiment of the present invention includes a plurality of pixel driving circuits. However, here only the layout of one pixel driving circuit is taken as an example to introduce the present invention in detail. The layouts of the remaining pixel driving circuits can be any one of those introduced in the following embodiments.

[0065] Figures 2 to 19 shows Figure 1 the layout design of each layer of the pixel driving circuit in Figures 2 to 19It can be obtained that the array substrate provided by the embodiment of the present invention includes a substrate 10, and a pixel driving circuit is located on one side of the substrate 10; the pixel driving circuit includes a first transistor T1 and a driving transistor T2, and the array substrate includes: a substrate 10, a semiconductor layer 30, and a first metal layer 40. Among them, the semiconductor layer 30 is located on one side of the substrate 10, and the semiconductor layer 30 includes a first active layer pattern 31 of the first transistor T1 and a second active layer pattern 32 of the driving transistor T2; the first active layer pattern 31 and the second active layer pattern 32 are mirror-symmetrical; the first metal layer 40 is located on the side of the semiconductor layer 30 away from the substrate 10, and the first metal layer 40 includes a first gate layer pattern 41, and at least a part of the first gate layer pattern 41 overlaps with the first active layer pattern 31 and the second active layer pattern 32. The overlapping part of the first gate layer pattern 41 and the first active layer pattern 31 is the first channel of the first transistor T1, and the overlapping part of the first gate layer pattern 41 and the second active layer pattern 32 is the second channel of the driving transistor T2. The first transistor T1 and the driving transistor T2 have the same aspect ratio in structure, so they have the same threshold voltage electrically. The first transistor T1 and the driving transistor T2 share the first gate layer pattern 41 as the gate, which can simplify the manufacturing process of the array substrate and improve the reliability of the pixel driving circuit.

[0066] It should be noted that here the first metal layer 40 is the gate for forming the transistors in the pixel driving circuit, and the semiconductor layers on both sides of the channel are the source or drain for forming the transistors in the pixel driving circuit.

[0067] The material of the semiconductor layer 30 can be low-temperature polycrystalline silicon, but is not limited thereto. As Figures 17 to 19 shown, a buffer layer 20 is further provided between the substrate 10 and the semiconductor layer 30 to enable good contact between the substrate 10 and the semiconductor layer 30.

[0068] Combined with Figure 1 It can be obtained that Figure 2 The white line part shown is the light-emitting path and the charging path. The path from the data writing transistor T4, the first transistor T1, the compensation transistor T5 to the first node n1 is the charging path; the path from the first light-emitting control transistor T7, the driving transistor T2 to the second light-emitting control transistor T8 is the light-emitting path. Since the first transistor T1 and the driving transistor T2 have exactly the same length and width dimensions, the threshold voltage of the first transistor T1 is the same as the threshold voltage of the driving transistor T2. Therefore, compensating for the threshold voltage of the first transistor T1 in the charging path is equivalent to compensating for the threshold voltage of the driving transistor T2, realizing writing the threshold voltage of the driving transistor T2 to the first node n1 during the charging stage to improve the display unevenness problem caused by different threshold voltages of the driving transistor T2.

[0069] As Figures 3 to 8As shown, in some embodiments, the first channel of the first transistor T1 and the second channel of the driving transistor T2 may be set to be bent. Since the emission brightness of the light-emitting element in the pixel is related to the driving current generated by the driving transistor T2, and the driving current is controlled by the data signal transmitted through the data line, increasing the channel length of the driving transistor T2 can increase the data voltage range of the data signal and improve the control ability of the driving transistor T2 over the light emission of the light-emitting element, thereby improving the display effect of the display panel.

[0070] Please continue to refer to Figures 3 to 5 , compared with Figure 3 , Figure 4 and Figure 5 the area of the first gate layer pattern 41 in Figure 4 and Figure 5 increases, that is, the area overlapping with the first active layer pattern 31 and the second active layer pattern 32 increases. Specifically, see the dotted frames shown in Figure 4 and Figure 5 . The increase in the area of the first gate layer pattern 41 overlapping with the first active layer pattern 31 and the second active layer pattern 32 can further increase the channel lengths of the first transistor T1 and the driving transistor T2, improve the control ability of the driving transistor T2 over the light emission of the light-emitting element, and thereby improve the display effect of the display panel.

[0071] As Figures 6 to 8 shown, the first transistor T1 and the driving transistor T2 can be designed to share a part of the channel to increase the channel length of the transistor. Compared with the channel design in Figures 3 to 5 , in the same layout space, the two transistors sharing a part of the channel can increase their respective channel lengths. Here, the design of the channels of the first transistor T1 and the driving transistor T2 is only for illustrative purposes and is not specifically limited. Compared with Figure 6 , Figure 7 and Figure 8 the area of the first gate layer pattern 41 in Figure 7 and Figure 8 overlapping with the first active layer pattern 31 and the second active layer pattern 32 increases (the increased part is shown in the dotted frames shown in Figure 7 and Figure 8 ), and the channel lengths of the first transistor T1 and the driving transistor T2 can be further increased.

[0072] Please continue to refer to Figure 2 , the pixel driving circuit further includes an initialization transistor T3, a data writing transistor T4, and a compensation transistor T5; the semiconductor layer 30 further includes a third active layer pattern of the initialization transistor T3, a fourth active layer pattern of the data writing transistor T4, and a fifth active layer pattern of the compensation transistor T5;

[0073] The first metal layer 40 further includes a third gate layer pattern 43 for initializing the transistor T3, a fourth gate layer pattern 44 for the data writing transistor T4, and a fifth gate layer pattern 45 for the compensation transistor T5. The third gate layer pattern 43 overlaps with the vertical projection of the third active layer pattern on the substrate 10, and the overlapping portion on the third active layer pattern is the channel of the initialization transistor T3. The fourth gate layer pattern 44 overlaps with the vertical projection of the fourth active layer pattern on the substrate 10, and the overlapping portion on the fourth active layer pattern is the channel of the data writing transistor T4. The fifth active layer pattern overlaps with the fifth gate layer pattern 45 in the vertical projection on the substrate 10, and the overlapping portion on the fifth active layer is the channel of the compensation transistor T5.

[0074] The third gate layer pattern 43 of the initialization transistor T3 has two non-connected overlapping portions with the third active layer pattern. The design of the third gate layer pattern 43 of the initialization transistor T3 and the third active layer pattern is equivalent to designing the initialization transistor T3 as a double-gate transistor, that is, the initialization transistor T3 includes a first sub-transistor T3a and a second sub-transistor T3b.

[0075] The fifth gate layer pattern 45 of the compensation transistor T5 has two non-connected overlapping portions with the fifth active layer pattern. The design of the fifth gate layer pattern 45 of the compensation transistor T5 and the fifth active layer pattern is equivalent to designing the compensation transistor T5 as a double-gate transistor, that is, the compensation transistor T5 includes a third sub-transistor T5a and a fourth sub-transistor T5b.

[0076] Furthermore, the pixel driving circuit further includes a reset transistor T6, a first light-emitting control transistor T7, and a second light-emitting control transistor T8. The semiconductor layer 30 further includes a sixth active layer pattern of the reset transistor T6, a seventh active layer pattern of the first light-emitting control transistor T7, and an eighth active layer pattern of the second light-emitting control transistor T8.

[0077] The first metal layer 40 further includes a sixth gate layer pattern 46 of the reset transistor T6, a seventh gate layer pattern 47 of the first light-emitting control transistor T7, and an eighth gate layer pattern 48 of the second light-emitting control transistor T8.

[0078] Among them, the sixth active layer pattern overlaps with the sixth gate layer pattern 46 in the vertical projection on the substrate 10, and the overlapping portion on the sixth active layer pattern is the channel of the reset transistor T6. The seventh active layer pattern overlaps with the seventh gate layer pattern 47 in the vertical projection on the substrate 10, and the overlapping portion on the seventh active layer is the channel of the first light-emitting control transistor T7. The eighth active layer pattern overlaps with the eighth gate layer pattern 48 in the vertical projection on the substrate 10, and the overlapping portion on the eighth active layer pattern is the channel of the second light-emitting control transistor T8.

[0079] In this embodiment, the seventh gate layer pattern 47 is connected to the eighth gate layer pattern 48, which is equivalent to the emission control signal line En and can transmit the emission control signal.

[0080] As Figures 9 to 11 shown, the first end or the second end of the third active layer pattern of the initialization transistor T3 can be designed to be stepped to extend the length of the third active layer pattern, so as to increase the resistance of the source or drain of the initialization transistor T3 and reduce the influence of the leakage of the initialization transistor T3 on the potential of the n1 node.

[0081] As Figure 12 and Figure 13 shown, the array substrate further includes a second metal layer 50, which is located on the side of the first metal layer 40 away from the substrate 10; the second metal layer 50 includes the second plate pattern of the storage capacitor Cs, the initialization voltage signal line Vint and the reset voltage signal line Vres;

[0082] The first plate pattern overlaps with the first gate layer pattern 41, and the overlapping portion of the first gate layer pattern 41 and the vertical projection of the second plate pattern on the substrate 10 forms the storage capacitor Cs; that is, the first gate layer pattern 41 is equivalent to the first plate of the storage capacitor Cs, and the second plate pattern is equivalent to the second plate of the storage capacitor Cs.

[0083] As Figure 2 , Figures 9 to 11 it can be obtained that the semiconductor layer 30 further includes a ninth active layer pattern 39 and a tenth active layer pattern 310 arranged along the first direction; as Figure 12 and Figure 13 it can be obtained that the initialization voltage signal line Vint overlaps with the ninth active layer pattern 39, and the initialization signal line Vint is electrically connected to the ninth active layer pattern 39 through a contact hole. The reset voltage signal line Vres overlaps with the tenth active layer pattern 310, and the reset voltage signal line Vres is electrically connected to the tenth active layer pattern 310 through a contact hole. The transverse semiconductor layer 30 and the transverse second metal layer 50 are used to transmit the initialization voltage signal and the reset voltage signal. The resistance of the second metal layer 50 is relatively low compared with that of the semiconductor layer 30, which can better transmit the signal, while the resistance of the semiconductor layer 30 is relatively large, which can relatively eliminate the static charges generated in the process.

[0084] It should be noted that in the schematic plan layout diagram of the pixel driving circuit in the specification drawings of the present application, only the functional layers included in the array substrate are shown. The functional layers include a semiconductor layer and multiple metal layers, etc. In practice, adjacent two functional layers need to be separated by an insulating layer. Therefore, an insulating film is provided between adjacent functional layers in practice. As Figures 17 to 19As shown, a first insulating layer 71 is provided between the semiconductor layer 30 and the first metal layer 40, and a second insulating layer 72 is provided between the second metal layer 50 and the first metal layer 40. By etching contact holes on the first insulating layer 71, the initialization signal line Vint is electrically connected to the ninth active layer pattern 39, and the reset voltage signal line Vres is electrically connected to the tenth active layer pattern 310.

[0085] Please continue reading Figure 12 and Figure 13 The area of ​​the second electrode pattern is not limited to overlapping with the first gate layer pattern 41. Figure 12 In the square dotted frame in FIG. 1 , the second electrode pattern also covers part of the fifth active layer pattern of the compensation transistor T5. On the one hand, the size of the storage capacitor Cs can be increased to improve the voltage stabilization effect of this part of the compensation transistor T5; on the other hand, other pulse signal routings or the power of nodes in the circuit can be attracted more to the second metal layer 50 to shield the first end of the compensation transistor T5 and reduce the disturbance of other signals; it can also play a light shielding effect to try to avoid light from being incident on the semiconductor layer, causing photogenerated carriers, thereby causing the potential change of the compensation transistor T5.

[0086] See also Figure 12 and Figure 13 As shown in the oval dotted frame in FIG. 1 , the portion of the second metal layer 50 needs to be narrowed to reduce the overlapping area with the upper film layer, thereby reducing the parasitic capacitance of the horizontal scanning signal.

[0087] like Figure 14 , Figure 15 , Figures 17 to 19 As shown, the pixel driving circuit further includes a third metal layer 60 arranged along the first direction (lateral direction), and the third metal layer 60 is located on the side of the second metal layer 50 away from the substrate 10, and a third insulating layer 73 is provided between the second metal layer 50 and the third metal layer 60. The third metal layer 60 includes a first scanning signal line Sn-1, a second scanning signal line Sn, a third scanning signal line Sn+1, a source-drain electrode 60 (T4) of a data writing transistor T4, a source-drain electrode 60 (T5) of a compensation transistor T5, a source-drain electrode 60 (T7) of a first light emission control transistor T7, a first positive power supply voltage signal line 60 (ELVDD), and a source-drain electrode 60 (T8) of a second light emission control transistor T8.

[0088] Among them, the first scan signal line Sn-1 overlaps with the third gate layer pattern 43 of the initialization transistor T3, and the first scan signal line Sn-1 is electrically connected to the third gate layer pattern 43 through a contact hole. The second scan signal line Sn overlaps with the fourth gate layer pattern 44 of the writing transistor T4 and the fifth gate layer pattern 45 of the compensation transistor T5, and the second scan signal line Sn is electrically connected to the fourth gate layer pattern 44 and the fifth gate layer pattern 45 through contact holes. The third scan signal line Sn+1 overlaps with the sixth gate layer pattern 46 of the reset transistor T6, and the third scan signal line Sn+1 is electrically connected to the sixth gate layer pattern 46 through a contact hole. The contact holes provided between the scan signal lines and the first metal layer 40 need to penetrate all the film layers between the scan signal lines and the first metal layer 40.

[0089] The source-drain electrodes 60(T4) of the data writing transistor T4 overlap with the fourth active layer pattern of the data writing transistor T4, and the source-drain electrodes 60(T4) of the data writing transistor T4 are electrically connected to one end of the fourth active layer pattern of the data writing transistor T4 through a contact hole. The source-drain electrodes 60(T5) of the compensation transistor T5 overlap with the fifth active layer pattern of the compensation transistor T5, and the source-drain electrodes 60(T5) of the compensation transistor T5 are electrically connected to the first gate layer pattern 41 through a contact hole. The source-drain electrodes 60(T7) of the first light-emitting control transistor T7 overlap with the seventh active layer pattern, and the source-drain electrodes 60(T7) of the first light-emitting control transistor T7 are electrically connected to one end of the seventh active layer pattern through a contact hole. The source-drain electrodes 60(T7) of the second light-emitting control transistor T8 overlap with the eighth active layer pattern, and the source-drain electrodes 60(T7) of the second light-emitting control transistor T8 are electrically connected to one end of the eighth active layer pattern through a contact hole. Contact holes are provided between the source-drain electrodes of each transistor and each active layer pattern, and all the film layers between the source-drain electrodes of each transistor and each active layer pattern need to be penetrated.

[0090] As Figure 12 shown, a through hole 51 is further provided on the second electrode pattern 50(Cs), and this through hole 51 is used to expose the first gate layer pattern 41 and is electrically connected to the source-drain electrodes 60(T5) of the compensation transistor T5.

[0091] As Figures 16 to 19 shown, the pixel driving circuit further includes a fourth metal layer 80, a fourth insulating layer 74, and a fifth insulating layer 75 arranged in the second direction. The fourth metal layer 80 is provided on the side of the third metal layer 60 away from the substrate 10, and the fifth insulating layer 75 is provided on the side of the fourth metal layer 80 away from the substrate 10. Here, the second direction is the up-down direction as seen on the paper surface, that is, the longitudinal direction. The fourth metal layer 80 includes a data line Data, a second positive power supply voltage signal line 80(ELVDD), and an anode signal transmission layer.

[0092] Transmitting the first power supply voltage signal in both the horizontal and vertical directions can improve the uniformity of the panel during the initialization process; the vertical signal lines can increase the area covering the semiconductor layer 30, reduce the influence of light incidence on the carrier concentration of the semiconductor layer in its area, and reduce the drain potential fluctuation caused by the photo-generated carrier effect.

[0093] As Figure 16 , Figure 18 and Figure 19 shown, a first type of contact hole is provided on the fourth insulating layer 74 to electrically connect the source-drain electrodes 60(T4) of the data writing transistor T4 of the data line Data. A second type of contact hole is provided on the fourth insulating layer to electrically connect the anode signal transmission layer to the source-drain electrodes 60(T8) of the second light-emitting control transistor T8. In subsequent steps, an anode layer is provided on the fifth insulating layer 75, and the anode layer is electrically connected to the anode signal transmission layer, so that the anode layer can be electrically connected to the second ends of the second light-emitting control transistor T8 and the reset transistor T6, thereby realizing the electrical connection between the pixel driving circuit and the light-emitting layer, and thus the signal can be transmitted to the anode of the light-emitting element OLED by using the pixel driving circuit to drive the light emission of the light-emitting element OLED.

[0094] The array substrate, display panel, and display device provided by the present invention have the following advantages:

[0095] The array substrate includes a plurality of pixel driving circuits, and the pixel driving circuit includes a first transistor and a driving transistor; the array substrate includes: a substrate; a semiconductor layer located on one side of the substrate, and the semiconductor layer includes a first active layer pattern of the first transistor and a second active layer pattern of the driving transistor; the first active layer pattern and the second active layer pattern are mirror-symmetrical; a first metal layer located on the side of the semiconductor layer away from the substrate, and the first metal layer includes a first gate layer pattern, and at least part of the first gate layer pattern overlaps with the first active layer pattern and the second active layer pattern. In the present invention, the first transistor T1 and the driving transistor T2 share the first gate layer pattern as the gate, which simplifies the process of preparing the pixel driving circuit.

[0096] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. An array substrate, characterized in that, including a plurality of pixel driving circuits, each of which includes a first transistor and a driving transistor; the array substrate includes: a substrate; a semiconductor layer located on one side of the substrate, the semiconductor layer including a first active layer pattern of the first transistor and a second active layer pattern of the driving transistor; the first active layer pattern and the second active layer pattern are mirror-symmetrical; a first metal layer located on the side of the semiconductor layer away from the substrate, the first metal layer including a first gate layer pattern, at least a part of the first gate layer pattern overlapping with the first active layer pattern and the second active layer pattern.

2. The array substrate according to claim 1, wherein The overlapping part of the first gate layer pattern and the first active layer pattern is the first channel of the first transistor, and the overlapping part of the first gate layer pattern and the second active layer pattern is the second channel of the driving transistor. The first channel and the second channel are bent.

3. The array substrate according to claim 2, wherein The first transistor and the driving transistor share a part of the channel.

4. The array substrate according to claim 3, wherein, The pixel driving circuit further includes an initialization transistor, a data writing transistor, and a compensation transistor; The semiconductor layer further includes a third active layer pattern of the initialization transistor, a fourth active layer pattern of the data writing transistor, and a fifth active layer pattern of the compensation transistor; The first metal layer further includes a third gate layer pattern of the initialization transistor, a fourth gate layer pattern of the data writing transistor, and a fifth gate layer pattern of the compensation transistor; wherein, the third gate layer pattern overlaps with the third active layer pattern, the fourth gate layer pattern overlaps with the fourth active layer pattern; the fifth gate layer pattern overlaps with the fifth active layer pattern.

5. The array substrate according to claim 4, characterized in that, The pixel driving circuit further includes a reset transistor, a first light-emitting control transistor, and a second light-emitting control transistor; The semiconductor layer further includes a sixth active layer pattern of the reset transistor, a seventh active layer pattern of the first light-emitting control transistor, and an eighth active layer pattern of the second light-emitting control transistor; The first metal layer further includes a sixth gate layer pattern of the reset transistor, a seventh gate layer pattern of the first light-emitting control transistor, and an eighth gate layer pattern of the second light-emitting control transistor; wherein, the sixth active layer pattern overlaps with the sixth gate layer pattern, the seventh active layer pattern overlaps with the seventh gate layer pattern, and the eighth active layer pattern overlaps with the eighth gate layer pattern.

6. The array substrate according to claim 5, wherein The pixel driving circuit further includes a storage capacitor; The array substrate further includes a second metal layer located on the side of the first metal layer away from the substrate; the second metal layer includes a second plate pattern of the storage capacitor, an initialization voltage signal line, and a reset voltage signal line; The second plate pattern overlaps with the first gate layer pattern, and the overlapping part of the first gate layer pattern and the vertical projection of the second plate pattern on the substrate forms the storage capacitor; The semiconductor layer further includes a ninth active layer pattern and a tenth active layer pattern arranged along a first direction, and the initialization voltage signal line overlaps with the ninth active layer pattern; The reset voltage signal line overlaps with the tenth active layer pattern.

7. The array substrate according to claim 6, wherein It further includes a third metal layer disposed along the first direction, on a side of the second metal layer away from the substrate; the third metal layer includes a first scan signal line, a second scan signal line, and a third scan signal line; The first scan signal line overlaps with the third gate layer pattern of the initialization transistor; The second scan signal line overlaps with the fourth gate layer pattern of the writing transistor and the fifth gate layer pattern of the compensation transistor; The third scan signal line overlaps with the sixth gate layer pattern of the reset transistor.

8. The array substrate according to claim 7, wherein The third metal layer further includes a first positive power supply voltage signal line, and the first electrode plate of the storage capacitor overlaps with the first positive power supply voltage signal line.

9. The array substrate according to claim 8, wherein It further includes a fourth metal layer disposed along the second direction, on a side of the third metal layer away from the substrate.

10. The array substrate according to claim 9, wherein, The fourth metal layer includes a data line and a second positive power supply voltage signal line; the data line overlaps with the fourth active layer pattern of the data writing transistor; the second positive power supply voltage signal line overlaps with the first positive power supply voltage signal line.

11. A display panel, characterized in that, It includes the array substrate according to any one of claims 1 to 10.

12. A display device, characterized in that, It includes the array substrate according to any one of claims 1 to 10.

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