Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes a substrate including a light-emitting area and a non-light-emitting area, a first positive electrode positioned on the light-emitting area of the substrate, an auxiliary electrode positioned on the non-light-emitting area of the substrate and spaced apart from the first positive electrode, a pixel defining layer positioned on the auxiliary electrode, a first negative electrode positioned on the non-light-emitting area of the substrate and spaced apart from the auxiliary electrode, a first light-emitting layer positioned on the auxiliary electrode, and a second light-emitting layer positioned on the non-light-emitting area of the substrate. The pixel defining layer is positioned on the first positive electrode and the auxiliary electrode and defines a first opening, the first light emitting layer is positioned on the first positive electrode and completely covers the pixel defining layer, the first negative electrode is positioned on the first light emitting layer, the bank structure is positioned on the auxiliary electrode and defines a second opening, and the first negative electrode is positioned on the second light emitting layer. The bank structure includes a first bank layer, a second bank layer, and a third bank layer sequentially stacked, and the first encapsulation layer is positioned on the bank structure.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of, and all benefits derived from, Korean Patent Application No. 10 - 2023 - 0186925, filed on December 20, 2023, the content of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a display device and a method of manufacturing the display device. Background art

[0004] With the development of the information society, the demand for various types of display devices for displaying images is increasing. For example, display devices have been applied to various electronic devices, such as, by way of example, smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat - panel display device, such as, by way of example, a liquid - crystal display device, a field - emission display device, or an organic - light - emitting display device. Among flat - panel display devices, a self - emissive display device may include a light - emitting element in each pixel of a display panel that can emit light by itself, thereby displaying an image without a backlight unit that provides light to the display panel.

[0005] With the development of various electronic devices, the demand for high - resolution display devices is increasing. Since a high - resolution display device requires high pixel integration, the pitch between light - emitting elements overlapping each light - emitting region can be narrowed. Therefore, in some cases, a high - resolution display device may be formed by a patterning process for forming each pixel rather than a mask process. Summary of the invention

[0006] Aspects of the present disclosure provide a display device including a cathode electrode disposed to overlap each light - emitting region and spaced apart from each other, and a bank structure disposed to overlap a non - light - emitting region. Aspects of the present disclosure also lie in solving defective detachment caused by a decrease in the adhesion between the bank structure and the cathode electrode, and external moisture penetration defects caused by the detachment of the bank structure from the cathode electrode.

[0007] However, aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] Details of other embodiments are included in the detailed description and the drawings.

[0009] In an embodiment of the present disclosure, a display device includes a substrate, a first anode electrode, an auxiliary electrode, a pixel defining layer, a first light-emitting layer, a first cathode electrode, a bank structure, and a first encapsulation layer. The substrate includes a light-emitting region and a non-light-emitting region. The first anode electrode is positioned on the light-emitting region of the substrate. The auxiliary electrode is positioned on the non-light-emitting region of the substrate and is spaced apart from the first anode electrode. The pixel defining layer is positioned on the first anode electrode and the auxiliary electrode and defines a first opening. The first light-emitting layer is positioned on the first anode electrode and completely covers the pixel defining layer. The first cathode electrode is positioned on the first light-emitting layer. The bank structure is positioned on the auxiliary electrode and defines a second opening. The bank structure includes a first bank layer, a second bank layer, and a third bank layer stacked in sequence. The first encapsulation layer is positioned on the bank structure. Wherein, in a region overlapping with the non-light-emitting region, a cavity is formed between a first side surface of the second bank layer facing the light-emitting region and the first bank layer. And in a region overlapping with the cavity, the first cathode electrode contacts the auxiliary electrode, and the first light-emitting layer does not overlap with the cavity.

[0010] In an embodiment, the second bank layer may include a second side surface facing the light-emitting region, and the second side surface protrudes toward the light-emitting region more than the first side surface of the first bank layer.

[0011] In an embodiment, the third bank layer may include a tip protruding toward the light-emitting region more than the second side surface of the second bank layer, and the protruding tip of the third bank layer and the second side surface form an undercut.

[0012] In an embodiment, the width of the cavity in a direction parallel to the substrate may be greater than twice the height of the first bank layer.

[0013] In an embodiment, the height of the second bank layer may be greater than twice the height of the first bank layer.

[0014] In an embodiment, the height of the first bank layer may be in the range of 500 angstroms to 2000 angstroms.

[0015] In an embodiment, the materials included in the first bank layer, the second bank layer, and the third bank layer may be different from each other.

[0016] In an embodiment, the first bank layer may include at least one of silicon nitride and aluminum, and the second bank layer may be silicon oxide.

[0017] In an embodiment, the display device may further include a residual electrode pattern positioned on the second side surface of the second bank layer facing the light-emitting region, wherein the residual electrode pattern includes the same material as the first cathode electrode and is spaced apart from the first cathode electrode.

[0018] In an embodiment, the second side surface may include a first portion in contact with the residual electrode pattern and a second portion in contact with the first encapsulation layer, and the second side surface may be completely covered by the first portion and the second portion.

[0019] In an embodiment, the area of the second portion may be greater than the area of the first portion.

[0020] In an embodiment, the first encapsulation layer may be in contact with the first cathode electrode at a portion overlapping with the cavity.

[0021] In an embodiment, the display device may further include an organic pattern and an electrode pattern. The organic pattern is positioned on the third bank layer, where the organic pattern includes the same material as that of the first light-emitting layer and is spaced apart from the first light-emitting layer. The electrode pattern is positioned on the organic pattern, where the electrode pattern includes the same material as that of the first cathode electrode and is spaced apart from the first cathode electrode, and where the electrode pattern and the residual electrode pattern may include the same material.

[0022] In an embodiment, the first encapsulation layer may be in contact with the organic pattern and the electrode pattern.

[0023] In an embodiment, the pixel defining layer may be completely covered by the first light-emitting layer in a plan view, and the second opening completely surrounds the first opening in the plan view.

[0024] In an embodiment, the display device may further include a second anode electrode, a second light-emitting layer, and a second cathode electrode. The second anode electrode is spaced apart from the first anode electrode, an auxiliary electrode is interposed between the first anode electrode and the second anode electrode, the second light-emitting layer is positioned on the second anode electrode, and the second cathode electrode is positioned on the second light-emitting layer. The auxiliary electrode includes a first side surface facing the bank structure. The first side surface of the auxiliary electrode includes a first portion in contact with the first cathode electrode, a second portion in contact with the second cathode electrode, and a third portion in contact with the first bank layer, and the first portion does not overlap with the first light-emitting layer, and the second portion does not overlap with the second light-emitting layer.

[0025] In an embodiment, the first portion and the second portion may be spaced apart from each other, the third portion is interposed between the first portion and the second portion, and the first cathode electrode and the second cathode electrode are electrically connected through the auxiliary electrode.

[0026] In an embodiment, the first encapsulation layer may include a first inorganic layer on the first cathode electrode and a second inorganic layer on the second cathode electrode, and in a direction perpendicular to the substrate, the first inorganic layer overlaps with the first portion, and the second inorganic layer overlaps with the second portion.

[0027] In an embodiment, each of the first inorganic layer and the second inorganic layer may be in contact with the second bank layer and the third bank layer, and the first inorganic layer and the second inorganic layer are spaced apart from each other in a region overlapping with the non-light-emitting region.

[0028] In an embodiment of the present disclosure, a method of manufacturing a display device includes: forming a substrate including a light-emitting region and a non-light-emitting region, an anode electrode located on the light-emitting region of the substrate, and an auxiliary electrode located on the non-light-emitting region of the substrate; forming a pixel defining layer between the anode electrode and the auxiliary electrode; and forming a first bank material layer, a second bank material layer, and a third bank material layer that completely cover the anode electrode, the auxiliary electrode, and the pixel defining layer; forming a photoresist while exposing the anode electrode and an overlapping portion around the anode electrode, and removing the first bank material layer, the second bank material layer, and the third bank material layer in a portion where the photoresist is not formed through a first etching process to form a hole in a portion overlapping with the anode electrode, and forming the third bank material layer as a third bank layer; partially etching an inner side of the first bank material layer and the second bank material layer overlapping with the hole through a second etching process such that a side surface of the second bank material layer protrudes toward the hole more than a side surface of the first bank material layer and the third bank layer has a tip protruding toward the hole more than the side surface of the second bank material layer, thereby forming a first bank layer and a second bank layer; and forming an organic pattern, an electrode pattern, and a first inorganic layer located on the third bank layer and a light-emitting element by forming a light-emitting layer, a cathode electrode, and a first encapsulation layer on the anode electrode and the third bank layer, forming a hard mask on the anode electrode and an overlapping portion around the anode electrode, and removing the light-emitting layer, the cathode electrode, and the first encapsulation layer located in a portion where the hard mask is not formed through an etching process, wherein in forming the first bank layer and the second bank layer, a cavity is formed between a side surface of the first bank layer facing the light-emitting region and the second bank layer, and the cathode electrode contacts the auxiliary electrode in a portion overlapping with the cavity.

[0029] A display device according to an embodiment includes a bank structure including a first bank layer, a second bank layer, and a third bank layer of the display device and an auxiliary electrode connected to the first bank layer. Sidewalls of the first bank layer of the embodiment may be recessed much more on both sides than sidewalls of the second bank layer to form an undercut portion with the second bank layer. In addition, the third bank layer of the embodiment may have a tip protruding toward the light-emitting region more than the sidewalls of the second bank layer.

[0030] The display device of the embodiment may be formed such that the cathode electrode contacts the auxiliary electrode at a portion overlapping with an undercut portion formed between the first bank layer and the second bank layer. Therefore, according to the embodiment, cathode electrodes provided to be spaced apart from each other in each light-emitting region may be electrically connected through the auxiliary electrode.

[0031] Therefore, according to the display device according to the embodiment, since cathode electrodes provided to overlap with each light-emitting region and be spaced apart from each other and a bank structure provided to overlap with a non-light-emitting region may be formed, and the cathode electrodes are formed to be electrically connected to the auxiliary electrode, moisture penetration defects in the display device caused by detachment of the cathode electrodes and the bank structure may be solved.

[0032] However, the effects of the embodiments are not limited to the effects described herein. By referring to the claims, the above and other effects of the embodiments will become more apparent to those of ordinary skill in the art to which the embodiments pertain. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other aspects and features of the present disclosure will become more apparent by describing embodiments of the present disclosure in detail with reference to the drawings, in which:

[0034] Figure 1 is a schematic perspective view showing an electronic device according to an embodiment;

[0035] Figure 2 is a perspective view showing a display device included in the electronic device according to an embodiment;

[0036] Figure 3 is Figure 2 a schematic cross-sectional view of the display device;

[0037] Figure 4 is a plan view showing the arrangement of light-emitting regions in the Figure 3 display area;

[0038] Figure 5 is a schematic cross-sectional view of the display area taken along line X1-X1' of Figure 4 ;

[0039] Figure 6 is Figure 5 an enlarged schematic cross-sectional view of a first light-emitting region;

[0040] Figure 7 is a plan view showing the Figure 6 first light-emitting region;

[0041] Figure 8 is an enlarged schematic cross-sectional view of a non-light-emitting region provided between the Figure 5 first light-emitting region and a second light-emitting region;

[0042] Figure 9 is Figure 8 an enlarged cross-sectional view of a bank structure; and

[0043] Figures 10 to 21 is a cross-sectional view schematically showing a method of manufacturing a display element layer and a thin film encapsulation layer included in the Figure 5 display device. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0044] The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which various embodiments are shown. However, aspects supported by the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example aspects of the present disclosure to those skilled in the art. Like reference numerals always refer to like elements.

[0045] It should be understood that when an element is referred to as being "on" another element, it can be directly on the other element or there can be intervening elements between the element and the other element. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0046] It should be understood that although the terms "first", "second", "third", and the like may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, without departing from the teachings herein, the "first element", "component", "region", "layer", or "section" discussed below may be referred to as a second element, component, region, layer, or section.

[0047] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. Unless the context clearly dictates otherwise, as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, including "at least one". Thus, reference to "an" element in the claims after the reference to "the" element includes one element and a plurality of elements. For example, unless the context clearly dictates otherwise, "element" has the same meaning as "at least one element". "At least one" should not be construed as limiting "a" or "an". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when the terms "comprises", "comprising", "includes", and / or "including" are used in this specification, they specify the presence of the stated features, regions, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or their groups.

[0048] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another as shown in the figures. It should be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is flipped, an element described as being on the "lower" side of another element will then be oriented on the "upper" side of the other element. Thus, the term "lower" can encompass both the "lower" and "upper" orientations, depending on the specific orientation of the figure. Similarly, if the device in one of the figures is flipped, an element described as "below" or "beneath" another element will then be oriented "above" the other element. Thus, the terms "below" or "beneath" can encompass both the above and below orientations.

[0049] Taking into account the measurements and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein includes the stated value and means within an acceptable deviation of the particular value as determined by one of ordinary skill in the art. For example, the term "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0050] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0051] Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of exemplary embodiments. Thus, variations in the shape of the illustrations as a result, for example, of manufacturing techniques and / or tolerances are to be expected. Accordingly, the embodiments described herein should not be construed as limited to the particular region shapes shown herein, but include deviations in shape that result, for example, from manufacturing. For example, regions shown or described as flat will generally have rough and / or non-linear features. Additionally, sharp corners shown may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the exact shape of the region and are not intended to limit the scope of the claims.

[0052] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0053] Figure 1 is a schematic perspective view of the electronic device 1 according to an embodiment.

[0054] Referring to Figure 1 , the electronic device 1 displays a moving image or a still image. The electronic device 1 may refer to any electronic device that provides a display screen. For example, the electronic device 1 may include a television, a notebook computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smartphone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, a camcorder, and the like that provide a display screen.

[0055] In Figure 1 , a first direction (X-axis direction), a second direction (Y-axis direction), and a third direction (Z-axis direction) are defined. The first direction (X-axis direction) and the second direction (Y-axis direction) may be perpendicular to each other, the first direction (X-axis direction) and the third direction (Z-axis direction) may be perpendicular to each other, and the second direction (Y-axis direction) and the third direction (Z-axis direction) may be perpendicular to each other. It can be understood that the first direction (X-axis direction) means the horizontal direction in the drawing, the second direction (Y-axis direction) means the vertical direction in the drawing, and the third direction (Z-axis direction) means the up-and-down direction in the drawing, that is, the thickness direction. In the following description, unless otherwise specified, the term "direction" may refer to two directions toward both sides extending along the direction. In some aspects, when the two "directions" extending to both sides are to be distinguished from each other, one side will be referred to as "one side in the direction" and the other side will be referred to as "the other side in the direction". In Figure 1 , the direction pointed by the arrow indicating the direction is referred to as one side, and the opposite direction thereof is referred to as the other side.

[0056] Hereinafter, for convenience of explanation, when referring to the surface of the electronic device 1 or each component constituting the electronic device 1, one surface on one side in the direction facing the direction in which the image is displayed (i.e., in the third direction (Z-axis direction)) is referred to as the upper surface, and the opposite surface of the one surface is referred to as the other surface. However, the embodiments of the present disclosure are not limited thereto, and one surface and the other surface of a component may be referred to as the front surface and the rear surface, respectively, or may also be referred to as the first surface or the second surface. In some aspects, when describing the relative positions of each component of the electronic device 1, one side in the third direction (Z-axis direction) may be referred to as the upper side, and the other side in the third direction (Z-axis direction) may be referred to as the lower side.

[0057] The shape of the electronic device 1 can be changed differently. For example, the electronic device 1 may have a shape such as a rectangle with a long width, a rectangle with a long length, a square, a quadrilateral with rounded corners (vertices), other polygons, or a circle in a plan view.

[0058] The electronic device 1 may include a display area DA and a non-display area NDA. The display area DA is an area where an image can be displayed, and the non-display area NDA is an area where an image is not displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA generally may occupy the center of the electronic device 1.

[0059] Figure 2 is a perspective view showing a display device 10 included in the electronic device 1 according to an embodiment.

[0060] Referring to Figure 2 , the electronic device 1 according to an embodiment may include a display device 10. The display device 10 may provide a screen for the electronic device 1. Examples of the display device 10 may include an inorganic light-emitting diode display device, an organic light-emitting display device, a quantum dot light-emitting display device, a plasma display device, and a field emission display device. Hereinafter, an example of using an organic light-emitting diode display device as the display device is shown, but the embodiments of the present disclosure are not limited thereto, and may also be applied to other display devices as long as the same technical idea is applicable thereto.

[0061] The display device 10 may have a planar shape similar to the shape of the electronic device 1 in a plan view. For example, the display device 10 may have a rectangular shape with a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction). The corners where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) intersect may be rounded to have a curvature, but are not limited thereto, and right angles may also be formed. The planar shape of the display device 10 is not limited to a quadrilateral, and may be formed similarly to other polygons, circles, or ellipses.

[0062] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400.

[0063] The display panel 100 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA including pixels for displaying an image and a non-display area NDA provided around the display area DA.

[0064] The display area DA can emit light from a plurality of light-emitting areas or a plurality of openings which will be described later. For example, the display panel 100 may include: a pixel circuit including a switching element, a pixel defining layer defining the light-emitting area or the opening, and a self-luminous element. For example, the self-luminous element may include, but is not limited to, at least one of an organic light-emitting diode (LED) including an organic light-emitting layer, a quantum dot LED including a quantum dot light-emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED. In the following drawings, the self-luminous element is shown as an organic light-emitting diode.

[0065] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of the main area MA of the display panel 100.

[0066] The sub-area SBA may be an area extending from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, curled, or the like. In an example where the sub-area SBA is bent, the sub-area SBA may overlap the main area MA in the thickness direction (e.g., the third direction (Z-axis direction)). The sub-area SBA may include the display driver 200 and a pad portion connected to the circuit board 300. In another embodiment, the sub-area SBA may be omitted, and the display driver 200 and the pad portion may be located in the non-display area NDA.

[0067] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may be formed as an integrated circuit (IC) and mounted on the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be disposed in the sub-area SBA and may overlap the main area MA in the thickness direction by bending of the sub-area SBA. As another example, the display driver 200 may be mounted on the circuit board 300.

[0068] The circuit board 300 may be attached to the pad portion of the display panel 100 using an anisotropic conductive film (ACF). The circuit board 300 may be a flexible film, such as, for example, a flexible printed circuit board or a chip on film. In some aspects, the circuit board 300 may be a rigid printed circuit board.

[0069] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be connected to the touch sensor layer of the display panel 100 ( Figure 3 in “180”). The touch driver 400 may be formed as an integrated circuit.

[0070] Figure 3 is Figure 2 a schematic cross-sectional view of the display device 10.

[0071] Reference Figure 3 Figure 3 , the display panel 100 may include a display layer DPL, a touch sensor layer 180, and a color filter layer 190. The display layer DPL may include a substrate 110, a thin film transistor layer 130, a display element layer 150, and a thin film encapsulation layer 170.

[0072] The substrate 110 may be a base substrate or a base member. The substrate 110 may be a flexible substrate that can be bent, folded, curled, or the like. For example, the substrate 110 may include a polymer resin, such as, by way of example, polyimide (PI), but is not limited thereto. In another embodiment, the substrate 110 may include a glass material or a metal material.

[0073] The thin film transistor layer 130 may be disposed on the substrate 110. The thin film transistor layer 130 may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor layer 130 may include a plurality of thin film transistors ( Figure 4 "TFT" in Figure 5 that constitute pixels (

[0074] The display element layer 150 may be disposed on the thin film transistor layer 130. The display element layer 150 may be positioned to overlap with the display area DA. The display element layer 150 may include a plurality of light emitting elements ( Figure 5 "ED" in

[0075] As an example, according to an embodiment, the display element may include, but is not limited to, at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED.

[0076] The thin film encapsulation layer 170 may be positioned on the display element layer 150. The thin film encapsulation layer 170 may be positioned to overlap with the display area DA and the non-display area NDA. The thin film encapsulation layer 170 may cover the upper surface and the side surface of the display element layer 150, and may protect the display element layer 150 from external oxygen and moisture. The thin film encapsulation layer 170 may include at least one inorganic film and at least one organic film for encapsulating the display element layer 150.

[0077] The color filter layer 190 may be disposed on the touch sensor layer 180. The color filter layer 190 may be positioned to overlap with the display area DA and the non-display area NDA. The color filter layer 190 may absorb a part of the light introduced from the outside of the display device 10 to reduce the reflected light caused by the external light. Accordingly, the color filter layer 190 may prevent color distortion caused by the reflection of the external light.

[0078] Since the color filter layer 190 is directly disposed on the touch sensor layer 180, the display device 10 may be implemented without a separate substrate for the color filter layer 190. Accordingly, the display device 10 may have a relatively small thickness. In some aspects, according to an embodiment, the color filter layer 190 may also be omitted.

[0079] As Figure 3 shown, a part of the display layer DPL overlapping with the sub-region SBA may be bent. In an example in which a part of the display layer DPL is bent, the display driver 200, the circuit board 300, and the touch driver 400 may overlap with the main region MA in the third direction (Z-axis direction).

[0080] Figure 4 is a plan view showing Figure 3 the arrangement of the light-emitting regions EA in the display area DA.

[0081] Referring to Figure 4 , the display area DA according to an embodiment may include a plurality of first light-emitting regions EA1, second light-emitting regions EA2, and third light-emitting regions EA3, and a non-light-emitting region NLA. The non-light-emitting region NLA may be positioned to surround the plurality of first light-emitting regions EA1, second light-emitting regions EA2, and third light-emitting regions EA3.

[0082] The non-light-emitting region NLA may block each light emitted from the plurality of first light-emitting regions EA1, second light-emitting regions EA2, and third light-emitting regions EA3. Accordingly, the non-light-emitting region NLA may help prevent each light emitted from the first light-emitting regions EA1, second light-emitting regions EA2, and third light-emitting regions EA3 from being mixed.

[0083] The light-emitting region EA may include a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3 that emit lights of different colors. Each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may emit red light, green light, or blue light respectively, and the color of the light emitted from each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be changed according to the type of the light-emitting element ED to be described later. In an embodiment, the first light-emitting region EA1 may emit red light of a first color, the second light-emitting region EA2 may emit green light of a second color, and the third light-emitting region EA3 may emit blue light of a third color, but the embodiments of the present disclosure are not limited thereto. In the drawings, the sizes and shapes of each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 are shown to be the same, but the embodiments of the present disclosure are not limited thereto. The sizes and shapes of each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be freely adjusted according to the required characteristics.

[0084] A plurality of the first light-emitting regions EA1, the second light-emitting regions EA2, and the third light-emitting regions EA3 may be defined by a first opening OP1 and a second opening OP2. As an example, the first opening OP1 may be defined by a pixel defining layer 151 to be described later, and the second opening OP2 may be defined by a bank structure 160 to be described later. In a plan view, the second opening OP2 may completely surround the first opening OP1, and the second opening OP2 may be completely surrounded by a non-light-emitting region NLA. Details will be described later.

[0085] In some embodiments, at least one first light-emitting region EA1, at least one second light-emitting region EA2, and at least one third light-emitting region EA3 that are arranged adjacent to each other may form a pixel group PXG. The pixel group PXG may be the smallest unit that emits white light. However, the types and / or the number of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 that constitute the pixel group PXG may be changed according to the embodiments.

[0086] Figure 5 is a schematic cross-sectional view of a display region DA taken along the Figure 4 line X1-X1'. Figure 5 is a partial cross-sectional view of the display device 10 that overlaps with the display region DA, and shows a schematic cross-section of a display layer DPL. That is, Figure 5 shows a cross-section of a substrate 110, a thin-film transistor layer 130, a display element layer 150, and a thin-film encapsulation layer 170 of the display device 10 according to an embodiment. Since the substrate 110 has been described with reference to Figure 3 it, its description will be omitted.

[0087] Referring toFigure 5 , the thin film transistor layer 130 may be positioned on the substrate 110. The thin film transistor layer 130 may include a first buffer layer 111, thin film transistors TFTs, a gate insulating layer 113, a first interlayer insulating layer 121, capacitor electrodes CPEs, a second interlayer insulating layer 123, a first connection electrode CNE1, a first via layer 125, a second connection electrode CNE2, and a second via layer 127.

[0088] The first buffer layer 111 may be disposed on the substrate 110. The first buffer layer 111 may include an inorganic film capable of preventing the penetration of air or moisture. For example, the first buffer layer 111 may include a plurality of inorganic films stacked alternately.

[0089] The thin film transistors TFTs may be disposed on the first buffer layer 111 and may constitute pixel circuits connected to each of a plurality of pixels. As an example, the thin film transistors TFTs may be driving transistors or switching transistors of the pixel circuits. The thin film transistors TFTs may include active layers ACTs, source electrodes SEs, drain electrodes DEs, and gate electrodes GEs.

[0090] The active layer ACT may be disposed on the first buffer layer 111. The active layer ACT may overlap with the gate electrode GE in the third direction (Z-axis direction) and may be insulated from the gate electrode GE through the gate insulating layer 113. In a part of the active layer ACT, the material of the active layer ACT may become a conductor to form the source electrode SE and the drain electrode DE.

[0091] The gate electrode GE may be disposed on the gate insulating layer 113. The gate electrode GE may overlap with the active layer ACT, and the gate insulating layer 113 is interposed between the gate electrode GE and the active layer ACT.

[0092] The gate insulating layer 113 may be disposed on the active layer ACT. The gate insulating layer 113 may cover the active layer ACT and the first buffer layer 111 and may insulate the active layer ACT and the gate electrode GE from each other. The gate insulating layer 113 may include a contact hole through which the first connection electrode CNE1 passes.

[0093] The first interlayer insulating layer 121 may cover the gate electrode GE and the gate insulating layer 113. The first interlayer insulating layer 121 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer 121 may be connected to the contact hole of the gate insulating layer 113 and the contact hole of the second interlayer insulating layer 123.

[0094] The capacitor electrodes CPEs may be disposed on the first interlayer insulating layer 121. The capacitor electrodes CPEs may overlap with the gate electrode GE in the third direction (Z-axis direction). The capacitor electrodes CPEs and the gate electrode GE may form a capacitance.

[0095] The second interlayer insulating layer 123 may cover the capacitor electrode CPE and the first interlayer insulating layer 121. The second interlayer insulating layer 123 may include contact holes through which the first connection electrode CNE1 passes. The contact holes of the second interlayer insulating layer 123 may be connected to the contact holes of the first interlayer insulating layer 121 and the contact holes of the gate insulating layer 113.

[0096] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer 123. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT and the second connection electrode CNE2 to each other. The first connection electrode CNE1 may be inserted into the contact holes formed in the first interlayer insulating layer 121, the second interlayer insulating layer 123, and the gate insulating layer 113, and may contact the drain electrode DE of the thin film transistor TFT.

[0097] The first via layer 125 may cover the first connection electrode CNE1 and the second interlayer insulating layer 123. The first via layer 125 may planarize the underlying structure. The first via layer 125 may include contact holes through which the second connection electrode CNE2 passes.

[0098] The second connection electrode CNE2 may be disposed on the first via layer 125. The second connection electrode CNE2 may be inserted into the contact holes formed in the first via layer 125 and may contact the first connection electrode CNE1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the first anode electrode AE1, the first connection electrode CNE1 to the second anode electrode AE2, and the first connection electrode CNE1 to the third anode electrode AE3 to each other.

[0099] The second via layer 127 may cover the second connection electrode CNE2 and the first via layer 125. The second via layer 127 may include contact holes through which the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 pass.

[0100] The display element layer 150 may be disposed on the second via layer 127. The display element layer 150 may include a pixel defining layer 151, an auxiliary electrode AX, a light emitting element ED, a cover layer CPL, and a bank structure 160.

[0101] The light-emitting element ED according to an embodiment may include a first light-emitting element ED1 disposed in a portion overlapping with the first light-emitting region EA1, a second light-emitting element ED2 disposed in a portion overlapping with the second light-emitting region EA2, and a third light-emitting element ED3 disposed in a portion overlapping with the third light-emitting region EA3. The first light-emitting element ED1 may include a first anode AE1, a first light-emitting layer EL1, and a first cathode CE1, the second light-emitting element ED2 may include a second anode AE2, a second light-emitting layer EL2, and a second cathode CE2, and the third light-emitting element ED3 may include a third anode AE3, a third light-emitting layer EL3, and a third cathode CE3. The first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may emit light of different colors according to the materials of the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3, respectively. For example, the first light-emitting element ED1 may emit red light of a first color, the second light-emitting element ED2 may emit green light of a second color, and the third light-emitting element ED3 may emit blue light of a third color.

[0102] According to an embodiment, the anode AE may be disposed on the second via layer 127. The anode AE may be electrically connected to the drain electrode DE of the thin-film transistor TFT through a first connection electrode CNE1 and a second connection electrode CNE2. According to an embodiment, the anode AE may include a first anode AE1 disposed in the first light-emitting region EA1, a second anode AE2 disposed in the second light-emitting region EA2, and a third anode AE3 disposed in the third light-emitting region EA3. The first anode AE1, the second anode AE2, and the third anode AE3 may be disposed such that the first anode AE1, the second anode AE2, and the third anode AE3 are spaced apart from each other with the auxiliary electrode AX interposed therebetween. For example, the auxiliary electrode AX may be interposed between the first anode AE1 and the second anode AE2, and the auxiliary electrode AX may be interposed between the second anode AE2 and the third anode AE3.

[0103] As an example, the anode AE may have a stacked film structure in which a material layer having a high work function formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3) and a reflective material layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof are stacked. As an example, the first anode AE1, the second anode AE2, and the third anode AE3 may have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, and ITO / Ag / ITO, but is not limited thereto.

[0104] The auxiliary electrode AX according to an embodiment may be disposed on the second via layer 127. The auxiliary electrode AX may be disposed to overlap with the light-emitting region EA and the non-light-emitting region NLA. The auxiliary electrode AX may be electrically connected to the drain electrode DE of the thin-film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2. The auxiliary electrode AX may be spaced apart from the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 in the first direction (X-axis direction) with the pixel defining layer 151 interposed therebetween. For example, the pixel defining layer 151 may be interposed between the auxiliary electrode AX and the first anode electrode AE1, between the auxiliary electrode AX and the second anode electrode AE2, between another auxiliary electrode AX and the second anode electrode AE2, and between another auxiliary electrode AX and the third anode electrode AE3.

[0105] The auxiliary electrode AX according to an embodiment may include the same metal as the anode electrode AE, or include a metal having a low contact resistance with the cathode electrode CE according to an embodiment. In an embodiment, when the auxiliary electrode AX includes the same material as the anode electrode AE, this may facilitate the process of forming the auxiliary electrode AX described herein. The material of the anode electrode AE has been mentioned and will thus be omitted. In another embodiment, when the auxiliary electrode AX is formed of molybdenum (Mo), this may minimize the contact resistance with the cathode electrode CE of the display device 10. However, molybdenum (Mo) is an example, and the auxiliary electrode AX according to an embodiment may include any metal having a low contact resistance with the cathode electrode CE according to an embodiment.

[0106] The pixel defining layer 151 according to an embodiment may be positioned on the second via layer 127, the anode electrode AE, and the auxiliary electrode AX. The pixel defining layer 151 according to an embodiment may be positioned between the anode electrode AE and the auxiliary electrode AX in the first direction (X-axis direction) in a portion overlapping with the light-emitting region EA, thereby separating and insulating the anode electrode AE and the auxiliary electrode AX from each other. In a portion overlapping with each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3, a plurality of pixel defining layers 151 adjacent to each other may define a first opening OP1, and the anode electrode AE may be exposed in a portion overlapping with the first opening OP1.

[0107] The pixel defining layer 151 according to an embodiment may include an inorganic insulating material. As an example, the pixel defining layer 151 may include alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. Zinc oxide may be ZnO and / or ZnO2.

[0108] The bank structure 160 according to an embodiment may be positioned on the auxiliary electrode AX in a portion overlapping with the non-light-emitting region NLA. The bank structure 160 according to an embodiment may define a second opening OP2, and the light-emitting region EA according to an embodiment may be defined by the second opening OP2.

[0109] The bank structure 160 according to an embodiment may include a first bank layer 161, a second bank layer 163, and a third bank layer 165. The first bank layer 161, the second bank layer 163, and the third bank layer 165 may include different materials. For example, the material included in the first bank layer 161 may be different from the materials included in the second bank layer 163 and the third bank layer 165, and the material included in the second bank layer 163 may be different from the material included in the third bank layer 165, which may support different respective characteristics (e.g., etching rate) of the first bank layer 161, the second bank layer 163, and the third bank layer 165. According to an embodiment, a cavity may be formed between the first bank layer 161 and the second bank layer 163. In some aspects, the third bank layer 165 according to an embodiment may have a tip protruding toward the light-emitting region EA more than the second bank layer 163. Details regarding the bank structure 160 will be described later.

[0110] The light-emitting layer EL according to an embodiment may be disposed on the anode AE and the pixel defining layer 151. In the light-emitting layer EL according to an embodiment, when the thin-film transistor TFT applies a predetermined voltage to the anode AE and the cathode CE receives a common voltage or a cathode voltage, each of the holes and electrons may move to the light-emitting layer EL through the hole transport layer and the electron transport layer, and the holes and electrons may combine with each other in the light-emitting layer EL to emit light.

[0111] The light-emitting layer EL according to an embodiment may be spaced apart from each other at portions overlapping with each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3. The first light-emitting layer EL1 may be disposed in a portion overlapping with the first light-emitting region EA1, the second light-emitting layer EL2 may be disposed in a portion overlapping with the second light-emitting region EA2, and the third light-emitting layer EL3 may be disposed in a portion overlapping with the third light-emitting region EA3. As an example, the first light-emitting layer EL1 may be a light-emitting layer that emits red light of a first color, the second light-emitting layer EL2 may be a light-emitting layer that emits green light of a second color, and the third light-emitting layer EL3 may be a light-emitting layer that emits blue light of a third color, but the embodiments of the present disclosure are not limited thereto.

[0112] The light-emitting layer EL according to an embodiment may be an organic light-emitting layer formed of an organic material and may be formed through a deposition process and a photolithography process without using a fine metal mask in the manufacturing process. The manufacturing process will be described later.

[0113] According to an embodiment, the cathode CE may be disposed on the light-emitting layer EL. The cathode CE may include a transparent conductive material such that light generated in the light-emitting layer EL can be emitted. The cathode CE may receive a common voltage or a low-potential voltage. In a case where the anode AE receives a voltage corresponding to a data voltage and the cathode CE receives a low-potential voltage, a potential difference is formed between the anode AE and the cathode CE, and thus the light-emitting layer EL may emit light.

[0114] According to an embodiment, the cathode CE may include a material layer having a small work function, such as, for example, Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or a compound or mixture thereof (for example, a mixture of Ag and Mg or the like). The cathode CE may further include a transparent metal oxide layer disposed on the material layer having a small work function.

[0115] According to an embodiment, the cathode CE may be spaced apart from each other at portions overlapping with each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3. The first cathode CE1 may be disposed on the first light-emitting layer EL1 in the first light-emitting region EA1, the second cathode CE2 may be disposed on the second light-emitting layer EL2 in the second light-emitting region EA2, and the third cathode CE3 may be disposed on the third light-emitting layer EL3 in the third light-emitting region EA3. The first cathode CE1, the second cathode CE2, and the third cathode CE3 spaced apart from each other at portions overlapping with each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be electrically connected to each other through the auxiliary electrode AX.

[0116] According to an embodiment, the cathode CE may be formed by a deposition process and a photolithography process during a manufacturing process without a fine metal mask. The manufacturing process will be described later.

[0117] According to an embodiment, the cover layer CPL may be disposed on the cathode CE. The cover layer CPL may include an inorganic insulating material to prevent patterns disposed on the plurality of light-emitting elements ED and the third bank layer 165 from being damaged by external air, and to prevent patterns disposed on the plurality of light-emitting elements ED and the bank structure 160 from being peeled off during a process of manufacturing the display device 10.

[0118] According to an embodiment, the cover layer CPL may include an inorganic insulating material. As an example, according to an embodiment, the cover layer CPL may include alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The zinc oxide may be ZnO and / or ZnO2.

[0119] The cover layer CPL according to the embodiment may be spaced apart from each other at portions overlapping with each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3. The first cover layer CPL1 may be disposed on the first cathode CE1 in the portion overlapping with the first light-emitting region EA1, the second cover layer CPL2 may be disposed on the second cathode CE2 in the portion overlapping with the second light-emitting region EA2, and the third cover layer CPL3 may be disposed on the third cathode CE3 in the portion overlapping with the third light-emitting region EA3.

[0120] On the bank structure 160 according to the embodiment, a plurality of first organic patterns ELP1, second organic patterns ELP2, and third organic patterns ELP3, a plurality of first electrode patterns CEP1, second electrode patterns CEP2, and third electrode patterns CEP3, and a plurality of first cover patterns CLP1, second cover patterns CLP2, and third cover patterns CLP3 may be provided to surround the second opening OP2.

[0121] The plurality of first organic patterns ELP1, second organic patterns ELP2, and third organic patterns ELP3 may be positioned on the third bank layer 165. The first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 may respectively include materials the same as those of the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3. The first organic pattern ELP1 may include a material the same as that of the first light-emitting layer EL1, the second organic pattern ELP2 may include a material the same as that of the second light-emitting layer EL2, and the third organic pattern ELP3 may include a material the same as that of the third light-emitting layer EL3.

[0122] As described herein, during the process of manufacturing the display device 10, the light-emitting layer EL according to the embodiment may be formed through a deposition process and a photolithography process without using a separate fine metal mask. Therefore, during the process of manufacturing the display device 10, the material for forming the light-emitting layer EL may be deposited on the anode AE and also on the third bank layer 165. Since the third bank layer 165 includes tips, the first organic patterns ELP1, second organic patterns ELP2, and third organic patterns ELP3 according to the embodiment may be traces formed when the material of the light-emitting layer EL deposited on the third bank layer 165 is not connected to the material of the light-emitting layer EL deposited on the anode AE and is disconnected.

[0123] In a portion overlapping with the non-light-emitting region NLA, the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 may be arranged such that the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 are spaced apart from each other in a first direction (X-axis direction). A second encapsulation layer 173 may be disposed between the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 that are spaced apart from each other. The first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 according to an embodiment may be formed to completely cover the third bank layer 165 during a process of manufacturing the display device 10, and then portions of the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 overlapping with the non-light-emitting region NLA may be removed by a subsequent etching process. Accordingly, the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 may include trench portions TP in the portions overlapping with the non-light-emitting region NLA. A manufacturing process will be described later.

[0124] A plurality of first electrode patterns CEP1, second electrode patterns CEP2, and third electrode patterns CEP3 may be respectively disposed on the plurality of first organic patterns ELP1, second organic patterns ELP2, and third organic patterns ELP3. For example, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be directly disposed on the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, respectively. An arrangement relationship between the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 and the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 may be the same as an arrangement relationship between the first cathode CE1, the second cathode CE2, and the third cathode CE3 and the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3. The first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may respectively include materials that are the same as those of the first cathode CE1, the second cathode CE2, and the third cathode CE3.

[0125] As described herein, the cathode electrode CE according to an embodiment may be formed through a deposition process and a photolithography process without using a separate fine metal mask during the process of manufacturing the display device 10. Therefore, during the process of manufacturing the display device 10, the material for forming the cathode electrode CE may be deposited on the anode electrode AE and may also be deposited on the third bank layer 165. Since the third bank layer 165 includes tips, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 according to an embodiment may be traces formed when the material of the cathode electrode CE deposited on the third bank layer 165 is not connected to and is disconnected from the material of the cathode electrode CE deposited on the anode electrode AE.

[0126] The deposition process for forming the cathode electrode CE according to an embodiment may have a higher step coverage than the deposition process for forming the light-emitting layer EL and the deposition process for forming the cover layer CPL. Therefore, during the process of manufacturing the display device 10, the material for forming the cathode electrode CE may also be deposited on the side surface of the second bank layer 163 facing the light-emitting region EA. Accordingly, the second bank layer 163 according to an embodiment may further include a first residual electrode pattern CP1, a second residual electrode pattern CP2, and a third residual electrode pattern CP3 on the side surface facing the light-emitting region EA.

[0127] In a portion overlapping with the non-light-emitting region NLA, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be arranged such that the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 are spaced apart from each other in a first direction (X-axis direction), and the second encapsulation layer 173 may be disposed between the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 that are spaced apart from each other. During the process of manufacturing the display device 10, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 according to an embodiment may be formed to completely cover the third bank layer 165, and then a portion of the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be removed through a subsequent etching process. Therefore, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may include a trench portion TP in a portion overlapping with the non-light-emitting region NLA. The manufacturing process will be described later.

[0128] A plurality of first cover patterns CLP1, second cover patterns CLP2, and third cover patterns CLP3 may be respectively positioned on a plurality of first electrode patterns CEP1, second electrode patterns CEP2, and third electrode patterns CEP3. The first cover patterns CLP1, second cover patterns CLP2, and third cover patterns CLP3 may include materials that are the same as the materials of the first cover layer CPL1, second cover layer CPL2, and third cover layer CPL3, respectively. The arrangement relationship between the first cover patterns CLP1, second cover patterns CLP2, and third cover patterns CLP3 and the first electrode patterns CEP1, second electrode patterns CEP2, and third electrode patterns CEP3 may be the same as the arrangement relationship between the first cover layer CPL1, second cover layer CPL2, and third cover layer CPL3 and the first cathode CE1, second cathode CE2, and third cathode CE3.

[0129] In the process of manufacturing the display device 10, the cover layer CPL according to the embodiment may be formed by a deposition process and a photolithography process without using a separate fine metal mask. Therefore, during the process of manufacturing the display device 10, the material of the cover layer CPL may be deposited on the anode electrode AE and also on the third bank layer 165. Since the third bank layer 165 includes tips, the first cover patterns CLP1, second cover patterns CLP2, and third cover patterns CLP3 according to the embodiment may be traces formed when the material of the cover layer CPL deposited on the third bank layer 165 is not connected to the cover layer CPL deposited on the anode electrode AE and is disconnected.

[0130] In a portion overlapping with the non-light-emitting region NLA, the first cover patterns CLP1, second cover patterns CLP2, and third cover patterns CLP3 may be arranged such that the first cover patterns CLP1, second cover patterns CLP2, and third cover patterns CLP3 are spaced apart from each other in a first direction (X-axis direction). The second encapsulation layer 173 may be disposed between the first cover patterns CLP1, second cover patterns CLP2, and third cover patterns CLP3 that are spaced apart from each other. The first cover patterns CLP1, second cover patterns CLP2, and third cover patterns CLP3 according to the embodiment may be formed to completely cover the third bank layer 165 during the process of manufacturing the display device 10, and then portions of the first cover patterns CLP1, second cover patterns CLP2, and third cover patterns CLP3 may be removed by a subsequent etching process. Therefore, the first cover patterns CLP1, second cover patterns CLP2, and third cover patterns CLP3 may include trench portions TP in a portion overlapping with the non-light-emitting region NLA. The manufacturing process will be described later.

[0131] The thin film encapsulation layer 170 may be positioned on the display element layer 150. The thin film encapsulation layer 170 includes at least one inorganic film to prevent oxygen or moisture from permeating into the display element layer 150. The thin film encapsulation layer 170 may include at least one organic film to protect the display element layer 150 from foreign substances such as dust. The thin film encapsulation layer 170 may include a first encapsulation layer 171, a second encapsulation layer 173, and a third encapsulation layer 175 that are sequentially stacked.

[0132] According to an embodiment, the first encapsulation layer 171 may be disposed on the first cover layer CPL1, the second cover layer CPL2, and the third cover layer CPL3, and the first cover pattern CLP1, the second cover pattern CLP2, and the third cover pattern CLP3. Since the first encapsulation layer 171 according to an embodiment may be formed by a chemical vapor deposition (CVD) process, the first encapsulation layer 171 may be formed to have a uniform thickness along the contour of the underlying structure.

[0133] The first encapsulation layer 171 may include one or more inorganic insulating materials. As an example, the first encapsulation layer 171 may include one or more of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. Zinc oxide may be ZnO and / or ZnO2.

[0134] According to an embodiment, the first encapsulation layer 171 may include a first inorganic layer 171-1, a second inorganic layer 171-2, and a third inorganic layer 171-3. The first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be positioned to overlap with the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3, respectively. As an example, the first inorganic layer 171-1 may overlap with the first light emitting region EA1 and cover the first cover layer CPL1 and the first cover pattern CLP1. In some aspects, the second inorganic layer 171-2 may overlap with the second light emitting region EA2 and cover the second cover layer CPL2 and the second cover pattern CLP2. In some aspects, the third inorganic layer 171-3 may overlap with the third light emitting region EA3 and cover the third cover layer CPL3 and the third cover pattern CLP3.

[0135] In the drawings, the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 are shown formed in the same layer, but the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be formed in different processes. For example, the first inorganic layer 171-1 may be formed after forming the first cathode CE1, the second inorganic layer 171-2 may be formed after forming the second cathode CE2, and the third inorganic layer 171-3 may be formed after forming the third cathode CE3. The manufacturing process will be described later.

[0136] In a portion overlapping with the non-light-emitting region NLA, the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be arranged such that the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 are spaced apart from each other in a first direction (X-axis direction), and the second encapsulation layer 173 may be disposed between the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 that are spaced apart from each other. The first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 according to an embodiment may be formed to completely cover the third bank layer 165 in a process of manufacturing the display device 10, and then portions of the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be removed by a subsequent etching process. Accordingly, the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may include trench portions TP in a portion overlapping with the non-light-emitting region NLA.

[0137] The second encapsulation layer 173 according to an embodiment may be disposed on the first encapsulation layer 171 and may flatten a step formed by the first encapsulation layer 171. The second encapsulation layer 173 may include a polymer-based material. As an example, the second encapsulation layer 173 may include one or more of an acrylic resin, an epoxy resin, a silicone resin, a silicone acrylic resin, a polyimide, and polyethylene.

[0138] The third encapsulation layer 175 according to an embodiment may be disposed on the second encapsulation layer 173 and may completely cover the second encapsulation layer 173. Since the third encapsulation layer 175 may be formed by a chemical vapor deposition (CVD) process, the third encapsulation layer 175 may be formed to have a uniform thickness. The third encapsulation layer 175 may include the same material as that of the first encapsulation layer 171.

[0139] Figure 6 is Figure 5 an enlarged schematic cross-sectional view of the first light-emitting region EA1.

[0140] Referring to Figure 6 , the first anode AE1 according to an embodiment may be positioned such that the first anode AE1 is spaced apart from a plurality of auxiliary electrodes AX in a first direction (X-axis direction) on the second via layer 127, and the first anode AE1 may be disposed between the plurality of auxiliary electrodes AX. The pixel defining layer 151 may be positioned between the first anode AE1 and the auxiliary electrodes AX that are spaced apart from each other.

[0141] In a portion overlapping with the first opening OP1, the first light-emitting layer EL1 according to the embodiment may be disposed on the first anodic electrode AE1 and may completely cover the first anodic electrode AE1. In some aspects, in a portion overlapping with the second opening OP2, the first light-emitting layer EL1 according to the embodiment may be disposed on the pixel defining layer 151 and the auxiliary electrode AX, may completely cover the pixel defining layer 151, and may cover a part of the auxiliary electrode AX. In a portion overlapping with the non-light-emitting region NLA, the first light-emitting layer EL1 according to the embodiment may be in contact with a part of the auxiliary electrode AX and may not overlap with the cavity provided between the first bank layer 161 and the second bank layer 163. In some aspects, the first light-emitting layer EL1 according to the embodiment may not be in contact with the bank structure 160.

[0142] The first cathodic electrode CE1 according to the embodiment may completely cover the first light-emitting layer EL1 in a portion overlapping with the second opening OP2. In addition, in a portion overlapping with the non-light-emitting region NLA, the first cathodic electrode CE1 according to the embodiment may cover the auxiliary electrode AX and may be in contact with the auxiliary electrode AX. In other words, in a portion overlapping with the cavity, the first cathodic electrode CE1 according to the embodiment may cover the auxiliary electrode AX and may be in contact with the auxiliary electrode AX. The first cathodic electrode CE1 according to the embodiment may be electrically connected to the auxiliary electrode AX.

[0143] As described herein, the deposition process for forming the first cathodic electrode CE1 according to the embodiment may have a higher step coverage than the deposition process for forming the first light-emitting layer EL1. Therefore, since a part of the material for forming the first cathodic electrode CE1 according to the embodiment is in contact with the bank structure 160 during the process of manufacturing the display device 10, the first residual electrode pattern CP1 may be formed.

[0144] The first cover layer CPL1 according to the embodiment may completely cover the first cathodic electrode CE1 in a portion overlapping with the first opening OP1 and may cover a part of the first cathodic electrode CE1 in a portion overlapping with the second opening OP2. This may be achieved because the deposition process for forming the first cathodic electrode CE1 during the process of manufacturing the display device 10 is a process having a higher step coverage than the deposition process for forming the first cover layer CPL1. Redundant descriptions will be omitted. The first cover layer CPL1 according to the embodiment may not overlap with the cavity provided between the first bank layer 161 and the second bank layer 163, and the first cover layer CPL1 may not be in contact with the bank structure 160.

[0145] The first bank layer 161 according to an embodiment may be positioned on the auxiliary electrode AX. The first bank layer 161 may be arranged to be in contact with the auxiliary electrode AX in a portion overlapping with the non-light-emitting region NLA. The first bank layer 161 according to an embodiment may include an inorganic insulating material or a metal. As an example, the first bank layer 161 may include at least one of silicon nitride and aluminum, but is not limited thereto.

[0146] A cavity may be formed between the first bank layer 161 and the second bank layer 163 according to an embodiment. Details will be described later.

[0147] The second bank layer 163 according to an embodiment may be positioned on the first bank layer 161. The second bank layer 163 may be arranged to be in contact with the first bank layer 161 in a portion overlapping with the non-light-emitting region NLA. The second bank layer 163 according to an embodiment may include an inorganic insulating material. Since the second bank layer 163 includes an inorganic insulating material, the interfacial adhesion with the first inorganic layer 171-1 may be improved. Accordingly, the display device 10 according to an embodiment may solve the external moisture penetration defect caused by the faulty detachment of the second bank layer 163 and the first inorganic layer 171-1.

[0148] The first bank layer 161 and the second bank layer 163 according to an embodiment may include different insulating materials. Since the first bank layer 161 and the second bank layer 163 include different materials, the first bank layer 161 and the second bank layer 163 may have different etching rates even when the same etching process is performed in the process of manufacturing the display device 10. That is, even when the same etching process is performed, the first bank layer 161 and the second bank layer 163 may be formed into different shapes. As an example, the second bank layer 163 may include silicon oxide, but is not limited thereto. For example, the second bank layer 163 may be silicon oxide, but is not limited thereto.

[0149] The third bank layer 165 according to an embodiment may be positioned on the second bank layer 163. The third bank layer 165 may be arranged to be in contact with the second bank layer 163 in a portion overlapping with the non-light-emitting region NLA. The third bank layer 165 according to an embodiment may include a metal that is stable in an etching process. As an example, the third bank layer 165 may include titanium (Ti).

[0150] During the process of manufacturing the display device 10, the third bank layer 165 according to an embodiment may be more stable than the first bank layer 161 and the second bank layer 163 in an etching process, and thus, the third bank layer 165 according to an embodiment may include a tip protruding toward the first light-emitting region EA1 more than the second bank layer 163.

[0151] In the display device 10 according to the embodiment, since the third bank layer 165 includes a tip TIP, during the process of manufacturing the display device 10, the first light-emitting element ED1 disposed to overlap with the first light-emitting region EA1 can be formed without a fine metal mask. The manufacturing process will be described later.

[0152] The first organic pattern ELP1 according to the embodiment can be disposed on the third bank layer 165 and can be in contact with the tip TIP of the third bank layer 165. In some aspects, the first electrode pattern CEP1 and the first cover pattern CLP1 according to the embodiment can overlap with the tip TIP of the third bank layer 165 in the third direction (Z-axis direction). Other redundant descriptions will be omitted.

[0153] The first inorganic layer 171-1 according to the embodiment can completely cover the first light-emitting element ED1 and the first cover layer CPL1 in the portion overlapping with the first opening OP1, and can cover the first cathode CE1, the first cover layer CPL1, the first residual electrode pattern CP1, and the first cover pattern CLP1 in the portions overlapping with the second opening OP2 and the non-light-emitting region NLA.

[0154] The first inorganic layer 171-1 according to the embodiment can perform coverage along the contour formed by the first bank layer 161, the second bank layer 163, and the third bank layer 165. Specifically, the first inorganic layer 171-1 according to the embodiment can be disposed in the portion overlapping with the cavity and can cover and contact the first cathode CE1 in the portion overlapping with the cavity. For convenience of explanation, the first cathode CE1 and the first inorganic layer 171-1 are shown in the drawings as being in contact with the first bank layer 161, but the embodiments of the present disclosure are not limited thereto. Depending on the process conditions, the first cathode CE1 and the first inorganic layer 171-1 may not be in contact with the first bank layer 161 either.

[0155] The first inorganic layer 171-1 according to the embodiment can cover the second bank layer 163 and the first residual electrode pattern CP1 and can be in contact with the second bank layer 163 and the first residual electrode pattern CP1. In addition, the first inorganic layer 171-1 according to the embodiment can cover the protruding tip TIP of the third bank layer 165 and can be in contact with the protruding tip TIP of the third bank layer 165. In some aspects, the first inorganic layer 171-1 can cover a portion of the first organic pattern ELP1, the first electrode pattern CEP1, and the first cover pattern CLP1, and the first inorganic layer 171-1 can be in contact with this portion of the first organic pattern ELP1, the first electrode pattern CEP1, and the first cover pattern CLP1. Other redundant descriptions will be omitted.

[0156] The second encapsulation layer 173 according to the embodiment may planarize the step formed by the first inorganic layer 171-1 in a portion overlapping with the first light-emitting region EA1 and the non-light-emitting region NLA. The second encapsulation layer 173 according to the embodiment may contact the third bank layer 165 in a portion overlapping with the non-light-emitting region NLA. Details will be described later.

[0157] Figure 7 is a schematic plan view showing Figure 6 the first light-emitting region EA1.

[0158] Referring to Figure 7 , in the plan view, the pixel defining layer 151 may define the first opening OP1 and may expose the first anodic electrode AE1 in a portion overlapping with the first opening OP1. In the plan view, the pixel defining layer 151 may completely surround the first anodic electrode AE1. In the plan view, the pixel defining layer 151 according to the embodiment may be positioned inside the first light-emitting region EA1.

[0159] In the plan view, the first light-emitting layer EL1 may completely cover the first anodic electrode AE1 and the pixel defining layer 151. In some aspects, in the plan view, the first cathodic electrode CE1 may completely cover the first light-emitting layer EL1, the first anodic electrode AE1, and the pixel defining layer 151. In other words, in the plan view, the first anodic electrode AE1 and the pixel defining layer 151 may be disposed inside the first light-emitting layer EL1, and in the plan view, the first anodic electrode AE1, the pixel defining layer 151, and the first light-emitting layer EL1 may be disposed inside the first cathodic electrode CE1.

[0160] In the plan view, the non-light-emitting region NLA may be defined by a portion overlapping with the bank structure 160. In some aspects, in the plan view, the bank structure 160 may define the second opening OP2, expose the first cathodic electrode CE1 in a portion overlapping with the second opening OP2, and completely surround the first cathodic electrode CE1.

[0161] Figure 8 is an enlarged schematic cross-sectional view of the non-light-emitting region NLA disposed between Figure 5 the first light-emitting region EA1 and the second light-emitting region EA2. Figure 9 is Figure 8 an enlarged cross-sectional view of the bank structure 160.

[0162] Referring to Figure 8 , the first light-emitting region EA1 and the second light-emitting region EA2 according to the embodiment may be spaced apart from each other, and the non-light-emitting region NLA is interposed between the first light-emitting region EA1 and the second light-emitting region EA2.

[0163] The auxiliary electrode AX according to an embodiment may be disposed on the second via layer 127 and may be disposed between the first anode electrode AE1 and the second anode electrode AE2. The auxiliary electrode AX may be disposed in a portion overlapping with the non-light-emitting region NLA, and the auxiliary electrode AX may be spaced apart from the first anode electrode AE1 and the second anode electrode AE2, and the pixel defining layer 151 is interposed between the auxiliary electrode AX and the first anode electrode AE1 and between the auxiliary electrode AX and the second anode electrode AE2.

[0164] In some embodiments, the auxiliary electrode AX according to an embodiment may include a first surface AX1 facing the bank structure 160. The first surface AX1 may have a first portion ax1, a second portion ax2, and a third portion ax3 according to the structure with which it is in contact. Specifically, the first portion ax1 may be a portion in contact with the first cathode electrode CE1, the second portion ax2 may be a portion in contact with the second cathode electrode CE2, and the third portion ax3 may be a portion in contact with the first bank layer 161. The third portion ax3 may be positioned between the first portion ax1 and the second portion ax2.

[0165] Since the auxiliary electrode AX according to an embodiment includes the first portion ax1 and the second portion ax2, the auxiliary electrode AX may be electrically connected to the first cathode electrode CE1 and the second cathode electrode CE2 that are spaced apart from each other in the first light-emitting region EA1 and the second light-emitting region EA2, respectively.

[0166] The first bank layer 161 according to an embodiment may space the auxiliary electrode AX and the second bank layer 163 apart from each other in the third direction (Z-axis direction), and may space the first cathode electrode CE1 and the second cathode electrode CE2 apart from each other in the first direction (X-axis direction).

[0167] In some embodiments, the first bank layer 161 may include a first side surface 1c and a second side surface 1d. The first side surface 1c may be disposed toward the first light-emitting region EA1, and the second side surface 1d may be disposed toward the second light-emitting region EA2.

[0168] The first side surface 1c according to an embodiment may be recessed much more toward one side in the first direction (X-axis direction) than the first side surface 3c of the second bank layer 163. Accordingly, an undercut portion may be formed between the second bank layer 163 and the first side surface 1c of the first bank layer 161, and a cavity may be formed in a portion where the undercut portion is formed. The second side surface 1d according to an embodiment may be recessed much more toward the other side in the first direction (X-axis direction) than the second side surface 3d of the second bank layer 163. Accordingly, an undercut portion may be formed between the second bank layer 163 and the second side surface 1d of the first bank layer 161, and a cavity may be formed in a portion where the undercut portion is formed.

[0169] Since the display device 10 according to the embodiment includes a cavity formed between the first bank layer 161 and the second bank layer 163, the formed cavity can help ensure that the first cathode electrode CE1 and the second cathode electrode CE2 are disposed in the cavity, while the first light-emitting layer EL1 and the second light-emitting layer EL2 are not formed in the portion overlapping with the cavity. This can be achieved by the step coverage characteristics of each performed process. Redundant descriptions will be omitted.

[0170] The second bank layer 163 according to the embodiment may be disposed on the first bank layer 161, and may space the first light-emitting element ED1 and the second light-emitting element ED2 apart from each other. In some aspects, the second bank layer 163 may be in contact with the first inorganic layer 171-1 and the second inorganic layer 171-2, and may space the first inorganic layer 171-1 and the second inorganic layer 171-2 apart from each other.

[0171] In some embodiments, the second bank layer 163 according to the embodiment may include a first side surface 3c and a second side surface 3d. The first side surface 3c may be disposed toward the first light-emitting region EA1, and the second side surface 3d may be disposed toward the second light-emitting region EA2. The first side surface 3c of the second bank layer 163 may protrude more toward the first light-emitting region EA1 than the first side surface 1c of the first bank layer 161, and may be recessed much more than the first side surface 5c of the third bank layer 165 toward one side in the first direction (X-axis direction). Accordingly, an undercut portion may be formed between the first side surface 3c of the second bank layer 163 and the third bank layer 165.

[0172] In some aspects, the second side surface 3d of the second bank layer 163 may protrude more toward the second light-emitting region EA2 than the second side surface 1d of the first bank layer 161, and may be recessed much more than the second side surface 5d of the third bank layer 165 toward the other side in the first direction (X-axis direction). Accordingly, an undercut portion may be formed between the second side surface 3d of the second bank layer 163 and the third bank layer 165.

[0173] Refer to Figure 9 , the first side surface 3c of the second bank layer 163 may include a first portion 3ca in contact with the first residual electrode pattern CP1 and a second portion 3cb in contact with the first inorganic layer 171-1. The area W3ca of the first portion 3ca may be smaller than the area W3cb of the second portion 3cb. In the display device 10 according to the embodiment, since the area W3cb of the second portion 3cb is formed to be larger than the area W3ca of the first portion 3ca, the adhesiveness between the second bank layer 163 and the first inorganic layer 171-1 may be increased, thereby solving the external air moisture penetration defect caused by the faulty detachment of the display device 10.

[0174] In some embodiments, the second side surface 3d of the second dam layer 163 may include a first portion 3da in contact with the second residual electrode pattern CP2 and a second portion 3db in contact with the second inorganic layer 171-2. The area W3da of the first portion 3da may be smaller than the area W3db of the second portion 3db. Redundant descriptions will be omitted.

[0175] In some embodiments, the height H161 of the first dam layer 161 according to the embodiment may be smaller than the height H163 of the second dam layer 163, and the width W161 of the first dam layer 161 according to the embodiment may be smaller than the width W163 of the second dam layer 163. As an example, the height H163 of the second dam layer 163 may be greater than twice the height H161 of the first dam layer 161. As an example, the range of the height H161 of the first dam layer 161 according to the embodiment may be from 500 angstroms to 2000 angstroms, and the range of the height H163 of the second dam layer 163 may be from 5000 angstroms to 10000 angstroms.

[0176] The width W163 of the second dam layer 163 according to the embodiment may be equal to the width Wuc of the undercut portion formed between the two side surfaces of the first dam layer 161 according to the embodiment and the second dam layer 163 plus the width W161 of the first dam layer 161. As an example, the width Wuc of the undercut portion according to the embodiment may be greater than twice the height H161 of the first dam layer 161. As an example, the width of the cavity corresponding to the undercut portion may be greater than twice the height H161 of the first dam layer 161. In some aspects, the width of the cavity in the direction parallel to the substrate 110 may be greater than twice the height H161 of the first dam layer 161.

[0177] Referring to Figure 8 , the third dam layer 165 according to the embodiment may include a first side surface 5c, a second side surface 5d, and a first surface 5b. The first side surface 5c may be disposed toward the first light-emitting region EA1, the second side surface 5d may be disposed toward the second light-emitting region EA2, and the first surface 5b may be disposed toward the second encapsulation layer 173.

[0178] The first side surface 5c according to the embodiment may protrude toward the first light-emitting region EA1 more than the first side surface 3c of the second dam layer 163, and thus, the third dam layer 165 may have a tip TIP that protrudes toward the first light-emitting region EA1 more than the first side surface 3c of the second dam layer 163. In some aspects, the second side surface 5d according to the embodiment may protrude toward the second light-emitting region EA2 more than the second side surface 3d of the second dam layer 163, and thus, the third dam layer 165 may have a tip TIP that protrudes toward the second light-emitting region EA2 more than the second side surface 3d of the second dam layer 163. That is, the third dam layer 165 may have tips TIP that protrude toward the first light-emitting region EA1 and the second light-emitting region EA2 on both sides.

[0179] Refer to Figure 9 Figure 9 , the first surface 5b of the third bank layer 165 can be divided into a first part 5ba, a second part 5bb, and a third part 5bc according to the contact structure. According to an embodiment, the first part 5ba and the second part 5bb can be spaced apart from each other, and the third part 5bc is between the first part 5ba and the second part 5bb.

[0180] According to an embodiment, the first part 5ba can be in contact with the first organic pattern ELP1, and can overlap with the first electrode pattern CEP1, the first cover pattern CLP1, and the first inorganic layer 171-1 in the third direction (Z-axis direction). According to an embodiment, the second part 5bb can be in contact with the second organic pattern ELP2, and can overlap with the second electrode pattern CEP2, the second cover pattern CLP2, and the second inorganic layer 171-2 in the third direction (Z-axis direction). According to an embodiment, the third part 5bc can be positioned between the first part 5ba and the second part 5bb, and can be in contact with the second encapsulation layer 173. According to an embodiment, the third part 5bc does not overlap with the first organic pattern ELP1, the first electrode pattern CEP1, the first cover pattern CLP1, the first inorganic layer 171-1, the second organic pattern ELP2, the second electrode pattern CEP2, the second cover pattern CLP2, and the second inorganic layer 171-2 in the third direction (Z-axis direction).

[0181] For convenience of explanation, the structures overlapping with the first light-emitting region EA1 and the second light-emitting region EA2 are shown and then described, but the third light-emitting region EA3 can have the same structure and characteristics as the first light-emitting region EA1 and the second light-emitting region EA2.

[0182] Figures 10 to 21 Schematically shows the manufacturing of Figure 5 The cross-sectional view of the method of the display element layer 150 and the thin film encapsulation layer 170 included in the display device 10.

[0183] In the description of the methods and processes herein, the operations can be performed in an order different from the order shown and / or described, or the operations can be in a different order or at different times. Some operations can also be excluded from the methods and processes, one or more operations can be repeated, or other operations can be added. According to the various exemplary aspects described herein, descriptions such as an element "can be arranged", "can be formed", and the like include methods, processes, and techniques for arranging, forming, positioning, and modifying the element and the like.

[0184] Refer to Figure 10, the method may include forming a plurality of anode electrodes AE and a plurality of auxiliary electrodes AX on the thin film transistor layer 130, where the plurality of anode electrodes AE are spaced apart from each other and the plurality of auxiliary electrodes AX are spaced apart from each other, and the method may include forming a pixel defining layer 151 between the plurality of anode electrodes AE and the plurality of auxiliary electrodes AX. The anode electrode AE may include a first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3.

[0185] The auxiliary electrode AX according to an embodiment may include the same material as that of the anode electrode AE, or may include a material different from that of the anode electrode AE. In an example of an embodiment in which the method includes forming an auxiliary electrode AX of the same material as that of the anode electrode AE, the method may have the advantage of simplifying the process of forming the auxiliary electrode AX. Although not shown, the thin film transistor layer 130 may be disposed on the substrate 110, and the structure of the thin film transistor layer 130 is the same as that Figure 5 described herein. A detailed description thereof will be omitted.

[0186] Next, referring to Figure 11 , the method may include forming a first bank material layer 161L, a second bank material layer 163L, and a third bank material layer 165L such that the first bank material layer 161L, the second bank material layer 163L, and the third bank material layer 165L are completely formed on the plurality of anode electrodes AE, the plurality of auxiliary electrodes AX, and the pixel defining layer 151. The method may include sequentially stacking and disposing the first bank material layer 161L, the second bank material layer 163L, and the third bank material layer 165L.

[0187] Next, referring to Figure 12 and Figure 13 , the method may include forming a photoresist PR, except for the portions overlapping with the anode electrode AE and the pixel defining layer 151. For example, the method may include forming a photoresist PR such that the photoresist PR does not overlap with the anode electrode AE and the pixel defining layer 151. Next, the method may include performing a first etching process of etching portions of the first bank material layer 161L, the second bank material layer 163L, and the third bank material layer 165L using the photoresist PR as a mask. In an embodiment, the first etching process may include isotropic dry etching. The portions of the first bank material layer 161L, the second bank material layer 163L, and the third bank material layer 165L at the portions where the photoresist PR is not formed may be isotropically etched by the first etching process. The term "portion" may refer to a "zone" or "region" associated with performing the method (e.g., forming, etching, and similar methods).

[0188] As Figure 13As shown, in this process, the method may include removing portions of the first bank material layer 161L, the second bank material layer 163L, and the third bank material layer 165L in portions overlapping with the plurality of anodes AE. Thus, holes HOL may be formed in the portions overlapping with the plurality of anodes AE, and the plurality of anodes AE and the pixel defining layer 151 may be exposed. Through this process, the third bank material layer 165L may be formed into Figure 5 the form of the third bank layer 165 shown in

[0189] Next, referring to Figure 13 and Figure 14 , after forming a photoresist PR covering the same portions as the first etching process on the third bank layer 165, the method may include performing a second etching process using the photoresist PR as a mask. In an embodiment, the second etching process may include anisotropic dry etching. In this process, the second etching process may remove portions inside the first bank material layer 161L and the second bank material layer 163L in the portions overlapping with the holes HOL.

[0190] The first bank material layer 161L and the second bank material layer 163L according to an embodiment may include different materials. For example, the material included in the first bank material layer 161L may be different from the material included in the second bank material layer 163L. Thus, the first bank material layer 161L and the second bank material layer 163L may have different etching rates. That is, in the display device 10 according to an embodiment, the method may include adjusting the materials and process conditions such that, in the same etching process, the etching rate of the first bank material layer 161L is greater than the etching rate of the second bank material layer 163L. As an example, when the first bank material layer 161L is formed of silicon nitride, the second bank material layer 163L may be formed of silicon oxide. However, this is only an example, and the present disclosure is not limited thereto.

[0191] In this process, the first bank material layer 161L may be formed into Figure 5 the form of the first bank layer 161 shown in Figure 5 and the second bank material layer 163L may be formed into

[0192] Next, referring to Figure 15, the method may include forming a first light-emitting element ED1 by depositing a first light-emitting layer EL1 and a first cathode electrode CE1 on a first anode electrode AE1, and the method may include then depositing a first cover layer CPL1. In the display device 10 according to an embodiment, since the third bank layer 165 includes a tip TIP, the first light-emitting layer EL1, the first cathode electrode CE1, and the first cover layer CPL1 may be formed on the first anode electrode AE1 through a deposition process and a photolithography process without a separate fine metal mask.

[0193] The method may include forming a first light-emitting layer EL1 according to an embodiment through a thermal deposition process. The deposition process of forming the first light-emitting layer EL1 according to an embodiment may be performed at an angle of 45° to 50° with respect to the upper surface of the first anode electrode AE1. Accordingly, the first light-emitting layer EL1 may be formed on the pixel defining layer 151 and an auxiliary electrode AX (e.g., according to a plan view) hidden under the tip of the third bank layer 165. However, the first light-emitting layer EL1 according to an embodiment may not be deposited on a portion overlapping with a cavity formed between the first bank layer 161 and the second bank layer 163.

[0194] The method may include forming a first cathode electrode CE1 according to an embodiment through a thermal deposition process or a sputtering deposition process. In an example in which the first cathode electrode CE1 according to an embodiment is formed through a thermal deposition process, the deposition process of forming the first cathode electrode CE1 may be performed at an angle of 30° or less with respect to the upper surface of the first anode electrode AE1. In other words, compared with the deposition process of forming the first light-emitting layer EL1, the deposition process of forming the first cathode electrode CE1 may be performed such that the first cathode electrode CE1 is formed to be inclined in a relatively more horizontal direction. That is, the deposition process of forming the first cathode electrode CE1 may have a higher step coverage than the deposition process of forming the first light-emitting layer EL1. Accordingly, the first cathode electrode CE1 may completely cover the first light-emitting layer EL1. In some aspects, the method may include forming a first cathode electrode CE1 according to an embodiment through a sputtering deposition process, and the sputtering deposition process of forming the first cathode electrode CE1 may have a higher step coverage characteristic than the thermal deposition process.

[0195] The method may further include depositing a first cathode electrode CE1 according to an embodiment on a portion overlapping with a cavity formed between the first bank layer 161 and the second bank layer 163 in addition to the upper surface of the first light-emitting layer EL1. The first cathode electrode CE1 according to an embodiment may be in contact with the auxiliary electrode AX at a portion overlapping with the cavity.

[0196] The method may include partially depositing a material for forming a first cathode electrode CE1 according to an embodiment on a side surface of the second bank layer 163, which may be Figure 5The first residual electrode pattern CP1 shown in []. The first residual electrode pattern CP1 may be formed such that the first residual electrode pattern CP1 is spaced apart from the first cathode electrode CE1.

[0197] The method may include forming a first capping layer CPL1 according to an embodiment by a thermal deposition process, and the first capping layer CPL1 may have a lower step coverage characteristic than the first cathode electrode CE1. Thus, the first capping layer CPL1 according to an embodiment may not be deposited on a portion overlapping with the cavity formed between the first bank layer 161 and the second bank layer 163.

[0198] In some aspects, the first light-emitting layer EL1, the first cathode electrode CE1, and the first capping layer CPL1 according to an embodiment may be deposited on the first anode electrode AE1, and may also be deposited on the third bank layer 165, the second anode electrode AE2, and the third anode electrode AE3. Since the third bank layer 165 includes a tip TIP, the first light-emitting layer EL1, the first cathode electrode CE1, and the first capping layer CPL1 deposited on the third bank layer 165 may be spaced apart from the first light-emitting layer EL1, the first cathode electrode CE1, and the first capping layer CPL1 deposited on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3.

[0199] Next, referring to Figure 16 , the method may include forming a first encapsulation material layer 171L such that the first encapsulation material layer 171L is completely formed on the first capping layer CPL1 and the first cathode electrode CE1. The method may include forming the first encapsulation material layer 171L by a chemical vapor deposition (CVD) process, and the first encapsulation material layer 171L may form a uniform film regardless of the steps of the underlying structure. As an example, the first encapsulation material layer 171L may cover the steps formed by the first light-emitting element ED1, may cover the undercut portion formed between the tip TIP of the second bank layer 163 and the third bank layer 165, and may be deposited such that the first encapsulation material layer 171L overlaps with the cavity formed between the first bank layer 161 and the second bank layer 163. In some aspects, the first encapsulation material layer 171L may completely cover the first capping layer CPL1 provided on the third bank layer 165.

[0200] Next, referring to Figure 17 and Figure 18 , after forming a hard mask on the first light-emitting element ED1 and the overlapping portion around the first light-emitting element ED1, the method may include performing a third etching process to remove the portions where the hard mask is not formed. In this process, the third etching process may remove all of the first light-emitting layer EL1, the first cathode electrode CE1, the first capping layer CPL1, and the first encapsulation material layer 171L in the portions where the hard mask is not formed. The hard mask used in this process may be indium gallium zinc oxide (IGZO).

[0201] In this process, the method may include forming a first encapsulation material layer 171L in the form of Figure 5 the first inorganic layer 171-1 shown in, and the method may include forming a first light-emitting layer EL1, a first cathode electrode CE1, and a first cover layer CPL1 deposited on the third bank layer 165 in the form of Figure 5 the first organic pattern ELP1, the first electrode pattern CEP1, and the first cover pattern CLP1 shown in.

[0202] In this process, the method may include re-exposing the second anode electrode AE2 and the pixel defining layer 151 disposed around the second anode electrode AE2, and forming a hole HOL in a portion overlapping with the second anode electrode AE2. In some aspects, the method may include re-exposing the third anode electrode AE3 and the pixel defining layer 151 disposed around the third anode electrode AE3, and forming a hole HOL in a portion overlapping with the third anode electrode AE3.

[0203] Next, referring to Figure 19 , the method may include forming a second light-emitting element ED2 by repeating the above process. Specifically, the method may include depositing a second light-emitting layer EL2, a second cathode electrode CE2, a second cover layer CPL2, and a first encapsulation material layer 171L such that the second light-emitting layer EL2, the second cathode electrode CE2, the second cover layer CPL2, and the first encapsulation material layer 171L are all deposited on the second anode electrode AE2. In this process, the method may include forming the second light-emitting layer EL2, the second cathode electrode CE2, the second cover layer CPL2, and the first encapsulation material layer 171L on the second anode electrode AE2 and on the first inorganic layer 171-1, the third anode electrode AE3, and the third bank layer 165 overlapping with the first anode electrode AE1. Other redundant descriptions will be omitted.

[0204] Next, the method may include forming a hard mask on the second light-emitting element ED2 and on an overlapping portion around the second light-emitting element ED2, and the method may include partially etching a portion where the hard mask is not formed. The etching process of this process may be the same as the third etching process.

[0205] Referring to Figure 20 In this process, the method may include forming the first encapsulation material layer 171L in the form of Figure 5 the second inorganic layer 171-2 shown in. The first inorganic layer 171-1 and the second inorganic layer 171-2 may be spaced apart from each other in a first direction (X-axis direction) on the third bank layer 165. In some aspects, the method may include forming the second light-emitting layer EL2, the second cathode electrode CE2, and the second cover layer CPL2 deposited on the third bank layer 165 in the form of Figure 5The forms of the second organic pattern ELP2, the second electrode pattern CEP2, and the second cover pattern CLP2 shown in []. The second organic pattern ELP2, the second electrode pattern CEP2, and the second cover pattern CLP2 may be spaced apart from the first organic pattern ELP1, the first electrode pattern CEP1, and the first cover pattern CLP1 in a first direction (X-axis direction) on the third bank layer 165.

[0206] In this process, the method may include exposing a pixel defining layer 151 of a third anode electrode AE3 and a portion overlapping with the third anode electrode AE3, and forming a hole HOL in the portion overlapping with the third anode electrode AE3. Next, the method may include forming a third light-emitting element ED3 by repeating the above process. Repeated descriptions will be omitted.

[0207] Referring to Figure 21 , by the above process, the first encapsulation material layer 171L may be formed into Figure 5 the form of the third inorganic layer 171-3 shown in []. The second inorganic layer 171-2 and the third inorganic layer 171-3 may be spaced apart from each other in a first direction (X-axis direction) on the third bank layer 165.

[0208] In this process, the method may include forming a third light-emitting layer EL3, a third cathode electrode CE3, and a third cover layer CPL3 deposited on the third bank layer 165 into Figure 5 the forms of the third organic pattern ELP3, the third electrode pattern CEP3, and the third cover pattern CLP3 shown in []. The third organic pattern ELP3, the third electrode pattern CEP3, and the third cover pattern CLP3 may be spaced apart from the second organic pattern ELP2, the second electrode pattern CEP2, and the second cover pattern CLP2 in a first direction (X-axis direction) on the third bank layer 165.

[0209] Next, the method may include forming a second encapsulation layer 173 to planarize the steps included in the first encapsulation layer 171, and then forming a third encapsulation layer 175. Thus, a Figure 5 display element layer 150 and a thin film encapsulation layer 170 shown in [] may be formed.

[0210] In the display device 10 according to the embodiment, since the third bank layer 165 includes tips, the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 spaced apart from each other can be formed without a separate fine metal mask. And since the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 overlap with the cavity formed between the first bank layer 161 and the second bank layer 163 and are in contact with the auxiliary electrode AX, the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 spaced apart from each other can be electrically connected. In some aspects, in the display device 10 according to the embodiment, since a high adhesiveness is formed between the second bank layer 163 and the first encapsulation layer 171, the faulty detachment of the second bank layer 163 and the first encapsulation layer 171 can be solved, and the moisture penetration defect caused by external air due to the faulty detachment can be solved.

[0211] Each exemplary aspect supported by the present disclosure should not be construed as limited to the embodiments set forth herein. On the contrary, the exemplary embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0212] Although the various exemplary aspects supported by the present disclosure have been specifically shown and described with reference to the embodiments of the present disclosure, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit or scope of the exemplary embodiments of the present disclosure defined by the appended claims.

Claims

1. A display device, comprising: A substrate, the substrate comprising a light-emitting area and a non-light-emitting area; a first anode electrode, the first anode electrode being positioned on the light emitting region of the substrate; an auxiliary electrode, the auxiliary electrode being positioned on the non-light emitting region of the substrate and spaced apart from the first anode electrode; a pixel defining layer, the pixel defining layer being positioned on the first anode electrode and the auxiliary electrode and defining a first opening; a first light-emitting layer, the first light-emitting layer being positioned on the first anode electrode and completely covering the pixel defining layer; a first cathode electrode, the first cathode electrode being positioned on the first light emitting layer; a bank structure positioned on the auxiliary electrode and defining a second opening, the bank structure comprising a first bank layer, a second bank layer, and a third bank layer sequentially stacked; as well as a first encapsulation layer, the first encapsulation layer being positioned on the bank structure, in, forming a cavity between the second bank layer and a first side surface of the first bank layer facing the light emitting region in a region overlapping the non-light emitting region, The first cathode electrode is in contact with the auxiliary electrode in a region overlapping the cavity, and The first light emitting layer does not overlap the cavity.

2. The display device according to claim 1, wherein: The second bank layer includes a second side surface facing the light emitting region, and The second side surface protrudes toward the light emitting region more than the first side surface of the first bank layer.

3. The display device according to claim 2, wherein: The third bank layer includes a tip protruding toward the light emitting region from the second side surface of the second bank layer, and The tip of the protrusion of the third bank and the second side surface form an undercut portion.

4. The display device according to claim 1, wherein: A width of the cavity in a direction parallel to the substrate is greater than twice a height of the first bank layer.

5. The display device according to claim 4, wherein: A height of the second bank layer is greater than twice the height of the first bank layer.

6. The display device according to claim 5, wherein: The height of the first bank layer is in a range of 500 angstroms to 2000 angstroms.

7. The display device according to claim 1, wherein: A material included in the first bank layer, a material included in the second bank layer, and a material included in the third bank layer are different from each other.

8. The display device according to claim 7, wherein: The first bank layer includes at least one of silicon nitride and aluminum, and The second bank layer includes silicon oxide.

9. The display device according to claim 1, further comprising: A residual electrode pattern is positioned on a second side surface of the second bank layer facing the light emitting region, wherein the residual electrode pattern includes the same material as that of the first cathode electrode and is spaced apart from the first cathode electrode.

10. The display device according to claim 9, wherein: The second side surface includes a first portion in contact with the residual electrode pattern and a second portion in contact with the first encapsulation layer, and The second side surface is completely covered by the first portion and the second portion.

11. The display device according to claim 10, wherein: An area of ​​the second portion is greater than an area of ​​the first portion.

12. The display device according to claim 1, wherein: The first encapsulation layer contacts the first cathode electrode at a portion of the first cathode electrode overlapping the cavity.

13. The display device according to claim 9, further comprising: an organic pattern positioned on the third bank layer, wherein the organic pattern includes a same material as that of the first light emitting layer and is spaced apart from the first light emitting layer; and an electrode pattern positioned on the organic pattern, wherein the electrode pattern includes the same material as that of the first cathode electrode and is spaced apart from the first cathode electrode, Wherein, the electrode pattern and the residual electrode pattern include the same material.

14. The display device according to claim 13, wherein: The first encapsulation layer contacts the organic pattern and the electrode pattern.

15. The display device according to claim 1, wherein: In a plan view, the pixel defining layer is completely covered by the first light emitting layer, and In the plan view, the second opening completely surrounds the first opening.

16. The display device according to claim 1, further comprising: a second anode electrode, the second anode electrode being spaced apart from the first anode electrode, and the auxiliary electrode being interposed between the first anode electrode and the second anode electrode; a second light-emitting layer, wherein the second light-emitting layer is located on the second anode electrode; as well as a second cathode electrode, the second cathode electrode being located on the second light-emitting layer, in, The auxiliary electrode includes a first side surface facing the bank structure, The first side surface of the auxiliary electrode includes a first portion in contact with the first cathode electrode, a second portion in contact with the second cathode electrode, and a third portion in contact with the first bank layer, and The first portion does not overlap with the first light emitting layer, and the second portion does not overlap with the second light emitting layer.

17. The display device according to claim 16, wherein: The first portion and the second portion are spaced apart from each other, the third portion is interposed between the first portion and the second portion, and The first cathode electrode and the second cathode electrode are electrically connected through the auxiliary electrode.

18. The display device according to claim 17, wherein: The first encapsulation layer includes a first inorganic layer on the first cathode electrode and a second inorganic layer on the second cathode electrode, and In a direction perpendicular to the substrate, the first inorganic layer overlaps the first portion, and the second inorganic layer overlaps the second portion.

19. The display device according to claim 18, wherein: Each of the first inorganic layer and the second inorganic layer is in contact with the second bank layer and the third bank layer, and The first inorganic layer and the second inorganic layer are spaced apart from each other in a region overlapping the non-light emitting region.

20. A method for manufacturing a display device, the method comprising: forming a substrate including a light-emitting region and a non-light-emitting region, an anode electrode located on the light-emitting region of the substrate, and an auxiliary electrode located on the non-light-emitting region of the substrate; forming a pixel defining layer between the anode electrode and the auxiliary electrode; forming a first bank material layer, a second bank material layer and a third bank material layer that completely cover the anode electrode, the auxiliary electrode and the pixel defining layer; forming a photoresist exposing the anode electrode and an overlapping portion around the anode electrode; performing a first etching process, wherein the first etching process removes the first bank material layer, the second bank material layer, and the third bank material layer in a portion where the photoresist is not formed, forms a hole in a portion overlapping the anode electrode, and forms the third bank material layer into a third bank layer; performing a second etching process, wherein the second etching process forms a first bank layer and a second bank layer by partially etching inner sides of the first bank material layer and the second bank material layer in a portion overlapping the hole so that a side surface of the second bank material layer protrudes toward the hole more than a side surface of the first bank material layer and the third bank layer has a tip protruding toward the hole more than the side surface of the second bank material layer; and An organic pattern, an electrode pattern, and a first inorganic layer positioned on the third bank layer and the light emitting element are formed by the following steps: forming a light emitting layer, a cathode electrode and a first encapsulation layer on the anode electrode and the third bank layer, forming a hard mask on the anode electrode and an overlapping portion around the anode electrode, and performing an etching process to remove the light emitting layer, the cathode electrode, and the first encapsulation layer located in a portion where the hard mask is not formed, in, forming the first bank layer and the second bank layer to form a cavity between a side surface of the first bank layer facing the light emitting region and the second bank layer, and The cathode electrode contacts the auxiliary electrode in a portion overlapping the cavity.

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