Display device

Abstract

The display device comprises a display area and a non-display area; a sub-pixel disposed in the display area; and a metal line intersecting the non-display area and the display area, and spaced apart from an emission area of the sub-pixel on a plane in the display area, and to which a voltage including a plurality of pulses is applied, and the voltage increases a step voltage value for each of the plurality of pulses.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10-2023-0191541, filed with the Korean Intellectual Property Office on December 26, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] With the development of information technology, the importance of display devices as a connection medium between users and information is emerging. In response thereto, the use of display devices such as liquid crystal display devices and organic light emitting display devices is increasing.

[0005] A display device uses pixels to display an image. To implement augmented reality (AR), virtual reality (VR), and mixed reality (MR), more pixels need to be provided on a small display screen in the display device.

[0006] As the distance between pixels becomes narrow, leakage current through a common layer of adjacent pixels may become a problem.

[0007] It should be understood that this background art section is intended to provide useful background for understanding the technology in part. However, this background art section may also include concepts, ideas, or understandings that are not part of what was known or learned by a person of ordinary skill in the relevant art prior to the effective filing date of the subject matter disclosed herein. Summary of the Invention

[0008] The technical object to be solved is to provide a display device and a wearable device capable of preventing leakage current through a common layer between adjacent pixels.

[0009] According to an embodiment of the present disclosure, a display device may include: a display area and a non-display area; sub-pixels disposed in the display area; and a metal line intersecting the non-display area and the display area, and the metal line is spaced apart from an emission area of the sub-pixels in a plane in the display area; and a voltage including a plurality of pulses is applied to the metal line, and the voltage increases a step voltage value for each of the plurality of pulses.

[0010] In an embodiment, pulse amplitudes of the plurality of pulses may be equal to each other.

[0011] In an embodiment, the display device may further include: a first metal pad disposed in the non-display area, and the first metal pad is electrically connected to an end of the metal wire; and a second metal pad disposed in the non-display area, and the first metal pad is electrically connected to the other end of the metal wire, the display area is disposed between the first metal pad and the second metal pad, and a voltage including the plurality of pulses is applied to the metal wire through the first metal pad.

[0012] In an embodiment, the metal wire may be disposed on a pixel defining layer in the display area, and the pixel defining layer defines an emission area of the sub-pixels.

[0013] In an embodiment, the metal wire may be in electrical contact with a cathode of a light-emitting element of the sub-pixel.

[0014] According to an embodiment of the present disclosure, a display device may include: a display area and a non-display area; a plurality of sub-pixels disposed in the display area; and a first sub-metal wire and a second sub-metal wire intersecting the non-display area and the display area, and the first sub-metal wire and the second sub-metal wire are spaced apart in a plane from a plurality of emission areas of the plurality of sub-pixels in the display area, wherein the first sub-metal wire and the second sub-metal wire are disposed on a substrate in a vertical direction.

[0015] In an embodiment, the first sub-metal wire may be disposed on a pixel defining layer in the display area, the pixel defining layer defines the plurality of emission areas of the plurality of sub-pixels, and the second sub-metal wire is disposed inside the pixel defining layer.

[0016] In an embodiment, the display device may further include: a pixel circuit layer disposed on the substrate, and the pixel circuit layer includes a sub-pixel circuit of each of the plurality of sub-pixels; a via layer disposed on the pixel circuit layer; and a light-emitting element layer disposed on the via layer, and the light-emitting element layer includes the pixel defining layer, wherein the second sub-metal wire contacts an upper surface of the via layer.

[0017] In an embodiment, the display device may further include: a pixel circuit layer disposed on the substrate, the pixel circuit layer includes a sub-pixel circuit of each of the plurality of sub-pixels; a via layer disposed on the pixel circuit layer; and a light-emitting element layer disposed on the via layer, the light-emitting element layer includes the pixel defining layer, wherein the second sub-metal wire is spaced apart from the via layer, and the second sub-metal wire is disposed inside the pixel defining layer.

[0018] In an embodiment, the second sub-metal wire may be formed of a plurality of wires.

[0019] In an embodiment, the display device may further include: a first metal pad disposed in the non-display area, and the first metal pad is electrically connected to ends of the first sub-metal line and the second sub-metal line; and a second metal pad disposed in the non-display area, and the second metal pad is electrically connected to the other ends of the first sub-metal line and the second sub-metal line, and the display area is disposed between the first metal pad and the second metal pad.

[0020] In an embodiment, the first metal pad may further include a first sub-metal pad and a second sub-metal pad, the end of the first sub-metal line is electrically connected to the first sub-metal pad, the end of the second sub-metal line is electrically connected to the second sub-metal pad, and separate voltages are applied to the first sub-metal pad and the second sub-metal pad.

[0021] In an embodiment, a voltage including a plurality of pulses may be applied to the first metal pad, and the voltage increases a step voltage value for each of the plurality of pulses, and a voltage including a single pulse is applied to the second metal pad.

[0022] In an embodiment, the first sub-metal line may be in electrical contact with a cathode of a light-emitting element of the sub-pixel.

[0023] The display device may be a head-mounted display device.

[0024] The display device and the wearable device according to the present disclosure can prevent leakage current from passing through a common layer between adjacent pixels and prevent damage to the adjacent pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] By describing embodiments of the present disclosure in more detail with reference to the accompanying drawings, the above and other features of the present disclosure will become more apparent. In the drawings:

[0026] Figure 1 is a block diagram showing an embodiment of a display device;

[0027] Figure 2 is showing Figure 1 a block diagram of an embodiment of any one of the sub-pixels of

[0028] Figure 3 is showing Figure 1 a schematic plan view of an embodiment of a display panel of

[0029] Figure 4 is showing Figure 3 an exploded perspective view of a part of a display panel of

[0030] Figure 5 is a schematic plan view showing the relationship between sub-pixels and metal lines;

[0031] Figure 6 is a schematic cross-sectional view showing an embodiment of a light-emitting structure;

[0032] Figure 7 is a schematic cross-sectional view showing an embodiment of a light-emitting structure;

[0033] Figure 8 is along Figure 5 a schematic cross-sectional view taken along line I-I';

[0034] Figure 9 is a diagram showing the voltage applied to the first metal pad;

[0035] Figure 10 is showing Figure 1 a schematic plan view of an embodiment of a display panel of;

[0036] Figure 11 is a schematic plan view showing the relationship between sub-pixels and metal lines;

[0037] Figure 12 and Figure 13 is along Figure 11 a schematic cross-sectional view taken along line II-II';

[0038] Figure 14 is showing Figure 1 a schematic plan view of an embodiment of a display panel of;

[0039] Figure 15 is a block diagram showing an embodiment of a display system;

[0040] Figure 16 is showing Figure 15 a schematic perspective view of an application example of a display system of; and

[0041] Figure 17 is showing Figure 16 a diagram of a head-mounted display device worn by a user of; Detailed Description of the Invention

[0042] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily implement the present disclosure. The present disclosure can be implemented in various different forms and is not limited to the embodiments described herein.

[0043] To clearly describe the present disclosure, parts irrelevant to the description are omitted, and throughout the specification, the same or similar elements are denoted by the same reference numerals. Therefore, the above reference numerals can be used in other drawings.

[0044] In addition, the dimensions and thicknesses of each component shown in the drawings are arbitrarily shown for convenience of description, and thus the present disclosure is not necessarily limited to those shown in the drawings. In the drawings, the thickness may be exaggerated to clearly express different layers and regions.

[0045] Unless the context clearly indicates otherwise, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms.

[0046] In the specification and claims, for purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in the conjunctive or disjunctive sense and can be understood to be equivalent to "and / or".

[0047] In the specification and claims, for purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0048] It should be understood that although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0049] The term "overlap (overlap or overlapped)" means that the first object can be above or below or on one side of the second object, and vice versa. In addition, the term "overlap" can include laminating, stacking, facing or facing, extending above..., covering, or partially covering, or any other suitable term that those of ordinary skill in the art will recognize and understand.

[0050] The terms "facing" and "facing" mean that the first element can be directly or indirectly opposite to the second element. In the case where a third element is between the first element and the second element, the first element and the second element can be understood to be indirectly opposite to each other, although still facing each other.

[0051] When an element is described as "not overlapping" another element or "not" "overlapping" another element, this can include these elements being spaced apart from each other, offset from each other, or separated from each other, or any other suitable term that those of ordinary skill in the art can understand.

[0052] As used in this specification, the terms "comprises" and / or "comprising", "includes" and / or "including", "has", "have" and / or "having", and variations thereof specify the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0053] Taking into account the measured values being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximate" as used herein includes the stated value and means within an acceptable deviation of the particular value as determined by a person of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0054] Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0055] It should be understood that when an element (or region, layer, or portion, etc.) is referred to in the specification as being "on", "connected to", or "coupled to" another element, the element can be directly disposed on, directly connected to, or directly coupled to the other element, or intervening elements can be disposed between the element and the other element.

[0056] It should be understood that the terms "connected to" or "coupled to" can include a physical connection or an electrical connection, or a physical coupling or an electrical coupling.

[0057] Embodiments may be described and illustrated in terms of functional blocks, units, and / or modules in the figures.

[0058] Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and wiring connections, etc., and these blocks, units, and / or modules can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques.

[0059] In cases where blocks, units, and / or modules are implemented by a microprocessor or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software.

[0060] It is also contemplated that each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) performing other functions.

[0061] Without departing from the scope of the present disclosure, each block, unit, and / or module of an embodiment can be physically divided into two or more interacting and discrete blocks, units, and / or modules.

[0062] Furthermore, without departing from the scope of the present disclosure, the blocks, units, and / or modules of an embodiment can be physically combined into more complex blocks, units, and / or modules.

[0063] In addition, the expression "…… is the same" in the description can mean "…… is substantially the same". For example, the expression "…… is the same" can be the same enough for a person of ordinary skill in the art to understand that it is the same. Other expressions can also be expressions that omit "substantially".

[0064] Figure 1 is a block diagram showing an embodiment of a display device.

[0065] Referring to Figure 1 , the display device 100 can include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0066] The display panel 110 can include sub-pixels SP. The sub-pixels SP can be connected to the gate driver 120 through the first gate line GL1 to the m-th gate line GLm. The sub-pixels SP can be connected to the data driver 130 through the first data line DL1 to the n-th data line DLn. m is an integer greater than 0, and n is an integer greater than 0.

[0067] Each of the sub-pixels SP can include at least one light-emitting element formed to generate light. Thus, each of the sub-pixels SP can generate light of a given color (such as red, green, blue, cyan, magenta, or yellow). Two or more of the sub-pixels SP can form a pixel PXL. For example, as Figure 1 shown in, three sub-pixels SP can form a pixel PXL.

[0068] The gate driver 120 is connected to sub-pixels SP arranged or disposed in the row direction through the first gate line GL1 to the m-th gate line GLm. The gate driver 120 may output gate signals to the first gate line GL1 to the m-th gate line GLm in response to a gate control signal GCS. In an embodiment, within the spirit and scope of the present disclosure, the gate control signal GCS may include a start signal indicating the start of each frame and a horizontal synchronization signal for outputting gate signals synchronously with the timing at which data signals are applied, etc.

[0069] The gate driver 120 may be disposed on one side or a side portion of the display panel 110. However, the embodiment is not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically separated drivers, and such drivers may be disposed on one side or a side portion of the display panel 110 and on the other side opposite to the one side or the side portion of the display panel 110. As described above, according to an embodiment, the gate driver 120 may be disposed around the display panel 110 in various shapes.

[0070] The data driver 130 is connected to sub-pixels SP arranged or disposed in the column direction through the first data line DL1 to the n-th data line DLn. The data driver 130 receives image data DATA and a data control signal DCS from the controller 150. The data driver 130 operates in response to the data control signal DCS. In an embodiment, within the spirit and scope of the present disclosure, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, etc.

[0071] The data driver 130 may use a voltage from the voltage generator 140 to apply data signals having gray-scale voltages corresponding to the image data DATA to the first data line DL1 to the n-th data line DLn. In the case where gate signals are applied to each of the first gate line GL1 to the m-th gate line GLm, data signals corresponding to the image data DATA may be applied to the data lines DL1 to DLm. Accordingly, the corresponding sub-pixels SP may generate light corresponding to the data signals. Thus, an image is displayed on the display panel 110.

[0072] In an embodiment, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0073] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 is configured to generate a voltage and supply the generated voltage to components of the display device 100. For example, the voltage generator 140 may be configured to generate a voltage by receiving an input voltage from outside the display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0074] The voltage generator 140 may generate a first power voltage VDD and a second power voltage VSS, and the generated first power voltage VDD and second power voltage VSS may be provided to the sub-pixel SP. The first power voltage VDD may have a relatively high voltage level, and the second power voltage VSS may have a voltage level lower than the voltage level of the first power voltage VDD. In other embodiments, the first power voltage VDD or the second power voltage VSS may be provided by an external device of the display device 100.

[0075] The voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage applied to the sub-pixel SP. For example, during a sensing operation for sensing the electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a selectable reference voltage may be applied to the first data line DL1 to the nth data line DLn, and the voltage generator 140 may generate such a reference voltage.

[0076] The controller 150 controls the overall operation of the display device 100. The controller 150 receives input image data IMG and a control signal CTRL for controlling the display of the input image data IMG from the outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0077] The controller 150 may convert the input image data IMG such that the input image data IMG is suitable for the display device 100 or the display panel 110, and output image data DATA. In an embodiment, the controller 150 may output the image data DATA by aligning the input image data IMG such that the input image data IMG is suitable for the settings of the sub-pixel SP.

[0078] Two or more components of the data driver 130, the voltage generator 140, and the controller 150 may be mounted on one integrated circuit. As Figure 1 shown, the data driver 130, the voltage generator 140, and the controller 150 may be included in the driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140, and the controller 150 may be components functionally divided in one driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a component different from the driver integrated circuit DIC.

[0079] According to an embodiment, the display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is formed to sense the temperature around the temperature sensor 160 and generate temperature data TEP indicating the sensed temperature. In an embodiment, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0080] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In an embodiment, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may control the data signal and the first power voltage VDD and the second power voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0081] Figure 2 is a block diagram showing Figure 1 an embodiment of any one of the sub-pixels in. In Figure 2 among them, in Figure 1 the sub-pixel SP of, the sub-pixel SPij arranged or set in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) is shown as an example.

[0082] Referring to Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD.

[0083] The light-emitting element LD is connected between the first power voltage node VDDN and the second power voltage node VSSN. At this time, the first power voltage node VDDN is a node for transmitting Figure 1 the first power voltage VDD of, and the second power voltage node VSSN is a node for transmitting Figure 1 the second power voltage VSS of.

[0084] The anode electrode AE of the light-emitting element LD may be connected to the first power voltage node VDDN through the sub-pixel circuit SPC, and the cathode electrode CE of the light-emitting element LD may be connected to the second power voltage node VSSN. For example, the anode electrode AE of the light-emitting element LD may be connected to the first power voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0085] The sub-pixel circuit SPC may be connected to Figure 1 the i-th gate line GLi among the first gate lines GL1 to the m-th gate line GLm of, Figure 1 the i-th emission control line ELi among the first emission control lines EL1 to the m-th emission control lines ELm of, and Figure 1The j-th data line DLj among the first data line DL1 to the n-th data line DLn. The sub-pixel circuit SPC is formed to control the light-emitting element LD according to the signals received through such signal lines.

[0086] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. In an embodiment, as Figure 2 shown, the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC may operate in response to the gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. As described above, in the case where the i-th gate line GLi may include two or more sub-gate lines, the sub-pixel circuit SPC may operate in response to the gate signals received through the corresponding sub-gate lines.

[0087] The sub-pixel circuit SPC may operate in response to an emission control signal received through the i-th emission control line ELi. In an embodiment, the i-th emission control line ELi may include one or more sub-emission control lines. In the case where the i-th emission control line ELi may include two or more sub-emission control lines, the sub-pixel circuit SPC may operate in response to the emission control signals received through the corresponding sub-emission control lines.

[0088] The sub-pixel circuit SPC may receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC may store a voltage corresponding to the data signal in response to at least one of the gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. In response to the emission control signal received through the i-th emission control line ELi, the sub-pixel circuit SPC may adjust the current flowing from the first power voltage node VDDN through the light-emitting element LD to the second power voltage node VSSN according to the stored voltage. Accordingly, the light-emitting element LD may generate light having a brightness corresponding to the data signal.

[0089] Figure 3 is a schematic plan view showing an embodiment of a Figure 1 display panel.

[0090] Referring to Figure 3 and also referring to Figure 1 , Figure 1 An embodiment of the display panel 110 (i.e., the display panel DP) may include a display area DA and a non-display area NDA. The display panel DP displays an image through the display area DA. The non-display area NDA is disposed around the display area DA.

[0091] The display panel DP may include a substrate SUB, sub-pixels SP, a first metal pad JPD1, a second metal pad JPD2, metal lines JHL1 to JHLo, and a pad PD.

[0092] When the display panel DP is used as a display screen of a head-mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, etc., the display panel DP may be located very close to the user's eyes. In this case, sub-pixels SP with relatively high integration are required. To increase the integration of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP and / or the display panel DP may be formed on the substrate SUB which is a silicon substrate. The display device 100 (refer to Figure 1 ) including the display panel DP formed on the substrate SUB which is a silicon substrate may be referred to as an organic light-emitting diode (OLED) on silicon (OLEDoS) display device.

[0093] The sub-pixels SP are located in the display area DA on the substrate SUB. The sub-pixels SP may be arranged or disposed in a matrix shape along a first direction DR1 and a second direction DR2 that intersects or crosses the first direction DR1. However, the embodiments are not limited thereto. For example, the sub-pixels SP may be arranged or disposed in a zigzag shape along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged or disposed in a shape. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction. Two or more of the sub-pixels SP may form a pixel PXL.

[0094] The substrate SUB may include a display area DA and a non-display area NDA. Components for controlling the sub-pixels SP may be disposed on the substrate SUB in the non-display area NDA. For example, lines connected to the sub-pixels SP (such as Figure 1 the first gate line GL1 to the m-th gate line GLm and the first data line DL1 to the n-th data line DLn) may be disposed in the non-display area NDA in a space-efficient manner.

[0095] The first metal pad JPD1 can be located in the non-display area NDA. The first metal pad JPD1 can have a substantially rectangular shape in which the long side extends in the second direction DR2 and the short side extends in the first direction DR1. The length of the long side can be similar to the length of the second direction DR2 of the display area DA. The first metal pad JPD1 can include at least one metal material. For example, the first metal pad JPD1 can include a material having a high resistivity or a high melting point, such as molybdenum (Mo), titanium (Ti), or titanium nitride (TiN). The first metal pad JPD1 can be located in a direction opposite to the first direction DR1 from the display area DA. In an embodiment, a voltage can be applied to the metal lines JHL1 to JHLo through the first metal pad JPD1.

[0096] The second metal pad JPD2 can be located in the non-display area NDA and can be located in the first direction DR1 from the first metal pad JPD1. The second metal pad JPD2 can have a substantially rectangular shape in which the long side extends in the second direction DR2 and the short side extends in the first direction DR1. The length of the long side can be similar to the length of the second direction DR2 of the display area DA. The second metal pad JPD2 can include at least one metal material. For example, the second metal pad JPD2 can include a material having a high resistivity or a high melting point, such as molybdenum (Mo), titanium (Ti), or titanium nitride (TiN). The second metal pad JPD2 can be located in the first direction DR1 from the display area DA. For example, the display area DA can be located between the first metal pad JPD1 and the second metal pad JPD2.

[0097] The metal lines JHL1 to JHLo can cross the non-display area NDA and the display area DA and can extend without overlapping the light-emitting area of the sub-pixels SP in the display area DA. For example, the metal lines JHL1 to JHLo can extend to be spaced apart from the emission area of the sub-pixels SP in the plane in the display area DA. o can be an integer greater than 1.

[0098] The metal lines JHL1 to JHLo can connect the first metal pad JPD1 and the second metal pad JPD2. The metal lines JHL1 to JHLo can be arranged or disposed parallel to each other in the second direction DR2. One end of the metal lines JHL1 to JHLo can be connected to the first metal pad JPD1, and the other end of the metal lines JHL1 to JHLo can be connected to the second metal pad JPD2. For example, the metal lines JHL1 to JHLo can include a material having a high resistivity or a high melting point, such as molybdenum (Mo), titanium (Ti), and titanium nitride (TiN).

[0099] The first metal pad JPD1, the second metal pad JPD2, and the metal wires JHL1 to JHLo can be integrally formed using the same material and process.

[0100] When an electric voltage is applied to the first metal pad JPD1, heat generated due to Joule heating may occur in the metal wires JHL1 to JHLo. The electric voltage can be a single pulse or can include pulses. Due to the heat generation, the organic material adjacent to the metal wires JHL1 to JHLo can be sublimated. Accordingly, during the operation of the display device 100, leakage current through the organic material can be prevented. In an embodiment, the display device 100 can separately include a voltage generator (not shown) that applies an electric voltage to the first metal pad JPD1.

[0101] To reach the temperature at which the organic material adjacent to the metal wires JHL1 to JHLo is sublimated, the voltage applied to the first metal pad JPD1 may need to be at a high voltage level. However, when a voltage having a high voltage level is applied to the first metal pad JPD1, damage may occur in the sub-pixels SP adjacent to the metal wires JHL1 to JHLo.

[0102] Therefore, a method may be needed to reach the temperature at which the organic material adjacent to the metal wires JHL1 to JHLo is sublimated without damaging the sub-pixels SP adjacent to the metal wires JHL1 to JHLo. A more detailed description of this is provided together with Figure 9 and Figure 10 provides a more detailed description thereof.

[0103] The virtual first cutting line SCL1 can extend in the second direction DR2 between the first metal pad JPD1 and the display area DA. The first cutting line SCL1 can cross the metal wires JHL1 to JHLo. The virtual second cutting line SCL2 can extend in the second direction DR2 between the second metal pad JPD2 and the display area DA. The second cutting line SCL2 can cross the metal wires JHL1 to JHLo.

[0104] After the Joule heating process, when the display panel DP is cut along the cutting lines SCL1 and SCL2, the first metal pad JPD1 and the second metal pad JPD2 may not be present in the final product. In an embodiment, by not cutting the display panel DP along the cutting lines SCL1 and SCL2, the first metal pad JPD1 and the second metal pad JPD2 can be present in the final product.

[0105] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 of Figure 1The gate driver 120 can be mounted on the display panel DP and can be disposed in the non-display area NDA. In other embodiments, the gate driver 120 can be implemented as an integrated circuit separate from the display panel DP. In an embodiment, the temperature sensor 160 can be disposed in the non-display area NDA to sense the temperature of the display panel DP.

[0106] The pad PD is disposed in the non-display area NDA on the substrate SUB. At least a portion of the pad PD can be electrically connected to the sub-pixel SP through a line. For example, a portion of the pad PD can be connected to the sub-pixel SP through the first data line DL1 to the nth data line DLn.

[0107] The pad PD can connect the display panel DP to other components of the display device 100 (refer to Figure 1 ). In an embodiment, the voltages and signals required for the operation of the components included in the display panel DP can be provided from Figure 1 the driver integrated circuit DIC. For example, the first data line DL1 to the nth data line DLn can be connected to the driver integrated circuit DIC through the pad PD. For example, the first power voltage VDD and the second power voltage VSS can be received from the driver integrated circuit DIC through the pad PD. For example, in the case where the gate driver 120 is mounted on the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit DIC to the gate driver 120 through the pad PD.

[0108] In an embodiment, the circuit board can be electrically connected to the pad PD using a conductive adhesive member such as an anisotropic conductive film. At this time, the circuit board can be a flexible printed circuit board (FPCB) or a flexible film having a flexible material. The driver integrated circuit DIC can be mounted on the circuit board to be electrically connected to the pad PD.

[0109] In an embodiment, the display area DA can have various shapes. The display area DA can have a closed-loop shape including straight edges and / or curved edges. For example, the display area DA can have shapes such as a polygon, a circle, a semi-circle, and an ellipse.

[0110] In an embodiment, the display panel DP can have a flat display surface. In other embodiments, the display panel DP can have a display surface that is at least partially rounded. In an embodiment, the display panel DP can be bendable, foldable, or rollable. In these cases, the display panel DP and / or the substrate SUB can include materials having flexible properties.

[0111] Figure 4 is a exploded perspective view showing a part of the Figure 3 display panel.

[0112] Refer toFigure 4 also refer to Figure 2 and Figure 3 , the display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light-emitting element layer LDL, a packaging layer TFE, an optical function layer OFL, an outer coating OC, and a cover window CW.

[0113] In an embodiment, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon germanium. Within the spirit and scope of the present disclosure, the substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer, etc. In other embodiments, the substrate SUB may include a glass substrate. In other embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0114] The pixel circuit layer PCL is disposed on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and conductive patterns disposed between the insulating layers. Within the spirit and scope of the present disclosure, the conductive patterns of the pixel circuit layer PCL may be used as at least a part of circuit elements and lines, etc. The conductive patterns may include copper, but the embodiments are not limited thereto.

[0115] The circuit elements may include sub-pixel circuits SPC for each of a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The sub-pixel circuit SPC may include a transistor and at least one capacitor. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping with the semiconductor portion. In an embodiment, when the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment, when the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other in a plane defined by a first direction DR1 and a second direction DR2. For example, each capacitor may include electrodes spaced apart from each other in a third direction DR3, and an insulating layer is disposed between these electrodes.

[0116] Within the spirit and scope of the present disclosure, the lines of the pixel circuit layer PCL may include signal lines connected to each of the sub-pixels SP, such as gate lines, emission control lines, and data lines, etc. These lines may also include lines connected to Figure 2 the first power voltage node VDDN ofFigure 2 Line of the second power voltage node VSSN.

[0117] The light-emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, a light-emitting structure EMS, and a cathode electrode CE.

[0118] The anode electrode AE may be disposed on the pixel circuit layer PCL. The anode electrode AE may be in contact with the circuit elements of the pixel circuit layer PCL. The anode electrode AE may include an opaque conductive material capable of reflecting light, but the embodiments are not limited thereto.

[0119] The pixel defining layer PDL is disposed on the anode electrode AE. The pixel defining layer PDL may include openings OP that expose portions of each of the anode electrodes AE. The openings OP of the pixel defining layer PDL may be understood as emission regions corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively.

[0120] In an embodiment, the pixel defining layer PDL may include an inorganic material. In this case, the pixel defining layer PDL may include stacked inorganic layers. For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x ). In other embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited thereto.

[0121] The light-emitting structure EMS may be disposed on the anode electrode AE exposed by the openings OP of the pixel defining layer PDL. Within the spirit and scope of the present disclosure, the light-emitting structure EMS may include a light-emitting layer formed to generate light, an electron transport layer formed to transport electrons, a hole transport layer formed to transport holes, and the like.

[0122] In an embodiment, the light-emitting structure EMS may fill the openings OP of the pixel defining layer PDL and may be completely disposed on the pixel defining layer PDL. In other words, the light-emitting structure EMS may extend across the first sub-pixel SP1 to the third sub-pixel SP3. In this case, at least a portion of the layers in the light-emitting structure EMS may be disconnected, bent, or removed at the boundaries between the sub-pixels SP. However, the embodiments are not limited thereto. For example, the portions of the light-emitting structure EMS corresponding to the sub-pixels SP may be separated from each other, and each of these portions may be disposed in the openings OP of the pixel defining layer PDL.

[0123] The cathode electrode CE may be disposed on the light-emitting structure EMS. The cathode electrode CE may extend across the sub-pixels SP. As described above, the cathode electrode CE may be provided as a common electrode for the sub-pixels SP.

[0124] The cathode electrode CE can be a thin metal layer having a thickness sufficient to transmit light emitted from the light-emitting structure EMS. The cathode electrode CE can be formed of a metal material or a transparent conductive material to have a relatively thin thickness. In an embodiment, the cathode electrode CE can include at least one of various transparent conductive materials, which include indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc oxide tin, or gallium tin oxide. In other embodiments, the cathode electrode CE can include at least one of silver (Ag), magnesium (Mg), and mixtures thereof. However, the material of the cathode electrode CE is not limited thereto.

[0125] It can be understood that any one of the anode electrodes AE, the portion of the light-emitting structure EMS overlapping with the any one of the anode electrodes AE, and the portion of the cathode electrode CE overlapping with the any one of the anode electrodes AE form a light-emitting element LD (refer to Figure 2 ). In other words, each of the light-emitting elements LD of the sub-pixels SP can be an anode electrode, the portion of the light-emitting structure EMS overlapping with the one anode electrode, and the portion of the cathode electrode CE overlapping with the one anode electrode. In each of the first sub-pixel SP1 to the third sub-pixel SP3, holes injected from the anode electrode AE and electrons injected from the cathode electrode CE can be transported to the light-emitting layer of the light-emitting structure EMS to form excitons, and when the excitons transition from the excited state to the ground state, light can be generated. The brightness of the light can be determined according to the amount of current flowing through the light-emitting layer. According to the configuration of the light-emitting layer, the wavelength range of the generated light can be determined.

[0126] The encapsulation layer TFE is disposed on the cathode electrode CE. The encapsulation layer TFE can cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE can be formed to prevent oxygen and / or moisture, etc. from penetrating into the light-emitting element layer LDL. In an embodiment, the encapsulation layer TFE can include a structure in which one or more inorganic layers and one or more organic layers are alternately stacked with each other. For example, within the spirit and scope of the present disclosure, the inorganic layer can include silicon nitride, silicon oxide, or silicon oxynitride (SiO x N y ), etc. For example, the organic layer can include organic insulating materials such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the encapsulation layer TFE are not limited thereto.

[0127] To improve the encapsulation efficiency of the encapsulation layer TFE, the encapsulation layer TFE can further include alumina (AlO x) The film. The film containing alumina can be located on the upper surface of the encapsulation layer TFE facing the optical functional layer OFL and / or on the lower surface of the encapsulation layer TFE facing the light-emitting element layer LDL.

[0128] The film containing alumina can be formed by an atomic layer deposition (ALD) method. However, the embodiments are not limited thereto. The encapsulation layer TFE may also include a film formed of at least one of various materials suitable for improving the encapsulation efficiency.

[0129] The optical functional layer OFL is disposed on the encapsulation layer TFE. The optical functional layer OFL may include a color filter layer CFL and a lens array LA.

[0130] The color filter layer CFL is disposed between the encapsulation layer TFE and the lens array LA. The color filter layer CFL is formed to filter the light emitted from the light-emitting structure EMS and selectively output light in a wavelength range or color corresponding to each sub-pixel SP. The color filter layer CFL may include color filters CF corresponding to the sub-pixels SP respectively, and each of the color filters CF may allow light in the wavelength range corresponding to the corresponding sub-pixel SP to pass through. For example, the color filter CF corresponding to the first sub-pixel SP1 may allow red light to pass through, the color filter CF corresponding to the second sub-pixel SP2 may allow green light to pass through, and the color filter CF corresponding to the third sub-pixel SP3 may allow blue light to pass through. At least a part of the color filter CF may be omitted according to the light emitted from the light-emitting structure EMS of each sub-pixel SP.

[0131] The lens array LA is disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the sub-pixels SP respectively. Each of the lenses LS may improve the light output efficiency by outputting the light emitted from the light-emitting structure EMS to an intended path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index higher than that of the outer coating OC. In an embodiment, the lens LS may include an organic material. In an embodiment, the lens LS may include an acrylate material. However, the material of the lens LS is not limited thereto.

[0132] In an embodiment, compared with the opening OP of the pixel defining layer PDL, at least a part of the color filter CF of the color filter layer CFL and at least a part of the lens LS of the lens array LA may be shifted in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2. For example, in the central region of the display area DA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be aligned with or overlap the center of the opening OP of the corresponding pixel defining layer PDL. For example, in the central region of the display area DA, the opening OP of the pixel defining layer PDL may completely overlap the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In the region of the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be shifted in the plane direction from the center of the opening OP of the corresponding pixel defining layer PDL. For example, in the region of the display area DA adjacent to the non-display area NDA, the opening OP of the pixel defining layer PDL may partially overlap the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Therefore, at the center of the display area DA, the light emitted from the light emitting structure EMS can be effectively output in the normal direction of the display surface. At the periphery (outskirt) of the display area DA, the light emitted from the light emitting structure EMS can be effectively output in a direction inclined at an optional angle with respect to the normal direction of the display surface.

[0133] An outer coating OC may be provided on the lens array LA. The outer coating OC may cover the optical functional layer OFL, the encapsulation layer TFE, the light emitting structure EMS, and / or the pixel circuit layer PCL. The outer coating OC may include various materials suitable for protecting the layers below the outer coating OC from foreign substances such as dust or moisture. For example, the outer coating OC may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the outer coating OC may include an epoxy resin, but the embodiment is not limited thereto. The outer coating OC may have a refractive index lower than that of the lens array LA.

[0134] A cover window CW may be provided on the outer coating OC. The cover window CW is formed to protect the layers below the cover window CW. The cover window CW may have a refractive index higher than that of the outer coating OC. The cover window CW may include glass, but the embodiment is not limited thereto. For example, the cover window CW may be a packaging glass formed to protect the components provided below the cover window CW. In other embodiments, the cover window CW may be omitted.

[0135] Figure 5 is a schematic plan view showing the relationship between sub-pixels and metal wires.

[0136] Referring to Figure 5, which shows a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 arranged or disposed in a first direction DR1. The first sub-pixel SP1 may include a first emission area EMA1 and a non-emission area NEA surrounding the first emission area EMA1. The second sub-pixel SP2 may include a second emission area EMA2 and a non-emission area NEA surrounding the second emission area EMA2. The third sub-pixel SP3 may include a third emission area EMA3 and a non-emission area NEA surrounding the third emission area EMA3.

[0137] The first emission area EMA1 may be an area that emits light from a portion of the light-emitting structure EMS (refer to Figure 4 ). The second emission area EMA2 may be an area that emits light from a portion of the light-emitting structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 may be an area that emits light from a portion of the light-emitting structure EMS corresponding to the third sub-pixel SP3. As referred to Figure 5 above, each of the emission areas EMA1, EMA2, and EMA3 may be understood as an opening OP of a pixel defining layer PDL corresponding to each of the first sub-pixel SP1 to the third sub-pixel SP3.

[0138] In Figure 5 , the emission areas EMA1, EMA2, and EMA3 are shown as hexagons, but the emission areas EMA1, EMA2, and EMA3 may also be formed as another polygon including a quadrilateral. The emission areas EMA1, EMA2, and EMA3 may be formed in a circular shape or an elliptical shape. The shapes and areas of the different emission areas EMA1, EMA2, and EMA3 may be different.

[0139] The metal lines JHLk and JHL(k + 1) may extend in the first direction DR1 and have a shape surrounding the corresponding emission areas EMA1, EMA2, and EMA3. For example, the metal lines JHLk and JHL(k + 1) may extend in a zigzag manner in the first direction DR1.

[0140] However, since the metal lines JHLk and JHL(k + 1) are not connected to each other in the display area DA, areas POI1 and POI2 that are not covered by the metal lines JHLk and JHL(k + 1) can exist between adjacent emission areas EMA1, EMA2, and EMA3. However, in areas POI1 and POI2, two or more metal lines JHLk and JHL(k + 1) can be arranged adjacent to each other at a minimum distance. According to an embodiment, since the organic material present in areas POI1 and POI2 that do not overlap with the metal lines JHLk and JHL(k + 1) can also be sublimated due to the heat generated from the two adjacent metal lines JHLk and JHL(k + 1), leakage current through the organic material can be prevented.

[0141] Figure 6 is a schematic cross-sectional view showing an embodiment of a light-emitting structure.

[0142] Referring to Figure 6 , the light-emitting structure EMS can have a tandem structure in which a first light-emitting unit EU1 and a second light-emitting unit EU2 can be stacked on top of each other.

[0143] Each of the first light-emitting unit EU1 and the second light-emitting unit EU2 can include a light-emitting layer that generates light according to the applied current. The first light-emitting unit EU1 can include a first light-emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light-emitting layer EML1 can be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting unit EU2 can include a second light-emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light-emitting layer EML2 can be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0144] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 can include at least one of a hole injection layer and a hole transport layer, and if necessary, can also include a hole buffer layer, an electron blocking layer, etc. The first hole transport unit HTU1 and the second hole transport unit HTU2 can have the same or different configurations from each other.

[0145] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 can include at least one of an electron injection layer and an electron transport layer, and if necessary, can also include an electron buffer layer, a hole blocking layer, etc. The first electron transport unit ETU1 and the second electron transport unit ETU2 can have the same or different configurations from each other.

[0146] A connection layer, which can be provided in the form of a charge generation layer CGL, can be disposed between the first light-emitting unit EU1 and the second light-emitting unit EU2 to connect the first light-emitting unit EU1 and the second light-emitting unit EU2 to each other. In an embodiment, the charge generation layer CGL can have a stacked structure of a p-dopant layer and an n-dopant layer. For example, the p-dopant layer can include p-type dopants such as HAT-CN, TCNQ, and NDP-9, and the n-dopant layer can include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, the embodiments are not limited thereto.

[0147] In an embodiment, the first light-emitting layer EML1 and the second light-emitting layer EML2 can emit lights of different colors. The lights emitted from the first light-emitting layer EML1 and the second light-emitting layer EML2 can be mixed and regarded as white light. For example, the first light-emitting layer EML1 can emit blue light, and the second light-emitting layer EML2 can emit yellow light. In an embodiment, the second light-emitting layer EML2 can have a structure in which a first sub-light-emitting layer formed to emit red light and a second sub-light-emitting layer formed to emit green light are stacked on each other. The red light and the green light can be mixed, and thus, yellow light can be provided. In this case, an intermediate layer formed to perform a function of transporting holes and / or blocking electron transport can also be disposed between the first sub-light-emitting layer and the second sub-light-emitting layer.

[0148] In other embodiments, the first light-emitting layer EML1 and the second light-emitting layer EML2 can emit lights of the same color.

[0149] In an embodiment, the light-emitting structure EMS can be formed by methods such as vacuum deposition or inkjet printing, but the embodiments are not limited thereto.

[0150] Figure 7 is a schematic cross-sectional view showing an embodiment of the light-emitting structure.

[0151] Referring to Figure 7 and also referring to Figure 8 , the light-emitting structure EMS' can have a series structure in which the first light-emitting unit EU1' to the third light-emitting unit EU3' are stacked on each other.

[0152] Each of the first light-emitting unit EU1' to the third light-emitting unit EU3' may include a light-emitting layer that generates light according to the applied current. The first light-emitting unit EU1' may include a first light-emitting layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first light-emitting layer EML1' may be disposed between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light-emitting unit EU2' may include a second light-emitting layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second light-emitting layer EML2' may be disposed between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light-emitting unit EU3' may include a third light-emitting layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third light-emitting layer EML3' may be disposed between the third electron transport unit ETU3' and the third hole transport unit HTU3'.

[0153] Each of the first hole transport unit HTU1' to the third hole transport unit HTU3' may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc. if necessary. The first hole transport unit HTU1' to the third hole transport unit HTU3' may have the same or different configurations from each other.

[0154] If necessary, each of the first electron transport unit ETU1' to the third electron transport unit ETU3' may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. The first electron transport unit ETU1' to the third electron transport unit ETU3' may have the same or different configurations from each other.

[0155] A first charge generation layer CGL1' is disposed between the first light-emitting unit EU1' and the second light-emitting unit EU2'. A second charge generation layer CGL2' is disposed between the second light-emitting unit EU2' and the third light-emitting unit EU3'.

[0156] In an embodiment, the first light-emitting layer EML1' to the third light-emitting layer EML3' may generate light of different colors. The light emitted from the first light-emitting layer EML1' to the third light-emitting layer EML3' may be mixed and may be regarded as white light. For example, the first light-emitting layer EML1' may generate blue light, the second light-emitting layer EML2' may generate green light, and the third light-emitting layer EML3' may generate red light.

[0157] In other embodiments, two or more of the first light-emitting layer EML1' to the third light-emitting layer EML3' may generate light of the same color.

[0158] Unlike Figure 6 and Figure 7 shown, each light-emitting structure EMS of each sub-pixel may include a light-emitting unit. At this time, the light-emitting units included in different adjacent sub-pixels SP1, SP2, and SP3 may be formed to emit lights of different colors. For example, the light-emitting unit of the first sub-pixel SP1 may emit red light, the light-emitting unit of the second sub-pixel SP2 may emit green light, and the light-emitting unit of the third sub-pixel SP3 may emit blue light. In this case, the light-emitting units of the first sub-pixel SP1 to the third sub-pixel SP3 may be separated from each other, and each of them may be disposed in the opening OP of the pixel defining layer PDL. In this case, at least a part of the color filters CF1, CF2, and CF3 may be omitted.

[0159] Figure 8 is a schematic cross-sectional view taken along the Figure 5 line I-I'.

[0160] Referring to Figure 8 , a substrate SUB and a pixel circuit layer PCL disposed on the substrate SUB are provided.

[0161] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium, and / or silicon germanium.

[0162] The pixel circuit layer PCL is disposed on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first sub-pixel SP1 to the third sub-pixel SP3. For example, the substrate SUB and the pixel circuit layer PCL may include the transistor T_SP1 of the first sub-pixel SP1, the transistor T_SP2 of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be any one of the transistors included in the sub-pixel circuit SPC of the first sub-pixel SP1 (refer to Figure 2 ), the transistor T_SP2 of the second sub-pixel SP2 may be any one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 may be any one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. In Figure 8 , for the sake of clear and concise description, one of the transistors of each sub-pixel is shown, and the remaining circuit elements are omitted.

[0163] The transistor T_SP1 of the first sub-pixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0164] The source region SRA and the drain region DRA can be provided in the substrate SUB. The well WL formed by an ion implantation process can be provided in the substrate SUB, and the source region SRA and the drain region DRA can be provided to be spaced apart from each other in the well WL. The region between the source region SRA and the drain region DRA in the well WL can be defined as the channel region.

[0165] The gate electrode GE can overlap with the channel region between the source region SRA and the drain region DRA, and can be provided in the pixel circuit layer PCL. The gate electrode GE can be spaced apart from the well WL or the channel region by an insulating material such as the gate insulating layer GI. The gate electrode GE can include a conductive material.

[0166] The multiple layers included in the pixel circuit layer PCL can include insulating layers and conductive patterns provided between the insulating layers, and such conductive patterns can include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 can be electrically connected to the drain region DRA through a drain connection portion DRC passing through one or more insulating layers. The second conductive pattern CP2 can be electrically connected to the source region SRA through a source connection portion SRC passing through one or more insulating layers.

[0167] Since the gate electrode GE and the first conductive pattern CP1 and the second conductive pattern CP2 are connected to different circuit elements and / or lines, the transistor T_SP1 of the first sub-pixel SP1 can be provided as any one of the transistors of the first sub-pixel SP1.

[0168] Each of the transistor T_SP2 of the second sub-pixel SP2 and the transistor T_SP3 of the third sub-pixel SP3 can be formed to be similar to the transistor T_SP1 of the first sub-pixel SP1.

[0169] The via layer VIAL is provided on the pixel circuit layer PCL. The via layer VIAL can cover the pixel circuit layer PCL, and can have an overall flat surface. The via layer VIAL is formed to planarize the steps on the pixel circuit layer PCL. The via layer VIAL can include at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon carbonitride (SiCN), but the embodiments are not limited thereto.

[0170] The light-emitting element layer LDL is provided on the via layer VIAL. The light-emitting element layer LDL can include a first reflective electrode RE1 to a third reflective electrode RE3, a planarization layer PLNL, a first anode electrode AE1 to a third anode electrode AE3, a pixel definition layer PDL, a light-emitting structure EMS, and a cathode electrode CE.

[0171] On the via layer VIAL, the first reflective electrode RE1 to the third reflective electrode RE3 are respectively disposed in the first sub-pixel SP1 to the third sub-pixel SP3. Each of the first reflective electrode RE1 to the third reflective electrode RE3 can contact a circuit element disposed in the pixel circuit layer PCL through a via passing through the via layer VIAL.

[0172] The first reflective electrode RE1 to the third reflective electrode RE3 can be used as a total reflection mirror that reflects the light emitted from the light-emitting structure EMS toward the display surface (or the cover window CW). The first reflective electrode RE1 to the third reflective electrode RE3 can include a metal material suitable for reflecting light. The first reflective electrode RE1 to the third reflective electrode RE3 can include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected from them, but the embodiments are not limited thereto.

[0173] In an embodiment, a connection electrode can be disposed below or beneath each of the first reflective electrode RE1 to the third reflective electrode RE3. The connection electrode can improve the electrical connection characteristics between the corresponding reflective electrode and the circuit element of the pixel circuit layer PCL. The connection electrode can have a multi-layer structure. The multi-layer structure can include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but the embodiments are not limited thereto. In an embodiment, the corresponding reflective electrode can be located between the multi-layers of the connection electrode.

[0174] The buffer pattern BFP can be disposed below or beneath at least one of the first reflective electrode RE1 to the third reflective electrode RE3. The buffer pattern BFP can include an inorganic material such as silicon carbonitride, but the embodiments are not limited thereto. By disposing the buffer pattern BFP, the height of the corresponding reflective electrode in the third direction DR3 can be adjusted. For example, the buffer pattern BFP can be disposed between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0175] The first reflective electrode RE1 to the third reflective electrode RE3 can be used as a total reflection mirror, and the cathode electrode CE can be used as a semi-reflection mirror. The light emitted from the light-emitting layer of the light-emitting structure EMS can be amplified by reciprocating at least partially between the corresponding reflective electrode and the cathode electrode CE, and the amplified light can be output through the cathode electrode CE. As described above, the distance between each reflective electrode and the cathode electrode CE can be understood as the resonance distance of the light emitted from the light-emitting layer of the corresponding light-emitting structure EMS.

[0176] Due to the buffer pattern BFP, the first sub-pixel SP1 may have a resonance distance shorter than that of the other sub-pixels. The resonance distance adjusted as described above may allow light in a given wavelength range (e.g., red) to be amplified effectively and efficiently. Accordingly, the first sub-pixel SP1 may effectively and efficiently output light in the corresponding wavelength range.

[0177] In Figure 8 it, the buffer pattern BFP is provided to the first sub-pixel SP1 and not provided to the second sub-pixel SP2 and the third sub-pixel SP3, but the embodiment is not limited thereto. The buffer pattern may also be provided to at least one of the second sub-pixel SP2 and the third sub-pixel SP3 to adjust the resonance distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the buffer pattern BFP may also be provided to the second sub-pixel SP2, and the resonance distance of the second sub-pixel SP2 may be adjusted. For example, the first sub-pixel SP1 to the third sub-pixel SP3 may correspond to red, green, and blue, respectively, the distance between the first reflective electrode RE1 and the cathode electrode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE, and the distance between the second reflective electrode RE2 and the cathode electrode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0178] To planarize the steps between the first reflective electrode RE1 to the third reflective electrode RE3, a planarization layer PLNL may be disposed on the via layer VIAL and the first reflective electrode RE1 to the third reflective electrode RE3. The planarization layer PLNL may generally cover the first reflective electrode RE1 to the third reflective electrode RE3 and the via layer VIAL and may have a flat surface. In an embodiment, the planarization layer PLNL may be omitted.

[0179] On the planarization layer PLNL, first anode electrodes AE1 to third anode electrodes AE3 that overlap the first reflective electrode RE1 to the third reflective electrode RE3, respectively, are disposed. When viewed in the third direction DR3, the first anode electrodes AE1 to the third anode electrodes AE3 may have a shape similar to that of Figure 5 the first emission regions EMA1 to the third emission regions EMA3. The first anode electrodes AE1 to the third anode electrodes AE3 are respectively connected to the first reflective electrode RE1 to the third reflective electrode RE3. The first anode electrode AE1 may be connected to the first reflective electrode RE1 through a first via VIA1 that passes through the planarization layer PLNL. The second anode electrode AE2 may be connected to the second reflective electrode RE2 through a second via VIA2 that passes through the planarization layer PLNL. The third anode electrode AE3 may be connected to the third reflective electrode RE3 through a third via VIA3 that passes through the planarization layer PLNL.

[0180] In an embodiment, the first anode electrode AE1 to the third anode electrode AE3 may include at least one of transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the materials of the first anode electrode AE1 to the third anode electrode AE3 are not limited thereto. For example, the first anode electrode AE1 to the third anode electrode AE3 may include titanium nitride.

[0181] In an embodiment, an insulating layer may also be provided for adjusting the height of one or more of the first anode electrode AE1 to the third anode electrode AE3. The insulating layer may be disposed between at least one of the first anode electrode AE1 to the third anode electrode AE3 and the corresponding reflective electrode. In this case, the planarization layer PLNL and / or the buffer pattern BFP may be omitted. For example, the first sub-pixel SP1 to the third sub-pixel SP3 may correspond to red, green, and blue, respectively. The distance between the first anode electrode AE1 and the cathode electrode CE may be shorter than the distance between the second anode electrode AE2 and the cathode electrode CE, and the distance between the second anode electrode AE2 and the cathode electrode CE may be shorter than the distance between the third anode electrode AE3 and the cathode electrode CE. The pixel defining layer PDL is disposed on the first anode electrode AE1 to the third anode electrode AE3 and a part of the planarization layer PLNL. The pixel defining layer PDL may include an opening OP exposing a part of each of the first anode electrode AE1 to the third anode electrode AE3. The opening OP of the pixel defining layer PDL may define the emission region of each of the first sub-pixel SP1 to the third sub-pixel SP3. As described above, the pixel defining layer PDL may be disposed in Figure 5 the non-emission region NEA and may define Figure 5 the first emission region EMA1 to the third emission region EMA3.

[0182] In an embodiment, the pixel defining layer PDL may include an inorganic insulating layer. Each of the inorganic insulating layers may include at least one of silicon oxide (SiO x ) and silicon nitride (SiN x ). For example, the pixel defining layer PDL may include insulating layers stacked in sequence, and each of the insulating layers may include silicon nitride, silicon oxide, and silicon nitride. However, the embodiment is not limited thereto. The insulating layer may have a stepped cross-section in a region adjacent to the opening OP.

[0183] Metal wires JHLk may be provided in the boundary region BDA between adjacent sub-pixels. Metal wires JHL1, JHL2, JHL3,... and JHLo including the metal wires JHLk (refer to Figure 3) Each one of them can be located on the pixel defining layer PDL.

[0184] Each one of the metal lines JHL1 to JHLo including the metal line JHLk can contact the cathode electrodes CE of the light-emitting elements LD1, LD2, and LD3 of the sub-pixels SP in the display area DA. For example, after stacking the light-emitting structure EMS, the metal lines JHL1 to JHLo can sublime a part of the light-emitting structure EMS located nearby by heat dissipation due to Joule heating. In Figure 6 In the case of the light-emitting structure EMS of, when the Joule heating process is performed after all the first light-emitting units EU1, the charge generation layer CGL, and the second light-emitting units EU2 can be stacked on each other, the light-emitting structure EMS may not remain on the metal line JHLk. In Figure 7 In the case of the light-emitting structure EMS of, when the Joule heating process is performed after all the first light-emitting units EU1', the first charge generation layer CGL1', the second light-emitting units EU2', the second charge generation layer CGL2, and the third light-emitting units EU3' can be stacked on each other, the light-emitting structure EMS' may not remain on the metal line JHLk. Accordingly, leakage current can be prevented from passing through the portion of the light-emitting structure EMS disconnected due to the metal lines JHL1 to JHLo. The metal lines JHL1 to JHLo can be exposed to the outside of the light-emitting structure EMS and can contact the subsequently deposited cathode electrode CE.

[0185] The light-emitting structure EMS can be disposed on the anode electrode AE exposed by the opening OP of the pixel defining layer PDL. In an embodiment, the light-emitting structure EMS can be formed by processes such as vacuum deposition and inkjet printing. The light-emitting structure EMS can fill the opening OP of the pixel defining layer PDL and can be disposed entirely across the first sub-pixel SP1 to the third sub-pixel SP3. As described above, through the metal line JHLk, the light-emitting structure EMS can be at least partially disconnected in the boundary region BDA. Accordingly, in the case where the display panel DP is operated, current leaking from each of the first sub-pixel SP1 to the third sub-pixel SP3 to the sub-pixels adjacent to each of the first sub-pixel SP1 to the third sub-pixel SP3 via the multiple layers included in the light-emitting structure EMS can be reduced. Accordingly, the first light-emitting elements LD1 to the third light-emitting elements LD3 can operate with relatively high reliability. However, in the case where a voltage having a high voltage level is applied to the first metal pad JPD1, damage may occur in the sub-pixels SP adjacent to the metal lines JHL1 to JHLo.

[0186] The cathode electrode CE can be disposed on the light-emitting structure EMS. The cathode electrode CE can be commonly provided to the first sub-pixel SP1 to the third sub-pixel SP3. The cathode electrode CE can serve as a half mirror that partially transmits and partially reflects the light emitted from the light-emitting structure EMS.

[0187] The first anode electrode AE1, the portion of the light-emitting structure EMS overlapping with the first anode electrode AE1, and the portion of the cathode electrode CE overlapping with the first anode electrode AE1 can form the first light-emitting element LD1. The second anode electrode AE2, the portion of the light-emitting structure EMS overlapping with the second anode electrode AE2, and the portion of the cathode electrode CE overlapping with the second anode electrode AE2 can form the second light-emitting element LD2. The third anode electrode AE3, the portion of the light-emitting structure EMS overlapping with the third anode electrode AE3, and the portion of the cathode electrode CE overlapping with the third anode electrode AE3 can form the third light-emitting element LD3.

[0188] The encapsulation layer TFE is provided on the cathode electrode CE. The encapsulation layer TFE can prevent the penetration of oxygen and / or moisture, etc. into the light-emitting element layer LDL.

[0189] The optical function layer OFL is provided on the encapsulation layer TFE. In an embodiment, the optical function layer OFL can be attached to the encapsulation layer TFE through the adhesive layer APL. For example, the optical function layer OFL can be manufactured separately and attached to the encapsulation layer TFE through the adhesive layer APL. The adhesive layer APL can also perform the function of protecting the underlying layer including the encapsulation layer TFE.

[0190] The optical function layer OFL can include a color filter layer CFL and a lens array LA. The color filter layer CFL can include a first color filter CF1 to a third color filter CF3 corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. The first color filter CF1 to the third color filter CF3 can allow light of different wavelength ranges to pass through. For example, the first color filter CF1 to the third color filter CF3 can allow red, green, and blue light to pass through, respectively.

[0191] In an embodiment, the first color filter CF1 to the third color filter CF3 can partially overlap in the boundary region BDA. In other embodiments, the first color filter CF1 to the third color filter CF3 can be spaced apart from each other, and a black matrix can be provided between the first color filter CF1 to the third color filter CF3.

[0192] The lens array LA is provided on the color filter layer CFL. The lens array LA can include a first lens LS1, a second lens LS2, and a third lens LS3 corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. Each of the first lens LS1 to the third lens LS3 can improve the light output efficiency by outputting the light emitted from the first light-emitting element LD1 to the third light-emitting element LD3 to the expected path.

[0193] Figure 9 It is a diagram showing the voltage applied to the first metal pad.

[0194] Refer to Figure 9 , and also refer to Figure 3 , which shows the waveform of the voltage VM applied to the first metal pad JPD1. Referring to the first time period P1 to the fourth time period P4, the voltage VM may have pulses, and the voltage level may gradually increase. In an embodiment, the voltage VM may be applied to the metal wires JHL1 to JHLo through the first metal pad JPD1.

[0195] For example, the pulse applied to the first metal pad JPD1 during the first time period P1 may have a first voltage level Va, and the pulse applied to the first metal pad JPD1 during the second time period P2 may have a second voltage level Vb that is increased by a step voltage value SH from the first voltage level Va. The pulse applied to the first metal pad JPD1 during the third time period P3 may have a third voltage level Vc that is increased by a step voltage value SH from the second voltage level Vb. The pulse applied to the first metal pad JPD1 during the fourth time period P4 may have a fourth voltage level Vd that is increased by a step voltage value SH from the third voltage level Vc.

[0196] Therefore, the voltage VM applied to the first metal pad JPD1 may increase from an initial voltage level VI to a final voltage level VF. The final voltage level VF may be the voltage level required to be applied to the first metal pad JPD1 to reach the target temperature.

[0197] In an embodiment, the pulse amplitude of each of the pulses applied to the first time period P1 to the fourth time period P4 may have a reference amplitude value PH.

[0198] As Figure 9 shown, when a voltage increased by a step voltage value SH for each pulse is applied to the first metal pad JPD1, a value lower than the pulse amplitude value required to previously reach the final voltage level VF may be required. Therefore, damage to the sub-pixels adjacent to the metal wires JHL1 to JHLo can be reduced.

[0199] Refer to Figure 9 , the voltage VM is shown as including four pulses, but the present disclosure is not limited thereto, and based on Figure 2 the temperature at which the light-emitting element LD of Figure 8 is damaged,

[0200] Figure 10 is a schematic plan view of an embodiment of a display panel showing Figure 1 .

[0201] Reference Figure 10 , each of the metal lines JHL1 to JHLo may include two sub-metal lines. Since Figure 10 's display panel DP is similar to Figure 3 's display panel DP, the repeated description can be omitted.

[0202] Each of the metal lines JHL1 to JHLo may include two sub-metal lines. For example, the first metal line JHL1 may include a first sub-metal line JHL1-1 and a second sub-metal line JHL1-2, the second metal line JHL2 may include a first sub-metal line JHL2-1 and a second sub-metal line JHL2-2, and the o-th metal line JHLo may include a first sub-metal line JHLo-1 and a second sub-metal line JHLo-2.

[0203] The first sub-metal lines JHL1-1 to JHLo-1 and the second sub-metal lines JHL1-2 to JHLo-2 may cross the non-display area NDA and the display area DA, and may extend without overlapping the emission area of the sub-pixels SP in the display area DA. For example, similar to Figure 3 's metal lines JHL1 to JHLo, the first sub-metal lines JHL1-1 to JHLo-1 and the second sub-metal lines JHL1-2 to JHLo-2 may connect the first metal pad JPD1 and the second metal pad JPD2.

[0204] Reference Figure 10 , the first sub-metal lines JHL1-1 to JHLo-1 and the second sub-metal lines JHL1-2 to JHLo-2 are shown as spaced apart on a plane, but this is for ease of illustration, and the first sub-metal lines JHL1-1 to JHLo-1 and the second sub-metal lines JHL1-2 to JHLo-2 may be disposed vertically along the third direction DR3.

[0205] Since each of the metal lines JHL1 to JHLo may include two sub-metal lines, even if a power voltage having a voltage level lower than that in the case where each of the metal lines JHL1 to JHLo does not include sub-metal lines is applied to the first metal pad JPD1, the temperature at which the organic material adjacent to the metal lines JHL1 to JHLo is sublimated can be reached. Therefore, damage to the sub-pixels SP adjacent to the metal lines JHL1 to JHLo can be reduced.

[0206] Reference Figure 10, the first metal pad JPD1 is connected to one end or an end of each of the first sub-metal lines JHL1-1 to JHLo-1 and one end or an end of each of the second sub-metal lines JHL1-2 to JHLo-2, but the present disclosure is not limited thereto, and the first metal pad JPD1 may be divided and may be connected to one end or an end of each of the first sub-metal lines JHL1-1 to JHLo-1 and one end or an end of each of the second sub-metal lines JHL1-2 to JHLo-2.

[0207] For example, in the case where the first metal pad JPD1 is divided into two, one of the divided pads may be connected to one end or an end of each of the first sub-metal lines JHL1-1 to JHLo-1, and the other may be connected to one end or an end of each of the second sub-metal lines JHL1-2 to JHLo-2.

[0208] Referring to Figure 10 , each of the metal lines JHL1 to JHLo is shown as including two sub-metal lines, but the present disclosure is not limited thereto, and only a part of the metal lines JHL1 to JHLo may include two sub-metal lines.

[0209] Figure 11 is a schematic plan view showing the relationship between sub-pixels and metal lines. Referring to Figure 11 , also referring to Figure 10 , a schematic plan view of a display panel is shown in which each of the metal lines JHL1 to JHLo may include two sub-metal lines.

[0210] Since Figure 11 the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 of Figure 5 are similar to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 of

[0211] Similar to Figure 10 the metal lines JHL1 to JHLo of Figure 11 each of the metal lines JHLk and JHL(k + 1) of

[0212] The metal lines JHLk and JHL(k + 1) can extend in the first direction DR1 and can have shapes surrounding the corresponding emission regions EMA1, EMA2, and EMA3. Since each of the metal lines JHLk and JHL(k + 1) can include a first sub-metal line and a second sub-metal line, according to an embodiment, since the organic materials present in the regions POI1 and POI2 that do not overlap with the metal lines JHLk and JHL(k + 1) can also be sublimated by the heat generated from the four adjacent sub-metal lines, leakage current through the organic materials can be prevented.

[0213] Figure 12 and Figure 13 is a schematic cross-sectional view taken along the line II-II' of Figure 11 . Since Figure 12 and Figure 13 the pixel circuit layer PCL, the substrate SUB, the via layer VIAL, the planarization layer PLNL, the encapsulation layer TFE, and the optical function layer OFL of Figure 8 are similar to the pixel circuit layer PCL, the substrate SUB, the via layer VIAL, the planarization layer PLNL, the encapsulation layer TFE, and the optical function layer OFL of

[0214] Referring to Figure 12 , an embodiment of the display panel is shown in which each of the metal lines JHL1 to JHLo can include two sub-metal lines. The first sub-metal line JHLk-1 and the second sub-metal line JHLk-2 can be disposed on the substrate SUB in the vertical direction (e.g., the third direction DR3). The first sub-metal line JHLk-1 can be disposed on the pixel defining layer PDL, and the second sub-metal line JHLk-2 can be disposed inside the pixel defining layer PDL.

[0215] In an embodiment, the second sub-metal line JHLk-2 can be disposed in contact with the upper surface of the planarization layer PLNL. In other embodiments, the second sub-metal line JHLk-2 can be disposed to be spaced apart from the planarization layer PLNL inside the pixel defining layer PDL.

[0216] In the case where the planarization layer PLNL is omitted, the second sub-metal line JHLk-2 can be disposed in contact with the upper surface of the via layer VIAL. In other embodiments, in the case where the planarization layer PLNL is omitted, the second sub-metal line JHLk-2 can be disposed to be spaced apart from the via layer VIAL inside the pixel defining layer PDL.

[0217] Referring to Figure 13 , an embodiment of the display panel is shown in which each of the metal lines JHL1 to JHLo can include two sub-metal lines. Referring to Figure 13, the first sub-metal line JHLk-1 can be disposed on the pixel defining layer PDL, and the second sub-metal line JHLk-2 can be disposed inside the pixel defining layer PDL.

[0218] More specifically, each of the second sub-metal lines JHLk-2 can be formed by two lines. However, the present disclosure is not limited thereto, and each of the second sub-metal lines JHLk-2 can be formed by multiple lines.

[0219] Figure 14 is a schematic plan view showing Figure 1 an embodiment of the display panel.

[0220] Referring to Figure 14 , the first sub-metal pad JPD1-1 and the second sub-metal pad JPD1-2 are shown. Since Figure 14 the display panel DP of Figure 10 is similar to the display panel DP of

[0221] One end or one side of the first sub-metal lines JHL1-1 to JHLo-1 can be connected to the first sub-metal pad JPD1-1, and one end or one side of the second sub-metal lines JHL1-2 to JHLo-2 can be connected to the second sub-metal pad JPD1-2.

[0222] Separate voltages can be applied to the first sub-metal pad JPD1-1 and the second sub-metal pad JPD1-2. For example, a voltage including a single pulse can be applied to the first sub-metal lines JHL1-1 to JHLo-1, and a voltage including a pulse as shown in Figure 9 can be applied to the second sub-metal lines JHL1-2 to JHLo-2.

[0223] A voltage including a single pulse can be applied to the second sub-metal lines JHL1-2 to JHLo-2, and a voltage including a pulse as shown in Figure 9 can be applied to the first sub-metal lines JHL1-1 to JHLo-1.

[0224] A voltage including a single pulse can be applied to both the first sub-metal lines JHL1-1 to JHLo-1 and the second sub-metal lines JHL1-2 to JHLo-2, and a voltage including a pulse as shown in Figure 9 can be applied to both the first sub-metal lines JHL1-1 to JHLo-1 and the second sub-metal lines JHL1-2 to JHLo-2.

[0225] Figure 15 is a block diagram showing an embodiment of the display system.

[0226] Referring to Figure 15, the display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220.

[0227] The processor 1100 may perform various tasks and calculations. In an embodiment, within the spirit and scope of the present disclosure, the processor 1100 may include an application processor, a graphics processor, a microprocessor, and a central processing unit (CPU), etc. The processor 1100 may be connected to other components of the display system 1000 through a bus system and may control other components.

[0228] In Figure 15 , the display system 1000 may include a first display device 1210 and a second display device 1220. The processor 1100 may be connected to the first display device 1210 through a first channel CH1 and may be connected to the second display device 1220 through a second channel CH2.

[0229] Through the first channel CH1, the processor 1100 may transmit first image data IMG1 and a first control signal CTRL1 to the first display device 1210. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 may be formed similar to the display device 100 described with reference to Figure 1 . In this case, the first image data IMG1 and the first control signal CTRL1 may be provided as the input image data IMG and the control signal CTRL of Figure 1 respectively.

[0230] Through the second channel CH2, the processor 1100 may transmit second image data IMG2 and a second control signal CTRL2 to the second display device 1220. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 may be formed similar to the display device 100 described with reference to Figure 1 . In this case, the second image data IMG2 and the second control signal CTRL2 may be provided as the input image data IMG and the control signal CTRL of Figure 1 respectively.

[0231] The display system 1000 may include a computing system that provides an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation device, and an ultra-mobile personal computer (UMPC). The display system 1000 may include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0232] Figure 16 is a schematic perspective view showing an application example of a display system Figure 15 .

[0233] Referring to Figure 16 , Figure 15 the display system 1000 of

[0234] can be applied to a head-mounted display device 2000. The head-mounted display device 2000 can be a wearable electronic device that can be worn on a user's head.

[0235] The head-mounted display device 2000 can include a head mounting band 2100 and a display device housing 2200. The head mounting band 2100 can be connected to the display device housing 2200. The head mounting band 2100 can include a horizontal band and / or a vertical band for fixing the head-mounted display device 2000 to the user's head. The horizontal band can be formed to surround a side portion of the user's head, and the vertical band can be formed to surround an upper portion of the user's head. However, the embodiments are not limited thereto. For example, within the spirit and scope of the present disclosure, the head mounting band 2100 can be implemented in the form of a spectacle frame, or a helmet form, etc.

[0235] The display device housing 2200 can accommodate Figure 15 the first display device 1210 and the second display device 1220 of Figure 15 . The display device housing 2200 can also accommodate

[0236] Figure 17 is a view showing Figure 16 the head-mounted display device worn by the user.

[0237] Referring to Figure 17 , in the head-mounted display device 2000, a first display panel DP1 of the first display device 1210 and a second display panel DP2 of the second display device 1220 are provided. The head-mounted display device 2000 can also include one or more lenses LLNS and RLNS.

[0238] In the display device housing 2200, the right-eye lens RLNS can be provided between the first display panel DP1 and the user's right eye. In the display device housing 2200, the left-eye lens LLNS can be provided between the second display panel DP2 and the user's left eye.

[0239] The image output from the first display panel DP1 can be displayed to the user's right eye through the right-eye lens RLNS. The right-eye lens RLNS can refract the light from the first display panel DP1 to direct it toward the user's right eye. The right-eye lens RLNS can perform an optical function for adjusting the viewing distance between the first display panel DP1 and the user's right eye.

[0240] The image output from the second display panel DP2 can be displayed to the left eye of the user through the left-eye lens LLNS. The left-eye lens LLNS can refract the light from the second display panel DP2 to direct it towards the left eye of the user. The left-eye lens LLNS can perform an optical function for adjusting the viewing distance between the second display panel DP2 and the left eye of the user.

[0241] In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a flat cross-section. In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical characteristics. In this case, each display panel may output an image corresponding to the sub-region of the multi-channel lens respectively, and the output image may pass through the corresponding sub-region and may be viewed by the user.

[0242] The accompanying drawings referred to and the detailed description of the present disclosure herein are examples of the present disclosure for describing the present disclosure and are not intended to limit the meaning and scope of the present disclosure as set forth in the claims. Thus, those skilled in the art will understand that various modifications and other equivalent embodiments are possible from these embodiments. Therefore, the true scope of the present disclosure should be determined by the technical spirit of the appended claims.

Claims

1. A display device, wherein: The display device comprises: Display area and non-display area; A sub-pixel is arranged in the display area; and a metal line intersecting the non-display area and the display area, and the metal line is spaced apart from the emission area of ​​the sub-pixel on a plane in the display area, Wherein, a voltage including a plurality of pulses is applied to the metal line, and the voltage increases by a step voltage value for each of the plurality of pulses.

2. The display device according to claim 1, wherein: The pulse amplitudes of the plurality of pulses are equal to each other.

3. The display device according to claim 1, wherein: The display device further includes: a first metal pad disposed in the non-display area and electrically connected to an end of the metal line; and A second metal pad is disposed in the non-display area and is electrically connected to the other end of the metal line, wherein: The display area is disposed between the first metal pad and the second metal pad, and The voltage including the plurality of pulses is applied to the metal line through the first metal pad.

4. A display device, wherein: The display device comprises: Display area and non-display area; A plurality of sub-pixels are arranged in the display area; and a first sub-metal line and a second sub-metal line intersecting the non-display area and the display area, and the first sub-metal line and the second sub-metal line are spaced apart from the plurality of emission areas of the plurality of sub-pixels on a plane in the display area, The first sub-metal line and the second sub-metal line are arranged on the substrate in a vertical direction.

5. The display device according to claim 4, wherein: The first sub-metal line is disposed on a pixel defining layer in the display area, the pixel defining layer defining the plurality of emission areas of the plurality of sub-pixels, and The second sub-metal line is disposed inside the pixel defining layer.

6. The display device according to claim 5, wherein: The display device further includes: A pixel circuit layer, disposed on the substrate, the pixel circuit layer comprising a sub-pixel circuit of each of the plurality of sub-pixels; a via layer, disposed on the pixel circuit layer; and a light emitting element layer, disposed on the via layer, wherein the light emitting element layer includes the pixel defining layer, Wherein, the second sub-metal line contacts the upper surface of the via layer.

7. The display device according to claim 5, wherein: The display device further includes: A pixel circuit layer, disposed on the substrate, the pixel circuit layer comprising a sub-pixel circuit of each of the plurality of sub-pixels; a via layer, disposed on the pixel circuit layer; and a light emitting element layer, disposed on the via layer, wherein the light emitting element layer includes the pixel defining layer, The second sub-metal line is spaced apart from the via layer, and the second sub-metal line is disposed inside the pixel defining layer.

8. The display device according to claim 4, wherein: The second sub metal line is formed of a plurality of lines.

9. The display device according to claim 4, wherein: The display device further includes: a first metal pad disposed in the non-display area and electrically connected to an end of the first sub-metal line and an end of the second sub-metal line; and a second metal pad disposed in the non-display area and electrically connected to the other end of the first sub-metal line and the other end of the second sub-metal line, Wherein, the display area is arranged between the first metal pad and the second metal pad.

10. The display device according to claim 9, wherein: The first metal pad further includes a first sub-metal pad and a second sub-metal pad. The end of the first sub-metal line is electrically connected to the first sub-metal pad, The end of the second sub-metal line is electrically connected to the second sub-metal pad, and Separate voltages are applied to the first sub-metal pad and the second sub-metal pad.

Images