Display device

Abstract

A display device is provided. The display device includes: a first semiconductor layer including first and second channel regions, a source-drain region between the first and second channel regions, and a source / drain region extending from the second channel region; a first conductive layer on the first semiconductor layer and including a first electrode and a second electrode overlapping the first channel region and the second channel region, respectively; a second semiconductor layer on the first conductive layer and including a third channel region; a second conductive layer on the second semiconductor layer and including a third electrode overlapping the third channel region and a first signal line electrically connected to the second electrode; a third conductive layer on the second conductive layer and including a first conductive region electrically connected to the source / drain region; and a fourth conductive layer on the third conductive layer and including a voltage line electrically connected to the first conductive region.

Description

[0001] Cross - reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application Nos. 10 - 2023 - 0185063 and 10 - 2024 - 0034102, filed with the Korean Intellectual Property Office on December 18, 2023 and March 11, 2024, respectively. The disclosures of these Korean patent applications are incorporated herein by reference in their entirety. Technical field

[0003] One or more embodiments relate to a display device. Background art

[0004] Recently, display devices with reduced thickness and weight have been developed, thereby achieving improved portability and expanded uses. A display device may include a plurality of light - emitting elements and pixel circuits configured to control the brightness and other parameters of each light - emitting element. Each pixel circuit may include transistors and capacitors connected to circuit lines such as data lines, gate lines, voltage lines, etc.

[0005] As the use range of display devices has expanded and the functions combined with or associated with them have increased, various forms of display devices have been designed. Summary of the invention

[0006] As the resolution of a display device increases, the distances between transistors, capacitors, and circuit lines decrease. As a result, the parasitic capacitance between the transistors and the circuit lines may increase, and when the display device is driven at low brightness and low gray levels, for example, spots in the shape of horizontal stripes that deteriorate the display quality may be displayed.

[0007] One or more embodiments disclosed herein relate to a display device that displays high - quality images while reducing the parasitic capacitance between transistors and circuit lines.

[0008] According to one or more embodiments, a display device includes: a first semiconductor layer including a first channel region, a second channel region, a first source - drain region between the first channel region and the second channel region, and a source / drain region extending from the second channel region; a first conductive layer disposed on the first semiconductor layer and including a first electrode overlapping the first channel region and a second electrode overlapping the second channel region; a second semiconductor layer disposed on the first conductive layer and including a third channel region; a second conductive layer disposed on the second semiconductor layer and including a third electrode overlapping the third channel region and a first signal line electrically connected to the second electrode; a third conductive layer disposed on the second conductive layer and including a first conductive region electrically connected to the source / drain region; and a fourth conductive layer disposed on the third conductive layer and including a voltage line electrically connected to the first conductive region.

[0009] The first channel region, the first source-drain region, the second channel region, and the source / drain region may be provided integrally.

[0010] The first signal line may extend in a first direction, and the first signal line may overlap with the first source-drain region and the second channel region.

[0011] The source / drain region may be arranged to be spaced apart from the first electrode in the first direction.

[0012] The first semiconductor layer may further include a fourth channel region extending from the first source-drain region and a third source / drain region extending from the fourth channel region. The first conductive layer may further include a second signal line overlapping with the fourth channel region, and the fourth conductive layer may further include a data line electrically connected to the third source / drain region.

[0013] The data line may overlap with the second channel region.

[0014] The first semiconductor layer may further include a fifth channel region, and the first conductive layer may further include a fourth electrode overlapping with the fifth channel region.

[0015] The first signal line may be electrically connected to the fourth electrode.

[0016] The first conductive layer may further include a third signal line overlapping with the third channel region and electrically connected to the third electrode.

[0017] The source / drain region may be a first source / drain region. The first semiconductor layer may include a first portion and a second portion that form a symmetric circuit layout with respect to a virtual straight line extending in a second direction. The first portion may include the first source / drain region, and the second portion includes a second source / drain region formed integrally (e.g., integrally connected) with the first source / drain region, and the first portion and the second portion may be connected to each other through the connection between the first source / drain region and the second source / drain region.

[0018] According to one or more embodiments, a display device includes: a first semiconductor layer including a first channel region, a second channel region, a first source-drain region between the first channel region and the second channel region, and a source / drain region extending from the second channel region; a first conductive layer disposed on the first semiconductor layer and including a first electrode overlapping with the first channel region and a second electrode overlapping with the second channel region; a second conductive layer disposed on the first conductive layer and including a first conductive region overlapping with the first electrode; a second semiconductor layer disposed on the second conductive layer and including a third channel region; a third conductive layer disposed on the second semiconductor layer and including a third electrode overlapping with the third channel region; a fourth conductive layer disposed on the third conductive layer and including a second conductive region electrically connected to the source / drain region and the first conductive region and a first signal line electrically connected to the second electrode; and a fifth conductive layer disposed on the fourth conductive layer and including a voltage line electrically connected to the second conductive region. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 is a plan view of a display device according to an embodiment;

[0021] Figure 2 is a schematic circuit diagram of a pixel included in a display device according to an embodiment;

[0022] Figure 3A and Figure 3B is a view for describing a driving method of a display device according to an embodiment;

[0023] Figure 4 is a schematic timing diagram of a gate signal applied to a pixel circuit during an address scan period;

[0024] Figure 5 is a schematic timing diagram of a gate signal applied to a pixel circuit during a self-scan period;

[0025] Figure 6 is a schematic layout diagram of a part of a display device according to an embodiment;

[0026] Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 and Figure 13 are Figure 6 corresponding views of layers of a part of the display device shown in

[0027] Figure 14 Exemplary cross-sectional views of portions of the display device shown along line I-I' and line II-II'; Figure 6 as shown in;

[0028] Figure 15 is a schematic layout diagram of a portion of a display device according to another embodiment;

[0029] Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 、 Figure 21 and Figure 22 are Figure 15 views of each of the layers of a portion of the display device shown in; and

[0030] Figure 23 is Figure 15 a schematic cross-sectional view of a portion of the display device shown in. DETAILED DESCRIPTION

[0031] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, in which like reference numerals always refer to like elements. In this regard, the present embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the embodiments are described below only by referring to the drawings to explain aspects of the present description.

[0032] As used herein, a "source / drain" region is a source region or a drain region of a field effect transistor (FET).

[0033] As used herein, a "source-drain region" may be a doped semiconductor region integrally formed to collectively form (i) a source region of a first transistor adjacent to a drain region of a second transistor; (ii) a source region of a first transistor adjacent to a source region of a second transistor; and (iii) a drain region of a first transistor adjacent to a drain region of a second transistor. Due to the integral formation, an electrical connection between adjacent regions can be made through a semiconductor material without external metallization connecting the adjacent regions.

[0034] Temporarily referring collectively to Figures 1 to 14, the display device 10 according to an embodiment may include a first semiconductor layer (e.g., 1200) including a first channel region (e.g., A1 of the first transistor T1), a second channel region (e.g., A5 of the fifth transistor T5), a first source-drain region (e.g., SD1) extending from the second channel region, and a source / drain region (e.g., S5 of the first pixel region PCA) extending from the second channel region. A first conductive layer (e.g., 1300) may be disposed on the first semiconductor layer, and may include a first electrode (e.g., forming the gate electrode G1) overlapping with the first channel region and a second electrode (e.g., forming the gate electrode G5) overlapping with the second channel region. A second semiconductor layer (e.g., 1500) may be disposed on the first conductive layer, and may include a third channel region (e.g., A4). A second conductive layer (e.g., 1600) may be disposed on the second semiconductor layer, and may include a third electrode (e.g., forming the gate electrode G4) overlapping with the third channel region and a first signal line (e.g., EML) electrically connected to the second electrode. A third conductive layer (e.g., 1700) may be disposed on the second conductive layer, and may include a first conductive region (e.g., 1740) electrically connected to the source / drain region. A fourth conductive layer (e.g., 1800) may be disposed on the third conductive layer, and may include a voltage line (e.g., PL) electrically connected to the first conductive region.

[0035] Temporarily refer collectively to Figures 15 to 23 , the display device 10 according to an embodiment (see Figure 1) may include a first semiconductor layer (e.g., 2200) including a first channel region (e.g., A1 of the first transistor T1), a second channel region (e.g., A5 of the fifth transistor T5), a first source-drain region between the first channel region and the second channel region, and a source / drain region (e.g., S5 of the fifth transistor T5) extending from the second channel region; a first conductive layer (e.g., 2300) disposed on the first semiconductor layer and including a first electrode (e.g., forming the gate electrode G1) overlapping with the first channel region and a second electrode (e.g., forming the gate electrode G5) overlapping with the second channel region; a second conductive layer (e.g., 2400) disposed on the first conductive layer and including a first conductive region (e.g., 2410) overlapping with the first electrode; a second semiconductor layer (e.g., 2500) disposed on the second conductive layer and including a third channel region (e.g., A4 of the fourth transistor T4); a third conductive layer (2600) disposed on the second semiconductor layer and including a third electrode (e.g., forming the gate electrode G4) overlapping with the third channel region; a fourth conductive layer (e.g., 2700) disposed on the third conductive layer and including a second conductive region (e.g., 2740) electrically connected to the source / drain region and the first conductive region and a first signal line (e.g., EML) electrically connected to the second electrode; and a fifth conductive layer (e.g., 2800) disposed on the fourth conductive layer and including a voltage line (e.g., PL) electrically connected to the second conductive region.

[0036] As used herein, a "conductive pattern" may encompass a single region or block of a conductive material and multiple conductive regions having geometric features arranged in a repeatable, random, or otherwise manner.

[0037] As used herein, a via hole may be interchangeably referred to as a "contact hole".

[0038] While the inventive concept is capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will be described in detail herein. By referring to the embodiments described in detail below together Figure 1 The effects and characteristics of the present disclosure and the method of achieving the same will become apparent. However, the present disclosure is not limited to the embodiments disclosed below and may be implemented in various forms.

[0039] Hereinafter, embodiments will be described in detail with reference to the drawings, wherein when describing the drawings, the same or corresponding elements will be assigned the same reference numerals, and redundant descriptions thereof may not be given.

[0040] It should be understood that although terms such as "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another.

[0041] Unless the context clearly indicates otherwise, as used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well.

[0042] It should also be understood that the terms "comprises" and / or "comprising" as used herein specify the presence of the stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0043] It should be understood that when a layer, region, or element is referred to as being formed "on" another layer, region, or element, it can be directly or indirectly formed on the other layer, region, or element. Thus, intervening layers, regions, or elements can exist.

[0044] In this specification, it should be understood that when an element, region, or layer is referred to as being connected to another element, region, or layer, it can be directly and / or indirectly connected to the other element, region, or layer. For example, it should be understood that in this specification, when an element, region, or layer is referred to as being in contact with or electrically connected to another element, region, or layer, it can be directly and / or indirectly in contact with or electrically connected to the other element, region, or layer.

[0045] In this specification, the x-direction, y-direction, and z-direction are not limited to the directions on the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-direction, y-direction, and z-direction can be perpendicular to each other, or can indicate different directions that are not perpendicular to each other.

[0046] In this specification, the expression "in a plan view" means observing the object portion downward (e.g., in a direction perpendicular to the upper surface of the substrate), and the expression "in a sectional view" means observing a vertical section of the object portion laterally.

[0047] In this specification, the first element "overlapping" the second element means that the first element is located above or below the second element such that at least a part of the first element and the second element overlap each other in a plan view.

[0048] In this specification, the terms "on" and "off" used with respect to the state of a device respectively refer to the activated state and the non-activated state of the device. The terms "on" and "off" used with respect to a signal received by the device can respectively refer to a signal configured to activate the device and a signal not configured to activate the device. The device can be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) can be activated by a low-level voltage, and an N-channel transistor (N-type transistor) can be activated by a high-level voltage. Thus, it should be understood that the "on" voltages for a P-type transistor and an N-type transistor can be opposite voltages (low and high) to each other.

[0049] For convenience of explanation, the dimensions of elements in the drawings may be enlarged. For example, for convenience of explanation, the dimensions and thicknesses of elements in the drawings may be arbitrarily represented, and thus, the present disclosure is not necessarily limited to the illustrations in the drawings.

[0050] Figure 1 is a plan view of a display device 10 according to an embodiment.

[0051] Referring to Figure 1 , the display device 10 may include a display area DA in which an image is displayed and a peripheral area PA disposed around the display area DA. The display device 10 may provide a specific image by using light emitted from pixels disposed in the display area DA. According to an embodiment, as Figure 1 shown, the display area DA may have a rectangular shape. In other instances, the display area DA has various other shapes, such as other polygonal shapes, circular shapes, elliptical shapes, or amorphous shapes.

[0052] The peripheral area PA may be disposed around the display area DA and may be of a type of non-display area in which no pixels are disposed. The display area DA may be completely surrounded by the peripheral area PA. In the peripheral area PA, pads may be disposed for engaging with various lines or circuits, printed circuit boards, driver integrated chips (ICs), and the like configured to transmit electrical signals to the display area DA.

[0053] The display device 10 according to an embodiment may display moving images or static images, and may be used not only as a display screen of portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs), but also as a display screen of various products such as televisions (TVs), notebook computers, monitors, signboards, Internet of Things (IoT) devices, etc. In addition, the display device 10 according to an embodiment may be used in wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). In addition, the display device 10 according to an embodiment may be used as: a central information display (CID) on an instrument panel of a vehicle or a center fascia or dashboard of a vehicle; an in-vehicle mirror display replacing a side mirror of a vehicle; or a display disposed on a rear surface of a front seat as an entertainment device for a rear seat of a vehicle. In addition, the display device 10 may be a flexible, rollable, foldable, or stretchable device.

[0054] Figure 2 is a schematic equivalent circuit diagram of a pixel PX included in a display device according to an embodiment.

[0055] Referring to Figure 2, a pixel PX may include an organic light emitting diode OLED as a light emitting element and a pixel circuit PC electrically connected to the organic light emitting diode OLED. The pixel circuit PC may include a first transistor T1 to an eighth transistor T8 and a storage capacitor Cst. The first transistor T1 may be a driving transistor configured to output a driving current Id corresponding to a data signal Dm, and each of the second transistor T2 to the eighth transistor T8 may be a switching transistor configured to transmit a signal.

[0056] A first terminal of each of the first transistor T1 to the eighth transistor T8 may be a source or a drain, and a second terminal may be the other of the source and the drain.

[0057] A node connected to the gate of the first transistor T1 may be defined as a first node N1, a node connected to the first terminal S of the first transistor T1 may be defined as a second node N2, and a node connected to the second terminal D of the first transistor T1 may be defined as a third node N3.

[0058] The pixel circuit PC may be connected to a first gate signal line GWL configured to supply a first gate signal GW, a second gate signal line GIL configured to supply a second gate signal GI, a third gate signal line GCL configured to supply a third gate signal GC, a fourth gate signal line GBL configured to supply a fourth gate signal GB, an emission control signal line EML configured to supply an emission control signal EM, a data line DL configured to supply a data signal Dm, a driving voltage line PL configured to supply a driving voltage ELVDD, a first initialization voltage line VL1 configured to supply a first initialization voltage Vint, a second initialization voltage line VL2 configured to supply a second initialization voltage Vaint, and a conduction bias voltage line VL3 configured to supply a conduction bias voltage VOBS.

[0059] The first transistor T1 may include a gate connected to the first node N1, a first terminal S connected to the second node N2, and a second terminal D connected to the third node N3. The first terminal S of the first transistor T1 may be connected to the driving voltage line PL through a fifth transistor T5, and the second terminal D of the first transistor T1 may be connected to a pixel electrode (or anode) of the organic light emitting diode OLED through a sixth transistor T6. The first transistor T1 may be configured to receive the data signal Dm according to the switching operation of the second transistor T2 and control the amount of the driving current Id flowing through the pixel electrode of the organic light emitting diode OLED.

[0060] The second transistor T2 may be connected between the data line DL and the second node N2. The second transistor T2 may include a gate connected to the first gate signal line GWL, a first terminal connected to the data line DL, and a second terminal connected to the second node N2. The second transistor T2 may be turned on by a first gate signal GW transmitted through the first gate signal line GWL, and may be configured to electrically connect the data line DL and the second node N2 and transmit a data signal Dm from the data line DL to the second node N2.

[0061] The third transistor T3 may be connected between the first node N1 and the third node N3. The third transistor T3 may include a gate connected to the third gate signal line GCL, a first terminal connected to the first node N1, and a second terminal connected to the third node N3. The third transistor T3 may be turned on by a third gate signal GC transmitted through the third gate signal line GCL, and may be configured to connect the first node N1 and the third node N3 in a diode manner.

[0062] The fourth transistor T4 may be connected between the first node N1 and the first initialization voltage line VL1. The fourth transistor T4 may include a gate connected to the second gate signal line GIL, a first terminal connected to the first node N1, and a second terminal connected to the first initialization voltage line VL1. The fourth transistor T4 may be turned on by a second gate signal GI transmitted through the second gate signal line GIL, and may be configured to transmit a first initialization voltage Vint from the first initialization voltage line VL1 to the first node N1.

[0063] The fifth transistor T5 may be connected between the driving voltage line PL and the second node N2. The fifth transistor T5 may include a gate connected to the emission control signal line EML, a first terminal connected to the driving voltage line PL, and a second terminal connected to the second node N2.

[0064] The sixth transistor T6 may be connected between the third node N3 and the organic light-emitting diode OLED. The sixth transistor T6 may include a gate connected to the emission control signal line EML, a first terminal connected to the third node N3, and a second terminal connected to the pixel electrode of the organic light-emitting diode OLED. The fifth transistor T5 and the sixth transistor T6 may be simultaneously turned on by an emission control signal EM transmitted through the emission control signal line EML so that a driving current Id may flow through the pixel electrode of the organic light-emitting diode OLED.

[0065] The seventh transistor T7 may be connected between the second initialization voltage line VL2 and the organic light-emitting diode OLED. The seventh transistor T7 may include a gate connected to the fourth gate signal line GBL, a first terminal connected to the second initialization voltage line VL2, and a second terminal connected to the pixel electrode of the organic light-emitting diode OLED. The seventh transistor T7 may be turned on by the fourth gate signal GB transmitted through the fourth gate signal line GBL, and may be configured to transmit the second initialization voltage Vaint from the second initialization voltage line VL2 to the pixel electrode of the organic light-emitting diode OLED.

[0066] The eighth transistor T8 may be connected between the second node N2 and the conduction bias voltage line VL3. The eighth transistor T8 may include a gate connected to the fourth gate signal line GBL, a first terminal connected to the second node N2, and a second terminal connected to the conduction bias voltage line VL3. The eighth transistor T8 may be turned on by the fourth gate signal GB transmitted through the fourth gate signal line GBL, and may be configured to transmit the conduction bias voltage VOBS from the conduction bias voltage line VL3 to the second node N2. For low-frequency driving operation, the conduction bias voltage VOBS may be applied to the second node N2 during the self-scanning period to prevent deterioration of the first transistor T1.

[0067] The storage capacitor Cst may be connected between the driving voltage line PL and the first node N1. The first capacitor electrode CE1 of the storage capacitor Cst may be connected to the first node N1, and the second capacitor electrode CE2 may be connected to the driving voltage line PL. The storage capacitor Cst may be configured to store the threshold voltage of the first transistor T1 and the voltage corresponding to the data signal Dm.

[0068] The organic light-emitting diode OLED may include a pixel electrode and a counter electrode (e.g., a cathode) facing the pixel electrode, and the counter electrode may receive the common voltage ELVSS. The counter electrode may be a common electrode common to a plurality of pixels PX.

[0069] Some of the first transistor T1 to the eighth transistor T8 may be P-channel transistors, and the other transistors may be N-channel transistors. According to an embodiment, the first transistor T1, the second transistor T2, and the fifth transistor T5 to the eighth transistor T8 may be P-channel transistors, and the third transistor T3 and the fourth transistor T4 may be N-channel transistors. According to other embodiments, all of the first transistor T1 to the eighth transistor T8 may be N-channel transistors or P-channel transistors.

[0070] Figure 2 It is shown that the pixel circuit PC may include eight transistors and one capacitor. However, the present disclosure is not limited thereto. For example, the pixel circuit PC may include seven transistors and one capacitor.

[0071] Figure 3A and Figure 3B is a view for describing a driving method of a display device according to an embodiment.

[0072] With Figure 1 and Figure 2 refer to together Figure 3A and Figure 3B , the display device 10 may support variable refresh rate (VRR). The refresh rate, which is the frequency at which a data signal Dm is substantially written into a driving transistor (e.g., the first transistor T1) of a pixel PX, may also be referred to as a screen scanning rate or a screen reproduction rate, and may indicate the number of image frames reproduced during one second. The frequency corresponding to the refresh rate may be indicated as a driving frequency.

[0073] According to the driving frequency, the display device 10 may adjust the output frequency of the gate driving circuit and the output frequency of the data driving circuit. The display device 10 supporting VRR may operate by changing the driving frequency within a range between the maximum driving frequency and the minimum driving frequency.

[0074] According to the driving frequency, one frame 1F may include an address scan period AS, or may include an address scan period AS and at least one self-scan period SS. For example, as Figure 3A shown, in the display device 10 operating at a driving frequency of A Hz, one frame 1F may include one address scan period AS and one self-scan period SS. As Figure 3B shown, in the display device 10 operating at a driving frequency of B Hz lower than A Hz, one frame 1F may include one address scan period AS and multiple self-scan periods SS. As the driving frequency decreases, the number of self-scan periods SS included in one frame 1F may increase.

[0075] During the address scan period AS, the data signal Dm may be written into the pixel PX according to the first gate signal GW. The operation of writing the data signal Dm from the data line DL into the pixel PX may also be referred to as a data programming operation. During the self-scan period SS, the first gate signal GW may not be applied, and the data signal Dm may not be written into the pixel PX. During the self-scan period SS, the data signal Dm written and stored during the address scan period AS may be maintained, and the pixel PX may emit light with a brightness corresponding to the data signal Dm stored during the address scan period AS. As the number of self-scan periods SS included in one frame 1F increases, the power consumption may be reduced.

[0076] According to an embodiment, the length of the address scan period AS and the length of the self-scan period SS may be the same as each other. For example, when the maximum driving frequency is 120 Hz, each of the address scan period AS and the self-scan period SS may be half of about 8.3 ms.

[0077] Figure 4 is a schematic timing diagram of a gate signal applied to a pixel circuit during an address scan period, and Figure 5 is a schematic timing diagram of a gate signal applied to a pixel circuit during a self-scan period.

[0078] With Figure 2 referring together to Figure 4 and Figure 5 , each of a first gate signal GW, a second gate signal GI, a third gate signal GC, a fourth gate signal GB, and an emission control signal EM may have a conduction voltage during some sections and may have a turn-off voltage during other sections. The conduction voltage and the turn-off voltage of each of the first gate signal GW, the fourth gate signal GB, and the emission control signal EM may be a low-level voltage and a high-level voltage, respectively. The conduction voltage and the turn-off voltage of each of the second gate signal GI and the third gate signal GC may be a high-level voltage and a low-level voltage, respectively.

[0079] The address scan period AS may include a first non-emission period ND1 in which the pixel PX does not emit light and a first emission period DD1 in which the pixel PX emits light. The first non-emission period ND1 may include a first period P1, a second period P2, a third period P3, and a fourth period P4.

[0080] In the first period P1, the third gate signal GC having a conduction voltage may be supplied to the third gate signal line GCL, and the fourth gate signal GB having a conduction voltage may be supplied to the fourth gate signal line GBL. The first gate signal GW, the second gate signal GI, and the emission control signal EM may be supplied as a turn-off voltage. In the first period P1, the seventh transistor T7 may be turned on so that the second initialization voltage Vaint may be transmitted to the pixel electrode of the organic light-emitting diode OLED to initialize the pixel electrode of the organic light-emitting diode OLED to the second initialization voltage Vaint. In addition, the eighth transistor T8 may be turned on so that the conduction bias voltage VOBS may be transmitted to the second node N2, and the third transistor T3 may be turned on to connect the first transistor T1 in a diode manner.

[0081] In the second period P2, the second gate signal GI having a conduction voltage may be supplied to the second gate signal line GIL. The first gate signal GW, the fourth gate signal GB, and the emission control signal EM may be supplied as a turn-off voltage. In the second period P2, the third gate signal GC having a turn-off voltage may change to a conduction voltage. In the second period P2, the fourth transistor T4 may be turned on so that the first initialization voltage Vint may be transmitted to the first node N1 to initialize the gate of the first transistor T1 to the first initialization voltage Vint. Thereafter, the third transistor T3 may be turned on to transmit the first initialization voltage Vint to the third node N3.

[0082] In the third period P3, the first gate signal GW of the turn-on voltage can be supplied to the first gate signal line GWL, and the third gate signal GC of the turn-on voltage can be supplied to the third gate signal line GCL. The second gate signal GI, the fourth gate signal GB, and the emission control signal EM can be supplied as the turn-off voltage. In the third period P3, the second transistor T2 can be turned on so that the data signal Dm can be transmitted to the second node N2, and thus, the voltage of the second node N2 can be changed to a voltage corresponding to the data signal Dm. Here, the third transistor T3 can be turned on to connect the first transistor T1 in a diode manner, and thus, the voltages of the first node N1 and the third node N3 can be changed according to the voltage change amount of the second node N2. After the first gate signal GW transitions to the turn-off voltage, the third gate signal GC can maintain the turn-on voltage for a specific period of time and then can transition to the turn-off voltage. The storage capacitor Cst can be configured to store the charge corresponding to the difference between the driving voltage ELVDD and the voltage of the first node N1.

[0083] In the fourth period P4, the fourth gate signal GB of the turn-on voltage can be supplied to the fourth gate signal line GBL. The first gate signal GW, the second gate signal GI, the third gate signal GC, and the emission control signal EM can be supplied as the turn-off voltage. In the fourth period P4, the seventh transistor T7 can be turned on to transmit the second initialization voltage Vaint to the pixel electrode of the organic light-emitting diode OLED, and the eighth transistor T8 can be turned on to transmit the turn-on bias voltage VOBS to the second node N2.

[0084] In the first emission period DD1, the emission control signal EM of the turn-on voltage can be supplied to the emission control signal line EML. The first gate signal GW, the second gate signal GI, the third gate signal GC, and the fourth gate signal GB can be supplied as the turn-off voltage. The fifth transistor T5 and the sixth transistor T6 can be turned on by the emission control signal EM, and the driving voltage ELVDD can be supplied to the second node N2 through the fifth transistor T5. The first transistor T1 can output a driving current Id having a magnitude corresponding to the voltage stored in the storage capacitor Cst, and the organic light-emitting diode OLED can emit light with a brightness corresponding to the driving current Id.

[0085] The self-scanning period SS can include a second non-emission period ND2 in which the pixel PX does not emit light and a second emission period DD2 in which the pixel PX emits light. The second non-emission period ND2 can include a fifth period P5.

[0086] During a second non-emission period ND2, a first gate signal GW, a second gate signal GI, a third gate signal GC, and an emission control signal EM may be supplied as turn-off voltages. In a fifth period P5, a fourth gate signal GB of a turn-on voltage may be supplied to a fourth gate signal line GBL, and a seventh transistor T7 and an eighth transistor T8 may be turned on. The seventh transistor T7 may be turned on to transmit a second initialization voltage Vaint to a pixel electrode of the organic light-emitting diode OLED, thereby initializing the pixel electrode of the organic light-emitting diode OLED to the second initialization voltage Vaint. The eighth transistor T8 may be turned on to transmit a turn-on bias voltage VOBS to a second node N2, thereby preventing deterioration of the first transistor T1 during a self-scanning period SS.

[0087] In a second emission period DD2, an emission control signal EM of a turn-on voltage may be supplied to an emission control signal line EML. A first gate signal GW, a second gate signal GI, a third gate signal GC, and a fourth gate signal GB may be supplied as turn-off voltages. A fifth transistor T5 and a sixth transistor T6 may be turned on by the emission control signal EM, and a driving voltage ELVDD may be supplied to the second node N2 through the fifth transistor T5. The first transistor T1 may output a driving current Id having a magnitude corresponding to the voltage stored in a storage capacitor Cst during an address scanning period AS, and the organic light-emitting diode OLED may emit light with a brightness corresponding to the driving current Id.

[0088] Figure 6 is a schematic layout diagram of a part of a display device according to an embodiment, and Figures 7 to 13 is Figure 6 a view of each of the layers of a part of the display device shown in Figure 14 shows a cross-section taken along line I-I' and line II-II' of Figure 6 an exemplary cross-sectional view of a part of the display device shown in

[0089] A display area DA (see Figure 14 ) defined on a substrate 100 (see Figure 1 ) may include a plurality of pixel areas, and a pixel circuit PC (see Figure 2 ) is arranged in each of the plurality of pixel areas. In a first pixel area PCA of a pixel PX (see Figure 2 ) and a second pixel area PCB of another pixel PX, which are two pixel areas adjacent to each other in a first direction (x direction), pixel circuits having a symmetric circuit layout with respect to a virtual first straight line VSL1 extending in a second direction (y direction) may be arranged. For convenience of illustration, reference numerals are given only to one of the elements forming the symmetric circuit layout. Hereinafter, a description is given by referring to Figures 6 to 14 .

[0090] The substrate 100 may include glass, metal, or a polymer resin. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, or a mixture thereof. The substrate 100 may have a layered structure including an organic layer containing a polymer resin and an inorganic layer disposed between the organic layers. The inorganic layer may be a barrier layer and may include a single layer or multiple layers containing an inorganic material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0091] The first conductive layer 1100 may be disposed on the substrate 100. The first conductive layer 1100 may include a conductive material such as Mo, Al, Cu, Ti, etc., and may include a single layer or multiple layers containing the above materials. Referring Figure 7 to, the first conductive layer 1100 may include a first conductive pattern 1110.

[0092] The first conductive pattern 1110 may include a first connection portion, a second connection portion, and a body portion. The first connection portion may extend to the left and right edges of the first conductive pattern 1110 in the first direction (x direction), and the second connection portion may extend to the upper and lower edges of the first conductive pattern 1110 in the second direction (y direction). The body portion of the first conductive pattern 1110 may be the central portion of the pattern connected to the first connection portion and the second connection portion, and may overlap with the channel region A1 of the first transistor T1 described below.

[0093] The first insulating layer 101 may be disposed on the first conductive layer 1100. The first insulating layer 101 may be a buffer layer for preventing impurities from penetrating into the first semiconductor layer 1200. The first insulating layer 101 may include a single layer or multiple layers containing an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0094] The first semiconductor layer 1200 may be disposed on the first insulating layer 101. The first semiconductor layer 1200 may include a silicon-based semiconductor material, for example, amorphous silicon or polycrystalline silicon.

[0095] The second insulating layer 103 may be disposed on the first semiconductor layer 1200. The second insulating layer 103 may include a single layer or multiple layers containing an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0096] The second conductive layer 1300 may be disposed on the second insulating layer 103. The second conductive layer 1300 may include a conductive material such as Mo, Al, Cu, Ti, etc., and may include multiple layers or a single layer containing the above materials.

[0097] Figure 8shows that the first semiconductor layer 1200 and the second conductive layer 1300 overlap each other in the z direction. Referring to Figure 8 , the first semiconductor layer 1200 may include a first semiconductor pattern. The first semiconductor pattern may include a first portion 1201 and a second portion 1202 that form a symmetric circuit layout with respect to a virtual first straight line VSL1. The virtual first straight line VSL1 may be a boundary between a first pixel region PCA and a second pixel region PCB.

[0098] The first semiconductor pattern may include a channel region A1 of a first transistor T1, a channel region A2 of a second transistor T2, a channel region A5 of a fifth transistor T5, a channel region A6 of a sixth transistor T6, a channel region A7 of a seventh transistor T7, and a channel region A8 of an eighth transistor T8. The first semiconductor pattern may be provided integrally, and source regions and drain regions may be disposed at opposite sides of each of the channel regions A1, A2, A5, A6, A7, and A8, respectively. As described above, herein, the source-drain region may refer to an integrally formed doped semiconductor region that collectively forms (i) a source region of the first transistor adjacent to the drain region of the second transistor; (ii) a source region of the first transistor adjacent to the source region of the second transistor; and (iii) a drain region of the first transistor adjacent to the drain region of the second transistor. The source-drain region may be a highly doped region, while the channel region may be a body region between the source region and the drain region, e.g., a less doped region, through which current flows from the source to the drain or vice versa when the transistor switches to the on state.

[0099] The second conductive layer 1300 may include a second conductive pattern 1310, a third conductive pattern 1320, a fourth conductive pattern 1330, a first gate signal line GWL, a second gate signal line GIL, and a fourth gate signal line GBL. The second conductive pattern 1310 to the fourth conductive pattern 1330 may each be an "island" (e.g., a conductive sheet having a closed boundary in the xy plane and interfacing with isolation material). Each of the first gate signal line GWL, the second gate signal line GIL, and the fourth gate signal line GBL may extend substantially in a first direction (x direction). The first gate signal line GWL may be configured to transmit a first gate signal GW (see Figure 2 ) to pixel circuits arranged in the same pixel row, the second gate signal line GIL may be configured to transmit a second gate signal GI (see Figure 2 ) to pixel circuits arranged in the same pixel row, and the fourth gate signal line GBL may be configured to transmit a fourth gate signal GB (see Figure 2 ) to pixel circuits arranged in the same pixel row.

[0100] The channel region A1 of the first transistor T1 may overlap with the second conductive pattern 1310 and may have a bent shape (e.g., U-shaped). The second conductive pattern 1310 may be the gate electrode G1 (an example of the "first electrode") of the first transistor T1. The source region S1 and the drain region D1 may be respectively disposed at opposite sides of the channel region A1 of the first transistor T1.

[0101] The channel region A2 of the second transistor T2 may overlap with the first gate signal line GWL. The portion of the first gate signal line GWL that overlaps with the channel region A2 of the second transistor T2 may be the gate electrode G2 of the second transistor T2. The source region S2 and the drain region D2 may be respectively disposed at opposite sides of the channel region A2 of the second transistor T2. The drain region D2 of the second transistor T2 may be connected to the source region S1 of the first transistor T1. In other words, the region between the channel region A2 of the second transistor T2 and the channel region A1 of the first transistor T1 may be indicated as the source-drain region. The channel region A2 of the second transistor T2 may extend from the source-drain region, and the source region S2 of the second transistor T2 may be indicated as the source / drain region (because if the P-type second transistor T2 is replaced with an N-type transistor in other embodiments, it may be feasible to replace the connection from the source region S2 to the data line DL with a connection from the drain region D2 of the second transistor T2 to the data line DL).

[0102] The channel region A5 of the fifth transistor T5 may overlap with the third conductive pattern 1320. The third conductive pattern 1320 may be the gate electrode G5 (an example of the "second electrode") of the fifth transistor T5. The source region S5 and the drain region D5 may be respectively disposed at opposite sides of the channel region A5 of the fifth transistor T5. The drain region D5 of the fifth transistor T5 may be connected to the source region S1 of the first transistor T1. A first source-drain region SD1 may be disposed between the channel region A1 of the first transistor T1 and the channel region A5 of the fifth transistor T5. The channel region A5 of the fifth transistor T5 in the first pixel region PCA may extend from the first source-drain region SD1 and the source region S5 of the fifth transistor T5 in the first pixel region PCA may be indicated as the source / drain region, or may be indicated as the source-drain region when integrally formed (e.g., integrally connected) with the source region S5 of the second pixel region PCB. It should be noted that in other embodiments, the source region S5 of the first pixel region PCA is separated from the source region S5 of the second pixel region PCB.

[0103] According to an embodiment, the source region S5 of the fifth transistor T5 may be arranged to be spaced apart from the gate electrode G1 of the first transistor T1 in a first direction (x direction). For example, the source region S5 of the fifth transistor T5 may be arranged to overlap with a virtual second straight line VSL2 that extends across a second conductive pattern 1310 in each of the first pixel region PCA and the second pixel region PCB in the first direction (x direction).

[0104] According to an embodiment, the first part 1201 and the second part 1202 of the first semiconductor pattern may be connected to each other in the source region S5 of the fifth transistor T5. In other words, the source region S5 of the fifth transistor T5 arranged in the first pixel region PCA may be connected to the source region S5 of the fifth transistor T5 arranged in the second pixel region PCB.

[0105] The channel region A6 of the sixth transistor T6 may overlap with the fourth conductive pattern 1330. The fourth conductive pattern 1330 may be the gate electrode G6 of the sixth transistor T6. The source region S6 and the drain region D6 may be respectively arranged at opposite sides of the channel region A6 of the sixth transistor T6. The source region S6 of the sixth transistor T6 may be connected to the drain region D1 of the first transistor T1.

[0106] The channel region A7 of the seventh transistor T7 may overlap with the fourth gate signal line GBL. The portion of the fourth gate signal line GBL that overlaps with the channel region A7 of the seventh transistor T7 may be the gate electrode G7 of the seventh transistor T7. The source region S7 and the drain region D7 may be respectively arranged at opposite sides of the channel region A7 of the seventh transistor T7. The drain region D7 of the seventh transistor T7 may be connected to the drain region D6 of the sixth transistor T6.

[0107] The channel region A8 of the eighth transistor T8 may overlap with the fourth gate signal line GBL. The portion of the fourth gate signal line GBL that overlaps with the channel region A8 of the eighth transistor T8 may be the gate electrode G8 of the eighth transistor T8. The source region S8 and the drain region D8 may be respectively arranged at opposite sides of the channel region A8 of the eighth transistor T8. The drain region D8 of the eighth transistor T8 may be connected to the source region S1 of the first transistor T1. According to an embodiment, the first part 1201 and the second part 1202 of the first semiconductor pattern may be connected to each other in the source region S8 of the eighth transistor T8. In other words, the source region S8 of the eighth transistor T8 arranged in the first pixel region PCA may be connected to the source region S8 of the eighth transistor T8 arranged in the second pixel region PCB.

[0108] The third insulating layer 105 may be provided on the second conductive layer 1300. The third insulating layer 105 may include a single layer or multiple layers containing an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0109] The third conductive layer 1400 may be disposed on the third insulating layer 105. The third conductive layer 1400 may include a conductive material such as Mo, Al, Cu, Ti, etc., and may include a multilayer or a single layer including the above materials. Refer to Figure 9 , the third conductive layer 1400 may include a fifth conductive pattern 1410, a sixth conductive pattern 1420, and a first initialization voltage line VL1.

[0110] The fifth conductive pattern 1410 may include a connection portion and a body portion. The connection portion of the fifth conductive pattern 1410 may extend substantially in the first direction (x direction). The body portion of the fifth conductive pattern 1410 may overlap with the second conductive pattern 1310 to form a storage capacitor Cst (see Figure 2 ). For example, the second conductive pattern 1310 may be the first capacitor electrode CE1 of the storage capacitor Cst (see Figure 2 ), and the fifth conductive pattern 1410 may be the second capacitor electrode CE2 of the storage capacitor Cst (see Figure 2 ). The fifth conductive pattern 1410 may include a hole 1410h that exposes a part of the second conductive pattern 1310.

[0111] The sixth conductive pattern 1420 may be provided in an island shape. The sixth conductive pattern 1420 may overlap with the channel region A3 of the third transistor T3. The first initialization voltage line VL1 may extend substantially in the first direction (x direction), and may be electrically connected to pixel circuits arranged in the same pixel row. The first initialization voltage line VL1 may be configured to transmit a first initialization voltage Vint (see Figure 2 ).

[0112] The fourth insulating layer 106 may be disposed on the third conductive layer 1400. The fourth insulating layer 106 may include a single layer or a multilayer including an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0113] The second semiconductor layer 1500 may be disposed on the fourth insulating layer 106. According to an embodiment, the second semiconductor layer 1500 may include an oxide-based semiconductor material, for example, an oxide of at least one material selected from the group consisting of In, Ga, Sn, Zr, V, Hf, Cd, Ge, Cr, Ti, Al, Cs, Ce, and Zn. According to an embodiment, the second semiconductor layer 1500 may include In-Ga-Zn-O (IGZO) or In-Sn-Ga-Zn-O (ITGZO).

[0114] The fourth conductive layer 1600 may be disposed on the second semiconductor layer 1500. The fifth insulating layer 107 may be disposed between the second semiconductor layer 1500 and the fourth conductive layer 1600. According to an embodiment, the fifth insulating layer 107 may have a shape corresponding to that of the fourth conductive layer 1600. The fifth insulating layer 107 may be formed as a single layer or multiple layers including an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride. The fourth conductive layer 1600 may include a conductive material such as Mo, Al, Cu, Ti, etc., and may include a multi-layer or a single layer including the above materials.

[0115] For convenience of explanation, Figure 10 the second semiconductor layer 1500 and the fourth conductive layer 1600 are shown overlapping each other. Referring to Figure 10 , the second semiconductor layer 1500 may include a second semiconductor pattern. The second semiconductor pattern may include a channel region A3 of the third transistor T3 and a channel region A4 of the fourth transistor T4. The second semiconductor pattern may be provided integrally, and source regions and drain regions may be respectively disposed at opposite sides of each of the channel regions A3 and A4.

[0116] The fourth conductive layer 1600 may include a seventh conductive pattern 1610, an eighth conductive pattern 1620, a third gate signal line GCL, an emission control signal line EML, and a conduction bias voltage line VL3. Each of the third gate signal line GCL, the emission control signal line EML, and the conduction bias voltage line VL3 may extend substantially in a first direction (x direction). The third gate signal line GCL may be configured to transmit a third gate signal GC (see Figure 2 ) to pixel circuits arranged in the same pixel row, and the emission control signal line EML may be configured to transmit an emission control signal EM (see Figure 2 ) to pixel circuits arranged in the same pixel row. The conduction bias voltage line VL3 may be configured to transmit a conduction bias voltage VOBS (see Figure 2 ) to pixel circuits arranged in the same pixel row.

[0117] The channel region A3 of the third transistor T3 may overlap with the third gate signal line GCL. A portion of the third gate signal line GCL that overlaps with the channel region A3 of the third transistor T3 may be an upper gate electrode G3 of the third transistor T3. The third gate signal line GCL may be connected to a sixth conductive pattern 1420 through a via hole (“contact hole”) CT4 that passes through the fourth insulating layer 106 and the fifth insulating layer 107. The sixth conductive pattern 1420 may be a lower gate electrode of the third transistor T3 and may be configured to receive the third gate signal GC from the third gate signal line GCL. The source region S3 and the drain region D3 may be respectively disposed at opposite sides of the channel region A3 of the third transistor T3.

[0118] The channel region A4 of the fourth transistor T4 may overlap with the seventh conductive pattern 1610. The seventh conductive pattern 1610 may be electrically connected to the second gate signal line GIL through a via hole (“contact hole”) CT3 that passes through the third insulating layer 105, the fourth insulating layer 106, and the fifth insulating layer 107. The seventh conductive pattern 1610 may be the upper gate electrode G4 of the fourth transistor T4 and may be configured to receive the second gate signal GI from the second gate signal line GIL. A portion of the second gate signal line GIL that overlaps with the channel region A4 of the fourth transistor T4 may be the lower gate electrode of the fourth transistor T4. The source region S4 and the drain region D4 may be disposed on opposite sides of the channel region A4 of the fourth transistor T4, respectively. The drain region D4 of the fourth transistor T4 may be connected to the source region S3 of the third transistor T3. The source region S4 of the fourth transistor T4 may extend substantially in the first direction (x direction) into an adjacent pixel region.

[0119] The emission control signal line EML may be electrically connected to the third conductive pattern 1320 through a via hole (“contact hole”) CT1 that passes through the third insulating layer 105, the fourth insulating layer 106, and the fifth insulating layer 107, and may be electrically connected to the fourth conductive pattern 1330 through a via hole (“contact hole”) CT2 that passes through the third insulating layer 105, the fourth insulating layer 106, and the fifth insulating layer 107. The third conductive pattern 1320 may be the gate electrode G5 of the fifth transistor T5 and may be configured to receive the emission control signal EM from the emission control signal line EML. The fourth conductive pattern 1330 may be the gate electrode G6 of the sixth transistor T6 and may be configured to receive the emission control signal EM from the emission control signal line EML.

[0120] The sixth insulating layer 108 may be disposed on the fourth conductive layer 1600, and the fifth conductive layer 1700 may be disposed on the sixth insulating layer 108. The seventh insulating layer 109 may be disposed on the fifth conductive layer 1700, and the sixth conductive layer 1800 may be disposed on the seventh insulating layer 109. The eighth insulating layer 111 may be disposed on the sixth conductive layer 1800.

[0121] The sixth insulating layer 108 may include a single layer or multiple layers including an inorganic material and / or an organic material. Each of the seventh insulating layer 109 and the eighth insulating layer 111 may include a single layer or multiple layers including an organic material. Here, the inorganic material may include silicon oxide, silicon nitride, silicon oxynitride, etc., and the organic material may include acrylic acid, benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), etc.

[0122] Each of the fifth conductive layer 1700 and the sixth conductive layer 1800 may include a conductive material such as Mo, Al, Cu, Ti, etc., and may include a multi-layer or a single layer including the above materials. According to an embodiment, each of the fifth conductive layer 1700 and the sixth conductive layer 1800 may have a layered structure of Ti / Al / Ti.

[0123] Referring to Figure 11 , the fifth conductive layer 1700 may include a ninth conductive pattern 1710, a tenth conductive pattern 1720, an eleventh conductive pattern 1730, a twelfth conductive pattern 1740, a thirteenth conductive pattern 1750, a fourteenth conductive pattern 1760, a fifteenth conductive pattern 1770, a horizontal data connection line BRL_h, and a second initialization voltage line VL2. Referring to Figure 12 , the sixth conductive layer 1800 may include a sixteenth conductive pattern 1810, a data line DL, a driving voltage line PL, and a vertical data connection line BRL_v.

[0124] The ninth conductive pattern 1710 may be electrically connected to the source region S3 of the third transistor T3 and the drain region D4 of the fourth transistor T4 through a contact hole CT14 passing through the sixth insulating layer 108, and may be electrically connected to the second conductive pattern 1310 through a contact hole CT15 passing through the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108. Through the ninth conductive pattern 1710, the source region S3 of the third transistor T3, the drain region D4 of the fourth transistor T4, the gate electrode G1 of the first transistor T1, and the first capacitor electrode CE1 of the storage capacitor Cst may be electrically connected to each other.

[0125] The tenth conductive pattern 1720 may be electrically connected to the source region S2 of the second transistor T2 through a contact hole CT13 passing through the second insulating layer 103, the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108, and may be electrically connected to the data line DL through a contact hole CT12 passing through the seventh insulating layer 109. The data line DL may extend in the second direction (y direction), and may be configured to transmit a corresponding data signal Dm (see Figure 2 ) to the pixel circuits arranged in the same pixel column. According to an embodiment, the data line DL may overlap with the channel region A5 of the fifth transistor T5. The source region S2 of the second transistor T2 may be configured to receive the data signal Dm from the data line DL through the tenth conductive pattern 1720.

[0126] The eleventh conductive pattern 1730 can be electrically connected to the drain region D3 of the third transistor T3 through the contact hole CT16 passing through the sixth insulating layer 108, and can be electrically connected to the drain region D1 of the first transistor T1 and the source region S6 of the sixth transistor T6 through the contact hole CT17 passing through the second insulating layer 103, the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108. Through the eleventh conductive pattern 1730, the drain region D3 of the third transistor T3, the drain region D1 of the first transistor T1, and the source region S6 of the sixth transistor T6 can be electrically connected to each other.

[0127] The twelfth conductive pattern 1740 can include a connection portion and a main body portion. The connection portion of the twelfth conductive pattern 1740 can extend in the first direction (x direction). The twelfth conductive pattern 1740 can be electrically connected to the fifth conductive pattern 1410 through the contact hole CT6 passing through the fourth insulating layer 106 and the sixth insulating layer 108, electrically connected to the source region S5 of the fifth transistor T5 through the contact hole CT7 passing through the second insulating layer 103, the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108, and connected to the driving voltage line PL through the contact hole CT18 passing through the seventh insulating layer 109. The source region S5 of the fifth transistor T5 and the second capacitor electrode CE2 of the storage capacitor Cst (see Figure 2 ) (see Figure 2 ) can be configured to receive the driving voltage ELVDD (see Figure 2 ) from the driving voltage line PL through the twelfth conductive pattern 1740.

[0128] The thirteenth conductive pattern 1750 can be electrically connected to the drain region D6 of the sixth transistor and the drain region D7 of the seventh transistor T7 through the contact hole CT20 passing through the second insulating layer 103, the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108, and can be electrically connected to the sixteenth conductive pattern 1810 through the contact hole CT19 passing through the seventh insulating layer 109. The sixteenth conductive pattern 1810 can be electrically connected to the pixel electrode 210 of the organic light emitting diode OLED through the contact hole CT21 passing through the eighth insulating layer 111. The drain region D6 of the sixth transistor T6, the drain region D7 of the seventh transistor T7, and the pixel electrode 210 of the organic light emitting diode OLED can be electrically connected to each other through the thirteenth conductive pattern 1750 and the sixteenth conductive pattern 1810.

[0129] The fourteenth conductive pattern 1760 can be electrically connected to the source region S4 of the fourth transistor T4 through a contact hole CT5 passing through the sixth insulating layer 108, and can be electrically connected to the first initialization voltage line VL1 through a contact hole CT11 passing through the fourth insulating layer 106 and the sixth insulating layer 108. The source region S4 of the fourth transistor T4 can be configured to receive a first initialization voltage Vint from the first initialization voltage line VL1 through the fourteenth conductive pattern 1760 (see Figure 2 ).

[0130] The fifteenth conductive pattern 1770 can be electrically connected to the conduction bias voltage line VL3 through a contact hole CT9 passing through the sixth insulating layer 108, and can be electrically connected to the source region S8 of the eighth transistor T8 through a contact hole CT8 passing through the second insulating layer 103, the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108. The source region S8 of the eighth transistor T8 can be configured to receive a conduction bias voltage VOBS from the conduction bias voltage line VL3 through the fifteenth conductive pattern 1770 (see Figure 2 ).

[0131] The horizontal data connection line BRL_h can extend in a first direction (x direction). The vertical data connection line BRL_v can extend in a second direction (y direction) intersecting the first direction (x direction). Figure 6 , Figure 11 and Figure 12 The horizontal data connection line BRL_h and the vertical data connection line BRL_v shown in Figure 2 can be electrically insulated from each other by the seventh insulating layer 109. However, in some pixel regions, the horizontal data connection line BRL_h and the corresponding vertical data connection line BRL_v can be electrically connected to each other through a contact hole passing through the seventh insulating layer 109. The horizontal data connection line BRL_h and the vertical data connection line BRL_v can be configured to transmit a data signal Dm (see Figure 2 ) to the corresponding pixel circuit PC (see

[0132] The second initialization voltage line VL2 may extend in a first direction (x direction) and may be electrically connected to pixel circuits arranged in the same pixel row. The second initialization voltage line VL2 may be electrically connected to the source region S7 of the seventh transistor T7 through a contact hole CT10 that passes through the second insulating layer 103, the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108. The source region S7 of the seventh transistor T7 may be configured to receive a second initialization voltage Vaint from the second initialization voltage line VL2 (see Figure 2 ).

[0133] The driving voltage line PL may extend in a second direction (y direction) and may be electrically connected to pixel circuits arranged in the same pixel column. The driving voltage line PL may overlap with the third transistor T3 and the fourth transistor T4, and thus may reduce an electrical effect caused by the pixel electrode 210 or the like.

[0134] The seventh conductive layer 1900 may be provided on the eighth insulating layer 111. Figure 13 is a layout diagram for describing the arrangement of the first pixel electrode 1901, the second pixel electrode 1902, and the third pixel electrode 1903, where Figure 14 the pixel electrode 210 of the organic light emitting diode OLED shown in may correspond to any one of the first pixel electrode 1901, the second pixel electrode 1902, and the third pixel electrode 1903. The first pixel electrode 1901, the second pixel electrode 1902, and the third pixel electrode 1903 may be repeatedly arranged in the first direction (x direction) and the second direction (y direction) according to a specific pattern. Each of the first pixel electrode 1901, the second pixel electrode 1902, and the third pixel electrode 1903 may be electrically connected to a lower conductive pattern (e.g., the sixteenth conductive pattern 1810) through a contact hole CT21 that passes through the eighth insulating layer 111.

[0135] According to an embodiment, the first pixel electrode 1901, the second pixel electrode 1902, and the third pixel electrode 1903 may be arranged as Arrangement type (or diamond arrangement type). For example, the first emission region EA1 defined in the first pixel electrode 1901 can emit red light, the second emission region EA2 defined in the second pixel electrode 1902 can emit green light, and the third emission region EA3 defined in the third pixel electrode 1903 can emit blue light. Four second pixel electrodes 1902 can be arranged relative to the first pixel electrode 1901 or the third pixel electrode 1903. The first pixel electrode 1901 and the third pixel electrode 1903 can have a substantially chamfered quadrilateral shape. The second pixel electrode 1902 can have an inclined octagonal shape. However, the present disclosure is not limited thereto. The first pixel electrode 1901, the second pixel electrode 1902, and the third pixel electrode 1903 can be arranged in various forms including a stripe arrangement, a mosaic arrangement, etc., and each of the first pixel electrode 1901, the second pixel electrode 1902, and the third pixel electrode 1903 can have various shapes such as other polygonal shapes, a circular shape, an oval shape, etc.

[0136] According to an embodiment, the pixel circuit arranged in the first pixel region PCA can be electrically connected to the first pixel electrode 1901 or the third pixel electrode 1903, and the pixel circuit arranged in the second pixel region PCB can be electrically connected to the second pixel electrode 1902. The first pixel electrode 1901 or the third pixel electrode 1903 can be arranged to overlap with the fifth transistor T5, and the second pixel electrode 1902 can be arranged to overlap with the third transistor T3 and the fourth transistor T4.

[0137] Referring to Figure 14 , the organic light emitting diode OLED can include a pixel electrode 210, a counter electrode 230 facing the pixel electrode 210, and an emission layer 220 disposed between the pixel electrode 210 and the counter electrode 230.

[0138] The pixel electrode 210 can include a transmissive or semi-transmissive electrode or a reflective electrode. According to an embodiment, the pixel electrode 210 can include a reflective layer including at least one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and their compounds, and a transparent or semi-transparent electrode layer disposed on the reflective layer. The transparent or semi-transparent electrode layer can include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). According to an embodiment, the pixel electrode 210 can include ITO / Ag / ITO.

[0139] The pixel defining layer PDL may be disposed on the eighth insulating layer 111 to cover the edge of the pixel electrode 210. The pixel defining layer PDL may define an opening exposing the central portion of the pixel electrode 210. The emission region of the organic light emitting diode OLED may be defined by the opening of the pixel defining layer PDL.

[0140] The pixel defining layer PDL may increase the distance between the edge of the pixel electrode 210 and the counter electrode 230, thereby preventing arcing or the like at the edge of the pixel electrode 210. The pixel defining layer PDL may include at least one organic material selected from the group consisting of polyimide, polyamide, acrylic resin, BCB, and phenolic resin. According to an embodiment, the pixel defining layer PDL may include a light-shielding material and may be provided in black. The light-shielding material may include: a resin or paste containing carbon black, carbon nanotubes, and a black dye; metal particles such as Ni, Al, Mo, and their alloys; metal oxide particles (e.g., chromium oxide); metal nitride particles (e.g., chromium nitride); or the like.

[0141] The emission layer 220 may be disposed on the pixel electrode 210. The emission layer 220 may include a high molecular weight or low molecular weight organic material that emits light of a specific color. The emission layer 220 may also include a metal-containing compound such as an organometallic compound and an inorganic material such as a quantum dot. According to an embodiment, the emission layer 220 may be patterned to correspond to the pixel electrode 210.

[0142] The first functional layer may be disposed between the emission layer 220 and the pixel electrode 210, and the second functional layer may be disposed between the emission layer 220 and the counter electrode 230. The first functional layer may be a hole transport layer. Alternatively, the first functional layer may include a hole injection layer and a hole transport layer. The second functional layer may include an electron transport layer and / or an electron injection layer. The first functional layer and the second functional layer may be integrally formed to correspond to a plurality of organic light emitting diodes OLED. The first functional layer or the second functional layer may be omitted.

[0143] The counter electrode 230 may be disposed on the emission layer 220. The counter electrode 230 may include Li, Ag, Mg, Al, Al-Li, Ca, Mg-In, Mg-Ag, Yb, Ag-Yb, ITO, IZO, or any combination thereof. The counter electrode 230 may be a transmissive electrode, a transflective electrode, or a reflective electrode. The counter electrode 230 may be integrally formed to correspond to a plurality of organic light emitting diodes OLED.

[0144] As Figures 6 to 14As shown, the emission control signal line EML may overlap with the source region S1 of the first transistor T1 and the drain region D5 of the fifth transistor T5 at the first source-drain region SD1 where they are connected to each other. The emission control signal line EML may be included in the fourth conductive layer 1600 and may be sufficiently spaced apart from the first source-drain region SD1 in the thickness direction (z or "vertical" direction) by the second insulating layer 103, the third insulating layer 105, the fourth insulating layer 106, and the fifth insulating layer 107 to avoid performance degradation as in conventional display devices. For example, in the case of the layout of the present embodiment, in the region of the first source-drain region SD1 that overlaps with the emission control signal line EML, unnecessary transistors may not be formed.

[0145] According to the comparative example, when the emission control signal line is included in the second conductive layer like the first gate signal line and the fourth gate signal line, unnecessary transistors may be formed in the first source-drain region. When a conductive pattern for connecting the source region of the first transistor to the drain region of the fifth transistor is formed to prevent the formation of unnecessary transistors, the display quality may deteriorate due to the parasitic capacitance between the conductive pattern and adjacent elements (e.g., data lines, etc.).

[0146] According to the embodiment, the emission control signal line EML may be included in the fourth conductive layer 1600, and thus, the source region S1 of the first transistor T1 and the drain region D5 of the fifth transistor T5 may be connected to each other in the first semiconductor layer 1200 without using an additional conductive layer. Therefore, the coupling between the source region S1 of the first transistor T1 and the data line DL can be prevented or reduced, and thus, the display device 10 (see Figure 1 ) can display high-quality images.

[0147] Figure 15 is a schematic layout diagram of a part of a display device according to another embodiment, and Figures 16 to 22 is Figure 15 a view of each of the layers of a part of the display device shown in Figure 23 is Figure 15 a schematic cross-sectional view of a part of the display device shown in

[0148] Figures 15 to 23 shows a case where the emission control signal line EML may be included in the fifth conductive layer 2700. The display area DA defined in the substrate 100 (see Figure 1 ) may include a plurality of pixel regions, and a pixel circuit PC is arranged in each of the plurality of pixel regions (see Figure 2)。In the first pixel region PCA and the second pixel region PCB, which are two pixel regions adjacent to each other in the first direction (x direction), pixel circuits having a symmetric circuit layout with respect to a virtual first straight line VSL1 extending in the second direction (y direction) may be arranged. For the convenience of illustration, reference numerals are assigned only to one of the elements forming the symmetric circuit layout. In addition, elements that are the same as or substantially the same as the elements described with reference to Figures 6 to 14 are not described again. Figure 23 The cross-sectional view of Figure 15 schematically shows a cross-section of the display device taken along the line III-III' of Figures 15 to 23 . Descriptions are given below by referring to

[0149] The substrate 100 may include glass, metal, or polymer resin. The substrate 100 may have a layered structure including an organic layer containing a polymer resin and an inorganic layer disposed between the organic layers.

[0150] The first conductive layer 2100 may be disposed on the substrate 100. Referring to Figure 16 , the first conductive layer 2100 may include a first conductive pattern 2110. The first conductive pattern 2110 may include a first connection portion, a second connection portion, a third connection portion, and a body portion. The first connection portion may extend in the first direction (x direction), and the second connection portion may extend in the second direction (y direction). The third connection portion may extend in the first direction (x direction) and may connect the first conductive pattern 2110 in the first pixel region PCA to the first conductive pattern 2110 in the second pixel region PCB. The body portion of the first conductive pattern 2110 may overlap with the channel region A1 of the first transistor T1 described below.

[0151] The first insulating layer 101 may be disposed on the first conductive layer 2100, and the first semiconductor layer 2200 may be disposed on the first insulating layer 101. The first semiconductor layer 2200 may include a silicon-based semiconductor material, such as amorphous silicon or polycrystalline silicon.

[0152] The second insulating layer 103 may be disposed on the first semiconductor layer 2200, and the second conductive layer 2300 may be disposed on the second insulating layer 103. The second conductive layer 2300 may include a conductive material such as Mo, Al, Cu, Ti, etc., and may include a multi-layer or a single layer containing the above materials.

[0153] For the convenience of explanation, Figure 17 it is shown that the first semiconductor layer 2200 and the second conductive layer 2300 overlap each other. Referring to Figure 17, the first semiconductor layer 2200 may include a first semiconductor pattern. The first semiconductor pattern may include a first portion 2201 and a second portion 2202 that form a symmetric circuit layout with respect to a virtual first straight line VSL1.

[0154] The first semiconductor pattern may include a channel region A1 of the first transistor T1, a channel region A2 of the second transistor T2, a channel region A5 of the fifth transistor T5, a channel region A6 of the sixth transistor T6, a channel region A7 of the seventh transistor T7, and a channel region A8 of the eighth transistor T8. The first semiconductor pattern may be provided integrally, and source regions and drain regions may be disposed at opposite sides of each of the channel regions A1, A2, A5, A6, A7, and A8, respectively.

[0155] The second conductive layer 2300 may include a second conductive pattern 2310, a third conductive pattern 2320, a fourth conductive pattern 2330, a first gate signal line GWL, a fourth gate signal line GBL, and a first initialization voltage line VL1. The second conductive pattern 2310, the third conductive pattern 2320, and the fourth conductive pattern 2330 may be provided as island shapes. Each of the first gate signal line GWL, the fourth gate signal line GBL, and the first initialization voltage line VL1 may extend substantially in a first direction (x direction). The first gate signal line GWL may be configured to transmit a first gate signal GW (see Figure 2 ) to pixel circuits arranged in the same pixel row, the fourth gate signal line GBL may be configured to transmit a fourth gate signal GB (see Figure 2 ) to pixel circuits arranged in the same pixel row, and the first initialization voltage line VL1 may be configured to transmit a first initialization voltage Vint (see Figure 2 ) to pixel circuits arranged in the same pixel row.

[0156] The channel region A1 of the first transistor T1 may overlap with the second conductive pattern 2310 and may have a bent shape. The second conductive pattern 2310 may be a gate electrode G1 of the first transistor T1. A source region S1 and a drain region D1 may be disposed at opposite sides of the channel region A1 of the first transistor T1, respectively.

[0157] The channel region A2 of the second transistor T2 may overlap with the first gate signal line GWL. A portion of the first gate signal line GWL that overlaps with the channel region A2 of the second transistor T2 may be a gate electrode G2 of the second transistor T2. A source region S2 and a drain region D2 may be disposed at opposite sides of the channel region A2 of the second transistor T2, respectively. The drain region D2 of the second transistor T2 may be connected to the source region S1 of the first transistor T1.

[0158] The channel region A5 of the fifth transistor T5 may overlap with the third conductive pattern 2320. The third conductive pattern 2320 may be the gate electrode G5 of the fifth transistor T5. The source region S5 and the drain region D5 may be disposed on opposite sides of the channel region A5 of the fifth transistor T5, respectively. The drain region D5 of the fifth transistor T5 may be connected to the source region S1 of the first transistor T1.

[0159] According to an embodiment, the source region S5 of the fifth transistor T5 may be disposed to be spaced apart from the gate electrode G1 of the first transistor T1 in a first direction (x direction). For example, the source region S5 of the fifth transistor T5 may be disposed to overlap with a virtual second straight line VSL2 that extends across the second conductive pattern 2310 in each of the first pixel region PCA and the second pixel region PCB in the first direction (x direction).

[0160] According to an embodiment, the first part 2201 and the second part 2202 of the first semiconductor pattern may be connected to each other in the source region S5 of the fifth transistor T5. In other words, the source region S5 of the fifth transistor T5 disposed in the first pixel region PCA may be connected to the source region S5 of the fifth transistor T5 disposed in the second pixel region PCB.

[0161] The channel region A6 of the sixth transistor T6 may overlap with the fourth conductive pattern 2330. The source region S6 and the drain region D6 may be disposed on opposite sides of the channel region A6 of the sixth transistor T6, respectively. The source region S6 of the sixth transistor T6 may be connected to the drain region D1 of the first transistor T1.

[0162] The channel region A7 of the seventh transistor T7 may overlap with the fourth gate signal line GBL. The portion of the fourth gate signal line GBL that overlaps with the channel region A7 of the seventh transistor T7 may be the gate electrode G7 of the seventh transistor T7. The source region S7 and the drain region D7 may be disposed on opposite sides of the channel region A7 of the seventh transistor T7, respectively. The drain region D7 of the seventh transistor T7 may be connected to the drain region D6 of the sixth transistor T6.

[0163] The channel region A8 of the eighth transistor T8 may overlap with the fourth gate signal line GBL. The portion of the fourth gate signal line GBL that overlaps with the channel region A8 of the eighth transistor T8 may be the gate electrode G8 of the eighth transistor T8. The source region S8 and the drain region D8 may be disposed on opposite sides of the channel region A8 of the eighth transistor T8, respectively. The drain region D8 of the eighth transistor T8 may be connected to the source region S1 of the first transistor T1.

[0164] The third insulating layer 105 may be disposed on the second conductive layer 2300, and the third conductive layer 2400 may be disposed on the third insulating layer 105. The third conductive layer 2400 may include a conductive material such as Mo, Al, Cu, Ti, etc., and may include a multi-layer or a single layer including the above materials. Referring to Figure 18 , the third conductive layer 2400 may include a fifth conductive pattern 2410, a second gate signal line GILa, and a third gate signal line GCLa.

[0165] The fifth conductive pattern 2410 may include a connection portion and a body portion. The connection portion of the fifth conductive pattern 2410 may extend substantially in the first direction (x direction). The body portion of the fifth conductive pattern 2410 may overlap with the second conductive pattern 2310 to form a storage capacitor Cst (see Figure 2 ). For example, the second conductive pattern 2310 may be the first capacitor electrode CE1 of the storage capacitor Cst (see Figure 2 ), and the fifth conductive pattern 2410 may be the second capacitor electrode CE2 of the storage capacitor Cst (see Figure 2 ). The fifth conductive pattern 2410 may include a hole 2410h exposing a part of the second conductive pattern 2310.

[0166] The second gate signal line GILa may extend in the first direction (x direction), and may be configured to transmit a second gate signal GI (see Figure 2 ) to pixel circuits arranged in the same pixel row. The third gate signal line GCLa may extend in the first direction (x direction), and may be configured to transmit a third gate signal GC (see Figure 2 ) to pixel circuits arranged in the same pixel row.

[0167] The second semiconductor layer 2500 may be disposed on the fourth insulating layer 106. According to an embodiment, the second semiconductor layer 2500 may include an oxide-based semiconductor material, for example, an oxide of at least one material selected from the group consisting of In, Ga, Sn, Zr, V, Hf, Cd, Ge, Cr, Ti, Al, Cs, Ce, and Zn. According to an embodiment, the second semiconductor layer 2500 may include IGZO or ITGZO.

[0168] The fourth conductive layer 2600 may be disposed on the second semiconductor layer 2500, and the fifth insulating layer 107 (see Figure 14 ) may be disposed between the second semiconductor layer 2500 and the fourth conductive layer 2600. According to an embodiment, the fifth insulating layer 107 may have a shape corresponding to the shape of the fourth conductive layer 2600.

[0169] For convenience of explanation, Figure 19It shows that the second semiconductor layer 2500 and the fourth conductive layer 2600 overlap each other. Referring to Figure 19 , the second semiconductor layer 2500 may include a second semiconductor pattern. The second semiconductor pattern may include a channel region A3 of the third transistor T3 and a channel region A4 of the fourth transistor T4. The second semiconductor pattern may be provided integrally, and source regions and drain regions may be respectively disposed at opposite sides of each of the channel regions A3 and A4.

[0170] The fourth conductive layer 2600 may include a 2-2nd gate signal line GILb, a 3-2nd gate signal line GCLb, and a conduction bias voltage line VL3. The 2-2nd gate signal line GILb, the 3-2nd gate signal line GCLb, and the conduction bias voltage line VL3 may extend substantially in a first direction (x direction). The 2-2nd gate signal line GILb may be configured to transmit a second gate signal GI (see Figure 2 ) to pixel circuits arranged in the same pixel row, the 3-2nd gate signal line GCLb may be configured to transmit a third gate signal GC (see Figure 2 ) to pixel circuits arranged in the same pixel row, and the conduction bias voltage line VL3 may be configured to transmit a conduction bias voltage VOBS (see Figure 2 ) to pixel circuits arranged in the same pixel row.

[0171] The channel region A3 of the third transistor T3 may overlap with a 3-1st gate signal line GCLa and a 3-2nd gate signal line GCLb. A portion of the 3-1st gate signal line GCLa that overlaps with the channel region A3 of the third transistor T3 may be a lower gate electrode of the third transistor T3, and a portion of the 3-2nd gate signal line GCLb that overlaps with the channel region A3 of the third transistor T3 may be an upper gate electrode G3 of the third transistor T3. Source region S3 and drain region D3 may be respectively disposed at opposite sides of the channel region A3 of the third transistor T3.

[0172] The channel region A4 of the fourth transistor T4 may overlap with a 2-1st gate signal line GILa and a 2-2nd gate signal line GILb. A portion of the 2-1st gate signal line GILa that overlaps with the channel region A4 of the fourth transistor T4 may be a lower gate electrode of the fourth transistor T4, and a portion of the 2-2nd gate signal line GILb that overlaps with the channel region A4 of the fourth transistor T4 may be an upper gate electrode G4 of the fourth transistor T4. The drain region D4 of the fourth transistor T4 may be connected to the source region S3 of the third transistor T3. The source region S4 of the fourth transistor T4 may extend substantially in the first direction (x direction) to an adjacent pixel region.

[0173] The sixth insulating layer 108 may be disposed on the fourth conductive layer 2600, and the fifth conductive layer 2700 may be disposed on the sixth insulating layer 108. The seventh insulating layer 109 may be disposed on the fifth conductive layer 2700, and the sixth conductive layer 2800 may be disposed on the seventh insulating layer 109. The eighth insulating layer 111 may be disposed on the sixth conductive layer 2800.

[0174] Each of the fifth conductive layer 2700 and the sixth conductive layer 2800 may include a conductive material such as Mo, Al, Cu, Ti, etc., and may include a multi-layer or a single layer containing the above materials. According to an embodiment, each of the fifth conductive layer 2700 and the sixth conductive layer 2800 may have a layered structure of Ti / Al / Ti.

[0175] Referring to Figure 20 , the fifth conductive layer 2700 may include a sixth conductive pattern 2710, a seventh conductive pattern 2720, an eighth conductive pattern 2730, a ninth conductive pattern 2740, a tenth conductive pattern 2750, an eleventh conductive pattern 2760, a twelfth conductive pattern 2770, a thirteenth conductive pattern 2780, a horizontal data connection line BRL_h, an emission control signal line EML, a 2-1 initialization voltage line VL2a, and a 2-2 initialization voltage line VL2b. Referring to Figure 21 , the sixth conductive layer 2800 may include a fourteenth conductive pattern 2801, a data line DL, a driving voltage line PL, and a vertical data connection line BRL_v.

[0176] The sixth conductive pattern 2710 may be electrically connected to the source region S4 of the fourth transistor T4 through a contact hole CT10 passing through the sixth insulating layer 108, and may be electrically connected to the first initialization voltage line VL1 through a contact hole CT11 passing through the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108. The source region S4 of the fourth transistor T4 may be configured to receive a first initialization voltage Vint from the first initialization voltage line VL1 through the sixth conductive pattern 2710 (see Figure 2 ).

[0177] The seventh conductive pattern 2720 may be electrically connected to the conduction bias voltage line VL3 through a contact hole CT7 passing through the sixth insulating layer 108, and may be electrically connected to the source region S8 of the eighth transistor T8 through a contact hole CT8 passing through the second insulating layer 103, the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108. The source region S8 of the eighth transistor T8 may be configured to receive a conduction bias voltage VOBS from the conduction bias voltage line VL3 through the seventh conductive pattern 2720 (see Figure 2 ).

[0178] The eighth conductive pattern 2730 can be electrically connected to the source region S2 of the second transistor T2 through a contact hole CT13 passing through the second insulating layer 103, the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108, and can be electrically connected to the data line DL through a contact hole CT14 passing through the seventh insulating layer 109. The data line DL can extend in the second direction (y direction), and can be configured to transmit a corresponding data signal Dm (see Figure 2 ) to pixel circuits arranged in the same pixel column. The source region S2 of the second transistor T2 can receive the data signal Dm from the data line DL through the eighth conductive pattern 2730.

[0179] The ninth conductive pattern 2740 can be electrically connected to the longitudinal data connection line BRL_v through a contact hole CT12 passing through the seventh insulating layer 109.

[0180] The tenth conductive pattern 2750 can be electrically connected to the source region S3 of the third transistor T3 and the drain region D4 of the fourth transistor T4 through a contact hole CT15 passing through the sixth insulating layer 108, and can be electrically connected to the second conductive pattern 2310 through a contact hole CT18 passing through the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108. Through the tenth conductive pattern 2750, the source region S3 of the third transistor T3, the drain region D4 of the fourth transistor T4, the gate electrode G1 of the first transistor T1, and the first capacitor electrode CE1 (see Figure 2 ) of the storage capacitor Cst (see Figure 2 ) can be electrically connected to each other.

[0181] The eleventh conductive pattern 2760 can be electrically connected to the fifth conductive pattern 2410 through a contact hole CT17 passing through the fourth insulating layer 106 and the sixth insulating layer 108, can be electrically connected to the source region S5 of the fifth transistor T5 through a contact hole CT5 passing through the second insulating layer 103, the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108, and is connected to the driving voltage line PL through a contact hole CT16 passing through the seventh insulating layer 109. The source region S5 of the fifth transistor T5 and the second capacitor electrode CE2 (see Figure 2 ) of the storage capacitor Cst (see Figure 2 ) can be configured to receive the driving voltage ELVDD (see Figure 2 ) from the driving voltage line PL through the eleventh conductive pattern 2760.

[0182] The twelfth conductive pattern 2770 may be electrically connected to the drain region D3 of the third transistor T3 through a contact hole CT1 passing through the sixth insulating layer 108, and may be electrically connected to the drain region D1 of the first transistor T1 and the source region S6 of the sixth transistor T6 through a contact hole CT2 passing through the second insulating layer 103, the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108. Through the twelfth conductive pattern 2770, the drain region D3 of the third transistor T3, the drain region D1 of the first transistor T1, and the source region S6 of the sixth transistor T6 may be electrically connected to each other.

[0183] The thirteenth conductive pattern 2780 may be electrically connected to the drain region D6 of the sixth transistor and the drain region D7 of the seventh transistor T7 through a contact hole CT20 passing through the second insulating layer 103, the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108, and may be electrically connected to the fourteenth conductive pattern 2801 through a contact hole CT19 passing through the seventh insulating layer 109. The fourteenth conductive pattern 2801 may be electrically connected to the pixel electrode 210 of the organic light emitting diode OLED through a contact hole CT21 passing through the eighth insulating layer 111.

[0184] The drain region D6 of the sixth transistor T6 , the drain region D7 of the seventh transistor T7 , and the pixel electrode 210 of the organic light emitting diode OLED may be electrically connected to each other through the thirteenth conductive pattern 2780 and the fourteenth conductive pattern 2801 .

[0185] The transverse data link line BRL_h may extend in a first direction (x direction), and the longitudinal data link line BRL_v may extend in a second direction (y direction) crossing the first direction (x direction). Figure 15 , Figure 20 and Figure 21 The horizontal data link line BRL_h and the vertical data link line BRL_v shown in FIG. 2 are electrically insulated from each other. However, in some pixel regions, the horizontal data link line BRL_h and the vertical data link line BRL_v may be electrically connected to each other through the ninth conductive pattern 2740. The horizontal data link line BRL_h and the vertical data link line BRL_v may be configured to transmit the data signal Dm (see FIG. Figure 2 ) is transmitted to the corresponding pixel circuit PC (see Figure 2 ). According to an embodiment, the vertical data link line BRL_v may overlap the channel area A5 of the fifth transistor T5.

[0186] The emission control signal line EML may extend in a first direction (x direction) and may be configured to transmit the emission control signal EM (see Figure 2)It is transmitted to the pixel circuits arranged in the same row. The emission control signal line EML can be electrically connected to the third conductive pattern 2320 through the contact hole CT6 passing through the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108, and can be electrically connected to the fourth conductive pattern 2330 through the contact hole CT3 passing through the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108. The third conductive pattern 2320 can be the gate electrode G5 of the fifth transistor T5, and the fourth conductive pattern 2330 can be the gate electrode G6 of the sixth transistor T6.

[0187] Each of the 2-1 initialization voltage line VL2a and the 2-2 initialization voltage line VL2b can correspond to the second initialization voltage line VL2 described with reference to Figure 2 For example, the pixel circuits arranged in the first pixel region PCA can be configured to receive the 2-1 initialization voltage from the 2-1 initialization voltage line VL2a, and the pixel circuits arranged in the second pixel region PCB can be configured to receive the 2-2 initialization voltage from the 2-2 initialization voltage line VL2b. The magnitude of the 2-1 initialization voltage can be different from the magnitude of the 2-2 initialization voltage. According to an embodiment, the pixel circuits arranged in the first pixel region PCA can be electrically connected to the organic light-emitting diode OLED that emits red light or blue light, and the pixel circuits arranged in the second pixel region PCB can be electrically connected to the organic light-emitting diode OLED that emits green light.

[0188] The 2-1 initialization voltage line VL2a can extend in the first direction (x direction). The 2-1 initialization voltage line VL2a can be electrically connected to the source region S7 of the seventh transistor T7 arranged in the first pixel region PCA through the contact hole CT4 passing through the second insulating layer 103, the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108.

[0189] The 2-2 initialization voltage line VL2b can extend in the first direction (x direction). The 2-2 initialization voltage line VL2b can be electrically connected to the source region S7 of the seventh transistor T7 arranged in the second pixel region PCB through the contact hole CT9 passing through the second insulating layer 103, the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108.

[0190] The drive voltage line PL can extend in the second direction (y direction) and can be electrically connected to the pixel circuits arranged in the same pixel column. The drive voltage line PL can overlap with the third transistor T3 and the fourth transistor T4 to reduce the electrical effects caused by the pixel electrode 210 and the like.

[0191] The seventh conductive layer 2900 can be provided on the eighth insulating layer 111. Figure 22is a layout diagram for describing the arrangement of the first pixel electrode 2901, the second pixel electrode 2902, and the third pixel electrode 2903, where Figure 23 the pixel electrode 210 of the organic light-emitting diode OLED shown in Figure 23 may correspond to any one of the first pixel electrode 2901, the second pixel electrode 2902, and the third pixel electrode 2903. The first pixel electrode 2901, the second pixel electrode 2902, and the third pixel electrode 2903 may be repeatedly arranged in a first direction (x direction) and a second direction (y direction) according to a specific pattern. Each of the first pixel electrode 2901, the second pixel electrode 2902, and the third pixel electrode 2903 may be electrically connected to a lower conductive pattern (e.g., the fourteenth conductive pattern 2801) through a contact hole CT21 passing through the eighth insulating layer 111.

[0192] According to an embodiment, the first pixel electrode 2901, the second pixel electrode 2902, and the third pixel electrode 2903 may be arranged as a layout type (or diamond layout type). The first emission region EA1 defined in the first pixel electrode 2901 may emit red light, the second emission region EA2 defined in the second pixel electrode 2902 may emit green light, and the third emission region EA3 defined in the third pixel electrode 2903 may emit blue light. Four second pixel electrodes 2902 may be arranged relative to the first pixel electrode 2901 or the third pixel electrode 2903. The first pixel electrode 2901, the second pixel electrode 2902, and the third pixel electrode 2903 may be arranged in various forms such as a stripe layout type, a mosaic layout type, etc., and each of the first pixel electrode 2901, the second pixel electrode 2902, and the third pixel electrode 2903 may have various shapes such as a polygon shape, a circular shape, an oval shape, etc.

[0193] According to an embodiment, the pixel circuit arranged in the first pixel area PCA may be electrically connected to the first pixel electrode 2901 or the third pixel electrode 2903, and the pixel circuit arranged in the second pixel area PCB may be electrically connected to the second pixel electrode 2902. The first pixel electrode 2901 or the third pixel electrode 2903 may be arranged to overlap with the fifth transistor T5, and the second pixel electrode 2902 may be arranged to overlap with the third transistor T3 and the fourth transistor T4.

[0194] Referring to Figure 23 , the organic light-emitting diode OLED may include a pixel electrode 210, a counter electrode 230 facing the pixel electrode 210, and an emission layer 220 disposed between the pixel electrode 210 and the counter electrode 230.

[0195] The emission control signal line EML may overlap with a first source-drain region SD1 where a source region S1 of the first transistor T1 and a drain region D5 of the fifth transistor T5 are connected to each other (see Figure 8 ). According to the present embodiment, the emission control signal line EML may be included in the fifth conductive layer 2700 and may be sufficiently spaced apart from the first source-drain region SD1 in the thickness direction (z direction) by the second insulating layer 103, the third insulating layer 105, the fourth insulating layer 106, and the sixth insulating layer 108. According to an embodiment, the fifth conductive pattern 2410 may be disposed between the first source-drain region SD1 and the emission control signal line EML. Thus, in the first source-drain region SD1 overlapping with the emission control signal line EML, unnecessary transistors may not be formed.

[0196] The first source-drain region SD1 may be sufficiently spaced apart from the data line DL in the thickness direction (z direction) by the second insulating layer 103, the third insulating layer 105, the fourth insulating layer 106, the sixth insulating layer 108, and the seventh insulating layer 109. Thus, the parasitic capacitance between the first source-drain region SD1 and the data line DL may be reduced, and accordingly, the display device 10 (see Figure 1 ) may display a high-quality image.

[0197] In addition, when the emission control signal line EML is disposed on the fifth conductive layer 2700, the emission control signal line EML may be sufficiently spaced apart from the peripheral elements disposed above and below the emission control signal line EML in the thickness direction (z direction). Thus, during the on / off voltage change of the emission control signal EM (see Figure 2 ), the load may be reduced.

[0198] [Table 1]

[0199] Drive frequency Power consumption Improvement rate of power consumption 120 Hz 0.84 mW 1.1％ 60 Hz 0.81 mW 1.7％ 30 Hz 0.80 mW 2.3％ 1 Hz 0.78 mW 3.4％

[0200] Table 1 shows the simulation results of the improvement rate of the power consumption of the display device 10 according to an embodiment in which the emission control signal line EML is included in the fifth conductive layer 2700. It is assumed that in the display device according to the comparative embodiment, the second conductive layer may include the emission control signal line, and the elements other than the emission control signal line may be the same as those in the display device according to the embodiment. It is shown that at all frequencies, an improvement in power consumption occurs, and as the driving frequency decreases, the improvement rate of power consumption may increase.

[0201] As described above, according to the embodiment, the parasitic capacitance between the transistor and the line may be reduced, and accordingly, the display device may display a high-quality image. However, the scope of the present disclosure is not limited to these effects described above.

[0202] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects within each embodiment is generally to be considered as available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the figures, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. A display device, comprising: a first semiconductor layer, the first semiconductor layer comprising a first channel region, a second channel region, a first source-drain region between the first channel region and the second channel region, and a source / drain region extending from the second channel region; a first conductive layer, the first conductive layer being disposed on the first semiconductor layer and comprising a first electrode overlapping the first channel region and a second electrode overlapping the second channel region; a second semiconductor layer, the second semiconductor layer being disposed on the first conductive layer and comprising a third channel region; a second conductive layer disposed on the second semiconductor layer and comprising a third electrode overlapping the third channel region and a first signal line electrically connected to the second electrode; a third conductive layer disposed on the second conductive layer and comprising a first conductive region electrically connected to the source / drain region; as well as A fourth conductive layer is disposed on the third conductive layer and includes a voltage line electrically connected to the first conductive region.

2. The display device according to claim 1, wherein: The first channel region, the first source-drain region, the second channel region, and the source / drain region are integrally provided.

3. The display device according to claim 1, wherein: The first signal line extends in a first direction, and The first signal line overlaps the first source-drain region and the second channel region.

4. The display device according to claim 3, wherein: The source / drain region is spaced apart from the first electrode in the first direction.

5. The display device according to claim 1, wherein: The first semiconductor layer further includes a fourth channel region extending from the first source-drain region and a third source / drain region extending from the fourth channel region, The first conductive layer further includes a second signal line overlapping the fourth channel region, and The fourth conductive layer also includes a data line electrically connected to the third source / drain region.

6. The display device according to claim 5, wherein: The data line overlaps the second channel region.

7. The display device according to claim 1, wherein: The first semiconductor layer further includes a fifth channel region, and The first conductive layer further includes a fourth electrode overlapping the fifth channel region.

8. The display device according to claim 7, wherein: The first signal line is electrically connected to the fourth electrode.

9. The display device according to claim 1, wherein: The first conductive layer further includes a third signal line overlapping the third channel region and electrically connected to the third electrode.

10. The display device according to claim 1, wherein: The source / drain region is a first source / drain region; The first semiconductor layer includes a first portion and a second portion forming a symmetrical circuit layout with respect to a virtual straight line extending in a second direction, the first portion including the first source / drain region, and the second portion including a second source / drain region integrally connected to the first source / drain region; as well as The first portion and the second portion are connected to each other through a connection between the first source / drain region and the second source / drain region.

11. A display device, comprising: a first semiconductor layer, the first semiconductor layer comprising a first channel region, a second channel region, a first source-drain region between the first channel region and the second channel region, and a source / drain region extending from the second channel region; a first conductive layer, the first conductive layer being disposed on the first semiconductor layer and comprising a first electrode overlapping the first channel region and a second electrode overlapping the second channel region; a second conductive layer, the second conductive layer being disposed on the first conductive layer and comprising a first conductive region overlapping the first electrode; a second semiconductor layer, the second semiconductor layer being disposed on the second conductive layer and comprising a third channel region; a third conductive layer, the third conductive layer being disposed on the second semiconductor layer and comprising a third electrode overlapping the third channel region; a fourth conductive layer disposed on the third conductive layer and comprising a second conductive region electrically connected to the source / drain region and the first conductive region and a first signal line electrically connected to the second electrode; as well as A fifth conductive layer is disposed on the fourth conductive layer and includes a voltage line electrically connected to the second conductive region.

12. The display device according to claim 11, wherein: The first channel region, the second channel region, the first source-drain region, and the source / drain region are integrally provided.

13. The display device according to claim 11, wherein: The first signal line extends in a first direction, and The first signal line overlaps the first source-drain region and the second channel region.

14. The display device according to claim 13, wherein: The first conductive region is disposed between the first signal line and the first source-drain region.

15. The display device according to claim 13, wherein: The second source-drain region is arranged to be spaced apart from the first electrode in the first direction.

16. The display device according to claim 11, wherein: The first semiconductor layer further includes a fourth channel region extending from the first source-drain region and a third source / drain region extending from the fourth channel region, The first conductive layer further includes a second signal line overlapping the fourth channel region, and The fifth conductive layer further includes a data line and a data connection line electrically connected to the third source / drain region.

17. The display device according to claim 16, wherein: The data connection line overlaps with the second channel region.

18. The display device according to claim 11, wherein: The first semiconductor layer further includes a fifth channel region, and The first conductive layer further includes a fourth electrode overlapping the fifth channel region.

19. The display device according to claim 18, wherein: The first signal line is electrically connected to the fourth electrode.

20. The display device according to claim 11, wherein: The source / drain region is a first source / drain region; The first semiconductor layer includes a first portion and a second portion forming a symmetrical circuit layout with respect to a virtual straight line extending in a second direction, the first portion including the first source / drain region, and the second portion including a second source / drain region integrally connected to the first source / drain region; as well as The first portion and the second portion are connected to each other through a connection between the first source / drain region and the second source / drain region.

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