Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes: a light emitting element layer including a light emitting element; an encapsulation layer disposed on the light emitting element layer and covering the light emitting element; the sensing electrode is arranged on the packaging layer; a sensing insulating layer disposed on the encapsulation layer, the sensing insulating layer having an upper surface, the sensing insulating layer including a trench pattern recessed from the upper surface; and a sensing line disposed in the trench pattern, the sensing line being connected to the sensing electrode and including a first metal layer.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of manufacturing the display device. More specifically, the present disclosure relates to a display device that senses an external input and a method of manufacturing the display device. Background Art

[0002] With the development of information technology, the importance of display devices as a medium for providing visual information to users has increased.

[0003] Recently, display devices including an input sensing layer for sensing an external input have been developed. When a user touches the input sensing layer, an input signal is generated. The input signal is provided to a display panel. The display panel provides an image corresponding to the input signal to the user. Summary of the Invention

[0004] Embodiments provide a display device having improved display quality and reduced useless space.

[0005] Embodiments provide a method of manufacturing a display device.

[0006] According to an embodiment of the present disclosure, a display device includes: a light-emitting element layer including light-emitting elements; a encapsulation layer disposed on the light-emitting element layer and covering the light-emitting elements; a sensing electrode disposed on the encapsulation layer; a sensing insulating layer disposed on the encapsulation layer, the sensing insulating layer having an upper surface, the sensing insulating layer including a trench pattern recessed from the upper surface; and a sensing line disposed in the trench pattern, the sensing line connected to the sensing electrode and including a first metal layer.

[0007] In an embodiment, the height of the upper surface of the first metal layer is less than or equal to the height of the upper surface of the sensing insulating layer with respect to the upper surface of the encapsulation layer.

[0008] In an embodiment, the first metal layer may include copper (Cu).

[0009] In an embodiment, the line width of the first metal layer may be less than or equal to about 2.6 micrometers.

[0010] In an embodiment, the interval between at least two trenches defining the trench pattern may be less than or equal to about 4.0 micrometers.

[0011] In an embodiment, the sensing line may be disposed on the encapsulation layer only at positions defining the trench pattern.

[0012] In an embodiment, the trench pattern may be recessed from the upper surface of the sensing insulating layer to a point inside the sensing insulating layer between the upper surface and the lower surface of the sensing insulating layer.

[0013] In an embodiment, the display device may further include: a protection pattern disposed on the first metal layer and covering an upper surface of the first metal layer.

[0014] In an embodiment, the protection pattern may be disposed on the encapsulation layer only at positions defining the trench pattern.

[0015] In an embodiment, the sensing line may further include: a second metal layer covering a side surface and a lower surface of the first metal layer, and the second metal layer includes a material different from that of the first metal layer.

[0016] In an embodiment, the first metal layer, the second metal layer, and the protection pattern may be in direct contact with each other.

[0017] In an embodiment, the display device may further include: a light-blocking pattern disposed in the trench pattern and covering a side surface and a lower surface of the first metal layer.

[0018] In an embodiment, the light-blocking pattern may include at least one material selected from a metal material and an organic material.

[0019] According to an embodiment of the present disclosure, a method of manufacturing a display device includes: forming a lower sacrificial layer including a first material on a sensing insulating layer, and forming an upper sacrificial layer including a second material different from the first material on the lower sacrificial layer; forming an upper sacrificial pattern by removing a part of the upper sacrificial layer, and forming a lower sacrificial pattern by removing a part of the lower sacrificial layer; removing a part of the sensing insulating layer by using the upper sacrificial pattern and the lower sacrificial pattern as masks to form a trench pattern; forming an undercut structure defined by the upper sacrificial pattern and the lower sacrificial pattern by removing a part of the lower sacrificial pattern; and forming a metal layer in the trench pattern of the sensing insulating layer.

[0020] In an embodiment, the formation of the trench pattern may be performed by a first etching process. The formation of the undercut structure may be performed by a second etching process different from the first etching process. An etching rate of the lower sacrificial pattern for the second etching process may be greater than an etching rate of the upper sacrificial pattern for the second etching process.

[0021] In an embodiment, the first etching process may be a dry etching process, and the second etching process may be a wet etching process.

[0022] In an embodiment, the metal layer may be formed of copper (Cu).

[0023] In an embodiment, in the formation of the metal layer, a dummy metal layer including the same material as the metal layer may be formed on the upper sacrificial pattern, and the dummy metal layer may be formed discontinuously with the metal layer through the undercut structure.

[0024] In an embodiment, the method may further include: forming a protection pattern on the metal layer to cover an upper surface of the metal layer.

[0025] In an embodiment, in the formation of the protection pattern, a dummy protection pattern including the same material as the protection pattern may be formed on the dummy metal layer, and the dummy protection pattern may be formed discontinuously with the protection pattern through the undercut structure.

[0026] In an embodiment, the method may further include: forming a photoresist pattern that covers the protection pattern and exposes the dummy protection pattern; using the photoresist pattern as a mask to remove the dummy protection pattern, the dummy metal layer, the upper sacrificial pattern, and the lower sacrificial pattern; and removing the photoresist pattern.

[0027] In an embodiment, the method may further include forming a light-blocking pattern in the trench pattern before the formation of the metal layer. In the formation of the light-blocking pattern, a dummy light-blocking pattern including the same material as the light-blocking pattern may be formed on the upper sacrificial pattern. Through the undercut structure, the dummy light-blocking pattern may be formed discontinuously with the light-blocking pattern.

[0028] According to an embodiment of the present disclosure, a display device includes: a display panel including a light-emitting element layer having a light-emitting element; and an input sensing layer on the display panel, the input sensing layer including sensing electrodes, a plurality of sensing lines, and a first sensing insulating layer and a second sensing insulating layer. Each of the plurality of sensing lines includes a lower sensing line disposed at the first sensing insulating layer and an upper sensing line disposed at the second sensing insulating layer. The upper sensing line and the lower sensing line are connected to each other. The lower sensing line is disposed in a concave pattern in an upper surface of the first sensing insulating layer, and / or the upper sensing line is disposed in a concave pattern in an upper surface of the second sensing insulating layer.

[0029] In an embodiment, the lower sensing line is disposed in the concave pattern in the upper surface of the first sensing insulating layer, and the upper sensing line is disposed in the concave pattern in the upper surface of the second sensing insulating layer.

[0030] In an embodiment, the lower sensing line and the upper sensing line are directly connected to each other through at least one contact hole defined in the second sensing insulating layer.

[0031] In an embodiment, the sensing electrode includes a first sensing electrode arranged in a first direction. The first sensing electrode includes a first sensing portion and a first connection portion. The sensing electrode further includes a second sensing electrode arranged in a second direction intersecting the first direction. The second sensing electrode includes a second sensing portion and a second connection portion. At least some of the first sensing portion, the first connection portion, the second sensing portion, and the second connection portion are respectively arranged in a concave pattern on the upper surface of the first sensing insulating layer or the upper surface of the second sensing insulating layer.

[0032] In a display device according to an embodiment, the sensing lines included in the input sensing layer may include a metal layer, and the metal layer of the sensing lines may be disposed in a trench pattern defined in the sensing insulating layer. That is, the metal layer of the sensing lines may be arranged in a concave pattern (engraved pattern) rather than a convex pattern (embossed pattern) with respect to the sensing insulating layer. Therefore, during the process of forming the metal layer, blank spaces such as skewing may not be generated in the metal layer. Therefore, it is possible to more easily implement the metal layer as a fine pattern. Therefore, the display quality of the display device can be improved and useless space can be reduced.

[0033] In addition, in a method of manufacturing a display device according to an embodiment, a trench pattern may be formed in the sensing insulating layer, and a sacrificial pattern may be formed on the sensing insulating layer to form an undercut structure. Therefore, through the undercut structure and the trench pattern, the metal layer can be automatically self-patterned during deposition. For example, a separate etching process may not be performed to form the metal layer. Therefore, blank spaces such as skewing due to the etching process may not be generated in the metal layer. Therefore, it is possible to more easily form the metal layer into a fine pattern.

[0034] It should be understood that both the foregoing general description and the following detailed description are non-limiting and are intended to provide further explanation of the present disclosure. Description of the Drawings

[0035] The illustrative, non-limiting embodiments of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0036] Figure 1 is a plan view showing a display device according to an embodiment of the present disclosure.

[0037] Figure 2 is a view showing a Figure 1 display device according to an embodiment of the present disclosure.

[0038] Figure 3 is a view showing a Figure 2 display panel according to an embodiment of the present disclosure.

[0039] Figure 4 is a circuit diagram showing pixels of a display panel according to an embodiment of the present disclosure Figure 3 of

[0040] Figure 5 is a cross-sectional view showing a display panel according to an embodiment of the present disclosure Figure 2 of

[0041] Figure 6 is a plan view showing an input sensing layer according to an embodiment of the present disclosure Figure 2 of

[0042] Figure 7 is a cross-sectional view showing an example taken along line X-X' according to an embodiment of the present disclosure Figure 6 of

[0043] Figure 8 is a cross-sectional view showing an example taken along line Y-Y' according to an embodiment of the present disclosure Figure 6 of

[0044] Figure 9 is a cross-sectional view showing an example taken along line Y-Y' according to an embodiment of the present disclosure Figure 6 of

[0045] Figure 10 is a cross-sectional view showing an example taken along line Y-Y' according to an embodiment of the present disclosure Figure 6 of

[0046] Figures 11 to 23 is a view showing a manufacturing method of a sensing line according to an embodiment of the present disclosure Figure 8 of

[0047] Figure 24 is a cross-sectional view showing an example taken along line Y-Y' according to an embodiment of the present disclosure Figure 6 of

[0048] Figures 25 to 29 is a view showing a manufacturing method of a sensing line according to an embodiment of the present disclosure Figure 24 of

[0049] Figure 30 is a cross-sectional view showing another example taken along line X-X' according to an embodiment of the present disclosure Figure 6 of DETAILED DESCRIPTION

[0050] Hereinafter, a display device according to an embodiment of the present disclosure will be described in more detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same components, and for the sake of brevity of explanation, redundant descriptions of the same components will be omitted.

[0051] Figure 1 is a plan view showing a display device according to an embodiment of the present disclosure, and Figure 2 is a view showing an embodiment according to the present disclosure Figure 1 cross-sectional view of the display device.

[0052] Referring to Figure 1 and Figure 2 , the display device DD may include an active area AA and a non-active area NAA. The active area AA may be an area that generates light or displays an image by adjusting the transmittance of light provided from an external light source. The non-active area NAA may be an area that does not display an image. The non-active area NAA may be located around the active area AA. For example, in an embodiment, the non-active area NAA may completely surround the active area AA (e.g., in a first direction DR1 and a second direction DR2). However, embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, the non-active area NAA may not surround at least one side of the active area AA.

[0053] In an embodiment, the display device DD may include a display panel DP and an input sensing layer ISU disposed on the display panel DP. The display panel DP may include a substrate SUB, a circuit element layer DP-CL, a light-emitting element layer DP-LE, and a packaging layer ECL.

[0054] The substrate SUB may include a transparent material or an opaque material. In an embodiment, examples of materials that may be used as the substrate SUB may include glass, quartz, or plastic, etc. These materials may be used alone or in combination with each other.

[0055] The circuit element layer DP-CL may be disposed on the substrate SUB (e.g., directly on the substrate SUB). The circuit element layer DP-CL may include a plurality of transistors. In an embodiment, each of the plurality of transistors may include a control terminal, an input terminal, and an output terminal. For example, the circuit element layer DP-CL may include transistors for driving light-emitting elements.

[0056] In an embodiment, the circuit element layer DP-CL may include a semiconductor pattern, a conductive pattern, and signal lines. In some embodiments, an insulating layer, a semiconductor layer, and a conductive layer may be formed on the substrate SUB by coating or deposition, etc., and the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned. Thus, the circuit element layer DP-CL including the semiconductor pattern, the conductive pattern, and the signal lines may be formed on the substrate SUB (e.g., directly formed on the substrate SUB).

[0057] The light-emitting element layer DP-LE may include light-emitting elements. The light-emitting element layer DP-LE is disposed on the circuit element layer DP-CL (e.g., directly on the circuit element layer DP-CL). The light-emitting element layer DP-LE may further include an organic layer such as a pixel definition layer.

[0058] The encapsulation layer ECL may be disposed on the light-emitting element layer DP-LE (e.g., directly on the light-emitting element layer DP-LE). The encapsulation layer ECL may cover the light-emitting elements. For example, the encapsulation layer ECL may protect the light-emitting elements from external moisture, heat, or impact, etc. In some embodiments, the encapsulation layer ECL may include a first inorganic encapsulation layer, an organic encapsulation layer disposed on the first inorganic encapsulation layer, and a second inorganic encapsulation layer disposed on the organic encapsulation layer. However, embodiments of the present disclosure are not necessarily limited thereto, and the encapsulation layer ECL may have various different configurations including at least one inorganic encapsulation layer and at least one organic encapsulation layer.

[0059] The input sensing layer ISU may be disposed on the encapsulation layer ECL (e.g., directly on the encapsulation layer ECL). The input sensing layer ISU may sense an external input. The external input may be provided in various forms. For example, in some embodiments, the external input may be in the form of a touch of a part of a user's body, a pen touch, light, heat, or pressure. In addition, the external input may be in the form of a touch (e.g., hovering or proximity) in an adjacent space as well as a form of direct contact.

[0060] In an embodiment, the input sensing layer ISU may be directly disposed on the encapsulation layer ECL. As used herein, "component A is directly disposed on component B" means that no adhesive layer or other intermediate element is disposed between component A and component B. In an embodiment, the input sensing layer ISU may be formed by a continuous process with the display panel DP. However, embodiments of the present disclosure are not necessarily limited thereto, and in some embodiments, the input sensing layer ISU may be provided as a separate panel and joined to the display panel DP through an adhesive layer.

[0061] Figure 3 is a plan view of a Figure 2 display panel according to an embodiment of the present disclosure.

[0062] Referring to Figure 3 , in the plan view, the display panel DP may be divided into a display area DA and a non-display area NDA. The non-display area NDA may surround the display area DA (e.g., in a first direction DR1 and a second direction DR2). The display area DA and the non-display area NDA of the display panel DP may respectively correspond to Figure 1 the active area AA and the non-active area NAA of a

[0063] Pixels PX can be disposed in the display area DA. The pixels PX can include a light-emitting element and a pixel circuit connected to the light-emitting element. In an embodiment, the driving circuit GDC and the signal pads DP-PD can be disposed in the non-display area NDA. The pixels PX can be connected to the driving circuit GDC and the signal pads DP-PD through signal lines SGL. The driving circuit GDC, the signal lines SGL, the signal pads DP-PD, and the pixel circuit can be included in Figure 2 the circuit element layer DP-CL shown.

[0064] In an embodiment, the driving circuit GDC can include a plurality of transistors formed by the same process as the pixel circuit of the pixels PX. For example, the driving circuit GDC can include a gate driving circuit. The gate driving circuit can output a gate signal to the gate line GL to be described later.

[0065] In an embodiment, the signal lines SGL can include a gate line GL, a data line DL, a power line PL, and a control signal line CSL. The gate line GL, the data line DL, and the power line PL can be connected to the corresponding pixels PX. The control signal line CSL can provide a control signal to the driving circuit GDC.

[0066] The area of the setting signal pads DP-PD and the dummy pads IS-DPD in the non-display area NDA can be defined as the pad area PDA. In an embodiment, the pad area PDA can be bent from the display area DA and can contact the rear surface of the display panel DP. An external device (e.g., a circuit board, etc.) can be bonded to the pad area PDA.

[0067] The display panel DP can further include dummy pads IS-DPD disposed in the pad area PDA. In an embodiment, the dummy pads IS-DPD can be formed by the same process as the signal lines SGL. The dummy pads IS-DPD can be optionally provided in a display device DD including an input sensing layer ISU (see Figure 2 ).

[0068] The dummy pads IS-DPD can overlap with the pad portion TSL-P of the input sensing layer ISU of Figure 6 to be described later. In an embodiment, the dummy pads IS-DPD can be floating electrodes.

[0069] In an embodiment, the display panel DP can further include at least one driving chip. The driving chip can be connected to the data line DL. Thus, the data line DL can be electrically connected to the signal pads DP-PD through the driving chip. In addition, in an embodiment, the control signal line CSL and / or the power line PL can also be connected to the driving chip.

[0070] Figure 4is a circuit diagram showing pixels of a display panel according to an embodiment of the present disclosure Figure 3 of the display panel

[0071] Figure 4 shows an example of a circuit diagram of a pixel PX of Figure 3 and embodiments of the present disclosure are not necessarily limited thereto

[0072] The pixel PX may include a light-emitting element LED and a pixel circuit. In an embodiment, the pixel circuit may include a first transistor T1, a second transistor T2, and a capacitor CST. The pixel circuit may be electrically connected to the light-emitting element LED and supply a driving current to the light-emitting element LED

[0073] In an embodiment, the first transistor T1 may include a control terminal, a first terminal (e.g., an input terminal), and a second terminal (e.g., an output terminal). The control terminal (e.g., a gate terminal) of the first transistor T1 may be connected to the first terminal of the capacitor CST. The control terminal of the first transistor T1 may be connected to the second transistor T2 to receive a data voltage. The first terminal of the first transistor T1 may be connected to the second terminal of the capacitor CST. The first terminal of the first transistor T1 may be connected to a power supply line PL to receive a high power supply voltage ELVDD. The second terminal of the first transistor T1 may be connected to the light-emitting element LED to supply a driving current. The first transistor T1 may generate a driving current based on a voltage difference between the control terminal and the first terminal

[0074] In an embodiment, the second transistor T2 may include a control terminal, a first terminal (e.g., an input terminal), and a second terminal (e.g., an output terminal). The control terminal of the second transistor T2 may receive a gate signal through a gate line GL. The first terminal of the second transistor T2 may receive a data voltage through a data line DL. The second terminal of the second transistor T2 may supply the data voltage to the control terminal of the first transistor T1 when the second transistor T2 is turned on

[0075] The capacitor CST may include a first terminal and a second terminal. The first terminal of the capacitor CST may be connected to the first transistor T1, and the second terminal of the capacitor CST may receive a high power supply voltage ELVDD. The capacitor CST may maintain a voltage level of the control terminal of the first transistor T1 in a specific interval

[0076] In an embodiment, the light-emitting element LED may include a first terminal (e.g., an anode terminal) and a second terminal (e.g., a cathode terminal). The first terminal of the light-emitting element LED may be connected to the first transistor T1 to receive a driving current, and the second terminal may receive a low power supply voltage ELVSS. The light-emitting element LED may generate light having a brightness corresponding to the driving current

[0077] As described above, Figure 4 only an example of the circuit diagram of the pixel PX is shown, and embodiments of the present disclosure are not necessarily limited thereto. The pixel PX may further include transistors and capacitors other than the first transistor T1, the second transistor T2, and the capacitor CST.

[0078] Figure 5 is a cross-sectional view of a Figure 2 display panel according to an embodiment of the present disclosure.

[0079] Referring to Figure 5 , a circuit element layer DP-CL, a light-emitting element layer DP-LE, and a packaging layer ECL may be disposed on a substrate SUB.

[0080] In an embodiment, the circuit element layer DP-CL may include a buffer layer BFR, a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer insulating layer ILD, a via insulating layer VIA, a first transistor T1, and a capacitor CST. The first transistor T1 may include an active pattern ACT, a first gate electrode GAT1 (control terminal), an input electrode SE (first terminal), and an output electrode DE (second terminal). The capacitor CST may include a first gate electrode GAT1 (first terminal) and a second electrode GAT2 (second terminal).

[0081] In an embodiment, the light-emitting element layer DP-LE may include a light-emitting element LED and a pixel defining layer PDL. The light-emitting element LED may include a pixel electrode AE (first terminal), an emission layer EML, and a common electrode CE (second terminal).

[0082] The buffer layer BFR may be disposed on the substrate SUB. For example, in an embodiment, the buffer layer BFR may be directly disposed on the upper surface of the substrate SUB. The buffer layer BFR may prevent impurities such as oxygen and moisture from diffusing above the substrate SUB. In an embodiment, the buffer layer BFR may include an inorganic insulating material such as a silicon compound or a metal oxide.

[0083] The active pattern ACT may be disposed on the buffer layer BFR. For example, in an embodiment, the active pattern ACT may be directly disposed on the upper surface of the buffer layer BFR. In an embodiment, the active pattern ACT may include a silicon semiconductor material or an oxide semiconductor material.

[0084] The first gate insulating layer GI1 may be disposed on the buffer layer BFR (e.g., directly on the buffer layer BFR). The first gate insulating layer GI1 may cover the active pattern ACT. The first gate insulating layer GI1 may include an inorganic insulating material.

[0085] The first gate electrode GAT1 may be disposed on the first gate insulating layer GI1. For example, in an embodiment, the first gate electrode GAT1 may be directly disposed on the upper surface of the first gate insulating layer GI1. The first gate electrode GAT1 may overlap with the active pattern ACT in a plan view. In an embodiment, the first gate electrode GAT1 may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material, etc.

[0086] The second gate insulating layer GI2 may be disposed on the first gate insulating layer GI1 and the first gate electrode GAT1 (e.g., directly disposed on the first gate insulating layer GI1 and the first gate electrode GAT1). The second gate insulating layer GI2 may cover the first gate electrode GAT1. In an embodiment, the second gate insulating layer GI2 may include an inorganic insulating material.

[0087] The second electrode GAT2 may be disposed on the second gate insulating layer GI2. For example, in an embodiment, the second electrode GAT2 may be directly disposed on the upper surface of the second gate insulating layer GI2. The second electrode GAT2 may overlap with the first gate electrode GAT1 in a plan view. In an embodiment, the second electrode GAT2 may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material, etc.

[0088] The interlayer insulating layer ILD may be disposed on the second gate insulating layer GI2 and the second electrode GAT2 (e.g., directly disposed on the second gate insulating layer GI2 and the second electrode GAT2). The interlayer insulating layer ILD may cover the second electrode GAT2. In an embodiment, the interlayer insulating layer ILD may include an inorganic insulating material.

[0089] The input electrode SE and the output electrode DE may be disposed on the interlayer insulating layer ILD. For example, in an embodiment, the input electrode SE and the output electrode DE may be directly disposed on the upper surface of the interlayer insulating layer ILD. In an embodiment, the input electrode SE and the output electrode DE may be connected to the active pattern ACT through contact holes formed in the interlayer insulating layer ILD, the first gate insulating layer GI1, and the second gate insulating layer GI2 (e.g., directly connected to the active pattern ACT). In an embodiment, the input electrode SE and the output electrode DE may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material, etc.

[0090] The via insulating layer VIA may be disposed on the interlayer insulating layer ILD, the input electrode SE, and the output electrode DE (e.g., directly disposed on the interlayer insulating layer ILD, the input electrode SE, and the output electrode DE). The via insulating layer VIA may cover the input electrode SE and the output electrode DE. In an embodiment, the via insulating layer VIA may include an organic insulating material.

[0091] The pixel electrode AE can be disposed on the via insulating layer VIA. For example, in an embodiment, the pixel electrode AE can be directly disposed on the upper surface of the via insulating layer VIA. In an embodiment, the pixel electrode AE can be electrically connected to the first transistor T1 through a contact hole formed in the via insulating layer VIA. In an embodiment, the pixel electrode AE can include a metal, an alloy, a conductive metal oxide, or a transparent conductive material, etc.

[0092] The pixel defining layer PDL can be disposed on the via insulating layer VIA. The pixel defining layer PDL can define a pixel opening PO that exposes a part of the pixel electrode AE. For example, in an embodiment, the pixel defining layer PDL can be directly disposed on the lateral end of the pixel electrode AE and can expose the central portion of the pixel electrode AE. In an embodiment, the pixel defining layer PDL can include an organic insulating material.

[0093] The emission layer EML can be disposed on the pixel electrode AE in the pixel opening PO. The emission layer EML can include a material that emits light. For example, in an embodiment, the emission layer EML can include an organic light-emitting material.

[0094] The common electrode CE can be disposed on the emission layer EML. In an embodiment, the common electrode CE can include a conductive material, such as a metal, an alloy, a conductive metal nitride, a conductive metal oxide, or a transparent conductive material.

[0095] The encapsulation layer ECL can be disposed on the light-emitting element layer DP-LE (e.g., directly on the light-emitting element layer DP-LE). The encapsulation layer ECL can cover the light-emitting element LED. In an embodiment, the encapsulation layer ECL can include a first inorganic encapsulation layer, an organic encapsulation layer disposed on the first inorganic encapsulation layer, and a second inorganic encapsulation layer disposed on the organic encapsulation layer. However, the embodiments of the present disclosure are not necessarily limited thereto.

[0096] Figure 6 is a plan view of the input sensing layer according to an embodiment of the present disclosure Figure 2 of the input sensing layer.

[0097] Referring to Figure 6 , the input sensing layer ISU can include a sensing region SA that senses an external input, and a peripheral region PA that is positioned around the sensing region SA (e.g., in a first direction DR1 and a second direction DR2).

[0098] The sensing region SA can correspond to Figure 3The display area DA of the display panel DP shown in the figure and has an area that is substantially the same as or larger than the area of the display area DA (e.g., the planar dimensions in the first direction DR1 and the second direction DR2). The peripheral area PA can surround the sensing area SA (e.g., in the first direction DR1 and the second direction DR2). For example, the peripheral area PA can correspond to the non-display area NDA of the display panel DP.

[0099] In an embodiment, the input sensing layer ISU can include first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, IE1-5 and second sensing electrodes IE2-1, IE2-2, IE2-3, IE2-4, first sensing lines TSL1-1, TSL1-2, TSL1-3, TSL1-4, TSL1-5, and second sensing lines TSL2-1, TSL2-2, TSL2-3, TSL2-4.

[0100] In an embodiment, the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, IE1-5 and the second sensing electrodes IE2-1, IE2-2, IE2-3, IE2-4 can be disposed in the sensing area SA, and the first sensing lines TSL1-1, TSL1-2, TSL1-3, TSL1-4, TSL1-5 and the second sensing lines TSL2-1, TSL2-2, TSL2-3, TSL2-4 can be disposed in the peripheral area PA.

[0101] In an embodiment, each of the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, IE1-5 can include a first sensing portion SP1 and a first connection portion CP1. The first sensing portion SP1 in one first sensing electrode can be arranged along the first direction DR1. Each of the first connection portions CP1 can connect adjacent first sensing portions SP1 to each other (e.g., in the first direction DR1).

[0102] In an embodiment, each of the second sensing electrodes IE2-1, IE2-2, IE2-3, IE2-4 can include a second sensing portion SP2 and a second connection portion CP2. The second sensing portion SP2 in one second sensing electrode can be arranged along the second direction DR2. Each of the second connection portions CP2 can connect adjacent second sensing portions SP2 to each other (e.g., in the second direction DR2).

[0103] In an embodiment, the first sensing portion SP1 and the second sensing portion SP2 can have a grid shape.

[0104] The first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, IE1-5 and the second sensing electrodes IE2-1, IE2-2, IE2-3, IE2-4 may include a metallic material. For example, in an embodiment, the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, IE1-5 and the second sensing electrodes IE2-1, IE2-2, IE2-3, IE2-4 may include aluminum (Al), titanium (Ti), copper (Cu), or molybdenum (Mo), etc. For example, in an embodiment, the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, IE1-5 and the second sensing electrodes IE2-1, IE2-2, IE2-3, IE2-4 may include copper (Cu).

[0105] The first sensing lines TSL1-1, TSL1-2, TSL1-3, TSL1-4, TSL1-5 may be connected to the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, IE1-5. The second sensing lines TSL2-1, TSL2-2, TSL2-3, TSL2-4 may be connected to the second sensing electrodes IE2-1, IE2-2, IE2-3, IE2-4.

[0106] In an embodiment, each of the first sensing lines TSL1-1, TSL1-2, TSL1-3, TSL1-4, TSL1-5 and the second sensing lines TSL2-1, TSL2-2, TSL2-3, TSL2-4 may include a line portion TSL-L and a pad portion TSL-P. The pad portion TSL-P may be aligned in the pad region PDA. The pad portion TSL-P may overlap with Figure 3 the dummy pad IS-DPD.

[0107] In an embodiment, the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, IE1-5 may operate as sensing electrodes (Rx), and the second sensing electrodes IE2-1, IE2-2, IE2-3, IE2-4 may operate as driving electrodes (Tx).

[0108] In Figure 6 the embodiment shown, the input sensing layer ISU includes five first sensing electrodes and four second sensing electrodes. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, the input sensing layer ISU may include four or fewer or six or more first sensing electrodes, and three or fewer or five or more second sensing electrodes.

[0109] In addition, in Figure 6In [the figure], the first sensing part SP1 and the second sensing part SP2 are shown (e.g., in a plan view) as having a rhombus shape. However, embodiments of the present disclosure are not necessarily limited thereto. For example, each of the first sensing part SP1 and the second sensing part SP2 may (e.g., in a plan view) have various polygonal shapes other than a rhombus shape.

[0110] Figure 7 is a cross-sectional view showing an example taken along the Figure 6 line X-X' according to an embodiment of the present disclosure.

[0111] Referring to Figure 6 and Figure 7 , in an embodiment, the input sensing layer ISU may include a first sensing insulating layer SIL1, a second sensing insulating layer SIL2, and a third sensing insulating layer SIL3. The first sensing insulating layer SIL1, the second sensing insulating layer SIL2, and the third sensing insulating layer SIL3 may be sequentially stacked on the encapsulation layer ECL (e.g., in a vertical direction perpendicular to the first direction DR1 and the second direction DR2). In an embodiment, each of the first sensing insulating layer SIL1, the second sensing insulating layer SIL2, and the third sensing insulating layer SIL3 may include an inorganic insulating material or an organic insulating material.

[0112] In an embodiment, the first connection part CP1 may be disposed on the first sensing insulating layer SIL1 (e.g., directly on the first sensing insulating layer SIL1), and the second sensing insulating layer SIL2 may cover the first connection part CP1. Further, the first sensing part SP1 and the second connection part CP2 may be disposed on the second sensing insulating layer SIL2 (e.g., directly on the second sensing insulating layer SIL2). In an embodiment, the first sensing part SP1 may be electrically connected to the first connection part CP1 through a contact hole CNT. Further, in an embodiment, the second sensing part SP2 may be disposed on the second sensing insulating layer SIL2. The third sensing insulating layer SIL3 may cover the first sensing part SP1, the second sensing part SP2, and the second connection part CP2.

[0113] However, embodiments of the present disclosure are not necessarily limited thereto, and the layers on which the first sensing part SP1, the second sensing part SP2, the first connection part CP1, and the second connection part CP2 are disposed may be changed in various ways according to embodiments.

[0114] Figure 8 is a cross-sectional view showing an example taken along the Figure 6 line Y-Y' according to an embodiment of the present disclosure.

[0115] In Figure 8Among them, three of the first sensing lines TSL1-1, TSL1-2, TSL1-3, TSL1-4, TSL1-5, namely, TSL1-1, TSL1-2, and TSL1-3, are selectively shown. In an embodiment, Figure 8 The first sensing lines TSL1-1, TSL1-2, and TSL1-3 shown therein may have the same structure as each other. In addition, Figure 8 The first sensing lines TSL1-4 and TSL1-5 not shown therein, and the second sensing lines TSL2-1, TSL2-2, TSL2-3, and TSL2-4 may also have the same structure as Figure 8 The first sensing lines TSL1-1, TSL1-2, and TSL1-3 shown therein. Hereinafter, the structure of the sensing line according to an embodiment of the present disclosure will be described in more detail focusing on the first sensing line TSL1-1.

[0116] Referring to Figure 6 and Figure 8 , in an embodiment, the first sensing line TSL1-1 may include a lower sensing line TSL1-11 and an upper sensing line TSL1-12. In an embodiment, the lower sensing line TSL1-11 and the upper sensing line TSL1-12 may be connected to each other through a contact hole. For example, the lower sensing line TSL1-11 and the upper sensing line TSL1-12 may be connected to each other (e.g., directly connected to each other) through at least one contact hole formed in the second sensing insulating layer SIL2. For example, in an embodiment, the first sensing line TSL1-1 may have a double-line structure in which two lines are connected to each other through a contact hole. Therefore, the resistance of the first sensing line TSL1-1 can be reduced.

[0117] However, the embodiments of the present disclosure are not necessarily limited thereto, and in some embodiments, the lower sensing line TSL1-11 or the upper sensing line TSL1-12 may be omitted. For example, in an embodiment, the first sensing line TSL1-1 may have a single-line structure. For example, the lower sensing line TSL1-11 itself may be the first sensing line TSL1-1, or the upper sensing line TSL1-12 itself may be the first sensing line TSL1-1.

[0118] Hereinafter, for ease of description, the description will focus on an example of a double-line structure in which the first sensing line TSL1-1 includes a lower sensing line TSL1-11 and an upper sensing line TSL1-12 connected to each other through a contact hole.

[0119] The first sensing insulating layer SIL1 may include a first trench pattern TRC1. The first trench pattern TRC1 may be defined by recessing (e.g., in a vertical direction) from the upper surface of the first sensing insulating layer SIL1. For example, the first trench pattern TRC1 may be defined as recessing from the upper surface of the first sensing insulating layer SIL1 to a point inside the first sensing insulating layer SIL1 between the upper surface and the lower surface of the first sensing insulating layer SIL1. For example, in an embodiment, the first trench pattern TRC1 may be defined by arranging a plurality of first trenches, and the first trenches do not completely penetrate the first sensing insulating layer SIL1 but only penetrate a part of the first sensing insulating layer SIL1 (e.g., partially penetrate in the vertical direction).

[0120] The lower sensing line TSL1-11 may be disposed in the first trench pattern TRC1. For example, in an embodiment, the lower sensing lines of the first sensing lines TSL1-1, TSL1-2, TSL1-3, TSL1-4, TSL1-5 and the second sensing lines TSL2-1, TSL2-2, TSL2-3, TSL2-4 may be disposed only at positions defining the first trench pattern TRC1. For example, in an embodiment, the lower sensing lines of the first sensing lines TSL1-1, TSL1-2, TSL1-3, TSL1-4, TSL1-5 and the second sensing lines TSL2-1, TSL2-2, TSL2-3, TSL2-4 may be arranged one by one to correspond to the first trenches of the first trench pattern TRC1.

[0121] In an embodiment, the lower sensing line TSL1-11 may include a first metal layer ML1 and a second metal layer ML2.

[0122] The first metal layer ML1 may be disposed in the first trench pattern TRC1. For example, with respect to the upper surface of the encapsulation layer ECL, the height of the upper surface of the first metal layer ML1 may be lower than the height of the upper surface of the first sensing insulating layer SIL1. For example, the first metal layer ML1 may be (e.g., in a vertical direction) located below the upper surface of the first sensing insulating layer SIL1. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, with respect to the upper surface of the encapsulation layer ECL, the height of the upper surface of the first metal layer ML1 may be (e.g., in a vertical direction) the same as the height of the upper surface of the first sensing insulating layer SIL1. In an embodiment, the first metal layer ML1 may not protrude above the upper surface of the first sensing insulating layer SIL1. For example, the first metal layer ML1 may be arranged to fill at least a part of the blank space generated by the first trench pattern TRC1.

[0123] In an embodiment, the first metal layer ML1 may include a metal material such as copper (Cu) or aluminum (Al). For example, the first metal layer ML1 may include copper (Cu). In an embodiment, when the first metal layer ML1 includes copper (Cu), the resistance of the lower sensing line TSL1-11 can be further reduced.

[0124] Since the first metal layer ML1 is disposed in the first trench pattern TRC1, the first metal layer ML1 can be more easily implemented as a fine pattern. For example, the line width LW of the first metal layer ML1 can be reduced. For example, in an embodiment, the line width LW of the first metal layer ML1 can be less than or equal to about 2.6 micrometers. In an embodiment, the line width LW of the first metal layer ML1 can be in the range of about 0.1 micrometer to about 2.6 micrometers. In an embodiment, the line width LW of the first metal layer ML1 can be in the range of about 0.1 micrometer to about 1.5 micrometers. Therefore, the useless space of the display device DD (see Figure 1 ) can be reduced.

[0125] In a comparative embodiment in which the first metal layer ML1 is disposed on the upper surface of the first sensing insulating layer SIL1 in the form of a convex pattern (embossed pattern), due to reasons in the manufacturing process, blank spaces such as skew may occur in the first metal layer ML1. Therefore, it may not be easy to implement the first metal layer ML1 as a fine pattern. However, according to an embodiment of the present disclosure, the first metal layer ML1 can be disposed in the first trench pattern TRC1. For example, the first metal layer ML1 can be disposed in a concave pattern (engraved pattern) rather than a convex pattern (embossed pattern) with respect to the first sensing insulating layer SIL1. Therefore, during the process of forming the first metal layer ML1, blank spaces such as skew may not be generated in the first metal layer ML1. Therefore, the first metal layer ML1 can be more easily implemented as a fine pattern.

[0126] In addition, as the line width LW of the first metal layer ML1 decreases, Figure 8 the interval PIT (e.g., pitch) of the repetition of the first trenches of the first trench pattern TRC1 shown in can be reduced. In an embodiment, the interval PIT of the repetition of the first trenches can be the same as the interval of the repetition of the lower sensing lines of the first sensing lines TSL1-1, TSL1-2, TSL1-3. For example, as the line width LW of the first metal layer ML1 decreases, the interval of the repetition of the lower sensing lines of the first sensing lines TSL1-1, TSL1-2, TSL1-3 can be reduced.

[0127] For example, in an embodiment, the pitch PIT of the repetition of the first trench pattern TRC1 may be less than or equal to about 4.0 micrometers. For example, in an embodiment, the pitch PIT of the repetition of the first trench pattern may be in the range of about 1.0 micrometer to about 4.0 micrometers. For example, in an embodiment, the pitch PIT of the repetition of the first trench pattern may be in the range of about 1.0 micrometer to about 3.0 micrometers. Accordingly, the useless space of the display device DD can be reduced.

[0128] As a method of reducing the pitch of the repetition of the lower sensing lines of the first sensing lines TSL1-1, TSL1-2, and TSL1-3, a method of increasing the resolution of the exposure apparatus and arranging adjacent lower sensing lines repeatedly at a narrow distance can be considered. However, since there are limitations in the resolution of the exposure apparatus, there are limitations in reducing the pitch of the repetition of the lower sensing lines by this method. As described above, according to an embodiment of the present disclosure, since the first metal layer ML1 is disposed in the first trench pattern TRC1, the first metal layer ML1 can be more easily formed into a fine pattern. Accordingly, regardless of the resolution of the exposure apparatus, the pitch of the repetition of the lower sensing lines of the first sensing lines TSL1-1, TSL1-2, and TSL1-3 can be reduced. Accordingly, the useless space of the display device DD can be reduced.

[0129] The second metal layer ML2 may be disposed in the first trench pattern TRC1. For example, the second metal layer ML2 may surround the inner surface of the first sensing insulating layer SIL1 that defines the first trench pattern TRC1.

[0130] The second metal layer ML2 may cover the side surface (e.g., the lateral side surface) and the lower surface of the first metal layer ML1. In an embodiment, the second metal layer ML2 may have a U-shaped cross section. Accordingly, the second metal layer ML2 can protect the first metal layer ML1 from corrosion and the like. In addition, the second metal layer ML2 can increase the color sense caused by the first metal layer ML1 and reduce the external light reflection caused by the first metal layer ML1.

[0131] In an embodiment, the second metal layer ML2 may include a different material from the first metal layer ML1. For example, the first metal layer ML1 may include a first metal material, and the second metal layer ML2 may include a second metal material different from the first metal material. In an embodiment, the first metal material may be copper (Cu), and the second metal material may be titanium (Ti). However, the embodiments of the present disclosure are not limited thereto.

[0132] In an embodiment, a first protection pattern PVX1 covering the upper surface of the first metal layer ML1 may be disposed on the first metal layer ML1 (e.g., directly on the first metal layer ML1). For example, the first protection pattern PVX1 may be disposed on the lower sensing line TSL1-11 (e.g., directly on the lower sensing line TSL1-11), and the first protection pattern PVX1 may cover the lower sensing line TSL1-11. The first protection pattern PVX1 may be disposed only at positions defining the first trench pattern TRC1. The first protection pattern PVX1 may protect the lower sensing line TSL1-11 (e.g., the first metal layer ML1) from the influence of the outside (e.g., the external environment). In an embodiment, the first protection pattern PVX1 may include an inorganic insulating material.

[0133] The first metal layer ML1, the second metal layer ML2, and the first protection pattern PVX1 may be in direct contact with each other. The first protection pattern PVX1 may directly contact the upper surfaces of the first metal layer ML1 and the second metal layer ML2 and the portion of the inner surface of the second metal layer ML2 exposed by the first metal layer ML1. For example, the second metal layer ML2 and the first protection pattern PVX1 may be in direct contact with each other, and thus, the first metal layer ML1 may be sealed by the second metal layer ML2 and the first protection pattern PVX1. Accordingly, damage to the first metal layer ML1 may be further reduced or prevented.

[0134] The second sensing insulating layer SIL2 may be disposed on the first sensing insulating layer SIL1, the lower sensing line TSL1-11, and the first protection pattern PVX1.

[0135] In an embodiment, the second sensing insulating layer SIL2 may define a second trench pattern TRC2. The second trench pattern TRC2 may be defined by recessing (e.g., in the vertical direction) from the upper surface of the second sensing insulating layer SIL2. For example, the second trench pattern TRC2 may be defined as a point recessed from the upper surface of the second sensing insulating layer SIL2 to the inside of the second sensing insulating layer SIL2 between the upper surface and the lower surface of the second sensing insulating layer SIL2. For example, in an embodiment, the second trench pattern TRC2 may be defined by arranging a plurality of second trenches, and the second trenches (e.g., in the vertical direction) do not completely penetrate the second sensing insulating layer SIL2 but only penetrate a part of the second sensing insulating layer SIL2.

[0136] The upper sensing line TSL1-12 can be disposed in the second trench pattern TRC2. For example, in an embodiment, the upper sensing lines of the first sensing lines TSL1-1, TSL1-2, TSL1-3, TSL1-4, TSL1-5 and the second sensing lines TSL2-1, TSL2-2, TSL2-3, TSL2-4 can be disposed only at positions defining the second trench pattern TRC2. For example, in an embodiment, the upper sensing lines of the first sensing lines TSL1-1, TSL1-2, TSL1-3, TSL1-4, TSL1-5 and the second sensing lines TSL2-1, TSL2-2, TSL2-3, TSL2-4 can be arranged one by one to correspond to the second trenches of the second trench pattern TRC2.

[0137] In an embodiment, the upper sensing line TSL1-12 can include a third metal layer ML3 and a fourth metal layer ML4.

[0138] The third metal layer ML3 can be disposed in the second trench pattern TRC2. For example, relative to the upper surface of the encapsulation layer ECL, the height of the upper surface of the third metal layer ML3 can be lower than the height of the upper surface of the second sensing insulating layer SIL2. For example, the third metal layer ML3 can be located below the upper surface of the second sensing insulating layer SIL2. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, relative to the upper surface of the encapsulation layer ECL, the height of the upper surface of the third metal layer ML3 can be the same as the height of the upper surface of the second sensing insulating layer SIL2. In an embodiment, the third metal layer ML3 can not protrude above the upper surface of the second sensing insulating layer SIL2. For example, the third metal layer ML3 can be arranged to fill at least a part of the blank space generated by the second trench pattern TRC2.

[0139] In an embodiment, the third metal layer ML3 can include a metal material such as copper (Cu) or aluminum (Al). For example, the third metal layer ML3 can include copper (Cu). In an embodiment where the third metal layer ML3 includes copper (Cu), the resistance of the upper sensing line TSL1-12 can be further reduced.

[0140] Since the third metal layer ML3 is disposed in the second trench pattern TRC2, it is possible to more easily implement the third metal layer ML3 as a fine pattern. For example, the line width LW of the third metal layer ML3 can be reduced. In an embodiment, the line width LW of the third metal layer ML3 can be less than or equal to about 2.6 microns. For example, the line width LW of the third metal layer ML3 can be in the range of about 0.1 micron to about 2.6 microns. For example, the line width LW of the third metal layer ML3 can be in the range of about 0.1 micron to about 1.5 microns. Therefore, the useless space of the display device DD can be reduced.

[0141] Like the first metal layer ML1, since the third metal layer ML3 is disposed in a concave pattern (engraved pattern) rather than a convex pattern (embossed pattern) with respect to the second sensing insulating layer SIL2, during the process of forming the third metal layer ML3, voids such as skews may not be generated in the third metal layer ML3. Therefore, it is possible to more easily implement the third metal layer ML3 as a fine pattern.

[0142] In addition, as the line width LW of the third metal layer ML3 decreases, Figure 8 the interval PIT (e.g., pitch) of the repetition of the second trench pattern TRC2 shown in can be decreased. In an embodiment, the interval PIT of the repetition of the second trench pattern TRC2 may be the same as the interval of the repetition of the upper sensing lines of the first sensing lines TSL1-1, TSL1-2, TSL1-3. For example, as the line width LW of the third metal layer ML3 decreases, the interval of the repetition of the upper sensing lines of the first sensing lines TSL1-1, TSL1-2, TSL1-3 can be decreased.

[0143] For example, in an embodiment, the interval PIT of the repetition of the second trench pattern TRC2 may be less than or equal to about 4.0 micrometers. For example, in an embodiment, the interval PIT of the repetition of the second trench pattern TRC2 may be in the range of about 1.0 micrometer to about 4.0 micrometers. For example, in an embodiment, the interval PIT of the repetition of the second trench pattern TRC2 may be in the range of about 1.0 micrometer to about 3.0 micrometers. Therefore, the useless space of the display device DD can be decreased.

[0144] Like the first metal layer ML1, since the third metal layer ML3 is disposed in the second trench pattern TRC2, it is possible to more easily implement the third metal layer ML3 as a fine pattern. Therefore, regardless of the resolution of the exposure device, the interval of the repetition of the upper sensing lines of the first sensing lines TSL1-1, TSL1-2, TSL1-3 can be decreased. Therefore, the useless space of the display device DD can be decreased.

[0145] The fourth metal layer ML4 may be disposed in the second trench pattern TRC2. For example, the fourth metal layer ML4 may surround the inner surface of the second sensing insulating layer SIL2 that defines the second trench pattern TRC2.

[0146] The fourth metal layer ML4 may cover the side surface (e.g., lateral side surface) and the lower surface of the third metal layer ML3. In an embodiment, the fourth metal layer ML4 may have a U-shaped shape in a cross-sectional view. Therefore, the fourth metal layer ML4 can protect the third metal layer ML3 from corrosion and the like. In addition, the fourth metal layer ML4 can increase the color sense caused by the third metal layer ML3 and reduce the external light reflection caused by the third metal layer ML3.

[0147] In an embodiment, the fourth metal layer ML4 may include a different material from the third metal layer ML3. For example, the third metal layer ML3 may include a third metal material, and the fourth metal layer ML4 may include a fourth metal material different from the third metal material. In an embodiment, the third metal material may be copper (Cu), and the fourth metal material may be titanium (Ti). However, the embodiments of the present disclosure are not necessarily limited thereto.

[0148] In an embodiment, a second protection pattern PVX2 covering the upper surface of the third metal layer ML3 may be disposed on the third metal layer ML3 (e.g., directly on the third metal layer ML3). For example, the second protection pattern PVX2 may be disposed on the upper sensing line TSL1-12, and the second protection pattern PVX2 may cover the upper sensing line TSL1-12. The second protection pattern PVX2 may be disposed only at positions defining the second trench pattern TRC2. The second protection pattern PVX2 may protect the upper sensing line TSL1-12 (e.g., the third metal layer ML3) from the influence of the outside (e.g., the external environment). In an embodiment, the second protection pattern PVX2 may include an inorganic insulating material.

[0149] In an embodiment, the third metal layer ML3, the fourth metal layer ML4, and the second protection pattern PVX2 may be in direct contact with each other. For example, the fourth metal layer ML4 and the second protection pattern PVX2 may be in direct contact with each other, and thus, the third metal layer ML3 may be sealed by the fourth metal layer ML4 and the second protection pattern PVX2. Accordingly, damage to the third metal layer ML3 may be further reduced or prevented.

[0150] A third sensing insulating layer SIL3 may be disposed on the second sensing insulating layer SIL2, the upper sensing line TSL1-12, and the second protection pattern PVX2.

[0151] Figure 9 is a cross-sectional view showing an example taken along the Figure 6 line Y-Y' according to an embodiment of the present disclosure.

[0152] Referring to Figure 6 and Figure 9 , in an embodiment, the first trench pattern ( Figure 8 the first trench pattern TRC1 in Figure 8 ) may be omitted. For example, in an embodiment, the lower sensing line TSL1-11 may be disposed on the upper surface of the first sensing insulating layer SIL1 in the form of a convex pattern, and the upper sensing line TSL1-12 may be disposed in the form of a concave pattern as described in reference to

[0153] In this embodiment, the first metal layer ML1 and the second metal layer ML2 may be sequentially stacked (e.g., in the vertical direction) on the upper surface of the first sensing insulating layer SIL1, and a first protective layer PVX1' that completely covers the lower sensing line TSL1-11 may be disposed on the first sensing insulating layer SIL1 and the lower sensing line TSL1-11. In an embodiment, the first protective layer PVX1' may include an inorganic insulating material.

[0154] Figure 10 is a cross-sectional view showing an example taken along the Figure 6 line Y-Y' of an embodiment according to the present disclosure.

[0155] Referring to Figure 6 and Figure 10 , in an embodiment, the second trench pattern (the second trench pattern TRC2 in Figure 8 ) may be omitted. For example, in an embodiment, the upper sensing line TSL1-12 may be disposed in the form of a convex pattern on the upper surface of the second sensing insulating layer SIL2, and the lower sensing line TSL1-11 may be disposed in the form of a concave pattern as described in reference Figure 8 . For example, in an embodiment, the lower surface of the upper sensing line TSL1-12 may be directly disposed on the upper surface of the second sensing insulating layer SIL2.

[0156] In this embodiment, the third metal layer ML3 and the fourth metal layer ML4 may be sequentially stacked (e.g., in the vertical direction) on the second sensing insulating layer SIL2, and a second protective layer PVX2' that completely covers the upper sensing line TSL1-12 may be disposed on the second sensing insulating layer SIL2 and the upper sensing line TSL1-12. In an embodiment, the second protective layer PVX2' may include an inorganic insulating material.

[0157] In an embodiment where the sensing line has a two-wire structure in which two lines are connected through a contact hole, at least one of the sensing lines may be arranged in the form of a concave pattern. For example, as shown in Figure 8 , both the lower sensing line and the upper sensing line may be disposed in the form of a concave pattern, or as shown in Figure 9 and Figure 10 , only one of the lower sensing line and the upper sensing line may be disposed in the form of a concave pattern.

[0158] Figures 11 to 23 is a view showing a method of manufacturing a sensing line of an embodiment according to the present disclosure. Figure 8 of

[0159] Figures 11 to 23 Selectively shows the manufacturing process for the first sensing lines TSL1-1, TSL1-2, TSL1-3 shown in Figure 8 .Figure 8 The first sensing lines TSL1-4, TSL1-5 (see Figure 6 ) and the second sensing lines TSL2-1, TSL2-2, TSL2-3, TSL2-4 (see Figure 6 ) that are not shown in Figures 11 to 23 can also be formed together by the manufacturing process shown in

[0160] Hereinafter, referring to Figures 11 to 23 , the method for manufacturing a sensing line according to an embodiment of the present disclosure will be focused on the first sensing line TSL1-1 shown in Figure 8 .

[0161] Referring to Figure 11 , a lower sacrificial layer LFL can be formed on the first sensing insulating layer SIL1 (for example, directly formed on the first sensing insulating layer SIL1), an upper sacrificial layer UFL can be formed on the lower sacrificial layer LFL (for example, directly formed on the lower sacrificial layer LFL), and a first photoresist pattern PR1 can be formed on the upper sacrificial layer UFL (for example, directly formed on the upper sacrificial layer UFL).

[0162] The lower sacrificial layer LFL can be formed of a first material. Examples of the first material that can be used as the lower sacrificial layer LFL can include aluminum (Al), chromium (Cr), titanium (Ti), gold (Au), silver (Ag), or indium tin oxide (ITO), etc. These materials can be used alone or in combination with each other. For example, the lower sacrificial layer LFL can be formed of aluminum (Al).

[0163] In an embodiment, the upper sacrificial layer UFL can be formed of a second material different from the first material. For example, the lower sacrificial layer LFL can be formed of aluminum (Al), and the upper sacrificial layer UFL can be formed of titanium (Ti). However, the embodiments of the present disclosure are not necessarily limited thereto.

[0164] In an embodiment, the first photoresist pattern PR1 can be formed by exposing and developing a photosensitive layer. The first photoresist pattern PR1 can expose a part of the upper sacrificial layer UFL.

[0165] Further referring to Figure 12 , an upper sacrificial pattern UFP can be formed by removing the part of the upper sacrificial layer UFL exposed from the first photoresist pattern PR1. For example, in an embodiment, the upper sacrificial layer UFL can be etched using the first photoresist pattern PR1 as a mask to form the upper sacrificial pattern UFP. In an embodiment, the etching process for forming the upper sacrificial pattern UFP can be a dry etching process. After forming the upper sacrificial pattern UFP, the upper sacrificial pattern UFP can expose a part of the lower sacrificial layer LFL.

[0166] Further referring toFigure 13 The lower sacrificial pattern LFP can be formed by removing the portion of the lower sacrificial layer LFL exposed from the upper sacrificial pattern UFP. For example, in an embodiment, the first photoresist pattern PR1 and the upper sacrificial pattern UFP can be used as masks to etch the lower sacrificial layer LFL to form the lower sacrificial pattern LFP. In an embodiment, the etching process for forming the lower sacrificial pattern LFP can be a wet etching process. After forming the lower sacrificial pattern LFP, the lower sacrificial pattern LFP can expose a portion of the first sensing insulating layer SIL1.

[0167] Further referring to Figure 14 The first trench pattern TRC1 can be formed by removing the portion of the first sensing insulating layer SIL1 exposed from the lower sacrificial pattern LFP. For example, in an embodiment, the first photoresist pattern PR1, the upper sacrificial pattern UFP, and the lower sacrificial pattern LFP can be used as masks to etch the first sensing insulating layer SIL1 to form the first trench pattern TRC1. In an embodiment, the etching process for forming the first trench pattern TRC1 can be a dry etching process.

[0168] In an embodiment, as described above, the first trench pattern TRC1 can be formed to be recessed from the upper surface of the first sensing insulating layer SIL1 to a point inside the first sensing insulating layer SIL1 between the upper surface and the lower surface of the first sensing insulating layer SIL1.

[0169] Referring to Figure 15 In an embodiment, a portion of the lower sacrificial pattern LFP can be removed to form an undercut structure UC. For example, in an embodiment, the portion of the lower sacrificial pattern LFP can be removed by an etching process. In an embodiment, the etching process for forming the undercut structure UC can be a wet etching process.

[0170] In an embodiment, the etching rate (e.g., etching speed) of the lower sacrificial pattern LFP for the etching process for forming the undercut structure UC can be greater than the etching rate (e.g., etching speed) of the upper sacrificial pattern UFP for the etching process for forming the undercut structure UC. For example, in an embodiment, the upper sacrificial pattern UFP can be substantially not etched by the etching process to form the undercut structure UC.

[0171] Therefore, as Figure 15 shown, the side surface of the lower sacrificial pattern LFP positioned inside the end of the upper sacrificial pattern UFP can be defined. Therefore, the upper sacrificial pattern UFP can define a tip structure related to the lower sacrificial pattern LFP. Therefore, the undercut structure UC can be formed by the side surface of the lower sacrificial pattern LFP and the lower surface of the upper sacrificial pattern UFP.

[0172] Further referring to Figure 16, the first photoresist pattern PR1 can be removed. For example, in an embodiment, the first photoresist pattern PR1 can be removed by a lift-off process. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, an etching process for forming the undercut structure UC can be performed after removing the first photoresist pattern PR1.

[0173] Referring to Figure 17 , a second metal layer ML2 and a second dummy metal layer DML2 can be formed. In an embodiment, the second metal layer ML2 and the second dummy metal layer DML2 can be formed by a deposition process of a second metal material. For example, in an embodiment, the second metal layer ML2 and the second dummy metal layer DML2 can be formed of titanium (Ti).

[0174] In this way, the second metal layer ML2 can be formed in the first trench pattern TRC1, and the second dummy metal layer DML2 can be formed on the upper sacrificial pattern UFP. For example, in an embodiment, the second metal layer ML2 and the second dummy metal layer DML2 can be formed together in the same process and can include the same material as each other. At this time, due to the undercut structure UC, the second metal layer ML2 and the second dummy metal layer DML2 can be formed discontinuously. For example, the second metal layer ML2 and the second dummy metal layer DML2 can be formed to be disconnected from each other through the undercut structure UC.

[0175] Referring to Figure 18 , a first metal layer ML1 and a first dummy metal layer DML1 can be formed. In an embodiment, the first metal layer ML1 and the first dummy metal layer DML1 can be formed by a deposition process of a first metal material. For example, in an embodiment, the first metal layer ML1 and the first dummy metal layer DML1 can be formed of copper (Cu).

[0176] In this way, the first metal layer ML1 can be formed in the first trench pattern TRC1, and the first dummy metal layer DML1 can be formed on the second dummy metal layer DML2 (e.g., directly formed on the second dummy metal layer DML2). For example, in an embodiment, the first metal layer ML1 and the first dummy metal layer DML1 can be formed together in the same process and can include the same material as each other. At this time, due to the undercut structure UC, the first metal layer ML1 and the first dummy metal layer DML1 can be formed discontinuously. For example, the first metal layer ML1 and the first dummy metal layer DML1 can be formed to be disconnected from each other through the undercut structure UC.

[0177] As a result, a lower sensing line TSL1-11 including a first metal layer ML1 and a second metal layer ML2 can be formed in the first trench pattern TRC1. In an embodiment, the first metal layer ML1 of the lower sensing line TSL1-11 can be formed in a concave pattern with respect to the first sensing insulating layer SIL1. For example, through the undercut structure UC and the first trench pattern TRC1, the first metal layer ML1 can be automatically self-patterned during deposition. Therefore, a separate etching process for forming the first metal layer ML1 may not be performed. Thus, blank spaces such as skewing due to the etching process may not be generated in the first metal layer ML1. Therefore, the first metal layer ML1 can be more easily formed into a fine pattern.

[0178] Referring to Figure 19 , a first protection pattern PVX1 and a dummy protection pattern DPVX can be formed. In an embodiment, the first protection pattern PVX1 and the dummy protection pattern DPVX can be formed by a deposition process of an inorganic insulating material.

[0179] In this way, a first protection pattern PVX1 covering the upper surface of the first metal layer ML1 can be formed on the first metal layer ML1 (e.g., directly on the first metal layer ML1), and a dummy protection pattern DPVX can be formed on the first dummy metal layer DML1 (e.g., directly on the first dummy metal layer DML1). For example, the first protection pattern PVX1 and the dummy protection pattern DPVX can be formed together in the same process and can include the same materials as each other. At this time, due to the undercut structure UC, the first protection pattern PVX1 and the dummy protection pattern DPVX may not be formed continuously. For example, the first protection pattern PVX1 and the dummy protection pattern DPVX can be formed to be disconnected from each other through the undercut structure UC.

[0180] Referring to Figure 20 , a second photoresist pattern PR2 can be formed. In an embodiment, the second photoresist pattern PR2 can be formed on the lower sensing line TSL1-11 and the first protection pattern PVX1. For example, the second photoresist pattern PR2 can be formed to cover the first protection pattern PVX1. For example, the second photoresist pattern PR2 can be formed on the first sensing insulating layer SIL1 to fill the blank spaces generated by the lower sacrificial pattern LFP, the upper sacrificial pattern UFP, the first dummy metal layer DML1, the second dummy metal layer DML2, and the dummy protection pattern DPVX. For example, in an embodiment, the second photoresist pattern PR2 can be formed to expose the dummy protection pattern DPVX. In an embodiment, the second photoresist pattern PR2 can be formed by exposing and developing a photosensitive layer.

[0181] Further referring to Figure 21, the dummy protection pattern DPVX, the first dummy metal layer DML1, the second dummy metal layer DML2, the upper sacrificial pattern UFP, and the lower sacrificial pattern LFP can be removed. For example, in an embodiment using the second photoresist pattern PR2 as a mask, the dummy protection pattern DPVX, the first dummy metal layer DML1, the second dummy metal layer DML2, the upper sacrificial pattern UFP, and the lower sacrificial pattern LFP can be etched sequentially. In an embodiment, even after the dummy protection pattern DPVX, the first dummy metal layer DML1, the second dummy metal layer DML2, the upper sacrificial pattern UFP, and the lower sacrificial pattern LFP are removed, the first metal layer ML1, the second metal layer ML2, and the first protection pattern PVX1 can remain intact under the second photoresist pattern PR2.

[0182] Further referring to Figure 22 , the second photoresist pattern PR2 can be removed. For example, in an embodiment, the second photoresist pattern PR2 can be removed by a lift-off process.

[0183] Thereafter, referring to Figure 23 , a second sensing insulating layer SIL2 can be formed on the first sensing insulating layer SIL1 (e.g., directly formed on the first sensing insulating layer SIL1). Thereafter, an upper sensing line TSL1-12 and a second protection pattern PVX2 electrically connected to the lower sensing line TSL1-11 can be formed on the second sensing insulating layer SIL2 in a manner substantially the same as the manufacturing process described with reference to Figures 11 to 22 for the lower sensing line TSL1-11 and the first protection pattern PVX1. For example, a fourth metal layer ML4 can be formed in a manner substantially the same as the manufacturing process of the second metal layer ML2 described with reference to Figure 17 , and a third metal layer ML3 can be formed in a manner substantially the same as the manufacturing process of the first metal layer ML1 described with reference to Figure 18 . In addition, a second protection pattern PVX2 can be formed in a manner substantially the same as the manufacturing process of the first protection pattern PVX1 described with reference to Figure 19 . Therefore, for the sake of simplicity of explanation, repeated descriptions are omitted.

[0184] As a result, a first sensing line TSL1-1, TSL1-2, TSL1-3 including a lower sensing line and an upper sensing line connected to each other through a contact hole can be formed.

[0185] Figure 24 is a cross-sectional view showing an example taken along the line Y-Y' according to an embodiment of the present disclosure. Figure 6 of the line Y-Y'.

[0186] In addition to including a first light-blocking pattern LB1 and a second light-blocking pattern LB2, referring to Figure 24The described input sensing layer ISU can be substantially the same as the reference Figures 6 to 8 described input sensing layer ISU. Thus, for the sake of brevity of explanation, the repeated description is omitted.

[0187] Referring to Figure 24 , in an embodiment, the input sensing layer ISU may further include a first light blocking pattern LB1 and a second light blocking pattern LB2.

[0188] The first light blocking pattern LB1 may be disposed in the first trench pattern TRC1. For example, the first light blocking pattern LB1 may surround the inner surface of the first sensing insulating layer SIL1 that defines the first trench pattern TRC1. In an embodiment, the first light blocking pattern LB1 may have a U-shaped configuration in a cross-sectional view.

[0189] The first light blocking pattern LB1 may include a light blocking material. In an embodiment, the light blocking material may be a metal material or an organic material. Examples of the metal material that can be used as the first light blocking pattern LB1 may include tantalum molybdenum oxide (MTO). For example, the first light blocking pattern LB1 may have a three-layer structure (such as MTO / Mo / MTO, MTO / Cu / MTO, and MTO / Al / MTO), a two-layer structure (such as MTO / Mo, MTO / Cu, and MTO / Al), or an MTO single-layer structure. In addition, examples of the organic material that can be used as the first light blocking pattern LB1 may include black dyes, black pigments, or carbon black, etc.

[0190] In this embodiment, the lower sensing line TSL1-11 may be disposed (e.g., directly disposed) on the first light blocking pattern LB1. For example, the first light blocking pattern LB1 may cover the outer surface of the lower sensing line TSL1-11. For example, the first light blocking pattern LB1 may cover the outer surface of the second metal layer ML2. As a result, the first light blocking pattern LB1 may cover the side surface (e.g., the lateral side surface) and the lower surface of the first metal layer ML1. Thus, the first light blocking pattern LB1 may increase the color sense caused by the first metal layer ML1 and reduce the external light reflection caused by the first metal layer ML1.

[0191] In an embodiment, the first protection pattern PVX1 may cover the first light-blocking pattern LB1, the first metal layer ML1, and the second metal layer ML2. The first light-blocking pattern LB1, the first metal layer ML1, the second metal layer ML2, and the first protection pattern PVX1 may be in direct contact with each other. For example, the first light-blocking pattern LB1, the second metal layer ML2, and the first protection pattern PVX1 may be in direct contact with each other, and thus, the first metal layer ML1 may be sealed by the first light-blocking pattern LB1, the second metal layer ML2, and the first protection pattern PVX1. Accordingly, damage to the first metal layer ML1 may be further reduced or prevented.

[0192] The second light-blocking pattern LB2 may be disposed in the second trench pattern TRC2. For example, the second light-blocking pattern LB2 may surround the inner surface of the second trench pattern TRC2 that defines the second sensing insulating layer SIL2. In an embodiment, the second light-blocking pattern LB2 may have a U-shaped configuration in a cross-sectional view.

[0193] The second light-blocking pattern LB2 may include a light-blocking material. In an embodiment, the light-blocking material may be a metal material or an organic material. Examples of the metal material that may be used as the second light-blocking pattern LB2 may include tantalum molybdenum oxide (MTO). For example, the second light-blocking pattern LB2 may have a three-layer structure (such as MTO / Mo / MTO, MTO / Cu / MTO, and MTO / Al / MTO), a two-layer structure (such as MTO / Mo, MTO / Cu, and MTO / Al), or an MTO single-layer structure. In addition, examples of the organic material that may be used as the second light-blocking pattern LB2 may include black dyes, black pigments, or carbon black, etc.

[0194] In this embodiment, the upper sensing line TSL1-12 may be disposed (e.g., directly disposed) on the second light-blocking pattern LB2. For example, the second light-blocking pattern LB2 may cover the outer surface of the upper sensing line TSL1-12. For example, the second light-blocking pattern LB2 may cover the outer surface of the fourth metal layer ML4. As a result, the second light-blocking pattern LB2 may cover the side surface (e.g., the lateral side surface) and the lower surface of the third metal layer ML3. Accordingly, the second light-blocking pattern LB2 may increase the color sense caused by the third metal layer ML3 and reduce external light reflection caused by the third metal layer ML3.

[0195] In an embodiment, the second protection pattern PVX2 may cover the second light-blocking pattern LB2, the third metal layer ML3, and the fourth metal layer ML4. The second light-blocking pattern LB2, the third metal layer ML3, the fourth metal layer ML4, and the second protection pattern PVX2 may be in direct contact with each other. For example, the second light-blocking pattern LB2, the fourth metal layer ML4, and the second protection pattern PVX2 may be in direct contact with each other, and thus, the third metal layer ML3 may be sealed by the second light-blocking pattern LB2, the fourth metal layer ML4, and the second protection pattern PVX2. Accordingly, damage to the third metal layer ML3 may be further reduced or prevented.

[0196] Figures 25 to 29 is a view showing a method of manufacturing a Figure 24 sensing line according to an embodiment of the present disclosure.

[0197] Figures 25 to 29 Selectively shown are manufacturing processes for Figure 24 the first sensing lines TSL1-1, TSL1-2, TSL1-3 shown in Figure 24 The first sensing lines TSL1-4, TSL1-5 (see Figure 6 ) and the second sensing lines TSL2-1, TSL2-2, TSL2-3, TSL2-4 (see Figure 6 ) not shown in Figures 25 to 29 may also be formed together by the manufacturing processes shown in

[0198] Hereinafter, with reference to Figures 25 to 29 a method of manufacturing a sensing line according to an embodiment of the present disclosure will be focused on the first sensing line TSL1-1 shown in Figure 24 .

[0199] Referring to Figure 25 , a lower sacrificial pattern LFP and an upper sacrificial pattern UFP defining an undercut structure UC may be formed on the first sensing insulating layer SIL1. In addition, a first trench pattern TRC1 may be formed in the first sensing insulating layer SIL1. This process may be performed in substantially the same manner as the manufacturing process described with reference to Figures 11 to 16 . Accordingly, for the sake of brevity of explanation, repeated descriptions are omitted.

[0200] Referring to Figure 26 , a first light-blocking pattern LB1 and a dummy light-blocking pattern DLB may be formed. For example, in an embodiment, the first light-blocking pattern LB1 and the dummy light-blocking pattern DLB may be formed by a deposition process of a metal material or an organic material. In an embodiment, the first light-blocking pattern LB1 and the dummy light-blocking pattern DLB may be formed of molybdenum tantalum oxide (MTO).

[0201] In this way, a first light-blocking pattern LB1 can be formed in the first trench pattern TRC1, and a dummy light-blocking pattern DLB can be formed on the upper sacrificial pattern UFP (e.g., directly on the upper sacrificial pattern UFP). For example, in an embodiment, the first light-blocking pattern LB1 and the dummy light-blocking pattern DLB can be formed together in the same process and can include the same material as each other. At this time, due to the undercut structure UC, the first light-blocking pattern LB1 and the dummy light-blocking pattern DLB can be formed discontinuously. For example, the first light-blocking pattern LB1 and the dummy light-blocking pattern DLB can be formed to be disconnected from each other through the undercut structure UC.

[0202] Referring to Figure 27 , a first metal layer ML1, a second metal layer ML2, a first protective pattern PVX1, a first dummy metal layer DML1, a second dummy metal layer DML2, and a dummy protective pattern DPVX can be formed. The first metal layer ML1 and the second metal layer ML2 can be formed in the first trench pattern TRC1, and the first protective pattern PVX1 can be formed on the first metal layer ML1 (e.g., directly on the first metal layer ML1) to cover the upper surface of the first metal layer ML1. The first dummy metal layer DML1, the second dummy metal layer DML2, and the dummy protective pattern DPVX can be formed on the dummy light-blocking pattern DLB. As a result, a lower sensing line TSL1-11 including the first metal layer ML1 and the second metal layer ML2 can be formed in the first trench pattern TRC1. For example, the lower sensing line TSL1-11 can be formed on the first light-blocking pattern LB1. In an embodiment, the first protective pattern PVX1 can have a line shape in which the entire upper surface of the first protective pattern PVX1 (e.g., in the vertical direction) is at the same height (horizontal). This process can be performed in substantially the same manner as the manufacturing process described with reference to Figures 17 to 19 . Therefore, for the sake of brevity of explanation, repeated descriptions are omitted.

[0203] Further referring to Figure 28 , the dummy protective pattern DPVX, the first dummy metal layer DML1, the second dummy metal layer DML2, the dummy light-blocking pattern DLB, the upper sacrificial pattern UFP, and the lower sacrificial pattern LFP can be removed. In an embodiment, except for adding a process of removing the dummy light-blocking pattern DLB, this process can be performed in the same manner as the reference Figures 20 to 22The described manufacturing processes are performed in substantially the same manner. Thus, for the sake of brevity of explanation, repeated descriptions are omitted. For example, even after removing the dummy protection pattern DPVX, the first dummy metal layer DML1, the second dummy metal layer DML2, the dummy light-blocking pattern DLB, the upper sacrificial pattern UFP, and the lower sacrificial pattern LFP, the first light-blocking pattern LB1, the first metal layer ML1, the second metal layer ML2, and the first protection pattern PVX1 can remain intact.

[0204] Thereafter, referring to Figure 29 , a second sensing insulating layer SIL2 can be formed (e.g., directly formed on the first sensing insulating layer SIL1) on the first sensing insulating layer SIL1. Thereafter, a second light-blocking pattern LB2, an upper sensing line TSL1-12 electrically connected to the lower sensing line TSL1-11, and a second protection pattern PVX2 can be formed on the second sensing insulating layer SIL2 in substantially the same manner as the manufacturing process described in reference Figures 25 to 28 . For example, the second light-blocking pattern LB2 can be formed in substantially the same manner as the manufacturing process of the first light-blocking pattern LB1 described in reference Figure 26 . In addition, a third metal layer ML3, a fourth metal layer ML4, and a second protection pattern PVX2 can be formed in substantially the same manner as the manufacturing processes of the first metal layer ML1, the second metal layer ML2, and the first protection pattern PVX1 described in reference Figure 27 . Thus, for the sake of brevity of explanation, repeated descriptions are omitted.

[0205] Figure 30 is a cross-sectional view showing an example taken along the line X-X' according to an embodiment of the present disclosure. Figure 6

[0206] Except that the sensing portions SP1 and SP2 (see Figure 6 ) and the connection portions CP1 and CP2 are disposed in the trench patterns TRC3 and TRC4, the input sensing layer ISU described in reference Figure 30 can be substantially the same as the input sensing layer ISU described in reference Figures 6 to 8 . Thus, repeated descriptions are omitted.

[0207] Referring to Figure 30 , in an embodiment, the input sensing layer ISU can further define a third trench pattern TRC3 and a fourth trench pattern TRC4. For example, the first sensing insulating layer SIL1 can further define the third trench pattern TRC3, and the second sensing insulating layer SIL2 can further define the fourth trench pattern TRC4. The third trench pattern TRC3 and the fourth trench pattern TRC4 can be defined in the sensing area SA of Figure 6 .

[0208] The third trench pattern TRC3 can be formed by the same process as Figure 8 the first trench pattern TRC1. For example, the third trench pattern TRC3 can be defined as being recessed from the upper surface of the first sensing insulating layer SIL1 into the first sensing insulating layer SIL1 at a point within the first sensing insulating layer SIL1 in the sensing region SA. For example, the third trench pattern TRC3 can be defined by arranging a plurality of third trenches in the sensing region SA, and the third trenches (e.g., in the vertical direction) do not completely penetrate the first sensing insulating layer SIL1 but only penetrate a part of the first sensing insulating layer SIL1.

[0209] The first connection portion CP1 can be disposed in the third trench pattern TRC3. For example, the first connection portion CP1 does not protrude above the upper surface of the first sensing insulating layer SIL1. For example, the first connection portion CP1 can be arranged to fill at least a part of the empty space generated by the third trench pattern TRC3.

[0210] The fourth trench pattern TRC4 can be formed by the same process as Figure 8 the second trench pattern TRC2. For example, the fourth trench pattern TRC4 can be defined as being recessed from the upper surface of the second sensing insulating layer SIL2 into the second sensing insulating layer SIL2 at a point within the second sensing insulating layer SIL2 in the sensing region SA. For example, the fourth trench pattern TRC4 can be defined by arranging a plurality of fourth trenches in the sensing region SA, and the fourth trenches (e.g., in the vertical direction) do not completely penetrate the second sensing insulating layer SIL2 but only penetrate a part of the second sensing insulating layer SIL2.

[0211] The first sensing portion SP1 and the second connection portion CP2 can be disposed in the fourth trench pattern TRC4. In addition, in an embodiment, the second sensing portion SP2 can also be disposed in the fourth trench pattern TRC4. For example, the first sensing portion SP1, the second sensing portion SP2, and the second connection portion CP2 do not protrude above the upper surface of the second sensing insulating layer SIL2. For example, the first sensing portion SP1, the second sensing portion SP2, and the second connection portion CP2 can be arranged to fill at least a part of the empty space generated by the fourth trench pattern TRC4.

[0212] In an embodiment, the first sensing portion SP1, the second sensing portion SP2, the first connection portion CP1, and the second connection portion CP2 can be disposed in the form of a concave pattern rather than a convex pattern with respect to the sensing insulating layer on which the respective portions are disposed.

[0213] In Figure 30In the embodiment shown, in the sensing region SA, the first sensing insulating layer SIL1 defines a third trench pattern TRC3, and the second sensing insulating layer SIL2 defines a fourth trench pattern TRC4. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, only one of the third trench pattern TRC3 and the fourth trench pattern TRC4 may be defined in the sensing region SA. For example, in an embodiment, the first connection portion CP1 may be provided in the form of a convex pattern shown in Figure 7 and the first sensing portion SP1, the second sensing portion SP2, and the second connection portion CP2 may be provided in the form of a concave pattern shown in Figure 30 . Alternatively, the first connection portion CP1 may be provided in the form of a concave pattern shown in Figure 30 and the first sensing portion SP1, the second sensing portion SP2, and the second connection portion CP2 may be provided in the form of a convex pattern shown in Figure 7 .

[0214] In an embodiment, as described above with reference to Figure 7 , the layer on which the first sensing portion SP1, the second sensing portion SP2, the first connection portion CP1, and the second connection portion CP2 are disposed may vary differently according to the embodiment. For example, according to some embodiments, the trench pattern in which each of the first sensing portion SP1, the second sensing portion SP2, the first connection portion CP1, and the second connection portion CP2 is provided may be determined as one of the third trench pattern TRC3 and the fourth trench pattern TRC4.

[0215] Embodiments of the present disclosure can be applied to various display devices. For example, embodiments of the present disclosure are applicable to various display devices (such as display devices for vehicles, ships, and aircraft, portable communication devices, display devices for exhibitions or information transmission, and medical display devices, etc.). However, embodiments of the present disclosure are not necessarily limited thereto.

[0216] The foregoing is an illustration of non-limiting embodiments of the present disclosure and should not be construed as a limitation thereof. Although several embodiments have been described, those skilled in the art will readily understand that many modifications can be made in the embodiments without substantially departing from the novel teachings and advantages of the present disclosure.

Claims

1. A display device, wherein: The display device comprises: a light emitting element layer, comprising a light emitting element; An encapsulation layer, disposed on the light emitting element layer and covering the light emitting element; A sensing electrode, disposed on the packaging layer; a sensing insulating layer disposed on the encapsulation layer, the sensing insulating layer having an upper surface, the sensing insulating layer comprising a groove pattern recessed from the upper surface; and A sensing line is disposed in the groove pattern, connected to the sensing electrode, and includes a first metal layer.

2. The display device according to claim 1, wherein: Relative to an upper surface of the packaging layer, a height of an upper surface of the first metal layer is lower than or equal to a height of an upper surface of the sensing insulation layer.

3. The display device according to claim 1, wherein: The first metal layer includes copper.

4. The display device according to claim 1, wherein: The line width of the first metal layer is less than or equal to 2.6 micrometers.

5. The display device according to claim 1, wherein: A spacing between at least two grooves defining the groove pattern is less than or equal to 4.0 micrometers.

6. The display device according to claim 1, wherein: The sensing line is disposed on the encapsulation layer only at a position where the groove pattern is defined.

7. The display device according to claim 1, wherein: The groove pattern is recessed from the upper surface of the sensing insulation layer to a point inside the sensing insulation layer between the upper surface of the sensing insulation layer and the lower surface of the sensing insulation layer.

8. The display device according to claim 1, wherein: The display device further includes: A protection pattern is disposed on the first metal layer and covers an upper surface of the first metal layer.

9. The display device according to claim 8, wherein: The protection pattern is disposed on the encapsulation layer only at a position where the groove pattern is defined.

10. The display device according to claim 8, wherein: The sensing line also includes: The second metal layer covers the side surface of the first metal layer and the lower surface of the first metal layer and includes a material different from that of the first metal layer.

11. The display device according to claim 10, wherein: The first metal layer, the second metal layer, and the protection pattern are in direct contact with each other.

12. The display device according to claim 1, wherein: The display device further includes: A light blocking pattern is disposed in the groove pattern and covers a side surface of the first metal layer and a lower surface of the first metal layer.

13. The display device according to claim 12, wherein: The light blocking pattern includes at least one material selected from a metallic material and an organic material.

14. A method for manufacturing a display device, wherein: The method comprises: forming a lower sacrificial layer including a first material on the sensing insulating layer, and forming an upper sacrificial layer including a second material different from the first material on the lower sacrificial layer; forming an upper sacrificial pattern by removing a portion of the upper sacrificial layer, and forming a lower sacrificial pattern by removing a portion of the lower sacrificial layer; removing a portion of the sensing insulation layer by using the upper sacrificial pattern and the lower sacrificial pattern as a mask to form a trench pattern; forming an undercut structure defined by the upper sacrificial pattern and the lower sacrificial pattern by removing a portion of the lower sacrificial pattern; and A metal layer is formed in the groove pattern of the sensing insulation layer.

15. The method according to claim 14, wherein: performing said forming of said trench pattern by a first etching process; performing said forming of said undercut structure by a second etching process different from said first etching process; and An etch rate of the lower sacrificial pattern for the second etch process is greater than an etch rate of the upper sacrificial pattern for the second etch process.

16. The method according to claim 15, wherein: The first etching process is a dry etching process; and The second etching process is a wet etching process.

17. The method according to claim 14, wherein: The metal layer is formed of copper.

18. The method according to claim 14, wherein: In the forming of the metal layer, a dummy metal layer including the same material as the metal layer is formed on the upper sacrificial pattern, and The dummy metal layer is formed discontinuously with the metal layer through the undercut structure.

19. The method according to claim 18, wherein: The method further comprises: A protection pattern covering an upper surface of the metal layer is formed on the metal layer.

20. The method according to claim 19, wherein: In the forming of the protection pattern, forming a dummy protection pattern including the same material as the protection pattern on the dummy metal layer; and The dummy protection pattern is formed discontinuously with the protection pattern by the undercut structure.

21. The method according to claim 20, wherein: The method further comprises: forming a photoresist pattern covering the protection pattern and exposing the dummy protection pattern; removing the dummy protection pattern, the dummy metal layer, the upper sacrificial pattern, and the lower sacrificial pattern using the photoresist pattern as a mask; and The photoresist pattern is removed.

22. The method according to claim 14, wherein: The method further comprises: forming a light blocking pattern in the groove pattern before said forming of the metal layer, and wherein, in the forming of the light blocking pattern, a dummy light blocking pattern including the same material as the light blocking pattern is formed on the upper sacrificial pattern; and The dummy light blocking pattern is formed discontinuously with the light blocking pattern by the undercut structure.

23. A display device, wherein: The display device comprises: A display panel including a light emitting element layer having light emitting elements; and An input sensing layer, on the display panel, the input sensing layer comprising a sensing electrode, a plurality of sensing lines, and a first sensing insulating layer and a second sensing insulating layer, and Each of the plurality of sensing lines includes a lower sensing line disposed at the first sensing insulating layer and an upper sensing line disposed at the second sensing insulating layer, wherein the upper sensing line and the lower sensing line are connected to each other, The lower sensing lines are arranged in a concave pattern in the upper surface of the first sensing insulating layer; and / or the upper sensing lines are arranged in a concave pattern in the upper surface of the second sensing insulating layer.

24. The display device according to claim 23, wherein: The lower sensing lines are arranged in the upper surface of the first sensing insulating layer in the concave pattern, and the upper sensing lines are arranged in the upper surface of the second sensing insulating layer in the concave pattern.

25. The display device according to claim 23, wherein: The lower sensing line and the upper sensing line are directly connected to each other through at least one contact hole defined in the second sensing insulating layer.

26. The display device according to claim 23, wherein: The sensing electrodes include first sensing electrodes arranged along a first direction, the first sensing electrodes including a first sensing portion and a first connecting portion; and The sensing electrode further includes a second sensing electrode arranged along a second direction crossing the first direction, the second sensing electrode including a second sensing portion and a second connecting portion; At least some of the first sensing portions, the first connecting portions, the second sensing portions, and the second connecting portions are arranged in a concave pattern in the upper surface of the first sensing insulating layer or the upper surface of the second sensing insulating layer, respectively.

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