Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and aims to improve the display quality of the display panel. The display panel comprises a substrate, a plurality of pixel driving circuits, a planarization layer and an anode. The planarization layer comprises a first via hole located in the transparent area, and the first via hole exposes a part of the pixel driving circuit. The anode extends from the light-emitting area to the transparent area and is electrically connected with the pixel driving circuit through the first via hole. Wherein the first via hole at least comprises a first boundary and a second boundary, the first boundary and the second boundary respectively extend along a first direction and a second direction which are parallel to the substrate and are crossed with each other, and the orthographic projection of the anode on the substrate crosses the first boundary along a third direction which is perpendicular to the first direction and parallel to the substrate; an orthographic projection of the anode on the substrate spans the second boundary in a fourth direction perpendicular to the second direction and parallel to the substrate. The display panel can be used for displaying pictures.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] During the preparation process of a large-size Organic Light-Emitting Diode (OLED) display panel, due to the thickness difference between the pixel defining layers (PDLs) in the transparent area and the light-emitting area, when the process margin is insufficient, when the PDL in the transparent area is normal, there may be a problem of PDL peeling in the light-emitting area, and when the PDL in the light-emitting area is normal, there may be a problem of PDL residue in the transparent area.

[0003] Moreover, the planarization layer is provided with small holes in the transparent area. Due to the existence of the PDL thickness difference, when the anode metal climbs at the small holes in the transparent area, it is prone to drilling fracture, forming a dark dot cluster, thereby reducing the display quality of the display panel. Summary of the Invention

[0004] This application provides a display panel and a display device, aiming to improve the display quality of the display panel.

[0005] To achieve the above object, the embodiments of this application provide the following technical solutions:

[0006] On the one hand, a display panel is provided. The display panel includes a display area, and the display area includes a plurality of light-emitting areas and a plurality of transparent areas. The display panel further includes a substrate, a plurality of pixel driving circuits, a planarization layer, and an anode. The plurality of pixel driving circuits are disposed on the substrate. The planarization layer is disposed on a side of the pixel driving circuits away from the substrate and is located in the light-emitting areas and the transparent areas. The planarization layer includes a first via hole located in the transparent area, and the first via hole exposes a part of the pixel driving circuits. The anode is disposed on a side of the planarization layer away from the substrate. The anode extends from the light-emitting areas to the transparent areas and is electrically connected to the pixel driving circuits through the first via hole. Wherein, the first via hole at least includes a first boundary and a second boundary. The first boundary extends along a first direction parallel to the substrate, and the second boundary extends along a second direction parallel to the substrate. The first direction intersects with the second direction. Along a third direction perpendicular to the first direction and parallel to the substrate, the positive projection of the anode on the substrate crosses the first boundary. Along a fourth direction perpendicular to the second direction and parallel to the substrate, the positive projection of the anode on the substrate crosses the second boundary.

[0007] The display panel provided by the embodiments of the present application includes a substrate, a plurality of pixel driving circuits, a planarization layer, and an anode. The plurality of pixel driving circuits, the planarization layer, and the anode are stacked on the substrate in this order. Among them, the planarization layer includes a first via hole in the transparent area. The first via hole exposes a part of the pixel driving circuit. The anode extends from the light-emitting area to the transparent area and is electrically connected to the pixel driving circuit through the first via hole. The pixel driving circuit is used to transmit an anode signal to the anode to drive the secondary sub-pixels to emit light.

[0008] Among them, the first via hole includes at least two boundaries (a first boundary and a second boundary) extending in different directions (a first direction and a second direction). Along the third direction and the fourth direction perpendicular to the first direction and the second direction respectively and parallel to the substrate, the orthographic projection of the anode on the substrate respectively straddles the first boundary and the second boundary. That is, the orthographic projection of the anode on the substrate at least covers at least two intersecting boundaries of the first via hole, so that the anode can "climb slopes" in multiple directions at the first via hole, avoiding the phenomenon that the anode is prone to drilling fracture along a single direction at the first via hole, resulting in dark spots or semi-dark spots on the display panel, improving the display quality of the display panel, and improving the product yield.

[0009] In some embodiments, the orthographic projection of the anode on the substrate covers the orthographic projection of the first via hole on the substrate, and the boundary of the orthographic projection of the anode on the substrate extends beyond the boundary of the orthographic projection of the first via hole on the substrate.

[0010] In some embodiments, the orthographic projection of the anode on the substrate and the orthographic projection of the first via hole on the substrate are at least partially non-overlapping, and a partial boundary of the orthographic projection of the anode on the substrate extends beyond a partial boundary of the orthographic projection of the first via hole on the substrate.

[0011] In some embodiments, the display panel further includes a passivation layer disposed between the pixel driving circuit and the planarization layer. The passivation layer includes a second via hole in the transparent area. The second via hole exposes a part of the pixel driving circuit. The boundary of the orthographic projection of the first via hole on the substrate surrounds the outside of the boundary of the orthographic projection of the second via hole on the substrate.

[0012] In some embodiments, the difference between the side length of the orthographic projection of the first via hole on the substrate and the side length of the orthographic projection of the second via hole on the substrate is greater than or equal to 3 micrometers.

[0013] In some embodiments, along the direction perpendicular to the substrate, the depth ratio range of the first via hole to the second via hole is 4 to 8.75.

[0014] In some embodiments, the display panel further includes a pixel defining layer disposed on the side of the anode away from the substrate. The pixel defining layer includes a plurality of openings in the light-emitting area. The openings expose the anode. The planarization layer further includes trenches in the light-emitting area. At least part of the pixel defining layer is in the trenches.

[0015] In some embodiments, the trench penetrates the planarization layer.

[0016] In some embodiments, the ratio of the thickness of the planarization layer to the width of the trench ranges from 0.4 to 1.75.

[0017] In some embodiments, at least a part of the pixel defining layer is also located in the first via.

[0018] In some embodiments, the material of the planarization layer includes silicon oxide.

[0019] On the other hand, a display device is provided, which includes the display panel in any of the above embodiments and a controller electrically connected to the display panel.

[0020] The above display device has the same structure and beneficial technical effects as the display panel provided in some of the above embodiments, and will not be elaborated here. Description of the Drawings

[0021] In order to more clearly illustrate the technical solutions in the present application, the drawings required to be used in some embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only the drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and do not represent the actual sizes of the products and the actual processes of the methods involved in the embodiments of the present application.

[0022] Figure 1 Structural diagram of the display device provided in the embodiment of the present application;

[0023] Figure 2 For Figure 1 Partial enlarged view of the display panel in

[0024] Figure 3 For Figure 2 Partial cross-sectional view of the display panel in

[0025] Figure 4 Another partial cross-sectional view of the display panel provided in the embodiment of the present application along the section line A-A';

[0026] Figure 5 Another partial enlarged view of the display panel provided in the embodiment of the present application at M;

[0027] Figure 6 For Figure 5 Partial cross-sectional view of the display panel in Detailed Description of the Embodiments

[0028] The following will clearly and completely describe the technical solutions in some embodiments of the present application in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided in the present application fall within the scope of protection of the present application.

[0029] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, i.e., "including, but not limited to".

[0030] Hereinafter, the terms "first" and "second" are used only for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0031] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or integrated; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other.

[0032] In addition, the use of "based on" means open and inclusive, because a process, step, calculation, or other action "based on" one or more of the stated conditions or values may in practice be based on additional conditions or values beyond those stated.

[0033] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0034] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of the regions are enlarged for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Accordingly, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0035] Embodiments of the present application provide a display device, which may be a large-size Organic Light-Emitting Diode (OLED) display device. Figure 1 It is a structural diagram of the display device provided by the embodiments of the present application.

[0036] Refer to Figure 1 , the display device 100 includes a display panel 10 and a controller 20 electrically connected to the display panel 10. The controller 20 can be disposed on the non-display side of the display panel 10 and is used to control the display panel 10 to perform screen display.

[0037] The above display device can be any device that displays whether it is moving (e.g., video) or stationary (e.g., still image), and whether it is text or image. More specifically, it is expected that the embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0038] Figure 2 It is Figure 1 a partial enlarged view of the display panel at M in Figure 3 It is Figure 2 a partial cross-sectional view of the display panel along the section line A-A' in

[0039] Refer to Figure 2 , the display panel 10 includes a display area 11. The display area 11 includes a plurality of light-emitting areas 12 and a plurality of transparent areas 13. For example, along the direction X, the transparent areas 13 are located on opposite sides of the light-emitting areas 12.

[0040] Refer to Figure 3 , the display panel 10 includes a substrate 1, a plurality of pixel driving circuits 2, a planarization layer 3, and an anode 5.

[0041] Exemplarily, the thickness range of the substrate 1 is 50um to 1000um. The substrate 1 can be Corning glass, Asahi Glass, or quartz glass and other transparent materials.

[0042] Exemplarily, the display panel 10 further includes a light-shielding layer 14 and a buffer layer 15 disposed on the substrate 1. Metal can be deposited on the substrate 1 by using a magnetron sputtering device, and through photolithography, wet etching patterning, and stripping the photoresist on the metal surface, the pattern of the light-shielding layer 14 can be obtained.

[0043] Then, a plasma enhanced chemical vapor deposition (PECVD) process is used to deposit and form the buffer layer 15. The material of the buffer layer 15 includes SiN x , SiO x or SiO x N y or one or more of them, and the thickness range of the buffer layer 15 is 150 nm to 500 nm.

[0044] The pixel driving circuit 2 is disposed on the substrate 1, and the pixel driving circuit 2 is located on the side of the light-shielding layer 14 away from the substrate 1. The light-shielding layer 14 extends from the light-emitting region 12 to the transparent region 13. The pixel driving circuit 2 includes a plurality of thin film transistors located in the light-emitting region 12. The plurality of thin film transistors include driving transistors. In the light-emitting region 12, the light-shielding layer 14 can block the light from the back of the display panel 10 to prevent the light from irradiating the driving transistors and causing the drift of their threshold voltages. Moreover, the source or drain of the driving transistor is electrically connected to the light-shielding layer 14, and the anode signal output by the driving transistor can be transmitted to the transparent region 13 through the light-shielding layer 14.

[0045] Exemplarily, the process of forming the plurality of pixel driving circuits 2 includes the following steps S1 to step S4:

[0046] Step S1: Refer to Figure 3 , an oxide is deposited on the buffer layer 15 as the active layer of the thin film transistor by using a magnetron sputtering device, and through photolithography, wet etching patterning, and stripping the photoresist on the metal surface, the active layer located in the light-emitting region 12 can be obtained. The above-mentioned oxide can be an amorphous oxide such as IGZO, ZnON, ITZO, etc.

[0047] Step S2: A gate insulating film is deposited by a chemical vapor deposition method, and a gate conductive film is deposited on the gate insulating film again by using a magnetron sputtering device. The metal thickness is 200 nm to 1000 nm. The composition of the gate conductive film can be Al, Mo, Cr, Cu, Ti, etc. The gate pattern is defined through photolithography and wet etching processes to form a gate conductive layer. At the same time, the photoresist is not stripped, and the gate insulating film is etched continuously by using the photoresist on the gate conductive layer as a mask to form a gate insulating layer.

[0048] Step S3: Refer to Figure 3, any one of NH3, N2, and H2 is used to conductivize the exposed IGZO to reduce the ohmic contact resistance between the active layer and the source-drain conductive layer. The interlayer insulating layer 16 is deposited by plasma-enhanced chemical vapor deposition process. The patterns of the deposited interlayer insulating holes and contact holes are defined through photolithography process. The contact holes between the source and drain electrodes of the driving transistor and the active layer, and the contact hole 161 connecting one of the source or drain electrodes to the light-shielding layer 102 are obtained through photolithography process. The interlayer insulating layer 16 is SiN x or SiO x single-layer or multi-layer structure.

[0049] Step S4: The source-drain conductive film is deposited by magnetron sputtering process. The deposited metal can be Al, Mo, Cr, Cu, Ti, etc. The thickness of the source-drain conductive film is 200nm to 1000nm. The pattern of the source-drain conductive layer is obtained through photolithography and wet etching processes to obtain the source-drain conductive layer. The source-drain conductive layer can be a two-layer or three-layer copper structure such as MoNb / Cu, MTD / Cu, MoNb / Cu / MTD, MoNb / Cu / ITO, or MoTD / Cu / ITO.

[0050] Exemplarily, referring to Figure 3 , the pixel driving circuit 2 further includes a transfer electrode 21 disposed in the transparent region 13. For example, the transfer electrode 21 is made of the same material as the above-mentioned source-drain conductive layer and is disposed in the same layer. In the transparent region 13, the transfer electrode 21 penetrates the interlayer insulating layer 16 and is electrically connected to the light-shielding layer 14.

[0051] The planarization layer 3 is disposed on the side of the pixel driving circuit 2 away from the substrate 1 and is located in the light-emitting region 12 and the transparent region 13. The planarization layer 3 includes a first via 31 in the transparent region 13, and the first via 31 exposes a part of the pixel driving circuit 2. For example, the first via 31 exposes the above-mentioned transfer electrode 21.

[0052] Exemplarily, referring to Figure 3 , the material of the planarization layer 3 includes silicon oxide.

[0053] For example, in the case where the planarization material is an organic solution containing silicon element, only a single-layer planarization layer 3 can be made in the display panel 10. The slit method can be used to deposit the planarization material as the planarization layer 3. The above-mentioned planarization material refers to an organic solution containing silicon element. After being cured by ultraviolet light irradiation or high-temperature baking, a solid silicon oxide film can be formed. The planarization material undergoes pre-baking, exposure, and development curing to form a pattern in the light-emitting region 12 and the transparent region 13. After drying at 230°C to remove water and organic solvents, the planarization layer 3 is obtained.

[0054] Exemplarily, the planarization material is organosilicone glass (SOG), and the organosilicone glass has a high transmittance. In the embodiments of the present application, the planarization layer 3 is coated on the entire surface of the light-emitting region 12 and the transparent region 13. Since the organosilicone glass has a high transmittance, it does not affect the transmission of light in the transparent region 13 of the planarization layer 3. Moreover, the thickness of the planarization layer 3 formed of the organosilicone glass material is uniform, making the surfaces of the light-emitting region 12 and the transparent region 13 flat. During the subsequent formation of the Pixel Defining Layer (PDL), problems such as the remaining and peeling of the PDL film layer are not likely to occur, thereby improving the product yield of the display panel 10.

[0055] Exemplarily, referring to Figure 2 and Figure 3 , the display panel 10 further includes a plurality of sub-pixels 4. The plurality of sub-pixels 4 are disposed on the side of the planarization layer 3 away from the substrate 1. One light-emitting region 12 is provided with one sub-pixel 4. One sub-pixel 4 includes two secondary sub-pixels, and the two secondary sub-pixels are respectively a first secondary sub-pixel 41 and a second secondary sub-pixel 42. Each secondary sub-pixel includes two pixel openings.

[0056] Exemplarily, the first secondary sub-pixel 41 is located on the right side of the transparent region 13. The first secondary sub-pixel 41 includes a green pixel opening and a blue pixel opening. The second secondary sub-pixel 42 is located on the left side of the transparent region 13. The second secondary sub-pixel 42 includes a red pixel opening and a white pixel opening.

[0057] Continuing to refer to Figure 2 and Figure 3 , each secondary sub-pixel includes the aforementioned anode 5, and the anode 5 extends from the light-emitting region 12 to the transparent region 13. Exemplarily, the process of forming the anode 5 includes the following steps S5 to S7:

[0058] Step S5: Depositing an anode layer of indium tin oxide (ITO) by magnetron sputtering and obtaining an anode pattern using a patterning process. The anode layer of indium tin oxide is used for Array Test (AT) and repair.

[0059] Step S6: Depositing an auxiliary electrode layer by magnetron sputtering. The auxiliary electrode layer is a triple layer of ITO / Cu / MoNb. Cu can also be replaced by Al, Mo, etc. The thickness of the auxiliary electrode layer is 6000 nm to 8000 nm. Using patterning and etching processes, an auxiliary electrode pattern is obtained.

[0060] Step S7: Depositing an anode layer by magnetron sputtering. The anode layer is a triple layer of Cu / MoNb / ITO. An anode pattern can be obtained using a patterning process.

[0061] During the process of repairing dark spots on the display panel 10, due to the existence of the first via 31, there is only an inorganic film layer (such as the substrate 1, the buffer layer 15, and the interlayer insulating layer 16, etc.) under the anode 5 in the transparent area 13. The inorganic film layer has a relatively high melting point and is not easily leveled, splashed, or diffused after laser high-temperature cutting, thereby improving the success rate of ITO laser cutting during dark spot repair.

[0062] The anode 5 is electrically connected to the pixel driving circuit 2 through the first via 31. For example, the anode 5 is electrically connected to the transfer electrode 21 through the first via 31. The anode signal from the driving transistor is transmitted to the anode 5 through the light-shielding layer 14 and the transfer electrode 21 to drive each secondary sub-pixel to emit light.

[0063] Continue to refer to Figure 2 and Figure 3 The first via 31 at least includes a first boundary E and a second boundary F. The first boundary E extends along a first direction parallel to the substrate 1, and the second boundary F extends along a second direction parallel to the substrate 1. The first direction intersects the second direction. In the embodiments of the present application, taking the first direction as the direction X and the second direction as the direction Y as an example for illustration, and the first direction is perpendicular to the second direction.

[0064] Exemplarily, when the first direction is the direction X, along a third direction (direction Y) perpendicular to the first direction and parallel to the substrate 1, the positive projection of the anode 5 on the substrate 1 crosses the first boundary E. When the second direction is the direction Y, along a fourth direction (direction X) perpendicular to the second direction and parallel to the substrate 1, the positive projection of the anode 5 on the substrate 1 crosses the second boundary F.

[0065] The display panel 10 provided by the embodiments of the present application includes a substrate 1, a plurality of pixel driving circuits 2, a planarization layer 3, and an anode 5. The plurality of pixel driving circuits 2, the planarization layer 3, and the anode 5 are sequentially stacked on the substrate 1. Among them, the planarization layer 3 includes a first via 31 located in the transparent area 13. The first via 31 exposes a part of the pixel driving circuit 2. The anode 5 extends from the light-emitting area 12 to the transparent area 13 and is electrically connected to the pixel driving circuit 2 through the first via 31. The pixel driving circuit 2 is used to transmit an anode signal to the anode 5 to drive the secondary sub-pixel to emit light.

[0066] Among them, the first via 31 includes at least two boundaries (first boundary E and second boundary F) extending in different directions (first direction and second direction), respectively along a third direction and a fourth direction perpendicular to the first direction and the second direction and parallel to the substrate 1, and the positive projection of the anode 5 on the substrate 1 respectively crosses the first boundary E and the second boundary F, that is, the positive projection of the anode 5 on the substrate 1 at least covers at least two intersecting boundaries of the first via 31, so that the anode 5 can "climb" in multiple directions at the first via 31, avoiding the phenomenon that the anode 5 climbs in a single direction at the first via 31 and is prone to drilling and breaking, resulting in dark spots or semi-dark spots on the display panel 10, thereby improving the display quality of the display panel 10 and improving the product yield.

[0067] In some embodiments, see Figure 2 and Figure 3 , the orthographic projection of the anode 5 on the substrate 1 covers the orthographic projection of the first via hole 31 on the substrate 1, and the boundary G of the orthographic projection of the anode 5 on the substrate 1 exceeds the boundary H of the orthographic projection of the first via hole 31 on the substrate 1, and the boundary H includes the first boundary E and the second boundary F involved above. That is, the anode 5 fully covers the first via hole 31, and along the plane parallel to the substrate 1, the anode 5 can climb along any direction at the first via hole 31, which can avoid the problem of drilling and breaking of the anode 5 climbing along a single direction, thereby improving the display quality of the display panel 10.

[0068] Figure 4 A partial cross-sectional view of another display panel provided in an embodiment of the present application along section line AA′.

[0069] In some embodiments, see Figure 4 The display panel 10 further includes a passivation layer 6 disposed between the pixel driving circuit 2 and the planarization layer 3. The passivation layer 6 is deposited by chemical vapor deposition, and the material of the passivation layer 6 is silicon oxide. The passivation layer 6 includes a second via hole 62 located in the transparent area 13. The second via hole 62 can be formed by an exposure process. The second via hole 62 exposes a portion of the pixel driving circuit 2. For example, the second via hole 62 exposes the switching electrode 21. The anode 5 is electrically connected to the switching electrode 21 through the first via hole 31 and the second via hole 62.

[0070] The boundary Q of the orthographic projection of the first via hole 31 on the substrate 1 surrounds the outer side of the boundary P of the orthographic projection of the second via hole 62 on the substrate 1, that is, the first via hole 31 surrounds the second via hole 62. The anode 5 covers the first via hole 31 and the second via hole 62, so that the anode 5 can overlap with the switching electrode 21 normally.

[0071] For example, see Figure 4, the ratio range of the area of the positive projection of the first via 31 on the substrate 1 to the area of the positive projection of the second via 62 on the substrate 1 is 1.2 to 1.5. For example, the ratio of the area of the positive projection of the first via 31 to the area of the positive projection of the second via 62 is 1.2, 1.3, 1.35, 1.4, or 1.5. It can be understood that the first via 31 surrounds the second via 62, and the opening area of the first via 31 is larger than that of the second via 62, which can slow down the slope of the sidewall of the first via 31, thereby slowing down the slope of the anode 5 climbing at the first via 31, and thus reducing the possibility of drilling and breaking caused by the anode 5 climbing in the transparent region 13.

[0072] Exemplarily, continue to refer to Figure 4 , along the direction perpendicular to the substrate 1 (direction Z), the thickness of the planarization layer 3 is thicker than the thickness of the passivation layer 6, so that the depth of the first via 31 is deeper than that of the second via 62. The ratio range of the depth of the first via 31 to the depth of the second via 62 is 4 to 8.75. For example, the ratio of the depth of the first via 31 to the depth of the second via 62 can be 4, 5, 6.375, 7, or 8.75, etc. It can be understood that the thickness of the planarization layer 3 is larger. During the process of etching the planarization layer 3 to form the first via 31, it is necessary to make the opening area of the first via 31 larger, which is beneficial to forming the first via 31 with a gentler slope, thereby slowing down the slope of the anode 5 climbing at the first via 31 and reducing the possibility of drilling and breaking caused by the anode 5 climbing in the transparent region 13.

[0073] For example, continue to refer to Figure 4 , the thickness range of the passivation layer 6 is 4000 Å to 5000 Å, and the thickness range of the planarization layer 3 is 2.0 μm to 3.5 μm. The thickness of the planarization layer 3 is thicker than the thickness of the passivation layer 6.

[0074] In the related art, no planarization layer is provided in the transparent region, and a pixel defining layer is provided above the planarization layer. While ensuring the transparency of the transparent region, the thickness difference between the pixel defining layers in the transparent region and the light emitting region is more than 3.2 μm, resulting in a relatively obvious thickness difference between the transparent region and the light emitting region. When the process margin is insufficient, when the pixel defining layer in the transparent region is normal, there may be a problem of peeling of the pixel defining layer in the pixel region. When the pixel defining layer in the pixel region is normal, there may be a problem of remaining pixel defining layer in the transparent region.

[0075] The material of the above-mentioned planarization layer 3 can be a conventional organic material or silicone glass.

[0076] An embodiment of the present application is described by taking the material of the planarization layer 3 as silicone glass as an example. Since silicone glass has a high transmittance, it does not affect the transmission of light in the transparent region 13 of the planarization layer 3. Therefore, in the embodiment of the present application, the planarization layer 3 is provided in the transparent region 13, reducing the thickness difference between the transparent region 13 and the light-emitting region 12, so that the thickness difference of the pixel defining layer to be developed between the transparent region 13 and the light-emitting region 12 is reduced, thereby improving the problem that it is impossible to balance both the peeling and the remaining of the pixel defining layer, and improving the product yield of the display panel 10.

[0077] Figure 5 It is a partial enlarged view of another display panel provided by an embodiment of the present application at M; Figure 6 is Figure 5 a partial cross-sectional view of the display panel in [reference] along the section line B-B'.

[0078] In some embodiments, referring to Figure 5 and Figure 6 , the orthographic projection of the anode 5 on the substrate 1 does not at least partially overlap with the orthographic projection of the first via 31 on the substrate 1, that is, in the transparent region 13, the anode 5 does not completely cover the first via 31, so as to increase the amount of light transmitted through the first via 31, thereby increasing the light transmittance of the transparent region 13.

[0079] Moreover, a partial boundary of the orthographic projection of the anode 5 on the substrate 1 extends beyond a partial boundary of the orthographic projection of the first via 31 on the substrate 1. Exemplarily, the boundary G of the orthographic projection of the anode 5 on the substrate 1 extends beyond the first boundary E, the third boundary K, and the fourth boundary L of the orthographic projection of the first via 31 on the substrate 1. Along the plane (plane X-Y) parallel to the substrate 1, the anode 5 can climb at multiple directions at the first via 31. The above-mentioned multiple directions include, for example, the direction Y perpendicular to the first boundary E and the third boundary K, or the direction X perpendicular to the fourth boundary L, etc. The anode 5 climbs at multiple directions at the first via 31, avoiding the problem that the anode 5 is prone to drilling fracture when climbing in a single direction, thereby improving the display quality of the display panel 10.

[0080] In some embodiments, referring to Figure 5 and Figure 6 , the display panel 10 further includes a pixel defining layer 7 disposed on the side of the anode 5 away from the substrate 1. The pixel defining layer 7 includes a plurality of openings 70 located in the light-emitting region. The plurality of openings 70 expose the anode 5. Exemplarily, two openings 70 expose one anode 5.

[0081] Exemplarily, the slit method can be used to deposit an organic film material. After pre-baking, exposure, and development, the patterns of the cured light-emitting region 12 and the transparent region 13 are exposed, and then dried at 230 °C to remove water and organic solvents to obtain the pixel defining layer 7. The thickness of the pixel defining layer 7 is 0.7 um to 2.5 um.

[0082] Moreover, the planarization layer 3 further includes a trench 32 located in the light-emitting region 13. The trench 32 may penetrate through the planarization layer 3 or may not penetrate through the planarization layer 3. In the embodiments of the present application, the case where the trench 32 penetrates through the planarization layer 3 is taken as an example for illustration. At least a part of the pixel definition layer 7 is located in the trench 32, which is equivalent to the pixel definition layer 7 being embedded in the trench 32, increasing the contact area between the pixel definition layer 7 and the planarization layer 3, thereby increasing the film adhesion of the pixel definition layer 7 in the light-emitting region 12 and improving the problem of peeling of the pixel definition layer 7 in the light-emitting region 12.

[0083] In some embodiments, referring to Figure 6 , at least a part of the pixel definition layer 7 is also located in the first via 31, and at least a part of the pixel definition layer 7 is located in the trench 32. The thickness difference of the pixel definition layer 7 located in the light-emitting region 12 and the transparent region 13 is reduced, increasing the film adhesion of the pixel definition layer 7, thereby improving the problem of peeling of the pixel definition layer 7 in the light-emitting region 12.

[0084] Exemplarily, in the case where the trench 32 penetrates through the planarization layer 3, since the first via 31 also penetrates through the planarization layer 3, and at least a part of the pixel definition layer 7 is located in the trench 32, the thickness of the pixel definition layer 7 located in the light-emitting region 12 and the transparent region 13 is made consistent, which can further increase the film adhesion of the pixel definition layer 7, thereby improving the problem of peeling of the pixel definition layer 7 in the light-emitting region 12.

[0085] In some embodiments, referring to Figure 6 , in the case where the trench 32 penetrates through the planarization layer 3, the ratio range of the thickness of the planarization layer 3 to the width of the trench 32 is 0.4 to 1.75. It can be understood that the aspect ratio range of the trench 32 is 0.4 to 1.75. Exemplarily, the aspect ratio of the trench 32 can be 0.4, 0.7, 1.075, 1.4 or 1.75. Exemplarily, the thickness range of the planarization layer 3 is 2.0 micrometers to 3.5 micrometers, and the width range of the trench 32 is 2.0 micrometers to 5.0 micrometers. Among them, when the spacing between two adjacent trenches 32 ensures a sufficient aperture ratio, the larger the spacing, the better the effect of improving the peeling problem of the pixel definition layer 7 in the light-emitting region 12. In terms of the width setting of the trench 32, the minimum value of the width of the trench 32 is related to the exposure accuracy of the exposure machine. It can be understood that, when the accuracy of the photolithography process permits, setting the trench 32 with a suitable aspect ratio can achieve the effect of improving the peeling problem of the pixel definition layer 7 in the light-emitting region 12.

[0086] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application, who thinks of changes or substitutions, should be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims described above.

Claims

1. A display panel, characterized in that: comprising a display area, wherein the display area comprises a plurality of light-emitting areas and a plurality of transparent areas; The display panel comprises: substrate; A plurality of pixel driving circuits are arranged on the substrate; a planarization layer, arranged on a side of the pixel driving circuit away from the substrate and located in the light emitting area and the transparent area; the planarization layer comprises a first via hole located in the transparent area, the first via hole exposing a portion of the pixel driving circuit; an anode, disposed on a side of the planarization layer away from the substrate, the anode extending from the light-emitting area to the transparent area and electrically connected to the pixel driving circuit through the first via hole; The first via hole at least includes a first boundary and a second boundary, the first boundary extends along a first direction parallel to the substrate, the second boundary extends along a second direction parallel to the substrate, and the first direction intersects with the second direction; Along a third direction perpendicular to the first direction and parallel to the substrate, the orthographic projection of the anode on the substrate crosses the first boundary; along a fourth direction perpendicular to the second direction and parallel to the substrate, the orthographic projection of the anode on the substrate crosses the second boundary.

2. The display panel according to claim 1, characterized in that: The orthographic projection of the anode on the substrate covers the orthographic projection of the first via on the substrate, and a boundary of the orthographic projection of the anode on the substrate exceeds a boundary of the orthographic projection of the first via on the substrate.

3. The display panel according to claim 1, characterized in that: The orthographic projection of the anode on the substrate at least partially does not overlap with the orthographic projection of the first via on the substrate, and a partial boundary of the orthographic projection of the anode on the substrate exceeds a partial boundary of the orthographic projection of the first via on the substrate.

4. The display panel according to claim 2 or 3, characterized in that: The display panel further includes a passivation layer disposed between the pixel driving circuit and the planarization layer, the passivation layer including a second via hole located in the transparent area, the second via hole exposing a portion of the pixel driving circuit; The boundary of the orthographic projection of the first via hole on the substrate surrounds the outside of the boundary of the orthographic projection of the second via hole on the substrate.

5. The display panel according to claim 4, characterized in that: The ratio of the area of ​​the orthographic projection of the first via hole on the substrate to the area of ​​the orthographic projection of the second via hole on the substrate is in the range of 1.2 to 1.

5.

6. The display panel according to claim 4, characterized in that: Along a direction perpendicular to the substrate, a depth ratio of the first via hole to the second via hole ranges from 4 to 8.

75.

7. The display panel according to claim 1, characterized in that: The display panel further comprises a pixel defining layer disposed on a side of the anode away from the substrate, the pixel defining layer comprising a plurality of openings located in the light emitting area, the openings exposing the anode; The planarization layer further includes a groove located in the light emitting area, and at least a portion of the pixel definition layer is located in the groove.

8. The display panel according to claim 7, characterized in that: The trench penetrates the planarization layer.

9. The display panel according to claim 8, characterized in that: The ratio of the thickness of the planarization layer to the width of the groove is in the range of 0.4 to 1.

75.

10. The display panel according to any one of claims 7 to 9, characterized in that: At least a portion of the pixel defining layer is also located within the first via hole.

11. The display panel according to claim 1, characterized in that: The material of the planarization layer includes silicon oxide.

12. A display device, characterized in that: include: The display panel according to any one of claims 1 to 11; A controller is electrically connected to the display panel.

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