Method of manufacturing display device

Abstract

The present disclosure relates to a method of manufacturing a display device, the method including: forming a first electrode on a substrate; forming an insulating layer across the first electrode; aligning a first light emitting element on the insulating layer; exposing the insulating layer; exposing at least a portion of the first electrode by developing the insulating layer; and bonding the first light emitting element to at least a portion of the first electrode.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0191537, filed with the Korean Intellectual Property Office on December 26, 2023, the entire content of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a method of bonding a light - emitting element and a method of manufacturing a display device having a light - emitting element. Background art

[0004] With the development of information technology, the importance of display devices as a connection medium between users and information has increased. Accordingly, display devices such as liquid - crystal display devices, organic light - emitting display devices, and inorganic light - emitting display devices are increasingly used. Summary of the invention

[0005] Embodiments provide a method of manufacturing a display device in which a light - emitting element is used as a mask.

[0006] Embodiments also provide a method of bonding a light - emitting element in which a light - emitting element is used as a mask.

[0007] According to an aspect of the present disclosure, a method of manufacturing a display device is provided. The method may include: forming a first electrode on a substrate; forming an insulating layer over the first electrode; aligning a first light - emitting element over the insulating layer; exposing the insulating layer; exposing at least a portion of the first electrode by developing the insulating layer; and bonding the first light - emitting element to at least a portion of the first electrode.

[0008] The first light - emitting element may include a first bonding electrode bonded to at least a portion of the first electrode.

[0009] The first light - emitting element may further include: a semiconductor layer; and a reflective electrode disposed between the semiconductor layer and the first bonding electrode.

[0010] Bonding the first light - emitting element may include: positioning the first bonding electrode in an opening of the insulating layer that exposes at least a portion of the first electrode; and melting the first bonding electrode.

[0011] An opening of the insulating layer that exposes at least a portion of the first electrode may be formed at a position corresponding to the position of the first bonding electrode.

[0012] During the process of forming the first electrode, a second electrode spaced apart from the first electrode may be formed. During the process of developing the insulating layer, at least a portion of the second electrode may be exposed. The first light - emitting element may be bonded to at least a portion of the first electrode and at least a portion of the second electrode.

[0013] The first light-emitting element may include a second bonding electrode bonded to at least a part of the second electrode.

[0014] The insulating layer may include a photosensitive organic insulating material.

[0015] The first light-emitting element may be bonded to the first electrode of the first sub-pixel. The method may further include bonding an additional light-emitting element to the first electrode of a repair region adjacent to the first sub-pixel in the case where the first light-emitting element is defective.

[0016] Bonding the additional light-emitting element may include: aligning the additional light-emitting element in the repair region on the insulating layer; exposing the insulating layer; developing the insulating layer to expose at least a part of the first electrode of the repair region; and bonding the additional light-emitting element to at least a part of the first electrode of the repair region.

[0017] The first light-emitting element may be bonded to the first electrode of the first sub-pixel. The method may further include bonding an additional light-emitting element to the first electrode of an overlapping region adjacent to the first sub-pixel.

[0018] In the case where the first light-emitting element becomes defective, the additional light-emitting element may be driven.

[0019] The first light-emitting element may be bonded to the first electrode of the first sub-pixel. The method may further include: aligning a second light-emitting element in the second sub-pixel on the insulating layer; repeatedly exposing the insulating layer; developing the insulating layer again to expose at least a part of the first electrode of the second sub-pixel; and bonding the second light-emitting element to at least a part of the first electrode of the second sub-pixel.

[0020] The first sub-pixel and the second sub-pixel may display different colors.

[0021] According to another aspect of the present disclosure, a method of bonding a light-emitting element is provided. The method may include: aligning a light-emitting element on an insulating layer formed over an electrode; exposing the insulating layer; developing the insulating layer to expose at least a part of the electrode; and bonding the light-emitting element to at least a part of the electrode.

[0022] The light-emitting element may include a bonding electrode bonded to at least a part of the electrode.

[0023] Bonding the light-emitting element may include: positioning the bonding electrode in an opening exposing at least a part of the electrode of the insulating layer; and melting the bonding electrode.

[0024] An opening exposing at least a part of the electrode of the insulating layer may be formed at a position corresponding to the position of the bonding electrode.

[0025] The light-emitting element may further include a semiconductor layer and a reflective electrode disposed between the semiconductor layer and the bonding electrode.

[0026] The insulating layer may include a photosensitive organic insulating material. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, the embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0028] In the drawings, the dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being “between” two elements, it may be the only element between the two elements, or there may be one or more intervening elements. The same reference numerals refer to the same elements throughout.

[0029] Figure 1 is a schematic block diagram showing an embodiment of a display device.

[0030] Figure 2 is showing Figure 1 a schematic block diagram of an embodiment of any one of the sub-pixels shown in.

[0031] Figure 3 is showing Figure 1 a schematic plan view of an embodiment of the display panel shown in.

[0032] Figure 4 is showing Figure 3 a schematic cross-sectional view of an embodiment of the display panel shown in.

[0033] Figure 5 is showing Figure 3 a schematic cross-sectional view of another embodiment of the display panel shown in.

[0034] Figure 6 is showing Figure 3 a schematic plan view of an embodiment of any one of the pixels shown in.

[0035] Figure 7 is along Figure 6 a schematic cross-sectional view taken along line I-I' shown in.

[0036] Figure 8 is along Figure 6 a schematic cross-sectional view taken along line II-II' shown in.

[0037] Figure 9Schematically shows a method of manufacturing a display device according to an embodiment of the present disclosure.

[0038] Figures 10 to 17 Shows sequentially Figure 9 A schematic diagram of the method shown in

[0039] Figure 18 And Figure 19 Is a schematic diagram showing the first light-emitting element aligned at a misaligned position.

[0040] Figure 20 Is a schematic diagram showing the bonding of the first light-emitting element of a display device according to an embodiment of the present disclosure.

[0041] Figure 21 Is a schematic plan view of a pixel of a display device according to an embodiment of the present disclosure.

[0042] Figure 22 Is along Figure 21 A schematic cross-sectional view taken along the line X-X' shown in

[0043] Figure 23 Is a schematic diagram showing the execution of exposure to bond Figure 21 The first light-emitting element shown in

[0044] Figure 24 And Figure 25 Is a schematic plan view of a first sub-pixel and a repair region of a display device according to an embodiment of the present disclosure.

[0045] Figure 26 Is a schematic plan view of a first sub-pixel and an overlapping region of a display device according to an embodiment of the present disclosure.

[0046] Figure 27 Is a schematic plan view showing an example in which the first to third light-emitting elements are provided in the pixel shown in Figure 6

[0047] Figure 28 Is a schematic block diagram showing an embodiment of a display system.

[0048] Figures 29 to 32 Is a schematic perspective view showing an application example of the display system shown in Figure 28 Detailed implementation

[0049] ​​In the following, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the following description, only parts that contribute to understanding the operation according to the present disclosure will be described, and descriptions of other parts may be omitted so as not to unnecessarily obscure the subject matter of the present disclosure. In addition, the present disclosure is not limited to the embodiments described herein, but can be implemented in various different forms. On the contrary, the embodiments described herein are provided to thoroughly and completely describe the disclosed content and will fully convey the idea of the present disclosure to those of ordinary skill in the art.

[0050] As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms as well.

[0051] In the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or" for purposes of its meaning and interpretation. For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a combined or separate sense and can be understood to be equivalent to "and / or".

[0052] The term "overlap" or "overlapping" means that a first object can be above or below a second object, or on one side of the second object, and vice versa. Additionally, the term "overlap" can include layer, stack, face or face toward, extend over, cover or partially cover, or any other suitable term as would be understood and appreciated by those of ordinary skill in the art.

[0053] When an element is referred to as "connected" or "coupled" to another element, it can be directly connected or directly coupled to the other element, or indirectly connected or indirectly coupled to the other element, and one or more intermediate elements are interposed therebetween. The technical terms used herein are for the purpose of illustrating particular embodiments only and are not intended to limit the present embodiments. It will be understood that when a component "includes", "has", or "contains" an element, it should be understood that the component does not exclude another element, but may also include another element. It will be understood that for the purposes of the present disclosure, "at least one of X, Y, and Z" can be understood to mean only X, only Y, only Z, or any combination of two or more of the items X, Y, and Z (e.g., XYZ, XY, YZ, XZ). Similarly, for the purposes of the present disclosure, "at least one selected from the group consisting of X, Y, and Z" can be understood to mean only X, only Y, only Z, or any combination of two or more of the items X, Y, and Z (e.g., XYZ, XY, YZ, XZ).

[0054] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the "first" element discussed below could also be termed "second" without departing from the teachings of the present disclosure.

[0055] For ease of description, spatial relative terms such as "below", "above", etc. may be used herein to facilitate the description of the relationship between one element and another as shown in the drawings. It will be understood that, in addition to the orientations described herein and depicted in the drawings, the spatial relative terms and the configurations shown are also intended to encompass different orientations of the device during use or operation. For example, if the device in the drawings is flipped, an element described as "below" or "beneath" other elements or features will then be oriented "above" the other elements or features. Thus, the term "above" can include both the orientation above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or in other directions), and the spatial relative descriptors used herein should be interpreted accordingly.

[0056] Furthermore, embodiments of the present disclosure are described herein with reference to schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes as illustrated, for example due to manufacturing techniques and / or tolerances, can be expected. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing techniques. The regions shown in the drawings are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.

[0057] It will be understood that the terms "connected to" or "coupled to" can include physical connection or coupling or electrical connection or coupling.

[0058] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a common dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0059] Figure 1 is a schematic block diagram showing an embodiment of a display device.

[0060] Referring to Figure 1 , the display device DD may include a display panel DP, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0061] The display panel DP may include sub-pixels SP. The sub-pixels SP may be connected to the gate driver 120 through the first gate line GL1 to the m-th gate line GLm. The sub-pixels SP may be connected to the data driver 130 through the first data line DL1 to the n-th data line DLn. Here, m and n are natural numbers greater than 1.

[0062] The sub-pixels SP may emit light of two or more colors. For example, each of the sub-pixels SP may emit light such as red, green, blue, cyan, magenta, yellow, white, etc.

[0063] Two or more of the sub-pixels SP may constitute a pixel PXL. For example, as Figure 1 shown, the pixel PXL may include three sub-pixels SP. Thus, the pixel PXL may emit various colors of light with various brightness levels according to the combination of light emitted from the sub-pixels SP included therein.

[0064] The gate driver 120 may be connected to the sub-pixels SP arranged in the row direction through the first gate line GL1 to the m-th gate line GLm. The gate driver 120 may output a gate signal to the first gate line GL1 to the m-th gate line GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal, etc.

[0065] The gate driver 120 may be disposed at one side of the display panel DP. However, the embodiment is not limited thereto. For example, the gate driver 120 may be divided into two or more drivers physically and / or logically divided, and these drivers may be disposed at one side of the display panel DP and the other side of the display panel DP that may be opposite to the first side. Thus, in some embodiments, the gate driver 120 may be disposed at the periphery of the display panel DP in various forms.

[0066] The data driver 130 may be connected to the sub-pixels SP arranged in the column direction through the first data line DL1 to the n-th data line DLn. The data driver 130 may receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse signal, a source shift clock signal, a source output enable signal, etc.

[0067] The data driver 130 may receive a voltage from the voltage generator 140. The data driver 130 may apply a data signal having a gray-scale voltage corresponding to the image data DATA to the first data line DL1 to the n-th data line DLn by using the received voltage. In a case where a gate signal is applied to each of the first gate line GL1 to the m-th gate line GLm, the data signal corresponding to the image data DATA may be applied to the first data line DL1 to the n-th data line DLn. Accordingly, the corresponding sub-pixel SP may generate light corresponding to the data signal. Accordingly, an image may be displayed on the display panel DP.

[0068] In an embodiment, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0069] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 may be configured to generate a voltage and provide the generated voltage to components of the display device DD. The voltage generator 140 may generate a voltage by receiving an input voltage from outside the display device DD and adjusting the received voltage.

[0070] The voltage generator 140 may generate a first power voltage and a second power voltage. The generated first power voltage and second power voltage may be provided to the sub-pixel SP through a power line PL. In other embodiments, at least one of the first power voltage and the second power voltage may be provided from outside the display device DD.

[0071] The voltage generator 140 may provide various voltages and / or signals. For example, the voltage generator 140 may provide one or more initialization voltages applied to the sub-pixel SP. For example, in a sensing operation for sensing electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a predetermined or selected reference voltage may be applied to the first data line DL1 to the n-th data line DLn, and the voltage generator 140 may generate a reference voltage and transmit the reference voltage to the data driver 130. For example, in a display operation for displaying an image on the display panel DP, a common pixel control signal may be applied to the sub-pixel SP, and the voltage generator 140 may generate a pixel control signal. In an embodiment, the voltage generator 140 may provide the pixel control signal to the sub-pixel SP through a pixel control line PXCL. In Figure 1 it, the pixel control line PXCL is shown connected between the voltage generator 140 and the display panel DP. However, the embodiment is not limited thereto. For example, the pixel control line PXCL may be connected between the gate driver 120 and the display panel DP. The pixel control signal may be transmitted from the gate driver 120 to the sub-pixel SP through the pixel control line PXCL.

[0072] The controller 150 may control the overall operation of the display device DD. The controller 150 may receive input image data IMG and a control signal CTRL corresponding to the input image data IMG from the outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0073] The controller 150 may convert the input image data IMG to be suitable for use in the display device DD or the display panel DP, and thus output image data DATA. In an embodiment, the controller 150 may align the input image data IMG to be suitable for sub-pixels SP in units of rows, and thus output image data DATA.

[0074] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be mounted on one integrated circuit. As Figure 1 shown, the data driver 130, the voltage generator 140, and the controller 150 may be included in the driver integrated circuit DIC. The data driver 130, the voltage generator 140, and the controller 150 may be components functionally divided in one driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a component separated from the driver integrated circuit DIC.

[0075] Figure 2 is a schematic block diagram showing an embodiment of any one of the sub-pixels shown in Figure 1 . In Figure 2 , a sub-pixel SPij arranged on the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels SP shown in Figure 1 is shown.

[0076] Referring to Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD.

[0077] The light-emitting element LD may be connected between a first power voltage node VDDN and a second power voltage node VSSN. The first power voltage node VDDN may be connected to Figure 1 one of the power lines PL shown in Figure 1 to receive a first power voltage. The second power voltage node VSSN may be connected to the other of the power lines PL to receive a second power voltage. The first power voltage may have a voltage level higher than the voltage level of the second power voltage.

[0078] The light-emitting element LD can be connected between the anode electrode AE and the cathode electrode CE. The anode electrode AE can be connected to the first power voltage node VDDN through the sub-pixel circuit SPC. For example, the anode electrode AE can be connected to the first power voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC. The cathode electrode CE can be connected to the second power voltage node VSSN. The light-emitting element LD can be configured to emit light according to the current flowing from the anode electrode AE to the cathode electrode CE.

[0079] The sub-pixel circuit SPC can be connected to Figure 1 the i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm shown in Figure 1 and the j-th data line DLj among the first data line DL1 to the n-th data line DLn shown in Figure 1 . In response to the gate signal received through the i-th gate line GLi, the sub-pixel circuit SPC can control the light-emitting element LD to emit light according to the data signal received through the j-th data line DLj. In an embodiment, the sub-pixel circuit SPC can also be connected to

[0080] the pixel control line PXCL shown in

[0081] . The sub-pixel circuit SPC can also control the light-emitting element LD in response to the control signal received through the pixel control line PXCL.

[0082] Figure 3 is a schematic plan view showing Figure 1 an embodiment of the display panel shown in

[0083] Referring to Figure 3 , the display panel DP can include a display area DA and a non-display area NDA. The display panel DP can display an image through the display area DA. The non-display area NDA can be provided at the periphery of the display area DA.

[0084] The display panel DP may include sub-pixels SP in the display area DA. The sub-pixels SP may be arranged in a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the sub-pixels SP may be arranged in a matrix form along the first direction DR1 and the second direction DR2. In another example, the sub-pixels SP may be arranged in a zigzag form along the first direction DR1 and the second direction DR2. In some embodiments, the arrangement of the sub-pixels SP may vary. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0085] Two or more of the sub-pixels SP may constitute a pixel PXL. In Figure 3 it, a pixel PXL is shown to include three sub-pixels SP1, SP2, and SP3. However, the embodiments are not limited thereto. For example, a pixel PXL may include two sub-pixels SP. Hereinafter, for ease of description, it is assumed that the pixel PXL includes a first sub-pixel SP1 to a third sub-pixel SP3.

[0086] Each of the first sub-pixel SP1 to the third sub-pixel SP3 may emit light of one of various colors such as red, green, blue, cyan, magenta, and yellow. Hereinafter, for clear and simple description, it is assumed that the first sub-pixel SP1 is configured to emit red light, the second sub-pixel SP2 is configured to emit green light, and the third sub-pixel SP3 is configured to emit blue light.

[0087] Each of the first sub-pixel SP1 to the third sub-pixel SP3 may include at least one light-emitting element configured to emit light. In an embodiment, the light-emitting elements of the first sub-pixel SP1 to the third sub-pixel SP3 may emit light of the same color. For example, the light-emitting elements of the first sub-pixel SP1 to the third sub-pixel SP3 may emit blue light. In other embodiments, the light-emitting elements of the first sub-pixel SP1 to the third sub-pixel SP3 may emit light of different colors. For example, the light-emitting elements of the first sub-pixel SP1 to the third sub-pixel SP3 may emit red, green, and blue light, respectively.

[0088] Self-emitting display panels such as a light-emitting diode display panel (LED display panel) using a light-emitting diode of a micron or nanometer level as a light-emitting element and an organic light-emitting display panel (OLED panel) using an organic light-emitting diode as a light-emitting element may be used as the display panel DP.

[0089] Components for controlling the sub-pixels SP may be provided in the non-display area NDA. Wires connected to the sub-pixels SP, such as Figure 1The first gate line GL1 to the m-th gate line GLm, the first data line DL1 to the n-th data line DLn, the power line PL, and the pixel control line PXCL shown in [Figure] can be disposed in the non-display area NDA.

[0090] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, and the controller 150 shown in [Figure] can be disposed in the non-display area NDA of the display panel DP. In an embodiment, the gate driver 120 can be disposed in the non-display area NDA. The data driver 130, the voltage generator 140, and the controller 150 can be implemented as Figure 1 a driver integrated circuit DIC separated from the display panel DP shown in [Figure], and the driver integrated circuit DIC can be connected to the lines disposed in the non-display area NDA. In other embodiments, the gate driver 120, the data driver 130, the voltage generator 140, and the controller 150 can be implemented as an integrated circuit separated from the display panel DP.

[0091] In an embodiment, the display area DA can have various shapes. The display area DA can have a closed-loop shape including linear edges and / or curved edges. For example, the display area DA can have shapes such as a polygon, a circle, a semi-circle, and an ellipse.

[0092] In an embodiment, the display panel DP can have a flat display surface. In other embodiments, the display panel DP can at least partially have a rounded display surface. In an embodiment, the display panel DP can be bendable, foldable, or rollable. The display panel DP and / or the substrate of the display panel DP can include a flexible material.

[0093] Figure 4 is a schematic cross-sectional view showing Figure 3 an embodiment of the display panel shown in [Figure].

[0094] Referring to Figure 4 , the display panel DP can include a substrate SUB and a pixel circuit layer PCL, a display panel layer DPL, and a light conversion layer LCL that are sequentially stacked on the substrate SUB in a third direction DR3 intersecting the first direction DR1 and the second direction DR2.

[0095] The substrate SUB can be made of an insulating material such as glass or resin. For example, the substrate SUB can include a glass substrate. In another example, the substrate SUB can include a polyimide (PI) substrate. In still another example, the substrate SUB can include a silicon wafer substrate formed using a semiconductor process.

[0096] In an embodiment, the substrate SUB can be made of a flexible material so as to be bendable or foldable, and have a single-layer structure or a multi-layer structure. For example, the flexible material can include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the embodiment is not limited thereto.

[0097] The pixel circuit layer PCL can be disposed on the substrate SUB. The pixel circuit layer PCL can include an insulating layer, and semiconductor patterns and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer PCL can be used as circuit elements, wires, etc.

[0098] The circuit elements of the pixel circuit layer PCL can include Figure 3 the sub-pixel circuits SPC of each of the sub-pixels SP shown in (see Figure 2 ). In other words, the circuit elements of the pixel circuit layer PCL can be provided as transistors and one or more capacitors of the sub-pixel circuit SPC.

[0099] The wires of the pixel circuit layer PCL can include wires connected to each of the sub-pixels SP. The wires of the pixel circuit layer PCL can include various signal lines and / or various voltage lines for driving the display panel layer DPL.

[0100] The display panel layer DPL can be disposed on the pixel circuit layer PCL. The display panel layer DPL can include light-emitting elements of the sub-pixels SP.

[0101] The light conversion layer LCL can be disposed on the display panel layer DPL. The light conversion layer LCL can include a light conversion pattern having color conversion particles and / or light scattering particles. For example, the color conversion particles can include quantum dots. The quantum dots can change the wavelength (or color) of the light emitted from the display panel layer DPL. In an embodiment, the light conversion pattern can be omitted.

[0102] The light conversion layer LCL can further include a color filter layer including color filters. The color filters can allow light having a specific wavelength (or specific color) to selectively transmit therethrough. In an embodiment, the color filter layer can be omitted.

[0103] A window for protecting the exposed surface (or top surface) of the display panel DP can be provided on the light conversion layer LCL. The window can protect the display panel DP from external impacts. The window can be joined to the light conversion layer LCL through an optically transparent adhesive (or adhesion) member. The window can have a multi-layer structure selected from a glass substrate, a plastic film, and a plastic substrate. Such a multi-layer structure can be formed by a continuous process or an adhesive process using an adhesive layer. All or part of the window can be flexible.

[0104] Figure 5 is a schematic cross-sectional view showing Figure 3 another embodiment of the display panel shown in

[0105] Referring to Figure 5 , the display panel DP’ can include a substrate SUB, a pixel circuit layer PCL, a display panel layer DPL, an input sensing layer ISL, and a light conversion layer LCL. The substrate SUB, the pixel circuit layer PCL, the display panel layer DPL, and the light conversion layer LCL can be configured to be the same as the substrate SUB, the pixel circuit layer PCL, the display panel layer DPL, and the light conversion layer LCL described in reference Figure 4 respectively. Redundant descriptions will be omitted hereinafter.

[0106] The input sensing layer ISL can sense user input regarding the top surface (or display surface) of the display panel DP’. The input sensing layer ISL can include components suitable for sensing an external object such as a user's hand or pen. For example, the input sensing layer ISL can include touch electrodes.

[0107] Figure 6 is a schematic plan view showing Figure 3 an embodiment of any one of the pixels shown in

[0108] Referring to Figure 6 , the pixel PXL can include a first sub-pixel SP1 to a third sub-pixel SP3. The first sub-pixel SP1 to the third sub-pixel SP3 can be arranged in a first direction DR1. However, the arrangement of the pixel PXL is not limited thereto, and various changes can be made in some embodiments. For example, the first sub-pixel SP1 to the third sub-pixel SP3 can be arranged in a zigzag form.

[0109] The first anode electrode AE1 to the third anode electrode AE3 can be respectively provided in the first sub-pixel SP1 to the third sub-pixel SP3. The first anode electrode AE1 can be set to be connected to the anode electrode AE (see Figure 2 ) of the sub-pixel circuit SPC (see Figure 2)。The second anode electrode AE2 can be set to be connected to the anode electrode AE of the sub-pixel circuit SPC of the second sub-pixel SP2. The third anode electrode AE3 can be set to be connected to the anode electrode AE of the sub-pixel circuit SPC of the third sub-pixel SP3.

[0110] The cathode electrode CE can be spaced apart from the first anode electrode AE1 to the third anode electrode AE3. The cathode electrode CE can be set at the same height as the first anode electrode AE1 to the third anode electrode AE3. The cathode electrode CE can be spaced apart from the first anode electrode AE1 to the third anode electrode AE3 in the second direction DR2. In an embodiment, the cathode electrode CE can extend in the first direction DR1 to serve as a common electrode for the pixel PXL and other pixels adjacent to the pixel PXL. Although not shown in the drawings, in addition to the first direction DR1, the cathode electrode CE can also extend in the second direction DR2 to serve as Figure 3 a common electrode for all the sub-pixels SP shown in. Thus, the cathode electrode CE can have various shapes.

[0111] The first light-emitting element LD1 to the third light-emitting element LD3 can be disposed on the first anode electrode AE1 to the third anode electrode AE3 and the cathode electrode CE. The first light-emitting element LD1 can be electrically connected to the first anode electrode AE1 and the cathode electrode CE. The first light-emitting element LD1 can be set to be connected to the light-emitting element LD of the sub-pixel circuit SPC of the first sub-pixel SP1 (see Figure 2 ). The second light-emitting element LD2 can be electrically connected to the second anode electrode AE2 and the cathode electrode CE. The second light-emitting element LD2 can be set to be connected to the light-emitting element LD of the sub-pixel circuit SPC of the second sub-pixel SP2. The third light-emitting element LD3 can be electrically connected to the third anode electrode AE3 and the cathode electrode CE. The third light-emitting element LD3 can be set to be connected to the light-emitting element LD of the sub-pixel circuit SPC of the third sub-pixel SP3.

[0112] The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be inorganic light-emitting diodes including inorganic light-emitting materials. However, the embodiment is not limited thereto. For example, organic light-emitting diodes can be used.

[0113] Figure 7 is a schematic cross-sectional view taken along the line I-I’ shown in Figure 6 .

[0114] Refer to Figure 6 and Figure 7 , the pixel circuit layer PCL, the display panel layer DPL, and the light conversion layer LCL can be sequentially disposed on the substrate SUB.

[0115] The pixel circuit layer PCL may include an insulating layer, a semiconductor pattern, and a conductive pattern stacked on a substrate SUB. The insulating layer may include a buffer layer BFL, one or more interlayer insulating layers ILD, and one or more passivation layers PSV1 and PSV2. The semiconductor pattern and the conductive pattern may be located between the insulating layers. The conductive pattern may include at least one material among copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0116] As referred to in Figure 2 each of the first sub-pixel SP1 to the third sub-pixel SP3, the sub-pixel circuit SPC (see Figure 2 ) may include a transistor and one or more capacitors. The semiconductor pattern and the conductive pattern of the pixel circuit layer PCL may be used as the transistor and the capacitor of the sub-pixel circuit SPC. The conductive pattern of the pixel circuit layer PCL may also be used as Figure 1 the lines shown in

[0117] such as the first gate line GL1 to the m-th gate line GLm, the first data line DL1 to the n-th data line DLn, the power line PL, and the pixel control line PXCL.

[0117] The buffer layer BFL may be disposed on the surface of the substrate SUB. The buffer layer BFL may prevent impurities from diffusing into the circuit elements and lines included in the pixel circuit layer PCL. The buffer layer BFL may include an inorganic insulating layer containing an inorganic material. In an embodiment, the buffer layer BFL may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and at least one of metal oxides such as aluminum oxide (AlO x ). The buffer layer BFL may be provided as a single layer or multiple layers. In the case where the buffer layer BFL is provided as multiple layers, the layers of the multiple layers may be formed of the same material or different materials.

[0118] In an embodiment, one or more barrier layers may be disposed between the substrate SUB and the buffer layer BFL. Each of the barrier layers may include polyimide.

[0119] The transistor T_SP1 may be disposed on the buffer layer BFL. The transistor T_SP1 may be any one of the transistors of the sub-pixel circuit SPC included in the first sub-pixel SP1. For example, the transistor T_SP1 may be understood as the transistor among the transistors of the sub-pixel circuit SPC that is connected to the first anode electrode AE1.

[0120] The transistor T_SP1 may include a semiconductor pattern SCP, a gate electrode GE, a first terminal ET1, and a second terminal ET2. The first terminal ET1 may be either a source electrode or a drain electrode, and the second terminal ET2 may be the other of the source electrode and the drain electrode. For example, the first terminal ET1 may be the source electrode, and the second terminal ET2 may be the drain electrode.

[0121] The semiconductor pattern SCP may be disposed on the buffer layer BFL. The semiconductor pattern SCP may include a first contact region in contact with the first terminal ET1 and a second contact region in contact with the second terminal ET2. The region between the first contact region and the second contact region may be a channel region. The channel region may overlap with the gate electrode GE of the transistor T_SP1. The channel region may be a semiconductor pattern without doped impurities and may be an intrinsic semiconductor. Each of the first contact region and the second contact region may be a semiconductor pattern doped with impurities. For example, p-type impurities may be used as the impurities, but the embodiments are not limited thereto.

[0122] The semiconductor pattern SCP may include any one of various types of semiconductors, such as amorphous silicon semiconductors, single-crystalline silicon semiconductors, polycrystalline silicon semiconductors, low-temperature polycrystalline silicon semiconductors, and oxide semiconductors.

[0123] The interlayer insulating layer ILD stacked in sequence may be disposed throughout the semiconductor pattern SCP. The interlayer insulating layer ILD may be an inorganic insulating layer including an inorganic material. For example, each of the interlayer insulating layers ILD may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and at least one of metal oxides such as aluminum oxide (AlO x ). However, the interlayer insulating layer ILD is not limited thereto. For example, any one of the interlayer insulating layers ILD may include an organic insulating layer containing an organic material.

[0124] The interlayer insulating layer ILD may electrically isolate the conductive patterns and / or semiconductor patterns disposed between the interlayer insulating layers ILD. For example, the interlayer insulating layer ILD may include a gate insulating layer GI disposed on the semiconductor pattern SCP. The gate insulating layer GI may be disposed between the semiconductor pattern SCP and the gate electrode GE such that the gate electrode GE is spaced apart from the semiconductor pattern SCP. In an embodiment, the gate insulating layer GI may be completely disposed on the semiconductor pattern SCP and the buffer layer BFL to cover the semiconductor pattern SCP and the buffer layer BFL. As the number of required layers in the conductive patterns and / or semiconductor patterns increases, the number of the interlayer insulating layers ILD may increase.

[0125] The gate electrode GE can be disposed on the gate insulating layer GI. The gate electrode GE can overlap with the channel region of the semiconductor pattern SCP. The gate electrode GE can be provided as a single layer including at least one material among copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag). In an embodiment, the gate electrode GE can be provided as a multilayer including at least one material among molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag) as low-resistance materials.

[0126] The first terminal ET1 and the second terminal ET2 can be disposed on the interlayer insulating layer ILD. The first terminal ET1 and the second terminal ET2 can contact the semiconductor pattern SCP through contact holes penetrating the interlayer insulating layer ILD. The first terminal ET1 and the second terminal ET2 can contact the first contact region and the second contact region of the semiconductor pattern SCP, respectively. Each of the first terminal ET1 and the second terminal ET2 can include at least one material among copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0127] Although the first terminal ET1 and the second terminal ET2 are shown as separate electrodes electrically connected to the semiconductor pattern SCP, the embodiment is not limited thereto. In some embodiments, the first terminal ET1 can be a first contact region adjacent to one side of the channel region of the semiconductor pattern SCP, and the second terminal ET2 can be a second contact region adjacent to the other side of the channel region of the semiconductor pattern SCP. The first terminal ET1 can be electrically connected to the first light-emitting element LD1 through a connection device such as a bridging electrode disposed on at least one of the interlayer insulating layers ILD.

[0128] In an embodiment, the transistor T_SP1 can be configured as a low-temperature polysilicon transistor. However, the embodiment is not limited thereto. For example, the transistor T_SP1 can be configured as an oxide semiconductor transistor. In an embodiment, the sub-pixel circuit of the first sub-pixel SP1 can include different types of transistors. For example, the transistor T_SP1 can be configured as a low-temperature polysilicon transistor, and another transistor of the first sub-pixel SP1 can be configured as an oxide semiconductor transistor. The oxide semiconductor of the corresponding oxide semiconductor transistor can be disposed on any one of the interlayer insulating layers ILD, rather than on the insulating layer of the semiconductor pattern SCP on which the transistor T_SP1 is disposed.

[0129] In an embodiment, the case where the transistor T_SP1 is a transistor having a top-gate structure is described as an example. However, the embodiment is not limited thereto. For example, the transistor T_SP1 can be a transistor having a bottom-gate structure. The structure of the transistor T_SP1 can be variously changed.

[0130] At least a part of various lines of the display panel DP and / or the display device DD may also be disposed on the interlayer insulating layer ILD.

[0131] The first passivation layer PSV1 may be disposed over the transistor T_SP1. The passivation layer may be represented as a protective layer or a via layer. The first passivation layer PSV1 may protect components disposed thereunder and provide a flat top surface.

[0132] The connection pattern CP may be disposed on the first passivation layer PSV1. The connection pattern CP may be connected to the first terminal ET1 of the transistor T_SP1 while penetrating the first passivation layer PSV1. The connection pattern CP may include at least one material among copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0133] At least a part of various lines of the display panel DP and / or the display device DD may also be disposed on the first passivation layer PSV1.

[0134] The second passivation layer PSV2 may be disposed on the connection pattern CP and the first passivation layer PSV1. The second passivation layer PSV2 may protect components disposed thereunder and provide a flat top surface.

[0135] Each of the first passivation layer PSV1 and the second passivation layer PSV2 may include an inorganic insulating layer containing an inorganic material and / or an organic insulating layer containing an organic material. The inorganic insulating layer may include, for example, at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), and metal oxides such as aluminum oxide (AlO x ). The organic insulating layer may include, for example, at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0136] The first passivation layer PSV1 and the second passivation layer PSV2 may include the same material as any one of the interlayer insulating layers ILD, but the embodiments are not limited thereto. Each of the first passivation layer PSV1 and the second passivation layer PSV2 may be provided as a single layer, but may also be provided as multiple layers.

[0137] The display panel layer DPL may be disposed on the second passivation layer PSV2. The display panel layer DPL may include a first anode electrode AE1, a cathode electrode CE, a first bank BNK1, a first light-emitting element LD1, an insulating layer OCL, a third passivation layer PSV3, and a capping layer CPL.

[0138] The first anode electrode AE1 and the cathode electrode CE may be disposed on the pixel circuit layer PCL.

[0139] The first anode electrode AE1 may be electrically connected to the connection pattern CP through a contact hole penetrating the second passivation layer PSV2. Thus, the first anode electrode AE1 may be electrically connected to the transistor T_SP1.

[0140] The cathode electrode CE may be spaced apart from the first anode electrode AE1 in the second direction DR2. The cathode electrode CE may be electrically connected to Figure 2 the second power voltage node VSSN shown in. Accordingly, the second power voltage applied to the second power voltage node VSSN may be transferred to the cathode electrode CE.

[0141] The first bank BNK1 may be disposed on the first anode electrode AE1 and the cathode electrode CE. The first bank BNK1 may have a first opening OP1 exposing portions of the first anode electrode AE1 and the cathode electrode CE. The first light-emitting element LD1 may be disposed in the first opening OP1 of the first bank BNK1. Thus, the first bank BNK1 may be provided as a pixel defining layer defining a region in which the first light-emitting element LD1 is located.

[0142] The first bank BNK1 may be configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In an embodiment, the first bank BNK1 may include an organic material. For example, the first bank BNK1 may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0143] The first light-emitting element LD1 may be electrically connected to the first anode electrode AE1. The first light-emitting element LD1 may be electrically connected to the cathode electrode CE. The first light-emitting element LD1 may be bonded to the first anode electrode AE1 and the cathode electrode CE.

[0144] The first light-emitting element LD1 may include a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, and an auxiliary layer 15. The first light-emitting element LD1 may include a light-emitting stack structure in which the auxiliary layer 15, the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked thereon.

[0145] The first light-emitting element LD1 may include a first bonding electrode BDE1 and a second bonding electrode BDE2 facing the same direction (e.g., the opposite direction of the third direction DR3). The first bonding electrode BDE1 may be connected to the second semiconductor layer 13. The second bonding electrode BDE2 may be connected to the first semiconductor layer 11 that is exposed as the second semiconductor layer 13 and the active layer 12 are exposed. The first light-emitting element LD1 may be a flip-chip type light-emitting element.

[0146] The first semiconductor layer 11 may be configured to supply electrons to the active layer 12. The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and is an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the first semiconductor layer 11 is not limited thereto. Various materials may constitute the first semiconductor layer 11. In an embodiment of the present disclosure, the first semiconductor layer 11 may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant). In some embodiments, the first semiconductor layer 11 may form an n-type semiconductor layer together with the auxiliary layer 15.

[0147] The active layer 12 may be disposed on the first semiconductor layer 11 and may be a region where electrons and holes are recombined. When electrons and holes are recombined in the active layer 12, light having an energy level changed to a lower energy level and having a wavelength corresponding to the lower energy level may be generated. The active layer 12 may be formed into a single quantum well structure or a multi-quantum well structure. In the case where the active layer 12 is formed into a multi-quantum well structure, units including a barrier layer, a strain enhancing layer, and a well layer may be repeatedly stacked with each other to form the active layer 12. However, the embodiment of the active layer 12 is not limited thereto.

[0148] The second semiconductor layer 13 may be disposed on the active layer 12 and may supply holes to the active layer 12. The second semiconductor layer 13 may include a semiconductor layer having a type different from that of the first semiconductor layer 11. In an example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and is a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), or barium (Ba). However, the material constituting the second semiconductor layer 13 is not limited thereto. Various materials may constitute the second semiconductor layer 13. In an embodiment of the present disclosure, the second semiconductor layer 13 may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant).

[0149] The auxiliary layer 15 may include an undoped gallium nitride (GaN) semiconductor material. The auxiliary layer 15 may form an n-type semiconductor layer together with the first semiconductor layer 11.

[0150] The first bonding electrode BDE1 may be electrically connected to the second semiconductor layer 13. The second bonding electrode BDE2 may be electrically connected to the first semiconductor layer 11. The first bonding electrode BDE1 and the second bonding electrode BDE2 may include a eutectic metal.

[0151] The first light-emitting element LD1 may further include an insulating film 16 covering the outer circumferential surface of the light-emitting stack structure. The insulating film 16 may prevent an electrical short circuit that may occur when the active layer 12 comes into contact with another conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. The insulating film 16 may include a transparent insulating material. The insulating film 16 may be configured to expose the bottom surfaces of the first bonding electrode BDE1 and the second bonding electrode BDE2.

[0152] The bottom surface of the first bonding electrode BDE1 may be in contact with the first anode electrode AE1. Accordingly, the first bonding electrode BDE1 may be electrically connected to the first anode electrode AE1. The bottom surface of the second bonding electrode BDE2 may be in contact with the cathode electrode CE. Accordingly, the second bonding electrode BDE2 may be electrically connected to the cathode electrode CE.

[0153] The insulating layer OCL can be disposed in the first opening OP1 in which the first light-emitting element LD1 is disposed. The insulating layer OCL can fix the first light-emitting element LD1 so as not to move. In addition, the insulating layer OCL can protect the components disposed thereunder from foreign substances such as dust or moisture. In addition, the insulating layer OCL can prevent a short circuit between the cathode electrode CE and the first anode electrode AE1. For example, the insulating layer OCL can include at least one of an inorganic insulating layer and an organic insulating layer.

[0154] In an embodiment, the insulating layer OCL can include a photosensitive organic insulating material. For example, the insulating layer OCL can include at least one of photosensitive polyimide (PSPI) and photoacryl. However, the embodiment is not limited thereto.

[0155] The third passivation layer PSV3 can be disposed over the first bank BNK1 and the insulating layer OCL. The third passivation layer PSV3 can protect the components disposed thereunder and provide a flat surface. The third passivation layer PSV3 can include the same material as any one of the first passivation layer PSV1 and the second passivation layer PSV2, but the embodiment is not limited thereto.

[0156] In an embodiment, the third passivation layer PSV3 may not be disposed on the top surface LTS of the first light-emitting element LD1. The first light-emitting element LD1 can protrude into the light conversion layer LCL. The first light-emitting element LD1 can be at least partially located in the second opening OP2 of the second bank BNK2. For example, the height of the top surface LTS of the first light-emitting element LD1 from the substrate SUB can be higher than the height of the lowermost end RBE of the reflective layer RFL from the substrate SUB. Therefore, the light emitted from the first light-emitting element LD1 can be provided to the light conversion layer LCL at a relatively high ratio.

[0157] The capping layer CPL can be disposed on the third passivation layer PSV3. The capping layer CPL can protect components such as the first light-emitting element LD1 disposed thereunder from external moisture, humidity, etc. In an embodiment, the capping layer CPL may not be disposed on the top surface LTS of the first light-emitting element LD1. In other embodiments, the capping layer CPL can completely cover the first light-emitting element LD1 and the third passivation layer PSV3. The capping layer CPL can include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and at least one of metal oxides such as aluminum oxide (AlO x ). However, the material of the capping layer CPL is not limited thereto.

[0158] In the foregoing, the pixel circuit layer PCL and the display panel layer DPL of the first sub-pixel SP1 have been described. Figure 6 Each of the second sub-pixel SP2 and the third sub-pixel SP3 shown in Figure 6 may also be configured to be the same as the first sub-pixel SP1 within the scope not differently described herein.

[0159] The light conversion layer LCL may be disposed on the capping layer CPL. The light conversion layer LCL may include a second bank BNK2, a reflective layer RFL, a fourth passivation layer PSV4, a first light conversion pattern CCP1, a low refractive index layer LRL, and a color filter layer CFL.

[0160] The second bank BNK2 may be disposed on the capping layer CPL. The second bank BNK2 may overlap with the first bank BNK1. The second bank BNK2 may have a second opening OP2 overlapping with the first opening OP1.

[0161] The second bank BNK2 may be configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In an embodiment, the second bank BNK2 may include an organic material. For example, the second bank BNK2 may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0162] The reflective layer RFL may be disposed on a side surface of the second bank BNK2 adjacent to the second opening OP2. The reflective layer RFL may be configured to reflect incident light and thus may improve light emission efficiency. The reflective layer RFL may include a material suitable for reflecting light. The reflective layer RFL may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiment is not limited thereto.

[0163] On the capping layer CPL, the fourth passivation layer PSV4 may be disposed in the second opening OP2. The fourth passivation layer PSV4 may protect the components disposed thereunder and provide a flat surface. The fourth passivation layer PSV4 may include the same material as any one of the first passivation layer PSV1 to the third passivation layer PSV3, but the embodiment is not limited thereto.

[0164] On the fourth passivation layer PSV4, the first light conversion pattern CCP1 may be disposed in the second opening OP2.

[0165] The first light conversion pattern CCP1 may include color conversion particles and / or light scattering particles. The color conversion particles may convert incident light into light of another color by changing the wavelength of the incident light. In addition, the color conversion particles may scatter the incident light. In an embodiment, the color conversion particles may be quantum dots. The light scattering particles may scatter the incident light.

[0166] The first sub-pixel SP1 may be a red sub-pixel. When the first light-emitting element LD1 emits blue light, the first light conversion pattern CCP1 may include first color conversion particles QD1 configured to convert blue light into red light. When the first light-emitting element LD1 emits red light, the first light conversion pattern CCP1 may include light scattering particles. Thus, the particles included in the first light conversion pattern CCP1 may vary in various ways according to the first light-emitting element LD1.

[0167] The low refractive index layer LRL may be disposed on the second bank BNK2, the reflective layer RFL, and the first light conversion pattern CCP1. The low refractive index layer LRL may have a refractive index lower than that of each of the first light conversion pattern CCP1 and the first color filter CF1. The low refractive index layer LRL may be configured to refract or totally reflect light according to the incident angle of the corresponding light. For example, the low refractive index layer LRL may re-provide the light passing through the first light conversion pattern CCP1 to the first light conversion pattern CCP1. Therefore, the light conversion efficiency of the first light conversion pattern CCP1 can be improved.

[0168] The color filter layer CFL may be disposed on the low refractive index layer LRL. The color filter layer CFL may include the first color filter CF1 and a light blocking pattern LBP. The first color filter CF1 may overlap with the first light conversion pattern CCP1. The first color filter CF1 may selectively transmit light within a desired wavelength range. When the first sub-pixel SP1 is a red sub-pixel, the first color filter CF1 may include a red color filter. The light blocking pattern LBP may include at least one of various types of light blocking materials.

[0169] Figure 8 is a schematic cross-sectional view taken along Figure 6 the line II-II' shown in

[0170] Refer to Figure 6 and Figure 8 , the pixel circuit layer PCL, the display panel layer DPL, and the light conversion layer LCL may be disposed on the substrate SUB.

[0171] The pixel circuit layer PCL and the display panel layer DPL may be the same as those in the reference Figure 7The same as described. In the pixel circuit layer PCL, sub-pixel circuits corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 can be provided. In the display panel layer DPL, the first light-emitting element LD1 to the third light-emitting element LD3 corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 can be provided. The first light-emitting element LD1 to the third light-emitting element LD3 can overlap with the first opening OP1 of the first bank BNK1. The first light-emitting element LD1 can be connected between the transistor T_SP1 (see Figure 7 ) included in the sub-pixel circuit of the first sub-pixel SP1 and the cathode electrode CE (see Figure 7 ). The second light-emitting element LD2 can be connected between the transistor included in the sub-pixel circuit of the second sub-pixel SP2 and the cathode electrode CE. The third light-emitting element LD3 can be connected between the transistor included in the sub-pixel circuit of the third sub-pixel SP3 and the cathode electrode CE. Hereinafter, redundant descriptions will be omitted.

[0172] The light conversion layer LCL can be provided on the display panel layer DPL. The light conversion layer LCL can be the same as described with reference to Figure 7 . Hereinafter, redundant descriptions will be omitted.

[0173] The second bank BNK2 can include a second opening OP2. It can be understood that the emission regions EMA and the non-emission regions NEMA of the first sub-pixel SP1 to the third sub-pixel SP3 can be defined by the second bank BNK2. The region overlapping with the second bank BNK2 can correspond to the non-emission region NEMA. The region overlapping with the second opening OP2 of the second bank BNK2 can correspond to the emission regions EMA of the first sub-pixel SP1 to the third sub-pixel SP3.

[0174] On the capping layer CPL, the fourth passivation layer PSV4 can be provided in the second opening OP2. On the fourth passivation layer PSV4, the first light conversion pattern CCP1 to the third light conversion pattern CCP3 can be provided in the second opening OP2.

[0175] In an embodiment, the first light-emitting element LD1 to the third light-emitting element LD3 may be configured to emit blue light. The first light conversion pattern CCP1 may include first color conversion particles QD1 configured to convert blue light into red light. The second light conversion pattern CCP2 may include second color conversion particles QD2 configured to convert blue light into green light. The third light conversion pattern CCP3 may include light scattering particles SCT configured to scatter blue light to improve light emission efficiency. Accordingly, the first sub-pixel SP1 to the third sub-pixel SP3 may be set as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. In an embodiment, at least one of the first light conversion pattern CCP1 to the third light conversion pattern CCP3 may further include color conversion particles configured to convert blue light into white light.

[0176] In an embodiment, the first light-emitting element LD1 to the third light-emitting element LD3 may be configured to emit red, green, and blue light, respectively. Each of the first light conversion pattern CCP1 to the third light conversion pattern CCP3 may include light scattering particles SCT. Thus, the particles included in the first light conversion pattern CCP1 to the third light conversion pattern CCP3 may be variously changed according to the first light-emitting element LD1 to the third light-emitting element LD3.

[0177] In an embodiment, the first light conversion pattern CCP1 to the third light conversion pattern CCP3 may be omitted.

[0178] The low refractive index layer LRL may be disposed on the second bank BNK2, the reflective layer RFL, and the first light conversion pattern CCP1 to the third light conversion pattern CCP3. The low refractive index layer LRL may have a refractive index lower than that of each of the first light conversion pattern CCP1 to the third light conversion pattern CCP3 and the first color filter CF1 to the third color filter CF3. In an embodiment, the low refractive index layer LRL may be omitted in a region corresponding to the third sub-pixel SP3.

[0179] The color filter layer CFL may be disposed on the low refractive index layer LRL. The color filter layer CFL may include the first color filter CF1 to the third color filter CF3 and a light blocking pattern LBP.

[0180] Each of the first color filter CF1 to the third color filter CF3 may allow light within a desired wavelength range to selectively transmit therethrough. In the case where the first sub-pixel SP1 is a red sub-pixel, the first color filter CF1 may include a red color filter. In the case where the second sub-pixel SP2 is a green sub-pixel, the second color filter CF2 may include a green color filter. In the case where the third sub-pixel SP3 is a blue sub-pixel, the third color filter CF3 may include a blue color filter.

[0181] The light-blocking pattern LBP may be disposed between the color filters CF1 to CF3. It can be understood that the emission regions (or light-emitting regions) EMA and the non-emission regions NEMA of the first sub-pixel SP1 to the third sub-pixel SP3 are defined by the light-blocking pattern LBP. The region corresponding to the light-blocking pattern LBP may correspond to the non-emission region NEMA. The region not overlapping with the light-blocking pattern LBP may correspond to the emission region EMA.

[0182] In an embodiment, the light-blocking pattern LBP may include at least one of various kinds of light-blocking materials. In an embodiment, each of the light-blocking patterns LBP may be arranged in a multi-layer form overlapping at least two of the first color filter CF1 to the third color filter CF3. For example, each of the light-blocking patterns LBP may be formed by overlapping the first color filter CF1 to the third color filter CF3 with each other. In another example, the light-blocking pattern LBP between the first color filter CF1 and the second color filter CF2 among the light-blocking patterns LBP may be formed in a multi-layer where the first color filter CF1 and the second color filter CF2 overlap, and the light-blocking pattern LBP between the second color filter CF2 and the third color filter CF3 among the light-blocking patterns LBP may be formed in a multi-layer where the second color filter CF2 and the third color filter CF3 overlap. The light-blocking pattern LBP between the first color filter CF1 and the third color filter CF3 of adjacent pixels may be formed in a multi-layer where the first color filter CF1 and the third color filter CF3 overlap. Thus, each of the first color filter CF1 to the third color filter CF3 may extend into the non-emission region NEMA to form the light-blocking pattern LBP.

[0183] Figure 9 A method of manufacturing a display device according to an embodiment of the present disclosure is schematically illustrated.

[0184] Reference Figure 9 , in the method of manufacturing a display device, a substrate (S100) may be provided, an electrode may be formed on the substrate (S200), an insulating layer may be formed on the electrode (S300), a light-emitting element may be aligned on the insulating layer (S400), the insulating layer may be exposed (S500), at least a part of the electrode may be exposed by developing the insulating layer (S600), and the light-emitting element may be bonded to at least a part of the electrode (S700).

[0185] Hereinafter, reference will be made to Figures 10 to 17 to describe this method in detail.

[0186] Figures 10 to 17 sequentially shows Figure 9 a schematic diagram of the method shown in

[0187] For ease of description,Figures 10 to 17 The first sub-pixel SP1 is shown, and Figure 6 each of the second sub-pixel SP2 and the third sub-pixel SP3 shown in may also be formed in the same manner as the first sub-pixel SP1 within the scope not differently described herein.

[0188] Referring to Figure 10 , a cathode electrode CE and a first anode electrode AE1 may be formed on the pixel circuit layer PCL. The cathode electrode CE and the first anode electrode AE1 may be formed simultaneously or sequentially. In the case of forming the cathode electrode CE and the first anode electrode AE1 simultaneously, the same mask may be used to pattern the cathode electrode CE and the first anode electrode AE1. In the case of forming the cathode electrode CE and the first anode electrode AE1 sequentially, different masks may be used to pattern the cathode electrode CE and the first anode electrode AE1.

[0189] Referring to Figure 11 and Figure 12 , a first bank BNK1 may be formed on the cathode electrode CE and the first anode electrode AE1. For example, after the first bank BNK1 is completely applied on the cathode electrode CE and the first anode electrode AE1, the first bank BNK1 may be etched to form a first opening OP1. An insulating layer OCL may be formed in the first opening OP1.

[0190] Referring to Figure 13 , a first light-emitting element LD1 may be aligned on the insulating layer OCL. That is, the first light-emitting element LD1 may be aligned in the first opening OP1 to overlap with the cathode electrode CE and the first anode electrode AE1. For example, the first light-emitting element LD1 may be aligned such that at least a part of the first bonding electrode BDE1 overlaps with the first anode electrode AE1. For example, the first light-emitting element LD1 may be aligned such that at least a part of the second bonding electrode BDE2 overlaps with the cathode electrode CE.

[0191] Alignment means that the first light-emitting element LD1 is positioned at a specific position (e.g., the insulating layer OCL) by an alignment device. For example, the alignment device may include an inserter. For example, the inserter may include polydimethylsiloxane (PDMS).

[0192] Referring to Figure 14 , the insulating layer OCL may be exposed by the light irradiated on the first light-emitting element LD1. For example, ultraviolet light may be irradiated toward the insulating layer OCL on the first light-emitting element LD1.

[0193] The light irradiated toward the insulating layer OCL may be blocked by the first bonding electrode BDE1 and the second bonding electrode BDE2. That is, the first bonding electrode BDE1 and the second bonding electrode BDE2 may be used as masks.

[0194] Reference Figure 15 ..., the insulating layer OCL can be developed. As a result of developing the insulating layer OCL, a first opening OCL_OP1 exposing the first anode electrode AE1 of the insulating layer OCL can be formed at a position corresponding to the position of the first bonding electrode BDE1, and a second opening OCL_OP2 exposing the cathode electrode CE of the insulating layer OCL can be formed at a position corresponding to the second bonding electrode BDE2.

[0195] Reference Figure 16 ..., the first bonding electrode BDE1 can be located in the first opening OCL_OP1 of the insulating layer OCL, and the second bonding electrode BDE2 can be located in the second opening OCL_OP2 of the insulating layer OCL. For example, pressure can be applied to the first light-emitting element LD1 in a direction opposite to the third direction DR3, and the first bonding electrode BDE1 and the second bonding electrode BDE2 can be located in the first opening OCL_OP1 and the second opening OCL_OP2 of the insulating layer OCL, respectively. An empty space may be required between the first bonding electrode BDE1 and the second bonding electrode BDE2 and the pixel circuit layer PCL, and in this empty space, the first bonding electrode BDE1 and the second bonding electrode BDE2 are filled by melting the first bonding electrode BDE1 and the second bonding electrode BDE2.

[0196] Reference Figure 17 ..., in the case where the first bonding electrode BDE1 and the second bonding electrode BDE2 are respectively located in the first opening OCL_OP1 and the second opening OCL_OP2 of the insulating layer OCL, heat can be applied to the first bonding electrode BDE1 and the second bonding electrode BDE2, and the first bonding electrode BDE1 and the second bonding electrode BDE2 can be melted. Therefore, the first bonding electrode BDE1 can be bonded to the first anode electrode AE1, and the second bonding electrode BDE2 can be bonded to the cathode electrode CE.

[0197] Figure 18 and Figure 19 are schematic diagrams showing the first light-emitting element aligned at a misaligned position.

[0198] Reference Figure 18 and Figure 19 ..., although the first light-emitting element LD1 is aligned at a slightly misaligned position, the first light-emitting element LD1 can also be electrically connected to the first anode electrode AE1 and the cathode electrode CE. That is, since the first opening OCL_OP1 and the second opening OCL_OP2 of the insulating layer OCL are formed using the first light-emitting element LD1 as a mask, even in the case where the alignment of the first light-emitting element LD1 is misaligned, the first light-emitting element LD1 can be appropriately bonded to the first anode electrode AE1 and the cathode electrode CE. Therefore, a wider process tolerance can be ensured.

[0199] Figure 20 is a schematic diagram showing the first light-emitting element of a bonding display device according to an embodiment of the present disclosure.

[0200] For ease of description, Figure 20 the first sub-pixel SP1 is shown, and Figure 6 each of the second sub-pixel SP2 and the third sub-pixel SP3 shown in may also be formed in the same manner as the first sub-pixel SP1 within the scope not otherwise described herein.

[0201] Except for the first reflective electrode RFE1 and the second reflective electrode RFE2, the display device according to an embodiment of the present disclosure may be configured to be substantially the same as Figure 1 the display device DD shown in. Thus, components that are the same as or similar to the components of the display device DD shown in Figure 1 are denoted by the same reference numerals, and redundant descriptions will be omitted.

[0202] Referring to Figure 20 , the first light-emitting element LD1 may include a first reflective electrode RFE1 disposed between the second semiconductor layer 13 and the first bonding electrode BDE1, and a second reflective electrode RFE2 disposed between the first semiconductor layer 11 and the second bonding electrode BDE2.

[0203] The first reflective electrode RFE1 and the second reflective electrode RFE2 may include a conductive material suitable for reflecting light. Thus, the light emission efficiency of the first light-emitting element LD1 can be improved. In an embodiment, the first reflective electrode RFE1 and the second reflective electrode RFE2 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiment is not limited thereto.

[0204] Figure 21 is a schematic plan view showing a pixel of a display device according to an embodiment of the present disclosure. Figure 22 is a schematic cross-sectional view taken along the line X-X' shown in Figure 21 .

[0205] Except for the first light-emitting element LD1', the second light-emitting element LD2', the third light-emitting element LD3', and their bonding, the pixel PXL' of the display device according to an embodiment of the present disclosure may be configured to be substantially the same as Figure 6 the pixel PXL of the display device shown in. Thus, the same as Figure 6Components of the display device shown in the figure that are the same or similar are denoted by the same reference numerals, and redundant descriptions will be omitted.

[0206] Reference Figure 21 , pixel PXL’ may include a first sub-pixel SP1’ to a third sub-pixel SP3’. The first sub-pixel SP1’ to the third sub-pixel SP3’ may be arranged in a first direction DR1. However, the arrangement of pixel PXL’ is not limited thereto, and various changes may be made in some embodiments. For example, the first sub-pixel SP1’ to the third sub-pixel SP3’ may be arranged in a zigzag form.

[0207] The first anode electrode AE1’ to the third anode electrode AE3’ may be respectively disposed in the first sub-pixel SP1’ to the third sub-pixel SP3’. The first anode electrode AE1’ may be set as the anode electrode connected to the sub-pixel circuit SPC of the first sub-pixel SP1’ (see Figure 2 ). The second anode electrode AE2’ may be set as the anode electrode connected to the sub-pixel circuit SPC of the second sub-pixel SP2’. The third anode electrode AE3’ may be set as the anode electrode connected to the sub-pixel circuit SPC of the third sub-pixel SP3’.

[0208] One or more first light-emitting elements LD1’, one or more second light-emitting elements LD2’, and one or more third light-emitting elements LD3’ may be disposed on the first anode electrode AE1’ to the third anode electrode AE3’. The first light-emitting element LD1’ may be connected to the first anode electrode AE1’. The second light-emitting element LD2’ may be connected to the second anode electrode AE2’. The third light-emitting element LD3’ may be connected to the third anode electrode AE3’. In the case where a plurality of light-emitting elements are provided in each sub-pixel, each anode electrode may have a shape extending in a specific direction such as a second direction DR2, and the light-emitting elements connected to the anode electrode may be arranged in the same direction.

[0209] The first light-emitting element LD1’ may be set as the light-emitting element LD shown in Figure 2 included in the first sub-pixel SP1’. The second light-emitting element LD2’ may be set as the light-emitting element LD shown in Figure 2 included in the second sub-pixel SP2’. The third light-emitting element LD3’ may be set as the light-emitting element LD shown in Figure 2 included in the third sub-pixel SP3’. In the case where a plurality of light-emitting elements are provided in one sub-pixel, the light-emitting elements may be connected in parallel between the anode electrode and the cathode electrode to be set as Figure 2 the light-emitting element LD shown in.

[0210] The first light-emitting element LD1', the second light-emitting element LD2', and the third light-emitting element LD3' may be inorganic light-emitting diodes including inorganic light-emitting materials. However, the embodiments are not limited thereto. For example, organic light-emitting diodes may be used.

[0211] Reference Figure 21 and Figure 22 , on the pixel circuit layer PCL, the first anode electrode AE1' to the third anode electrode AE3' may be respectively disposed in the first sub-pixel SP1' to the third sub-pixel SP3'.

[0212] The first anode electrode AE1' may be electrically connected to the first connection electrode CP1 through a contact hole penetrating the second passivation layer PSV2. The second anode electrode AE2' may be electrically connected to the second connection electrode CP2 through another contact hole penetrating the second passivation layer PSV2. The third anode electrode AE3' may be electrically connected to the third connection electrode CP3 through yet another contact hole penetrating the second passivation layer PSV2. Thus, the first anode electrode AE1' to the third anode electrode AE3' may be respectively electrically connected to the first transistor T_SP1 to the third transistor T_SP3.

[0213] The first bank BNK1 may be disposed on the first anode electrode AE1' to the third anode electrode AE3'. The first bank BNK1 may have a first opening OP1 exposing portions of the first anode electrode AE1' to the third anode electrode AE3'. The first light-emitting element LD1' to the third light-emitting element LD3' may be disposed in the first opening OP1 of the first bank BNK1. Thus, the first bank BNK1 may be provided as a pixel defining layer defining a region in which the first light-emitting element LD1' to the third light-emitting element LD3' are located.

[0214] The first light-emitting element LD1' to the third light-emitting element LD3' may be respectively disposed on the first anode electrode AE1' to the third anode electrode AE3'. The first light-emitting element LD1' to the third light-emitting element LD3' may be respectively bonded to the first anode electrode AE1' to the third anode electrode AE3'.

[0215] The first light-emitting element LD1' may include a bonding electrode BDE, a first semiconductor layer 21, an active layer 22, a second semiconductor layer 23, and an auxiliary layer 25. The first light-emitting element LD1' may be implemented as a vertical light-emitting stack structure in which the bonding electrode BDE, the second semiconductor layer 23, the active layer 22, the first semiconductor layer 21, and the auxiliary layer 25 are sequentially stacked on each other along the third direction DR3.

[0216] The first semiconductor layer 21 may be configured to provide electrons. The first semiconductor layer 21 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 21 may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the first semiconductor layer 21 is not limited thereto. Various materials may constitute the first semiconductor layer 21. In an embodiment of the present disclosure, the first semiconductor layer 21 may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant). In some embodiments, the first semiconductor layer 21 and the auxiliary layer 25 may together constitute an n-type semiconductor layer.

[0217] The active layer 22 is disposed on the first semiconductor layer 21 and may be a region where electrons and holes recombine. When electrons and holes recombine in the active layer 22, light having an energy level changed to a lower energy level and having a wavelength corresponding to the lower energy level may be generated. The active layer 22 may be formed as a single quantum well structure or a multi-quantum well structure. In the case where the active layer 22 is formed as a multi-quantum well structure, units including a barrier layer, a strain enhancing layer, and a well layer may be repeatedly stacked on each other to form the active layer 22. However, the embodiments of the active layer 22 are not limited thereto.

[0218] The second semiconductor layer 23 is disposed on the active layer 22 and provides holes to the active layer 22. The second semiconductor layer 23 may include a semiconductor layer having a type different from that of the first semiconductor layer 21. In an example, the second semiconductor layer 23 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 23 may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), or barium (Ba). However, the material constituting the second semiconductor layer 23 is not limited thereto. Various materials may constitute the second semiconductor layer 23. In an embodiment of the present disclosure, the second semiconductor layer 23 may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant).

[0219] The bonding electrode BDE may be electrically connected to the second semiconductor layer 23. The bonding electrode BDE may include an eutectic metal.

[0220] The auxiliary layer 25 may include an undoped gallium nitride (GaN) semiconductor material. The auxiliary layer 25 may together with the first semiconductor layer 21 form an n-type semiconductor layer.

[0221] The first light-emitting element LD1’ may further include an insulating film 26 covering the outer circumferential surface of the vertical light-emitting stack structure. The insulating film 26 may prevent an electrical short circuit that may occur when the active layer 22 comes into contact with another conductive material other than the first semiconductor layer 21 and the second semiconductor layer 23. The insulating film 26 may include a transparent insulating material. The insulating film 26 may be configured to expose the bottom surface of the bonding electrode BDE that faces the second semiconductor layer 23. In addition, the insulating film 26 may be configured to expose the top surface of the auxiliary layer 25 that is to contact the cathode electrode CE’.

[0222] The bottom surface of the bonding electrode BDE may contact the first anode electrode AE1’. The top surface of the auxiliary layer 25 may be connected to the cathode electrode CE’. Accordingly, the first light-emitting element LD1’ may be electrically connected between the first anode electrode AE1’ and the cathode electrode CE’.

[0223] In an embodiment, a reflective electrode may be provided between the bonding electrode BDE and the second semiconductor layer 23. Light emitted from the first light-emitting element LD1’ may be effectively output toward the light conversion layer LCL. The reflective electrode may be configured with a conductive material having a predetermined or selected reflectivity. The conductive material may include an opaque metal. The opaque metal may include, for example, metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys thereof. However, the material of the reflective electrode is not limited thereto.

[0224] Each of the second light-emitting element LD2’ and the third light-emitting element LD3’ may be configured to be the same as the first light-emitting element LD1’. Redundant descriptions will be omitted hereinafter.

[0225] An insulating layer OCL may be provided in a first opening OP1 in which the first light-emitting element LD1’ to the third light-emitting element LD3’ are provided. The insulating layer OCL may fix the first light-emitting element LD1’ to the third light-emitting element LD3’ bonded to the first anode electrode AE1’ to the third anode electrode AE3’ so as not to move. In addition, the insulating layer OCL may protect components provided thereunder from foreign substances such as dust or moisture. For example, the insulating layer OCL may include at least one of an inorganic insulating layer and an organic insulating layer.

[0226] In an embodiment, the insulating layer OCL may not be provided on the top surface LTS of each of the first light-emitting element LD1' to the third light-emitting element LD3'. The first light-emitting element LD1' to the third light-emitting element LD3' may protrude into the light conversion layer LCL. The first light-emitting element LD1' to the third light-emitting element LD3' may be at least partially located in the second opening OP2 of the second bank BNK2. For example, the height of the top surface LTS of each of the first light-emitting element LD1' to the third light-emitting element LD3' from the substrate SUB may be higher than the height of the lowermost end RBE of the reflective layer RFL from the substrate SUB. Therefore, the light emitted from the first light-emitting element LD1' to the third light-emitting element LD3' can be provided to the light conversion layer LCL at a relatively high ratio.

[0227] The cathode electrode CE' may be provided on the first light-emitting element LD1' to the third light-emitting element LD3'. The cathode electrode CE' may be entirely provided on the first bank BNK1, the first light-emitting element LD1' to the third light-emitting element LD3', and the insulating layer OCL. The cathode electrode CE' may be in contact with the auxiliary layer 25 of each of the first light-emitting element LD1' to the third light-emitting element LD3'. The cathode electrode CE' may be electrically connected to Figure 2 the second power voltage node VSSN shown in. The second power voltage applied to the second power voltage node VSSN may be transmitted to the first light-emitting element LD1' to the third light-emitting element LD3' through the cathode electrode CE'.

[0228] The cathode electrode CE' may be substantially transparent or semi-transparent to meet a predetermined or selected light transmittance. In an embodiment, the cathode electrode CE' may include at least one of various transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the material of the cathode electrode CE' is not limited thereto.

[0229] The capping layer CPL may be provided throughout the cathode electrode CE'. The capping layer CPL may protect components such as the cathode electrode CE' and the first light-emitting element LD1' to the third light-emitting element LD3' provided thereunder from external moisture, humidity, etc. The capping layer CPL may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and at least one of metal oxides such as aluminum oxide (AlO x ). However, the material of the capping layer CPL is not limited thereto.

[0230] The light conversion layer LCL can be disposed on the capping layer CPL. The light conversion layer LCL can include a second bank BNK2, a reflective layer RFL, a third passivation layer PSV3, a first light conversion pattern CCP1 to a third light conversion pattern CCP3, a low refractive index layer LRL, and a color filter layer CFL.

[0231] The second bank BNK2 can be disposed on the capping layer CPL. The second bank BNK2 can overlap with the first bank BNK1. The second bank BNK2 can have a second opening OP2 that overlaps with the first opening OP1.

[0232] The second bank BNK2 can be configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels and between the first sub-pixel SP1’ to the third sub-pixel SP3’. In an embodiment, the second bank BNK2 can include an organic material. For example, the second bank BNK2 can include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0233] The reflective layer RFL can be disposed on a side surface of the second bank BNK2 adjacent to the second opening OP2. The reflective layer RFL can be configured to reflect incident light and thus can improve light emission efficiency. The reflective layer RFL can include a material suitable for reflecting light. The reflective layer RFL can include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0234] It can be understood that the emission areas EMA and non-emission areas NEMA of the first sub-pixel SP1’ to the third sub-pixel SP3’ are defined by the second bank BNK2. The area overlapping with the second bank BNK2 can correspond to the non-emission area NEMA. The area overlapping with the second opening OP2 of the second bank BNK2 can correspond to the emission area EMA.

[0235] On the capping layer CPL, the third passivation layer PSV3 can be disposed in the second opening OP2. The third passivation layer PSV3 can protect the components disposed thereunder and provide a flat top surface. The third passivation layer PSV3 can include the same material as either the first passivation layer PSV1 or the second passivation layer PSV2, but the embodiments are not limited thereto.

[0236] On the third passivation layer PSV3, the first light conversion pattern CCP1 to the third light conversion pattern CCP3 can be disposed in the second opening OP2.

[0237] Figure 23is a schematic diagram showing the execution of exposure for bonding Figure 21 the first light-emitting element shown in Figure 21 The method of bonding the first light-emitting element LD1' shown in can be substantially the same as the method described in the reference Figures 10 to 17 and thus, redundant descriptions will be omitted.

[0238] Reference Figure 23 , the insulating layer OCL can be exposed by the light irradiated on the first light-emitting element LD1'. For example, ultraviolet light can be irradiated toward the insulating layer OCL on the first light-emitting element LD1'.

[0239] The light irradiated toward the insulating layer OCL can be blocked by the bonding electrode BDE. That is, the bonding electrode BDE can be used as a mask.

[0240] As a result of developing the insulating layer OCL, a first opening OCL_OP1 exposing the first anode electrode AE1' of the insulating layer OCL can be formed at a position corresponding to the position of the bonding electrode BDE.

[0241] Figure 24 and Figure 25 are schematic plan views showing a first sub-pixel and a repair region of a display device according to an embodiment of the present disclosure.

[0242] Except for the repair region RA, the pixels of the display device according to the embodiment of the present disclosure can be configured to be substantially the same as the pixels PXL of the display device shown in Figure 6 Therefore, components that are the same as or similar to the components of the display device shown in are denoted by the same reference numerals, and redundant descriptions will be omitted. Figure 6

[0243] Reference Figure 24 and Figure 25 , in the case where the first light-emitting element LD1 has a defect, a light-emitting element ALD (hereinafter, referred to as an additional light-emitting element) can be bonded to an anode electrode AAE (hereinafter, referred to as an additional anode electrode) of a repair region RA adjacent to the first sub-pixel SP1. The structure of the repair region RA can be substantially the same as the structure of the first sub-pixel SP1.

[0244] The defect of the first light-emitting element LD1 not only means a defect of the first light-emitting element LD1 itself, but also includes all defects such as the first light-emitting element LD1 being unable to emit light normally due to problems in the bonding of the first light-emitting element LD1.

[0245] ​The additional light-emitting element ALD can be bonded substantially in the same manner as the first light-emitting element LD1. For example, after bonding the first light-emitting element LD1, in the case where the first light-emitting element LD1 is determined to be a defective light-emitting element, the additional light-emitting element ALD can be aligned in the repair region RA on the insulating layer OCL (see Figure 8 ). When the insulating layer OCL (see Figure 8 ) is exposed and developed, at least a part of the additional anode electrode AAE can be exposed, and the additional light-emitting element ALD can be bonded to the additional anode electrode AAE.

[0246] Thus, even in the process of bonding the additional light-emitting element ALD, the additional light-emitting element ALD can be used as a mask, so that process tolerances can be ensured.

[0247] In the above, the repair region RA adjacent to the first sub-pixel SP1 has been described. Figure 6 Each of the second sub-pixel SP2 and the third sub-pixel SP3 shown in

[0248] Figure 26 can be configured to be the same as the first sub-pixel SP1 within the scope not differently described herein. However, it is not necessary to provide a repair region RA for each of all sub-pixels.

[0249] Except for the overlapping region RDA, the pixels of the display device according to an embodiment of the present disclosure can be configured to be substantially the same as the pixels PXL of the display device shown in Figure 6 . Therefore, components that are the same as or similar to the components of the display device shown in Figure 6 are denoted by the same reference numerals, and redundant descriptions will be omitted.

[0250] Referring to Figure 26 , the light-emitting element ALD (hereinafter, referred to as the additional light-emitting element) can be bonded to the anode electrode AAE (hereinafter, referred to as the additional anode electrode) of the overlapping region RDA adjacent to the first sub-pixel SP1. The structure of the overlapping region RDA can be substantially the same as the structure of the first sub-pixel SP1.

[0251] The additional light-emitting element ALD can be bonded substantially in the same manner as the first light-emitting element LD1. For example, after bonding the first light-emitting element LD1, the additional light-emitting element ALD can be aligned in the overlapping region RDA on the insulating layer OCL (see Figure 8 ). When the insulating layer OCL (see Figure 8 ) is exposed and developed, at least a part of the additional anode electrode AAE can be exposed, and the additional light-emitting element ALD can be bonded to the additional anode electrode AAE.

[0252] In the case where the first light-emitting element LD1 becomes defective, the additional light-emitting element ALD can operate. For example, in the case where the first light-emitting element LD1 becomes defective while using the display device, the additional light-emitting element ALD can be driven to replace the first light-emitting element LD1.

[0253] Thus, even in the process of bonding the additional light-emitting element ALD, the additional light-emitting element ALD can be used as a mask, so that process tolerance can be ensured.

[0254] In the above, the overlapping region RDA adjacent to the first sub-pixel SP1 has been described. Figure 6 Each of the second sub-pixel SP2 and the third sub-pixel SP3 shown in can be configured to be the same as the first sub-pixel SP1 within the range not differently described herein. However, it is not necessary to provide the overlapping region RDA for each of all the sub-pixels.

[0255] Figure 27 is a schematic plan view showing an example in which the first light-emitting element to the third light-emitting element are provided in the Figure 6 pixels shown in.

[0256] Reference Figure 27 , each of the first light-emitting element LD1 to the third light-emitting element LD3 can be bonded. For example, after the first light-emitting element LD1 is bonded to the first anode electrode AE1 and the cathode electrode CE, the second light-emitting element LD2 can be bonded to the second anode electrode AE2 and the cathode electrode CE. For example, after the second light-emitting element LD2 is bonded to the second anode electrode AE2 and the cathode electrode CE, the third light-emitting element LD3 can be bonded to the third anode electrode AE3 and the cathode electrode CE. However, the present disclosure is not limited to the order in which the first light-emitting element LD1 to the third light-emitting element LD3 are bonded.

[0257] For example, in the method of manufacturing a display device, the first light-emitting element LD1 can be aligned in the first sub-pixel SP1 on the insulating layer OCL (see Figure 8 ), the insulating layer OCL (see Figure 8 ) can be exposed, the first anode electrode AE1 and the cathode electrode CE can be exposed by developing the insulating layer OCL (see Figure 8 ), the first light-emitting element LD1 can be bonded to the first anode electrode AE1 and the cathode electrode CE, the second light-emitting element LD2 can be aligned in the second sub-pixel SP2 on the insulating layer OCL (see Figure 8 ), the insulating layer OCL (see Figure 8 ) can be repeatedly exposed, and the insulating layer OCL (see Figure 8)By redeveloping to expose the second anode electrode AE2 and the cathode electrode CE, the second light-emitting element LD2 can be bonded to the second anode electrode AE2 and the cathode electrode CE. It is possible to align the third light-emitting element LD3 in the third sub-pixel SP3 on the insulating layer OCL (see Figure 8 ). The insulating layer OCL (see Figure 8 ) can be repeatedly exposed. By redeveloping the insulating layer OCL (see Figure 8 ), the third anode electrode AE3 and the cathode electrode CE can be exposed, and the third light-emitting element LD3 can be bonded to the third anode electrode AE3 and the cathode electrode CE.

[0258] The first sub-pixel SP1 to the third sub-pixel SP3 mean the concept including even the area where the first sub-pixel SP1 to the third sub-pixel SP3 are provided.

[0259] Thus, each of the first light-emitting element LD1 to the third light-emitting element LD3 is bonded so that the process tolerance of each of the first light-emitting element LD1 to the third light-emitting element LD3 can be ensured.

[0260] Figure 28 is a schematic block diagram showing an embodiment of the display system.

[0261] Referring to Figure 28 , the display system 1000 may include a processor 1100 and a display device 1200.

[0262] The processor 1100 may perform various tasks and various calculations. In an embodiment, the processor 1100 may include an application processor (AP), a graphics processing unit (GPU), a microprocessor, a central processing unit (CPU), etc. The processor 1100 may be connected to other components of the display system 1000 through a bus system to control the components of the display system 1000.

[0263] The processor 1100 may transmit input image data IMG and a control signal CTRL to the display device 1200. The display device 1200 may display an image based on the input image data IMG and the control signal CTRL. The display device 1200 may be configured to be the same as the display device DD described in reference Figure 1 . The input image data IMG and the control signal CTRL may be set to the input image data IMG and the control signal CTRL shown in Figure 1 respectively.

[0264] The display system 1000 may include a computing system for providing an image display function, such as a smart watch, a mobile phone, a smartphone, a portable computer, a tablet personal computer (PC), a watch phone, a car display, smart glasses, a portable multimedia player (PMP), a navigation system, or an ultra-mobile computer (UMPC). The display system 1000 may include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0265] Figures 29 to 32 is a schematic perspective view showing Figure 28 an application example of the display system shown in

[0266] Reference Figure 29 , Figure 28 the display system 1000 shown in can be applied to a smart watch 2000 including a display part 2100 and a band part 2200.

[0267] The smart watch 2000 may be a wearable electronic device. For example, the smart watch 2000 may have a structure in which the band part 2200 is mounted on a user's wrist. The display system 1000 and / or the display device 1200 may be applied to the display part 2100 such that image data including time information can be provided to the user.

[0268] Reference Figure 30 , Figure 28 the display system 1000 shown in can be applied to a car display system 3000. The car display system 3000 may include a computing system provided inside / outside the vehicle to provide image data.

[0269] For example, the display system 1000 and / or the display device 1200 may be applied to at least one of an infotainment panel 3100, an instrument panel 3200, a co-pilot display 3300, a head-up display 3400, a side mirror display 3500, and a rear seat display 3600 provided in the vehicle.

[0270] Reference Figure 31 , Figure 28 the display system 1000 shown in can be applied to smart glasses 4000. The smart glasses 4000 are wearable electronic devices that can be worn on a user's face. For example, the smart glasses 4000 may be wearable devices for augmented reality (AR).

[0271] The smart glasses 4000 may include a frame 4100 and a lens portion 4200. The frame 4100 may include a housing 4110 that supports the lens portion 4200 and a leg portion 4120 for allowing a user to wear the smart glasses 4000. The leg portion 4120 may be connected to the housing 4110 by a hinge to fold or unfold relative to the housing 4110.

[0272] A battery, a touchpad, a microphone, a camera, etc. may be built into the frame 4100. A projector for outputting light, a processor for controlling an optical signal, etc. may be built into the frame 4100.

[0273] The lens portion 4200 may be an optical member that allows light to transmit therethrough or allows light to be reflected therefrom. For example, the lens portion 4200 may include glass, a transparent synthetic resin, etc.

[0274] In order for a user's eyes to recognize visual information, the lens portion 4200 may allow an image caused by an optical signal transmitted from the projector of the frame 4100 to be reflected by the rear surface of the lens portion 4200 (e.g., the surface in the direction facing the user's eyes). For example, the user may recognize information including time, data, etc. displayed on the lens portion 4200. The projector and / or the lens portion 4200 may be a display device. The display device 1200 may be applied to the projector and / or the lens portion 4200.

[0275] Reference Figure 32 , Figure 28 the display system 1000 shown in may be applied to the head-mounted display device 5000.

[0276] The head-mounted display device 5000 may be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device 5000 may be a wearable device for virtual reality (VR) or mixed reality (MR).

[0277] The head-mounted display device 5000 may include a head-mounted band 5100 and a display housing box 5200. The head-mounted band 5100 may be connected to the display housing box 5200. The head-mounted band 5100 may include a horizontal band and / or a vertical band for fixing the head-mounted display device 5000 to the user's head. The horizontal band may be configured to surround a side portion of the user's head, and the vertical band may be configured to surround an upper portion of the user's head. However, the embodiments are not limited thereto. For example, the head-mounted band 5100 may be implemented in the form of a glasses frame, a helmet, etc.

[0278] The display housing box 5200 may accommodate the display system 1000 and / or the display device 1200.

[0279] The present disclosure can be applied to a display device and an electronic device including the display device. For example, the present disclosure can be applied to a digital TV, a 3D TV, a mobile phone, a smart phone, a tablet computer, a VR device, a PC, a household appliance, a notebook computer, a PDA, a PMP, a digital camera, a music player, a portable game console, a navigation system, etc.

[0280] In a method of manufacturing a display device according to the present disclosure, a light-emitting element is used as a mask, so that process tolerance can be ensured. Accordingly, the yield of the display device can be improved.

[0281] In a method of manufacturing a display device according to the present disclosure, a light-emitting element is used as a mask, so that the number of masks can be reduced. Accordingly, the process can be simplified.

[0282] In a method of manufacturing a display device according to the present disclosure, an insulating layer is formed on an anode electrode and / or a cathode electrode, and an opening is formed using a light-emitting element as a mask, so that a short circuit between the cathode electrode and the anode electrode can be prevented.

[0283] Exemplary embodiments have been disclosed herein, and although specific terms are used, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to those of ordinary skill in the art at the time of filing this application, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Accordingly, those skilled in the art will understand that various changes may be made in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a display device, the method comprising: forming a first electrode on a substrate; forming an insulating layer over the first electrode; aligning a first light emitting element on the insulating layer; exposing the insulating layer; exposing at least a portion of the first electrode by developing the insulating layer; as well as The first light emitting element is bonded to the at least a portion of the first electrode.

2. The method according to claim 1, wherein: The first light emitting element includes a first bonding electrode bonded to the at least a portion of the first electrode.

3. The method according to claim 2, wherein: The first light emitting element further comprises: a semiconductor layer; and The reflective electrode is provided between the semiconductor layer and the first bonding electrode.

4. The method according to claim 2, wherein: Engaging the first light emitting element comprises: positioning the first bonding electrode in the opening of the insulating layer exposing the at least a portion of the first electrode; and The first bonding electrode is melted.

5. The method according to claim 2, wherein: An opening of the insulating layer exposing the at least a portion of the first electrode is formed at a position corresponding to a position of the first bonding electrode.

6. The method according to claim 1, wherein: In the process of forming the first electrode, forming a second electrode spaced apart from the first electrode, During the development of the insulating layer, at least a portion of the second electrode is exposed, and The first light emitting element is bonded to the at least a portion of the first electrode and the at least a portion of the second electrode.

7. The method according to claim 6, wherein: The first light emitting element includes a second bonding electrode bonded to the at least a portion of the second electrode.

8. The method according to claim 1, wherein: The insulating layer includes a photosensitive organic insulating material.

9. The method according to claim 1, wherein: The first light emitting element is bonded to the first electrode of the first sub-pixel, and The method further includes bonding an additional light emitting element to the first electrode at a repair area adjacent to the first sub-pixel if the first light emitting element is defective.

10. The method according to claim 9, wherein: Engaging the additional light emitting element comprises: aligning the additional light emitting element in the repair area on the insulating layer; exposing the insulating layer; exposing at least a portion of the first electrode of the repair area by developing the insulating layer; and The additional light emitting element is bonded to the at least a portion of the first electrode of the repair area.

11. The method according to claim 1, wherein: The first light emitting element is bonded to the first electrode of the first sub-pixel, and The method also includes bonding an additional light emitting element to the first electrode at an overlapping region adjacent to the first subpixel.

12. The method according to claim 11, wherein: In case the first light emitting element becomes defective, the additional light emitting element is driven.

13. The method according to claim 1, wherein: The first light emitting element is bonded to the first electrode of the first sub-pixel, and The method further comprises: aligning a second light emitting element in a second sub-pixel on the insulating layer; repeatedly exposing the insulating layer; exposing at least a portion of the first electrode of the second sub-pixel by redeveloping the insulating layer; and The second light emitting element is bonded to the at least a portion of the first electrode of the second sub-pixel.

14. The method according to claim 13, wherein: The first sub-pixel and the second sub-pixel display different colors.

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