Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes: an insulating layer; a pad portion disposed on the insulating layer; a conductive metal portion disposed on the pad portion; a protective layer disposed on the conductive metal portion; and a bonding portion passing through at least a portion of the protective layer and electrically connected to the conductive metal portion, in which the pad portion includes a first portion inclined in a vertical direction from an upper surface of the pad portion toward a lower surface of the insulating layer to widen a width in a horizontal direction, and a second portion inclined in a vertical direction from an upper surface of the pad portion toward a lower surface of the insulating layer. The second portion extends from the first portion and has an inclination different from an inclination of the first portion, and the conductive metal portion is disposed to cover at least a portion of a side surface of the first portion.

Description

Technical Field

[0001] The embodiments relate to semiconductor packages, and more particularly, to a circuit board including highly consistent bonding portions and a semiconductor package including the circuit board. Background Art

[0002] The performance of electrical / electronic products is improving, and thus, technologies for arranging a larger number of semiconductor devices on a semiconductor package substrate of a limited size are being proposed and studied. However, since general semiconductor packages are based on mounting a single semiconductor device, there are limitations in obtaining desired performance.

[0003] Therefore, recent semiconductor packages use multiple circuit boards to arrange multiple semiconductor devices. The semiconductor package has a structure in which multiple semiconductor devices are connected to each other in the horizontal direction and / or the vertical direction on the circuit board. Thus, the semiconductor package has the advantages of effectively using the mounting area of the semiconductor devices and transmitting high-speed signals through short signal transmission paths between the semiconductor devices.

[0004] In addition, according to the trend of high integration, the number and / or the size of each semiconductor device increase, or the functional portions of the semiconductor devices are divided, and the concept of semiconductor packages applied to products such as the Internet of Things (IoT), autonomous driving vehicles, and high-performance servers is expanding to semiconductor chiplets.

[0005] Therefore, the mutual communication between semiconductor devices and / or semiconductor chiplets becomes important, and thus, there is a trend of mounting an interposer between a semiconductor package substrate connected to a main board of an electronic device and the semiconductor devices.

[0006] The interposer can be used as a redistribution layer that gradually increases the width or length of the circuit pattern from the semiconductor device to the semiconductor package to facilitate the mutual communication between the semiconductor devices and / or semiconductor chiplets, or to interconnect the semiconductor devices and the semiconductor package substrate. Thus, the interposer can be used to facilitate the electrical signals between the semiconductor device and the semiconductor package substrate, and the semiconductor package substrate has a relatively larger circuit pattern compared to the circuit pattern of the semiconductor device.

[0007] Meanwhile, recently, as the functions provided by semiconductor devices increase and the performance of semiconductor devices improves, the number of I / O terminals provided in semiconductor devices has also increased. Therefore, as the width and / or pitch of the I / O terminals provided in semiconductor devices become smaller, during the process of connecting the I / O terminals of semiconductor devices through a coupling member such as solder, electrical short circuits where multiple coupling members come into contact with each other may occur. Therefore, as the terminal density of semiconductor devices increases, a micro-bonding process such as Thermal Compression Bonding (hereinafter referred to as "TC bonding") can be performed to reduce the amount of coupling members such as solder. Additionally, if a micro-bonding process is performed, an interposer and / or a semiconductor package substrate can be provided with bonding portions to improve alignment with the terminals of the semiconductor device. The semiconductor package substrate can have bonding portions protruding on the interposer and / or the semiconductor package substrate to reduce the volume of the coupling member and increase alignment with the terminals of the semiconductor device.

[0008] At this time, due to process variations in the plating process for forming the bonding portions and / or differences in the width in the horizontal direction and / or the area of the lower surface of each of the multiple bonding portions, differences in the current applied during the plating process occur, which may lead to differences in the plating process speed. Therefore, height variations may occur between the multiple bonding portions. If there are height variations between the multiple bonding portions, the semiconductor device may not be stably mounted, and the electrical connection reliability between the semiconductor device and the circuit board may deteriorate. Summary of the Invention

[0009] Technical Problem

[0010] Embodiments provide a circuit board having improved adhesion between an insulating layer and an electrode portion and a semiconductor package including the circuit board.

[0011] In addition, embodiments provide a circuit board and a semiconductor package that impart a uniform center line average surface roughness (Ra) on the interface between an insulating layer and an electrode portion.

[0012] In addition, embodiments provide a circuit board having improved electrical reliability and a semiconductor package including the circuit board.

[0013] In addition, embodiments provide a circuit board and a semiconductor package in which an electroless copper layer of an electrode portion and a reinforcing member in an insulating layer do not contact each other.

[0014] In addition, embodiments provide a circuit board and a semiconductor package that minimize height variations between multiple bonding portions.

[0015] The technical problems to be solved by the proposed embodiments are not limited to the above technical problems, and those skilled in the art of the proposed embodiments can clearly understand other technical problems not mentioned from the following description.

[0016] Technical solution

[0017] The circuit board according to the embodiment includes: an insulating layer; a pad portion provided on the insulating layer; a conductive metal portion provided on the pad portion; a protective layer provided on the conductive metal portion; and a bonding portion passing through at least a part of the protective layer and electrically connected to the conductive metal portion, wherein the pad portion includes a first portion and a second portion, the first portion is inclined vertically from the upper surface of the pad portion toward the lower surface of the insulating layer to widen the width in the horizontal direction, the second portion extends from the first portion and has an inclination different from that of the first portion, and the conductive metal portion is provided to cover at least a part of the side surface of the first portion.

[0018] In addition, the bonding portion includes a protruding portion provided on the protective layer and a through portion extending from the protruding portion, the through portion passing through at least a part of the protective layer and electrically connected to the conductive metal portion.

[0019] In addition, the insulating layer has a reinforcing member, and at least a part of the side surface of the first portion of the pad portion does not overlap with the reinforcing member of the insulating layer in the horizontal direction.

[0020] In addition, a concave portion is provided on the upper surface of the insulating layer, and the first portion of the pad portion is provided in the concave portion.

[0021] In addition, the conductive metal portion includes a metal material different from the metal material of at least one of the pad portion and the bonding portion.

[0022] In addition, the side surface of the first portion of the pad portion has a curved surface.

[0023] In addition, the through portion does not overlap with the curved surface in the vertical direction.

[0024] In addition, the width of the protruding portion in the horizontal direction is smaller than the width of the second portion of the pad portion.

[0025] In addition, the conductive metal portion includes a contact portion and an extending portion, the contact portion is in contact with the upper surface of the first portion of the pad portion, and the extending portion extends from the contact portion and does not overlap with the upper surface of the first portion in the vertical direction.

[0026] In addition, the extension portion overlaps with the curved surface in the vertical direction.

[0027] In addition, the extension portion bends from the contact portion toward the upper surface of the insulating layer and overlaps with the side surface of the first portion of the pad portion in the horizontal direction.

[0028] In addition, the extension portion includes an upper surface, an inner surface facing the side surface of the first portion of the pad portion, an outer surface opposite to the inner surface, and a lower surface between the inner surface and the outer surface, and the upper surface and the outer surface of the extension portion are in contact with the protective layer.

[0029] In addition, the lower surface of the extension portion does not contact the side surface of the first portion of the pad portion.

[0030] In addition, the lower surface of the extension portion is in contact with the protective layer.

[0031] In addition, the inner surface of the extension portion is in contact with the side surface of the first portion of the pad portion.

[0032] In addition, at least a part of the inner surface of the extension portion does not contact the side surface of the first portion of the pad portion and contacts the protective layer.

[0033] In addition, the extension portion does not overlap with the side surface of the first portion of the pad portion in the horizontal direction.

[0034] In addition, the lower surface of the extension portion is in contact with the side surface of the first portion of the pad portion.

[0035] In addition, the width of the through portion is smaller than the width of the conductive metal portion in the horizontal direction.

[0036] In addition, the width of the through portion is smaller than the width of the upper surface of the first portion of the pad portion.

[0037] In addition, the vertical length of the through portion is greater than the vertical length of the pad portion.

[0038] In addition, the vertical length of the through portion is smaller than the vertical length of the pad portion.

[0039] In addition, the circuit board further includes a connection circuit pattern portion that overlaps with the second portion of the pad portion in the horizontal direction and does not overlap with the pad portion in the vertical direction, and the connection circuit pattern portion does not overlap with the first portion of the pad portion in the horizontal direction.

[0040] In addition, the insulating layer includes a first layer and a second layer. The first layer includes a reinforcing member, and the second layer is disposed on the first layer and does not include a reinforcing member. At least a part of the pad portion overlaps with the second layer in the horizontal direction.

[0041] In addition, a recess is provided on the upper surface of the insulating layer, and each of the first portion and the second portion of the pad portion is disposed in the recess.

[0042] In addition, the conductive metal portion includes a first region and a second region. The first region is disposed on the pad portion, and the second region extends from the first region between the side surface of the first portion of the pad portion and the inner wall of the recess.

[0043] In addition, the second region of the conductive metal portion overlaps with at least a part of each of the first layer, the second layer, and the pad portion in the horizontal direction.

[0044] In addition, the recess includes a first portion and a second portion. The first portion is disposed in the first layer of the insulating layer, and the second portion is disposed in the second layer of the insulating layer and is connected to the first portion.

[0045] In addition, the upper surface of the pad portion is positioned lower than the upper surface of the second layer of the insulating layer.

[0046] In addition, the side surface of the first portion of the pad portion overlaps with the inner wall of the recess in the horizontal direction and is spaced apart from the inner wall of the recess.

[0047] In addition, the side surface of the second portion of the pad portion contacts the inner wall of the recess.

[0048] In addition, the conductive metal portion is disposed between the side surface of the first portion of the pad portion and the inner wall of the recess.

[0049] In addition, the conductive metal portion includes a portion protruding above the second layer of the insulating layer, and at least a part of the protruding portion of the conductive metal portion contacts the upper surface of the second layer of the insulating layer.

[0050] In addition, the reinforcing member is a filler disposed in a resin of an organic material, and the second layer of the insulating layer is a pure resin layer that does not include a filler.

[0051] In addition, a first surface roughness is provided on the upper surface of the second layer of the insulating layer, and a second surface roughness different from the first surface roughness is provided at the interface between the first layer and the second layer of the insulating layer.

[0052] In addition, the second surface roughness corresponding to the particle size of the filler provided in the first layer of the insulating layer is provided at the interface.

[0053] In addition, the first surface roughness is a center line average surface roughness (Ra) in the range of 0.2 μm to 1.5 μm.

[0054] In addition, the inner wall of the recess has a third surface roughness smaller than the first surface roughness.

[0055] In addition, the deviation of the center line average surface roughness of the plurality of lines provided on the upper surface of the second layer of the insulating layer is smaller than the deviation of the center line average surface roughness of the plurality of lines at the interface between the first layer and the second layer.

[0056] In addition, the first layer of the insulating layer is provided with fillers having different particle sizes, and the value of the center line average surface roughness of the upper surface of the second layer is smaller than the average value of the particle sizes of the fillers.

[0057] Advantageous Effects

[0058] The circuit board of the embodiment can minimize the height deviation between a plurality of joint portions connected to the coupling member. Specifically, the circuit board of the embodiment may include a pad portion. The pad portion may include a first portion embedded in the insulating layer and a second portion provided on the first portion and protruding on the insulating layer. In addition, the circuit board may include a connection circuit pattern portion corresponding to the trace, and the connection circuit pattern portion overlaps the first portion of the plurality of pad portions in the horizontal direction. At this time, the second portion of the pad portion may be a seed layer for forming the first portion of the pad portion and the connection circuit pattern portion by electroplating.

[0059] Specifically, the conventional circuit board completely removes the copper layer used as the seed layer. Therefore, the thickness of the bonding portion provided on the pad portion in the conventional circuit board can be increased. As a result, the conventional circuit board may have a height deviation between a plurality of bonding portions spaced apart from each other in the horizontal direction. Therefore, when the semiconductor device is bonded to the bonding portion, due to the height difference between the plurality of bonding portions, the conventional circuit board may not be able to stably place the semiconductor device on the bonding portion, but may bond the semiconductor device in a tilted state in a specific direction. In contrast, the embodiment may not remove the portion of the copper layer used as the seed layer in the region where the bonding portion is to be provided, thereby allowing the pad portion to have a second portion, which is the non-removed portion of the copper layer as described above. At this time, the upper surface of the second portion of the pad portion may represent the upper surface of the copper layer preferentially provided on the carrier member during the manufacturing process of the circuit board. Therefore, the upper surface of the second portion of the pad portion may be flat. In addition, the upper surfaces of the second portions of the plurality of pad portions may be located on the same plane. Therefore, the embodiment may form a plurality of bonding portions having a uniform thickness and / or height by arranging the bonding portions on the second portion of the pad portion. In addition, the embodiment may reduce the thickness of the bonding portion by the thickness of the second portion of the pad portion. Therefore, the embodiment may solve the problem that the thickness deviation between the plurality of bonding portions increases in proportion to the thickness of the bonding portion. Therefore, the embodiment may minimize the height deviation between the plurality of bonding portions. Therefore, the embodiment may stably dispose the semiconductor device on the plurality of bonding portions. In addition, compared with the thickness of the conventional bonding portion, the embodiment may increase the thickness of the bonding portion by the thickness of the second portion of the pad portion. In addition, even if the thickness of the bonding portion is increased, the embodiment may minimize the thickness deviation between the plurality of bonding portions by forming the bonding portion using the pad portion having a uniform height.

[0060] Therefore, the embodiment can ensure the height of the bonding portion that allows the semiconductor device to be stably bonded, and can improve the overall physical and / or electrical characteristics of the semiconductor package. Therefore, the semiconductor device can be operated smoothly, and further, the server or electronic product can be operated smoothly.

[0061] In addition, the bonding portion may include a through portion that passes through at least a part of the region of the upper surface of the protective layer and protrudes onto the protective layer, and a protruding portion provided on the through portion and protruding onto the protective layer. The second portion of the pad portion may include a side surface having a curvature. The through portion of the bonding portion may overlap with the side surface having a curvature of the pad portion in the vertical direction. Therefore, when forming the through portion of the bonding portion, the embodiment may allow the through portion to be offset to one side on the pad portion. Thereby, the embodiment may increase the interval between a plurality of through portions adjacent to each other, and further increase the interval between a plurality of bonding portions adjacent to each other. The embodiment may increase the amount of coupling members provided on the bonding portion by increasing the spacing between the bonding portions, thereby improving the bonding strength between the semiconductor device and the circuit board.

[0062] In addition, the conductive metal portion of the bonding portion may include a contact portion that overlaps with the upper surface of the pad portion in the vertical direction, and an extension portion that overlaps with the side surface having a curvature of the pad portion in the vertical direction. The extension portion may be bent from the contact portion in a bending direction corresponding to the curvature of the side surface of the pad portion. Thereby, the embodiment may increase the contact area between the protective layer and the pad portion by using the extension portion, thereby improving the bonding force between the protective layer and the pad portion.

[0063] In addition, at least a part of the inner surface of the extension portion of the conductive metal portion may not be in contact with the side surface of the pad portion. Thereby, a certain separation space may be provided between the side surface of the pad portion and the inner surface of the extension portion. At this time, a protective layer may be provided to fill the separation space. At this time, the separation space may be used as an anchor for improving the bonding force with the protective layer. Thereby, the embodiment may improve the adhesion between the insulating layer and the protective layer and the adhesion between the protective layer and the bonding portion.

[0064] The insulating layer of another embodiment may include a first layer and a second layer on the first layer, and the first layer includes a reinforcing member. The first layer of the insulating layer may include a reinforcing member such as a filler, and the second layer may not include a reinforcing member and may be, for example, a pure resin layer. Thereby, the embodiment may improve the electrical characteristics of the electrode portion while ensuring the adhesion between the insulating layer and the circuit layer. Specifically, the insulating layer of the comparative example only includes the first layer integrally provided with the reinforcing member. Therefore, there is a problem that the reinforcing member provided in the first layer comes into contact with the circuit layer. When the circuit layer comes into contact with the filler, the adhesion decreases in the corresponding contact area, and due to the physical properties of the reinforcing member, the transmission loss of the signal transmitted through the circuit layer increases, which may deteriorate the electrical characteristics. In addition, when reducing the content of the reinforcing member provided in the insulating layer to solve this problem, the rigidity of the circuit board may deteriorate. When the rigidity of the circuit board deteriorates, there may be a reliability problem that the circuit board bends significantly in a specific direction.

[0065] Therefore, the embodiment allows the insulating layer to be divided into a first layer and a second layer, thereby ensuring the adhesion between the electrode portion and the insulating layer while improving the electrical characteristics of the electrode portion. To this end, the first layer of the insulating layer may be composed of an organic material including a reinforcing member. Thus, the first layer can ensure the rigidity of the insulating layer while allowing the electrode portion to be stably disposed on the insulating layer. The second layer of the insulating layer may be disposed on the first layer of the insulating layer. The second layer of the insulating layer may not include a reinforcing member, and the electrode portion may be disposed on the second layer of the insulating layer. For example, the electrode portion may be in contact with the second layer of the insulating layer. At this time, the second layer of the insulating layer may not be provided with a reinforcing member, and thus, the electrode portion may not be in contact with the reinforcing member. Therefore, the embodiment can improve the adhesion between the electrode portion and the insulating layer. In addition, the embodiment can improve the electrical characteristics of the electrode portion.

[0066] In addition, the electrode portion of the embodiment may include a lower wiring electrode, and the lower wiring electrode may include a first metal layer of an electroless copper plating layer. At this time, the insulating layer includes a third layer below the first layer, and the third layer of the insulating layer may not include a reinforcing member. In addition, a certain degree of center line average surface roughness (Ra) may be provided on the lower surface of the third layer. Therefore, the embodiment can improve the adhesion between the first metal layer of the lower wiring electrode and the insulating layer. At this time, the first metal layer of the embodiment does not contact the first layer of the insulating layer. That is, the first metal layer does not contact the reinforcing member provided in the first layer of the insulating layer. Thus, the embodiment can solve the problem that the adhesion between the first metal layer and the insulating layer is reduced due to the reinforcing member. In addition, the embodiment can prevent the transmission loss of the signal transmitted through the first metal layer from increasing due to the reinforcing member. Thus, the embodiment can improve the physical reliability and electrical reliability of the circuit board.

[0067] In addition, the embodiment can give a uniform surface roughness to the upper surface of the second layer by allowing the insulating layer to include a first layer and a second layer. Thus, the embodiment can provide a conductive metal portion and / or a bonding portion having a uniform thickness. Specifically, by disposing the conductive metal portion and / or the bonding portion on the second layer of the insulating layer having a uniform surface roughness, the embodiment can allow the conductive metal portions and / or the bonding portions spaced apart from each other in the horizontal direction to have a uniform thickness. Thus, the embodiment can allow the semiconductor device to be stably bonded to the conductive metal portion and / or the bonding portion. Therefore, the embodiment can improve the operating characteristics of the semiconductor device and the product including the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Figure 1a is a cross-sectional view showing a semiconductor package according to a first embodiment.

[0069] Figure 1b is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0070] Figure 1c is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0071] Figure 1d is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0072] Figure 1e is a cross-sectional view showing a semiconductor package according to the fifth embodiment.

[0073] Figure 1f is a cross-sectional view showing a semiconductor package according to the sixth embodiment.

[0074] Figure 1g is a cross-sectional view showing a semiconductor package according to the seventh embodiment.

[0075] Figure 2 is a cross-sectional view showing a circuit board according to the first embodiment.

[0076] Figure 3 is provided on Figure 2 a plan view of a first electrode on the uppermost side of a first insulating layer.

[0077] Figure 4 and Figure 5 is a magnified view showing a part of a region of a circuit board provided in Figure 2 the circuit board.

[0078] Figure 6 is a magnified view showing Figure 2 a first modified example of the circuit board.

[0079] Figure 7 is a magnified view showing Figure 2 a second modified example of the circuit board.

[0080] Figure 8 is a magnified view showing Figure 2 a third modified example of the circuit board.

[0081] Figure 9 is a magnified view showing Figure 2 a fourth modified example of the circuit board.

[0082] Figure 10 is a magnified view showing Figure 2 a fifth modified example of the circuit board.

[0083] Figure 11 is a magnified view showing Figure 2 a sixth modified example of the circuit board.

[0084] Figures 12 to 23 shows in process sequenceFigure 2 Cross-sectional view of the manufacturing method of the circuit board shown.

[0085] Figure 24 It is a cross-sectional view showing the circuit board according to the second embodiment.

[0086] Figure 25 It shows the setting in accordance with Figure 24 Optical micrograph of the interface of the insulating layer in the circuit board of the embodiment.

[0087] Figure 26 It shows the state before arranging the conductive metal part in the Figure 24 area. Cross-sectional view.

[0088] Figure 27 It shows the state after arranging the conductive metal part in the Figure 26 . Diagram.

[0089] Figure 28 It shows the Figure 24 detailed layer structure of the lower wiring electrode in the circuit board. Diagram.

[0090] Figure 29 It is a cross-sectional view showing the circuit board according to the third embodiment.

[0091] Figure 30 It is a cross-sectional view showing the circuit board according to the fourth embodiment.

[0092] Figure 31 It is a cross-sectional view showing the circuit board according to the fifth embodiment. Detailed Description of the Invention

[0093] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0094] However, the spirit and scope of the present disclosure are not limited to a part of the described embodiments, and can be implemented in various other forms, and within the spirit and scope of the present disclosure, one or more elements of the embodiments can be selectively combined and rearranged.

[0095] In addition, unless otherwise clearly defined and described, the terms (including technical terms and scientific terms) used in the embodiments of the present disclosure can be interpreted as having the same meaning as that generally understood by those of ordinary skill in the art to which the present disclosure pertains, and terms such as those defined in a common dictionary can be interpreted as having a meaning consistent with their meaning in the context of the relevant field. In addition, the terms used in the embodiments of the present disclosure are used to describe the embodiments and are not intended to limit the present disclosure.

[0096] In this specification, the singular forms may also include the plural forms unless specifically recited in a phrase, and when described as "at least one (or more) of A, B, and C", it may include at least one of all combinations that can be combined in A, B, and C. Additionally, when describing the elements of embodiments of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used.

[0097] These terms are only used to distinguish an element from other elements, and these terms do not limit the nature, order, or sequence of the element. Additionally, when an element is described as "connected", "coupled", or "contacted" to another element, it may include not only that the element is directly "connected", "coupled", or "contacted" to the other element, but also that the element is "connected", "coupled", or "contacted" to the other element through another element between the element and the other element.

[0098] Additionally, when described as being "on (above)" or "under (below)" each element, "on (above)" or "under (below)" may include not only that the two elements are directly connected to each other, but also that one or more other elements are formed or disposed between the two elements. Additionally, when expressed as "on (above)..." or "under (below)...", it may include not only the upper direction based on one element, but also the lower direction.

[0099] -Electronic device-

[0100] Before describing the embodiments, the electronic device to which the embodiments are applied, a semiconductor package, will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiment. Various semiconductor devices may be mounted on the semiconductor package.

[0101] The semiconductor devices may include active devices and / or passive devices. The active devices may be semiconductor chips in the form of integrated circuits (ICs), in which hundreds to millions of devices are integrated into one semiconductor chip. The semiconductor devices may be logic chips, memory chips, etc. The logic chips may be central processing units (CPUs), graphics processing units (GPUs), etc. For example, the logic chip may be an application processor (AP) chip including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an ASIC (application-specific IC), etc., or a chipset including a specific combination of those listed so far.

[0102] The memory chip can be a stacked memory such as HBM. The memory chip can also include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), or flash memory.

[0103] On the other hand, the product group of the semiconductor package applying the embodiment can be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0104] In addition, the electronic device can be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an Automotive, etc. However, the embodiment is not limited thereto and can be any other electronic device that processes data other than these.

[0105] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package of the embodiment can have various package structures including the circuit board described later.

[0106] Figure 1a is a cross-sectional view showing a semiconductor package according to a first embodiment, Figure 1b is a cross-sectional view showing a semiconductor package according to a second embodiment, Figure 1c is a cross-sectional view showing a semiconductor package according to a third embodiment, Figure 1d is a cross-sectional view showing a semiconductor package according to a fourth embodiment, Figure 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment, Figure 1f is a cross-sectional view showing a semiconductor package according to a sixth embodiment, Figure 1g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0107] ReferenceFigure 1a , according to the first embodiment, the semiconductor package may include a first circuit board 10, a second circuit board 20, and a semiconductor device 30.

[0108] The first circuit board 10 represents the semiconductor package substrate.

[0109] For example, the first circuit board 10 may provide a space for coupling to at least one external circuit board. The external circuit board may refer to the second circuit board 20 coupled to the first circuit board 10. In addition, the external circuit board may refer to the main board in an electronic device included in the lower part coupled to the first circuit board 10.

[0110] In addition, although not shown in the figure, the first circuit board 10 may provide a space for mounting at least one semiconductor device.

[0111] The first circuit board 10 includes at least one insulating layer, a circuit pattern layer provided on the at least one insulating layer, and a through electrode passing through the at least one insulating layer.

[0112] The second circuit board 20 is disposed on the first circuit board 10.

[0113] The second circuit board 20 may be an interposer. For example, the second circuit board 20 may provide a space for mounting at least one semiconductor device. The second circuit board 20 may be connected to at least one semiconductor device 30. For example, the second circuit board 20 may provide a space for mounting a first semiconductor device 31 and a second semiconductor device 32. The second circuit board 20 may electrically connect the first semiconductor device 31, the second semiconductor device 32, and the first circuit board 10, while electrically connecting the first semiconductor device 31 and the second semiconductor device 32. That is, the second circuit board 20 may perform a horizontal connection function between multiple semiconductor devices and a vertical connection function between a semiconductor device and a package circuit substrate.

[0114] Figure 1a The first semiconductor device 31 and the second semiconductor device 32 are shown disposed on the second circuit board 20, but are not limited thereto. For example, one semiconductor device may be disposed on the second circuit board 20, or alternatively, three or more semiconductor devices may be disposed.

[0115] The second circuit board 20 may be disposed between at least one semiconductor device 30 and the first circuit board 10.

[0116] In one embodiment, the second circuit board 20 may be an active interposer used as a semiconductor device. When the second circuit board 20 is used as a semiconductor device, the semiconductor package of the embodiment may have a structure vertically stacked on the first circuit board 10 and may have the functions of multiple logic chips. Having the functions of a logic chip may mean that it can have the functions of active devices and passive devices. In the case of active devices, different from passive devices, the characteristics of current and voltage may not be linear. In the case of an active interposer, it can have the functions of active devices. In addition, the active interposer can execute the functions of the corresponding logic chip while executing the signal transmission function between the second logic chip disposed thereon and the first circuit board 10.

[0117] According to another embodiment, the second circuit board 20 may be a passive interposer. For example, the second circuit board 20 may be used as a signal relay between the semiconductor device 30 and the first circuit board 10 and may have the functions of passive devices such as resistors, capacitors, or inductors. For example, due to 5G, the Internet of Things (IoT), the improvement of image quality, and the increase in communication speed, the number of terminals of the semiconductor device 30 has gradually increased. That is, the number of terminals provided in the semiconductor device 30 increases, thereby reducing the width of the terminals or the interval between multiple terminals. In this case, the first circuit board 10 is connected to the main board of the electronic device. The problem is that in order to make the electrodes provided on the first circuit board 10 have a certain width and interval to be respectively connected to the semiconductor device 30 and the main board, the thickness of the first circuit board 10 increases or the layer structure of the first circuit board 10 becomes complicated. Therefore, in the first embodiment, the second circuit board 20 may be disposed between the first circuit board 10 and the semiconductor device 30. In addition, the second circuit board 20 may include electrodes having a fine width and interval corresponding to the terminals of the semiconductor device 30.

[0118] The semiconductor package includes a first coupling member 41 located between the first circuit board 10 and the second circuit board 20. The first coupling member 41 electrically connects the first circuit board 10 and the second circuit board 20 while bonding the second circuit board 20 to the first circuit board 10.

[0119] The semiconductor package may include a second coupling member 42 disposed between the second circuit board 20 and the semiconductor device 30. The second coupling member 42 can electrically connect the semiconductor device 30 and the second circuit board 20 while bonding the semiconductor device 30 to the second circuit board 20.

[0120] The semiconductor package includes a third coupling member 43 disposed on the lower surface of the first circuit board 10. The third coupling member 43 can electrically connect the first circuit board 10 and the main board while bonding the first circuit board 10 to the main board.

[0121] At this time, the first coupling member 41, the second coupling member 42, and the third coupling member 43 can be electrically connected between multiple components by using at least one of bonding methods such as wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first coupling member 41, the second coupling member 42, and the third coupling member 43 have the function of electrically connecting multiple components, when direct metal-to-metal bonding is used, the connection part of the semiconductor package can be understood as an electrical connection part rather than solder or a lead.

[0122] The wire bonding method can refer to electrically connecting multiple components by using a conductive wire such as gold (Au). In addition, the solder bonding method can use a material containing at least one of Sn, Ag, and Cu to electrically connect multiple components. Additionally, the direct metal-to-metal bonding method can refer to recrystallization by applying heat and pressure between multiple components in the absence of solder, leads, conductive adhesives, etc., and can also refer to directly bonding between multiple components. Additionally, the direct metal-to-metal bonding method can refer to the bonding method through the second coupling member 42. In this case, the second coupling member 42 can represent a metal layer formed between multiple components by recrystallization.

[0123] Specifically, the first coupling member 41, the second coupling member 42, and the third coupling member 43 can couple multiple components to each other by a TC (Thermal Compression) bonding method. The TC bonding can refer to a method of directly bonding multiple components by applying heat and pressure to the first coupling member 41, the second coupling member 42, and the third coupling member 43.

[0124] In this case, at least one of the first circuit board 10 and the second circuit board 20 can include a bonding part provided in the electrode, on which the first coupling member 41, the second coupling member 42, and the third coupling member 43 are provided. The bonding part can protrude outward from the first circuit board 10 or the second circuit board 20.

[0125] The bonding portion may be referred to as a bump or a post or a pillar. Preferably, the bonding portion may refer to an electrode among the electrodes of the second circuit board 20 on which a second coupling member 42 for bonding to the semiconductor device 30 is provided. That is, as the pitch of the terminals of the semiconductor device 30 becomes finer, a short circuit may occur between the plurality of second coupling members 42 respectively connected to the plurality of terminals of the semiconductor device 30 through a conductive adhesive such as solder. Therefore, in an embodiment, thermocompression bonding may be performed to reduce the volume of the second coupling member 42, and in order to ensure diffusion prevention and alignment for preventing the intermetallic compound IMC (Inter Metallic Compound) formed between the conductive adhesive such as solder and the bonding portion from diffusing into the interposer and / or the circuit board, the bonding portion may be included in the electrode of the second circuit board 20 on which the second coupling member 42 is provided.

[0126] Reference Figure 1b , the semiconductor package of the second embodiment is different from the semiconductor package of the first embodiment in that the coupling member 21 is provided on the second circuit board 20. Recently, the number of signals that a semiconductor device has to process is increasing, and thus, the size of the semiconductor device is becoming larger. In addition, such a large-area semiconductor device becomes a problem of reducing the yield of the semiconductor device. Therefore, there is a trend to divide the pattern size or functional part of the semiconductor device, arrange small chips on the circuit board, and bury the connection member 21 having the function of electrically connecting the divided small chips into the circuit board. However, the connection member 21 is not limited thereto, and may also connect semiconductor devices having other functions such as memories. For example, the connection member 21 may include a redistribution layer. The connection member 21 may perform a function of horizontally electrically connecting a plurality of semiconductor devices to each other. For example, since the area of the semiconductor device is generally too large, the connection member 21 may include a redistribution layer. Since the semiconductor package and the semiconductor device are quite different in terms of the width or pitch of the circuit pattern, etc., a buffering effect of the circuit pattern is required for electrical connection. The buffering effect may mean that the size is between the width or interval of the circuit pattern of the semiconductor package and the width or interval of the circuit pattern of the semiconductor device, and the redistribution layer may include a function of performing the buffering effect.

[0127] In one embodiment, the connection member 21 may include a silicon material and include a silicon circuit board and a redistribution layer provided on the silicon circuit board.

[0128] In another embodiment, the connection member 21 may include an organic material. For example, instead of the silicon circuit board, the connection member 21 includes an organic circuit board containing an organic material.

[0129] The connecting member 21 can be embedded in the second circuit board 20, but is not limited thereto. For example, the connecting member 21 can be disposed on the second circuit board 20 to have a protruding structure. Additionally, the second circuit board 20 can include a cavity, and the connecting member 21 can be disposed in the cavity of the second circuit board 20. The connecting member 21 can horizontally connect a plurality of semiconductor devices disposed on the second circuit board 20.

[0130] Reference Figure 1c , the semiconductor package according to the third embodiment can include a second circuit board 20 and a semiconductor device 30. In this case, compared with the semiconductor package of the second embodiment, the semiconductor package of the third embodiment has a structure in which the first circuit board 10 is removed.

[0131] That is, the second circuit board 20 of the third embodiment can serve as a package substrate while performing the interposer function.

[0132] The first coupling member 41 disposed on the lower surface of the second circuit board 20 can couple the second circuit board 20 to the main board of the electronic device.

[0133] Reference Figure 1d , the semiconductor package according to the fourth embodiment can include a first circuit board 10 and a semiconductor device 30.

[0134] In this case, compared with the semiconductor package of the second embodiment, the semiconductor package of the fourth embodiment has a structure in which the second circuit board 20 is removed.

[0135] That is, the first circuit board 10 of the fourth embodiment can serve as a package circuit board while also performing the function of connecting the semiconductor device 30 and the main board. To this end, the first circuit board 10 can include a connecting member 11 for connecting a plurality of semiconductor devices. The connecting member 11 can be a silicon bridge or an organic material bridge connecting a plurality of semiconductor devices.

[0136] Reference Figure 1e , compared with the semiconductor package of the fourth embodiment, the semiconductor package of the fifth embodiment further includes a third semiconductor device 33.

[0137] To this end, a fourth coupling member 44 can be disposed on the lower surface of the first circuit board 10. Additionally, the third semiconductor device 33 can be disposed on the fourth coupling member 44. That is, the semiconductor package of the fifth embodiment can have a structure in which semiconductor devices are respectively mounted on the upper side and the lower side.

[0138] In this case, the third semiconductor device 33 can have a structure disposed on Figure 1c the lower surface of the second circuit board 20 in the semiconductor package.

[0139] Reference Figure 1f, the semiconductor package according to the sixth embodiment includes a first circuit board 10.

[0140] A first semiconductor device 31 may be disposed on the first circuit board 10. To this end, a first coupling member 41 may be disposed between the first circuit board 10 and the first semiconductor device 31.

[0141] In addition, the first circuit board 10 includes a conductive bonding portion 45. The conductive bonding portion 45 may also protrude from the first circuit board 10 toward the second semiconductor device 32. The conductive bonding portion 45 may be referred to as a bump, or alternatively, may also be referred to as a column. The conductive bonding portion 45 may be configured to have a structure that protrudes from an electrode disposed on the uppermost side of the first circuit board 10.

[0142] A second semiconductor device 32 may be disposed on the conductive bonding portion 45. In this case, the second semiconductor device 32 may be connected to the first circuit board 10 through the conductive bonding portion 45. In addition, a second coupling member 42 may be disposed between the first semiconductor device 31 and the second semiconductor device 32.

[0143] Therefore, the second semiconductor device 32 may be electrically connected to the first semiconductor device 31 through the second coupling member 42.

[0144] That is, the second semiconductor device 32 may be connected to the first circuit board 10 through the conductive bonding portion 45, and may also be connected to the first semiconductor device 31 through the second coupling member 42.

[0145] In this case, the second semiconductor device 32 may receive a power signal and / or electric power through the conductive bonding portion 45. In addition, the second semiconductor device 32 may transmit a communication signal to the first semiconductor device 31 and receive a communication signal from the first semiconductor device 31 through the second coupling member 42.

[0146] The semiconductor package according to the sixth embodiment provides a power signal and / or electric power to the second semiconductor device 32 through the conductive bonding portion 45, thereby providing sufficient power to drive the second semiconductor device 32 or allowing smooth control of the power operation.

[0147] Therefore, the embodiment can improve the driving characteristics of the second semiconductor device 32. That is, the embodiment can solve the problem of insufficient power supplied to the second semiconductor device 32. In addition, in the embodiment, at least one of the power signal, electric power, and communication signal of the second semiconductor device 32 is provided by different paths passing through the conductive bonding portion 45 and the second coupling member 42. Thus, the embodiment can solve the problem of loss of the communication signal due to the power signal. For example, the embodiment can minimize the mutual interference between the communication signal and the power signal.

[0148] Meanwhile, the second semiconductor device 32 in the sixth embodiment may have a POP (Package On Package) structure in which a plurality of package substrates are stacked, and may be disposed on the first circuit board 10. For example, the second semiconductor device 32 may be a memory package including memory chips. Additionally, the memory package may be coupled to the conductive bonding portion 45. In this case, the memory package may not be connected to the first semiconductor device 31.

[0149] Meanwhile, the semiconductor package in the sixth embodiment may include a molding member 46. The molding member 46 may be disposed between the first circuit board 10 and the second semiconductor device 32. For example, the molding member 46 may mold the first coupling member 41, the second coupling member 42, the first semiconductor device 31, and the conductive bonding portion 45.

[0150] Reference Figure 1g , the semiconductor package according to the seventh embodiment may include a first circuit board 10, a first coupling member 41, a semiconductor device 30, and a third coupling member 43. In this case, the semiconductor package of the seventh embodiment is different from the semiconductor package of the fourth embodiment in that the first circuit board 10 includes a plurality of circuit board layers, and the connection member 11 is removed.

[0151] The first circuit board 10 includes a plurality of circuit board layers. For example, the first circuit board 10 may include a first circuit board layer 10A corresponding to a package substrate and a second circuit board layer 10B corresponding to a redistribution layer of the connection member.

[0152] That is, the semiconductor package of the seventh embodiment may include a first circuit board layer 10A and a second circuit board layer 10B, where Figure 1a the first circuit board (package circuit board 10) and the second circuit board (interposer 20) shown in are integrally formed. The material of the insulating layer of the second circuit board layer 10B may be different from the material of the insulating layer of the first circuit board layer 10A. For example, the material of the insulating layer of the second circuit board layer 10B may include a photo-curable material. For example, the second circuit board layer 10B may be a PID (photoimageable dielectric). Additionally, since the second circuit board layer 10B includes a photo-curable material, the electrodes can be miniaturized. Therefore, in the seventh embodiment, the second circuit board layer 10B can be formed by sequentially stacking an insulating layer of a photo-curable material on the first circuit board layer 10A and forming miniaturized electrodes on the insulating layer of the photo-curable material. Therefore, the second circuit board layer 10B may include a redistribution layer function including microelectrodes, and may include a function of horizontally connecting a plurality of semiconductor devices 31 and 32.

[0153] Hereinafter, the circuit boards of the embodiments will be described.

[0154] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, regardless of the reference numerals, the same or corresponding components are assigned the same reference numerals, and redundant descriptions thereof will be omitted.

[0155] Figure 2 is a cross-sectional view showing a circuit board according to a first embodiment, Figure 3 is provided on Figure 2 a plan view of a first electrode provided on the uppermost side of a first insulating layer of Figure 4 and Figure 5 is a magnified view showing a part of a region of the circuit board provided in Figure 2 Figure 6 is a magnified view showing Figure 2 a first modified example of the circuit board of Figure 7 is a magnified view showing Figure 2 a second modified example of the circuit board of Figure 8 is a magnified view showing Figure 2 a third modified example of the circuit board of Figure 9 is a magnified view showing Figure 2 a fourth modified example of the circuit board of Figure 10 is a magnified view showing Figure 2 a fifth modified example of the circuit board of Figure 11 is a magnified view showing Figure 2 a sixth modified example of the circuit board of

[0156] Hereinafter, the circuit board of the embodiment will be specifically described with reference to Figures 2 to 11

[0157] Referring to Figure 2 , the circuit board 100 may include an insulating substrate 110. Specifically, the insulating substrate 110 may refer to a layer including an insulating material among the components of the circuit board 100, and may include, for example, an insulating layer 111, a first protective layer 112, and a second protective layer 113.

[0158] The insulating layer 111 may be provided for interlayer insulation of the wiring electrode 120 and the via electrode 130. The first protective layer 112 may be an upper protective layer provided on the insulating layer 111, and the second protective layer 113 may be a lower protective layer provided below the insulating layer 111. The first protective layer 112 and the second protective layer 113 may include materials different from those of the insulating layer 111, and may include, for example, a solder resist.

[0159] The insulating layer 111 may have a structure in which multiple layers are stacked in the vertical direction. For example, as Figure 2 ​​As shown, based on the number of layers of the insulating layer 111, the circuit board 100 may have a double-layer structure, but is not limited thereto. Based on the number of layers of the insulating layer 111, the circuit board 100 of one embodiment may have less than two layers. Based on the number of layers of the insulating layer 111, the circuit board 100 of another embodiment may have three or more layers. Preferably, based on the number of layers of the insulating layer 111, the circuit board 100 of the embodiment may have five or more, or seven or more, or nine or more layers.

[0160] When the insulating layer 111 has a multi-layer structure, the plurality of insulating layers 111 may include the same insulating material, but is not limited thereto. For example, at least one of the plurality of insulating layers 111 may include an insulating material different from that of at least another of the plurality of insulating layers 111.

[0161] The insulating layer 111 is provided for vertical insulation between wiring electrodes, which will be described later. For example, a thermosetting insulating material containing inorganic fillers in a resin may be used as the insulating layer 111. As an example, ABF (Ajinomoto Build-up Film) of Ajinomoto Co., Inc. may be used. However, the embodiment is not limited thereto, and a photo-curable insulating material PID (Photo Imageable Dielectric) for forming a fine pattern may be used.

[0162] The first protective layer 112 may be provided on the upper surface of the insulating layer 111, and the second protective layer 113 may be provided on the lower surface of the insulating layer 111.

[0163] The first protective layer 112 may protect the wiring electrodes 120 and / or the upper surface of the insulating layer 111 described later from external moisture or contaminants. In addition, when a semiconductor device is provided on the circuit board 100 using a material such as solder, the first protective layer 112 serves to prevent short circuits between the solders due to the low wettability of the solder. The first protective layer 112 may use a photo-curable insulating material. For example, a solder resist may be used. However, the embodiment is not limited thereto, and the first protective layer 112 may include a thermo-curable insulating material that is the same insulating material as the insulating layer 111. The first protective layer 112 may include the same insulating material as the insulating layer 111. For example, it may be set as ABF (Ajinomoto Build-up Film) of Ajinomoto Co., Inc.

[0164] The circuit board 100 may include an electrode portion 150.

[0165] The electrode portion 150 may be disposed on the insulating substrate 110. For example, the electrode portion 150 may penetrate the insulating substrate 110. For example, a part of the electrode portion 150 may be disposed in the insulating substrate 110, and the remaining part of the electrode portion 150 may protrude above or below the surface of the insulating substrate 110.

[0166] The electrode portion 150 may include a plurality of electrodes according to the position or function.

[0167] For example, the electrode portion 150 may include a wiring electrode 120 and a via electrode 130. The wiring electrode 120 may be disposed on the surface of the insulating layer 111. For example, the wiring electrode 120 may be disposed on the upper surface and / or the lower surface of the insulating layer 111. For example, when the insulating layer 111 includes a first insulating layer and a second insulating layer, the wiring electrode 120 may include a first wiring layer disposed on the upper surface of the first insulating layer, a second wiring layer disposed between the first insulating layer and the second insulating layer, and a third wiring layer disposed on the lower surface of the second insulating layer.

[0168] The via electrode 130 may be connected between the wiring electrodes 120 disposed in different layers along the vertical direction of the circuit board 100. For example, when the insulating layer 111 has a three-layer structure, the via electrodes 130 may be spaced apart from each other in the vertical direction and may be disposed in each of the three layers of the insulating layer 111.

[0169] Any one of the plurality of wiring electrodes 120 disposed in different layers may have an ETS (Embedded Trace Substrate) structure. For example, the wiring electrode 120 disposed on the uppermost side of the circuit board 100 may have an ETS structure. Here, the meaning that the wiring electrode 120 has an ETS structure may mean that at least a part of the wiring electrode 120 disposed on the uppermost side has an embedded structure embedded in the insulating layer 111. That is, the embedded structure may mean that at least a part of the wiring electrode 120 overlaps the insulating layer 111 in the horizontal direction. For example, the embedded structure may mean that the lower surface and / or the upper surface of the wiring electrode 120 is positioned closer to the lower surface of the insulating layer 111 than the upper surface of the insulating layer 111. In addition, the embedded structure may mean that the lower surface and / or the upper surface of the wiring electrode 120 is positioned closer to the lower surface of the second protective layer 113 located below the insulating layer 111 than the upper surface of the insulating layer 111.

[0170] Compared with the wiring electrode having a general protruding structure, the ETS structure is beneficial to miniaturization. Therefore, the embodiment can form a wiring electrode corresponding to the size and pitch of the terminals provided in the semiconductor device. Thus, the embodiment can improve the circuit integration degree. In addition, the embodiment can minimize the transmission distance of the signal transmitted through the semiconductor device, thereby minimizing the signal transmission loss.

[0171] The wiring electrode 120 may include a pad portion 120P and a connection circuit pattern portion 120T according to position and / or function.

[0172] The pad portion 120P may represent a wiring electrode among the wiring electrodes 120 provided on the uppermost side of the circuit board 100 that vertically overlaps the bonding portion 140. For example, the pad portion 120P may represent a wiring electrode that directly contacts the bonding portion 140.

[0173] The connection circuit pattern portion 120T may represent the remaining electrodes among the wiring electrodes 120 other than the pad portion 120P. For example, the connection circuit pattern portion 120T may represent an electrode electrically connected between a plurality of pad portions 120P. For example, the connection circuit pattern portion 120T may represent a trace connected between a plurality of pad portions 120P.

[0174] The pad portion 120P may be divided into a plurality of parts. For example, the pad portion 120P may include a first part 121 that overlaps the connection circuit pattern portion 120T in the horizontal direction. The first part 121 of the pad portion 120P may be embedded in the insulating layer 111. For example, the side surface of the first part 121 of the pad portion 120P may be covered by the insulating layer 111. The pad portion 120P may include a second part 122 provided on the first part 121. The second part 122 of the pad portion 120P may refer to the part provided on the insulating layer 111 in the entire area of the pad portion 120P.

[0175] At this time, the first part 121 and the second part 122 of the pad portion 120P may be formed by a plurality of separate processes. For example, the second part 122 of the pad portion 120P may be a copper layer. For example, the second part 122 of the pad portion 120P may be a seed layer for electroplating the first part 121 of the pad portion 120P and the connection circuit pattern portion 120T. That is, the first part 121 of the pad portion 120P and the connection circuit pattern portion 120T may be electroplated layers formed by using the second part 122 of the pad portion 120P as a seed layer.

[0176] At this time, the conventional circuit board completely removes the copper layer used as the seed layer. Therefore, the thickness of the bonding portion provided on the electrode of the conventional circuit board may increase. Therefore, the conventional circuit board may have a height difference between a plurality of bonding portions horizontally spaced apart from each other. Therefore, when bonding a semiconductor device to the bonding portion, due to the height difference of the bonding portion, the conventional circuit board may not be able to stably place the semiconductor device on the bonding portion, and the semiconductor device may be bonded in an inclined state in a specific direction.

[0177] In contrast, in an embodiment, a part of the copper layer used as a seed layer in a region where the bonding portion 140 is to be provided may not be removed. Additionally, the non-removed part of the copper layer may form a second part 122 of the pad portion 120P. The upper surface of the second part 122 of the pad portion 120P may represent the upper surface of the copper layer that is first provided on the carrier member during the manufacturing process of the circuit board. Thus, the upper surface of the second part 122 of the pad portion 120P may be flat. Moreover, the upper surfaces of the second parts 122 of the plurality of pad portions 120P may be located on the same plane. Accordingly, in an embodiment, a plurality of bonding portions 140 having a uniform thickness may be formed by disposing the bonding portions 140 on the second parts 122 of the pad portions 120P. Further, in an embodiment, the thickness of the bonding portion 140 may be reduced by the thickness of the second part 122 of the pad portion 120P. Thus, in an embodiment, the problem that the thickness deviation increases in proportion to the thickness of the bonding portion 140 may be solved. Therefore, in an embodiment, the height deviation between the plurality of bonding portions 140 may be minimized. Accordingly, in an embodiment, the semiconductor device may be stably disposed on the plurality of bonding portions 140. Additionally, compared to the thickness of a conventional bonding portion, in an embodiment, the thickness of the bonding portion 140 may be increased by the thickness of the second part 122 of the pad portion 120P. Thus, in an embodiment, the height of the bonding portion that allows for stable bonding of the semiconductor device may be ensured, and accordingly, the overall physical and / or electrical characteristics of the semiconductor package may be improved. Therefore, the semiconductor device may be operated smoothly, and further, a server or an electronic product may be operated smoothly.

[0178] The first part 121 and the second part 122 of the pad portion 120P may include the same metal material. Thus, the interface between the first part 121 and the second part 122 of the pad portion 120P may be difficult to distinguish. Accordingly, the first part 121 and the second part 122 of the pad portion 120P may have a structure integrally formed with each other. However, the embodiment is not limited thereto. When the interface between the first part 121 and the second part 122 of the pad portion 120P can be distinguished, the pad portion 120P may have a two-layer structure including the first part 121 and the second part 122.

[0179] The pad portion 120P may include a region where the width varies in the vertical direction. The pad portion 120P may include a region where the width increases from the upper surface toward the lower surface. Specifically, the first portion 121 and the second portion 122 of the pad portion 120P may have different vertical cross-sectional shapes. The first portion 121 of the pad portion 120P may be formed by an electrolytic plating process. Additionally, the second portion 122 of the pad portion 120P may be formed by an etching process. For example, the second portion 122 of the pad portion 120P may be formed by a dry etching and / or a wet etching process. The interface between the first portion 121 and the second portion 122 of the pad portion 120P may be difficult to distinguish, but it can be distinguished based on the shape of the side surface of the pad portion 120P. For example, the pad portion 120P may include a side surface 122S formed by etching, and the side surface 122S has a curvature and / or a slope in the vertical direction. Additionally, the side surface 122S having a curvature may be provided in the second portion 122. Additionally, the side surface of the first portion 121 may not have a curvature. Thus, the embodiment can distinguish the first portion 121 and the second portion 122 of the pad portion 120P by the side surface 122S having a curvature. Here, having a curvature may mean having a slope where the width varies in the vertical direction (e.g., increases or decreases), and not having a curvature may mean that the width hardly changes in the vertical direction.

[0180] The pad portion 120P may include a first side surface adjacent to the lower surface and having a first inclination. The first side surface may represent the side surface of the first portion 121 of the pad portion 120P. The first inclination of the first side surface may be perpendicular to the upper surface of the pad portion 120P. For example, the inner angle between the first side surface of the pad portion 120P and the upper surface may be in the range of 85 degrees to 95 degrees. Additionally, the pad portion 120P may include a second side surface 122S adjacent to the upper surface and having a second inclination different from the first inclination. The second side surface may refer to the side surface 122S of the second portion 122 of the pad portion 120P. The second side surface 122S may be a curved surface having a specific curvature and / or a slope in the vertical direction. The second side surface 122S may have a curvature corresponding to the etching process conditions of the copper layer for electroplating the first portion 121 of the pad portion 120P. The pad portion 120P may have a width different from that of the connection circuit pattern portion 120T. The width may refer to the horizontal distance in the horizontal direction perpendicular to the vertical direction of the circuit board 100. Preferably, the width of the pad portion 120P may refer to the horizontal distance in the region of the pad portion 120P where the width is the largest in the entire region in the vertical direction. Additionally, the width of the connection circuit pattern portion 120T may represent the horizontal distance in the horizontal direction in the region of the connection circuit pattern portion 120T where the width is the largest in the entire region in the vertical direction of the connection circuit pattern portion 120T.

[0181] The width of the pad portion 120P can represent the width of the first part 121 of the pad portion 120P. For example, the width of the pad portion 120P can represent the width of the lower surface of the pad portion 120P.

[0182] In addition, the planar shape of the pad portion 120P can be circular. In another embodiment, the planar shape of the pad portion 120P can be oval. Additionally, when the planar shape of the pad portion 120P is circular, the width of the pad portion 120P can represent the diameter of the pad portion 120P. Additionally, when the planar shape of the pad portion 120P is oval, the width of the pad portion 120P can represent the diameter in the major axis direction of the pad portion 120P.

[0183] Reference Figure 3 , the width W1 of the pad portion 120P can have a range of 40 μm to 70 μm. Preferably, the width W1 of the pad portion 120P can have a range of 42 μm to 68 μm. More preferably, the width W1 of the pad portion 120P can have a range of 45 μm to 65 μm. If the width W1 of the pad portion 120P is less than 40 μm, the electrical connectivity with the chip mounted on the circuit board may deteriorate. If the width W1 of the pad portion 120P is less than 40 μm, the allowable current of the signal transmitted through the pad portion 120P may be reduced. Additionally, when the allowable current is reduced, the signal transmission characteristics may deteriorate. If the width W1 of the pad portion 120P exceeds 70 μm, it may be difficult to place all the pad portions connected to the respective terminals of the semiconductor device within a limited space. If the width W1 of the pad portion 120P exceeds 70 μm, the volume of the circuit board and the volume of the semiconductor package may increase.

[0184] Meanwhile, the width W2 of the connection circuit pattern portion 120T can have a range of 2 μm to 20 μm. Preferably, the width W2 of the connection circuit pattern portion 120T can have a range of 2.2 μm to 18 μm. More preferably, the width W2 of the connection circuit pattern portion 120T can have a range of 2.5 μm to 15 μm.

[0185] If the width W2 of the connection circuit pattern portion 120T is less than 2 μm, the signal resistance of the connection circuit pattern portion 120T increases, so it may be difficult to communicate normally with the chip provided on the circuit board. In addition, if the width W2 of the connection circuit pattern portion 120T is less than 2 μm, not only is it difficult to achieve, but there may be a reliability problem that the connection circuit pattern portion 120T is prone to collapse during the manufacturing process. In addition, if the width W2 of the connection circuit pattern portion 120T exceeds 20 μm, it may be difficult to place all the connection circuit pattern portions 120T connected to the pad portion 120P in a limited space. If the width W2 of the connection circuit pattern portion 120T exceeds 20 μm, the volume of the circuit board and the semiconductor package may increase, so it may be difficult to thin them.

[0186] The electrode portion 150 may include a bonding portion 140. The bonding portion 140 may be provided on the wiring electrode 120. Preferably, the bonding portion 140 may be provided on the pad portion 120P of the wiring electrode 120.

[0187] The bonding portion 140 may include a conductive metal portion 141 provided on the pad portion 120P and a coupling portion 142 provided on the conductive metal portion 141.

[0188] The conductive metal portion 141 may be provided on the pad portion 120P. The conductive metal portion 141 may be provided on the second portion 122 of the pad portion 120P. The conductive metal portion 141 may include a metal material different from the metal material constituting the pad portion 120P. For example, the conductive metal portion 141 may include a second metal material capable of selective etching with the first metal material constituting the pad portion 120P. In this case, the meaning that the first metal material and the second metal material can be selectively etched may mean that when an etching process is performed with an etching solution capable of etching the first metal material, the second metal material is not etched.

[0189] Reference Figure 4, the width of the conductive metal portion 141 may be greater than the width W3 of the upper surface of the pad portion 120P. The width of the conductive metal portion 141 may represent the horizontal distance from the left end to the right end of the conductive metal portion 141. The width of the conductive metal portion 141 may represent the length of the upper surface of the conductive metal portion 141. The width of the conductive metal portion 141 may be in the range of 110% to 180% of the width W3 of the upper surface of the pad portion 120P. Preferably, the width of the conductive metal portion 141 may be in the range of 112% to 170% of the width W3 of the upper surface of the pad portion 120P. More preferably, the width of the conductive metal portion 141 may be in the range of 115% to 150% of the width W3 of the upper surface of the pad portion 120P. If the width of the conductive metal portion 141 is less than 110% of the width W3 of the upper surface of the pad portion 120P, the processability during the formation of the second portion 122 of the pad portion 120P by an etching process may deteriorate. For example, if the width of the conductive metal portion 141 is less than 110% of the width W3 of the upper surface of the pad portion 120P, the pad portion 120P may not have a constant thickness, and thus the effects achieved by the structure of the embodiment may be insufficient. For example, if the width of the conductive metal portion 141 is less than 110% of the width W3 of the upper surface of the pad portion 120P, the width W3 of the upper surface of the pad portion 120P may become too small. Additionally, if the width W3 of the upper surface of the pad portion 120P becomes too small, the vertical cross-section of the second portion 122 of the pad portion 120P may have a shape close to a triangle, and thus the coupling portion 142 of the joint portion 140 may not be stably disposed on the pad portion 120P. Additionally, if the width of the conductive metal portion 141 exceeds 180% of the width W3 of the upper surface of the pad portion 120P, the width of the region in the entire area of the conductive metal portion 141 that does not vertically overlap with the upper surface of the pad portion 120P may increase. Additionally, when the width of the region of the conductive metal portion 141 that does not vertically overlap with the upper surface of the pad portion 120P increases, the conductive metal portion 141 may contact the connection circuit pattern portion 120T or another pad portion adjacent to the pad portion 120P, thereby causing an electrical short circuit problem. Additionally, when the width of the conductive metal portion 141 exceeds 180% of the width W3 of the upper surface of the pad portion 120P, there may be a problem that a partial region of the second portion 122 of the pad portion 120P that does not vertically overlap with the first portion 121 of the pad portion 120P is not etched and removed. As a result, since at least a part of the second portion 122 is not etched, an electrical connection is caused between the adjacent pad portion 120P and the connection circuit pattern portion 120T or between a plurality of adjacent pad portions, and thus an electrical short circuit problem may occur.

[0190] The conductive metal part 141 may be divided into multiple parts. The conductive metal part 141 may include a contact part 141-1 that contacts the upper surface of the pad part 120P. The contact part 141-1 of the conductive metal part 141 may vertically overlap the upper surface of the pad part 120P. Accordingly, the embodiment may enable the coupling part 142 to be stably coupled to the conductive metal part 141. Specifically, the conductive metal part 141 may include a metal material that increases the bonding force between the pad part 120P and the coupling part 142. Accordingly, the problem of the coupling part 142 peeling off from the pad part 120P may be solved.

[0191] The conductive metal part 141 may include an extension part 141-2 that extends in an outward direction from the contact part 141-1 of the pad part 120P. The extension part 141-2 of the conductive metal part 141 may not vertically overlap the upper surface of the pad part 120P. The extension part 141-2 of the conductive metal part 141 may vertically overlap the side surface 122S of the pad part 120P. Preferably, the extension part 141-2 of the conductive metal part 141 may vertically overlap the curved side surface 122S of the pad part 120P. Since the side surface 122S of the pad part 120P has a curvature, the area of the upper surface of the pad part 120P may decrease according to the curvature. At this time, since the extension part 141-2 of the conductive metal part 141 vertically overlaps the curved side surface 122S, the contact area with the coupling part 142 may be increased. Accordingly, the embodiment may further improve the bonding strength between the coupling part 142 and the pad part 120P.

[0192] At this time, the extension part 141-2 of the conductive metal part 141 may be bent with a curvature corresponding to the curvature of the side surface 122S of the pad part 120P. Accordingly, the extension part 141-2 may minimize the difference between the width of the upper surface and the width of the lower surface of the second part 122 of the pad part 120P. Therefore, the embodiment may prevent a decrease in signal characteristics caused by the width difference between the upper surface and the lower surface of the second part 122. Accordingly, the embodiment may further improve the operational reliability of the semiconductor package.

[0193] Therefore, the extension portion 141-2 of the conductive metal portion 141 can be arranged to surround the side surface 122S of the pad portion 120P. For example, the extension portion 141-2 can include an inner surface 141-2S1 facing the side surface 122S of the pad portion 120P and an outer surface 141-2S2 opposite to the inner surface 141-2S1. Additionally, the extension portion 141-2 can include a lower surface 141-2L between the inner surface 141-2S1 and the outer surface 141-2S2. Thereby, the embodiment can solve the problem that the extension portion 141-2 of the conductive metal portion 141 is separated from the contact portion 141-1. Moreover, even if the extension portion 141-2 of the conductive metal portion 141 is separated from the contact portion 141-1, the embodiment can prevent the extension portion 141-2 of the conductive metal portion 141 from contacting another electrode portion adjacent thereto. Thereby, the embodiment can further improve the electrical reliability of the semiconductor package.

[0194] At this time, the inner surface 141-2S1 of the extension portion 141-2 can contact the curved side surface 122S of the pad portion 120P. For example, the entire area of the inner surface 141-2S1 can contact the side surface 122S of the pad portion 120P.

[0195] Additionally, the outer surface 141-2S2 of the extension portion 141-2 can be covered by the first protective layer 112. For example, the outer surface 141-2S2 of the extension portion 141-2 can be in direct contact with the first protective layer 112. The lower surface 141-2L of the extension portion 141-2 may not contact the side surface 122S of the pad portion 120P. For example, the lower surface 141-2L of the extension portion 141-2 can contact the first protective layer 112. The outer surface 141-2S2 and the lower surface 141-2L of the extension portion 141-2 of the first embodiment can contact the first protective layer 112, and the inner surface 141-2S1 of the extension portion 141-2 can contact the curved side surface 122S of the pad portion 120P. Therefore, the contact area between the electrode portion 150 and the first protective layer 112 can be increased through the extension portion 141-2 of the conductive metal portion 141, and thus the adhesion between the electrode portion 150 and the first protective layer 112 can be improved.

[0196] The bonding portion 140 can include a coupling portion 142 provided on the conductive metal portion 141. The coupling portion 142 can include a through portion 142-1 provided on the conductive metal portion 141 and a protruding portion 142-2 provided on the through portion 142-1. Therefore, the bonding portion 140 can have a structure in which the conductive metal portion 141, the through portion 142-1, and the protruding portion 142-2 are stacked in the vertical direction.

[0197] The through portion 142-1 may pass through at least a part of the first protective layer 112. For example, the second portion 122 of the pad portion 120P, the conductive metal portion 141, and the through portion 142-1 may be through electrodes passing through the first protective layer 112. Additionally, the through portion 142-1 may be a part of the through electrode passing through the first protective layer 112.

[0198] The width W4 of the through portion 142-1 may be smaller than the width of the conductive metal portion 141. At this time, the width of the conductive metal portion 141 may represent the length in the horizontal direction of the contact portion 141-1 and the extension portion 141-2 of the conductive metal portion 141. The contact portion 141-1 of the conductive metal portion 141 may represent the portion vertically overlapping with the upper surface of the pad portion 120P, and the extension portion 141-2 of the conductive metal portion 141 may represent the portion vertically overlapping with the curved side surface 122S but not vertically overlapping with the upper surface of the pad portion 120P. Accordingly, the boundary between the contact portion 141-1 and the extension portion 141-2 of the conductive metal portion 141 can be distinguished.

[0199] The width W4 of the through portion 142-1 may be smaller than the width of the contact portion 141-1 of the conductive metal portion 141. When the width W4 of the through portion 142-1 is greater than the width of the conductive metal portion 141, a height deviation may occur between the plurality of coupling portions 142. For example, if the width W4 of the through portion 142-1 is greater than the width of the conductive metal portion 141, the thickness deviation and / or the height deviation between the plurality of bonding portions spaced apart from each other may increase, and thus the bondability with the semiconductor device may deteriorate. Additionally, if the width W4 of the through portion 142-1 is greater than the width of the conductive metal portion 141, the interval between the plurality of adjacent through portions may decrease, and thus the signal transmission loss may increase due to an increase in signal interference therebetween.

[0200] The width W4 of the through portion 142-1 can be smaller than the width W3 of the upper surface of the pad portion 120P. For example, the width W4 of the through portion 142-1 can be smaller than the width W3 of the upper surface of the second portion 122 of the pad portion 120P. If the width W4 of the through portion 142-1 is larger than the width W3 of the upper surface of the pad portion 120P, the height deviation of the coupling portion 142 may increase. For example, if the width W4 of the through portion 142-1 is larger than the width W3 of the upper surface of the pad portion 120P, the thickness deviation and / or height deviation between a plurality of bonding portions spaced apart from each other may increase, and thus the bondability with the semiconductor device may deteriorate. Additionally, if the width W4 of the through portion 142-1 is larger than the width W3 of the upper surface of the pad portion 120P, the interval between a plurality of adjacent through portions decreases, and thus the signal transmission loss may increase due to an increase in signal interference therebetween.

[0201] The coupling portion 142 can include a protruding portion 142-2 provided on the through portion 142-1. The through portion 142-1 and the protruding portion 142-2 can be integrally formed with each other. Additionally, the through portion 142-1 can represent a region overlapping with the first protective layer 112 in the horizontal direction, and the protruding portion 142-2 can represent a region not overlapping with the first protective layer 112 in the horizontal direction. For example, the protruding portion 142-2 can represent a portion protruding above the upper surface of the first protective layer 112. The protruding portion 142-2 can refer to a portion joined with a conductive bonding agent such as solder. The width W5 of the protruding portion 142-2 can be smaller than the width W1 of the lower surface of the pad portion 120P. Specifically, the width W5 of the protruding portion 142-2 can be smaller than the width W1 of the lower surface of the first portion 121 of the pad portion 120P. If the width W5 of the protruding portion 142-2 is larger than the width W1 of the lower surface of the pad portion 120P, the interval between a plurality of bonding portions spaced apart from each other may decrease. Additionally, if the interval between a plurality of bonding portions decreases, a short circuit problem may occur because the solder provided on adjacent bonding portions is connected to each other.

[0202] According to Figure 5In an embodiment, the vertical length H1 of the pad portion 120P may be different from the vertical length H2 of the through portion 142-1. In one embodiment, the vertical length H1 of the pad portion 120P may be greater than the vertical length H2 of the through portion 142-1. That is, the embodiment may reduce the vertical length H2 of the through portion 142-1 by allowing the pad portion 120P to include the second portion 122 by the vertical length of the second portion 122. Therefore, the embodiment may allow the vertical length H2 of the through portion 142-1 to be less than the vertical length H1 of the pad portion 120P. In addition, since the vertical length H2 of the through portion 142-1 is less than the vertical length H1 of the pad portion 120P, the vertical length of each of the plurality of bonding portions may be adjusted consistently.

[0203] According to Figure 6 the embodiment of, the vertical length H1 of the pad portion 120P may be different from the vertical length H2 of the through portion 142-1A of the coupling portion 142.

[0204] In one embodiment, the vertical length H1 of the pad portion 120P may be less than the vertical length H2 of the through portion 142-1A. That is, the embodiment may improve the flatness of the upper surface of the pad portion 120P by allowing the pad portion 120P to have the second portion 122. Therefore, even if the through portion 142-1A having a vertical length H2 greater than the vertical length H1 of the pad portion 120P is formed, the embodiment may consistently match the vertical length of each of the plurality of bonding portions. That is, even if the vertical length H2 of the through portion 142-1A increases, the embodiment may minimize the height deviation between the plurality of coupling portions 142 by the pad portion 120P including the second portion 122.

[0205] The wiring electrode 120, the via electrode 130, and the coupling portion 142 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the wiring electrode 120, the via electrode 130, and the coupling portion 142 may be formed of a paste or solder paste including at least one metal material having excellent bonding strength selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the wiring electrode 120, the via electrode 130, and the coupling portion 142 may be formed of copper (Cu) having high conductivity and relatively low price.

[0206] The conductive metal portion 141 may include a metal material different from the wiring electrode 120, the via electrode 130, and the coupling portion 142. Preferably, the conductive metal portion 141 of the electrode portion 150 may include a metal material different from the metal material of the wiring electrode 120. For example, the conductive metal portion 141 may include a metal material different from the metal material constituting the wiring electrode 120 among nickel (Ni), palladium (Pd), gold (Au), and titanium (Ti). For example, the second portion 122 of the pad portion 120P of the electrode portion 150 may include copper and may be etched with an etchant such as H2SO4 in an etching process. The conductive metal portion 141 may include a metal material that is not etched by an etchant such as H2SO4. When the conductive metal portion 141 includes nickel, the adhesion between the pad portion 120P and the coupling portion 142 may be improved, so that the bonding force between the pad portion 120P and the coupling portion 142 may be increased.

[0207] The via electrode 130 of the electrode portion 150 may be formed by filling the inside of a through hole provided in the insulating substrate 110 with a conductive material. The through hole may be formed by any one of mechanical, laser, and chemical processing methods. When the through hole is formed by mechanical processing, methods such as milling, drilling, and routing may be used. In addition, when the through hole is formed by laser processing, a UV or CO2 laser method may be used. In addition, when the through hole is formed by chemical processing, chemicals including aminosilane, ketone, etc. may be used.

[0208] Hereinafter, the structure of another embodiment will be described based on the structure of the described circuit board. In the circuit board of the following embodiment, the detailed description of the parts substantially the same as the structure of the aforementioned circuit board will be omitted.

[0209] At the same time, reference Figure 7 , the structure of the bonding portion 140B of the circuit board may be different from that of the aforementioned embodiment.

[0210] That is, the bonding portion 140 of the previous embodiment includes the conductive metal portion 141 and the coupling portion 142, and the through portion 142-1 does not overlap with the side surface 122S having the curved surface of the pad portion 120P in the vertical direction. That is, the through portion 142-1 of the previous embodiment completely overlaps with the upper surface of the pad portion 120P in the vertical direction.

[0211] In another embodiment, the joint portion 140 may include a conductive metal portion 141 and a coupling portion 142B. In addition, the conductive metal portion 141 may include a contact portion 141-1 and an extension portion 141-2. In addition, the coupling portion 142B may include a through portion 142-1B and a protrusion portion 142-2.

[0212] At this time, the through portion 142-1B can be set to be offset to one side on the conductive metal portion 141. For example, the central axis in the horizontal direction of the through portion 142-1B may not be aligned with the central axis in the horizontal direction of the conductive metal portion 141. This may be because the conductive metal portion 141 includes a contact portion 141-1 and an extension portion 141-2, and the width of the conductive metal portion 141 is greater than the width of the upper surface of the pad portion 120P due to the extension portion 141-2.

[0213] Therefore, in the embodiment, when forming the through portion 142-1B, the through portion 142-1B can be set to be offset to one side on the pad portion 120P. Thus, the through portion 142-1B can include a portion that overlaps with the side surface 122S having a curved surface of the pad portion 120P in the vertical direction. For example, the through portion 142-1B can include a first portion that overlaps with the upper surface of the pad portion 120P in the vertical direction, and a second portion that overlaps with the side surface 122S having a curved surface of the pad portion 120P in the vertical direction.

[0214] Thereby, the embodiment can increase the interval between a plurality of adjacent through portions 142-1B, and further increase the interval between a plurality of adjacent coupling portions 142B. In addition, the embodiment can increase the amount of conductive adhesive provided on the coupling portion 142B by increasing the interval between the coupling portions 142B, thereby improving the bonding strength between the semiconductor device and the circuit board.

[0215] Meanwhile, referring to Figure 8 , the embodiment can include a bonding portion 140C. The bonding portion 140C can include a conductive metal portion 141C and a coupling portion 142.

[0216] The conductive metal portion 141C can include a contact portion 141-1 that vertically overlaps with the upper surface of the pad portion 120P. In addition, the conductive metal portion 141C can include an extension portion 141-2C that bends downward and extends from the contact portion 141-1. At this time, the inner surface of the extension portion 141-2 of the previous embodiment can be in contact with the side surface 122S having a curved surface of the pad portion 120P as a whole.

[0217] In contrast, the inner surface of the extension portion 141-2C may partially contact the curved side surface 122S of the pad portion 120P. For example, the extension portion 141-2C may be bent in a bending direction corresponding to the curvature of the side surface 122S of the pad portion 120P. However, the curvature of the inner surface of the extension portion 141-2C may be different from the curvature of the side surface 122S of the pad portion 120P. Therefore, the inner surface of the extension portion 141-2C may include a first portion that contacts the curved side surface 122S of the pad portion 120P and a second portion that is spaced apart from the side surface 122S of the pad portion 120P. Additionally, a certain separation space may be provided between the second portion of the inner surface of the extension portion 141-2C and the side surface 122S of the pad portion 120P. At this time, the first protective layer 112 may be provided to fill the separation space. At this time, the separation space may serve as an anchor for improving the bonding force with the first protective layer 112. Thus, the embodiment may increase the adhesion between the insulating layer 111 and the first protective layer 112 and the adhesion between the first protective layer 112 and the bonding portion 140C.

[0218] Meanwhile, as a variant example thereof, the inner surface of the extension portion 141-2C may include only the second portion. For example, the inner surface of the extension portion 141-2C may not contact the side surface 122S having a curved surface of the pad portion 120P at all. For example, the inner surface of the extension portion 141-2C may contact the first protective layer 112 as a whole.

[0219] According to Figure 9 the embodiment of, the embodiment may include a bonding portion 140D. The bonding portion 140D may include a conductive metal portion 141D and a coupling portion 142. The conductive metal portion 141D may include a contact portion 141-1 that vertically overlaps the upper surface of the pad portion 120P. Additionally, the conductive metal portion 141D may include an extension portion 141-2D that bends downward and extends from the contact portion 141-1. The inner surface of the extension portion 141-2D may not contact the curved side surface 122S of the pad portion 120P as a whole. For example, the extension portion 141-2D may be bent in a bending direction different from the curvature of the side surface 122S of the pad portion 120P. However, the curvature of the inner surface of the extension portion 141-2D may be different from the curvature of the side surface 122S of the pad portion 120P. Therefore, the inner surface of the extension portion 141-2C may not contact the curved side surface 122S of the pad portion 120P. At this time, the lower surface of the extension portion 141-2D may also not contact the side surface 122S of the pad portion 120P. For example, all of the inner surface, outer surface, and lower surface of the extension portion 141-2D may contact the first protective layer 112.

[0220] According toFigure 10 An embodiment may include a bonding portion 140E. The bonding portion 140E may include a conductive metal portion 141E and a coupling portion 142.

[0221] The conductive metal portion 141E may include a contact portion 141-1 that vertically overlaps the upper surface of the pad portion 120P. Additionally, the conductive metal portion 141E may include an extension portion 141-2E that bends downward and extends from the contact portion 141-1. The inner surface of the extension portion 141-2E may not completely contact the curved side surface 122S of the pad portion 120P. For example, the extension portion 141-2E may bend in a bending direction different from the curvature of the side surface 122S of the pad portion 120P. However, the curvature of the inner surface of the extension portion 141-2E may be different from the curvature of the side surface 122S of the pad portion 120P. Thus, the inner surface of the extension portion 141-2E may not contact the curved side surface 122S of the pad portion 120P. Additionally, the lower surface of the extension portion 141-2E may contact the curved side surface 122S of the pad portion 120P. That is, depending on the length of the extension portion 141-2E in the horizontal direction, the lower surface corresponding to the end of the extension portion 141-2E may contact the side surface 122S of the pad portion 120P.

[0222] According to Figure 11 An embodiment may include a bonding portion 140F. The bonding portion 140F may include a conductive metal portion 141F and a coupling portion 142.

[0223] The conductive metal portion 141F may include a contact portion 141-1 that vertically overlaps the upper surface of the pad portion 120P. Additionally, the conductive metal portion 141F may include an extension portion 141-2F that bends downward and extends from the contact portion 141-1. The extension portion 141-2F may not horizontally overlap the side surface 122S of the pad portion 120P. For example, the extension portion 141-2F may extend horizontally from the contact portion 141-1 instead of extending downward. That is, the extension portion 141-2F may overlap the side surface 122S of the pad portion 120P in the vertical direction, but may not overlap the side surface 122S of the pad portion 120P in the horizontal direction.

[0224] The circuit board of the above-described embodiment can minimize the height deviation between a plurality of bonding portions connected to the coupling member. Specifically, the circuit board of the embodiment can include a pad portion. The pad portion can include a first portion embedded in the insulating layer and a second portion disposed on the first portion and protruding on the insulating layer. Additionally, the circuit board can include a connection circuit pattern portion corresponding to the trace, and the connection circuit pattern portion overlaps the first portion of the plurality of pad portions in the horizontal direction. At this time, the second portion of the pad portion can be a seed layer for forming the first portion of the pad portion and the connection circuit pattern portion by electrolytic plating.

[0225] Specifically, in a conventional circuit board, the copper layer used as the seed layer is completely removed. As a result, the thickness of the bonding portion provided on the pad portion in the conventional circuit board can increase. Consequently, the conventional circuit board may have a height deviation between a plurality of bonding portions spaced apart from each other in the horizontal direction. Therefore, when a semiconductor device is bonded to the bonding portion, due to the height difference between the plurality of bonding portions, the conventional circuit board may not be able to stably place the semiconductor device on the bonding portion, and the semiconductor device may be bonded in a tilted state in a specific direction. In contrast, the embodiment can not remove the portion of the copper layer used as the seed layer in the region where the bonding portion is to be provided, thereby allowing the pad portion to have a second portion that is the non-removed portion of the copper layer as described above. At this time, the upper surface of the second portion of the pad portion can represent the upper surface of the copper layer preferentially provided on the carrier member during the manufacturing process of the circuit board. Therefore, the upper surface of the second portion of the pad portion can be flat. Moreover, the upper surfaces of the second portions of the plurality of pad portions can be located on the same plane. Thus, the embodiment can form a plurality of bonding portions having a uniform thickness and / or height by arranging the bonding portions on the second portion of the pad portion. Additionally, the embodiment can reduce the thickness of the bonding portion by the thickness of the second portion of the pad portion. Therefore, the embodiment can solve the problem that the thickness deviation between the plurality of bonding portions increases in proportion to the thickness of the bonding portion. Thus, the embodiment can minimize the height deviation between the plurality of bonding portions. Therefore, the embodiment can stably dispose the semiconductor device on the plurality of bonding portions. Moreover, compared with the thickness of the conventional bonding portion, the embodiment can increase the thickness of the bonding portion by the thickness of the second portion of the pad portion. Additionally, even if the thickness of the bonding portion increases, by forming the bonding portion using the pad portions having a uniform height, the embodiment can minimize the thickness deviation between the plurality of bonding portions.

[0226] Therefore, the embodiment can ensure the height of the bonding portion that allows the semiconductor device to be stably bonded, and can improve the overall physical and / or electrical characteristics of the semiconductor package. Thus, the semiconductor device can be operated smoothly, and further, the server or electronic product can be operated smoothly.

[0227] In addition, the bonding portion may include a through portion that passes through at least a part of the region of the upper surface of the protective layer and protrudes onto the protective layer, and a protruding portion provided on the through portion and protruding onto the protective layer. The second portion of the pad portion may include a side surface having a curvature. The through portion of the bonding portion may overlap with the side surface having a curvature of the pad portion in the vertical direction. Thus, when forming the through portion of the bonding portion, the embodiment may allow the through portion to be offset to one side on the pad portion. Thereby, the embodiment may increase the interval between a plurality of through portions adjacent to each other, and further increase the interval between a plurality of bonding portions adjacent to each other. The embodiment may increase the amount of coupling members provided on the bonding portion by increasing the spacing between the bonding portions, thereby improving the bonding strength between the semiconductor device and the circuit board.

[0228] In addition, the conductive metal portion of the bonding portion may include a contact portion that overlaps with the upper surface of the pad portion in the vertical direction, and an extension portion that overlaps with the side surface having a curvature of the pad portion in the vertical direction. The extension portion may be bent from the contact portion in a bending direction corresponding to the curvature of the side surface of the pad portion. Thereby, the embodiment may use the extension portion to increase the contact area between the protective layer and the pad portion, thereby improving the bonding force between the protective layer and the pad portion.

[0229] In addition, at least a part of the inner surface of the extension portion of the conductive metal portion may not be in contact with the side surface of the pad portion. Thereby, a certain separation space may be provided between the side surface of the pad portion and the inner surface of the extension portion. At this time, a protective layer may be provided to fill the separation space. At this time, the separation space may be used as an anchor for improving the bonding force with the protective layer. Thereby, the embodiment may improve the adhesion between the insulating layer and the protective layer and the adhesion between the protective layer and the bonding portion.

[0230] Figures 12 to 23 is shown in the process sequence Figure 2 A cross-sectional view of the manufacturing method of the circuit board shown.

[0231] Reference Figure 12 , the embodiment may prepare a carrier board. For example, the embodiment may prepare a carrier board having a carrier insulating layer CB1 and a metal layer CB2 provided on at least one surface of the carrier insulating layer CB1. At this time, the metal layer CB2 may be provided only on one of the first surface and the second surface of the carrier insulating layer CB1, or alternatively, may be provided on both surfaces. For example, the metal layer CB2 may be provided only on one surface of the carrier insulating layer CB1, and thus, the manufacturing process of the circuit board may be performed only on one surface. In another embodiment, the metal layer CB2 may be provided on both surfaces of the carrier insulating layer CB1, and thus, the manufacturing processes of a plurality of circuit boards may be performed simultaneously on both surfaces of the carrier board.

[0232] The metal layer CB2 can be formed by electroless plating on the carrier insulating layer CB1. Alternatively, the carrier insulating layer CB1 and the metal layer CB2 can be a CCL (Copper Clad Laminate). That is, the metal layer CB2 can be a copper layer. For example, the metal layer CB2 can be a copper foil. For example, the metal layer CB2 can be an electroless plating layer formed on the carrier insulating layer CB1. That is, the metal layer CB2 can be the first-formed metal layer during the process of manufacturing a circuit board. The metal layer CB2 can constitute the second part 122 of the pad portion 120P in the wiring electrode 120. The metal layer CB2 can be a seed layer for electrolytically plating the first part 121 of the pad portion 120P and the connection circuit pattern portion 120T. The metal layer CB2 can have a certain thickness. The metal layer CB2 can be composed of one layer, or can be composed of at least two layers. Thus, the thickness of the second part 122 of the pad portion 120P can be ensured. When the metal layer CB2 is composed of two or more layers, one of the layers can be a copper layer and the other layer can be an electroless plating layer.

[0233] Next, referring to Figure 13 , embodiments can perform the process of forming the wiring electrode 120 under the metal layer CB2. Preferably, embodiments can perform the process of electrolytically plating on the metal layer CB2 as a seed layer to form the first part 121 of the pad portion 120P and the connection circuit pattern portion 120T. To this end, a mask M1 can be provided under the metal layer CB2, and the mask M1 includes an opening area corresponding to the areas where the first part 121 of the pad portion 120P and the connection circuit pattern portion 120T are to be provided.

[0234] At this time, in embodiments, before the electrolytic plating process of the first part 121 of the pad portion 120P and the connection circuit pattern portion 120T, a curing process of the mask M1 can be additionally performed. For example, in embodiments, the process of curing the mask M1 can be performed after the exposure and development processes of the mask M1. The curing of the mask M1 can include curing using ultraviolet rays and curing using infrared rays. For example, in embodiments, ultraviolet rays in the range of 5mV to 100mV can be used to cure the mask M1. Alternatively, in embodiments, the mask M1 can be cured using infrared thermal curing. As described above, in embodiments, the bonding strength between the metal layer CB2 and the mask M1 can be improved by additionally performing the process of curing the mask M1. Therefore, in embodiments, the first part 121 of the pad portion 120P and the connection circuit pattern portion 120T can be refined according to the improved bonding strength between the mask M1 and the metal layer CB2.

[0235] Next, referring to Figure 14, in an embodiment, the mask M1 can be removed. After that, the embodiment can perform a process on the first part 121 of the preprocessed pad portion 120P and the connection circuit pattern portion 120T. For example, the embodiment can perform a process of providing a surface roughness of a certain degree or higher to the surfaces of the first part 121 of the pad portion 120P and the connection circuit pattern portion 120T. For example, in the embodiment, the side surfaces and the lower surfaces of each of the first part 121 of the pad portion 120P and the connection circuit pattern portion 120T can have a ten-point average surface roughness (Rz) in the range of 0.01 μm to 0.5 μm. After that, in the embodiment, an insulating layer 111 can be formed under the metal layer CB2.

[0236] Next, referring to Figure 15 , the embodiment can perform a process of forming a through hole TH in the insulating layer 111. The through hole TH can be formed by laser processing, but is not limited thereto.

[0237] Next, referring to Figure 16 , the embodiment can perform a process of forming a wiring electrode 120 and a via electrode 130 on the insulating layer 111.

[0238] Next, referring to Figure 17 , the embodiment can perform a process of laminating an additional stacked layer under the insulating layer 111. For example, the embodiment can perform a process of laminating the second layer of the insulating layer 111 under the first layer of the insulating layer 111. After that, the embodiment can perform a process of forming a wiring electrode 120 and a via electrode 130 on the second layer of the insulating layer 111 by repeating the Figure 15 and Figure 16 processes.

[0239] Next, referring to Figure 18 , the embodiment can perform a process of removing the carrier board from the circuit board manufactured as described above. For example, the embodiment can perform a process of separating the carrier insulating layer CB1 and the metal layer CB2 on the carrier board from each other. Therefore, in the circuit board of the embodiment, the metal layer CB2 included in the carrier board remains on the outermost side.

[0240] Next, referring to Figure 19 , the embodiment can perform a process of forming a conductive metal portion 141 on the upper surface of the metal layer CB2. The conductive metal portion 141 can be disposed in a region of the metal layer CB2 of the carrier board that vertically overlaps with the pad portion 120P of the wiring electrode 120. At this time, the conductive metal portion 141 can be formed of a metal material having selective etching properties with respect to the metal layer CB2 of the carrier board.

[0241] Next, referring to Figure 20, in an embodiment, a process of forming a second portion 122 of the pad portion 120P by etching a metal layer CB2 of a carrier substrate using a conductive metal portion 141 can be performed. At this time, according to the etching characteristics, a side surface of the second portion 122 may include a side surface having a curvature. In addition, by etching the second portion 122, at least a portion of the conductive metal portion 141 may vertically overlap with an upper surface of the second portion 122. That is, the conductive metal portion 141 may include a contact portion 141-1 and an extension portion 141-2. According to the etching characteristics, the extension portion 141-2 may be in complete contact with the side surface having a curvature of the second portion 122 of the pad portion 120P. However, the embodiment is not limited thereto, and the extension portion 141-2 may have Figures 8 to 11 any one of the shapes shown in

[0242] Next, referring to Figure 21 , in an embodiment, a process of forming a first protective layer 112 and a second protective layer 113 on upper and lower surfaces of the insulating layer 111, respectively, can be performed.

[0243] Next, referring to Figure 22 , in an embodiment, a process of forming an opening 112TH that vertically overlaps with the contact portion 141-1 of the conductive metal portion 141 in the first protective layer 112 can be performed. In addition, in an embodiment, a process of forming at least one opening 113TH in the second protective layer 113 can be performed.

[0244] Next, referring to Figure 23 , in an embodiment, a process of forming a coupling portion 142 in the opening 112TH of the first protective layer 112 can be performed. At this time, the coupling portion 142 may include a through portion 142-1 that fills the opening 112TH of the first protective layer 112 and a protruding portion 142-2 provided on the first protective layer 112.

[0245] Figure 24 is a cross-sectional view showing a circuit board according to a second embodiment, Figure 25 is an optical micrograph showing an interface of an insulating layer provided in a circuit board according to an embodiment of Figure 24 , Figure 26 is a cross-sectional view showing a state before arranging a conductive metal portion in a region of Figure 24 , Figure 27 is a view showing a state after arranging a conductive metal portion in Figure 26 , Figure 28 is a view showing Figure 24 a detailed layer structure of a lower wiring electrode in a circuit board of Figure 29 is a cross-sectional view showing a circuit board according to a third embodiment, Figure 30 is a cross-sectional view showing a circuit board according to a fourth embodiment, Figure 31It is a cross-sectional view showing a circuit board according to the fifth embodiment.

[0246] Hereinafter, reference will be made to Figures 24 to 9 Specifically describe the circuit board according to the embodiment.

[0247] Referring to Figure 24 , the circuit board 1000 may include an insulating layer 1110, an electrode portion 1120, a first protective layer 1130, and a second protective layer 1140. The electrode portion 1120 may include a first wiring electrode 1121, a second wiring electrode 1122, and a via electrode 1123. The first wiring electrode 1121 may represent an electrode provided on the lower surface of one insulating layer, and the second wiring electrode 1122 may represent an electrode provided on the upper surface of one insulating layer. In addition, the electrode portion 1120 may include a conductive metal portion 1124 provided on the second wiring electrode 1122. For ease of explanation, Figure 24 The circuit board 1000 in

[0248] The insulating layer 1110 may include multiple layers based on one via electrode 1123. For example, the insulating layer 1110 may include a first layer 1111 and a second layer 1112. The first layer 1111 and the second layer 1112 of the insulating layer 1110 may include different insulating materials. For example, the first layer 1111 of the insulating layer 1110 may include a reinforcing member. The reinforcing member may represent a filler. That is, the reinforcing member may represent an inorganic filler and may have a different meaning from the glass fiber material that can extend in the horizontal direction of the insulating layer 1110. The first layer 1111 of the insulating layer 1110 may include an organic material containing a filler. As an example, the first layer 1111 of the insulating layer 1110 may use ABF (Ajinomoto Build-up Film) or PID (Photo Imageable Dielectric resin) corresponding to products released by Ajinomoto Co., Inc. The second layer 1112 of the insulating layer 1110 may be provided on the first layer 1111 of the insulating layer 1110. The second layer 1112 of the insulating layer 1110 may be provided on the first layer 1111 while having a smaller thickness than the first layer 1111. For example, the second layer 1112 of the insulating layer 1110 may include an insulating material different from the insulating material provided in the first layer 1111. Preferably, the second layer 1112 of the insulating layer 1110 may not include a reinforcing member. For example, the second layer 1112 of the insulating layer 1110 may include a pure polymer.

[0249] For example, the insulating layer of the control example only includes the first layer. In this case, when the insulating layer only includes the first layer, the physical reliability and electrical reliability of the circuit board may deteriorate. Specifically, the first layer of the insulating layer may include a reinforcing member. In addition, when the electrode portion is disposed on the insulating layer, surface treatment may be performed to ensure the adhesion between the electrode portion and the first layer of the insulating layer. The surface treatment may be etching the surface of the first layer of the insulating layer. At this time, when the surface of the first layer of the insulating layer is etched, the filler provided in the first layer of the insulating layer may be exposed to the outside. In addition, the filler exposed to the outside may act as a factor that reduces the electrical reliability and physical reliability of the circuit board. For example, when electroless copper plating is performed on the first layer of the insulating layer to form a seed layer, the seed layer may contact the resin of the first layer of the insulating layer and the filler of the first layer, respectively. In addition, the adhesion between the seed layer and the filler may deteriorate depending on the characteristics of the seed layer. That is, when the contact area between the seed layer and the filler increases or the contact area between the seed layer and the resin decreases, the adhesion between the seed layer and the insulating layer may decrease. In addition, the leakage current or impedance of the circuit board may change due to changes in capacitance, resistance, inductance, etc., so the electrical reliability may also deteriorate. To solve this problem, the content of the filler provided in the insulating layer may be reduced. However, if the content of the filler is reduced, the rigidity of the circuit board may be correspondingly reduced. In addition, if the rigidity of the circuit board is reduced, a reliability problem may occur in which the circuit board is greatly bent in a specific direction. In addition, if the electrode portion contacts the filler, the transmission loss of the signal transmitted through the electrode portion may increase due to the physical properties of the filler, and the electrical characteristics may deteriorate accordingly.

[0250] Therefore, the embodiment can improve the electrical characteristics of the electrode portion 1120 while ensuring the adhesion between the insulating layer 1110 and the electrode portion 1120. For this purpose, the insulating layer 1110 may include a first layer 1111 and a second layer 1112 on the first layer 1111. The first layer 1111 of the insulating layer 1110 may be composed of an organic material including a reinforcing member. As an example, the reinforcing member may represent a filler. Thus, the first layer 1111 can ensure the rigidity of the insulating layer 1110 while being able to stably place the electrode portion 1120 on the insulating layer 1110. The second layer 1112 of the insulating layer 1110 may be provided on the first layer 1111 of the insulating layer 1110. The second layer 1112 of the insulating layer 1110 may not include a reinforcing member. Additionally, at least a part of the electrode portion 1120 may be provided on the second layer 1112 of the insulating layer 1110. For example, at least a part of the electrode portion 1120 may be in contact with the second layer 1112 of the insulating layer 1110. At this time, the second layer 1112 of the insulating layer 1110 may not include a reinforcing member. Therefore, the electrode portion 1120 may not be in contact with the reinforcing member. Thus, the embodiment can improve the adhesion between the electrode portion 1120 and the insulating layer 1110. In addition, the embodiment can improve the electrical characteristics of the electrode portion 1120.

[0251] A third layer 1113 may be provided below the first layer 1111 of the insulating layer 1110. The third layer 1113 may include the same material as the second layer 1112. The third layer 1113 may include an organic material without a reinforcing member. The third layer 1113 may be a pure polymer not including a reinforcing member. At this time, the third layer 1113 of the insulating layer 1110 may include the same insulating material as the second layer 1112 and thus may also be referred to as the "second layer". For example, when the circuit board has a multi-layered structure, one of the multiple insulating layers may include the first layer 1111, the second layer 1112, and the third layer 1113 of the insulating layer 1110. For example, when the substrate has a multi-layered structure, one of the multiple insulating layers may include the first layer 1111 and the second layer 1112 of the insulating layer 1110. For example, when the circuit board has a multi-layered structure, one of the multiple insulating layers may include the first layer 1111 and the third layer 1113 of the insulating layer 1110.

[0252] The thickness of the first layer 1111 of the insulating layer 1110 may be in the range of 20 μm to 40 μm. Preferably, the thickness of the first layer 1111 of the insulating layer 1110 may be in the range of 22 μm to 38 μm. More preferably, the thickness of the first layer 1111 of the insulating layer 1110 may be in the range of 25 μm to 35 μm. If the thickness of the first layer 1111 is less than 20 μm, the rigidity of the circuit board 1000 may deteriorate. Additionally, if the thickness of the first layer 1111 is less than 20 μm, it may be impossible to stably arrange the electrode portion 1120, and thus the electrical reliability of the circuit board may deteriorate. Further, if the thickness of the first layer 1111 of the insulating layer 1110 exceeds 40 μm, the total thickness of the circuit board 1000 may increase, and thus the thickness of the semiconductor package may increase. Moreover, if the thickness of the first layer 1111 of the insulating layer 1110 exceeds 40 μm, it may be difficult to miniaturize the electrode portion 1120 of the circuit board 1000.

[0253] The thickness of the second layer 1112 of the insulating layer 1110 may be less than the thickness of the first layer 1111. For example, the second layer 1112 of the insulating layer 1110 may have a thickness in the range of 1 μm to 5 μm. Preferably, the thickness of the second layer 1112 of the insulating layer 1110 may be in the range of 1.2 μm to 4 μm. More preferably, the thickness of the second layer 1112 of the insulating layer 1110 may be in the range of 1.5 μm to 3 μm. Preferably, the thickness of the second layer 1112 of the insulating layer 1110 may be in the range of 2% to 25% of the thickness of the first layer 1111 of the insulating layer 1110. Preferably, the thickness of the second layer 1112 of the insulating layer 1110 may be in the range of 3% to 18% of the thickness of the first layer 1111 of the insulating layer 1110. More preferably, the thickness of the second layer 1112 of the insulating layer 1110 may be in the range of 4% to 12% of the thickness of the first layer 1111 of the insulating layer 1110. If the thickness of the second layer 1112 of the insulating layer 1110 is less than 1 μm or less than 2% of the thickness of the first layer 1111, it may be difficult to provide a uniform center line average surface roughness (Ra) on the upper surface of the second layer 1112 of the insulating layer 1110. If the thickness of the second layer 1112 of the insulating layer 1110 is less than 1 μm or less than 2% of the thickness of the first layer 1111, the filler provided in the first layer 1111 of the insulating layer 1110 may be exposed on the second layer 1112. As a result, due to the contact between the electrode portion 1120 and the filler of the first layer 1111, the adhesiveness may decrease or the electrical characteristics of the electrode portion 1120 may decrease. Additionally, if the thickness of the second layer 1112 of the insulating layer 1110 exceeds 5 μm or is greater than 25% of the thickness of the first layer 1111, the thickness of the insulating layer 1110 may increase, and thus the thickness of the circuit board may increase.

[0254] Here, the thickness may correspond to the distance of each layer of the insulating layer 1110 in the vertical direction of the circuit board. That is, the thickness may represent the length in the direction from the upper surface to the lower surface or from the lower surface to the upper surface of the circuit board 1000, and may represent the length in the vertical direction of the circuit board. Here, the upper surface may represent the highest position of each component in the vertical direction, and the lower surface may represent the lowest position of each component in the vertical direction. Additionally, these positions may be referred to as relative to each other.

[0255] The first layer 1111 of the insulating layer 1110 is provided with a filler, and the second layer 1112 of the insulating layer 1110 is not provided with a filler. Thus, the interface between the first layer 1111 and the second layer 1112 can be distinguished. Specifically, the refractive index of the filler may be higher than the refractive index of ordinary epoxy resin or acrylic resin. Thereby, a difference in refractive index may occur, and thus the interface between the first layer 1111 including the filler and the second layer 1112 not including the filler can be distinguished. For example, as Figure 25 shown, when images are obtained by reflection and refraction electrons, the image colors of the first layer 1111 and the second layer 1112 of the insulating layer 1110 may look different, and thus the interface can be distinguished.

[0256] The first layer 1111 of the insulating layer 1110 may be provided with a filler to a certain degree or higher. For example, the first layer 1111 of the insulating layer 1110 may include a resin 1111P and a reinforcing member 1111F. The reinforcing member 1111F may represent the filler. The reinforcing member 1111F may be provided in the first layer 1111 in a certain amount or higher. The content of the reinforcing member 1111F in the first layer 1111 of the insulating layer 1110 may be in the range of 60 wt% to 85 wt%. If the content of the reinforcing member 1111F in the first layer 1111 of the insulating layer 1110 is less than 60 wt%, the rigidity of the insulating layer 1110 may be reduced. If the content of the reinforcing member 1111F in the first layer 1111 of the insulating layer 1110 exceeds 85 wt%, the signal transmission characteristics of the via electrode 1123 passing through the first layer 1111 may be reduced.

[0257] At this time, in the prior art, when more than 60 wt% of the reinforcing member 1111F is provided in the first layer 1111 of the insulating layer 1110, the reinforcing member 1111F is exposed to the upper side or the lower side of the insulating layer 1110, and thus the electrode portion 1120 and the reinforcing member 1111F are in contact with each other.

[0258] In contrast, since the insulating layer 1110 of the embodiment includes the second layer 1112 on the first layer 1111, even if the filler content in the first layer 1111 increases, the problem of the electrode portion 1120 and the filler coming into contact with each other can be solved. Accordingly, the embodiment can improve the rigidity of the circuit board 1000 and, thus, improve the electrical characteristics of the electrode portion 1120.

[0259] The surface of the insulating layer 1110 may be provided with a predetermined degree of center line average surface roughness (Ra). For example, the insulating layer 1110 may include an interface 1112B between the first layer 1111 and the second layer 1112. In addition, the insulating layer 1110 may include an upper surface 1112U of the second layer 1112. The center line average surface roughness (Ra) of the interface 1112B may be different from the center line average surface roughness (Ra) of the upper surface 1112U. The deviation of the center line average surface roughness (Ra) of the plurality of lines provided at the interface 1112B may be greater than the deviation of the center line average surface roughness (Ra) of the plurality of lines provided at the upper surface 1112U.

[0260] That is, the embodiment can provide the second layer 1112 of the insulating layer 1110 with a uniform center line average surface roughness (Ra) without deviation. This may be because a metal layer (not shown) provided with surface roughness is attached to the second layer 1112 of the insulating layer 1110, and the surface roughness provided to the surface of the metal layer is transferred to the second layer 1112 of the insulating layer 1110. Accordingly, a uniform center line average surface roughness (Ra) can be provided to the upper surface 1112U of the second layer 1112 of the insulating layer 1110. However, the interface 1112B between the first layer 1111 and the second layer 1112 of the insulating layer 1110 may provide the center line average surface roughness (Ra) by the reinforcing member 1111F included in the first layer 1111. At this time, the particle sizes of the reinforcing members 1111F provided in the first layer 1111 of the insulating layer 1110 may be different. That is, fillers having various particle sizes may be provided in the first layer 1111 of the insulating layer 1110. Accordingly, the center line average surface roughness (Ra) of the interface 1112B between the first layer 1111 and the second layer 1112 of the insulating layer 1110 may have a deviation for each line.

[0261] The center line average surface roughness (Ra) of the upper surface 1112U of the second layer 1112 may be in the range of 0.2 μm to 1.5 μm. Preferably, the center line average surface roughness (Ra) of the upper surface 1112U of the second layer 1112 may be in the range of 0.25 μm to 1.3 μm. More preferably, the center line average surface roughness (Ra) of the upper surface 1112U of the second layer 1112 may be in the range of 0.3 μm to 1.25 μm. If the center line average surface roughness (Ra) of the upper surface 1112U of the second layer 1112 is less than 0.2 μm, the adhesion between the electrode portion 1120 and the upper surface 1112U of the second layer 1112 may not be ensured, and thus physical reliability problems such as peeling of the electrode portion 1120 from the insulating layer 1110 may occur. If the center line average surface roughness (Ra) of the upper surface 1112U of the second layer 1112 exceeds 1.5 μm, the transmission loss of the signal transmitted through the electrode portion 1120 may increase. For example, as the frequency of the transmitted signal increases, the skin effect in which the signal flows along the surface of the electrode portion 1120 occurs. At this time, if the center line average surface roughness (Ra) of the upper surface 1112U of the second layer 1112 exceeds 1.5 μm, the length of the surface may be extended, and the transmission distance of the signal flowing along the surface may also increase. In addition, if the signal transmission distance increases, the signal transmission loss caused thereby may increase. Therefore, it may be difficult to operate the semiconductor device smoothly, and it may be difficult to operate the server or electronic product smoothly. That is, the center line average surface roughness (Ra) of the upper surface 1112U of the second layer 1112 may be directly related to the reliability of the server or electronic product, and thus may have technical interoperability or functional integrity.

[0262] The center line average surface roughness (Ra) of the upper surface 1112U of the second layer 1112 may be less than the particle size of the filler of the reinforcing member 1111F provided in the first layer 1111. Preferably, the particle size of the filler may have various sizes. At this time, the average value of the particle size of the filler may be greater than the center line average surface roughness (Ra) of the upper surface 1112U of the second layer 1112. Thereby, the adhesion between the electrode portion 1120 provided on the upper surface 1112U of the second layer 1112 and the insulating layer 1110 can be ensured, and at the same time, the transmission loss of the signal flowing through the electrode portion 1120 can be reduced to improve the signal characteristics.

[0263] The lower surface of the third layer 1113 of the insulating layer 1110 may have a center line average surface roughness (Ra) corresponding to the center line average surface roughness (Ra) of the upper surface 1112U of the second layer 1112.

[0264] Here, the center line average surface roughness (Ra) can be expressed as the height of the uneven surface. For example, a first uneven surface can be provided at the interface between the first layer 1111 and the second layer 1112 of the insulating layer 1110. Additionally, a second uneven surface can be provided on the upper surface of the second layer 1112 of the insulating layer 1110. Moreover, the height of the first uneven surface and the height of the second uneven surface can be different. Additionally, the deviation of the height of the first uneven surface can be greater than the deviation of the height of the second uneven surface. Preferably, the height of the second uneven surface can be uniform.

[0265] Meanwhile, referring to Figure 26 , the insulating layer 1110 can include a recess 1110R, and at least a part of the electrode portion 1120 is disposed in the recess 1110R. The recess 1110R can be provided to be recessed from the upper surface of the insulating layer 1110 toward the lower surface. The recess 1110R can be a space for the second wiring electrode 1122 of the electrode portion 1120.

[0266] The recess 1110R can be provided in the first layer 1111 and the second layer 1112 of the insulating layer 1110. At this time, the recess 1110R can penetrate the second layer 1112 of the insulating layer 1110 without penetrating the first layer 1111. For example, the recess 1110R can include a first portion 1111R provided in the first layer 1111 of the insulating layer 1110 and a second portion 1112R provided in the second layer 1112 and connected to the first portion 1111R at the same time. The first portion 1111R can be provided in the form of a groove that does not penetrate the first layer 1111 of the insulating layer 1110. The second portion 1112R can be provided in the form of a through hole that penetrates the second layer 1112 of the insulating layer 1110.

[0267] The first wiring electrode 1121 and the second wiring electrode 1122 can have different vertical cross-sectional shapes. For example, the second wiring electrode 1122 can be provided on the uppermost side of the circuit board 1000 and can be used as an electrode connected to an interposer or a semiconductor device. The second wiring electrode 1122 can represent the wiring electrode 120 in the circuit board described in reference Figure 2 . A conductive metal portion 1124 can be provided on the second wiring electrode 1122. At this time, the conductive metal portion 1124 of the second embodiment can be formed by a method different from that of the conductive metal portion of the first embodiment, and thus can have a structure different from that of the conductive metal portion of the first embodiment. At this time, in order to improve the bonding strength between the second wiring electrode 1122 and the conductive metal portion 1124, a process of etching the conductive metal portion 1124 can be performed. Therefore, the recess 1110R of the insulating layer 1110 can include a portion filled with the second wiring electrode 1122 and a portion filled with the conductive metal portion 1124.

[0268] The second wiring electrode 1122 may include a plurality of outer surfaces. The second wiring electrode 1122 may include an upper surface 1122U, side surfaces 1122S, and a lower surface. The upper surface and the lower surface of the second wiring electrode 1122 may have different widths. For example, the upper surface of the second wiring electrode 1122 may have a smaller width than the lower surface of the second wiring electrode 1122. This may be because during the etching process of the second wiring electrode 1122, a part of the upper surface and the side surfaces of the second wiring electrode 1122 are etched and removed, thereby increasing the contact area with the conductive metal part 1124. The upper surface 1122U of the second wiring electrode 1122 may not be in contact with the insulating layer 1110. The upper surface 1122U of the second wiring electrode 1122 may not be in contact with the first layer 1111 and the second layer 1112 of the insulating layer 1110. The upper surface 1122U of the second wiring electrode 1122 may be positioned lower than the upper surface of the insulating layer 1110. Preferably, the upper surface 1122U of the second wiring electrode 1122 may be positioned lower than the upper surface 1112U of the second layer 1112 of the insulating layer 1110. For example, the upper surface 1122U of the second wiring electrode 1122 may be positioned lower than the uppermost second uneven surface among the second uneven surfaces provided on the upper surface 1112U of the second layer 1112. The side surfaces 1122S of the second wiring electrode 1122 may include a plurality of inclinations.

[0269] The side surfaces 1122S of the second wiring electrode 1122 may include a first inclination 1122S1 adjacent to the upper surface 1122U of the second wiring electrode 1122 and increasing the width toward the lower surface of the second wiring electrode 1122. The side surfaces 1122S of the second wiring electrode 1122 may include a second inclination 1122S2 adjacent to the lower surface of the second wiring electrode 1122 and different from the first inclination 1122S1. The second inclination of the side surfaces 1122S of the second wiring electrode 1122 may be an inclination that changes the width toward the upper surface of the second wiring electrode 1122, but is not limited thereto. The second inclination 1122S2 of the side surfaces 1122S of the second wiring electrode 1122 may not horizontally overlap with the second layer 1112 of the insulating layer 1110. The second inclination 1122S2 of the side surfaces 1122S of the second wiring electrode 1122 may be in contact with the first layer 1111. For example, the second inclination 1122S2 of the side surfaces 1122S of the second wiring electrode 1122 may be in contact with the inner wall of the first part 1111R of the recess 1110R provided in the first layer 1111.

[0270] The first inclination 1122S1 of the side surface 1122S of the second wiring electrode 1122 may include a first portion that horizontally overlaps with the first layer 1111 and a second portion that horizontally overlaps with the second layer 1112. The first inclination 1122S1 of the side surface 1122S of the second wiring electrode 1122 may not contact the insulating layer 1110. For example, the first inclination 1122S1 of the side surface 1122S of the second wiring electrode 1122 may be horizontally spaced apart from the inner wall of the first portion 1111R of the recess 1110R provided in the first layer 1111 and the inner wall of the second portion 1112R of the recess 1110R provided in the second layer 1112. The second wiring electrode 1122 may not completely fill the recess 1110R, but may only partially fill the recess. This is because the manufacturing process of the second wiring electrode 1122 includes a process of surface-treating the second wiring electrode 1122, and a part of the outer surface of the second wiring electrode 1122 may be removed by etching in the surface-treatment process. Therefore, the second wiring electrode 1122 may include a gap spaced apart from the inner wall of the recess 1110R.

[0271] A conductive metal part 1124 is provided on the second wiring electrode 1122. Preferably, the second wiring electrode 1122 has a pad part, and the conductive metal part 1124 is provided on the pad part. The conductive metal part 1124 may include a metal different from that of the second wiring electrode 1122. The conductive metal part 1124 may include a metal material for improving the bonding strength between the second wiring electrode 1122 and the connection member. In addition, the conductive metal part 1124 may include a metal material for improving the bonding strength between the second wiring electrode 1122 and the bonding part. For example, the conductive metal part 1124 may include nickel. In addition, when the conductive metal part 1124 includes nickel, the adhesion between the second wiring electrode 1122 and the bonding part may be increased. In addition, when a material such as solder is later used to form an electrical connection with the second wiring electrode 1122, the solder may diffuse into the second wiring electrode 1122 to form an inter-metallic compound, and the inter-metallic compound has problems of poor mechanical and electrical reliability. In particular, if the second wiring electrode 1122 is made of copper, the problem of forming an inter-metallic compound may be further aggravated. However, if nickel is provided, the diffusion of the solder can be prevented, thereby preventing the formation of an inter-metallic compound, thereby improving the electrical reliability and mechanical reliability of the semiconductor package. The conductive metal part 1124 may include a metal other than nickel. For example, the conductive metal part 1124 may include gold. For example, the conductive metal part 1124 may include palladium.

[0272] The conductive metal portion 1124 may protrude above the upper surface of the insulating layer 1110. For example, at least a part of the conductive metal portion 1124 may be disposed in the recess 1110R of the insulating layer 1110, and the remaining part may protrude above the insulating layer 1110. Therefore, when the semiconductor package and the electronic device are combined by subsequent thermocompression (TC) bonding, there is an advantage of ensuring consistency and diffusivity so that the TC bonding process can be smoothly performed.

[0273] The conductive metal portion 1124 may be arranged to surround the second wiring electrode 1122 in the recess 1110R. For example, the upper surface 1122U and the first inclination 1122S1 of the side surface 1122S of the second wiring electrode 1122 may not be in contact with the insulating layer 1110. Therefore, the conductive metal portion 1124 may include a portion disposed in the recess 1110R, and the portion disposed in the recess 1110R may be arranged to cover the upper surface 1122U and the first inclination 1122S1 of the side surface 1122S of the second wiring electrode 1122.

[0274] Specifically, referring to Figure 27 , the conductive metal portion 1124 may include an embedded portion disposed in the recess 1110R. In addition, the embedded portion of the conductive metal portion 1124 may include a portion in contact with the insulating layer 1110. The embedded portion of the conductive metal portion 1124 may include a portion 1124S2 in contact with the inner wall of the first portion 1111R of the recess 1110R and a portion 1124S3 in contact with the inner wall of the second portion 1112R of the recess 1110R.

[0275] In addition, the embedded portion of the conductive metal portion 1124 may include a portion in contact with the second wiring electrode 1122. Specifically, the embedded portion of the conductive metal portion 1124 may include a portion 1124S4 in contact with the upper surface 1122U and the first inclination 1122S1 of the side surface 1122S of the second wiring electrode 1122.

[0276] In addition, the conductive metal portion 1124 may include a protruding portion protruding above the insulating layer 1110. The protruding portion of the conductive metal portion 1124 may include a portion contacting the insulating layer 1110. Specifically, the protruding portion of the conductive metal portion 1124 may include a portion 1124S1 contacting the upper surface 1112U of the second layer 1112 of the insulating layer 1110. That is, the protruding portion of the conductive metal portion 1124 may be arranged to extend horizontally on the second wiring electrode 1122. Therefore, a part of the protruding portion of the conductive metal portion 1124 may vertically overlap with the second wiring electrode 1122, and the remaining part may not vertically overlap with the second wiring electrode 1122. In addition, the lower surface 1124S1 of the portion not vertically overlapping with the second wiring electrode 1122 may contact the upper surface 1112U of the second layer 1112 of the insulating layer 1110.

[0277] The conductive metal portion 1124 may include an upper surface 1124U protruding above the insulating layer 1110. The upper surface 1124U of the conductive metal portion 1124 may include a convex portion extending away from the upper surface of the insulating layer 1110. At least a part of the conductive metal portion 1124 is disposed in the concave portion 1110R of the insulating layer 1110. Therefore, the embodiment can increase the contact area between the conductive metal portion 1124 and the second wiring electrode 1122. Thereby, the embodiment can improve the adhesion between the conductive metal portion 1124 and the second wiring electrode 1122. Therefore, the embodiment can improve the physical reliability between the conductive metal portion 1124 and the second wiring electrode 1122. In addition, since the embodiment has a structure in which the conductive metal portion 1124 surrounds the outer surface of the second wiring electrode 1122, signals can be smoothly transmitted between the conductive metal portion 1124 and the second wiring electrode 1122, and thus the electrical characteristics can be improved. In addition, the embodiment can allow the thicknesses of a plurality of conductive metal portions 1124 spaced apart in the horizontal direction to be consistent. Specifically, the conductive metal portion 1124 may be disposed on the second layer of the insulating layer. At this time, the second layer of the insulating layer may be a pure resin layer not including a reinforcing member such as a filler. Therefore, a uniform surface roughness can be imparted to the surface of the second layer. In addition, a plurality of conductive metal portions may be disposed on the second layer of the insulating layer having a uniform surface roughness. Thereby, the embodiment can make the plurality of conductive metal portions have a consistent thickness. In addition, when a bonding portion is additionally provided on the conductive metal portion, the plurality of bonding portions may have a consistent thickness. Thereby, the embodiment can enable the semiconductor device to be stably bonded to the conductive metal portion or the bonding portion. Therefore, the embodiment can enable the semiconductor device to operate stably and smoothly, thereby improving the operating characteristics of the server or electronic product.

[0278] Reference Figure 28, the first wiring electrode 1121 and the second wiring electrode 1122 may have different layer structures. The second wiring electrode 1122 may have a layer structure that does not include a seed layer. Differently, the first wiring electrode 1121 may have a multilayer structure that includes a seed layer.

[0279] For example, the first wiring electrode 1121 may include a first metal layer 1121-1 disposed below the third layer 1113 of the insulating layer 1110. The first metal layer 1121-1 may be an electroless plating layer. The first metal layer 1121-1 may be an electroless copper plating layer. Additionally, the first wiring electrode 1121 may include a second metal layer 1121-2 disposed below the first metal layer 1121-1. The second metal layer 1121-2 may be an electrolytic electroplating layer using the first metal layer 1121-1 as a seed layer. At this time, a predetermined degree of centerline average surface roughness (Ra) may be provided to the lower surface of the third layer 1113 in contact with the first metal layer 1121-1. Accordingly, the embodiment may improve the adhesion between the first metal layer 1121-1 of the first wiring electrode 1121 and the insulating layer 1110. At this time, the first metal layer 1121-1 of the embodiment does not contact the first layer 1111 of the insulating layer 1110. That is, the first metal layer 1121-1 does not contact the reinforcing member 1111F provided in the first layer 1111 of the insulating layer 1110. Thereby, the embodiment may solve the problem that the adhesion between the first metal layer 1121-1 and the insulating layer 1110 is reduced due to the reinforcing member 1111F. In addition, the embodiment may prevent an increase in the transmission loss of the signal flowing through the first metal layer 1121-1 due to the reinforcing member 1111F. Thereby, the embodiment may improve the physical reliability and electrical reliability of the circuit board. Accordingly, the operation of the semiconductor device may be performed smoothly, and further, the operation of the server or electronic product may be performed smoothly.

[0280] Additionally, when the conductive metal part 1124 is included in the electrode part 1120, the width of the conductive metal part 1124 may have a range of 40 μm to 70 μm. If the width of the conductive metal part 1124 is less than 40 μm, the conductive metal part 1124 may collapse during thermocompression bonding because the width is too small. Additionally, if the width of the conductive metal part 1124 is greater than 70 μm, there may be a problem in that it is difficult to correspond to the fine pitch of the electrodes of the terminals or interposers of the semiconductor device.

[0281] Reference Figure 29 , the electrode part 1120 may further include a bonding part 1125.

[0282] The bonding portion 1125 may protrude on the conductive metal portion 1124 in a direction away from the circuit board 1000. At this time, the embodiment shows that the bonding portion 1125 is provided on the upper side of the circuit board 1000, but is not limited thereto. For example, the bonding portion 1125 may also be provided on the lower side of the circuit board 1000. At this time, the bonding portion 1125 may protrude above the upper surface of the first protective layer 1130. In addition, the conductive metal portion 1124 may be positioned lower than the upper surface of the first protective layer 1130. The bonding portion 1125 may be used to provide ease in the micro-bonding process.

[0283] Reference Figure 30 , the electrode portion 1120 of the circuit board of the embodiment may include a conductive metal portion 1124 having a structure protruding above the upper surface of the first protective layer 1130. For example, the upper surface of the conductive metal portion 1124 of the second embodiment may be positioned lower than the upper surface of the first protective layer 1130. In addition, the upper surface of the conductive metal portion 1124 of the third embodiment may be positioned lower than the upper surface of the first protective layer 1130, while the bonding portion 1125 may be provided on the conductive metal portion 1124.

[0284] In contrast, the conductive metal portion 1124 of the fourth embodiment may be provided while filling a part of the recess 1110R and filling the opening of the first protective layer 1130. Thus, the conductive metal portion 1124 may have a structure protruding above the upper surface of the first protective layer 1130.

[0285] Reference Figure 31 , the circuit board of the embodiment may be a core board.

[0286] For example, the insulating layer of the circuit board may include a first insulating layer 1211 as a core layer. The first insulating layer 1211 may be provided with reinforcing members such as glass fibers. The insulating layer may include a second insulating layer 1212 provided on the first insulating layer 1211 and a third insulating layer 1213 provided below the first insulating layer 1211. The second insulating layer 1212 may have a structure in which multiple layers are stacked in the vertical direction. For example, the second insulating layer 1212 may be stacked on the first insulating layer 1211 in multiple layers, and each stacked layer may include Figure 24 the first layer 1111 and the second layer 1112 of the insulating layer 1110 described in. In addition, the third insulating layer 1213 may also have a structure corresponding to that of the second insulating layer 1212. The electrode portion 1220 may be provided in the insulating layer. At this time, the electrode portion 1220 may be provided in the second insulating layer 1212 and the third insulating layer 1213.

[0287] Each of the second insulating layer 1212 and the third insulating layer 1213 includes a first layer including a reinforcing member and a second layer not including a reinforcing member as described above, thereby ensuring adhesion to the electrode portion 1220 while improving the electrical characteristics of the electrode portion 1220.

[0288] On the other hand, when the circuit board having the above-described features of the present invention is used in IT devices or household appliances (such as smartphones, server computers, TVs, etc.), functions such as signal transmission or power supply can be stably performed. For example, if the circuit board having the features of the present invention performs a semiconductor packaging function, the circuit board can be used to safely protect semiconductor devices from external moisture or contaminants, or alternatively, problems such as leakage current, electrical short circuit, and electrical open circuit between terminals provided to semiconductor chips can be solved. In addition, when the signal transmission function is dominant, the noise problem can be solved. Thus, the circuit board having the above-described features of the present invention can maintain the stable functions of IT devices or household appliances, such that the entire product and the circuit board applying the present invention can achieve functional unity or technical interlock with each other.

[0289] When the circuit board having the above-described features of the present invention is used in a transportation device such as a vehicle, the problem of signal distortion transmitted to the transportation device can be solved, or alternatively, by safely protecting the semiconductor chip that controls the transportation device from the outside and solving problems such as leakage current, electrical short circuit, or electrical open circuit between terminals provided to the semiconductor device, the safety of the transportation device can be further improved. Therefore, the transportation device and the circuit board applying the present invention can achieve functional integrity or technical interlock with each other.

[0290] The characteristics, structures, and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, those of ordinary skill in the art to which the embodiments pertain can even combine or modify the characteristics, structures, effects, etc. shown in each embodiment with respect to other embodiments. Therefore, it should be understood that the content related to such combinations and such modifications is included within the scope of the embodiments.

[0291] The above description focuses on the embodiments, but it is merely illustrative and does not limit the embodiments. Those skilled in the art to which the embodiments pertain can understand that various modifications and applications not shown above are possible without departing from the basic features of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, it should be understood that the differences related to these changes and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: An insulating layer; A pad portion, the pad portion being disposed on the insulating layer; A conductive metal portion, the conductive metal portion being disposed on the pad portion; A protective layer, the protective layer being disposed on the conductive metal portion; And A bonding portion, the bonding portion passing through at least a portion of the protective layer and being electrically connected to the conductive metal portion, Wherein, the pad portion includes a first portion and a second portion, the first portion being inclined in a vertical direction from the upper surface of the pad portion towards the lower surface of the insulating layer to widen the width in the horizontal direction, and the second portion extending from the first portion and having an inclination different from that of the first portion, Wherein, the conductive metal portion is disposed to cover at least a portion of the side surface of the first portion.

2. The circuit board according to claim 1, wherein The bonding portion includes a protruding portion disposed on the protective layer and a through portion extending from the protruding portion, the through portion passing through at least a portion of the protective layer and being electrically connected to the conductive metal portion.

3. The circuit board according to claim 1, wherein, The insulating layer has a reinforcing member, Wherein, at least a portion of the side surface of the first portion of the pad portion does not overlap with the reinforcing member of the insulating layer in the horizontal direction.

4. The circuit board according to claim 1, wherein A recess is provided on the upper surface of the insulating layer, Wherein, the first portion of the pad portion is disposed in the recess.

5. The circuit board according to claim 1, wherein, The conductive metal portion includes a metal material different from that of at least one of the pad portion and the bonding portion.

6. The circuit board according to claim 2, wherein, The side surface of the first portion of the pad portion has a curved surface.

7. The circuit board according to claim 1, wherein, The through portion does not overlap with the curved surface in the vertical direction.

8. The circuit board according to claim 7, wherein, The width of the protruding portion in the horizontal direction is smaller than the width of the second portion of the pad portion.

9. The circuit board according to claim 7, wherein The conductive metal portion includes a contact portion and an extending portion, the contact portion being in contact with the upper surface of the first portion of the pad portion, and the extending portion extending from the contact portion and not overlapping with the upper surface of the first portion in the vertical direction.

10. The circuit board according to claim 9, wherein, The extending portion overlaps with the curved surface in the vertical direction.

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