Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises a silicon-based substrate, wherein the silicon-based substrate comprises a display area and a peripheral area; the sub-pixels are located in the display area, at least one sub-pixel comprises a pixel driving circuit, the pixel driving circuit comprises a first transistor, and the first transistor comprises a semiconductor layer, a grid electrode, a source electrode and a drain electrode; the electronic device is located in the peripheral area and comprises a second transistor, the second transistor comprises a semiconductor layer, a grid electrode, a source electrode and a drain electrode, and the semiconductor layer, the grid electrode, the source electrode and the drain electrode of the second transistor and the semiconductor layer, the grid electrode, the source electrode and the drain electrode of the first transistor are located on the same layer; the metal shielding parts are located in the peripheral area and are intermittently distributed on the side, away from the silicon-based substrate, of the layer where each of the semiconductor layer, the grid electrode, the source electrode and the drain electrode of the second transistor is located, and the orthographic projection of the metal shielding parts and the orthographic projection of the electronic device on the silicon-based substrate are at least partially overlapped.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and particularly to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, silicon-based organic light-emitting diode (OLED) display products have attracted widespread attention due to their advantages such as high resolution, low power consumption, small size and light weight. They have good application prospects in high-resolution near-eye display industries such as wearable devices, industrial security, and medical treatment. In order to improve the display effect of silicon-based OLED, silicon-based OLED usually uses OTP (one time programmable) to compensate pixel units. However, during the production process of silicon-based OLED, silicon-based OLED OTP is easily affected by the energy radiation during ion sputtering coating and UV irradiation during curing, which causes the OTP to fail, and ultimately leads to display abnormalities or black screens on silicon-based OLED, seriously affecting the product yield.

[0003] One of the important research topics for R&D personnel is how to design protection for silicon-based OLED OTP, shield the energy radiation and UV exposure to the OTP during the process, ensure the stability of the OTP programming state, and improve product yield.

[0004] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art.

[0005] Summary of the Invention

[0006] In one aspect, a display substrate is provided, characterized in that the display substrate comprises: a silicon-based substrate, the silicon-based substrate comprising a display area and a peripheral area, the peripheral area surrounding the display area; a plurality of sub-pixels located in the display area of ​​the silicon-based substrate, the plurality of sub-pixels being arrayed in the display area along a first direction and a second direction, at least one of the sub-pixels comprising a pixel driving circuit and a light-emitting element, the pixel driving circuit being electrically connected to the light-emitting element for driving the light-emitting element to emit light, the pixel driving circuit comprising a first transistor, the first transistor comprising a semiconductor layer, a gate, a source and a drain ... An electronic device in the silicon-based substrate, the electronic device comprising a second transistor, the second transistor comprising a semiconductor layer, a gate, a source and a drain, the semiconductor layer, gate, source and drain of the second transistor being located on the same layer as the semiconductor layer, gate, source and drain of the first transistor respectively; and a metal shielding portion located in a peripheral area of ​​the silicon-based substrate, the metal shielding portion being discontinuously distributed on a side of the layer where each of the semiconductor layer, gate, source and drain of the second transistor is located away from the silicon-based substrate, wherein the orthographic projection of the metal shielding portion on the silicon-based substrate at least partially overlaps with the orthographic projection of the electronic device on the silicon-based substrate.

[0007] According to some exemplary embodiments, an orthographic projection of the metal shield on the silicon-based substrate covers an orthographic projection of the electronic device on the silicon-based substrate.

[0008] According to some exemplary embodiments, the display substrate further comprises n metal film layers, the n metal film layers being located on a side of the layer where the source and drain of the electronic device are located away from the silicon-based substrate, and the multiple metal film layers are sequentially away from the silicon-based substrate, and n is a positive integer greater than or equal to 2; and the metal shielding portion comprises n metal shielding sub-portions, and the n metal shielding sub-portions are respectively located in the n metal film layers.

[0009] According to some exemplary embodiments, the display substrate further includes n conductive connection portions located in the display area, the n conductive connection portions are respectively located in the n metal film layers, and the n metal shielding sub-portions and the n conductive connection portions are respectively located in the same metal film layer.

[0010] According to some exemplary embodiments, the metal shielding portion includes a plurality of metal shielding sub-portions located in the same metal film layer, and any two adjacent metal shielding sub-portions located in the same metal film layer are spaced apart.

[0011] According to some exemplary embodiments, the orthographic projections of the n metal shielding sub-portions on the silicon-based substrate at least partially overlap with the orthographic projection of the same electronic device on the silicon-based substrate; and the orthographic projections of any two of the n metal shielding sub-portions on the silicon-based substrate coincide.

[0012] According to some exemplary embodiments, orthographic projections of at least two of the n metal shield sub-portions on the silicon-based substrate at least partially do not overlap.

[0013] According to some exemplary embodiments, the n metal shielding sub-sections include: a plurality of first metal shielding sub-sections located in the i-th metal film layer; and a plurality of second metal shielding sub-sections located in the i+1-th metal film layer, wherein i is a positive integer greater than or equal to 1 and less than or equal to n-2; the orthographic projections of the plurality of first metal shielding sub-sections on the silicon-based substrate and the orthographic projections of the plurality of second metal shielding sub-sections on the silicon-based substrate are alternately arranged along a first direction.

[0014] According to some exemplary embodiments, the n metal shielding sub-sections further include: a plurality of third metal shielding sub-sections located in the i+2th metal film layer; the orthographic projections of the plurality of third metal shielding sub-sections on the silicon-based substrate and the orthographic projections of the plurality of second metal shielding sub-sections on the silicon-based substrate are alternately arranged along a first direction.

[0015] According to some exemplary embodiments, an orthographic projection of at least one of the second metal shield sub-portion on the silicon-based substrate partially overlaps with an orthographic projection of an adjacent first metal shield sub-portion or third metal shield sub-portion on the silicon-based substrate.

[0016] According to some exemplary embodiments, orthographic projections of the plurality of first metal shield sub-portions on the silicon-based substrate respectively coincide with orthographic projections of the plurality of third metal shield sub-portions on the silicon-based substrate.

[0017] According to some exemplary embodiments, the display substrate includes m electronic devices and m metal shielding parts, wherein m is a positive integer greater than or equal to 2; the orthographic projections of the m metal shielding parts on the silicon-based substrate respectively cover the orthographic projections of the m electronic devices on the silicon-based substrate.

[0018] According to some exemplary embodiments, orthographic projections of at least two adjacent metal shielding portions among the m metal shielding portions on the silicon-based substrate are spaced apart in a first direction.

[0019] According to some exemplary embodiments, the orthographic projections of any two adjacent metal shields among the m metal shields on the silicon-based substrate at least partially overlap, so that the orthographic projections of the m metal shields on the silicon-based substrate extend continuously in the first direction.

[0020] According to some exemplary embodiments, thicknesses of at least two of the n metal shielding sub-portions are unequal; or thicknesses of the n metal shielding sub-portions are equal to each other.

[0021] According to some exemplary embodiments, thicknesses of the n metal shielding sub-portions and the n conductive connecting portions respectively located in the same metal film layer are equal to each other.

[0022] According to some exemplary embodiments, the display substrate further includes a plurality of binding terminals located in a peripheral area of ​​the silicon-based substrate, and the orthographic projection of the metal shielding portion on the silicon-based substrate is located between the orthographic projection of the plurality of binding terminals on the silicon-based substrate and the display area.

[0023] According to some exemplary embodiments, the metal shielding portion includes a plurality of metal shielding sub-portions located in the same metal film layer as the plurality of binding terminals, and the sizes of the plurality of metal shielding sub-portions located in the same metal film layer as the plurality of binding terminals in the first direction are respectively substantially equal to the sizes of the plurality of binding terminals in the first direction; and / or, the sizes of the gaps between the plurality of metal shielding sub-portions located in the same metal film layer as the plurality of binding terminals in the first direction are respectively substantially equal to the sizes of the gaps between the plurality of binding terminals in the first direction; and / or, the sizes of the plurality of metal shielding sub-portions located in the same metal film layer as the plurality of binding terminals in the second direction are respectively smaller than the sizes of the plurality of binding terminals in the second direction.

[0024] According to some exemplary embodiments, at least one of the sub-pixels further includes a reflective electrode, and the film layer where the reflective electrode is located is located between the film layer where the pixel driving circuit is located and the film layer where the light-emitting element is located; the metal shielding portion further includes a plurality of top-layer metal shielding sub-portions located on the same layer as the reflective electrode; the dimensions of the plurality of top-layer metal shielding sub-portions in the first direction are respectively substantially equal to the dimensions of the plurality of reflective electrodes in the first direction; and / or the dimensions of the gaps between the plurality of top-layer metal shielding sub-portions in the first direction are respectively substantially equal to the dimensions of the gaps between the plurality of reflective electrodes in the first direction.

[0025] According to some exemplary embodiments, the i+1th metal film layer is located on a side of the i-th metal film layer away from the silicon-based substrate, and the i+2th metal film layer is located on a side of the i+1th metal film layer away from the silicon-based substrate; an edge of the second metal shielding sub-section is retracted relative to an edge of the first metal shielding sub-section toward a center of an electronic device corresponding to both the first metal shielding sub-section and the second metal shielding sub-section, and an edge of the third metal shielding sub-section is retracted relative to an edge of the second metal shielding sub-section toward a center of an electronic device corresponding to both the second metal shielding sub-section and the third metal shielding sub-section.

[0026] According to some exemplary embodiments, the edge of the first metal shielding sub-section is provided with a raised structure, so that the thickness at the edge of the first metal shielding sub-section is greater than the thickness at the center of the first metal shielding sub-section; and / or, the edge of the second metal shielding sub-section is provided with a raised structure, so that the thickness at the edge of the second metal shielding sub-section is greater than the thickness at the center of the second metal shielding sub-section.

[0027] According to some exemplary embodiments, the shape of the protruding structure in a cross section perpendicular to the upper surface of the silicon-based substrate is the same as the shape of the conductive connecting portion located in the same layer in a cross section perpendicular to the upper surface of the silicon-based substrate.

[0028] According to some exemplary embodiments, the n metal shielding sub-sections further include: a fourth metal shielding sub-section located in the j-th metal film layer, where j is a positive integer greater than 1 and less than n; the pixel driving circuit further includes a capacitor, at least one plate of which is located in the j-th metal film layer; and the thickness of the fourth metal shielding sub-section is less than the thickness of any one of the first metal shielding sub-section, the second metal shielding sub-section, and the third metal shielding sub-section.

[0029] According to some exemplary embodiments, the electronic device includes a memory cell, which includes a pair of transistors located on the silicon-based substrate and electrically connected in series; the orthographic projection of the metal shielding portion on the silicon-based substrate covers the orthographic projection of the pair of transistors on the silicon-based substrate.

[0030] According to some exemplary embodiments, the sum of the thicknesses of the n metal shielding sub-parts meets the following requirements:

[0031] Wherein, δ and ω are respectively the penetration depth and frequency of the radiation irradiated on the metal shielding portion, μ and σ are respectively the magnetic permeability and electrical conductivity of the metal shielding portion, and H is the sum of the thicknesses of the n metal shielding sub-portions.

[0032] In another aspect, a display device is provided, comprising the display substrate as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0034] FIG1 is a schematic diagram of an arrangement of a display substrate on a silicon wafer according to an embodiment of the present disclosure;

[0035] FIG2 is a schematic diagram of various functional areas in a display substrate provided by an embodiment of the present disclosure;

[0036] 3 is a partially enlarged cross-sectional schematic diagram of a sub-pixel of a display substrate provided along line CC' in FIG. 2 according to some embodiments of the present disclosure;

[0037] 4 is a partial cross-sectional schematic diagram of a display substrate provided along line BB′ in FIG. 2 according to some embodiments of the present disclosure, showing the corresponding relationship between the film layers where the first transistor located in the display area AA and the second transistor located in the peripheral area EA are located;

[0038] FIG5 is a schematic cross-sectional view of a single electronic device OTP in a display substrate taken along line DD′ in FIG2 according to some embodiments of the present disclosure;

[0039] FIG6 is an equivalent circuit diagram of the electronic device OTP in FIG5 ;

[0040] 7 is a schematic diagram of charge loss on a floating gate FG in an OTP of a display substrate according to some embodiments of the present disclosure;

[0041] 8 is a partial cross-sectional schematic diagram of an OTP region of a display substrate taken along line DD′ in FIG. 2 according to other embodiments of the present disclosure, showing a metal shielding portion;

[0042] FIG9 is a partial cross-sectional schematic diagram of an OTP region of a display substrate taken along line DD′ in FIG2 according to other embodiments of the present disclosure;

[0043] FIG10 is a partial cross-sectional schematic diagram of a display substrate taken along line BB′ in FIG2 according to some embodiments of the present disclosure, showing the correspondence between the metal film layer in the display area and the film layer where the metal shielding portion is located in the peripheral area;

[0044] FIG11 is a partial cross-sectional schematic diagram of an OTP region of a display substrate taken along line DD′ in FIG2 according to other embodiments of the present disclosure;

[0045] FIG12 is a partial cross-sectional schematic diagram of an OTP region of a display substrate taken along line DD′ in FIG2 according to other embodiments of the present disclosure;

[0046] 13A and 13B are plan views of an OTP region of a display substrate according to some embodiments of the present disclosure;

[0047] FIG14 is a plan view of a metal shielding portion and binding terminals of a display substrate according to other embodiments of the present disclosure;

[0048] FIG15 is a plan view of a top metal shielding sub-portion and a reflective electrode of a display substrate according to other embodiments of the present disclosure;

[0049] FIG16 is a schematic structural diagram of a metal shielding layer corresponding to a single OTP according to some embodiments of the present disclosure;

[0050] FIG17 is a partial cross-sectional schematic diagram of a display substrate taken along line BB′ in FIG2 according to some embodiments of the present disclosure, showing a metal shielding sub-portion and a conductive connection portion located on the same layer;

[0051] FIG18 is a schematic structural diagram of a metal shielding layer corresponding to a single OTP according to other embodiments of the present disclosure;

[0052] FIG19 is a schematic structural diagram of a display device according to some embodiments of the present disclosure.

[0053] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present invention, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0054] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0055] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0056] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by those of ordinary skill in the art. The terms "first," "second," and similar terms used in this disclosure do not denote any order, quantity, or importance, but are simply used to distinguish different components. The terms "include," "comprising," and similar words mean that the element or object preceding the word encompasses the elements or objects listed after the word, and their equivalents, without excluding other elements or objects.

[0057] Unless otherwise specified, directional terms such as "upper," "lower," "left," "right," "inner," and "outer" are used herein to indicate positions or relationships based on the figures shown. These terms are intended solely to facilitate the description of the present disclosure and are not intended to indicate or imply that the devices, components, or parts referred to must have, be constructed, or operate in a specific orientation. It should be understood that when the absolute positions of the objects being described change, the relative positions they represent may also change accordingly. Therefore, these directional terms should not be construed as limiting the present disclosure.

[0058] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0059] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0060] In this document, the directional expressions "first direction" and "second direction" are used to describe different directions along a pixel unit, such as the longitudinal and transverse directions of a pixel unit, or the row and column directions of a sub-pixel arrangement. It should be understood that such expressions are merely exemplary descriptions and are not intended to limit the present disclosure.

[0061] In this document, the term "transistor" may refer to a triode, a thin-film transistor, a field-effect transistor, or other device with similar characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of a transistor other than the control electrode, one electrode is referred to as the first electrode, and the other electrode is referred to as the second electrode. In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode may be the drain electrode, and the second electrode may be the source electrode; alternatively, the first electrode may be the source electrode, and the second electrode may be the drain electrode.

[0062] Some exemplary embodiments of the present disclosure provide a display substrate, the display substrate comprising: a silicon-based substrate, the silicon-based substrate comprising a display area and a peripheral area, the peripheral area surrounding the display area; a plurality of sub-pixels located in the display area of ​​the silicon-based substrate, the plurality of sub-pixels being arrayed in the display area along a first direction and a second direction, at least one of the sub-pixels comprising a pixel driving circuit and a light-emitting element, the pixel driving circuit being electrically connected to the light-emitting element for driving the light-emitting element to emit light, the pixel driving circuit comprising a first transistor, the first transistor comprising a semiconductor layer, a gate, a source, and a drain ... An electronic device in the silicon substrate, the electronic device includes a second transistor, the second transistor includes a semiconductor layer, a gate, a source, and a drain, the semiconductor layer, gate, source, and drain of the second transistor being located on the same layer as the semiconductor layer, gate, source, and drain of the first transistor; and a metal shielding portion located in a peripheral region of the silicon-based substrate, the metal shielding portion being intermittently distributed on a side of the layer where each of the semiconductor layer, gate, source, and drain of the second transistor is located, away from the silicon-based substrate, wherein the orthographic projection of the metal shielding portion on the silicon-based substrate at least partially overlaps with the orthographic projection of the electronic device on the silicon-based substrate. In the display substrate provided in the embodiment of the present disclosure, a metal shielding portion is provided above the electronic device, which can not only shield the electronic device from energy radiation and UV irradiation during the process, thereby maintaining the stability of the electronic device, but also reduce the impact of the reflection of the metal shielding portion on the display effect, and provide process manufacturing uniformity.

[0063] For example, in some exemplary embodiments of the present disclosure, the electronic device may be a one-time programmable device. Thus, by providing a metal shielding portion above the one-time programmable electronic device, the one-time programmable electronic device can be shielded from energy radiation and UV exposure during the silicon-based OLED process, maintaining the stability of the programmable state of the electronic device. This ensures that the electronic device can effectively compensate for the voltage of the pixel unit, improves the brightness uniformity of the display product, and further enhances the display quality of the silicon-based OLED display product.

[0064] Figure 1 is a schematic diagram of the arrangement of display substrates on a silicon wafer, also known as a wafer map, according to an embodiment of the present disclosure. The wafer map schematically illustrates the number and arrangement of display substrates 100 on a silicon wafer 1000. It should be understood that the number and arrangement of display substrates 100 shown in the figure are for illustrative purposes only and do not limit the present disclosure.

[0065] FIG2 is a schematic diagram of various functional areas in a display substrate provided by an embodiment of the present disclosure.

[0066] For example, in some embodiments of the present disclosure, referring to FIG2 , the display substrate 100 includes a silicon-based substrate 200, the silicon-based substrate 200 including a display area (Active Area, AA) and an Edge Area (EA), the Edge Area EA surrounding the display area AA; a plurality of pixel units PX located in the display area AA of the silicon-based substrate, the plurality of pixel units PX being arrayed in the display area AA along a first direction D1 and a second direction D2; a CG (i.e., cover glass) bonding adhesive area located in the peripheral area EA of the silicon-based substrate, the CG bonding adhesive area closely surrounding the display area AA and being used to set an encapsulation layer to seal and protect the display area AA; an electronic device located in the peripheral area EA of the silicon-based substrate, for example, the electronic device may be a one-time programmable device (OTP), and a metal shielding portion 300 located in the peripheral area EA of the silicon-based substrate, wherein the orthographic projection of the metal shielding portion 300 on the silicon-based substrate 200 at least partially overlaps with the orthographic projection of the electronic device OTP on the silicon-based substrate 200. By designing a metal shielding part, the influence of some radiation energy during ion sputtering coating or UV curing on the OTP of electronic devices in the silicon-based OLED display substrate manufacturing process can be shielded, thereby improving the display effect of the display substrate.

[0067] Exemplarily, the display substrate 100 further includes a bonding pad (BP) located in the peripheral area EA of the silicon-based substrate. The bonding pad includes a plurality of bonding terminals 400 . The plurality of bonding terminals 400 are used to provide signal input or output channels for the display substrate.

[0068] 2 , in some embodiments of the present disclosure, the orthographic projection of the metal shielding portion 300 on the silicon substrate 200 is located between the orthographic projections of the plurality of binding terminals 400 on the silicon substrate 200 and the orthographic projection of the display area AA on the silicon substrate 200 .

[0069] In the embodiments of the present disclosure, the display area AA may have various shapes. For example, the display area AA may be provided in various shapes, such as a closed polygon (e.g., a rectangle) with straight sides, a circle or an ellipse with curved sides, or a semicircle or a semiellipse with both straight and curved sides. In the embodiments of the present disclosure, the display area AA is provided as a quadrilateral with straight sides. It should be understood that this is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure.

[0070] The peripheral area EA may surround the outer circumference of the display area AA. In an embodiment of the present disclosure, the peripheral area EA may include a transverse portion extending in the first direction D1 and a longitudinal portion extending in the second direction D2.

[0071] The pixel unit PX is provided in the display area AA. The pixel unit PX is the smallest unit for displaying an image and may be provided in plurality. For example, the pixel unit PX may include a light emitting device that emits white light and / or colored light.

[0072] The pixel cells PX may be provided in a plurality and arranged in a matrix along rows extending in the first direction D1 and columns extending in the second direction D2. However, the embodiments of the present disclosure do not specifically limit the arrangement of the pixel cells PX, and the pixel cells PX may be arranged in various forms. For example, the pixel cells PX may be arranged such that a direction inclined relative to the first direction D1 and the second direction D2 becomes a column direction, and a direction intersecting the column direction becomes a row direction.

[0073] A pixel unit PX may include multiple sub-pixels. For example, a pixel unit PX may include three sub-pixels, namely a first sub-pixel, a second sub-pixel, and a third sub-pixel. For another example, a pixel unit PX may include four sub-pixels, namely a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. For example, the first sub-pixel may be a red sub-pixel, the second sub-pixel may be a green sub-pixel, the third sub-pixel may be a blue sub-pixel, and the fourth sub-pixel may be a white sub-pixel. At least one sub-pixel may include a light-emitting element and a pixel driving circuit for driving the light-emitting element. The pixel driving circuit is electrically connected to the light-emitting element of the corresponding sub-pixel and can drive the light-emitting element of the sub-pixel to emit light of a corresponding color.

[0074] FIG. 3 is a partially enlarged cross-sectional schematic diagram of a sub-pixel of a display substrate taken along line CC′ in FIG. 2 according to some embodiments of the present disclosure.

[0075] For example, in some embodiments of the present disclosure, referring to FIG. 3 , a display substrate includes a sub-pixel located in display area AA. The sub-pixel may include a reflective electrode 106 and a light-emitting element 120 located on the reflective electrode 106. The light-emitting element 120 includes a first electrode layer 122, an organic light-emitting functional layer 124, and a second electrode layer 126, which are sequentially stacked on the reflective electrode 106. The sub-pixel may further include an insulating layer 103 located between the reflective electrode 106 and the first electrode layer 122. The insulating layer 103 is light-transmissive, allowing light emitted by the organic light-emitting functional layer 124 to pass through it and reach the reflective electrode 106 for reflection. The insulating layer 103 separates the reflective electrode 106 from the first electrode layer 122. This allows the reflective electrode 106 to be integrated into a drive substrate manufactured in a wafer fab, reducing the manufacturing cost and difficulty of the reflective electrode 106. Furthermore, when light L emitted by the organic light-emitting functional layer 124 is incident on the first surface 1031 of the insulating layer 103 near the organic light-emitting functional layer 124, due to the light-transmitting properties of the insulating layer 103, the light L can penetrate the first surface 1031 of the insulating layer 103, be emitted from the second surface 1032 of the insulating layer 103 near the reflective electrode 106, and reach the reflective electrode 106. The reflective electrode 106 has a reflective property and reflects the incident light L back to the light-emitting element 120, and ultimately is emitted from the light-emitting element 120. For example, the insulating layer 103 can have high light transmittance, so that the light reflected by the reflective electrode 106 is emitted outward with almost no loss, thereby ensuring high light output brightness and high light extraction efficiency of the display substrate. The insulating layers in multiple sub-pixels can be formed integrally to facilitate manufacturing and reduce the difficulty of the manufacturing process.

[0076] For example, the insulating layer may provide a conductive path for electrically connecting the first electrode layer and the reflective electrode. For example, the insulating layer 103 may include a via 110 filled with a metal member 108, and the reflective electrode 106 is electrically connected to the first electrode layer 122 through the metal member 108. In this way, by forming a conductive channel between the reflective electrode 106 and the first electrode layer 122 in the insulating layer 103, it is beneficial to transmit the signal provided by the pixel circuit in the display device to the first electrode layer 122 through the reflective electrode 106. This not only facilitates the control of the light-emitting element by the pixel circuit, but also makes the structure of the display substrate more compact, which is beneficial to the miniaturization of the device. Furthermore, for example, the metal member 108 is made of a metal material, such as tungsten metal, and the via filled with tungsten metal is also called a tungsten via (W-via). For example, when the insulating layer 103 is relatively thick, forming tungsten vias in the insulating layer 103 can ensure the stability of the conductive path. Furthermore, due to the mature process for forming tungsten vias, the resulting insulating layer 103 has a good surface flatness, which helps reduce the contact resistance between the reflective electrode 106 and the first electrode layer 122. It will be understood that tungsten vias are not only suitable for the electrical connection between the reflective electrode 106 and the first electrode layer 122, but also for the electrical connection between the reflective electrode 106 and the pixel driving circuit, as well as the electrical connection between other wiring layers.

[0077] For example, in some embodiments of the present disclosure, with continued reference to FIG. 3 , the display substrate may further include at least one wiring layer M1, located between the reflective electrode 106 and the silicon-based substrate 200. For example, the wiring layer M1 includes a metal layer, and the pixel driving circuit of the light-emitting element includes a first transistor T1, which includes a semiconductor layer ACT1, a gate G1, a source S1, and a drain D1. The gate G1 of the first transistor T1 is electrically connected to the gate electrode connection portion 102g via a via, the source S1 of the first transistor T1 is electrically connected to the source electrode connection portion 102s via a via, and the drain D1 of the first transistor T1 is electrically connected to the drain electrode connection portion 102d via a via. The gate electrode connection portion 102g, the source electrode connection portion 102s, and the drain electrode connection portion 102d may be located in the same metal layer. For example, the gate electrode connection portion 102g, the source electrode connection portion 102s, and the drain electrode connection portion 102d may all be located in the metal layer included in the wiring layer M1.

[0078] By way of example, continuing with Figure 3 , the reflective electrode 106 may also include a metal layer 105. The metal layer 105 may be made of aluminum or an aluminum alloy, such as an aluminum-copper alloy. Because aluminum or an aluminum-copper alloy has low electrical resistance and high reflectivity, it can improve the brightness and efficiency of light emitted from the display substrate. For example, the thickness of the metal layer 105 ranges from 10 nm to 1000 nm. If the thickness is too low, the reflective effect is insignificant. If the thickness is too high, the overall thickness of the display substrate becomes excessively large. The reflective electrode 106 can be considered the wiring layer M2 of the display substrate.

[0079] For example, the display substrate may further include more metal layers. For example, the display substrate may include a metal layer used as a capacitor plate in a pixel driving circuit or multiple metal layers for routing wires in different film layers in the driving circuit of the display substrate to facilitate wiring design. For example, the metal layers in the display substrate may be 5, 6, 7, or 8 layers. When the display substrate includes multiple metal layers, the wiring layer M2 where the reflective electrode 106 is located is the topmost wiring layer. This simplifies the production of the reflective electrode 106 without destroying the structure of the bottom layer of the display substrate.

[0080] For example, in some embodiments of the present disclosure, with continued reference to FIG3 , the reflective electrode 106 may further include at least one protective layer 104, which is stacked with the metal layer 105 and located on the surface of the metal layer 105 close to the silicon-based substrate 200. In this way, the protective layer 104 can prevent the metal layer 105 from being oxidized. For example, the material of the protective layer is a conductive material, such as titanium nitride (TiN). Since the protective layer 104 is not provided on the surface of the metal layer 105 close to the first electrode layer 122, the light emitted by the organic light-emitting functional layer 124 and passing through the first electrode layer 122 and the insulating layer 103 can be directly incident on the surface of the metal layer 105, thereby reducing the loss of light at the interface and improving the light reflection efficiency and the brightness of the display substrate.

[0081] It should be noted that the configuration and number of the protective layer 104 are not limited to those shown in FIG3 . For example, the reflective electrode may not have a protective layer and may only include a metal layer. Alternatively, two protective layers may be provided, and the two protective layers may be located on both sides of the metal layer.

[0082] It is understood that the aforementioned protective layer can also be applied to other metal layers. For example, referring to FIG3 , protective layers can be provided on both the upper and lower sides of each metal electrode of the gate electrode connection portion 102g, the source electrode connection portion 102s, and the drain electrode connection portion 102d. This effectively prevents oxidation of these electrode connections and improves conductivity. It is understood that other metal layers may not have protective layers or may only have protective layers on one side.

[0083] For example, in some embodiments of the present disclosure, referring to FIG. 2 , the display substrate may further include an electronic device located in the peripheral region of the silicon substrate. In some exemplary embodiments, the electronic device is a one-time programmable (OTP) device. The OTP device is used to compensate the pixel drive circuit of the light-emitting element, improve the brightness uniformity of multiple light-emitting elements in the display substrate, and enhance the display quality of the display substrate.

[0084] 4 is a partial cross-sectional schematic diagram of a display substrate provided along line BB′ in FIG. 2 according to some embodiments of the present disclosure, showing the correspondence between the film layers where the first transistor located in the display area AA and the second transistor located in the peripheral area EA are located.

[0085] For example, in some embodiments of the present disclosure, referring to FIG. 4 , the electronic device OTP is located in the peripheral area EA. The electronic device OTP includes a second transistor T2, which includes a semiconductor layer ACT2, a gate G2, a source S2, and a drain D2. The pixel drive circuit for the light-emitting element is located in the display area AA. The pixel drive circuit includes a first transistor T1 and multiple conductive traces or conductive components. The first transistor T1 includes a semiconductor layer ACT1, a gate G1, a source S1, and a drain D1. The semiconductor layer ACT2, gate G2, source S2, and drain D2 of the second transistor T2 are located on the same layer as the semiconductor layer ACT1, gate G1, source S1, and drain D1 of the first transistor T1, respectively. In other words, the semiconductor layer ACT1 and the semiconductor layer ACT2 are located on the same layer, the gate G1 and the gate G2 are located on the same layer, the source S1 and the source S2 are located on the same layer, and the drain D1 and the drain D2 are located on the same layer. The electronic device OTP and the transistors in the pixel drive circuit can be manufactured on the same layer, saving process steps and simplifying the manufacturing process.

[0086] Figure 5 is a schematic cross-sectional view of a single electronic device OTP in a display substrate according to some embodiments of the present disclosure, taken along line DD' in Figure 2. Figure 6 is an equivalent circuit diagram of the electronic device OTP in Figure 5 .

[0087] For example, in some embodiments of the present disclosure, a one-time programmable electronic device (OTP) in a display substrate may include a pair of transistors connected in series. For example, the OTP may include a second transistor T2 and a third transistor T3, with the second transistor T2 and the third transistor T3 connected in series. For example, the second transistor T2 may be a select transistor with a select gate, and the third transistor T3 may be a storage transistor with a floating gate; or, the second transistor T2 may be a storage transistor with a floating gate, and the third transistor T3 may be a select transistor with a select gate. The floating gate of the storage transistor is configured to store a data bit, where the value of the data bit depends on the amount of charge stored by the floating gate. The select gate of the select transistor is configured to prevent charge leakage from the floating gate. The semiconductor layer, gate, source, and drain of the second transistor T2 are located on the same layer as the semiconductor layer, gate, source, and drain of the third transistor T3, respectively. This means that the second and third transistors can be fabricated on the same layer, saving process steps. The second transistor T2 may be a P-type or N-type doped transistor; and / or the third transistor T3 may be a P-type or N-type doped transistor.

[0088] For example, in some embodiments of the present disclosure, referring to FIG5 , the second transistor T2 is a select transistor and the third transistor T3 is a memory transistor. The select transistor and the memory transistor are arranged on one or more corresponding body regions 206 and are connected in series. The gate electrodes SG and FG of the select transistor and the memory transistor are laterally spaced apart from each other and isolated from the body region 206 by corresponding insulating layers 212 and 214. The select gate SG of the select transistor is electrically connected to the first terminal V of the electronic device OTP. SG , and the floating gate FG of the storage transistor is configured to store a data bit. Whether the bit is a logic "1" or a logic "0" is determined by the amount of charge stored on the floating gate FG.

[0089] The source / drain regions 216, 218, and 220 of the select transistor and the memory transistor, respectively, are arranged in the body region 206 and are located on opposite sides of the select gate SG and the floating gate FG. Furthermore, the source / drain regions 216, 218, and 220 define channel regions 222 and 224 of the select transistor and the memory transistor, respectively. The channel regions 222 and 224 are located below the select gate SG of the select transistor and the floating gate FG of the memory transistor, respectively. The semiconductor layers of the select transistor and the memory transistor are located in their respective channel regions. In some embodiments, the source / drain region 216 of the select transistor alone is electrically connected to the second terminal V of the electronic device OTP. SL , the source / drain region 220 belonging to the storage transistor is electrically connected to the third terminal V of the electronic device OTP BL , the main region 206 is electrically connected to the fourth terminal V of the electronic device OTPNW .

[0090] For example, referring to FIG6, in the programming state, if a certain OTP storage unit is to be programmed, firstly, the first terminal V SG and the third terminal V BL Select the corresponding storage unit, turn on the selection tube (the corresponding first terminal V SG Connect to a high negative potential (e.g. -5V), the fourth terminal V NW and the second terminal V SL Connect gnd), and then connect the third terminal V BL A high negative potential (e.g. -5V) is applied to the floating gate, which will generate a strong pull current in the channel. Due to the hot carrier effect, some electrons will move to the floating gate FG (1 state). If there is no programming, there are no electrons on the floating gate FG (0 state). In the normal reading state, the first terminal V SG and the third terminal V BL Only a relatively low potential such as -1.8V is added. If there is charge on the floating gate FG, the storage unit will have a relatively large current. If there is no charge on the floating gate FG, the current of the entire OTP storage unit is very small. This method is used to determine whether the storage unit of the OTP memory is 1 or 0.

[0091] As mentioned above, after programming, the floating gate FG holds a charge, which we define as 1. However, in the silicon-based OLED display substrate manufacturing process, the charge on the floating gate FG of the one-time programmable electronic device (OTP) can be affected by other process steps, leading to charge loss. This can cause the logic state of the OTP to change, further rendering the corresponding pixel driver circuit ineffective, and thus resulting in defective silicon-based OLED display products.

[0092] FIG. 7 is a schematic diagram illustrating charge loss on a floating gate FG in an OTP of a display substrate according to some embodiments of the present disclosure.

[0093] For example, referring to Figure 7, during the silicon-based OLED production process, the UV radiation used to cure both the CG bonding adhesive and the FPC bonding reinforcement adhesive during packaging may cause the charge in the floating gate FG in the OTP to escape, thereby causing the programming state of the OTP to change, and then causing the OTP compensation to fail, and ultimately causing the silicon-based OLED display product to have an abnormal display or a black screen, seriously affecting the yield of the display product. In addition to the UV radiation energy during UV curing that may cause the charge in the floating gate FG in the OTP to escape, some of the energy radiation during ion sputtering coating on the silicon-based OLED OTP may also cause the charge in the floating gate FG in the OTP to escape.

[0094] In order to reduce or eliminate the impact of energy radiation from ion sputtering coating or energy radiation from UV curing on OTP, a metal shielding portion can be set above the OTP. The metal shielding portion can shield the energy radiation from ion sputtering coating or radiation from UV curing, thereby shielding and protecting the OTP and ensuring the stability of the OTP state.

[0095] FIG. 8 is a partial cross-sectional schematic diagram of an OTP region of a display substrate taken along line DD′ in FIG. 2 according to further embodiments of the present disclosure, wherein a metal shielding portion is shown.

[0096] For example, in some embodiments of the present disclosure, referring to FIG. 8 , the electronic device (OTP) includes a memory cell, which includes a pair of transistors, for example, a second transistor T2 and a third transistor T3, located on the silicon substrate and electrically connected in series. A conductive component is disposed in a layer stacked above the transistor pair and within the interconnect structure of the OTP memory cell. The orthographic projection of the metal shield 300 on the silicon substrate 200 covers the orthographic projection of the pair of transistors on the silicon substrate 200.

[0097] To prevent charge from escaping from the floating gate FG in the OTP, a metal shield 300 is provided above the region where the OTP is located. The metal shield 300 is located in the peripheral region of the silicon-based substrate, and is located on a side of the layer where each of the semiconductor layer, gate, source, and drain of the transistor in the OTP is located that is away from the silicon-based substrate 200. For example, the metal shield 300 is located on a side of the layer where each of the semiconductor layer, gate, source, and drain of the second transistor T2 is located that is away from the silicon-based substrate 200.

[0098] Different designs of the shape, thickness and position of the metal shielding layer will affect the shielding effect, resulting in different protection effects on the OTP of electronic devices.

[0099] For example, in some embodiments of the present disclosure, with continued reference to FIG8 , in order to improve the protective effect of the metal shield on the electronic device OTP, the orthographic projection of the metal shield 300 on the silicon-based substrate can cover the orthographic projection of the electronic device OTP on the silicon-based substrate. By designing the orthographic projection of the metal shield on the silicon-based substrate to cover the orthographic projection of the electronic device OTP on the silicon-based substrate, the shielding protection range of the metal shield for the OTP can be increased, and the partial radiation energy during ion sputtering coating or UV curing can be better shielded, thereby providing better protection for the electronic device OTP, reducing the probability of charge escape in the electronic device OTP, and increasing the stability of the OTP programmable state, thereby improving the display effect of the silicon-based OLED display substrate.

[0100] FIG. 9 is a partial cross-sectional schematic diagram of an OTP region of a display substrate according to other embodiments of the present disclosure.

[0101] For example, in some embodiments of the present disclosure, referring to FIG. 9 , the display substrate further includes n metal film layers, such as metal film layer 1, metal film layer 2, ..., metal film layer n. The n metal film layers are located on a side of the layer where the source and drain electrodes of the electronic device OTP are located, away from the silicon-based substrate 200, and the multiple metal film layers are sequentially away from the silicon-based substrate. n is a positive integer greater than or equal to 2, for example, n can be 5, 6, 7, or 8.

[0102] The metal shielding portion 300 includes n metal shielding sub-portions, each of which is located in the n metal film layers. For example, referring to FIG9 , the metal shielding portion 300 includes metal shielding sub-portion 301, metal shielding sub-portion 302, and metal shielding sub-portion 30n. Metal shielding sub-portion 301 is located in metal film layer 1, metal shielding sub-portion 302 is located in metal film layer 2, and metal shielding sub-portion 30n is located in metal film layer n. By providing multiple metal shielding sub-portions located in different layers, the total thickness of the metal shielding portion can be increased, thereby providing better shielding against energy radiation from sputtering coating or UV curing radiation, better protecting the OTP, and improving the yield of silicon-based OLED display products.

[0103] 10 is a partial cross-sectional schematic diagram of a display substrate taken along line BB′ in FIG. 2 according to some embodiments of the present disclosure, showing the correspondence between the metal film layer in the display area and the film layer where the metal shielding portion is located in the peripheral area.

[0104] For example, in some embodiments of the present disclosure, referring to FIG. 10 , the display substrate further includes n conductive connection portions L located in the display area AA. For example, the conductive connection portions may be conductive components such as traces or connections in a pixel driving circuit. The n conductive connection portions L are respectively located in n metal film layers. For example, the n conductive connection portions include conductive connection portion L1, conductive connection portion L2, ..., conductive connection portion Ln, wherein conductive connection portion L1 is located in metal film layer 1, conductive connection portion L2 is located in metal film layer 2, and conductive connection portion Ln is located in metal film layer n. The n metal shielding sub-portions and the n conductive connection portions may be respectively located in the same metal film layer. For example, the metal shielding sub-portion 301 and the conductive connection portion L1 may both be located in metal film layer 1, the metal shielding sub-portion 302 and the conductive connection portion L2 may both be located in metal film layer 2, and the metal shielding sub-portion 30n and the conductive connection portion Ln may both be located in metal film layer n. The thicknesses of the n metal shielding sub-portions and the n conductive connection portions, respectively located in the same metal film layer, are equal. That is to say, the metal shielding portion can be manufactured in the same process as the metal film layer in the display area, without adding an additional mask, which can save manufacturing costs.

[0105] For example, in some embodiments of the present disclosure, with continued reference to FIG. 10 , the orthographic projections of n metal shielding sub-portions on the silicon-based substrate may at least partially overlap with the orthographic projection of the same electronic device on the silicon-based substrate. For example, the orthographic projection of the metal shielding sub-portion 301 and the electronic device OTP on the silicon-based substrate at least partially overlap, the orthographic projection of the metal shielding sub-portion 302 and the same electronic device OTP on the silicon-based substrate also at least partially overlap, and the orthographic projection of the metal shielding sub-portion 30n and the same electronic device OTP on the silicon-based substrate also at least partially overlap. The orthographic projections of any two of the n metal shielding sub-portions located in the n metal layers on the silicon-based substrate may overlap, for example, the orthographic projections of the metal shielding sub-portion 301 and the metal shielding sub-portion 302 on the silicon-based substrate overlap, the orthographic projections of the metal shielding sub-portion 301 and the metal shielding sub-portion 30n on the silicon-based substrate overlap, and the orthographic projections of the metal shielding sub-portion 302 and the metal shielding sub-portion 30n on the silicon-based substrate overlap. This means that the orthographic projections of n metal shielding sub-sections in different metal film layers on the silicon substrate can be identical in shape and position. By stacking multiple metal shielding sub-sections, the total thickness of the metal shield can be increased, providing better shielding against energy radiation from sputtering or UV curing, further protecting the OTP and improving the yield of silicon-based OLED display products.

[0106] FIG. 11 is a partial cross-sectional schematic diagram of an OTP region of a display substrate taken along line DD′ in FIG. 2 according to some other embodiments of the present disclosure.

[0107] For example, in some embodiments of the present disclosure, the n metal shielding sub-sections may include: a plurality of first metal shielding sub-sections 310 located in the i-th metal film layer; and a plurality of second metal shielding sub-sections 320 located in the i+1-th metal film layer, where i is a positive integer greater than or equal to 1 and less than or equal to n-2. For example, when i is 1, referring to FIG. 11 , the first metal shielding sub-sections 310 may be located in metal film layer 1, and the second metal shielding sub-sections 320 may be located in metal film layer 2. The orthographic projections of the plurality of first metal shielding sub-sections 310 and the orthographic projections of the plurality of second metal shielding sub-sections 320 on the silicon-based substrate are alternately arranged along a first direction D1. The metal shielding sub-sections may include multiple metal shielding sub-sections located in the same metal film layer. For example, the second metal shielding sub-section 320 located in metal film layer 2 may include multiple metal shielding sub-sections, such as metal shielding sub-section 3201 and metal shielding sub-section 3202. Any two adjacent metal shielding sub-sections in the same metal film layer are spaced apart, for example, metal shielding sub-section 3201 and metal shielding sub-section 3202 in second metal shielding sub-section 320 are spaced apart. By segmenting the metal shielding sub-sections in multiple metal film layers, it is possible to avoid the metal shielding sub-sections from agglomerating and resulting in an excessively large area, thereby gathering a large number of charged ions and causing the risk of electrostatic damage to the OTP.

[0108] For example, with continued reference to FIG. 11 , the n metal shielding sub-segments may further include: a plurality of third metal shielding sub-segments 330 located in the (i+2)th metal film layer; the orthographic projections of the plurality of third metal shielding sub-segments 330 on the silicon-based substrate and the orthographic projections of the plurality of second metal shielding sub-segments 320 on the silicon-based substrate are alternately arranged along a first direction D1. By staggering the metal shielding sub-segments in adjacent layers, it is possible to prevent the metal shielding sub-segments from agglomerating and resulting in an excessively large area, thereby concentrating a large number of charged ions and incurring the risk of electrostatic damage (OTP).

[0109] For example, in some embodiments, with continued reference to FIG. 11 , the orthographic projections of the plurality of first metal shielding sub-sections 310 on the silicon-based substrate can overlap with the orthographic projections of the plurality of third metal shielding sub-sections 330 on the silicon-based substrate. By stacking the plurality of metal shielding sub-sections in different metal film layers at varying thicknesses, radiation energy can be prevented from penetrating the shielding layer and damaging the OTP, thereby enhancing the shielding capability of the metal shielding sections and further improving the display quality of the display substrate.

[0110] For example, in some embodiments of the present disclosure, the orthographic projections of at least two of the n metal shield sub-sections located in the n metal film layers on the silicon-based substrate may at least partially not overlap. For example, with continued reference to FIG. 11 , the orthographic projections of the first metal shield sub-section 310 located in metal film layer 1 and one of the metal shield sub-sections 3201 located in metal film layer 2 on the silicon-based substrate may at least partially not overlap.

[0111] Exemplarily, the thicknesses of the n metal shield sub-parts may be equal to each other.

[0112] By staggering the metal shielding sub-sections in adjacent layers, it is possible to avoid the metal shielding sub-sections from agglomerating and resulting in an excessively large area, thereby gathering a large number of charged ions and causing the risk of electrostatic damage to the OTP. The arrangement of the metal shielding sub-sections in adjacent layers can be diverse. For example, different staggered arrangements can be designed to block oblique radiation, thereby improving the shielding effect of the metal shielding sub-sections. It should be noted that the embodiments of the present disclosure do not limit the overlapping area of ​​the metal shielding sub-section directly above the OTP and the metal shielding sub-section directly above the OTP spacing area.

[0113] FIG. 12 is a partial cross-sectional schematic diagram of an OTP region of a display substrate taken along line DD′ in FIG. 2 according to some other embodiments of the present disclosure.

[0114] 12 , in some embodiments of the present disclosure, n metal shield sub-sections in the metal shield section include a first metal shield sub-section 310, a second metal shield sub-section 320, and a third metal shield sub-section 330. An orthographic projection of at least one of the second metal shield sub-sections 320 on the silicon-based substrate partially overlaps with an orthographic projection of an adjacent first metal shield sub-section 310 or third metal shield sub-section 330 on the silicon-based substrate.

[0115] By optimizing the staggered arrangement of the metal shielding sub-parts in multiple metal film layers, the orthographic projection of the metal shielding part on the silicon-based substrate can completely cover the entire OTP area without leaving any gaps. In other words, there is no hollow area within the orthographic projection area of ​​the metal shielding part on the silicon-based substrate, thereby avoiding the occurrence of energy radiation shielding omission areas, improving the shielding effect of the metal shielding part, and benefiting the stability of the OTP and improving the display effect of the display substrate.

[0116] For example, referring again to FIG. 12 , at least two of the n metal shielding sub-sections may have different thicknesses. For example, the first metal shielding sub-section 310 and the third metal shielding sub-section 330 may have different thicknesses. This means that the n metal shielding sub-sections located on different metal film layers can have different thicknesses, facilitating fabrication on the same layer as the metal layer in the display area, eliminating the need for a separate process and reducing costs.

[0117] Exemplarily, in some embodiments of the present disclosure, referring to FIG2 , the display substrate may include m electronic devices OTP and m metal shielding parts 300 , where m is a positive integer greater than or equal to 2;

[0118] The orthographic projections of the m metal shielding parts 300 on the silicon substrate respectively cover the orthographic projections of the m electronic devices OTP on the silicon substrate. The orthographic projections of at least two adjacent metal shielding parts among the m metal shielding parts 300 on the silicon substrate are spaced apart in the first direction D1.

[0119] By providing metal shielding parts for the electronic devices on the display substrate respectively, all electronic devices can be shielded and protected, preventing the OTP of the electronic devices from being affected by radiation, resulting in OTP damage, and causing abnormal display or black screen of the display substrate and other defects.

[0120] 13A and 13B are plan views schematically illustrating an OTP region of a display substrate according to some embodiments of the present disclosure.

[0121] For example, in some embodiments of the present disclosure, the orthographic projections of any two adjacent metal shielding portions among the m metal shielding portions on the silicon-based substrate may at least partially overlap, such that the orthographic projections of the m metal shielding portions on the silicon-based substrate 200 extend continuously in the first direction D1. For example, referring to FIG13A , the orthographic projections of metal shielding portion 300-1 and adjacent metal shielding portion 300-2 on the silicon-based substrate 200 partially overlap. By optimizing the staggered arrangement of the metal shielding sub-portions in the multiple metal film layers, the orthographic projections of the metal shielding portions on the silicon-based substrate can completely cover the entire OTP region S1 without leaving any gaps. In other words, there are no hollow areas within the orthographic projection area of ​​the metal shielding portion on the silicon-based substrate, thereby avoiding the occurrence of energy radiation shielding omission areas, improving the shielding effectiveness of the metal shielding portions, and facilitating the stability of the OTP and the display effect of the display substrate.

[0122] It should be noted that while some embodiments of the present disclosure illustrate a matrix-shaped metal shield, the present disclosure is not limited thereto. For example, referring to FIG13B , the metal shield may also be circular. Similarly, the metal shield may also be elliptical, polygonal, or any other shape. The present disclosure does not limit the shape of the metal shield.

[0123] Any two adjacent metal shielding portions with different shapes can have their orthographic projections on the silicon-based substrate at least partially overlap, so that the orthographic projections of the m metal shielding portions on the silicon-based substrate extend continuously in the first direction, thereby improving the shielding effect of the metal shielding portions, which is beneficial to the stability of the OTP and to improving the display effect of the display substrate.

[0124] FIG. 14 is a plan view schematically showing a metal shielding portion and binding terminals of a display substrate according to other embodiments of the present disclosure.

[0125] For example, in some embodiments of the present disclosure, the metal shield 300 includes multiple metal shield sub-sections located in the same metal film layer as the multiple binding terminals 400. Referring to FIG. 14 , for example, the multiple binding terminals 400 and the multiple metal shield sub-sections may be located in the top metal film layer n, where the multiple metal shield sub-sections may be referred to as 30n. The dimensions d1 of the multiple metal shield sub-sections 30n located in the same metal film layer as the multiple binding terminals 400 in the first direction D1 are substantially equal to the dimensions d2 of the multiple binding terminals 400 in the first direction. Furthermore, the dimensions d3 of the gaps between the multiple metal shield sub-sections 30n located in the same metal film layer as the multiple binding terminals 400 in the first direction are substantially equal to the dimensions d4 of the gaps between the multiple binding terminals in the first direction. Substantially equal means that the ratio of the two dimensions is within the range of 0.8-1.2, for example, d1 / d2 is within the range of 0.8-1.2. The dimensions of the multiple terminals may be the same or different; and / or the gaps between multiple adjacent terminals may be the same or different.

[0126] The dimensions d5 of the metal shielding sub-parts 30n located in the same metal film layer as the binding terminals 400 in the second direction are respectively smaller than the dimensions d6 of the binding terminals 400 in the second direction, that is, d5 is smaller than d6.

[0127] By designing a metal shielding sub-portion on the same metal film layer as the binding terminal to have a size in the first direction that is basically equal to the size of the corresponding binding terminal in the first direction, and a size in the second direction that is smaller than the size of the corresponding binding terminal in the second direction, the etching load of the metal shielding sub-portion on the same metal film layer as the binding terminal and the binding terminal can be balanced, thereby improving etching uniformity.

[0128] FIG. 15 is a plan view schematically showing a top metal shielding sub-portion and a reflective electrode of a display substrate according to other embodiments of the present disclosure.

[0129] For example, in some embodiments of the present disclosure, with reference to FIG3 , FIG10 , and FIG15 , at least one sub-pixel further includes a reflective electrode 106, the reflective electrode 106 being located in a layer between the pixel driving circuit layer and the light-emitting element 120 layer. The metal shield 300 further includes multiple top-layer metal shield sub-layers 30n located in the same layer as the reflective electrode 106. A dimension d9 of each of the multiple top-layer metal shield sub-layers 30n in the first direction D1 is substantially equal to a dimension d7 of each of the multiple reflective electrodes 106 in the first direction. Furthermore, a dimension d10 of each gap between each of the multiple top-layer metal shield sub-layers 30n in the first direction is substantially equal to a dimension d8 of each gap between each of the multiple reflective electrodes in the first direction. "Substantially equal" means that the ratio of the two dimensions is in the range of 0.8-1.2, for example, d7 / d9 is in the range of 0.8-1.2.

[0130] By adopting such a design, the etching load between the reflective electrode and the top metal shielding sub-portion can be balanced, thereby improving etching uniformity.

[0131] For example, in some embodiments of the present disclosure, the binding terminals 400 may be located in the top metal film layer n. Referring to Figures 14 and 15 , the dimension d2 of the plurality of binding terminals in the first direction may be substantially equal to the dimension d7 of the plurality of reflective electrodes 106 in the first direction. This design balances the etching load between the reflective electrodes and the binding terminals, improving etching uniformity.

[0132] It should be noted that the dimensions of the metal shielding sub-sections located in other film layers and the metal traces located in the same layer in the AA region in the first direction may be substantially equal; and / or the spacing between the metal shielding sub-sections located in other film layers and the spacing between the metal traces located in the same layer in the AA region in the first direction may be substantially equal. This design balances the etching load of the metal shielding sub-sections and the metal traces located in the same film layer in the AA region, improving etching uniformity.

[0133] FIG16 is a schematic structural diagram of a metal shielding layer corresponding to a single OTP according to some embodiments of the present disclosure.

[0134] For example, in some embodiments of the present disclosure, referring to FIG. 16 , the display substrate includes n metal film layers, where n is greater than or equal to 3. The n metal film layers include an i-th metal film layer, an i+1-th metal film layer, and an i+2-th metal film layer, where i is greater than or equal to 1 and less than or equal to n-2. The i+1-th metal film layer is located on a side of the i-th metal film layer away from the silicon-based substrate 200, and the i+2-th metal film layer is located on a side of the i+1-th metal film layer away from the silicon-based substrate 200. The display substrate further includes a metal shielding portion 300, which includes: a first metal shielding sub-portion 310 located on the i-th metal film layer; a second metal shielding sub-portion 320 located on the i+1-th metal film layer; and a third metal shielding sub-portion 330 located on the i+2-th metal film layer.

[0135] The edge of the second metal shielding sub-section 320 is retracted relative to the edge of the first metal shielding sub-section 310 toward the center of the electronic device OTP corresponding to both the first metal shielding sub-section 310 and the second metal shielding sub-section 320 (as shown by the dotted line M in the figure), and the edge of the third metal shielding sub-section 330 is retracted relative to the edge of the second metal shielding sub-section 320 toward the center of the electronic device OTP corresponding to both the second metal shielding sub-section 320 and the third metal shielding sub-section 330.

[0136] The metal shielding sub-parts located on multiple metal film layers corresponding to the OTP of the same electronic device are arranged in a stepped manner, which can prevent the top metal shielding sub-part from being close to the cutting path area when the wafer is cut, thereby reducing the risk of ESD damage.

[0137] Exemplarily, in some embodiments of the present disclosure, continuing to refer to Figure 16, the edge of the first metal shielding sub-section 310 may be provided with a raised structure T1, so that the thickness h11 at the edge of the first metal shielding sub-section is greater than the thickness h12 at the center of the first metal shielding sub-section; and / or, the edge of the second metal shielding sub-section 320 is provided with a raised structure, so that the thickness h21 at the edge of the second metal shielding sub-section is greater than the thickness h22 at the center of the second metal shielding sub-section.

[0138] By setting a raised structure on the edge of the bottom metal or the bottom metal and the multi-layer metal above it, the raised structure can block oblique radiation, which is conducive to better blocking the energy of the radiation, improving the shielding effect of the metal shielding layer, and protecting the stability of the OTP programmable state, thereby improving the display effect of silicon-based OLED display products.

[0139] 17 is a partial cross-sectional schematic diagram of the display substrate taken along line BB′ in FIG. 2 according to some embodiments of the present disclosure, showing a metal shielding sub-portion and a conductive connection portion located on the same layer.

[0140] For example, in some embodiments of the present disclosure, the metal shielding portion includes a plurality of metal shielding sub-portions, wherein the edges of some of the metal shielding sub-portions are provided with a raised structure T1. Referring to FIG17 , the shape of the raised structure T1 of some of the metal shielding sub-portions in a cross section perpendicular to the upper surface of the silicon-based substrate 200 is the same as the shape of the conductive connection portion L located in the same layer in a cross section perpendicular to the upper surface of the silicon-based substrate. For example, the cross section of the edge raised structure may be a rectangular or trapezoidal shape, and the cross-sectional shapes of the edge raised structures of different layers may be different. By designing in this way, it is possible to ensure that the metal shielding portion 300 located in the peripheral area EA is manufactured on the same layer as the metal layers of the various layers in the AA area, without the need for special debugging of the etching process in the area where the metal shielding portion is located, which is conducive to simplifying the process flow and saving costs.

[0141] FIG18 is a schematic structural diagram of a metal shielding layer corresponding to a single OTP according to other embodiments of the present disclosure.

[0142] Exemplarily, in some embodiments of the present disclosure, referring to Figure 18, the n metal shielding sub-sections further include: a fourth metal shielding sub-section 340 located in the j-th metal film layer, where j is a positive integer greater than 1 and less than n; the pixel driving circuit further includes a capacitor, at least one plate of which is located in the j-th metal film layer; the thickness h2 of the fourth metal shielding sub-section is less than the thickness of any one of the first metal shielding sub-section h1, the second metal shielding sub-section h3 and the third metal shielding sub-section h4.

[0143] For example, in some embodiments of the present disclosure, the display substrate includes a metal shielding portion, the metal shielding portion includes n metal shielding sub-portions located in n metal film layers, wherein the sum of the thicknesses of the n metal shielding sub-portions meets the following requirements:

[0144] Wherein, δ and ω are respectively the penetration depth and frequency of the radiation rays irradiated on the metal shielding portion, μ and σ are respectively the magnetic permeability and electrical conductivity of the metal shielding portion, and H is the sum of the thicknesses of the n metal shielding sub-parts. For example, the thicknesses of the n metal shielding sub-parts are h1, h2…hn, respectively, so the sum of the thicknesses of the n metal shielding sub-parts H=h1+h2+…+hn. For example, when n is 4, H=h1+h2+h3+h4. By designing the total thickness of the n metal shielding sub-parts located in the n metal film layers to exceed the penetration depth of the radiation rays on the metal shielding portion, the effects of energy radiation and UV irradiation on the OTP of electronic devices can be completely shielded, thereby improving the yield of silicon-based OLED display products.

[0145] It should be noted that in the embodiments of the present disclosure, the metal shield 300 is discontinuously distributed on the side of the layer where each of the semiconductor layer, gate, source, and drain of the second transistor T2 is located, away from the silicon substrate. The term "discontinuously distributed" includes the various situations described in the above embodiments. For example, as shown in conjunction with Figures 2 and 8 , the orthographic projection of the metal shield 300 on the silicon substrate is discontinuously distributed, that is, the metal shield 300 is discontinuously distributed in a direction parallel to the upper surface of the silicon substrate. For another example, referring to Figures 9 , the metal shield 300 is discontinuously distributed in a direction perpendicular to the upper surface of the silicon substrate. For another example, referring to Figures 11 , 12 , and 16-18 , the metal shield 300 is discontinuously distributed both in a direction parallel to the upper surface of the silicon substrate and in a direction perpendicular to the upper surface of the silicon substrate.

[0146] In the display substrate provided in the embodiments of the present disclosure, a metal shield is provided above the electronic device to shield the electronic device from energy radiation and UV exposure during the manufacturing process, maintaining the stability of the electronic device. Furthermore, because the metal shield is distributed intermittently, there are no large or large metal shields, which reduces the impact of reflections from the metal shield on the display effect and improves process uniformity.

[0147] FIG19 is a schematic structural diagram of a display device according to some embodiments of the present disclosure.

[0148] Optionally, embodiments of the present disclosure further provide a display device. Referring to FIG. 19 , this display device 800 may include the aforementioned display substrate 100. The display device may include, but is not limited to, electronic paper, mobile phones, tablet computers, monitors, laptop computers, digital photo frames, navigation systems, and any other product or component with a display function. It should be understood that this display device has the same beneficial effects as the display substrates provided in the aforementioned embodiments.

[0149] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined in the claims and their equivalents.

Claims

1. A display substrate, characterized in that: The display substrate comprises: A silicon-based substrate, the silicon-based substrate comprising a display area and a peripheral area, the peripheral area surrounding the display area; A plurality of sub-pixels located in a display area of ​​the silicon-based substrate, wherein the plurality of sub-pixels are arranged in an array in the display area along a first direction and a second direction, wherein at least one of the sub-pixels comprises a pixel driving circuit and a light-emitting element, wherein the pixel driving circuit is electrically connected to the light-emitting element and is used to drive the light-emitting element to emit light, wherein the pixel driving circuit comprises a first transistor, wherein the first transistor comprises a semiconductor layer, a gate, a source, and a drain; An electronic device located in a peripheral region of the silicon-based substrate, the electronic device comprising a second transistor, the second transistor comprising a semiconductor layer, a gate, a source and a drain, the semiconductor layer, the gate, the source and the drain of the second transistor being located in the same layer as the semiconductor layer, the gate, the source and the drain of the first transistor, respectively; and a metal shielding portion located in a peripheral region of the silicon-based substrate, wherein the metal shielding portion is intermittently distributed on a side of a layer where each of the semiconductor layer, the gate, the source and the drain of the second transistor is located away from the silicon-based substrate, The orthographic projection of the metal shielding portion on the silicon-based substrate at least partially overlaps with the orthographic projection of the electronic device on the silicon-based substrate.

2. The display substrate according to claim 1, wherein: The orthographic projection of the metal shielding portion on the silicon-based substrate covers the orthographic projection of the electronic device on the silicon-based substrate.

3. The display substrate according to claim 1 or 2, wherein: The display substrate further comprises n metal film layers, the n metal film layers are located on a side of the layer where the source and drain of the electronic device are located away from the silicon-based substrate, and the plurality of metal film layers are sequentially away from the silicon-based substrate, and n is a positive integer greater than or equal to 2; and The metal shielding portion includes n metal shielding sub-portions, and the n metal shielding sub-portions are respectively located in the n metal film layers.

4. The display substrate according to claim 3, wherein: The display substrate further comprises n conductive connection parts located in the display area, the n conductive connection parts are respectively located in the n metal film layers, and the n metal shielding sub-parts and the n conductive connection parts are respectively located in the same metal film layer.

5. The display substrate according to claim 4, wherein: The metal shielding part comprises a plurality of metal shielding sub-parts located in the same metal film layer, and any two adjacent metal shielding sub-parts located in the same metal film layer are arranged at intervals.

6. The display substrate according to any one of claims 3 to 5, wherein: The orthographic projections of the n metal shielding sub-portions on the silicon-based substrate at least partially overlap with the orthographic projection of the same electronic device on the silicon-based substrate; as well as The orthographic projections of any two of the n metal shielding sub-portions on the silicon-based substrate coincide with each other.

7. The display substrate according to any one of claims 3 to 5, wherein: Orthographic projections of at least two of the n metal shielding sub-portions on the silicon-based substrate at least partially do not overlap.

8. The display substrate according to any one of claims 3 to 5, wherein: The n metal shielding sub-sections include: a plurality of first metal shielding sub-sections located in the i-th metal film layer; and a plurality of second metal shielding sub-sections located in the i+1-th metal film layer, wherein i is a positive integer greater than or equal to 1 and less than or equal to n-2; and The orthographic projections of the plurality of first metal shield sub-portions on the silicon-based substrate and the orthographic projections of the plurality of second metal shield sub-portions on the silicon-based substrate are alternately arranged along a first direction.

9. The display substrate according to claim 8, wherein: The n metal shielding sub-portions further include: a plurality of third metal shielding sub-portions located in the (i+2)th metal film layer; and The orthographic projections of the plurality of third metal shield sub-portions on the silicon-based substrate and the orthographic projections of the plurality of second metal shield sub-portions on the silicon-based substrate are alternately arranged along a first direction.

10. The display substrate according to claim 9, wherein: An orthographic projection of at least one of the second metal shield sub-portions on the silicon-based substrate partially overlaps with an orthographic projection of an adjacent first metal shield sub-portion or a third metal shield sub-portion on the silicon-based substrate.

11. The display substrate according to claim 10, wherein: The orthographic projections of the plurality of first metal shielding sub-portions on the silicon-based substrate respectively coincide with the orthographic projections of the plurality of third metal shielding sub-portions on the silicon-based substrate.

12. The display substrate according to any one of claims 1 to 11, wherein: The display substrate includes m electronic devices and m metal shielding parts, wherein m is a positive integer greater than or equal to 2; and The orthographic projections of the m metal shielding parts on the silicon-based substrate respectively cover the orthographic projections of the m electronic devices on the silicon-based substrate.

13. The display substrate according to claim 12, wherein: Orthographic projections of at least two adjacent metal shielding portions among the m metal shielding portions on the silicon-based substrate are arranged at intervals in the first direction.

14. The display substrate according to claim 12, wherein: The orthographic projections of any two adjacent metal shielding portions among the m metal shielding portions on the silicon-based substrate at least partially overlap, so that the orthographic projections of the m metal shielding portions on the silicon-based substrate extend continuously in the first direction.

15. The display substrate according to any one of claims 3 to 5, wherein: At least two of the n metal shielding sub-parts have unequal thicknesses; or, The thicknesses of the n metal shielding sub-parts are equal to each other.

16. The display substrate according to claim 4, wherein: The thicknesses of the n metal shielding sub-parts and the n conductive connecting parts respectively located in the same metal film layer are equal to each other.

17. The display substrate according to any one of claims 1 to 16, wherein: The display substrate further includes a plurality of binding terminals located in a peripheral region of the silicon-based substrate, and an orthographic projection of the metal shielding portion on the silicon-based substrate is located between an orthographic projection of the plurality of binding terminals on the silicon-based substrate and the display region.

18. The display substrate according to claim 17, wherein: The metal shielding portion comprises a plurality of metal shielding sub-portions located in the same metal film layer as the plurality of binding terminals, and the sizes of the plurality of metal shielding sub-portions located in the same metal film layer as the plurality of binding terminals in the first direction are substantially equal to the sizes of the plurality of binding terminals in the first direction; and / or, The sizes of the gaps between the plurality of metal shielding sub-parts located in the same metal film layer as the plurality of binding terminals in the first direction are substantially equal to the sizes of the gaps between the plurality of binding terminals in the first direction; and / or, The dimensions of the plurality of metal shielding sub-parts located on the same metal film layer as the plurality of binding terminals in the second direction are are respectively smaller than the dimensions of the plurality of binding terminals in the second direction.

19. The display substrate according to any one of claims 1 to 18, wherein: At least one of the sub-pixels further includes a reflective electrode, and the film layer where the reflective electrode is located is located between the film layer where the pixel driving circuit is located and the film layer where the light-emitting element is located; The metal shielding portion further comprises a plurality of top-layer metal shielding sub-portions located at the same layer as the reflective electrode; as well as The sizes of the plurality of top-layer metal shielding sub-portions in the first direction are substantially equal to the sizes of the plurality of reflective electrodes in the first direction; And / or, the sizes of the gaps between the plurality of top-layer metal shielding sub-portions in the first direction are substantially equal to the sizes of the gaps between the plurality of reflective electrodes in the first direction.

20. The display substrate according to claim 9, wherein: The i+1th metal film layer is located on a side of the i-th metal film layer away from the silicon-based substrate, and the i+2th metal film layer is located on a side of the i+1th metal film layer away from the silicon-based substrate; as well as The edge of the second metal shielding sub-section is retracted toward the center of the electronic device corresponding to both the first metal shielding sub-section and the second metal shielding sub-section relative to the edge of the first metal shielding sub-section, and the edge of the third metal shielding sub-section is retracted toward the center of the electronic device corresponding to both the second metal shielding sub-section and the third metal shielding sub-section relative to the edge of the second metal shielding sub-section.

21. The display substrate according to any one of claims 9 to 11 and 20, wherein: The edge of the first metal shielding sub-portion is provided with a protruding structure, so that the thickness at the edge of the first metal shielding sub-portion is greater than the thickness at the center of the first metal shielding sub-portion; and / or, The edge of the second metal shielding sub-portion is provided with a protruding structure, so that the thickness at the edge of the second metal shielding sub-portion is greater than the thickness at the center of the second metal shielding sub-portion.

22. The display substrate according to claim 21, wherein: The shape of the protruding structure in a cross section perpendicular to the upper surface of the silicon-based substrate is the same as the shape of the conductive connecting portion located in the same layer in a cross section perpendicular to the upper surface of the silicon-based substrate.

23. The display substrate according to any one of claims 9 to 11, 21 and 22, wherein: The n metal shielding sub-sections further include: a fourth metal shielding sub-section located in the j-th metal film layer, where j is a positive integer greater than 1 and less than n; The pixel driving circuit further comprises a capacitor, at least one electrode plate of the capacitor is located in the j-th metal film layer; and The thickness of the fourth metal shield sub-portion is smaller than the thickness of any one of the first metal shield sub-portion, the second metal shield sub-portion, and the third metal shield sub-portion.

24. The display substrate according to any one of claims 1 to 23, wherein: The electronic device includes a memory cell, the memory cell includes a pair of transistors, the pair of transistors are located on the silicon-based substrate and are electrically connected in series; as well as The orthographic projection of the metal shielding portion on the silicon-based substrate covers the orthographic projection of the pair of transistors on the silicon-based substrate.

25. The display substrate according to any one of claims 3 to 24, wherein: The sum of the thicknesses of the n metal shielding sub-parts meets the following requirements: Wherein, δ and ω are respectively the penetration depth and frequency of the radiation rays irradiated on the metal shielding part, μ and σ are respectively the magnetic permeability and electrical conductivity of the metal shielding part, and H is the sum of the thicknesses of the n metal shielding sub-parts.

26. A display device, wherein: The display device comprises the display substrate as described in any one of the above items.

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