Array substrate and display device

Abstract

The invention provides an array substrate and a display device. The array substrate comprises a plurality of first wires and a plurality of second wires which are arranged on a substrate, the first wires and the second wires intersect with each other to define a plurality of pixel areas, and each pixel area comprises a transistor, a first electrode, a second electrode, a first via hole and a second via hole; the orthographic projection of the first via hole on the substrate is at least partially overlapped with the orthographic projection of the first electrode on the substrate, and the orthographic projection of the second via hole on the substrate is at least partially overlapped with the orthographic projection of the first electrode on the substrate; the orthographic projection of the first via hole on the substrate is not overlapped with the orthographic projection of the second electrode on the substrate, and the orthographic projection of the second via hole on the substrate is not overlapped with the orthographic projection of the second electrode on the substrate. According to the invention, the on-state current of the transistor can be improved.

Description

Array substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] In the existing oxide (Oxide) BCE (Back-channel Etch) process, the gate insulation layer is located between the source / drain metal layer and the gate metal layer. Since both the source / drain metal layer and the gate metal layer are metal layers, the thickness of the gate insulation layer cannot be further reduced at current mass production levels. Otherwise, the risk of ESD (electrostatic discharge) between the gate metal layer and the source / drain metal layer will increase. The on-state current of the transistor is inversely proportional to the thickness of the gate insulation layer. The thicker the gate insulation layer, the lower the on-state current of the transistor. Therefore, the on-state current of BCE transistors cannot be further increased due to the thickness of the gate insulation layer.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present invention provides an array substrate, comprising a plurality of first routing lines and a plurality of second routing lines disposed on a substrate, the first routing lines and the second routing lines intersecting to define a plurality of pixel regions, each of the pixel regions comprising a transistor, a first electrode, a second electrode, a first via hole, and a second via hole; an orthographic projection of the first via hole on the substrate at least partially overlaps with an orthographic projection of the first electrode on the substrate, and an orthographic projection of the second via hole on the substrate at least partially overlaps with an orthographic projection of the first electrode on the substrate;

[0005] The orthographic projection of the first via hole on the substrate does not overlap with the orthographic projection of the second electrode on the substrate, and the orthographic projection of the second via hole on the substrate does not overlap with the orthographic projection of the second electrode on the substrate.

[0006] Optionally, the first via hole and the second via hole are located in the same pixel area;

[0007] Another pixel region adjacent to the pixel region includes a third via hole;

[0008] An orthographic projection of the second via hole on the substrate and an orthographic projection of the third via hole on the substrate are located on opposite sides of an orthographic projection of the first trace on the substrate.

[0009] Optionally, the transistor includes an active pattern;

[0010] The orthographic projection of the second via on the substrate at least partially overlaps with the orthographic projection of the first conductor portion of the active pattern on the substrate; the second via is used to electrically connect the first electrode of the transistor and the first conductor portion of the active pattern;

[0011] A portion of the first electrode falls into the first via hole, and the first via hole is used to electrically connect the first electrode and the first conductor portion included in the active pattern.

[0012] Optionally, the orthographic projection of the third via on the substrate at least partially overlaps with the orthographic projection of the second conductor portion included in the active pattern on the substrate; the third via is used to electrically connect the second electrode of the transistor with the second conductor portion of the active pattern.

[0013] Optionally, along the first direction, the minimum distance between the orthographic projection of the first via on the substrate and the orthographic projection of the first trace on the substrate is smaller than the minimum distance between the orthographic projection of the second via on the substrate and the orthographic projection of the first trace on the substrate.

[0014] Optionally, the active pattern is dumbbell-shaped; and an angle between an orthographic projection of the active pattern on the substrate and an orthographic projection of the first trace on the substrate is greater than or equal to 85 degrees and less than or equal to 95 degrees.

[0015] Optionally, the second wiring includes a second wiring body, a first auxiliary portion, and a second auxiliary portion;

[0016] The first auxiliary portion is electrically connected to the second wiring body, and the second auxiliary portion is in a floating state;

[0017] The first auxiliary portion is electrically connected to the second conductor portion included in the active pattern, and the second auxiliary portion is electrically connected to the first electrode.

[0018] Optionally, the array substrate includes 3a second wirings and 2a third wirings; a is a positive integer;

[0019] The two third routing lines correspond to the three second routing lines, and the orthographic projections of the third routing lines on the substrate at least partially overlap with the orthographic projection of one of the three second routing lines on the substrate.

[0020] Optionally, the array substrate includes 3a second wirings and a third wiring; a is a positive integer;

[0021] One of the third routing lines corresponds to three of the second routing lines, and an orthographic projection of the third routing line on the substrate at least partially overlaps with an orthographic projection of one of the three second routing lines on the substrate.

[0022] Optionally, the array substrate further includes a third trace;

[0023] The third trace includes a signal line main body portion and a connecting portion electrically connected to each other;

[0024] An orthographic projection of the connecting portion on the substrate at least partially overlaps with an orthographic projection of the second via hole on the substrate.

[0025] Optionally, the array substrate further includes a light-shielding pattern; the light-shielding pattern and the third trace are arranged in different layers;

[0026] The orthographic projection of the connecting portion on the substrate at least partially overlaps with the orthographic projection of the light-shielding pattern on the substrate.

[0027] Optionally, the array substrate further includes a light-shielding pattern;

[0028] The orthographic projection of the light-shielding pattern on the substrate covers the orthographic projection of the conductor portion of the active pattern of the transistor on the substrate.

[0029] Optionally, the array substrate includes a first metal layer, a second metal layer, a semiconductor layer and a first insulating layer;

[0030] The transistor includes an active pattern, a first gate, a first electrode and a second electrode;

[0031] The first gate is formed in the first metal layer, the first electrode and the second electrode are formed in the second metal layer, and the active pattern is located in the semiconductor layer;

[0032] The first insulating layer is provided between the first metal layer and the semiconductor layer;

[0033] The thickness of the first insulating layer is less than a first thickness threshold; the first thickness threshold is greater than or equal to 800 angstroms and less than or equal to 2000 angstroms;

[0034] The first metal layer is disposed on a side of the semiconductor layer away from the substrate.

[0035] Optionally, the thickness of the first insulating layer is greater than or equal to 500 angstroms and less than or equal to 2000 angstroms.

[0036] Optionally, the active pattern includes a semiconductor portion; the semiconductor portion includes a first semiconductor portion and a second semiconductor portion stacked together;

[0037] The first semiconductor portion is disposed between the second semiconductor portion and the substrate, and the first semiconductor portion and the second semiconductor portion are made of semiconductor materials with different carrier mobilities.

[0038] Optionally, the array substrate further includes a third metal layer and a second insulating layer;

[0039] The third metal layer is disposed between the semiconductor layer and the substrate, and the second insulating layer is disposed between the semiconductor layer and the third metal layer;

[0040] The third metal layer includes a light-shielding pattern, and an orthographic projection of the light-shielding pattern on the substrate covers an orthographic projection of a semiconductor portion in the active pattern on the substrate.

[0041] Optionally, the active pattern extends along a first direction;

[0042] The maximum distance between an edge of an orthographic projection of the light-shielding pattern on the substrate and an edge of an orthographic projection of the active pattern on the substrate along the second direction is greater than a first distance threshold;

[0043] The first distance threshold is greater than or equal to 4 μm; and the first direction intersects the second direction.

[0044] Optionally, the shading pattern is multiplexed as the second gate of the switching transistor.

[0045] Optionally, the array substrate further includes a fourth metal layer; the first electrode is formed on the fourth metal layer; the fourth metal layer is arranged on a side of the second metal layer away from the substrate;

[0046] The first electrode is electrically connected to the second electrode of the transistor through a first via hole;

[0047] An orthographic projection area of ​​the first via hole on the substrate is greater than or equal to 6 μm×7 μm and less than or equal to 8 μm×10 μm.

[0048] Optionally, the array substrate further includes a fifth metal layer; the second electrode is formed on the fifth metal layer; and the fifth metal layer is disposed between the fourth metal layer and the second metal layer;

[0049] The shortest distance between the orthographic projection of the second electrode on the substrate and the edge of the orthographic projection of the first via hole on the substrate is greater than a second distance threshold;

[0050] The second distance threshold is greater than 2 μm.

[0051] Optionally, the shortest distance between an orthographic projection of the first electrode on the substrate and an edge of an orthographic projection of the first via hole on the substrate is greater than a third distance threshold;

[0052] The third distance threshold is greater than or equal to 1.6 μm.

[0053] Optionally, the array substrate further includes a fifth metal layer and a sixth metal layer, the fifth metal layer being disposed on a side of the second metal layer away from the substrate, and the sixth metal layer being disposed on a side of the fifth metal layer away from the substrate;

[0054] The array substrate includes a third trace;

[0055] The third trace is formed on the sixth metal layer, and the second electrode is formed on the fifth metal layer;

[0056] The array substrate further includes a fourth metal layer, a third insulating layer disposed between the sixth metal layer and the fifth metal layer, and a fourth insulating layer disposed between the sixth metal layer and the fourth metal layer; the fourth metal layer is disposed on a side of the sixth metal layer away from the substrate;

[0057] The array substrate includes a first conductive pattern formed on the fourth metal layer;

[0058] The first conductive pattern is electrically connected to the third trace through the fourth via, and the first conductive pattern is electrically connected to the second electrode through the fourth via and the fifth via, so that the third trace is electrically connected to the second electrode;

[0059] The fourth via hole is a via hole that passes through the fourth insulating layer, and the fifth via hole is a via hole that passes through the third insulating layer;

[0060] An orthographic projection area of ​​the fourth via hole on the substrate is greater than or equal to 3 μm×6 μm and less than or equal to 5 μm×8 μm.

[0061] Optionally, the array substrate includes a sixth metal layer; the array substrate includes a third trace, and the third trace is formed in the sixth metal layer;

[0062] The third wiring includes a signal line main body portion and a connecting portion that are interconnected;

[0063] The orthographic projection of the connecting portion on the base covers the orthographic projection of the spacer portion on the base, and the connecting portion is used to support the spacer portion;

[0064] The array substrate is included in a display device, which includes a color filter substrate. The spacer portion is disposed between the color filter substrate and the array substrate.

[0065] Optionally, the array substrate according to at least one embodiment of the present invention further includes a driving module disposed on the base; the driving module is disposed in the peripheral area;

[0066] The driving module includes a multi-stage driving circuit; the driving circuit is used to provide a driving signal for the pixel circuit;

[0067] The driving circuit includes an input circuit, a reset circuit and a first node control circuit;

[0068] The input circuit is electrically connected to the input control terminal, the input terminal and the first node respectively, and is used to write the input signal provided by the input terminal into the first node under the control of the input control signal provided by the input control terminal;

[0069] The reset circuit is electrically connected to the reset line, the first node and the first voltage line respectively, and is used to control the connection between the first node and the first voltage line under the control of the reset signal provided by the reset line;

[0070] The first node control circuit is electrically connected to the first second node, the second second node, the second voltage line and the first node, respectively, and is used to control the connection between the first node and the second voltage line under the control of the potential of the first second node, and to control the connection between the first node and the second voltage line under the control of the potential of the second second node.

[0071] Optionally, the driving circuit further includes a frame reset circuit;

[0072] The frame reset circuit is electrically connected to the frame reset line, the first node and the second voltage line respectively, and is used to control the connection between the first node and the second voltage line under the control of the frame reset signal provided by the frame reset line.

[0073] Optionally, the input circuit includes a first transistor and a second transistor;

[0074] The gate of the first transistor and the gate of the second transistor are electrically connected to the input control terminal, the first electrode of the first transistor is electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the control node;

[0075] A first electrode of the second transistor is electrically connected to the control node, and a second electrode of the second transistor is electrically connected to the first node.

[0076] Optionally, the driving circuit further includes a control circuit;

[0077] The control circuit is electrically connected to the control node, the first node and the third voltage line respectively, and is used to control the connection between the control node and the third voltage line under the control of the potential of the first node.

[0078] Optionally, the input terminal and the input control terminal are the same signal terminal, and the input terminal is the carry signal output terminal of the adjacent previous n stages; or,

[0079] The input terminal is the carry signal output terminal of the adjacent n previous stages, and the input control terminal is the drive signal output terminal of the adjacent n previous stages;

[0080] n is a positive integer.

[0081] Optionally, the reset circuit includes a third transistor and a fourth transistor, and the first node control circuit includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor;

[0082] The gates of the third transistor and the fourth transistor are both electrically connected to the reset line, the first electrode of the third transistor is electrically connected to the first node, the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor; and the second electrode of the third transistor is electrically connected to the control node;

[0083] The second electrode of the fourth transistor is electrically connected to the first voltage line;

[0084] The gate of the fifth transistor and the gate of the sixth transistor are both electrically connected to the first second node, the first electrode of the fifth transistor is electrically connected to the first node, the second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor; the second electrode of the fifth transistor is electrically connected to the control node;

[0085] The second electrode of the sixth transistor is electrically connected to the second voltage line;

[0086] The gate of the seventh transistor and the gate of the eighth transistor are both electrically connected to the second second node, the first electrode of the seventh transistor is electrically connected to the first node, the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor; and the second electrode of the seventh transistor is electrically connected to the control node;

[0087] A second electrode of the eighth transistor is electrically connected to the second voltage line.

[0088] Optionally, the frame reset circuit includes a ninth transistor and a tenth transistor;

[0089] The gate of the ninth transistor is electrically connected to the frame reset line, the first electrode of the ninth transistor is electrically connected to the first node, the second electrode of the ninth transistor is electrically connected to the first electrode of the tenth transistor; and the second electrode of the ninth transistor is electrically connected to the control node;

[0090] A second electrode of the tenth transistor is electrically connected to the second voltage line.

[0091] Optionally, the driving circuit further includes a storage capacitor and a driving signal output terminal; the first plate of the storage capacitor is electrically connected to the first node, and the second plate of the storage capacitor is electrically connected to the driving signal output terminal.

[0092] Optionally, the array substrate further includes a third metal layer and a second insulating layer; the third metal layer is disposed on a side of the semiconductor layer close to the substrate, and the second insulating layer is disposed between the semiconductor layer and the third metal layer;

[0093] The first electrode plate is formed on the first metal layer, and the second electrode plate includes a first electrode plate portion and a second electrode plate portion electrically connected to each other;

[0094] The first electrode plate is partially formed on the second metal layer, and the second electrode plate is partially formed on the third metal layer;

[0095] An orthographic projection of the first electrode plate on the substrate, an orthographic projection of the first electrode plate portion on the substrate, and an orthographic projection of the second electrode plate portion on the substrate at least partially overlap.

[0096] Optionally, the first electrode plate includes a first first electrode plate portion, a second first electrode plate portion and a third first electrode plate portion;

[0097] The first electrode portion includes a first second electrode portion, a second second electrode portion, and a third second electrode portion that are electrically connected to each other;

[0098] The second electrode plate portion includes a first third electrode plate portion, a second third electrode plate portion and a third third electrode plate portion;

[0099] The first first electrode portion, the second first electrode portion, and the third first electrode portion are all formed on a first metal layer, the first second electrode portion, the second second electrode portion, and the third second electrode portion are all formed on a second metal layer, and the first third electrode portion, the second third electrode portion, and the third third electrode portion are all formed on a third metal layer;

[0100] The orthographic projection of the first electrode plate portion on the substrate, the orthographic projection of the first second electrode plate portion on the substrate, and the orthographic projection of the first third electrode plate portion on the substrate at least partially overlap;

[0101] The orthographic projection of the second first electrode portion on the substrate, the orthographic projection of the second second electrode portion on the substrate, and the orthographic projection of the second third electrode portion on the substrate at least partially overlap;

[0102] The orthographic projection of the third first electrode plate portion on the substrate, the orthographic projection of the third second electrode plate portion on the substrate, and the orthographic projection of the third third electrode plate portion on the substrate at least partially overlap.

[0103] Optionally, the driving circuit includes a driving output circuit and a carry output circuit;

[0104] The drive output circuit is used to control the output of the drive signal under the control of the potential of the first node; the carry output circuit is used to control the output of the carry signal under the control of the potential of the first node;

[0105] The orthographic projection of the active pattern of the transistor included in the driving output circuit on the substrate and the orthographic projection of the first electrode portion on the substrate are arranged along a first direction;

[0106] The active pattern of the transistor included in the carry output circuit is arranged on a side of the active pattern of the transistor included in the drive output circuit close to the display area;

[0107] The orthographic projection of the second first electrode portion on the substrate is arranged on a side of the orthographic projection of the active pattern of the transistor included in the carry output circuit on the substrate close to the display area;

[0108] An orthographic projection of the third first electrode portion on the substrate and an active pattern of a transistor included in the first node control circuit are arranged along a first direction.

[0109] Optionally, the peripheral area includes a fan-out area and a gate transistor setting area arranged between the fan-out area and the display area;

[0110] The array substrate includes M gate control lines and a gate portion provided in the gate transistor setting area; the gate portion includes a plurality of gate parts; M is an integer greater than 1;

[0111] The gating part includes multiple gating transistors; the gates of the multiple gating transistors are electrically connected to the corresponding gating control lines, the first electrodes of the multiple gating transistors are electrically connected to the corresponding data voltage supply lines, and the second electrodes of the multiple gating transistors are electrically connected to the corresponding data lines.

[0112] Optionally, the peripheral area further includes an integrated circuit arrangement area arranged in the fan-out area away from the display area;

[0113] The array substrate includes a driving integrated circuit and a plurality of gate control signal supply lines arranged in the integrated circuit arrangement area;

[0114] an mth gate control signal supply line electrically connected to the driving integrated circuit and the mth gate control line, respectively, for receiving the mth gate control signal from the driving integrated circuit and providing the mth gate control signal to the mth gate control line;

[0115] m is a positive integer less than or equal to M.

[0116] Optionally, the peripheral area further includes an integrated circuit arrangement area arranged in the fan-out area away from the display area; the array substrate includes a driving integrated circuit arranged in the integrated circuit arrangement area;

[0117] The array substrate includes a touch signal line arranged in the display area;

[0118] The data voltage supply line is electrically connected to the driver integrated circuit via a first connection line provided in the fan-out region, and is used for receiving a data voltage provided by the driver integrated circuit;

[0119] The touch signal line is electrically connected to the driver integrated circuit via a second connection line provided in the fan-out area, and is used for receiving a touch sensing signal provided by the driver integrated circuit.

[0120] Optionally, the array substrate further includes a sixth metal layer;

[0121] The second connecting line is formed in the sixth metal layer.

[0122] Optionally, part of the first connecting lines is formed in the first metal layer, and another part of the first connecting lines is formed in the second metal layer.

[0123] Optionally, the array substrate further includes a third metal layer; the third metal layer is disposed on a side of the semiconductor layer close to the substrate;

[0124] A portion of the first connecting line is formed in the first metal layer, another portion of the first connecting line is formed in the second metal layer, and another portion of the first connecting line is formed in the third metal layer.

[0125] Optionally, in the region where the gate transistor is provided, the array substrate further comprises a third metal layer; the third metal layer is provided on a side of the semiconductor layer close to the substrate;

[0126] In the selection transistor setting area, the conductive pattern on the third metal layer is in a floating state.

[0127] Optionally, the array substrate further includes a touch signal line;

[0128] The touch signal line is formed on the second metal layer;

[0129] The array substrate further includes a fourth metal layer, a fifth metal layer and a sixth metal layer;

[0130] The sixth metal layer is disposed on a side of the second metal layer away from the substrate, and the fifth metal layer is disposed between the second metal layer and the sixth metal layer;

[0131] The touch signal line is electrically connected to the second conductive pattern formed on the fourth metal layer through the sixth via hole; the second conductive pattern is electrically connected to the common electrode formed on the fifth metal layer.

[0132] Optionally, the data voltage supply line is electrically connected to the driver integrated circuit via a first connection line provided in the fan-out region; the touch signal line is electrically connected to the driver integrated circuit via a second connection line provided in the fan-out region; the array substrate further comprises a third metal layer; the third metal layer is provided on a side of the semiconductor layer close to the substrate; the second connection line is formed in the second metal layer;

[0133] A portion of the first connecting line is formed in the first metal layer, and another portion of the first connecting line is formed in the third metal layer.

[0134] In a second aspect, an embodiment of the present invention provides a display device including the above-mentioned array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0135] 1A and 1B are plan layout diagrams of parts of an array substrate according to at least one embodiment of the present invention;

[0136] FIG2 is a BB′ cross-sectional view of the array substrate according to at least one embodiment of the present invention shown in FIG1A ;

[0137] 3 is a BB' cross-sectional view of the array substrate according to at least one embodiment of the present invention shown in FIG1A;

[0138] FIG4 is a BB′ cross-sectional view of the array substrate according to at least one embodiment of the present invention shown in FIG1A ;

[0139] 5 is a BB' cross-sectional view of the array substrate according to at least one embodiment of the present invention shown in FIG1A;

[0140] FIG6 is a layout diagram of the third metal layer in FIG1A ;

[0141] FIG7 is a layout diagram of the semiconductor layer in FIG1A;

[0142] FIG8 is a layout diagram of the sixth metal layer in FIG1A;

[0143] FIG9 is a layout diagram of the fifth metal layer in FIG1A ;

[0144] FIG10 is a layout diagram of the fourth metal layer in FIG1A ;

[0145] FIG11 is a layout diagram of the first metal layer in FIG1A ;

[0146] FIG12 is a layout diagram of the second metal layer in FIG1A;

[0147] FIG13 is a stack diagram of the third metal layer and the semiconductor layer in FIG1A;

[0148] FIG14 is a BB′ cross-sectional view of the array substrate according to at least one embodiment of the present invention shown in FIG1A ;

[0149] FIG15 is a BB' cross-sectional view of the array substrate according to at least one embodiment of the present invention shown in FIG1A;

[0150] FIG16 is a BB′ cross-sectional view of the array substrate according to at least one embodiment of the present invention shown in FIG1A ;

[0151] FIG17 is a cross-sectional view of FIG1B 'CC;

[0152] FIG18 is a CC' cross-sectional view in FIG1B;

[0153] FIG19 is a cross-sectional view of FIG1B 'CC;

[0154] FIG20 is an overlay diagram of the third metal layer and the sixth metal layer in FIG1A ;

[0155] FIG21 is a layout diagram of an array substrate according to at least one embodiment of the present invention;

[0156] FIG22 is a layout diagram of the third metal layer in FIG21;

[0157] FIG23 is a layout diagram of the semiconductor layer in FIG21;

[0158] FIG24 is a layout diagram of the first metal layer in FIG21;

[0159] 25A and 25B are layout diagrams of the second metal layer in FIG. 21 ;

[0160] FIG26 is a layout diagram of the fifth metal layer in FIG21;

[0161] 27A and 27B are layout diagrams of the sixth metal layer in FIG. 21 ;

[0162] FIG28 is a layout diagram of the fourth metal layer in FIG21;

[0163] FIG29 is a block diagram of at least one embodiment of a driving circuit;

[0164] FIG30 is a block diagram of at least one embodiment of a driving circuit;

[0165] FIG31 is a circuit diagram of at least one embodiment of a driving circuit;

[0166] FIG32 is a waveform diagram of the potential of the first node PU in the LH well during operation of at least one embodiment of the driving circuit shown in FIG31 ;

[0167] FIG. 33 is a structural diagram of at least one embodiment of a storage capacitor.

[0168] FIG34 is a cross-sectional view of AA′ in FIG33 ;

[0169] FIG35 is a layout diagram of at least one embodiment of the two-stage driver circuit shown in FIG31;

[0170] FIG36 is a layout diagram of the third metal layer in FIG35;

[0171] FIG37 is a layout diagram of the semiconductor layer in FIG35;

[0172] FIG38 is a layout diagram of the first metal layer in FIG35;

[0173] FIG39 is a layout diagram of the second metal layer in FIG35;

[0174] FIG40 is a layout diagram of the fourth metal layer in FIG35;

[0175] FIG41 is a layout diagram of at least one embodiment of a gate control line and a gate portion disposed in a gate transistor arrangement region, included in the array substrate, in at least one embodiment of the present invention;

[0176] FIG42 is a layout diagram of the third metal layer in FIG41;

[0177] FIG43 is a layout diagram of the semiconductor layer in FIG41;

[0178] FIG44 is a layout diagram of the first metal layer in FIG41;

[0179] FIG45 is a layout diagram of the second metal layer in FIG41;

[0180] FIG46 is a layout diagram of the sixth metal layer in FIG41;

[0181] FIG47 is a partial layout diagram of a fan-out region and an integrated circuit placement region in an array substrate in at least one embodiment of the present invention;

[0182] FIG48 is a layout diagram of the first metal layer in FIG47;

[0183] FIG49 is a layout diagram of the second metal layer in FIG47;

[0184] FIG50 is a layout diagram of the sixth metal layer in FIG47;

[0185] FIG51 is a layout diagram of the fourth metal layer in FIG47;

[0186] FIG52 is a planar layout diagram of a portion of an array substrate according to at least one embodiment of the present invention;

[0187] FIG53 is a layout diagram of the third metal layer in FIG52;

[0188] FIG54 is a layout diagram of the semiconductor layer in FIG52;

[0189] FIG55 is a layout diagram of the first metal layer in FIG52;

[0190] FIG56 is a layout diagram of the second metal layer in FIG52;

[0191] FIG57 is a layout diagram of the fifth metal layer in FIG52;

[0192] FIG58 is a layout diagram of the fourth metal layer in FIG52;

[0193] FIG59 is a stacked diagram of the third metal layer shown in FIG53 and the semiconductor layer shown in FIG54;

[0194] FIG60 is a DD' cross-sectional view of the array substrate according to at least one embodiment of the present invention shown in FIG52;

[0195] FIG61 is a DD' cross-sectional view of the array substrate according to at least one embodiment of the present invention shown in FIG52;

[0196] FIG62 is a DD' cross-sectional view of the array substrate according to at least one embodiment of the present invention shown in FIG52;

[0197] FIG63 is a DD' cross-sectional view of the array substrate according to at least one embodiment of the present invention shown in FIG52;

[0198] FIG64 is a DD' cross-sectional view of the array substrate according to at least one embodiment of the present invention shown in FIG52;

[0199] FIG65 is a DD' cross-sectional view of the array substrate according to at least one embodiment of the present invention shown in FIG52;

[0200] FIG66 is a DD' cross-sectional view of the array substrate according to at least one embodiment of the present invention shown in FIG52;

[0201] FIG67 is a cross-sectional view of EE′ in FIG52;

[0202] FIG68 is a cross-sectional view of four metal layers in a fan-out region;

[0203] FIG69 is a circuit diagram of at least one embodiment of a driver circuit;

[0204] FIG70 is a layout diagram of at least one embodiment of the driving circuit shown in FIG69;

[0205] FIG71 is a layout diagram of the third metal layer in FIG70;

[0206] FIG72 is a layout diagram of the semiconductor layer in FIG70;

[0207] FIG73 is a layout diagram of the first metal layer in FIG70;

[0208] FIG74 is a layout diagram of the second metal layer in FIG70;

[0209] FIG75 is a layout diagram of the fourth metal layer in FIG70;

[0210] FIG76 is a schematic diagram illustrating the positional relationship between touch signal lines and data lines in an array substrate according to at least one embodiment of the present invention;

[0211] FIG77 is a schematic diagram showing the positional relationship between touch signal lines and data lines in an array substrate according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0212] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0213] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0214] As used herein, "parallel," "perpendicular," and "equal" include the conditions described and conditions similar to the conditions described, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range for approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range for approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range for approximate equality may be, for example, that the difference between the two equals is less than or equal to 10% of either of them.

[0215] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0216] The present disclosure describes exemplary embodiments with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0217] In the present invention, circles, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0218] The transistors used in all embodiments of the present invention may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0219] In actual operation, when the transistor is a thin film transistor (TFT) or a field effect transistor (FET), the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0220] An array substrate according to an embodiment of the present invention includes a plurality of first routing lines and a plurality of second routing lines disposed on a substrate, the first routing lines and the second routing lines intersecting each other to define a plurality of pixel regions, each of the pixel regions including a transistor, a first electrode, a second electrode, a first via hole, and a second via hole; an orthographic projection of the first via hole on the substrate at least partially overlaps with an orthographic projection of the first electrode on the substrate, and an orthographic projection of the second via hole on the substrate at least partially overlaps with an orthographic projection of the first electrode on the substrate;

[0221] The orthographic projection of the first via hole on the substrate does not overlap with the orthographic projection of the second electrode on the substrate, and the orthographic projection of the second via hole on the substrate does not overlap with the orthographic projection of the second electrode on the substrate.

[0222] In at least one embodiment of the present invention, the first wiring may be a gate line, the second wiring may be a data line, the third wiring may be a touch signal line, the first electrode may be a pixel electrode, and the second electrode may be a common electrode.

[0223] In the embodiment of the present invention, the first wiring X1 and the second wiring X2 intersect each other to define a plurality of pixel areas, and a transistor, a pixel electrode PX, a common electrode VCOM, a first via hole H1 and a second via hole H2 are provided in each pixel area;

[0224] As shown in FIG1A , the first via hole is labeled H1 and the second via hole is labeled H2; a second trace is provided below the third trace X3;

[0225] In FIG1A , the pixel electrode is labeled PX, and the common electrode is labeled VCOM;

[0226] As shown in FIG1A , the orthographic projection of H1 on the substrate at least partially overlaps with the orthographic projection of the pixel electrode PX on the substrate, and the orthographic projection of H2 on the substrate at least partially overlaps with the orthographic projection of the pixel electrode PX on the substrate;

[0227] The orthographic projection of H1 on the substrate does not overlap with the orthographic projection of the common electrode VCOM on the substrate, and the orthographic projection of H2 on the substrate does not overlap with the orthographic projection of the common electrode VCOM on the substrate.

[0228] As shown in FIG1A , the first via hole H1 and the second via hole H2 are located in the same pixel area.

[0229] The first via hole H1 is used to electrically connect the pixel electrode PX and the first conductor portion included in the active pattern, that is, the second via hole H1 is used to electrically connect the first electrode of the transistor and the first conductor portion of the active pattern;

[0230] The first via hole H1 is used to electrically connect the pixel electrode PX and the first electrode of the transistor;

[0231] The second via hole is used to electrically connect the first electrode of the transistor and the first conductor portion of the active pattern, so that the pixel electrode PX is electrically connected to the first conductor portion of the active pattern.

[0232] As shown in FIG. 1A , H1 and H2 are located in the same pixel region, so that the pixel electrode PX is conveniently electrically connected to the first conductor portion of the active pattern.

[0233] As shown in FIG1A , another pixel region adjacent to the pixel region includes a third via hole H3 ;

[0234] The orthographic projection of the second via hole H2 on the substrate and the orthographic projection of the third via hole H3 on the substrate are located on opposite sides of the orthographic projection of the first trace X1 on the substrate.

[0235] Optionally, the transistor includes an active pattern;

[0236] The orthographic projection of the second via on the substrate at least partially overlaps with the orthographic projection of the first conductor portion of the active pattern on the substrate; the second via is used to electrically connect the first electrode of the transistor and the first conductor portion of the active pattern;

[0237] A portion of the first electrode falls into the first via hole, and the first via hole is used to electrically connect the first electrode and the first conductor portion included in the active pattern.

[0238] As shown in FIG7 , the transistor includes an active pattern A0;

[0239] The active pattern A0 includes a semiconductor portion B0, a first conductor portion DT1 and a second conductor portion DT2; in FIG16 , B0 is the semiconductor portion, DT1 is the first conductor portion, and DT2 is the second conductor portion;

[0240] As shown in FIG16 , the orthographic projection of the second via H2 on the substrate at least partially overlaps with the orthographic projection of the first conductor portion DT1 on the substrate; the second via H2 is used to electrically connect the first electrode S1 of the transistor and the first conductor portion DT1;

[0241] A portion of the pixel electrode PX falls into the first via hole H1 , and the first via hole H1 is used to electrically connect the pixel electrode PX and the first conductor portion DT1 .

[0242] Optionally, the orthographic projection of the third via on the substrate at least partially overlaps with the orthographic projection of the second conductor portion included in the active pattern on the substrate; the third via is used to electrically connect the second electrode of the transistor with the second conductor portion of the active pattern.

[0243] As shown in FIG. 1A to FIG. 16 , the orthographic projection of the third via hole H3 on the substrate at least partially overlaps with the orthographic projection of the second conductor portion DT2 on the substrate;

[0244] The third via hole H3 is used to electrically connect the second electrode D2 of the transistor and the second conductor portion DT2.

[0245] In at least one embodiment of the present invention, along the first direction, the minimum distance between the orthographic projection of the first via on the substrate and the orthographic projection of the first routing on the substrate is smaller than the minimum distance between the orthographic projection of the second via on the substrate and the orthographic projection of the first routing on the substrate.

[0246] Optionally, the first direction may be a vertical direction.

[0247] In the drawings of the present invention, the direction labeled X is the second direction, the direction labeled Y is the first direction, and the direction labeled Z is the third direction;

[0248] The second direction X may be a horizontal direction, the first direction Y may be a vertical direction, and the third direction Z may be a direction perpendicular to the substrate.

[0249] As shown in FIG1A , DS1 is the distance between the orthographic projection of the first via hole H1 on the substrate and the orthographic projection of the first trace X1 on the substrate, and DS2 is the distance between the orthographic projection of the second via hole H2 on the substrate and the orthographic projection of the first trace X1 on the substrate;

[0250] DS1 is smaller than DS2.

[0251] Optionally, the active pattern is dumbbell-shaped; and an angle between an orthographic projection of the active pattern on the substrate and an orthographic projection of the first trace on the substrate is greater than or equal to 85 degrees and less than or equal to 95 degrees.

[0252] As shown in Figure 23, the semiconductor layer includes active patterns arranged in an array, and the active pattern A0 is dumbbell-shaped; as shown in Figure 21, the angle between the orthographic projection of the active pattern A0 on the substrate and the orthographic projection of the gate line GL on the substrate is greater than or equal to 85 degrees and less than or equal to 95 degrees; preferably, the angle between the orthographic projection of the active pattern A0 on the substrate and the orthographic projection of the gate line GL on the substrate is greater than or equal to 88 degrees and less than or equal to 92 degrees.

[0253] In at least one embodiment of the present invention, the second wiring includes a second wiring body, a first auxiliary portion, and a second auxiliary portion;

[0254] The first auxiliary portion is electrically connected to the second wiring body, and the second auxiliary portion is in a floating state;

[0255] The first auxiliary portion is electrically connected to the second conductor portion included in the active pattern, and the second auxiliary portion is electrically connected to the first electrode.

[0256] As shown in FIG25B , the first auxiliary portion is labeled F1 and the second auxiliary portion is labeled F2. The first auxiliary portion F1 is electrically connected to the data line body DLB, and the second auxiliary portion is in a floating state.

[0257] The first auxiliary portion F1 is electrically connected to the second conductor portion included in the active pattern A0, and the second auxiliary portion F2 is electrically connected to the pixel electrode.

[0258] Optionally, the array substrate includes 3a second wirings and 2a third wirings; a is a positive integer;

[0259] The two third routing lines correspond to the three second routing lines, and the orthographic projections of the third routing lines on the substrate at least partially overlap with the orthographic projection of one of the three second routing lines on the substrate.

[0260] Optionally, the array substrate includes 3a second wirings and a third wiring; a is a positive integer;

[0261] One of the third routing lines corresponds to three of the second routing lines, and an orthographic projection of the third routing line on the substrate at least partially overlaps with an orthographic projection of one of the three second routing lines on the substrate.

[0262] In at least one embodiment of the present invention, the array substrate further includes a third trace;

[0263] The third trace includes a signal line main body portion and a connecting portion electrically connected to each other;

[0264] An orthographic projection of the connecting portion on the substrate at least partially overlaps with an orthographic projection of the second via hole on the substrate.

[0265] Optionally, the third trace may be a touch signal line.

[0266] As shown in FIG1A and FIG8 , the third trace includes a signal line main portion TX0 and a connection portion L1 electrically connected to each other;

[0267] An orthographic projection of the connecting portion L1 on the substrate at least partially overlaps with an orthographic projection of the second via hole H2 on the substrate.

[0268] In at least one embodiment of the present invention, the array substrate further includes a light-shielding pattern; the light-shielding pattern and the third trace are disposed in different layers;

[0269] The orthographic projection of the connecting portion on the substrate at least partially overlaps with the orthographic projection of the light-shielding pattern on the substrate.

[0270] In FIG20 , the connection portion is labeled L1, and the light shielding pattern is labeled ZX. The orthographic projection of the connection portion L1 on the substrate overlaps with the orthographic projection of the light shielding pattern ZX on the substrate, and the overlapping area is greater than or equal to 100 μm. 2 Less than or equal to 150μm 2 For example, the overlapping area between the orthographic projection of the connection portion L1 on the substrate and the orthographic projection of the light shielding pattern ZX on the substrate may be 122 μm 2 .

[0271] In at least one embodiment of the present invention, the array substrate further includes a light-shielding pattern;

[0272] The orthographic projection of the light-shielding pattern on the substrate covers the orthographic projection of the conductor portion of the active pattern of the transistor on the substrate, so as to prevent the influence of backlight illumination on the leakage of the semiconductor portion of the active pattern.

[0273] In at least one embodiment of the present invention, the array substrate includes a first metal layer, a second metal layer, a semiconductor layer and a first insulating layer;

[0274] The switching transistor includes an active pattern, a first gate, a first electrode and a second electrode;

[0275] The first gate is formed in the first metal layer, the first electrode and the second electrode are formed in the second metal layer, and the active pattern is located in the semiconductor layer;

[0276] The first insulating layer is provided between the first metal layer and the semiconductor layer;

[0277] The thickness of the first insulating layer is less than a first thickness threshold; the first thickness threshold is greater than or equal to 800 angstroms and less than or equal to 2000 angstroms;

[0278] The first metal layer is disposed on a side of the semiconductor layer away from the substrate.

[0279] In existing oxide BCE processes, because the gate insulation layer is located between the source / drain metal layer and the gate metal layer, and because both the source / drain metal layer and the gate metal layer are metal layers, the thickness of the gate insulation layer cannot be further reduced at current mass production levels, otherwise the risk of ESD (electrostatic discharge) between the gate metal layer and the source / drain metal layer increases. The on-state current of a transistor is inversely proportional to the thickness of the gate insulation layer: the thicker the gate insulation layer, the lower the on-state current of the transistor. Therefore, due to the limitation of the gate insulation layer thickness, the on-state current of a transistor with a BCE structure cannot be further increased. Therefore, to further increase the on-state current of the transistor, in an embodiment of the present invention, a first metal layer is disposed above a semiconductor layer, and a second metal layer is disposed above the first metal layer (the first metal layer can be a gate metal layer, and the second metal layer can be a source / drain metal layer), with a first insulation layer disposed between the first metal layer and the semiconductor layer. In this embodiment of the present invention, the thickness of the first insulation layer can be reduced to increase the on-state current of the transistor.

[0280] In at least one embodiment of the present invention, the transistor may be a top-gate structure, and accordingly, the first gate may be a top gate.

[0281] In at least one embodiment of the present invention, the thickness of the insulating layer between the first metal layer and the second metal layer can be kept unchanged from that in the related art to prevent ESD.

[0282] In at least one embodiment of the present invention, the first insulating layer may be a gate insulating layer, and the thickness of the first insulating layer may be less than a first thickness threshold, which may be greater than or equal to 800 angstroms and less than or equal to 2000 angstroms.

[0283] An embodiment of the present invention provides a display screen that uses a top-gate process and integrates a touch function.

[0284] Optionally, the thickness of the first insulating layer is greater than or equal to 500 angstroms and less than or equal to 2000 angstroms, but is not limited thereto.

[0285] In at least one embodiment of the present invention, the active pattern includes a semiconductor portion; the semiconductor portion includes a first semiconductor portion and a second semiconductor portion stacked together;

[0286] The first semiconductor portion is disposed between the second semiconductor portion and the substrate, and the first semiconductor portion and the second semiconductor portion are made of semiconductor materials with different carrier mobilities.

[0287] The active pattern can be made of one or more materials selected from the group consisting of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), and rare earth-doped oxide (Ln-OS). The active layer can be amorphous, partially crystalline, single crystal, or polycrystalline, and can have a single-layer or multi-layer structure.

[0288] Optionally, the first semiconductor portion is made of any one or both of IGZTO and Ln-OS, and the second semiconductor portion is made of any one or both of IGZO and IZO.

[0289] In a specific implementation, the semiconductor portion included in the active pattern may include a first semiconductor portion and a second semiconductor portion that are stacked. For example, the first semiconductor portion may be made of IGZTO (indium gallium zinc tin oxide), and the second semiconductor portion may be made of IGZO (indium gallium zinc oxide). The first semiconductor portion can ensure the mobility of the transistor, and the second semiconductor portion can ensure the stability of the transistor.

[0290] In at least one embodiment of the present invention, the array substrate further includes a third metal layer and a second insulating layer;

[0291] The third metal layer is disposed between the semiconductor layer and the substrate, and the second insulating layer is disposed between the semiconductor layer and the third metal layer;

[0292] The third metal layer includes a light-shielding pattern, and an orthographic projection of the light-shielding pattern on the substrate covers an orthographic projection of a semiconductor portion in the active pattern on the substrate.

[0293] In a specific implementation, the array substrate may further include a third metal layer, which is arranged between the semiconductor layer and the substrate, and a second insulating layer is arranged between the semiconductor layer and the third metal layer. The orthographic projection of the shading pattern included in the third metal layer on the substrate can cover the orthographic projection of the semiconductor part in the active pattern on the substrate to prevent the backlight from affecting the leakage of the semiconductor part in the active pattern.

[0294] In a specific implementation, the orthographic projection of the light-shielding pattern on the substrate may also cover the orthographic projection of the active pattern on the substrate.

[0295] In at least one embodiment of the present invention, the light shielding pattern is multiplexed as the second gate of the switch transistor.

[0296] In a specific implementation, the light-shielding pattern can be reused as the second gate of the switch transistor, and the second gate can be a bottom gate. Accordingly, the switch transistor can have a dual-gate structure.

[0297] Optionally, the active pattern extends along a first direction;

[0298] The maximum distance between an edge of an orthographic projection of the light-shielding pattern on the substrate and an edge of an orthographic projection of the active pattern on the substrate along the second direction is greater than a first distance threshold;

[0299] The first distance threshold is greater than or equal to 4 μm; and the first direction intersects the second direction.

[0300] In a specific implementation, the active pattern may extend along a first direction, for example, the first direction may be a vertical direction. At least one embodiment of the present invention sets the maximum distance along the second direction between the edge of the orthographic projection of the shading pattern on the substrate and the edge of the orthographic projection of the active pattern on the substrate to be greater than a first distance threshold to ensure that the orthographic projection of the shading pattern on the substrate can cover the orthographic projection of the active pattern on the substrate. The first direction intersects with the second direction, for example, the second direction may be a horizontal direction.

[0301] For example, the first distance threshold may be greater than or equal to 4 μm. For example, the maximum distance along the second direction between the edge of the orthographic projection of the shading pattern on the substrate and the edge of the orthographic projection of the active pattern on the substrate may be 6 μm. This distance mainly considers the effect of backlight illumination on leakage of the active pattern. This distance takes into account the effect of misalignment caused by the alignment offset of the third metal layer and the semiconductor layer. If the alignment accuracy of the equipment is improved, the distance between the third metal layer and the active pattern can be appropriately reduced to less than 6 μm.

[0302] Optionally, the array substrate further includes a fourth metal layer; the first electrode is formed on the fourth metal layer; the fourth metal layer is arranged on a side of the second metal layer away from the substrate;

[0303] The first electrode is electrically connected to the second electrode of the transistor through a first via hole;

[0304] The orthographic projection area of ​​the first via hole on the substrate is between 40-80 square micrometers. Optionally, the orthographic projection of the first via hole on the substrate is roughly rectangular, which may be greater than or equal to 6 μm×7 μm and less than or equal to 8 μm×10 μm.

[0305] In a specific implementation, the array substrate includes a fourth metal layer, a first electrode is formed on the fourth metal layer, and the fourth metal layer is electrically connected to the second electrode through a first via. The area of ​​the orthographic projection of the first via on the substrate can be greater than or equal to 6μm×7μm and less than or equal to 8μm×10μm. For example, the area of ​​the orthographic projection of the first via on the substrate can be 7μm×8.5μm. If the area of ​​the first via increases, the aperture ratio will decrease. If the area of ​​the first via decreases, there is a risk of exposure failure under current exposure accuracy. As the exposure accuracy of the equipment improves, the size of the first via can be further reduced.

[0306] In at least one embodiment of the present invention, the array substrate further includes a fifth metal layer; the second electrode is formed on the fifth metal layer; the fifth metal layer is disposed between the fourth metal layer and the second metal layer;

[0307] The shortest distance between the orthographic projection of the second electrode on the substrate and the edge of the orthographic projection of the first via hole on the substrate is greater than a second distance threshold;

[0308] The second distance threshold is greater than 2 μm.

[0309] In a specific implementation, the array substrate may further include a fifth metal layer, the second electrode is formed on the fifth metal layer, the fifth metal layer is disposed between the fourth metal layer and the second metal layer, the shortest distance between the orthographic projection of the second electrode on the substrate and the orthographic projection of the first via on the substrate is greater than a second distance threshold, and the second distance threshold may be greater than 2 μm. For example, the shortest distance between the orthographic projection of the second electrode on the substrate and the orthographic projection of the first via on the substrate may be 3 μm, to prevent etching errors and misalignment between the second electrode and the first via, which may cause the second electrode to enter the first via, while the first via contains a conductive pattern included in the fourth metal layer. If the second electrode enters the first via, it will short-circuit with the conductive pattern included in the fourth metal layer, resulting in poor display. If the etching error is reduced and the alignment accuracy is improved, the distance from the first via to the second electrode can be further reduced.

[0310] Optionally, the first electrode may be a pixel electrode, and the second electrode may be a common electrode.

[0311] Optionally, the shortest distance between an orthographic projection of the first electrode on the substrate and an edge of an orthographic projection of the first via hole on the substrate is greater than a third distance threshold;

[0312] The third distance threshold is greater than or equal to 1.6 μm.

[0313] In a specific implementation, the shortest distance between the orthographic projection of the first electrode on the substrate and the edge of the orthographic projection of the first via on the substrate is greater than a third distance threshold, which may be greater than or equal to 1.6 μm. For example, the shortest distance between the orthographic projection of the first electrode on the substrate and the edge of the orthographic projection of the first via on the substrate may be 2.25 μm. Considering the case of alignment offset, the first electrode can still cover the first via, thereby ensuring conductivity between the first electrode and the second electrode. If the device alignment accuracy is improved, this distance can be further reduced.

[0314] In at least one embodiment of the present invention, the first electrode is electrically connected to the active pattern through a second via hole, and the second electrode is electrically connected to the active pattern through a third via hole;

[0315] The shortest distance between the edge of the orthographic projection of the first pole on the substrate and the edge of the orthographic projection of the second via on the substrate is greater than a fourth distance threshold;

[0316] The shortest distance between an edge of an orthographic projection of the second pole on the substrate and an edge of an orthographic projection of the third via hole on the substrate is greater than a fifth distance threshold;

[0317] The fourth distance threshold is greater than or equal to 1.6 μm, and the fifth distance threshold is greater than or equal to 1.6 μm.

[0318] In a specific implementation, the first electrode can be electrically connected to the active pattern through a second via, and the second electrode can be electrically connected to the active pattern through a third via. The shortest distance between the edge of the orthographic projection of the first electrode on the substrate and the edge of the orthographic projection of the second via on the substrate is set to be greater than a fourth distance threshold; the shortest distance between the edge of the orthographic projection of the second electrode on the substrate and the edge of the orthographic projection of the third via on the substrate is set to be greater than a fifth distance threshold. The fourth and fifth distance thresholds can be greater than or equal to 1.6 μm. For example, the shortest distance between the edge of the orthographic projection of the first electrode on the substrate and the edge of the orthographic projection of the second via on the substrate can be 2.25 μm, and the shortest distance between the edge of the orthographic projection of the second electrode on the substrate and the edge of the orthographic projection of the third via on the substrate can be 2.25 μm. Even when alignment offset is taken into account, the second metal layer can still cover the second and third vias, thereby ensuring conductivity between the second metal layer and the active pattern. If the device alignment accuracy is improved, this distance can be further reduced.

[0319] 1A and 1B are plan layout diagrams of parts of an array substrate according to at least one embodiment of the present invention.

[0320] In FIG. 1A and FIG. 1B , the via hole labeled H1 is the first via hole, the via hole labeled H2 is the second via hole, the via hole labeled H3 is the third via hole, and the via hole labeled H0 is the TX via hole.

[0321] In FIG. 1A and FIG. 1B , the light-shielding pattern is labeled ZX, the first trace is labeled X1, the second trace is labeled X2, and the third trace is labeled X3.

[0322] The first wiring may be a gate line, the second wiring may be a data line, and the third wiring may be a touch signal line.

[0323] In the drawings of the present invention, the direction labeled X is the second direction, the direction labeled Y is the first direction, and the direction labeled Z is the third direction;

[0324] The second direction X may be a horizontal direction, the first direction Y may be a vertical direction, and the third direction Z may be a direction perpendicular to the substrate.

[0325] FIG. 2 is a BB′ cross-sectional view of the array substrate shown in FIG. 1 according to at least one embodiment of the present invention.

[0326] As shown in FIG2 , the array substrate according to at least one embodiment of the present invention includes a first metal layer 21, a second metal layer 22, a semiconductor layer 20, a first insulating layer 201, a third metal layer 23, a second insulating layer 202, a fourth metal layer 24, a fifth metal layer 25, a sixth metal layer 26, a fifth insulating layer 205, a sixth insulating layer 206, a seventh insulating layer 207, and an eighth insulating layer 208.

[0327] The third metal layer 23, the semiconductor layer 20, the first metal layer 21, the second metal layer 22, the fifth metal layer 25, the sixth metal layer 26 and the fourth metal layer 24 are arranged in sequence along a direction away from the substrate J1;

[0328] A second insulating layer 202 is provided between the third metal layer 23 and the semiconductor layer 20;

[0329] A first insulating layer 201 is provided between the semiconductor layer 20 and the first metal layer 21;

[0330] A fifth insulating layer 205 is provided between the first metal layer 21 and the second metal layer 22;

[0331] A sixth insulating layer 206 and a seventh insulating layer 207 are stacked between the second metal layer 22 and the fifth metal layer 25 ; the sixth insulating layer 206 is disposed between the seventh insulating layer 207 and the second metal layer 22 ;

[0332] An eighth insulating layer 208 is provided between the fourth metal layer 24 and the fifth metal layer 25;

[0333] Among them, the first metal layer 21 can be a second gate metal layer, the second metal layer 22 can be a source-drain metal layer, the first insulating layer 201 can be a second gate insulating layer, the third metal layer 23 can be a light-shielding metal layer, and the light-shielding metal layer can be reused as the first gate metal layer; the fourth metal layer 24 can be a pixel electrode layer, the fifth metal layer 25 can be a common electrode layer, and the sixth metal layer 26 can be a touch layer;

[0334] The first insulating layer 201 may be a second gate insulating layer, the second insulating layer 202 may be a first gate insulating layer, the fifth insulating layer 205 may be an interlayer dielectric layer, the sixth insulating layer 206 may be a first passivation layer, the seventh insulating layer 207 may be an organic film layer, and the eighth insulating layer 208 may be a second passivation layer;

[0335] As shown in FIG3 , the switch transistor includes an active pattern A0 , a first gate G1 , a first electrode S1 , and a second electrode D1 ;

[0336] The first gate G1 is formed in the first metal layer 21 , the first electrode S1 and the second electrode D1 are formed in the second metal layer 22 , and the active pattern A0 is formed in the semiconductor layer 20 ;

[0337] The third metal layer includes a light-shielding pattern ZX, wherein an orthographic projection of the light-shielding pattern ZX on the substrate at least partially overlaps with an orthographic projection of the active pattern A0 on the substrate;

[0338] The orthographic projection of the light-shielding pattern ZX on the substrate covers the orthographic projection of the semiconductor portion of the active pattern A0 on the substrate;

[0339] The light shielding pattern ZX can be reused as the second gate of the switching transistor;

[0340] The pixel circuit further includes a pixel electrode PX; the pixel electrode PX is formed on the fourth metal layer 24;

[0341] The pixel electrode PX is electrically connected to the second electrode D1 through a first via hole H1; the first via hole H1 penetrates the first passivation layer and the organic film layer; that is, the first via hole H1 includes a first sub-via hole penetrating the organic film layer and a second sub-via hole penetrating the first passivation layer;

[0342] The display unit further includes a common electrode VCOM, and the common electrode VCOM is formed on the fifth metal layer 25;

[0343] In FIG3 , the line labeled TX is a touch signal line, and the touch signal line is electrically connected to the common electrode VCOM.

[0344] As shown in FIG. 4 , based on at least one embodiment of the array substrate shown in FIG. 3 , the active pattern A0 may include a semiconductor portion B0 .

[0345] As shown in FIG5 , based on at least one embodiment of the array substrate shown in FIG4 , the semiconductor portion includes a first semiconductor portion B1 and a second semiconductor portion B2 , and B1 and B2 may be a stacked structure.

[0346] Figure 6 is a layout diagram of the third metal layer in Figure 1A, Figure 7 is a layout diagram of the semiconductor layer in Figure 1A, Figure 8 is a layout diagram of the sixth metal layer in Figure 1A, Figure 9 is a layout diagram of the fifth metal layer in Figure 1A, Figure 10 is a layout diagram of the fourth metal layer in Figure 1A, Figure 11 is a layout diagram of the first metal layer in Figure 1A, and Figure 12 is a layout diagram of the second metal layer in Figure 1A.

[0347] FIG. 13 is a stacked diagram of the third metal layer and the semiconductor layer in FIG. 1A .

[0348] In FIG11 , the gate lines are labeled GL, and in FIG12 , the data lines are labeled DL.

[0349] As shown in FIG13 , the active pattern A0 extends in the vertical direction, and the maximum distance between the edge of the orthographic projection of the light-shielding pattern ZX on the substrate and the edge of the orthographic projection of the active pattern A0 on the substrate along the second direction is a first distance JL1;

[0350] JL1 is greater than the first distance threshold.

[0351] In FIG. 1A , the first via hole is labeled H1 , and the orthographic projection of the first via hole H1 on the substrate has an area greater than or equal to 6 μm×7 μm and less than or equal to 8 μm×10 μm.

[0352] Optionally, the second direction may be a horizontal direction.

[0353] As shown in FIG14 , based on at least one embodiment of the array substrate shown in FIG3 , the shortest distance between the orthographic projection of the common electrode VCOM on the substrate and the edge of the orthographic projection of the first via hole H1 on the substrate is a second distance JL2 ;

[0354] The second distance JL2 is greater than the second distance threshold.

[0355] As shown in Figure 15, based on at least one embodiment of the array substrate shown in Figure 3, the shortest distance between the orthographic projection of the pixel electrode PX on the substrate and the edge of the orthographic projection of the first via H1 on the substrate is a third distance JL3, and the third distance JL3 is greater than the third distance threshold.

[0356] As shown in Figure 16, based on at least one embodiment of the array substrate shown in Figure 3, the shortest distance between the edge of the orthographic projection of the first pole S1 on the substrate and the edge of the orthographic projection of the second via H2 on the substrate is a fourth distance JL4, and the shortest distance between the edge of the orthographic projection of the second pole D1 on the substrate and the edge of the orthographic projection of the second via H2 on the substrate is a fifth distance JL5.

[0357] In at least one embodiment of the present invention, the array substrate further includes a fifth metal layer and a sixth metal layer, the fifth metal layer being disposed on a side of the second metal layer away from the substrate, and the sixth metal layer being disposed on a side of the fifth metal layer away from the substrate;

[0358] The array substrate includes a third trace;

[0359] The third wiring is formed in the sixth metal layer, and the second electrode is formed in the fifth metal layer.

[0360] FIG17 is a cross-sectional view taken along line CC′ in FIG1B .

[0361] In FIG17 , only the fourth metal layer 24 , the fifth metal layer 25 , the sixth metal layer 26 , the third insulating layer 203 disposed between the sixth metal layer 26 and the fifth metal layer 25 , and the fourth insulating layer 204 disposed between the sixth metal layer 26 and the fourth metal layer 24 are drawn;

[0362] The third insulating layer 203 may be a passivation layer, and the fourth insulating layer 204 may be a passivation layer.

[0363] In FIG18 , based on at least one embodiment of the array substrate shown in FIG17 , the element labeled TX is a touch signal line, and the element labeled VCOM is a common electrode; the touch signal line is electrically connected to the common electrode VCOM.

[0364] Optionally, the array substrate further includes a fourth metal layer, a third insulating layer disposed between the sixth metal layer and the fifth metal layer, and a fourth insulating layer disposed between the sixth metal layer and the fourth metal layer; the fourth metal layer is disposed on a side of the sixth metal layer away from the substrate;

[0365] The array substrate includes a first conductive pattern formed on the fourth metal layer;

[0366] The first conductive pattern is electrically connected to the third trace through the fourth via, and the first conductive pattern is electrically connected to the second electrode through the fourth via and the fifth via, so that the third trace is electrically connected to the second electrode;

[0367] The fourth via hole is a via hole that passes through the fourth insulating layer, and the fifth via hole is a via hole that passes through the third insulating layer;

[0368] An orthographic projection area of ​​the fourth via hole on the substrate is greater than or equal to 3 μm×6 μm and less than or equal to 5 μm×8 μm.

[0369] In a specific implementation, the area of ​​the orthographic projection of the fourth via on the substrate is set to be greater than or equal to 3μm×6μm and less than or equal to 5μm×8μm. For example, the area of ​​the orthographic projection of the fourth via on the substrate can be 4μm×7μm. It is necessary to ensure that the fourth via can still cover the touch signal line and the common electrode after being offset. At the same time, the fourth via is covered by the first conductive pattern, and it is necessary to ensure that the first conductive pattern can still cover the fourth via after being offset.

[0370] In Figure 19, based on at least one embodiment of the array substrate shown in Figure 18, the fourth via hole is labeled H4, the fifth via hole is labeled H5, and the area of ​​the orthographic projection of the fourth via hole H4 on the substrate can be greater than or equal to 3μm×6μm and less than or equal to 5μm×8μm.

[0371] As shown in Figure 19, the TX via is a half-overlap hole, half of which connects to the touch signal line TX and the other half to the common electrode VCOM. The entire TX via is covered with a first conductive pattern DX1. The first conductive pattern DX1 is connected to the touch signal line TX through the hole on the left, and the first conductive pattern DX1 is connected to the common electrode VCOM through the hole on the right, so that the touch signal line TX is electrically connected to the common electrode VCOM.

[0372] In at least one embodiment of the present invention, the array substrate includes a sixth metal layer; the array substrate includes a third trace, and the third trace is formed in the sixth metal layer;

[0373] The third wiring includes a signal line main body portion and a connecting portion that are interconnected;

[0374] The orthographic projection of the connecting portion on the base covers the orthographic projection of the spacer portion on the base, and the connecting portion is used to support the spacer portion;

[0375] The array substrate is included in a display device, which includes a color filter substrate. The spacer portion is disposed between the color filter substrate and the array substrate.

[0376] In a specific implementation, the array substrate may include a touch signal line formed in the sixth metal layer, and the touch signal line may include a signal line main body and a connecting part that are interconnected, wherein the connecting part can be used to support the spacer part between the color film substrate and the array substrate.

[0377] As shown in FIG8 , the line labeled TX is a touch signal line. The touch signal line TX may include a signal line main portion TX0 and a connecting portion L1 that are interconnected. The connecting portion L1 may be used to support the spacer portion.

[0378] In at least one embodiment of the present invention, the array substrate further includes a third metal layer;

[0379] The third metal layer is disposed on a side of the semiconductor layer close to the substrate; the third metal layer includes a light-shielding pattern;

[0380] The overlapping area between the orthographic projection of the connecting portion on the substrate and the orthographic projection of the light-shielding pattern on the substrate is greater than or equal to 100 μm 2 Less than or equal to 150μm 2 .

[0381] FIG20 is an overlay diagram of the third metal layer and the sixth metal layer in FIG1A ;

[0382] In FIG20 , the connection portion is labeled L1, and the light shielding pattern is labeled ZX. The orthographic projection of the connection portion L1 on the substrate overlaps with the orthographic projection of the light shielding pattern ZX on the substrate, and the overlapping area is greater than or equal to 100 μm. 2 Less than or equal to 150μm 2 For example, the overlapping area between the orthographic projection of the connection portion L1 on the substrate and the orthographic projection of the light shielding pattern ZX on the substrate may be 122 μm 2 .

[0383] Figure 21 is a layout diagram of the array substrate described in at least one embodiment of the present invention, Figure 22 is a layout diagram of the third metal layer in Figure 21, Figure 23 is a layout diagram of the semiconductor layer in Figure 21, Figure 24 is a layout diagram of the first metal layer in Figure 21, Figures 25A and 25B are layout diagrams of the second metal layer in Figure 21, Figure 26 is a layout diagram of the fifth metal layer in Figure 21, Figures 27A and 27B are layout diagrams of the sixth metal layer in Figure 21, and Figure 28 is a layout diagram of the fourth metal layer in Figure 21.

[0384] In FIG21 , the line labeled TX1 is a first touch signal line, the line labeled TX2 is a second touch signal line, the line labeled TX3 is a third touch signal line, and the line labeled DL is a data line.

[0385] In FIG22 , the pattern labeled ZX is a light-shielding pattern.

[0386] As shown in FIG22 , the shading patterns ZX corresponding to the pixel units in the same column but different rows are staggered, that is, the shading units corresponding to the pixel units in the same column but different rows are offset by a certain distance. As shown in FIG21 , the corresponding data lines DL are bent to increase the area of ​​the pixel region as much as possible.

[0387] In FIG23, the pattern labeled A0 is an active pattern.

[0388] As shown in Figure 23, the semiconductor layer includes active patterns arranged in an array, and the active pattern A0 is dumbbell-shaped; as shown in Figure 21, the angle between the orthographic projection of the active pattern A0 on the substrate and the orthographic projection of the gate line GL on the substrate is greater than or equal to 85 degrees and less than or equal to 95 degrees; preferably, the angle between the orthographic projection of the active pattern A0 on the substrate and the orthographic projection of the gate line GL on the substrate is greater than or equal to 88 degrees and less than or equal to 92 degrees.

[0389] In FIG24 , the gate lines are labeled GL.

[0390] In FIG. 25A , the line labeled DL is a data line.

[0391] As shown in FIG25B , the first auxiliary portion is labeled F1 and the second auxiliary portion is labeled F2. The first auxiliary portion F1 is electrically connected to the data line body DLB, and the second auxiliary portion is in a floating state.

[0392] The first auxiliary portion F1 is electrically connected to the second conductor portion included in the active pattern A0, and the second auxiliary portion F2 is electrically connected to the pixel electrode.

[0393] In FIG26 , the common electrode is labeled VCOM.

[0394] In FIG. 27A , the line labeled TX1 is the first touch signal line, the line labeled TX2 is the second touch signal line, and the line labeled TX3 is the third touch signal line.

[0395] In at least one embodiment of the present invention, one touch signal line may be provided in three pixels, or two touch signal lines may be provided in three pixels.

[0396] As shown in FIG27A , a first touch signal line TX1 and a second touch signal line TX2 are provided in three pixels;

[0397] In FIG27B , L11 is the first connection portion, L12 is the second connection portion, L13 is the third connection portion, L14 is the fourth connection portion, L15 is the fifth connection portion, and L16 is the sixth connection portion;

[0398] L11 and L12 are both electrically connected to the signal line main body portion TX20 included in TX2, L13 and L14 are in a floating state, and L15 and L16 are both electrically connected to the signal line main body portion TX30 included in TX3.

[0399] As shown in Figure 21, the orthographic projection of each connecting portion on the substrate partially overlaps with the orthographic projection of the shading pattern on the substrate, and is located to the upper right of the orthographic projection of the shading pattern on the substrate; the orthographic projection of each connecting portion on the substrate overlaps with the orthographic projection of the second via H2 on the substrate.

[0400] In FIG28 , the pixel electrode is denoted by PX.

[0401] The array substrate according to at least one embodiment of the present invention further includes a driving module disposed on the base; the driving module is disposed in the peripheral area;

[0402] The driving module includes a multi-stage driving circuit; the driving circuit is used to provide a driving signal for the pixel circuit.

[0403] In a specific implementation, the pixel circuit can be arranged in the display area, and the driving module can be arranged on the first side and / or the second side of the display area; the first side and the second side are opposite sides, for example, the first side can be the left side, and the second side panel can be the right side.

[0404] Optionally, the driving circuit includes an input circuit, a reset circuit and a first node control circuit;

[0405] The input circuit is electrically connected to the input control terminal, the input terminal and the first node respectively, and is used to write the input signal provided by the input terminal into the first node under the control of the input control signal provided by the input control terminal;

[0406] The reset circuit is electrically connected to the reset line, the first node and the first voltage line respectively, and is used to control the connection between the first node and the first voltage line under the control of the reset signal provided by the reset line;

[0407] The first node control circuit is electrically connected to the first second node, the second second node, the second voltage line and the first node, respectively, and is used to control the connection between the first node and the second voltage line under the control of the potential of the first second node, and to control the connection between the first node and the second voltage line under the control of the potential of the second second node.

[0408] Optionally, the first voltage line may be a first low voltage line, and the second voltage line may be a second low voltage line.

[0409] In a specific implementation, the driving circuit may include an input circuit, a reset circuit and a first node control circuit; the input circuit writes the input signal to the first node under the control of the input control signal, the reset circuit resets the potential of the first node under the control of the reset signal, and the first node control circuit controls the potential of the first node under the control of the potential of the second node.

[0410] In at least one embodiment of the present invention, the driving circuit further includes a frame reset circuit;

[0411] The frame reset circuit is electrically connected to the frame reset line, the first node and the second voltage line respectively, and is used to control the connection between the first node and the second voltage line under the control of the frame reset signal provided by the frame reset line.

[0412] In a specific implementation, the driving circuit may further include a frame reset circuit, which resets the potential of the first node under the control of a frame reset signal.

[0413] Optionally, the input circuit includes a first transistor and a second transistor;

[0414] The gate of the first transistor and the gate of the second transistor are electrically connected to the input control terminal, the first electrode of the first transistor is electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the control node;

[0415] A first electrode of the second transistor is electrically connected to the control node, and a second electrode of the second transistor is electrically connected to the first node.

[0416] In at least one embodiment of the present invention, the driving circuit further includes a control circuit;

[0417] The control circuit is electrically connected to the control node, the first node and the third voltage line respectively, and is used to control the connection between the control node and the third voltage line under the control of the potential of the first node.

[0418] In a specific implementation, the driving circuit may further include a control circuit, which controls the connection between the control node and the third voltage line under the control of the potential of the first node.

[0419] Optionally, the third voltage line may be a high voltage line.

[0420] Optionally, the input terminal and the input control terminal are the same signal terminal, and the input terminal is the carry signal output terminal of the adjacent previous n stages; or,

[0421] The input terminal is the carry signal output terminal of the adjacent n previous stages, and the input control terminal is the drive signal output terminal of the adjacent n previous stages;

[0422] n is a positive integer.

[0423] In a specific implementation, the input end and the input control end can both be the carry signal output end of the adjacent first n stages of driving circuits; or, the input end can be the carry signal output end of the adjacent first n stages, and the input control end can be the drive signal output end of the adjacent first n stages.

[0424] Optionally, the reset circuit includes a third transistor and a fourth transistor, and the first node control circuit includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor;

[0425] The gates of the third transistor and the fourth transistor are both electrically connected to the reset line, the first electrode of the third transistor is electrically connected to the first node, the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor; and the second electrode of the third transistor is electrically connected to the control node;

[0426] The second electrode of the fourth transistor is electrically connected to the first voltage line;

[0427] The gate of the fifth transistor and the gate of the sixth transistor are both electrically connected to the first second node, the first electrode of the fifth transistor is electrically connected to the first node, the second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor; the second electrode of the fifth transistor is electrically connected to the control node;

[0428] The second electrode of the sixth transistor is electrically connected to the second voltage line;

[0429] The gate of the seventh transistor and the gate of the eighth transistor are both electrically connected to the second second node, the first electrode of the seventh transistor is electrically connected to the first node, the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor; and the second electrode of the seventh transistor is electrically connected to the control node;

[0430] A second electrode of the eighth transistor is electrically connected to the second voltage line.

[0431] Optionally, the frame reset circuit includes a ninth transistor and a tenth transistor;

[0432] The gate of the ninth transistor is electrically connected to the frame reset line, the first electrode of the ninth transistor is electrically connected to the first node, the second electrode of the ninth transistor is electrically connected to the first electrode of the tenth transistor; and the second electrode of the ninth transistor is electrically connected to the control node;

[0433] A second electrode of the tenth transistor is electrically connected to the second voltage line.

[0434] In at least one embodiment of the present invention, the driving circuit further includes a storage capacitor and a driving signal output terminal; the first plate of the storage capacitor is electrically connected to the first node, and the second plate of the storage capacitor is electrically connected to the driving signal output terminal.

[0435] In a specific implementation, the driving circuit may further include a storage capacitor, which is arranged between the first node and the driving signal output terminal.

[0436] In at least one embodiment of the present invention, the driving circuit may include a driving output circuit and a carry output circuit;

[0437] The drive output circuit is used to control the output of a drive signal under the control of the potential of the first node; the carry output circuit is used to control the output of a carry signal under the control of the potential of the first node.

[0438] In at least one embodiment of the present invention, when the array substrate includes a sixth metal layer (the sixth metal layer may be a touch layer), the array substrate adopts a 10mask process; that is, the array substrate may include a light-shielding metal layer, a semiconductor layer, a gate metal layer, an interlayer dielectric layer, a source-drain metal layer, an organic film layer, a common electrode layer, a third insulating layer, a touch layer, a passivation layer and a pixel electrode layer arranged in sequence along a direction away from the substrate.

[0439] As shown in FIG29 , the driving circuit includes an input circuit 291, a reset circuit 292, a first node control circuit 293, a frame reset circuit 294, a control circuit 295, a storage capacitor C1, a driving output circuit 296, a carry output circuit 297, a driving signal output terminal GT, and a carry signal output terminal OC;

[0440] The input circuit 291 is electrically connected to the input control terminal ICt, the input terminal I1, and the first node PU, respectively, and is configured to write the input signal provided by the input terminal I1 into the first node PU under the control of the input control signal provided by the input control terminal ICt. The input circuit 291 is also electrically connected to the control node NC.

[0441] The reset circuit 292 is electrically connected to the reset line RST, the first node PU and the first voltage line V1 respectively, and is used to control the connection between the first node PU and the first voltage line V1 under the control of the reset signal provided by the reset line RST;

[0442] The first node control circuit 293 is electrically connected to the first second node PDo, the second second node PDe, the second voltage line V2 and the first node PU, respectively, and is used to control the connection between the first node PU and the second voltage line V2 under the control of the potential of the first second node PDo, and to control the connection between the first node PU and the second voltage line V2 under the control of the potential of the second second node PDe.

[0443] The frame reset circuit 294 is electrically connected to the frame reset line STV, the first node PU and the second voltage line V2, respectively, and is used to control the connection between the first node PU and the second voltage line V2 under the control of the frame reset signal provided by the frame reset line STV;

[0444] The control circuit 295 is electrically connected to the control node NC, the first node PU, and the third voltage line V3, respectively, and is configured to control the connection between the control node NC and the third voltage line V3 under the control of the potential of the first node PU;

[0445] The first plate of the storage capacitor C1 is electrically connected to the first node PU, and the second plate of the storage capacitor C1 is electrically connected to the driving signal output terminal GT;

[0446] The driving output circuit 296 is electrically connected to the first node PU, the clock signal line CLK, and the driving signal output terminal GT, respectively, and is used to control the connection between the driving signal output terminal GT and the clock signal line CLK under the control of the potential of the first node PU, and output the driving signal through the driving signal output terminal GT;

[0447] The carry output circuit 297 is electrically connected to the first node PU, the clock signal line CLK and the carry signal output terminal OC respectively, and is used to control the electrical connection between the carry signal output terminal OC and the clock signal line CLK under the control of the potential of the first node PU, and control the output of the carry signal through the carry signal output terminal OC.

[0448] As shown in FIG30 , based on at least one embodiment of the driving circuit shown in FIG29 , the driving circuit may further include a first second-node control circuit 301, a second second-node control circuit 302, a driving reset circuit 303, a carry reset circuit 304, a driving output reset circuit 305, and a second-node reset circuit.

[0449] The first second-node control circuit 301 is electrically connected to the first control voltage line VDDO, the first node PU, the first second node PDo, and the second voltage line V2, respectively, and is configured to control the potential of the first second node PDo under the control of the first control voltage provided by the first control voltage line VDDO and the potential of the first node PU;

[0450] The second second-node control circuit 302 is electrically connected to the second control voltage line VDDE, the first node PU, the first second node PDo, and the second voltage line V2, respectively, and is configured to control the potential of the second second node PDe under the control of the second control voltage provided by the second control voltage line VDDE and the potential of the first node PU;

[0451] The driving reset circuit 303 is electrically connected to the first second node PDo, the second second node PDe, the driving signal output terminal GT and the first voltage line V1, respectively, and is used to control the connection between the driving signal output terminal GT and the first voltage line V1 under the control of the potential of the first second node PDo, and to control the connection between the driving signal output terminal GT and the first voltage line V1 under the control of the potential of the second second node PDe;

[0452] The carry reset circuit 304 is electrically connected to the first second node PDo, the second second node PDe, the carry signal output terminal OC, and the second voltage line V2, respectively, and is configured to control the communication between the carry signal output terminal OC and the second voltage line V2 under the control of the potential of the first second node PDo, and to control the communication between the carry signal output terminal OC and the second voltage line V2 under the control of the potential of the second second node PDe;

[0453] The driving output reset circuit 305 is electrically connected to the output reset control line R1, the driving signal output terminal GT and the first voltage line V1, respectively, and is used to control the connection between the driving signal output terminal GT and the first voltage line V1 under the control of the output reset control signal provided by the output reset control line R1;

[0454] The second node reset circuit 306 is electrically connected to the input control terminal ICt, the first second node PDo, the second second node PDe and the second voltage line V2, respectively, and is used to control the connection between the first second node PDo and the second voltage line V2, and control the connection between the second second node PDe and the second voltage line V2 under the control of the input control signal provided by the input control terminal ICt.

[0455] Optionally, the first second node control circuit may include an eleventh transistor and a twelfth transistor;

[0456] The gate of the eleventh transistor and the first electrode of the eleventh transistor are both electrically connected to the first control voltage line, and the second electrode of the eleventh transistor is electrically connected to the first second node;

[0457] The gate of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the first second node, and the second electrode of the twelfth transistor is electrically connected to the second voltage line;

[0458] The second second-node control circuit may include a thirteenth transistor and a fourteenth transistor;

[0459] The gate electrode of the thirteenth transistor and the first electrode of the thirteenth transistor are both electrically connected to the second control voltage line, and the second electrode of the thirteenth transistor is electrically connected to the second second node;

[0460] The gate of the fourteenth transistor is electrically connected to the first node, the first electrode of the fourteenth transistor is electrically connected to the second second node, and the second electrode of the fourteenth transistor is electrically connected to the second voltage line;

[0461] The driving reset circuit may include a fifteenth transistor and a sixteenth transistor;

[0462] A gate of the fifteenth transistor is electrically connected to the first second node, a first electrode of the fifteenth transistor is electrically connected to the drive signal output terminal, and a second electrode of the fifteenth transistor is electrically connected to the first voltage line;

[0463] A gate of the sixteenth transistor is electrically connected to the second second node, a first electrode of the sixteenth transistor is electrically connected to the drive signal output terminal, and a second electrode of the sixteenth transistor is electrically connected to the first voltage line;

[0464] The carry reset circuit may include a seventeenth transistor and an eighteenth transistor;

[0465] A gate of the seventeenth transistor is electrically connected to the first second node, a first electrode of the seventeenth transistor is electrically connected to the carry signal output terminal, and a second electrode of the seventeenth transistor is electrically connected to the second voltage line;

[0466] a gate of an eighteenth transistor electrically connected to the second second node, a first electrode of the eighteenth transistor electrically connected to the carry signal output terminal, and a second electrode of the eighteenth transistor electrically connected to the second voltage line;

[0467] The drive output reset circuit includes a nineteenth transistor;

[0468] The gate of the nineteenth transistor is electrically connected to the output reset control line, the first electrode of the nineteenth transistor is electrically connected to the drive signal output terminal, and the second electrode of the nineteenth transistor is electrically connected to the first voltage line;

[0469] The control circuit includes a twentieth transistor;

[0470] The gate of the twentieth transistor is electrically connected to the first node, the first electrode of the twentieth transistor is electrically connected to the third voltage line, and the second electrode of the twentieth transistor is electrically connected to the control node;

[0471] The drive output circuit includes a twenty-first transistor, the carry output circuit includes a twenty-second transistor, and the second node reset circuit 306 includes a twenty-third transistor and a twenty-fourth transistor;

[0472] The gate of the twenty-first transistor is electrically connected to the first node, the first electrode of the twenty-first transistor is electrically connected to the clock signal line, and the second electrode of the twenty-first transistor is electrically connected to the driving signal output terminal;

[0473] The gate of the twenty-second transistor is electrically connected to the first node, the first electrode of the twenty-second transistor is electrically connected to the clock signal line, and the second electrode of the twenty-second transistor is electrically connected to the carry signal output terminal;

[0474] a gate of the twenty-third transistor is electrically connected to the input control terminal ICt, a first electrode of the twenty-third transistor is electrically connected to the first second node, and a second electrode of the twenty-third transistor is electrically connected to the second voltage line;

[0475] A gate of the twenty-fourth transistor is electrically connected to the input control terminal ICt, a first electrode of the twenty-fourth transistor is electrically connected to the second second node, and a second electrode of the twenty-fourth transistor is electrically connected to the second voltage line.

[0476] As shown in FIG31, based on at least one embodiment of the driving circuit shown in FIG30,

[0477] The input circuit includes a first transistor M1 and a second transistor M2;

[0478] The gate of the first transistor M1 and the gate of the second transistor M2 are electrically connected to the input control terminal ICt, the first electrode of the first transistor M1 is electrically connected to the input terminal I1, and the second electrode of the first transistor M1 is electrically connected to the control node NC;

[0479] A first electrode of the second transistor M2 is electrically connected to the control node NC, and a second electrode of the second transistor M2 is electrically connected to the first node PU;

[0480] The reset circuit includes a third transistor M3 and a fourth transistor M4, and the first node control circuit includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8;

[0481] The gate of the third transistor M3 and the gate of the fourth transistor M4 are both electrically connected to the reset line RST, a first electrode of the third transistor M3 is electrically connected to the first node PU, a second electrode of the third transistor M3 is electrically connected to the first electrode of the fourth transistor M4; and a second electrode of the third transistor M3 is electrically connected to the control node NC;

[0482] A second electrode of the fourth transistor M4 is electrically connected to the first low voltage line LVGL;

[0483] The gate of the fifth transistor M5 and the gate of the sixth transistor M6 are both electrically connected to the first second node PDo, the first electrode of the fifth transistor M5 is electrically connected to the first node PU, the second electrode of the fifth transistor M5 is electrically connected to the first electrode of the sixth transistor M6; the second electrode of the fifth transistor M5 is electrically connected to the control node NC;

[0484] The second electrode of the sixth transistor M6 is electrically connected to the second low voltage line VGL;

[0485] A gate of the seventh transistor M7 and a gate of the eighth transistor M8 are both electrically connected to the second second node PDe, a first electrode of the seventh transistor M7 is electrically connected to the first node PU, a second electrode of the seventh transistor M7 is electrically connected to the first electrode of the eighth transistor M8; and a second electrode of the seventh transistor M7 is electrically connected to the control node NC.

[0486] A second electrode of the eighth transistor M8 is electrically connected to the second low voltage line VGL;

[0487] The frame reset circuit includes a ninth transistor M9 and a tenth transistor M10;

[0488] The gate of the ninth transistor M9 is electrically connected to the frame reset line STV, the first electrode of the ninth transistor M9 is electrically connected to the first node PU, the second electrode of the ninth transistor M9 is electrically connected to the first electrode of the tenth transistor M10; and the second electrode of the ninth transistor M9 is electrically connected to the control node NC.

[0489] A second electrode of the tenth transistor M10 is electrically connected to the second low voltage line VGL;

[0490] The first second node control circuit may include an eleventh transistor M11 and a twelfth transistor M12;

[0491] The gate of the eleventh transistor M11 and the first electrode of the eleventh transistor M11 are both electrically connected to the first control voltage line VDDO, and the second electrode of the eleventh transistor M11 is electrically connected to the first second node PDo;

[0492] The gate of the twelfth transistor M12 is electrically connected to the first node PU, the first electrode of the twelfth transistor M12 is electrically connected to the first second node PDo, and the second electrode of the twelfth transistor M12 is electrically connected to the second low voltage line VGL;

[0493] The second second node control circuit may include a thirteenth transistor M13 and a fourteenth transistor M14;

[0494] The gate of the thirteenth transistor M13 and the first electrode of the thirteenth transistor M13 are both electrically connected to the second control voltage line VDDE, and the second electrode of the thirteenth transistor M13 is electrically connected to the second second node PDe;

[0495] The gate of the fourteenth transistor M14 is electrically connected to the first node PU, the first electrode of the fourteenth transistor M14 is electrically connected to the second second node PDe, and the second electrode of the fourteenth transistor M14 is electrically connected to the second low voltage line VGL;

[0496] The driving reset circuit may include a fifteenth transistor M15 and a sixteenth transistor M16;

[0497] A gate of the fifteenth transistor M15 is electrically connected to the first second node PDo, a first electrode of the fifteenth transistor M15 is electrically connected to the driving signal output terminal GT, and a second electrode of the fifteenth transistor M15 is electrically connected to the first low voltage line LVGL;

[0498] A gate of the sixteenth transistor M16 is electrically connected to the second second node PDe, a first electrode of the sixteenth transistor M16 is electrically connected to the driving signal output terminal GT, and a second electrode of the sixteenth transistor M16 is electrically connected to the first low voltage line LVGL;

[0499] The carry reset circuit may include a seventeenth transistor M17 and an eighteenth transistor M18;

[0500] A gate of the seventeenth transistor M17 is electrically connected to the first second node PDo, a first electrode of the seventeenth transistor M17 is electrically connected to the carry signal output terminal OC, and a second electrode of the seventeenth transistor M17 is electrically connected to the second low voltage line VGL;

[0501] A gate of the eighteenth transistor M18 is electrically connected to the second second node PDe, a first electrode of the eighteenth transistor M18 is electrically connected to the carry signal output terminal OC, and a second electrode of the eighteenth transistor M18 is electrically connected to the second low voltage line VGL;

[0502] The drive output reset circuit includes a nineteenth transistor M19;

[0503] A gate of the nineteenth transistor M19 is electrically connected to the output reset control line R1, a first electrode of the nineteenth transistor M19 is electrically connected to the drive signal output terminal GT, and a second electrode of the nineteenth transistor M19 is electrically connected to the first low voltage line LVGL;

[0504] The control circuit includes a twentieth transistor M20;

[0505] A gate of the twentieth transistor M20 is electrically connected to the first node PU, a first electrode of the twentieth transistor M20 is electrically connected to the high voltage line VDD, and a second electrode of the twentieth transistor M20 is electrically connected to the control node NC;

[0506] The drive output circuit includes a twenty-first transistor M21, the carry output circuit includes a twenty-second transistor M22, and the second node reset circuit 306 includes a twenty-third transistor M23 and a twenty-fourth transistor M24;

[0507] A gate of the twenty-first transistor M21 is electrically connected to the first node PU, a first electrode of the twenty-first transistor M21 is electrically connected to the clock signal line CLK, and a second electrode of the twenty-first transistor M21 is electrically connected to the driving signal output terminal GT;

[0508] The gate of the twenty-second transistor M22 is electrically connected to the first node PU, the first electrode of the twenty-second transistor M22 is electrically connected to the clock signal line CLK, and the second electrode of the twenty-second transistor M22 is electrically connected to the carry signal output terminal OC;

[0509] A gate of the twenty-third transistor M23 is electrically connected to the input control terminal ICt, a first electrode of the twenty-third transistor M23 is electrically connected to the first second node PDo, and a second electrode of the twenty-third transistor M23 is electrically connected to the second low voltage line VGL;

[0510] A gate of the twenty-fourth transistor M24 is electrically connected to the input control terminal ICt, a first electrode of the twenty-fourth transistor M24 is electrically connected to the second second node PDe, and a second electrode of the twenty-fourth transistor M24 is electrically connected to the second low voltage line VG.

[0511] In at least one embodiment of the driving circuit shown in FIG31 , the input control terminal ICt is electrically connected to the input terminal I1, and both ICt and I1 can be electrically connected to the carry signal output terminal of the adjacent n-stage driving circuit, where n can be a positive integer.

[0512] All transistors may be n-type transistors, but are not limited thereto.

[0513] During operation, at least one embodiment of the driving circuit shown in FIG31 increases the leakage current of the transistor when the gate-source voltage is 0V due to the increased mobility of the top-gate process. To prevent the increased leakage current of the transistor electrically connected to the first node PU from affecting the operation of the first node, the transistor electrically connected to the first node PU is connected in series using two transistors. The input signal is written to the first node PU via M1 and M2. The node between M1 and M2 is the control node NC, and the control node N0 is controlled by PU and M20. When the potential of PU is high, M20 is turned on and charges the middle node between M1 and M2 with a high voltage. The drain-source voltage of M2 is reduced compared to when only one input transistor is used, thereby improving the leakage current of the first node and enhancing the stability of the driving circuit. FIG32 shows the potential of the first node PU within the LH pit during operation of at least one embodiment of the driving circuit shown in FIG31. It can be seen that within the LH pit, the potential of the first node PU can be well maintained at a high voltage, and the driving circuit has good stability.

[0514] Furthermore, in at least one embodiment of the driving circuit shown in Figure 31, the intermediate node between M5 and M6, the intermediate node between M7 and M8, the intermediate node between M11 and M12, and the intermediate node between M13 and M14 are all electrically connected to the control node NC to reduce the leakage current of the first node PU.

[0515] In at least one embodiment of the present invention, the array substrate further includes a third metal layer and a second insulating layer; the third metal layer is disposed on a side of the semiconductor layer close to the substrate, and the second insulating layer is disposed between the semiconductor layer and the third metal layer;

[0516] The first electrode plate is formed on the first metal layer, and the second electrode plate includes a first electrode plate portion and a second electrode plate portion electrically connected to each other;

[0517] The first electrode plate is partially formed on the second metal layer, and the second electrode plate is partially formed on the third metal layer;

[0518] An orthographic projection of the first electrode plate on the substrate, an orthographic projection of the first electrode plate portion on the substrate, and an orthographic projection of the second electrode plate portion on the substrate at least partially overlap.

[0519] In a specific implementation, the array substrate may further include a third metal layer and a second insulating layer, the first electrode plate may be formed on the first metal layer, the second electrode plate may include a first electrode plate portion and a second electrode plate portion, the first electrode plate portion is formed on the second metal layer, the second electrode plate portion is formed on the third metal layer, and the orthographic projection of the first electrode plate on the substrate, the orthographic projection of the first electrode plate portion on the substrate, and the orthographic projection of the second electrode plate portion on the substrate at least partially overlap.

[0520] In a specific implementation, a first metal layer, a second metal layer, and a third metal layer can be used to form a storage capacitor. The first metal layer and the upper second metal layer form a capacitor. At the same time, the first metal layer and the lower third metal layer form a capacitor. The size of the capacitor is proportional to the area of ​​the plate. Therefore, for a storage capacitor of the same size, the area of ​​the plate can be half that of the plate formed using three metal layers compared to two metal layers. This can reduce the space occupied by the drive circuit and facilitate the realization of a narrow frame. In at least one embodiment of the present invention, the plate of the storage capacitor is located in a blank area of ​​the drive circuit architecture (where there is no wiring or transistor), and the capacitance value of the storage capacitor is greater than or equal to 1pF and less than or equal to 3pF.

[0521] FIG. 33 is a structural diagram of at least one embodiment of a storage capacitor.

[0522] FIG34 is a cross-sectional view taken along line AA′ in FIG33 .

[0523] In FIG34 , C1a is a plate, C1b1 is a first plate portion, and C1b2 is a second plate portion; C1b1 and C1b2 are electrically connected.

[0524] In FIG34 , the reference numeral 201 is a first insulating layer, the reference numeral 202 is a second insulating layer, and the reference numeral 203 is a third insulating layer.

[0525] Optionally, the first metal layer may be a gate metal layer, the second metal layer may be a source / drain metal layer, and the third metal layer may be a light-shielding metal layer.

[0526] Optionally, the first electrode plate includes a first first electrode plate portion, a second first electrode plate portion, and a third first electrode plate portion electrically connected to each other;

[0527] The first electrode portion includes a first second electrode portion, a second second electrode portion, and a third second electrode portion that are electrically connected to each other;

[0528] The second electrode portion includes a first third electrode portion, a second third electrode portion, and a third third electrode portion that are electrically connected to each other;

[0529] The first first electrode plate portion, the second first electrode plate portion and the third first electrode plate portion are all formed in the first metal layer, the first second electrode plate portion, the second second electrode plate portion and the third second electrode plate portion are all formed in the second metal layer, and the first third electrode plate portion, the second third electrode plate portion and the third third electrode plate portion are all formed in the third metal layer.

[0530] In a specific implementation, the first electrode plate may include three first electrode plate portions, the first electrode plate portion may include three second electrode plate portions, and the second electrode plate portion may include three third electrode plate portions. The electrode plate portions may be set by utilizing the space between the transistor and the signal line, as well as the space between the transistors. This may increase the capacitance value of the storage capacitor while effectively utilizing the space.

[0531] FIG. 35 is a layout diagram of at least one embodiment of the two-stage driving circuit shown in FIG. 31 .

[0532] Figure 36 is a layout diagram of the third metal layer in Figure 35, Figure 37 is a layout diagram of the semiconductor layer in Figure 35, Figure 38 is a layout diagram of the first metal layer in Figure 35, Figure 39 is a layout diagram of the second metal layer in Figure 35, and Figure 40 is a layout diagram of the fourth metal layer in Figure 35.

[0533] The third metal layer may be a light-shielding metal layer, the first metal layer may be a gate metal layer, the second metal layer may be a source / drain metal layer, and the fourth metal layer may be a pixel electrode layer.

[0534] In Figure 35, the first low voltage line is labeled LVGL1, the second low voltage line is labeled LVGL2, the first part of the storage capacitor C1 is labeled C11, the second part of the storage capacitor C1 is labeled C12, and the third part of the storage capacitor C1 is labeled C13; the high voltage line is labeled VGH, the first clock signal line is labeled CLK1, the second clock signal line is labeled CLK2, the third clock signal line is labeled CLK3, the fourth clock signal line is labeled CLK4, and the start signal line is labeled STV0.

[0535] In FIG36 , the first third electrode plate portion is labeled C1b13 , the second third electrode plate portion is labeled C1b23 , and the third third electrode plate portion is labeled C1b33 .

[0536] In FIG37 , A21 is the active pattern of M21, A22 is the active pattern of M22, A5 is the active pattern of M5, A6 is the active pattern of M6, A7 is the active pattern of M7, and A8 is the active pattern of M8.

[0537] In FIG38 , the first electrode plate portion is labeled C1b11 , the second first electrode plate portion is labeled C1b21 , and the third first electrode plate portion is labeled C1b31 .

[0538] In FIG39 , the first second electrode plate portion is labeled C1b12 , the second second electrode plate portion is labeled C1b22 , and the third second electrode plate portion is labeled C1b32 .

[0539] In FIG. 40 , each pattern is a conductive pattern.

[0540] As shown in FIG35 to FIG40 , the orthographic projection of C1b11 on the base, the orthographic projection of C1b12 on the base, and the orthographic projection of C1b13 on the base at least partially overlap;

[0541] The orthographic projection of C1b21 on the base, the orthographic projection of C1b22 on the base, and the orthographic projection of C1b23 on the base at least partially overlap;

[0542] The orthographic projection of C1b31 on the base, the orthographic projection of C1b32 on the base, and the orthographic projection of C1b33 on the base at least partially overlap.

[0543] In at least one embodiment of the present invention, the driving circuit includes a driving output circuit and a carry output circuit;

[0544] The drive output circuit is used to control the output of the drive signal under the control of the potential of the first node; the carry output circuit is used to control the output of the carry signal under the control of the potential of the first node;

[0545] The orthographic projection of the active pattern of the transistor included in the driving output circuit on the substrate and the orthographic projection of the first electrode portion on the substrate are arranged along a first direction;

[0546] The active pattern of the transistor included in the carry output circuit is arranged on a side of the active pattern of the transistor included in the drive output circuit close to the display area;

[0547] The orthographic projection of the second first electrode portion on the substrate is arranged on a side of the orthographic projection of the active pattern of the transistor included in the carry output circuit on the substrate close to the display area;

[0548] An orthographic projection of the third first electrode portion on the substrate and an active pattern of a transistor included in the first node control circuit are arranged along a first direction.

[0549] Optionally, the first direction may be a vertical direction.

[0550] As shown in FIG35 to FIG40 , the drive output circuit includes a twenty-first transistor M21, and the carry output circuit includes a twenty-second transistor M22;

[0551] An orthographic projection of the active pattern A21 of the twenty-first transistor M21 on the substrate and an orthographic projection of the first first electrode plate portion C1b11 on the substrate are arranged in a vertical direction;

[0552] The active pattern A22 of the twenty-second transistor M22 is disposed on a side of the active pattern A21 of the twenty-first transistor M21 close to the display area;

[0553] The orthographic projection of the first second electrode portion C1b12 on the substrate is disposed on a side of the orthographic projection of the active pattern A22 of the twenty-second transistor M22 on the substrate close to the display area;

[0554] The first node control circuit includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8;

[0555] The orthographic projection of the first third electrode portion C1b13 on the substrate is aligned with the active pattern A5 of M5 in a vertical direction;

[0556] The orthographic projection of the first third electrode portion C1b13 on the substrate is aligned with the active pattern A6 of M6 in a vertical direction;

[0557] The orthographic projection of the first third electrode portion C1b13 on the substrate is aligned with the active pattern A7 of M7 in a vertical direction;

[0558] The orthographic projection of the first third electrode portion C1b13 on the substrate is aligned with the active pattern A8 of M8 in a vertical direction.

[0559] In at least one embodiment of the present invention, the peripheral region includes a fan-out region and a gate transistor arrangement region arranged between the fan-out region and the display region;

[0560] The array substrate includes M gate control lines and a gate portion provided in the gate transistor setting area; the gate portion includes a plurality of gate parts; M is an integer greater than 1;

[0561] The gating part includes multiple gating transistors; the gates of the multiple gating transistors are electrically connected to the corresponding gating control lines, the first electrodes of the multiple gating transistors are electrically connected to the corresponding data voltage supply lines, and the second electrodes of the multiple gating transistors are electrically connected to the corresponding data lines.

[0562] In a specific implementation, the peripheral area may include a gate transistor setting area arranged between the display area and the fan-out area. In the gate transistor setting area, M gate control lines and a gate part are provided. The gate part includes multiple gate parts. The gate part includes multiple gate transistors. The multiple gate transistors respectively control the connection or disconnection between the data voltage supply line and the data line under the control of the gate control signal provided by the corresponding gate control line.

[0563] FIG41 is a layout diagram of at least one embodiment of a gate control line and a gate portion provided in a gate transistor setting region, included in the array substrate, in at least one embodiment of the present invention.

[0564] Figure 42 is a layout diagram of the third metal layer in Figure 41, Figure 43 is a layout diagram of the semiconductor layer in Figure 41, Figure 44 is a layout diagram of the first metal layer in Figure 41, Figure 45 is a layout diagram of the second metal layer in Figure 41, and Figure 46 is a layout diagram of the sixth metal layer in Figure 41.

[0565] In FIG41 , the first selection control line is labeled MUX1, the second selection control line is labeled MUX2, the third selection control line is labeled MUX3, and the fourth selection control line is labeled MUX4;

[0566] The first gate transistor is labeled TM1, the second gate transistor is labeled TM2, the third gate transistor is labeled TM3, the fourth gate transistor is labeled TM4, the fifth gate transistor is labeled TM5, the sixth gate transistor is labeled TM6, the seventh gate transistor is labeled TM7, the eighth gate transistor is labeled TM8, the ninth gate transistor is labeled TM9, the tenth gate transistor is labeled TM10, the eleventh gate transistor is labeled TM11, and the twelfth gate transistor is labeled TM12;

[0567] LD1 is a first data voltage supply line, LD2 is a second data voltage supply line, LD3 is a third data voltage supply line, LD4 is a fourth data voltage supply line, LD5 is a fifth data voltage supply line, and LD6 is a sixth data voltage supply line;

[0568] DL1 is the first data line, DL2 is the second data line, DL3 is the third data line, DL4 is the fourth data line, DL5 is the fifth data line, DL6 is the sixth data line, DL7 is the seventh data line, DL8 is the eighth data line, DL9 is the ninth data line, DL10 is the tenth data line, DL11 is the eleventh data line, and DL12 is the twelfth data line;

[0569] The gate of TM1 is electrically connected to the first selection control line MUX1, the first electrode of TM1 is electrically connected to the first data voltage supply line LD1, and the second electrode of TM1 is electrically connected to the first data line DL1;

[0570] The gate line of TM2 is electrically connected to the second selection control line MUX2, the first electrode of TM2 is electrically connected to the first data voltage supply line LD1, and the second electrode of TM2 is electrically connected to the second data line DL2;

[0571] A gate electrode of TM3 is electrically connected to a third selection control line MUX3 , a first electrode of TM3 is electrically connected to a second data voltage supply line LD2 , and a second electrode of TM3 is electrically connected to a third data line DL3 ;

[0572] The gate line of TM4 is electrically connected to the fourth selection control line MUX4, the first electrode of TM4 is electrically connected to the second data voltage supply line LD2, and the second electrode of TM4 is electrically connected to the fourth data line DL4;

[0573] A gate electrode of TM5 is electrically connected to the first selection control line MUX1 , a first electrode of TM5 is electrically connected to the third data voltage supply line LD3 , and a second electrode of TM5 is electrically connected to the fifth data line DL5 ;

[0574] The gate line of TM6 is electrically connected to the second selection control line MUX2, the first electrode of TM6 is electrically connected to the third data voltage supply line LD3, and the second electrode of TM6 is electrically connected to the sixth data line DL6;

[0575] A gate electrode of TM7 is electrically connected to the third selection control line MUX3 , a first electrode of TM7 is electrically connected to the fourth data voltage supply line LD4 , and a second electrode of TM7 is electrically connected to the seventh data line DL7 ;

[0576] The gate line of TM8 is electrically connected to the fourth selection control line MUX4, the first electrode of TM8 is electrically connected to the fourth data voltage supply line LD4, and the second electrode of TM8 is electrically connected to the eighth data line DL8;

[0577] A gate electrode of TM9 is electrically connected to the first selection control line MUX1 , a first electrode of TM9 is electrically connected to the fifth data voltage supply line LD5 , and a second electrode of TM9 is electrically connected to the ninth data line DL9 ;

[0578] The gate line of TM10 is electrically connected to the second gate control line MUX2, the first electrode of TM10 is electrically connected to the fifth data voltage supply line LD5, and the second electrode of TM10 is electrically connected to the tenth data line DL10;

[0579] A gate electrode of TM11 is electrically connected to the third selection control line MUX3 , a first electrode of TM11 is electrically connected to the sixth data voltage supply line LD6 , and a second electrode of TM11 is electrically connected to the eleventh data line DL11 ;

[0580] A gate line of TM12 is electrically connected to the fourth gate control line MUX4 , a first electrode of TM12 is electrically connected to the sixth data voltage supply line LD6 , and a second electrode of TM12 is electrically connected to the twelfth data line DL12 .

[0581] In FIG41 , the gate portion includes TM1 to TM12, and the gate portion includes a first gate portion, a second gate portion, a third gate portion, a fourth gate portion, a fifth gate portion, and a sixth gate portion;

[0582] The first gating part includes TM1 and TM2; the second gating part includes TM3 and TM4; the third gating part includes TM5 and TM6; the fourth gating part includes TM7 and TM8; the fifth gating part includes TM9 and TM10; and the sixth gating part includes TM11 and TM12.

[0583] In FIG43 , AM1 is the active pattern of TM1, AM2 is the active pattern of TM2, AM3 is the active pattern of TM3, AM4 is the active pattern of TM4, AM5 is the active pattern of TM5, AM6 is the active pattern of TM6, AM7 is the active pattern of TM7, AM8 is the active pattern of TM8, AM9 is the active pattern of TM9, AM10 is the active pattern of TM10, AM11 is the active pattern of TM11, and AM12 is the active pattern of TM12.

[0584] In FIG46 , the lead labeled TXL is a touch signal lead.

[0585] Optionally, in the region where the gate transistor is provided, the array substrate further comprises a third metal layer; the third metal layer is provided on a side of the semiconductor layer close to the substrate;

[0586] In the selection transistor setting area, the conductive pattern on the third metal layer is in a floating state.

[0587] In a specific implementation, in the region where the gate transistor is provided, the conductive pattern on the third metal layer may be a light-shielding pattern, which is in a floating state and is used to protect the active pattern of each gate transistor from backlight.

[0588] In FIG42 , the light-shielding pattern labeled ZX is a light-shielding pattern. In a specific implementation, when the light-shielding pattern ZX is electrically connected to the gate electrode formed in the first metal layer, the light-shielding pattern ZX is multiplexed as the bottom gate of the selection transistor.

[0589] In at least one embodiment of the array substrate shown in FIG. 41 to FIG. 46 , the light-shielding pattern ZX may also be in a floating state, which can reduce the load of the selection control signal and help improve the charging capacity of the selection transistor.

[0590] In a specific implementation, the shading pattern included in the third metal layer can also be set to be in a floating state in the pixel area, while in the GOA area (the GOA area is the area where the driving circuit is set) and the selection transistor setting area, the shading pattern included in the third metal layer can be connected to the gate signal.

[0591] In at least one embodiment of the present invention, the peripheral area further includes an integrated circuit arrangement area arranged in a fan-out area away from the display area;

[0592] The array substrate includes a driving integrated circuit and a plurality of gate control signal supply lines arranged in the integrated circuit arrangement area;

[0593] an mth gate control signal supply line electrically connected to the driving integrated circuit and the mth gate control line, respectively, for receiving the mth gate control signal from the driving integrated circuit and providing the mth gate control signal to the mth gate control line;

[0594] m is a positive integer less than or equal to M.

[0595] As shown in FIG47 , the area labeled FO is the fan-out area, and the area labeled FI is the integrated circuit setting area;

[0596] In FIG47 , LX1 is a first strobe control signal supply line, LX2 is a second strobe control signal supply line, LX3 is a third strobe control signal supply line, and LX4 is a fourth strobe control signal supply line.

[0597] LX1, LX2, LX3 and LX4 are all arranged in the integrated circuit arrangement area FI;

[0598] In FIG47 , the first selection control line is labeled MUX1, the second selection control line is labeled MUX2, the third selection control line is labeled MUX3, and the fourth selection control line is labeled MUX4;

[0599] The line labeled L01 is the first gate connection line, the line labeled L02 is the second gate connection line, the line labeled L03 is the third gate connection line, and the line labeled L04 is the fourth gate connection line;

[0600] MUX1 is electrically connected to LX1 through L01; MUX2 is electrically connected to LX1 through L02; MUX3 is electrically connected to LX3 through L03; and MUX4 is electrically connected to LX4 through L04.

[0601] Figure 48 is a layout diagram of the first metal layer in Figure 47, Figure 49 is a layout diagram of the second metal layer in Figure 47, Figure 50 is a layout diagram of the sixth metal layer in Figure 47, and Figure 51 is a layout diagram of the fourth metal layer in Figure 47.

[0602] In at least one embodiment of the present invention, the peripheral area further includes an integrated circuit arrangement area disposed in the fan-out area away from the display area; the array substrate includes a driver integrated circuit disposed in the integrated circuit arrangement area;

[0603] The array substrate includes a touch signal line arranged in the display area;

[0604] The data voltage supply line is electrically connected to the driver integrated circuit via a first connection line provided in the fan-out region, and is used for receiving a data voltage provided by the driver integrated circuit;

[0605] The touch signal line is electrically connected to the driver integrated circuit via a second connection line provided in the fan-out area, and is used for receiving a touch sensing signal provided by the driver integrated circuit.

[0606] As shown in FIG50 , the line labeled TX is the touch signal line;

[0607] As shown in FIG48 and FIG49 , the line labeled LDT1 is a first data voltage supply line, the line labeled LDT2 is a second data voltage supply line; the line labeled LT11 is a first first connection line, and the line labeled LT21 is a second first connection line;

[0608] Both LDT1 and LDT2 are formed in the second metal layer;

[0609] LDT1 is electrically connected to the driver integrated circuit via a first connecting line LT11 formed on the first metal layer;

[0610] LDT2 is electrically connected to the driver integrated circuit via a second connection line LT21 formed on the second metal layer;

[0611] As shown in Figures 47 to 51, the orthographic projection of LT11 on the substrate at least partially overlaps with the orthographic projection of LT21 on the substrate, and the data voltage supply line is electrically connected to the driver integrated circuit through a connecting line formed on the first metal layer and a connecting line formed on the second metal layer, so as to save space.

[0612] As shown in FIG50 , the touch signal line TX is electrically connected to the driver integrated circuit via a second connection line LT2 provided in the fan-out region, and is used to receive a touch sensing signal provided by the driver integrated circuit.

[0613] In FIG51 , the first conductive wire is labeled DX1, the second conductive wire is labeled DX2, the third conductive wire is labeled DX3, and the fourth conductive wire is labeled DX4.

[0614] Optionally, the array substrate further includes a sixth metal layer;

[0615] The second connecting line is formed in the sixth metal layer.

[0616] During specific implementation, the second connecting line may be provided in the sixth metal layer.

[0617] Optionally, part of the first connecting lines is formed in the first metal layer, and another part of the first connecting lines is formed in the second metal layer.

[0618] In at least one embodiment of the present invention, the array substrate further includes a third metal layer; the third metal layer is disposed on a side of the semiconductor layer close to the substrate;

[0619] A portion of the first connecting line is formed in the first metal layer, another portion of the first connecting line is formed in the second metal layer, and another portion of the first connecting line is formed in the third metal layer.

[0620] In a specific implementation, part of the first connecting lines can be set to be formed in the first metal layer, part of the first connecting lines can be set to be formed in the second metal layer, and part of the connecting lines can be set to be formed in the third metal layer. The orthographic projection of the first connecting line set in the first metal layer on the substrate, the orthographic projection of the second connecting line set in the second metal layer on the substrate, and the orthographic projection of the third connecting line set in the third metal layer on the substrate can at least partially overlap to save space.

[0621] In at least one embodiment of the present invention, the array substrate further includes a touch signal line;

[0622] The touch signal line is formed on the second metal layer;

[0623] The array substrate further includes a fourth metal layer, a fifth metal layer and a sixth metal layer;

[0624] The sixth metal layer is disposed on a side of the second metal layer away from the substrate, and the fifth metal layer is disposed between the second metal layer and the sixth metal layer;

[0625] The touch signal line is electrically connected to the second conductive pattern formed on the fourth metal layer through the sixth via hole; the second conductive pattern is electrically connected to the common electrode formed on the fifth metal layer.

[0626] In a specific implementation, the array substrate may not be provided with a sixth metal layer, and the touch signal line may be set to be formed on the second metal layer, and the touch signal line is electrically connected to the second conductive pattern formed on the fourth metal layer through the sixth via hole, and the second conductive pattern is electrically connected to the common electrode formed on the fifth metal layer.

[0627] In at least one embodiment of the present invention, when the array substrate is not provided with a sixth metal layer, a 9-mask process is adopted, that is, a light-shielding metal layer, a semiconductor layer, a gate metal layer, an interlayer dielectric layer, a source-drain metal layer, an organic film layer, a common electrode layer, a passivation layer and a pixel electrode layer are sequentially provided on the substrate.

[0628] FIG52 is a planar layout diagram of a portion of an array substrate according to at least one embodiment of the present invention.

[0629] In FIG52 , the via hole labeled H1 is the first via hole, the via hole labeled H0 is the TX via hole, the via hole labeled TX is the touch signal line, and the via hole labeled DL is the data line.

[0630] The orthographic projection area of ​​the first via hole H1 on the substrate is greater than or equal to 6 μm×7 μm and less than or equal to 8 μm×10 μm. For example, the orthographic projection area of ​​the first via hole H1 on the substrate may be 7 μm×8.5 μm.

[0631] As shown in Figures 52 to 58, the TX via H0 is a half-overlapping hole, half of which overlaps the fifth metal layer and the other half overlaps the second metal layer. The conductive pattern on the fourth metal layer is connected to the first metal layer through the via on the left and to the second metal layer through the via on the right. The touch signal line formed on the second metal layer is indirectly electrically connected to the common electrode formed on the fifth metal layer through the conductive pattern on the fourth metal layer.

[0632] Figure 53 is a layout diagram of the third metal layer in Figure 52, Figure 54 is a layout diagram of the semiconductor layer in Figure 52, Figure 55 is a layout diagram of the first metal layer in Figure 52, Figure 56 is a layout diagram of the second metal layer in Figure 52, Figure 57 is a layout diagram of the fifth metal layer in Figure 52, and Figure 58 is a layout diagram of the fourth metal layer in Figure 52.

[0633] In Figure 53, the one labeled ZX is a shading pattern; in Figure 54, the one labeled A0 is an active pattern; in Figure 55, the one labeled GL is a gate line; in Figure 56, the one labeled DL is a data line, and the one labeled TX is a touch signal line; in Figure 57, the one labeled VCOM is a common electrode; in Figure 58, the one labeled PX is a pixel electrode.

[0634] FIG59 is a stacking diagram of the third metal layer shown in FIG53 and the semiconductor layer shown in FIG54.

[0635] As shown in FIG59 , the active pattern A0 extends along a first direction (the first direction may be a vertical direction), and the maximum horizontal distance between an edge of an orthographic projection of the light-shielding pattern ZX on the substrate and an edge of an orthographic projection of the active pattern A0 on the substrate is a first distance JL1.

[0636] JL1 is greater than the first distance threshold.

[0637] FIG. 60 is a DD′ cross-sectional view of the array substrate according to at least one embodiment of the present invention shown in FIG. 52 .

[0638] As shown in FIG60 , the array substrate according to at least one embodiment of the present invention includes a first metal layer 21, a second metal layer 22, a semiconductor layer 20, a first insulating layer 201, a third metal layer 23, a second insulating layer 202, a fourth metal layer 24, a fifth metal layer 25, a fifth insulating layer 205, a sixth insulating layer 206, a seventh insulating layer 207, and an eighth insulating layer 208.

[0639] The third metal layer 23, the semiconductor layer 20, the first metal layer 21, the second metal layer 22, the fifth metal layer 25 and the fourth metal layer 24 are arranged in sequence along a direction away from the substrate J1;

[0640] A second insulating layer 202 is provided between the third metal layer 23 and the semiconductor layer 20;

[0641] A first insulating layer 201 is provided between the semiconductor layer 20 and the first metal layer 21;

[0642] A fifth insulating layer 205 is provided between the first metal layer 21 and the second metal layer 22;

[0643] A sixth insulating layer 206 and a seventh insulating layer 207 are stacked between the second metal layer 22 and the fifth metal layer 25 ; the sixth insulating layer 206 is disposed between the seventh insulating layer 207 and the second metal layer 22 ;

[0644] An eighth insulating layer 208 is provided between the fourth metal layer 24 and the fifth metal layer 25;

[0645] Among them, the first metal layer 21 can be a second gate metal layer, the second metal layer 22 can be a source-drain metal layer, the first insulating layer 201 can be a second gate insulating layer, the third metal layer 23 can be a light-shielding metal layer, and the light-shielding metal layer can be reused as the first gate metal layer; the fourth metal layer 24 can be a pixel electrode layer, and the fifth metal layer 25 can be a common electrode layer;

[0646] The first insulating layer 201 may be a second gate insulating layer, the second insulating layer 202 may be a first gate insulating layer, the fifth insulating layer 205 may be an interlayer dielectric layer, the sixth insulating layer 206 may be a first passivation layer, the seventh insulating layer 207 may be an organic film layer, and the eighth insulating layer 208 may be a second passivation layer;

[0647] As shown in FIG61 , the switch transistor includes an active pattern A0, a first gate G1, a first electrode S1, and a second electrode D1;

[0648] The first gate G1 is formed in the first metal layer 21 , the first electrode S1 and the second electrode D1 are formed in the second metal layer 22 , and the active pattern A0 is formed in the semiconductor layer 20 ;

[0649] The third metal layer includes a light-shielding pattern ZX, and the orthographic projection of the light-shielding pattern ZX on the substrate covers the orthographic projection of the active pattern A0 on the substrate;

[0650] The light shielding pattern ZX can be reused as the second gate of the switching transistor;

[0651] The pixel circuit further includes a pixel electrode PX; the pixel electrode PX is formed on the fourth metal layer 24;

[0652] The pixel electrode PX is electrically connected to the second electrode D1 through a first via hole H1; the first via hole H1 penetrates the first passivation layer and the organic film layer; that is, the first via hole H1 includes a first sub-via hole penetrating the organic film layer and a second sub-via hole penetrating the first passivation layer;

[0653] The display unit further includes a common electrode VCOM, and the common electrode VCOM is formed on the fifth metal layer 25;

[0654] As shown in FIG. 62 , based on at least one embodiment of the array substrate shown in FIG. 61 , the active pattern A0 may include a semiconductor portion B0 .

[0655] As shown in FIG. 63 , based on at least one embodiment of the array substrate shown in FIG. 62 , the semiconductor portion includes a first semiconductor portion B1 and a second semiconductor portion B2 .

[0656] As shown in FIG64 , based on at least one embodiment of the array substrate shown in FIG61 , the shortest distance between the orthographic projection of the common electrode VCOM on the substrate and the edge of the orthographic projection of the first via hole H1 on the substrate is a second distance JL2 ;

[0657] The second distance JL2 is greater than the second distance threshold.

[0658] As shown in Figure 65, based on at least one embodiment of the array substrate shown in Figure 61, the shortest distance between the orthographic projection of the pixel electrode PX on the substrate and the edge of the orthographic projection of the first via H1 on the substrate is a third distance JL3, and the third distance J3 is greater than the third distance threshold.

[0659] As shown in Figure 66, based on at least one embodiment of the array substrate shown in Figure 61, the shortest distance between the edge of the orthographic projection of the first pole S1 on the substrate and the edge of the orthographic projection of the second via H2 on the substrate is a fourth distance JL4, and the shortest distance between the edge of the orthographic projection of the second pole D1 on the substrate and the edge of the orthographic projection of the second via H2 on the substrate is a fifth distance JL5; the fourth distance JL4 is greater than the fourth distance threshold, and the fifth distance JL5 is greater than the fifth distance threshold.

[0660] FIG67 is a cross-sectional view taken along line EE′ in FIG52.

[0661] In FIG67 , only the second metal layer 22 , the seventh insulating layer 207 , the eighth insulating layer 208 , the fourth metal layer 24 , and the fifth metal layer 25 are drawn;

[0662] The fourth metal layer 24 is electrically connected to the second metal layer 22 and the fifth metal layer 25 through vias, so that the touch signal line formed in the second metal layer 22 is electrically connected to the common electrode formed in the fifth metal layer 25;

[0663] In FIG. 67 , the via hole labeled H6 is the sixth via hole.

[0664] In at least one embodiment of the present invention, the data voltage supply line is electrically connected to the driver integrated circuit via a first connection line provided in the fan-out region; the touch signal line is electrically connected to the driver integrated circuit via a second connection line provided in the fan-out region; the array substrate further comprises a third metal layer; the third metal layer is provided on a side of the semiconductor layer close to the substrate; the second connection line is formed in the second metal layer;

[0665] A portion of the first connecting line is formed in the first metal layer, and another portion of the first connecting line is formed in the third metal layer.

[0666] In a specific implementation, part of the first connecting line can be formed in the first metal layer, and another part of the first connecting line can be formed in the third metal layer. The orthographic projection of the first connecting line formed in the first metal layer on the substrate at least partially overlaps with the orthographic projection of the first connecting line formed in the third metal layer on the substrate to save space.

[0667] In a specific implementation, when the array substrate includes a sixth metal layer, four layers of metal wiring can be used in the fan-out area. The four layers of metal can be: a third metal layer, a first metal layer, a second metal layer and a sixth metal layer. Through four layers of metal stacking wiring, the lower frame can be further reduced.

[0668] Figure 68 is a cross-sectional view of the four metal layers of the fan-out area.

[0669] In FIG68 , the number 23 is the third metal layer, the number 21 is the first metal layer, the number 22 is the second metal layer, and the number 26 is the sixth metal layer;

[0670] The number 201 is the first insulating layer, the number 205 is the fifth insulating layer, the number 207 is the seventh insulating layer, the number 203 is the third insulating layer, and the number 208 is the eighth insulating layer.

[0671] FIG. 69 is a circuit diagram of at least one embodiment of a driver circuit.

[0672] The difference between at least one embodiment of the driving circuit shown in FIG69 and at least one embodiment of the driving circuit shown in FIG31 is as follows: the input control terminal ICt and the input terminal I1 are not connected;

[0673] ICt is electrically connected to the carry signal output terminal of the adjacent previous n-stage driving circuit, and I1 is electrically connected to the drive signal output terminal of the adjacent previous n-stage driving circuit.

[0674] Figure 70 is a layout diagram of at least one embodiment of the driving circuit shown in Figure 69, Figure 71 is a layout diagram of the third metal layer in Figure 70, Figure 72 is a layout diagram of the semiconductor layer in Figure 70, Figure 73 is a layout diagram of the first metal layer in Figure 70, Figure 74 is a layout diagram of the second metal layer in Figure 70, and Figure 75 is a layout diagram of the fourth metal layer in Figure 70.

[0675] In FIG. 75 , each pattern is a conductive pattern.

[0676] In FIG72 , A1 is the active pattern of M1, A2 is the active pattern of M2, A21 is the active pattern of M21, and A22 is the active pattern of M22.

[0677] The array substrate according to at least one embodiment of the present invention further includes a data line formed in the second metal layer;

[0678] The array substrate includes 3a data lines and 2a touch signal lines; a is a positive integer;

[0679] The two touch signal lines correspond to the three data lines, and an orthographic projection of the touch signal line on the substrate at least partially overlaps with an orthographic projection of one of the three data lines on the substrate.

[0680] In a specific implementation, two touch signal lines may be provided corresponding to three data lines, and the orthographic projections of the touch signal lines on the substrate at least partially overlap with the orthographic projections of the data lines on the substrate, which is beneficial to reducing the capacitance of the touch signal lines.

[0681] As shown in FIG76 , TX1 is the first touch signal line, TX2 is the second touch signal line, TX3 is the third touch signal line, TX4 is the fourth touch signal line, TX5 is the fifth touch signal line, TX6 is the sixth touch signal line, TX7 is the seventh touch signal line, TX8 is the eighth touch signal line, TX9 is the ninth touch signal line, TX10 is the tenth touch signal line, TX11 is the eleventh touch signal line, TX12 is the twelfth touch signal line, TX13 is the thirteenth touch signal line, and TX14 is the fourteenth touch signal line.

[0682] DL1 is the first data line, DL4 is the fourth data line, DL7 is the seventh data line, DL10 is the tenth data line, DL13 is the thirteenth data line, DL16 is the sixteenth data line, DL19 is the nineteenth data line, and DL22 is the twenty-second data line;

[0683] A second data line is arranged below the first touch signal line TX1, a third data line is arranged below the second touch signal line TX2, a fifth data line is arranged below the third touch signal line TX3, a sixth data line is arranged below the fourth touch signal line TX4, an eighth data line is arranged below the fifth touch signal line TX5, a ninth data line is arranged below the sixth touch signal line TX6, an eleventh data line is arranged below the seventh touch signal line TX7, a twelfth data line is arranged below the eighth touch signal line TX8, a fourteenth data line is arranged below the ninth touch signal line TX9, a fifteenth data line is arranged below the tenth touch signal line TX10, a seventeenth data line is arranged below the eleventh touch signal line TX11, an eighteenth data line is arranged below the twelfth touch signal line TX12, a twentieth data line is arranged below the thirteenth touch signal line TX13, and a twenty-first data line is arranged below the fourteenth touch signal line TX14.

[0684] The array substrate according to at least one embodiment of the present invention further includes a data line formed in the second metal layer;

[0685] The array substrate includes 3a data lines and a touch signal line; a is a positive integer;

[0686] One touch signal line corresponds to three data lines, and an orthographic projection of the touch signal line on the substrate at least partially overlaps with an orthographic projection of one of the three data lines on the substrate.

[0687] In a specific implementation, one or two touch signal lines may be provided corresponding to three data lines, and the orthographic projections of the touch signal lines on the substrate at least partially overlap with the orthographic projections of the data lines on the substrate, which is beneficial to reducing the capacitance of the touch signal lines.

[0688] As shown in FIG77 , the first touch signal line is labeled TX1, the second touch signal line is labeled TX2, the third touch signal line is labeled TX3, the fourth touch signal line is labeled TX4, the fifth touch signal line is labeled TX5, the sixth touch signal line is labeled TX6, and the seventh touch signal line is labeled TX7;

[0689] DL2 is the second data line, DL3 is the third data line, DL4 is the fourth data line, DL6 is the sixth data line, DL8 is the eighth data line, DL9 is the ninth data line, DL10 is the tenth data line, DL12 is the twelfth data line, DL14 is the fourteenth data line, DL15 is the fifteenth data line, DL16 is the sixteenth data line, and DL18 is the eighteenth data line;

[0690] A first data line is provided under TX1, a fifth data line is provided under TX2, a seventh data line is provided under TX3, an eleventh data line is provided under TX4, a thirteenth data line is provided under TX5, a seventeenth data line is provided under TX6, and a nineteenth data line is provided under TX7.

[0691] The display device according to the embodiment of the present invention includes the above-mentioned array substrate.

[0692] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. An array substrate, comprising a plurality of first routing lines and a plurality of second routing lines arranged on a substrate, wherein the first routing lines and the second routing lines intersect with each other to define a plurality of pixel areas, each of the pixel areas comprising a transistor, a first electrode, a second electrode, a first via hole and a second via hole; an orthographic projection of the first via hole on the substrate at least partially overlaps with an orthographic projection of the first electrode on the substrate, and an orthographic projection of the second via hole on the substrate at least partially overlaps with an orthographic projection of the first electrode on the substrate; The orthographic projection of the first via hole on the substrate does not overlap with the orthographic projection of the second electrode on the substrate, and the orthographic projection of the second via hole on the substrate does not overlap with the orthographic projection of the second electrode on the substrate.

2. The array substrate according to claim 1, wherein: The first via hole and the second via hole are located in the same pixel area; Another pixel region adjacent to the pixel region includes a third via hole; An orthographic projection of the second via hole on the substrate and an orthographic projection of the third via hole on the substrate are located on opposite sides of an orthographic projection of the first trace on the substrate.

3. The array substrate according to claim 1, wherein: The transistor includes an active pattern; The orthographic projection of the second via on the substrate at least partially overlaps with the orthographic projection of the first conductor portion included in the active pattern on the substrate; The second via is used to electrically connect the first electrode of the transistor and the first conductor portion of the active pattern; A portion of the first electrode falls into the first via hole, and the first via hole is used to electrically connect the first electrode and a first conductor portion included in the active pattern.

4. The array substrate according to claim 2, wherein: The orthographic projection of the third via hole on the substrate at least partially overlaps with the orthographic projection of the second conductor portion included in the active pattern on the substrate; The third via hole is used to electrically connect the second electrode of the transistor and the second conductor portion of the active pattern.

5. The array substrate according to claim 1, wherein: Along the first direction, the minimum distance between the orthographic projection of the first via hole on the substrate and the orthographic projection of the first trace on the substrate is smaller than the minimum distance between the orthographic projection of the second via hole on the substrate and the orthographic projection of the first trace on the substrate.

6. The array substrate according to claim 1, wherein: The active pattern is in a dumbbell shape; the angle between the orthographic projection of the active pattern on the substrate and the orthographic projection of the first trace on the substrate is greater than or equal to 85 degrees and less than or equal to 95 degrees.

7. The array substrate according to claim 1, wherein: The second routing line includes a second routing line body, a first auxiliary portion, and a second auxiliary portion; The first auxiliary portion is electrically connected to the second wiring body, and the second auxiliary portion is in a floating state; The first auxiliary portion is electrically connected to a second conductor portion included in the active pattern, and the second auxiliary portion is electrically connected to the first electrode.

8. The array substrate according to claim 1, wherein: The array substrate comprises 3a second wirings and 2a third wirings; a is a positive integer; The two third routing lines correspond to the three second routing lines, and the orthographic projection of the third routing lines on the substrate at least partially overlaps with the orthographic projection of one of the three second routing lines on the substrate.

9. The array substrate according to claim 1, wherein: The array substrate comprises 3a second wirings and a third wiring; a is a positive integer; One of the third routing lines corresponds to three of the second routing lines, and an orthographic projection of the third routing line on the substrate at least partially overlaps with an orthographic projection of one of the three second routing lines on the substrate.

10. The array substrate according to claim 1, wherein: The array substrate further includes a third wiring; The third wiring includes a signal line main body portion and a connecting portion electrically connected to each other; An orthographic projection of the connecting portion on the substrate at least partially overlaps with an orthographic projection of the second via hole on the substrate.

11. The array substrate according to claim 10, wherein: The array substrate further includes a light shielding pattern; the light shielding pattern and the third wiring are arranged in different layers; The orthographic projection of the connecting portion on the substrate at least partially overlaps with the orthographic projection of the light-shielding pattern on the substrate.

12. The array substrate according to claim 1, wherein: The array substrate further includes a light shielding pattern; The orthographic projection of the light-shielding pattern on the substrate covers the orthographic projection of the conductor portion of the active pattern of the transistor on the substrate.

13. The array substrate according to any one of claims 1 to 12, wherein: The array substrate comprises a first metal layer, a second metal layer, a semiconductor layer and a first insulating layer; The transistor includes an active pattern, a first gate, a first electrode and a second electrode; The first gate is formed on the first metal layer, the first electrode and the second electrode are formed on the second metal layer, and the active pattern is located on the semiconductor layer; The first insulating layer is disposed between the first metal layer and the semiconductor layer; The thickness of the first insulating layer is less than a first thickness threshold; The first thickness threshold is greater than or equal to 800 angstroms and less than or equal to 2000 angstroms; The first metal layer is disposed on a side of the semiconductor layer away from the substrate.

14. The array substrate according to claim 13, wherein: The thickness of the first insulating layer is greater than or equal to 500 angstroms and less than or equal to 2000 angstroms.

15. The array substrate according to claim 13, wherein: The active pattern includes a semiconductor portion; the semiconductor portion includes a first semiconductor portion and a second semiconductor portion which are stacked; The first semiconductor portion is disposed between the second semiconductor portion and the substrate, and the first semiconductor portion and the second semiconductor portion are made of semiconductor materials with different carrier mobilities.

16. The array substrate according to claim 13, wherein: The array substrate further includes a third metal layer and a second insulating layer; The third metal layer is disposed between the semiconductor layer and the substrate, and the second insulating layer is disposed between the semiconductor layer and the third metal layer; The third metal layer includes a light-shielding pattern, and an orthographic projection of the light-shielding pattern on the substrate covers an orthographic projection of a semiconductor portion in the active pattern on the substrate.

17. The array substrate according to claim 16, wherein: The active pattern extends along a first direction; The farthest distance between the edge of the orthographic projection of the light-shielding pattern on the substrate and the edge of the orthographic projection of the active pattern on the substrate along the second direction is greater than a first distance threshold; The first distance threshold is greater than or equal to 4 μm; and the first direction intersects with the second direction.

18. The array substrate according to claim 16, wherein: The light shielding pattern is multiplexed as the second gate of the switch transistor.

19. The array substrate according to claim 13, wherein: The array substrate further includes a fourth metal layer; the first electrode is formed on the fourth metal layer; the fourth metal layer is arranged on a side of the second metal layer away from the substrate; The first electrode is electrically connected to the second electrode of the transistor through a first via hole; An area of ​​an orthographic projection of the first via hole on the substrate is greater than or equal to 6 μm×7 μm and less than or equal to 8 μm×10 μm.

20. The array substrate according to claim 19, wherein: The array substrate further includes a fifth metal layer; the second electrode is formed on the fifth metal layer; the fifth metal layer is disposed between the fourth metal layer and the second metal layer; The shortest distance between the orthographic projection of the second electrode on the substrate and the edge of the orthographic projection of the first via hole on the substrate is greater than a second distance threshold; The second distance threshold is greater than 2 μm.

21. The array substrate according to claim 19, wherein: The shortest distance between the orthographic projection of the first electrode on the substrate and the edge of the orthographic projection of the first via hole on the substrate is greater than a third distance threshold; The third distance threshold is greater than or equal to 1.6 μm.

22. The array substrate according to claim 13, wherein: The array substrate further comprises a fifth metal layer and a sixth metal layer, wherein the fifth metal layer is arranged on a side of the second metal layer away from the substrate, and the sixth metal layer is arranged on a side of the fifth metal layer away from the substrate; The array substrate comprises a third wiring; The third wiring is formed on the sixth metal layer, and the second electrode is formed on the fifth metal layer; The array substrate further includes a fourth metal layer, a third insulating layer disposed between the sixth metal layer and the fifth metal layer, and a fourth insulating layer disposed between the sixth metal layer and the fourth metal layer; the fourth metal layer is disposed on a side of the sixth metal layer away from the substrate; The array substrate comprises a first conductive pattern formed on the fourth metal layer; The first conductive pattern is electrically connected to the third trace through a fourth via hole, and the first conductive pattern is electrically connected to the third trace through the fourth via hole. The fourth via hole and the fifth via hole are electrically connected to the second electrode, so that the third trace is electrically connected to the second electrode; The fourth via hole is a via hole penetrating the fourth insulating layer, and the fifth via hole is a via hole penetrating the third insulating layer; An area of ​​an orthographic projection of the fourth via hole on the substrate is greater than or equal to 3 μm×6 μm and less than or equal to 5 μm×8 μm.

23. The array substrate according to claim 13, wherein: The array substrate comprises a sixth metal layer; the array substrate comprises a third wiring, and the third wiring is formed in the sixth metal layer; The third wiring includes a signal line main body portion and a connecting portion that are interconnected; The orthographic projection of the connecting portion on the substrate covers the orthographic projection of the spacer portion on the substrate, and the connecting portion is used to support the spacer portion; The array substrate is included in a display device, and the display device includes a color filter substrate. The spacer portion is arranged between the color filter substrate and the array substrate.

24. The array substrate according to claim 13, wherein: It also includes a driving module disposed on the substrate; the driving module is disposed in the peripheral area; The driving module includes a multi-stage driving circuit; the driving circuit is used to provide a driving signal for the pixel circuit; The driving circuit includes an input circuit, a reset circuit and a first node control circuit; The input circuit is electrically connected to the input control terminal, the input terminal and the first node respectively, and is used to write the input signal provided by the input terminal into the first node under the control of the input control signal provided by the input control terminal; The reset circuit is electrically connected to the reset line, the first node and the first voltage line respectively, and is used to control the connection between the first node and the first voltage line under the control of the reset signal provided by the reset line; The first node control circuit is electrically connected to the first second node, the second second node, the second voltage line and the first node, respectively, and is used to control the connection between the first node and the second voltage line under the control of the potential of the first second node, and to control the connection between the first node and the second voltage line under the control of the potential of the second second node.

25. The array substrate according to claim 24, wherein: The driving circuit also includes a frame reset circuit; The frame reset circuit is electrically connected to the frame reset line, the first node and the second voltage line respectively, and is used to control the connection between the first node and the second voltage line under the control of the frame reset signal provided by the frame reset line.

26. The array substrate according to claim 24, wherein: The input circuit includes a first transistor and a second transistor; The gate of the first transistor and the gate of the second transistor are electrically connected to the input control terminal, the first electrode of the first transistor is electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the control node; A first electrode of the second transistor is electrically connected to the control node, and a second electrode of the second transistor is electrically connected to the first node.

27. The array substrate according to claim 26, wherein: The driving circuit also includes a control circuit; The control circuit is electrically connected to the control node, the first node and the third voltage line respectively, and is used for Under the control of the potential of the first node, the control node is controlled to be connected to the third voltage line.

28. The array substrate according to claim 24, wherein: The input terminal and the input control terminal are the same signal terminal, and the input terminal is the carry signal output terminal of the adjacent previous n stages; or, The input terminal is the carry signal output terminal of the adjacent previous n stages, and the input control terminal is the drive signal output terminal of the adjacent previous n stages; n is a positive integer.

29. The array substrate according to claim 24, wherein: The reset circuit includes a third transistor and a fourth transistor, and the first node control circuit includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; The gate of the third transistor and the gate of the fourth transistor are both electrically connected to the reset line, the first electrode of the third transistor is electrically connected to the first node, the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor; the second electrode of the third transistor is electrically connected to the control node; The second electrode of the fourth transistor is electrically connected to the first voltage line; The gate of the fifth transistor and the gate of the sixth transistor are both electrically connected to the first second node, the first electrode of the fifth transistor is electrically connected to the first node, the second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor; the second electrode of the fifth transistor is electrically connected to the control node; The second electrode of the sixth transistor is electrically connected to the second voltage line; The gate of the seventh transistor and the gate of the eighth transistor are both electrically connected to the second second node, the first electrode of the seventh transistor is electrically connected to the first node, the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor; the second electrode of the seventh transistor is electrically connected to the control node; A second electrode of the eighth transistor is electrically connected to the second voltage line.

30. The array substrate according to claim 25, wherein: The frame reset circuit includes a ninth transistor and a tenth transistor; The gate of the ninth transistor is electrically connected to the frame reset line, the first electrode of the ninth transistor is electrically connected to the first node, the second electrode of the ninth transistor is electrically connected to the first electrode of the tenth transistor; the second electrode of the ninth transistor is electrically connected to the control node; A second electrode of the tenth transistor is electrically connected to the second voltage line.

31. The array substrate according to claim 24, wherein: The driving circuit further includes a storage capacitor and a driving signal output terminal; a first plate of the storage capacitor is electrically connected to the first node, and a second plate of the storage capacitor is electrically connected to the driving signal output terminal.

32. The array substrate according to claim 31, wherein: The array substrate further includes a third metal layer and a second insulating layer; the third metal layer is disposed on a side of the semiconductor layer close to the substrate, and the second insulating layer is disposed between the semiconductor layer and the third metal layer; The first electrode plate is formed on the first metal layer, and the second electrode plate includes a first electrode plate portion and a second electrode plate portion electrically connected to each other; The first electrode plate is partially formed on the second metal layer, and the second electrode plate is partially formed on the third metal layer; An orthographic projection of the first plate on the substrate, an orthographic projection of the first plate portion on the substrate, and an orthographic projection of the second plate portion on the substrate at least partially overlap.

33. The array substrate according to claim 31, wherein: The first electrode plate includes a first first electrode plate portion, a second first electrode plate portion and a third first electrode plate portion; The first electrode portion includes a first second electrode portion, a second second electrode portion and a third second electrode portion electrically connected to each other; The second electrode plate portion includes a first third electrode plate portion, a second third electrode plate portion and a third third electrode plate portion; The first first electrode portion, the second first electrode portion and the third first electrode portion are all formed on the first metal layer, the first second electrode portion, the second second electrode portion and the third second electrode portion are all formed on the second metal layer, and the first third electrode portion, the second third electrode portion and the third third electrode portion are all formed on the third metal layer; The orthographic projection of the first first electrode plate portion on the substrate, the orthographic projection of the first second electrode plate portion on the substrate and the orthographic projection of the first third electrode plate portion on the substrate at least partially overlap; The orthographic projection of the second first electrode portion on the substrate, the orthographic projection of the second second electrode portion on the substrate and the orthographic projection of the second third electrode portion on the substrate at least partially overlap; The orthographic projection of the third first electrode plate portion on the substrate, the orthographic projection of the third second electrode plate portion on the substrate, and the orthographic projection of the third third electrode plate portion on the substrate at least partially overlap.

34. The array substrate according to claim 33, wherein: The driving circuit includes a driving output circuit and a carry output circuit; The drive output circuit is used to control the output drive signal under the control of the potential of the first node; The carry output circuit is used to control the output of a carry signal under the control of the potential of the first node; The orthographic projection of the active pattern of the transistor included in the driving output circuit on the substrate and the orthographic projection of the first first electrode portion on the substrate are arranged along a first direction; The active pattern of the transistor included in the carry output circuit is arranged on a side of the active pattern of the transistor included in the drive output circuit close to the display area; The orthographic projection of the second first electrode portion on the substrate is arranged on a side of the orthographic projection of the active pattern of the transistor included in the carry output circuit on the substrate close to the display area; The orthographic projection of the third first electrode portion on the substrate is aligned with the active pattern of the transistor included in the first node control circuit along the first direction.

35. The array substrate according to claim 13, wherein: The peripheral area includes a fan-out area and a gate transistor setting area arranged between the fan-out area and the display area; The array substrate includes M gate control lines and a gate portion disposed in the gate transistor arrangement region; the gate portion includes a plurality of gate parts; M is an integer greater than 1; The gating part includes a plurality of gating transistors; the gates of the plurality of gating transistors are electrically connected to the corresponding gating control lines, the first electrodes of the plurality of gating transistors are electrically connected to the corresponding data voltage supply lines, and the Second electrodes of the plurality of selection transistors are electrically connected to corresponding data lines respectively.

36. The array substrate according to claim 35, wherein: The peripheral area also includes an integrated circuit arrangement area arranged in the fan-out area away from the display area; The array substrate comprises a driving integrated circuit arranged in the integrated circuit arrangement area and a plurality of gate control signal supply lines; The mth gate control signal supply line is electrically connected to the driving integrated circuit and the mth gate control line respectively, and is used to receive the mth gate control signal from the driving integrated circuit and provide the mth gate control signal to the mth gate control line; m is a positive integer less than or equal to M.

37. The array substrate according to claim 35, wherein: The peripheral area also includes an integrated circuit arrangement area arranged in the fan-out area away from the display area; the array substrate includes a driving integrated circuit arranged in the integrated circuit arrangement area; The array substrate includes a touch signal line arranged in the display area; The data voltage supply line is electrically connected to the driving integrated circuit through a first connection line arranged in the fan-out area, and is used to receive the data voltage provided by the driving integrated circuit; The touch signal line is electrically connected to the driving integrated circuit via a second connecting line arranged in the fan-out area, and is used for receiving a touch sensing signal provided by the driving integrated circuit.

38. The array substrate according to claim 37, wherein: A portion of the first connecting line is formed in the first metal layer, and another portion of the first connecting line is formed in the second metal layer.

39. The array substrate according to claim 37, wherein: The array substrate further comprises a third metal layer; the third metal layer is arranged on a side of the semiconductor layer close to the substrate; A portion of the first connecting wires is formed in the first metal layer, another portion of the first connecting wires is formed in the second metal layer, and another portion of the first connecting wires is formed in the third metal layer.

40. The array substrate according to claim 36, wherein: In the selection transistor setting area; the array substrate further includes a third metal layer; the third metal layer is arranged on a side of the semiconductor layer close to the substrate; In the selection transistor setting area, the conductive pattern on the third metal layer is in a floating state.

41. The array substrate according to claim 13, 35, 36 or 37, wherein: The array substrate further includes a touch signal line; The touch signal line is formed on the second metal layer; The array substrate further includes a fourth metal layer, a fifth metal layer and a sixth metal layer; The sixth metal layer is disposed on a side of the second metal layer away from the substrate, and the fifth metal layer is disposed between the second metal layer and the sixth metal layer; The touch signal line is electrically connected to the second conductive pattern formed on the fourth metal layer through the sixth via hole; the second conductive pattern is electrically connected to the common electrode formed on the fifth metal layer.

42. The array substrate according to claim 41, wherein: The data voltage supply line is electrically connected to the driver integrated circuit through a first connection line arranged in the fan-out area; the touch signal line is electrically connected to the driver integrated circuit through a second connection line arranged in the fan-out area; the array substrate further comprises a third metal layer; the third metal layer is arranged on a side of the semiconductor layer close to the substrate; the second connection line is formed in the second metal layer; A portion of the first connecting line is formed in the first metal layer, and another portion of the first connecting line is formed in the third metal layer.

43. A display device comprising the array substrate according to any one of claims 1 to 42.

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