Display substrate and display device

Abstract

A display substrate comprises a substrate (40), a plurality of first pixel circuits (21), a plurality of first light-emitting elements and a plurality of second light-emitting elements (12) which are located in a first display area (A1), and a plurality of reserved pixel circuits, a plurality of in-situ pixel circuits (23) and a plurality of third light-emitting elements which are located in a second display area (A2). The plurality of reserved pixel circuits includes a plurality of second pixel circuits (22). In the second display area (A2), one row of reserved pixel circuits is arranged every m rows of in-situ pixel circuits, and m is an integer larger than 1. The at least one second pixel circuit (22) is connected to the at least one second light-emitting element (12) by means of at least one first electrically conductive connection line (31) extending in the second direction (Y). The maximum length of the first display area (A1) in the first direction (X) is different from the maximum length in the second direction (Y).

Description

Display substrate and display device

[0001] This application claims priority to the international application filed on October 25, 2023, with application number PCT / CN2023 / 126428 and invention name “Display Substrate and Display Device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] Embodiments of the present disclosure provide a display substrate and a display device.

[0007] On the one hand, this embodiment provides a display substrate, comprising: at least one first display area and a second display area located at least to one side of the first display area; the maximum length of the first display area along a first direction is different from the maximum length along a second direction, and the first direction intersects the second direction. The display substrate comprises: a substrate, a plurality of pixel circuits disposed on the substrate, and a plurality of light-emitting elements. The plurality of pixel circuits comprise: a plurality of first pixel circuits located in the first display area, and a plurality of reserved pixel circuits and a plurality of in-situ pixel circuits located in the second display area; the plurality of reserved pixel circuits comprise a plurality of second pixel circuits. In the second display area, the plurality of reserved pixel circuits arranged along the first direction form a row of reserved pixel circuits, the plurality of in-situ pixel circuits arranged along the first direction form a row of in-situ pixel circuits, and along the second direction, a row of reserved pixel circuits is arranged for every m rows of in-situ pixel circuits, where m is an integer greater than 1. The plurality of light-emitting elements comprise: a plurality of first light-emitting elements and a plurality of second light-emitting elements located in the first display area, and a plurality of third light-emitting elements located in the second display area. At least one first pixel circuit among the plurality of first pixel circuits is connected to at least one first light-emitting element among the plurality of first light-emitting elements, and the orthographic projection of the at least one first pixel circuit on the substrate at least partially overlaps with the orthographic projection of the at least one first light-emitting element to which it is connected. At least one second pixel circuit among the plurality of second pixel circuits is connected to at least one second light-emitting element among the plurality of second light-emitting elements via at least one first conductive connection line extending along the second direction, and the orthographic projection of the at least one second pixel circuit on the substrate does not overlap with the orthographic projection of the at least one second light-emitting element to which it is connected. At least one in-situ pixel circuit among the plurality of in-situ pixel circuits is connected to at least one third light-emitting element among the plurality of third light-emitting elements, and the orthographic projection of the at least one in-situ pixel circuit on the substrate at least partially overlaps with the orthographic projection of the at least one third light-emitting element to which it is connected.

[0008] In some exemplary embodiments, the maximum length of the first display area along the first direction is greater than the maximum length along the second direction. The first display area includes: a+1 first sub-areas and a second sub-areas; the a+1 first sub-areas and the a second sub-areas are spaced apart along the first direction, where a is an integer greater than 0; at least one first sub-area is disposed between the second sub-area and the second display area in the first direction. The first sub-area is provided with the plurality of first pixel circuits and the plurality of first light-emitting elements, and the second sub-area is provided with the plurality of second light-emitting elements.

[0009] In some exemplary embodiments, the display substrate further includes: a plurality of data lines connected to the plurality of pixel circuits and configured to provide data signals to the plurality of pixel circuits, the plurality of data lines being arranged along the first direction and extending along the second direction; the plurality of data lines including: a plurality of first data lines, a plurality of second data lines, and a plurality of third data lines, the plurality of first data lines being separated by the first display area and bypassing the second sub-area from both sides of the second sub-area along the first direction, the plurality of second data lines being connected to the plurality of first pixel circuits of the first sub-area, and the plurality of third data lines being located in the second display area.

[0010] In some exemplary embodiments, a is 1 or 3.

[0011] In some exemplary embodiments, the maximum length of the first display area along the second direction is greater than the maximum length along the first direction. The first display area includes: b first sub-areas and b+1 second sub-areas; the b first sub-areas and the b+1 second sub-areas are arranged at intervals along the second direction, where b is an integer greater than 0; at least one second sub-area is provided between the first sub-area and the second display area in the second direction; the first sub-area is provided with the plurality of first pixel circuits and the plurality of first light-emitting elements, and the second sub-area is provided with the plurality of second light-emitting elements.

[0012] In some exemplary embodiments, within the second display area, a plurality of reserved pixel circuits arranged sequentially along the second direction constitute a column of reserved pixel circuits, a plurality of in-situ pixel circuits arranged sequentially along the second direction constitute a column of in-situ pixel circuits, and along the first direction, a column of reserved pixel circuits is arranged every n columns of in-situ pixel circuits, where n is an integer greater than 1. A plurality of second light-emitting elements disposed in a second sub-area between the second display area and the first sub-area in the second direction are connected to the plurality of second pixel circuits in the second display area via a plurality of first conductive connecting lines; a plurality of second light-emitting elements disposed in a second sub-area between two adjacent first sub-areas in the second direction are connected to the plurality of second pixel circuits in the second display area via a plurality of second conductive connecting lines, wherein the plurality of second conductive connecting lines extend along the first direction.

[0013] In some exemplary embodiments, the first display area includes: a plurality of island areas, a transmissive area located between adjacent island areas, and an inter-island connection area connecting adjacent island areas; the transmissive area has a greater light transmittance than the island areas; the island areas are provided with the plurality of first pixel circuits and the plurality of first light-emitting elements; and the first display area satisfies at least one of the following conditions: the transmissive area is provided with the plurality of second light-emitting elements; and the inter-island connection area is provided with the plurality of second light-emitting elements.

[0014] In some exemplary embodiments, the first display area includes a plurality of transmission areas, the plurality of transmission areas including: at least one first transmission area and a plurality of second transmission areas, the first transmission area being provided with the plurality of second light-emitting elements; the second transmission areas having a light transmittance greater than that of the first transmission area; and the second transmission areas being spaced apart from the first transmission areas along the first direction or the second direction. The first display area satisfies at least one of the following conditions: the maximum length of the first transmission area along the first direction is greater than the maximum length of the second transmission area along the first direction; the maximum length of the first transmission area along the first direction is equal to the maximum length of the second transmission area along the first direction; the maximum length of the first transmission area along the second direction is greater than the maximum length of the second transmission area along the second direction; and the maximum length of the first transmission area along the second direction is equal to the maximum length of the second transmission area along the second direction.

[0015] In some exemplary embodiments, the display substrate further includes: a blocking layer located in the first display area, the blocking layer being located on a side of the multiple first pixel circuits close to the substrate; the blocking layer's orthographic projection on the substrate covers the multiple island areas, the multiple inter-island connection areas, and the orthographic projection of the multiple second light-emitting elements in the first transmission area on the substrate.

[0016] In some exemplary embodiments, the at least one first conductive connection line is disposed in the same layer as the shielding layer.

[0017] In some exemplary embodiments, the first transmission area is located in a central region of the first display area, and a maximum length of the first transmission area along the first direction is greater than a maximum length of the first transmission area along the second direction.

[0018] In some exemplary embodiments, the first display area includes a plurality of inter-island connecting areas, the plurality of inter-island connecting areas including a plurality of first inter-island connecting areas, a plurality of second inter-island connecting areas, and a plurality of third inter-island connecting areas; the plurality of first inter-island connecting areas and the plurality of third inter-island connecting areas extend along the first direction, and the plurality of second inter-island connecting areas extend along the second direction; the first inter-island connecting areas are adjacent to the second transmissive areas along the second direction, and the third inter-island connecting areas are adjacent to the first transmissive areas along the second direction; and the maximum length of the third inter-island connecting areas along the first direction is greater than the maximum length of the first inter-island connecting areas along the first direction.

[0019] In some exemplary embodiments, a maximum length of the third inter-island connecting region along the second direction is greater than or equal to a maximum length of the first inter-island connecting region along the second direction.

[0020] In some exemplary embodiments, a minimum distance between the second light-emitting element located in the transmission region and the substrate is less than or equal to a minimum distance between the first light-emitting element located in the island region and the substrate.

[0021] In some exemplary embodiments, the inter-island connection area is provided with a plurality of traces, and the plurality of traces are straight line segments extending along the first direction or the second direction, or arc segments extending along the first direction or the second direction.

[0022] In some exemplary embodiments, the first display area includes: a display edge area and a display middle area, the display edge area surrounds the display middle area, the display middle area includes: a plurality of island areas, a transmission area located between adjacent island areas, and an inter-island connection area connecting adjacent island areas; the plurality of second light-emitting elements are located in the display edge area.

[0023] In some exemplary embodiments, the display substrate includes: a plurality of first display areas, at least one of the plurality of first display areas is provided with the plurality of first pixel circuits, the plurality of first light-emitting elements and the plurality of second light-emitting elements; the plurality of first display areas are staggered along the first direction or staggered along the second direction.

[0024] In some exemplary embodiments, the display substrate further includes a peripheral region located on at least one side of the second display area, the peripheral region including a first peripheral region located on one side of the second display area along the second direction and a second peripheral region located on the remaining sides of the second display area. The display substrate further includes a gate driver circuit located in the second peripheral region, the gate driver circuit including a plurality of first driver units configured to provide gate signals to multiple rows of in-situ pixel circuits and multiple rows of reserved pixel circuits.

[0025] In some exemplary embodiments, the display substrate further includes a peripheral region located on at least one side of the second display area, the peripheral region including a first peripheral region located on one side of the second display area along the second direction and a second peripheral region located on the remaining sides of the second display area. The display substrate further includes a gate driver circuit located in the second peripheral region, the gate driver circuit including a plurality of first driver units and a plurality of second driver units, the plurality of first driver units configured to provide gate signals to multiple rows of in-situ pixel circuits, and the plurality of second driver units configured to provide gate signals to multiple rows of reserved pixel circuits.

[0026] In some exemplary embodiments, the first display area is in the shape of a racetrack hole.

[0027] In some exemplary embodiments, the plurality of second light-emitting elements in the first display area are connected to the plurality of second pixel circuits in the second display area via a plurality of first conductive connection lines, and the plurality of first conductive connection lines are located in the same conductive layer.

[0028] On the other hand, this embodiment provides a display device, comprising a display substrate as described above, and a sensor located on the non-display surface side of the display substrate, wherein the orthographic projection of the sensor on the substrate of the display substrate at least partially overlaps with the orthographic projection of the first display area of ​​the display substrate on the substrate.

[0029] On the other hand, this embodiment provides a display substrate, comprising: a plurality of first display areas and a second display area located on at least one side of the plurality of first display areas; the plurality of first display areas are arranged staggered along a first direction or a second direction, the first direction intersecting the second direction. The display substrate comprises: a substrate, a plurality of pixel circuits disposed on the substrate, and a plurality of light-emitting elements. The plurality of pixel circuits include a plurality of first pixel circuits located in at least one first display area of ​​the plurality of first display areas, and a plurality of reserved pixel circuits and a plurality of in-situ pixel circuits located in the second display area; the plurality of reserved pixel circuits include a plurality of second pixel circuits; within the second display area, the plurality of reserved pixel circuits arranged along the first direction form a row of reserved pixel circuits, the plurality of in-situ pixel circuits arranged along the first direction form a row of in-situ pixel circuits, and along the second direction, a row of reserved pixel circuits is arranged every m rows of in-situ pixel circuits, where m is an integer greater than 1. The plurality of light-emitting elements include a plurality of first light-emitting elements and a plurality of second light-emitting elements located in the at least one first display area, and a plurality of third light-emitting elements located in the second display area. The at least one first display area includes: a first region and a second region arranged along the first direction, the first region being adjacent to the second display area in the first direction, and the second region being adjacent to another first display area in the first direction. The plurality of second light-emitting elements are located in the first region, and the plurality of first pixel circuits and the plurality of first light-emitting elements are located in the second region. At least one first pixel circuit among the plurality of first pixel circuits is connected to at least one first light-emitting element among the plurality of first light-emitting elements, and the orthographic projection of the at least one first pixel circuit on the substrate at least partially overlaps with the orthographic projection of the at least one first light-emitting element to which it is connected. At least one second pixel circuit among the plurality of second pixel circuits is connected to at least one second light-emitting element among the plurality of second light-emitting elements via at least one first conductive connecting line extending along the second direction, and the orthographic projection of the at least one second pixel circuit on the substrate does not overlap with the orthographic projection of the at least one second light-emitting element to which it is connected. At least one in-situ pixel circuit among the plurality of in-situ pixel circuits is connected to at least one third light-emitting element among the plurality of third light-emitting elements, and the orthographic projection of the in-situ pixel circuit on the substrate at least partially overlaps with the orthographic projection of the at least one third light-emitting element to which it is connected.

[0030] In some exemplary embodiments, the display substrate includes three first display areas, two of which are aligned along the first direction, and a third first display area is located on the same side of the two first display areas along the second direction; each first display area is provided with the plurality of first light-emitting elements, the plurality of second light-emitting elements, and the plurality of first pixel circuits. Within two first display areas located in the same row, the plurality of second light-emitting elements are located in a first region of the first display area along the first direction, and the plurality of first pixel circuits and the plurality of first light-emitting elements are located in a second region of the first display area along the first direction; within the third first display area, the plurality of second light-emitting elements are located between the plurality of first light-emitting elements along the first direction.

[0031] In some exemplary embodiments, the display substrate includes four first display areas arranged in two rows, with the first display areas in the two rows staggered along the first direction. The plurality of first light-emitting elements, the plurality of second light-emitting elements, and the plurality of first pixel circuits are disposed in two first display areas in at least one row; or, one first display area in one row is disposed in one first display area.

[0032] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0033] Summary of the Figures

[0034] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0035] FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0036] FIG2 is a partial schematic diagram of a display area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0037] 3 is a schematic diagram illustrating an arrangement of a plurality of second light-emitting elements in a second sub-area of ​​a first display area according to at least one embodiment of the present disclosure;

[0038] FIG4 is another partial schematic diagram of the display area of ​​the display substrate according to at least one embodiment of the present disclosure;

[0039] FIG5 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0040] FIG6 is another partial schematic diagram of the display area of ​​the display substrate according to at least one embodiment of the present disclosure;

[0041] FIG7 is another schematic diagram of the display area of ​​the display substrate according to at least one embodiment of the present disclosure;

[0042] FIG8 is another partial schematic diagram of the display area of ​​the display substrate according to at least one embodiment of the present disclosure;

[0043] FIG9 is another partial schematic diagram of the display area of ​​the display substrate according to at least one embodiment of the present disclosure;

[0044] FIG10 is another partial schematic diagram of the first display area of ​​the display substrate according to at least one embodiment of the present disclosure;

[0045] FIG11 is a partial schematic diagram of a shielding layer in the first display area in FIG10 ;

[0046] FIG12 is a partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0047] FIG13 is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0048] FIG14 is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0049] FIG15 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0050] FIG16 is a partial schematic diagram of a semiconductor layer in a display area according to at least one embodiment of the present disclosure;

[0051] FIG17A is a partial schematic diagram of a display area after forming a first conductive layer in at least one embodiment of the present disclosure;

[0052] FIG17B is a schematic diagram of the first conductive layer in FIG17A ;

[0053] FIG18A is a partial schematic diagram of a display area after a second conductive layer is formed in at least one embodiment of the present disclosure;

[0054] FIG18B is a schematic diagram of the second conductive layer in FIG18A ;

[0055] FIG19A is a partial schematic diagram of a display area after a third conductive layer is formed in at least one embodiment of the present disclosure;

[0056] FIG19B is a schematic diagram of the third conductive layer in FIG19A;

[0057] FIG20A is a partial schematic diagram of a display area after a fourth conductive layer is formed in at least one embodiment of the present disclosure;

[0058] FIG20B is a schematic diagram of the fourth conductive layer in FIG20A ;

[0059] FIG21A is a partial schematic diagram of a display area after an anode layer is formed in at least one embodiment of the present disclosure;

[0060] FIG21B is a schematic diagram of the anode layer in FIG21A;

[0061] FIG22 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0062] FIG23 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0063] FIG24 is another partial schematic diagram of the display area according to at least one embodiment of the present disclosure;

[0064] FIG25 is another partial schematic diagram of the display area according to at least one embodiment of the present disclosure;

[0065] FIG26 is another partial schematic diagram of the display area according to at least one embodiment of the present disclosure;

[0066] FIG27 is another partial schematic diagram of the display area according to at least one embodiment of the present disclosure;

[0067] FIG28 is another partial schematic diagram of the display area according to at least one embodiment of the present disclosure;

[0068] FIG29 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0069] FIG30 is another partial schematic diagram of the display area according to at least one embodiment of the present disclosure;

[0070] FIG31 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0071] FIG32 is another partial schematic diagram of the display area according to at least one embodiment of the present disclosure;

[0072] FIG33 is another schematic diagram of an arrangement of a plurality of second light-emitting elements in the second sub-area of ​​the first display area according to at least one embodiment of the present disclosure;

[0073] FIG34 is another partial schematic diagram of the display area according to at least one embodiment of the present disclosure;

[0074] FIG35 is another partial schematic diagram of the display area according to at least one embodiment of the present disclosure;

[0075] FIG36 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0076] FIG37 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0077] FIG38 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0078] FIG39 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0079] FIG40 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0080] FIG. 41 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0081] Details

[0082] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0083] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0084] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0085] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0086] In this specification, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connected," and "coupled" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meanings of these terms in this disclosure based on the specific circumstances.

[0087] In this specification, "connection" includes "electrical connection." "Electrical connection" includes the connection of components via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0088] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0089] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0090] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0091] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0092] The term "light transmittance" in this disclosure refers to the ability of light to pass through a medium, and is the percentage of the luminous flux passing through a transparent or translucent body to the incident luminous flux.

[0093] In the present disclosure, "about" and "substantially" are used without strict limits and allow for process and measurement errors. In the present disclosure, "same" may include values ​​that differ by less than 10%.

[0094] In this disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In this disclosure, "A extends along direction B" means "the main portion of A extends along direction B."

[0095] The terms "A and B are disposed in the same layer" or "A and B are in the same layer structure" in this disclosure mean that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B near the substrate are substantially the same distance from the substrate, or that the surfaces of A and B near the substrate are in direct contact with the same film layer. The "thickness" of a film layer refers to its dimension perpendicular to the display substrate.

[0096] In the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The "shape of A" mentioned in the present disclosure refers to the shape of the orthographic projection of A on the substrate.

[0097] With the continuous development of display technology, cameras are usually installed on display devices to meet the needs of shooting or face recognition. In order to maximize the screen-to-body ratio, technologies such as bangs screen, water drop screen, and hollowing out in the screen have appeared one after another. These technologies are achieved by making holes in part of the display area and placing a camera below the hole area to reduce the area occupied by the camera, thereby increasing the screen-to-body ratio. However, the above technologies require digging out part of the display area, which will cause part of the display image to be unable to be displayed, and the screen-to-body ratio cannot be further increased. In order to avoid punching holes in the display area and to make a true full screen possible while ensuring the practicality of the display substrate, an external pixel circuit or a built-in pixel circuit is usually used in the camera area under the screen.

[0098] The external pixel circuit method refers to setting the pixel circuit connected to the light-emitting element in the under-screen camera area in the normal display area, and improving the light transmittance of the under-screen camera area by arranging the light-emitting element and the pixel circuit separately. The light-emitting element and the pixel circuit can be electrically connected through a conductive connecting wire. Since there is no pixel circuit in the under-screen camera area, there is no other light-shielding layer in this area except the anode of the light-emitting element, which can achieve a higher light transmittance. However, under this method, the pixel circuit and the light-emitting element need to be electrically connected through a conductive connecting wire. Due to the limited arrangement space of the conductive connecting wire, the size (such as the aperture) of the under-screen camera area of ​​the display substrate using the external pixel circuit method is limited. For example, the external pixel circuit method is not suitable for under-screen camera areas in the shape of a runway hole, nor is it suitable for structures with multiple under-screen camera areas. Moreover, increasing the aperture of the under-screen camera area usually requires adding a mask process for the conductive connecting wire, which increases costs.

[0099] The built-in pixel circuit approach involves placing a light-emitting element and the pixel circuit connected to it in the under-screen camera area. Compared to the external pixel circuit approach, the built-in approach eliminates the need for long conductive wires to connect the pixel circuit and light-emitting element in the under-screen camera area, thus avoiding poor display quality in the under-screen camera area caused by these wires. Furthermore, the built-in approach places no restrictions on the size of the under-screen camera area, supporting large-aperture under-screen camera areas and multiple under-screen camera area structures. However, in display substrates employing the built-in pixel circuit approach, the anode of the light-emitting element in the under-screen camera area cannot completely shield the pixel circuit, thus affecting the light transmittance of the under-screen camera area.

[0100] This embodiment provides a display substrate, comprising: a substrate, a plurality of pixel circuits arranged on the substrate, and a plurality of light-emitting elements. The display substrate comprises at least one first display area and a second display area located on at least one side of the first display area. The maximum length of the first display area along the first direction is different from the maximum length along the second direction. The first direction intersects the second direction. For example, the first direction may be perpendicular to the second direction. The plurality of pixel circuits comprise: a plurality of first pixel circuits located in the first display area, and a plurality of reserved pixel circuits and a plurality of in-situ pixel circuits located in the second display area. In the second display area, the plurality of reserved pixel circuits arranged in sequence along the first direction constitute a row of reserved pixel circuits, the plurality of in-situ pixel circuits arranged along the first direction constitute a row of in-situ pixel circuits, and along the second direction, a row of reserved pixel circuits is arranged every m rows of in-situ pixel circuits, where m may be an integer greater than 1. The plurality of light-emitting elements may comprise a plurality of first light-emitting elements and a plurality of second light-emitting elements located in the first display area, and a plurality of third light-emitting elements located in the second display area. At least one first pixel circuit among the plurality of first pixel circuits is connected to at least one first light-emitting element among the plurality of first light-emitting elements, and the orthographic projection of the at least one first pixel circuit on the substrate may at least partially overlap with the orthographic projection of the at least one first light-emitting element to which it is connected on the substrate. At least one second pixel circuit among the plurality of second pixel circuits is connected to at least one second light-emitting element among the plurality of second light-emitting elements via at least one first conductive connecting line extending along the second direction, and the orthographic projection of the at least one second pixel circuit on the substrate may not overlap with the orthographic projection of the at least one second light-emitting element to which it is connected on the substrate. At least one in-situ pixel circuit among the plurality of in-situ pixel circuits is connected to at least one third light-emitting element among the plurality of third light-emitting elements, and the orthographic projection of the at least one in-situ pixel circuit on the substrate may at least partially overlap with the orthographic projection of the at least one third light-emitting element to which it is connected on the substrate.

[0101] The display substrate provided in this embodiment combines both external and internal pixel circuit configurations in the first display area, ensuring light transmittance in the first display area while also allowing for increased size. For example, this example can accommodate an under-display camera area in the shape of a runway hole, and can also be adapted to the design requirements of multiple under-display camera areas.

[0102] In some exemplary embodiments, the maximum length of the first display area along the first direction may be greater than the maximum length along the second direction. The first display area may include a+1 first sub-areas and a second sub-areas, and the a+1 first sub-areas and a second sub-areas are arranged at intervals along the first direction, and a is an integer greater than 0. For example, a can be 1 or can be 3. In the first direction, at least one first sub-area is set between the second sub-area and the second display area. In other words, in the first direction, the first sub-area is adjacent to the second display area. The first sub-area is provided with a plurality of first pixel circuits and a plurality of first light-emitting elements, and the second sub-area is provided with a plurality of second light-emitting elements. In other words, the first sub-area can be a built-in area for the pixel circuit, and the second sub-area can be an external area for the pixel circuit. The arrangement of the first display area of ​​this example can be beneficial for shortening the length of the first conductive connecting line and improving the display uniformity of the display substrate.

[0103] In some exemplary embodiments, the maximum length of the first display area along the second direction may be greater than the maximum length along the first direction. The first display area may include: b first sub-areas and b+1 second sub-areas, b first sub-areas and b+1 second sub-areas are arranged at intervals along the second direction, and b is an integer greater than 0. For example, b may be 1 or may be 2. In the second direction, at least one second sub-area may be set between the first sub-area and the second display area. In other words, in the second direction, the second sub-area is adjacent to the second display area. The first sub-area is provided with a plurality of first pixel circuits and a plurality of first light-emitting elements, and the second sub-area is provided with a plurality of second light-emitting elements. The arrangement of the first display area of ​​this example can be beneficial for shortening the length of the first conductive connecting line and improving display uniformity.

[0104] In some exemplary embodiments, the first display area may include: a plurality of island areas, a transmissive area located between adjacent island areas, and an inter-island connection area connecting adjacent island areas. The light transmittance of the transmissive area is greater than that of the island areas. The island areas are provided with a plurality of first pixel circuits and a plurality of first light-emitting elements. The first display area may satisfy at least one of the following conditions: the transmissive area is provided with a plurality of second light-emitting elements; and the inter-island connection area is provided with a plurality of second light-emitting elements. In this example, the island areas serve as built-in pixel circuit areas, and the transmissive area, the inter-island connection area, or both the transmissive area and the inter-island connection area may serve as external pixel circuit areas.

[0105] In some exemplary embodiments, the first display area includes multiple transmissive areas, each of which includes at least one first transmissive area and multiple second transmissive areas. The first transmissive area is provided with multiple second light-emitting elements, and the light transmittance of the second transmissive areas is greater than that of the first transmissive areas. The second transmissive areas may be spaced apart from the first transmissive areas along the first direction or the second direction. In this example, a portion of the transmissive areas (i.e., the first transmissive areas) may be provided with second light-emitting elements, while another portion of the transmissive areas (i.e., the second transmissive areas) may not be provided with pixel circuits or light-emitting elements, thereby improving the light transmittance of the first display area.

[0106] The solution of this embodiment is illustrated below through some examples.

[0107] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display substrate may include a display area AA and a peripheral area BB located outside the display area AA. The peripheral area BB may include a first peripheral area B1 located on one side of the display area AA and a second peripheral area located on the remaining sides of the display area AA. For example, the first peripheral area B1 may be the lower border area of ​​the display substrate, and the second peripheral area may include an upper border area B2, a left border area B3, and a right border area B4 of the display substrate. The first peripheral area B1 may be connected to the left border area B3 and the right border area B4, and the upper border area B2 may be connected to the left border area B3 and the right border area B4. The left border area B3 and the right border area B4 may be located on either side of the display area AA along a first direction X, and the upper border area B2 and the first peripheral area B1 may be located on either side of the display area AA along a second direction Y. The first direction X intersects the second direction Y. For example, the first direction X may be perpendicular to the second direction Y.

[0108] In some examples, as shown in Figure 1, the first peripheral area B1 may include: a first signal access area B11 and a second signal access area B12. The first signal access area B11 may be located on a side of the second signal access area B12 close to the display area AA. The first signal access area B11 may be provided with a plurality of first contact pads, and the second signal access area B12 may be provided with a plurality of second contact pads. A portion of the first contact pads within the first signal access area B11 may be connected to a portion of the second contact pads within the second signal access area B12 through a plurality of contact pad connection lines. The plurality of first contact pads within the first signal access area B11 may be connected to a driver integrated circuit (IC), and the driver integrated circuit may be configured to provide a plurality of signals, such as data signals. The plurality of second contact pads within the second signal access area B12 may be connected to an external circuit board (e.g., a flexible circuit board).

[0109] In some examples, as shown in Figure 1, the display area AA may include a first display area A1 and a second display area A2, and the second display area A2 may at least partially surround the first display area A1. For example, the display area AA may be rectangular, the first display area A1 may be located at the top center of the display area AA, and the second display area A2 may surround the first display area A1. The peripheral area BB may surround the second display area A2. In other examples, the first display area A1 may be located at other locations such as the upper left corner, lower left corner, upper right corner, or lower right corner of the display area.

[0110] In some examples, the first display area A1 can be called a light-transmitting display area and can serve as an under-screen camera (FDC, Full Display With Camera) area or an under-screen facial recognition function area (Face ID). The second display area A2 can be called a normal display area. The light transmittance of the first display area A1 can be greater than the light transmittance of the second display area A2. For example, the orthographic projection of a sensor (including hardware such as a camera) on the display substrate can be located within the first display area A1 of the display substrate.

[0111] In some examples, the first display area A1 may be in the shape of a racetrack hole. For example, the first display area A1 may include a rectangular area and two semicircular areas, where the two semicircular areas may be connected at opposite ends of the rectangular area along a first direction X. The maximum length L1 of the first display area A1 along the first direction X may be greater than the maximum length L2 along the second direction Y. In other words, the first display area A1 may be in the shape of a racetrack hole extending along the first direction X.

[0112] In some examples, the display area AA may be provided with multiple pixel units, and each pixel unit may include three or four sub-pixels. For example, the three sub-pixels included in a pixel unit may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel; or the four sub-pixels included in a pixel unit may be two green sub-pixels, one red sub-pixel, and one blue sub-pixel.

[0113] In some examples, at least one sub-pixel may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0114] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The light-emitting color of the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0115] Figure 2 is a partial schematic diagram of the display area of ​​a display substrate according to at least one embodiment of the present disclosure. Figure 2 illustrates a portion of the first pixel circuit 21, a portion of the first light-emitting element 11, a portion of the second light-emitting element 12, a portion of the second pixel circuit 22, and a portion of the third light-emitting element 13 in the first display area A1. Subsequent figures illustrate portions of the pixel circuits and light-emitting elements in the display area as examples.

[0116] In some examples, as shown in FIG2 , the first display area A1 may be in the shape of a runway hole extending along the first direction X. In this example, the number a of second sub-areas may be 1. The first display area A1 may include two first sub-areas A11a and A11b, and one second sub-area A12. The second sub-area A12 may be located between the two first sub-areas A11a and A11b along the first direction X. The first sub-area A11a may be located between the second display area A2 and the second sub-area A12 along the first direction X. The first sub-area A11b may be located between the second sub-area A12 and the second display area A2 along the first direction X. In other words, the first sub-area A11a, the second sub-area A12, and the first sub-area A11b may be arranged sequentially along the first direction X. For example, the first sub-areas A11a and A11b may be semicircular areas, and the second sub-area A12 may be a rectangular area. This embodiment is not limited to this.

[0117] In some examples, the first sub-areas A11a and A11b may be provided with a plurality of first pixel circuits 21 and a plurality of first light-emitting elements 11. At least one first pixel circuit 21 is connected to at least one first light-emitting element 11 and is configured to drive the connected first light-emitting element 11 to emit light. The orthographic projection of the at least one first pixel circuit 21 on the substrate may at least partially overlap with the orthographic projection of the at least one first light-emitting element 11 to which it is connected on the substrate. The first pixel circuits 21 and the first light-emitting elements 11 in the first sub-areas A11a and A11b may be in a one-to-one drive relationship, or may be in a one-to-many drive relationship. In this example, the one-to-one drive relationship between the pixel circuit and the light-emitting element means that one pixel circuit is connected to one light-emitting element and is configured to drive one light-emitting element to emit light; the one-to-many drive relationship means that one pixel circuit is connected to multiple light-emitting elements and is configured to drive multiple light-emitting elements to emit light. The first sub-areas A11a and A11b in this example may be pixel circuit built-in areas.

[0118] In some examples, the second sub-area A12 may be provided with a plurality of second light-emitting elements 12. The plurality of second pixel circuits 22 connected to the plurality of second light-emitting elements 12 are located in the second display area A2. At least one second pixel circuit 22 may be connected to at least one second light-emitting element 12 via at least one first conductive connection line 31, and configured to drive the connected second light-emitting element 12 to emit light. The orthographic projection of the at least one second pixel circuit 22 on the substrate may not overlap with the orthographic projection of the at least one second light-emitting element 12 to which it is connected. The second pixel circuit 22 and the second light-emitting element 12 may be in a one-to-one relationship, or in a one-to-many relationship. The second sub-area A12 of this example may be an external pixel circuit area.

[0119] In some examples, the first conductive connection lines 31 may extend along the second direction Y. The material of the first conductive connection lines 31 may include a transparent conductive material, such as indium tin oxide (ITO). Using a transparent conductive material to prepare the first conductive connection lines 31 can help ensure the light transmittance of the first display area A1. For example, multiple first conductive connection lines 31 can be located in the same conductive film layer and can be prepared by a single patterning process. In other examples, multiple first conductive connection lines 31 can be arranged in multiple conductive film layers to reduce wiring space.

[0120] In some examples, the second display area A2 may be provided with a plurality of reserved pixel circuits 20, a plurality of in-situ pixel circuits 23, and a plurality of third light-emitting elements 13. At least one in-situ pixel circuit 23 is connected to at least one third light-emitting element 13 and is configured to drive the connected third light-emitting element 13 to emit light. The orthographic projection of the at least one in-situ pixel circuit 23 on the substrate may at least partially overlap with the orthographic projection of the at least one third light-emitting element 13 to which it is connected. The in-situ pixel circuit 23 and the third light-emitting element 13 may be in a one-to-one relationship, or in a one-to-many relationship.

[0121] In some examples, the multiple reserved pixel circuits 20 may include: multiple second pixel circuits 22 and multiple invalid pixel circuits 24. Within the second display area A2, the multiple reserved pixel circuits 20 and the multiple in-situ pixel circuits 23 may be arranged at intervals along the second direction Y. For example, the multiple reserved pixel circuits 20 arranged along the first direction X are referred to as a row of reserved pixel circuits, and the multiple in-situ pixel circuits 23 arranged along the first direction X are referred to as a row of in-situ pixel circuits; the multiple reserved pixel circuits 20 arranged along the second direction Y are referred to as a column of reserved pixel circuits, and the multiple in-situ pixel circuits 23 arranged along the second direction Y are referred to as a column of in-situ pixel circuits. For example, a row of reserved pixel circuits may include multiple second pixel circuits 22, or may include multiple second pixel circuits 22 and multiple invalid pixel circuits 24, or may include multiple invalid pixel circuits 24. Along the second direction Y, a row of reserved pixel circuits may be arranged with m rows of in-situ pixel circuits spaced apart, where m may be an integer greater than 1. In other words, m rows of in-situ pixel circuits may be arranged between two adjacent rows of reserved pixel circuits. In this example, m may be 2. In other examples, m can be 3 or 4. The structure of the inactive pixel circuit 24 in this example can be similar to that of the second pixel circuit 22, and the inactive pixel circuit 24 is not connected to the light-emitting element. By providing the inactive pixel circuit 24 in the second display area A2, the uniformity of the circuit film layer in the second display area A2 can be ensured.

[0122] In some examples, the second display area A2 may further be provided with a plurality of first signal lines 35 and a plurality of second signal lines 36. The plurality of first signal lines 35 may extend along the first direction X and be arranged along the second direction Y; the plurality of second signal lines 36 may extend along the second direction Y and be arranged along the first direction X. For example, the plurality of first signal lines 35 may include: a plurality of gate lines (such as a first scan line, a second scan line, and a light-emitting control line), a plurality of initial signal lines; the plurality of second signal lines 36 may include: a plurality of data lines and a plurality of first power lines. For example, the first signal lines 35 connected to a row of pixel circuits may include: a first scan line, a second scan line, a light-emitting control line, a first initial signal line and a second initial signal line; the plurality of second signal lines 36 connected to a column of pixel circuits may include: a data line and a first power line.

[0123] In some examples, as shown in FIG2 , the plurality of data lines may include: a plurality of first data lines DL1, a plurality of second data lines DL2, and a plurality of third data lines DL3. The plurality of third data lines DL3 are located within the second display area A2, extend along the second direction Y, and do not pass through the first display area A1. The plurality of first data lines DL1 and the plurality of second data lines DL2 extend along the second direction Y and pass through the first display area A1; the plurality of first data lines DL1 are interrupted by the first display area A1. The first data line DL1 may include: two sub-segments interrupted by the first display area A1, and a first data transfer line 361. The two sub-segments of the first data line DL1 interrupted by the first display area A1 may be connected by the first data transfer line 361 located in the first display area A1. The first data transfer line 361 may bypass the second sub-area A12 and, for example, may be located in the first sub-area A11a or A11b, or may be located at the junction of the first sub-area A11a (or A11b) and the second sub-area A12. The first data transfer line 361 may not be connected to any pixel circuits in the first display area A1. The second data line DL2 may include two sub-segments located in the second display area A2 and a second data transfer line 362 located in the first display area A1. The two sub-segments of the second data line DL2 located in the second display area A2 may be connected via the second data transfer line 362 located in the first display area A1. The second data transfer line 362 may be connected to a plurality of first pixel circuits 21 arranged sequentially along the second direction Y in the first sub-area A11a (or A11b).

[0124] In some examples, the first data line DL1 and the connected first data transfer line 361 can be an integral structure, and the second data line DL2 and the connected second data transfer line 362 can be an integral structure. However, this embodiment is not limited to this. For example, the first data line DL1 and the connected first data transfer line 361 can be located on different conductive layers, or the second data line DL2 and the connected second data transfer line 362 can be located on different conductive layers.

[0125] In some examples, at least one first signal line 35 can extend to the first display area A1, connect to the multiple first pixel circuits 21 arranged along the first direction X in the first sub-area A11a, and bypass the second sub-area A12 from the outer edge of the second sub-area A12 and then connect to the multiple first pixel circuits 21 arranged along the first direction X in the first sub-area A11b.

[0126] In some examples, the routing portion of the first signal line 35 located in the first sub-areas A11a and A11b can be made of a transparent conductive material, and the routing portion of the second signal line 36 located in the first sub-areas A11a and A11b can be made of a transparent conductive material, thereby ensuring light transmittance in the first display area A1. In other examples, the routing portions of multiple first signal lines 35 located in the first sub-areas A11a and A11b can be arranged in a centralized manner, or the routing portions of multiple second signal lines 36 located in the first sub-areas A11a and A11b can be arranged in a centralized manner.

[0127] In some examples, the plurality of first pixel circuits 21 in the first sub-areas A11a and A11b may be arranged in a dispersed manner. For example, the arrangement of the plurality of first pixel circuits 21 in the plurality of first sub-areas A11a and A11b may be similar to the arrangement of the pixel circuits in the second display area A2. For example, the first pixel circuits 21 may be aligned with the pixel circuits in the second display area A2 in the first direction X and the second direction Y.

[0128] In this example, the first sub-areas A11a and A11b of the first display area A1 can employ an internal pixel circuit approach, while the second sub-area A12 can employ an external pixel circuit approach. Compared to the first display area employing only external pixel circuits, this example can reduce the number of external second pixel circuits, thereby reducing the number of first conductive connection lines, which helps reduce the masking process for the conductive connection lines.

[0129] In this example, the second sub-area A12 is located between the two first sub-areas A11a and A11b along the first direction X, and the first conductive connection lines 31 are extended along the second direction Y. This can alleviate the problem of uneven conductive connection line lengths that require compensation when extending along the first direction X. Furthermore, multiple data lines can be routed along the edge of the second sub-area A12, rather than along the edge of the first display area A1. This reduces the data line length and thus reduces load differences between the multiple data lines, which helps avoid uneven display.

[0130] Figure 3 is a schematic diagram illustrating the arrangement of multiple second light-emitting elements in the second sub-area of ​​the first display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 3, the multiple second light-emitting elements 12 in the first display area may include: multiple second light-emitting elements 12a emitting first color light, multiple second light-emitting elements 12b emitting second color light, and multiple second light-emitting elements 12c and 12d emitting third color light. A pixel unit PX in the second sub-area may include: one second light-emitting element 12a emitting first color light, one second light-emitting element 12b emitting second color light, and two second light-emitting elements 12c and 12d emitting third color light. For example, the first color light may be red, the second color light may be blue, and the third color light may be green.

[0131] In some examples, within the second sub-region, the plurality of pixel units PX may be arranged in an array along a first direction X and a second direction Y. The plurality of pixel units PX arranged along the first direction X constitute a row of pixel units, and adjacent rows of pixel units may be staggered along the first direction X. For example, the staggered distance between adjacent rows of pixel units along the first direction X may be less than the length of a single pixel unit along the first direction X.

[0132] In some examples, the orthographic projection of the light-emitting area of ​​a single second light-emitting element 12a or 12b on the substrate can be approximately hexagonal, and the orthographic projection of the light-emitting area of ​​a single second light-emitting element 12c or 12d on the substrate can be approximately pentagonal. The area of ​​the light-emitting area of ​​a single second light-emitting element 12a can be smaller than the area of ​​the light-emitting area of ​​a single second light-emitting element 12b, and the area of ​​the light-emitting area of ​​a single second light-emitting element 12c or 12d can be smaller than the area of ​​the light-emitting area of ​​a single second light-emitting element 12a. The area of ​​the light-emitting area of ​​a single second light-emitting element 12c can be the same as the area of ​​the light-emitting area of ​​a single second light-emitting element 12d. The light-emitting area of ​​a light-emitting element in this example refers to the overlapping area of ​​the orthographic projection of the anode of the light-emitting element exposed by the pixel opening of the pixel definition layer and the organic functional layer and cathode on the substrate.

[0133] In some examples, within a pixel unit PX, the second light-emitting elements 12c and 12d may be aligned along the second direction Y and located between the second light-emitting elements 12a and 12b in the first direction X. The second light-emitting elements 12c and 12d may be symmetrically arranged about a middle line extending along the first direction X between the second light-emitting elements 12c and 12d.

[0134] The arrangement of the plurality of first light emitting elements in the first sub-area and the arrangement of the plurality of third light emitting elements in the second display area may refer to the arrangement of the plurality of second light emitting elements in the second sub-area, and thus will not be described in detail here.

[0135] Figure 4 is another partial schematic diagram of the display area of ​​a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 4, the first display area A1 may be in the shape of a racetrack hole extending along a first direction X. The first display area A1 may include four first sub-areas A11a, A11b, A11c, and A11d, and three second sub-areas A12a, A12b, and A12c. In this example, the number a of second sub-areas may be three. The four first sub-areas and the three second sub-areas may be arranged in intervals along the first direction X. For example, the first sub-area A11a may be located between the second display area A2 and the second sub-area A12a along the first direction X, the first sub-area A11b may be located between the second display area A2 and the second sub-area A12c along the first direction X, the first sub-area A11c may be located between the second sub-areas A12a and A12b along the first direction X, and the first sub-area A11d may be located between the second sub-areas A12b and A12c along the first direction X. In other words, along the first direction X, the first sub-area A11a, the second sub-area A12a, the first sub-area A11c, the second sub-area A12b, the first sub-area A11d, the second sub-area A12c, and the first sub-area A11b may be arranged in sequence.

[0136] In some examples, as shown in FIG4 , the four first sub-areas A11a, A11b, A11c, and A11d can be provided with a plurality of first pixel circuits 21 and a plurality of first light-emitting elements 11 using a built-in pixel circuit approach; the three second sub-areas A12a, A12b, and A12c can be provided with a plurality of second light-emitting elements 12 using an external pixel circuit approach, wherein the plurality of second light-emitting elements 12 are connected to a plurality of second pixel circuits 22 located in the second display area A2 via a plurality of first conductive connection lines 31. Within the second display area A2, along the second direction Y, a row of reserved pixel circuits can be arranged every two rows of in-situ pixel circuits 23, and at least one row of reserved pixel circuits can include a plurality of second pixel circuits 22 and a plurality of invalid pixel circuits 24. The structure of the invalid pixel circuit 24 can be similar to that of the second pixel circuit 22, and the invalid pixel circuit 24 is not connected to the light-emitting element. By providing the invalid pixel circuit 24 in the second display area A2, the uniformity of the circuit film layer of the second display area A2 can be ensured.

[0137] In this example, within the first display area, first sub-areas employing internal pixel circuits and second sub-areas employing external pixel circuits are alternately arranged along the first direction, thereby improving display uniformity within the first display area. Furthermore, by inserting the second pixel circuits into multiple in-situ pixel circuits along the second direction, the first conductive connection lines can be arranged along the second direction Y, further shortening the length of the first conductive connection lines. The remaining description of the display substrate of this example can be found in the description of the aforementioned embodiment, and will not be repeated here.

[0138] Figure 5 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 6 is another partial schematic diagram of a display region of a display substrate according to at least one embodiment of the present disclosure. Figure 6 illustrates only the first conductive connecting lines 31 between a plurality of second light-emitting elements 12 and second pixel circuits 22 as an example.

[0139] In some examples, as shown in Figures 5 and 6, the first display area A1 can be located at the upper left corner of the display area AA, or can be located at the upper right corner. The first display area A1 of the display substrate can be in the shape of a racetrack hole extending along the second direction Y. The maximum length L1 of the first display area A1 along the first direction X can be less than the maximum length L2 along the second direction Y.

[0140] In some examples, the number b of first sub-areas within the first display area may be 1. The first display area A1 may include: a first sub-area A11 and two second sub-areas A12d and A12e. The first sub-area A11 may be located between the two second sub-areas A12e and A12d along the second direction Y. The second sub-area A12e, the first sub-area A11, and the second sub-area A12d are aligned along the second direction Y. The second sub-areas A12e and A12d are both adjacent to the second display area A2 along the second direction Y. The maximum length of the first sub-area A11 along the second direction Y may be greater than the maximum length of the second sub-area A12e along the second direction Y, and greater than the maximum length of the second sub-area A12d along the second direction Y. For example, the second sub-areas A12e and A12d may be semicircular, and the first sub-area A11 may be rectangular.

[0141] In some examples, within the second display area A2, along the second direction Y, a row of reserved pixel circuits can be arranged every two rows of in-situ pixel circuits 23, and at least one row of reserved pixel circuits can include multiple second pixel circuits 22 and multiple invalid pixel circuits 24. The structure of the invalid pixel circuit 24 can be similar to that of the second pixel circuit 22, and the invalid pixel circuit 24 is not connected to the light-emitting element. The second light-emitting elements 12 within the second sub-areas A12e and A12d can be connected to the second pixel circuit 22 within the second display area A2 via a first conductive connection line 31. The first conductive connection line 31 can extend along the second direction Y.

[0142] In this example, the first display area A1 is shaped like a racetrack hole extending along the second direction Y. The two second sub-areas A12d and A12e are disposed at either end (e.g., the upper and lower ends) of the first sub-area A11 along the second direction Y. This further reduces the length of the first conductive connection line, thereby alleviating the need to compensate for uneven lengths of the conductive connection line between the second light-emitting element and the second pixel circuit. The remaining description of the display substrate of this example can be found in the description of the aforementioned embodiment and is therefore not repeated here.

[0143] Figure 7 is another schematic diagram of the display area of ​​a display substrate according to at least one embodiment of the present disclosure. In some examples, the number b of first sub-areas within the first display area can be 2. As shown in Figure 7, the first display area A1 can include two first sub-areas A11e and A11f, and three second sub-areas A12e, A12d, and A12f. The first display area A1 can have a racetrack-shaped aperture extending along the second direction Y. The first sub-area A11e can be located between the second sub-areas A12d and A12f along the second direction Y, the second sub-area A12f can be located between the first sub-areas A11e and A11f along the second direction Y, and the first sub-area A11f can be located between the second sub-areas A12f and A12e along the second direction Y. The second sub-area A12d, the first sub-area A11e, the second sub-area A12f, the first sub-area A11f, and the second sub-area A12e can be aligned along the second direction Y. The second sub-areas A12d and A12e are both adjacent to the second display area A2 in the second direction Y.

[0144] In some examples, within the second display area A2, along the second direction Y, a row of reserved pixel circuits may be arranged every m rows of in-situ pixel circuits 23, and at least one row of reserved pixel circuits may include a plurality of second pixel circuits 22 and a plurality of invalid pixel circuits 24; along the first direction X, a column of reserved pixel circuits may be arranged every n columns of in-situ pixel circuits, and at least one column of reserved pixel circuits may include a plurality of second pixel circuits 22 and a plurality of invalid pixel circuits 24; m and n may both be integers greater than 1. For example, m and n may be the same, both 2. In other examples, m and n may be different, for example, n may be greater than m.

[0145] In some examples, the second sub-areas A12d and A12e are adjacent to the second display area A2 in the second direction Y. The plurality of second light-emitting elements 12 in the second sub-areas A12d and A12e can be connected to the plurality of second pixel circuits 22 inserted into the third pixel circuit 23 in the second display area A2 along the second direction Y via a plurality of first conductive connection lines 31. The second sub-area A12f is located between the first sub-areas A11e and A11f in the second direction Y. The plurality of second light-emitting elements 12 in the second sub-area A12f can be connected to the plurality of second pixel circuits 22 inserted into the third pixel circuit 23 in the second display area A2 along the first direction X via a plurality of second conductive connection lines 32. The first conductive connection lines 31 can extend along the second direction Y, and the second conductive connection lines 32 can extend along the first direction X.

[0146] In this example, the first display area A1 is divided into a first sub-area and a second sub-area. The second light-emitting element 12 in the second sub-area adjacent to the second display area A2 along the second direction Y is connected to the second pixel circuit 22 via a first conductive connection line 31. The second light-emitting element 12 in the second sub-area located between the two first sub-areas along the second direction Y is connected to the second pixel circuit 22 via a second conductive connection line 32. This can further shorten the length of the conductive connection lines and reduce the length differences between different conductive connection lines. The remaining description of the display substrate of this example can be referred to the description of the previous embodiment and will not be repeated here.

[0147] FIG8 is another partial schematic diagram of the display area of ​​a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG8 , the first display area A1 may be in the shape of a runway hole extending along the first direction X. The first display area A1 may include: a plurality of island areas A13 separated from each other, a transmissive area (e.g., including a plurality of first transmissive areas A14a) located between adjacent island areas A13, and an inter-island connection area (e.g., including a plurality of first inter-island connection areas A15a and a plurality of second inter-island connection areas A15b) connecting adjacent island areas A13. The plurality of island areas A13 may be arranged in an array. For example, the plurality of island areas A13 arranged along the first direction X may be referred to as a row of island areas, and the plurality of island areas A13 arranged along the second direction Y may be referred to as a column of island areas. The light transmittance of the first transmissive area A14a may be greater than the light transmittance of the island areas A13 and the inter-island connection area.

[0148] In some examples, within a plane parallel to the display substrate, the multiple islands A13 may have the same shape, such as a substantially rectangular shape, or even a substantially square shape. The first inter-island connecting region A15a may be a linear region extending along a first direction X, connecting two adjacent islands A13 along the first direction X. The second inter-island connecting region A15b may be a linear region extending along a second direction Y, connecting two adjacent islands A13 along the second direction Y.

[0149] In some examples, within a plane parallel to the display substrate, the shapes of the multiple first transmission areas A14a can be the same, such as a "cross" shape with twelve sides. For example, one first transmission area A14a can be surrounded by four island areas A13 and four inter-island connecting areas (e.g., including two first inter-island connecting areas A15a and two second inter-island connecting areas A15b). Adjacent first transmission areas A14a arranged along the first direction X can be separated by the second inter-island connecting area A15b, and adjacent first transmission areas A14a arranged along the second direction Y can be separated by the first inter-island connecting area A15a.

[0150] In some examples, the area of ​​a single first transmission region A14a may be larger than the area of ​​a single island region A13 to improve the light transmittance of the first display region A1.

[0151] In some examples, a single island area A13 can be provided with multiple first pixel circuits and multiple first light-emitting elements, and the multiple first pixel circuits are connected to the multiple first light-emitting elements and configured to drive the multiple first light-emitting elements to emit light. A single first transmission area A14a can be provided with multiple second light-emitting elements 12, and the multiple second light-emitting elements 12 can be connected to the multiple second pixel circuits 22 located in the second display area A2 via multiple first conductive connection lines 31 extending along the second direction Y. Within the second display area A2, along the second direction Y, a row of reserved pixel circuits can be arranged every other two rows of in-situ pixel circuits 23, and at least one row of reserved pixel circuits can include multiple second pixel circuits 22 and multiple inactive pixel circuits 24.

[0152] In some examples, the first display area A1 includes only a plurality of first transmission areas A14a. In other words, a plurality of second light-emitting elements 12 are disposed in each transmission area between adjacent island areas A13. In other examples, the first display area A1 may include a plurality of transmission areas, which may include a plurality of first transmission areas A14a and a plurality of second transmission areas. The plurality of second light-emitting elements 12 may be disposed in the first transmission areas A14a, and the second transmission areas may not be provided with pixel circuits or light-emitting elements. For example, the size of a single first transmission area A14a may be the same as the size of a single second transmission area. The plurality of first transmission areas and the plurality of second transmission areas may be spaced apart along the first direction, or the plurality of first transmission areas and the plurality of second transmission areas may be spaced apart along both the first and second directions.

[0153] In the first display area of ​​this example, the island area adopts a built-in pixel circuit method, serving as a built-in pixel circuit area; the first transmission area adopts an external pixel circuit method, serving as an external pixel circuit area, which can help improve the display uniformity of the first display area. Moreover, in combination with the second pixel circuit being inserted into the third pixel circuit arrangement along the second direction, the first conductive connection line can be arranged along the second direction, which can help shorten the length of the first conductive connection line. In addition, multiple data lines (such as multiple first data lines separated by the first display area A1) can be arranged in an island area and an inter-island connection area wiring method, without having to bypass the edge of the first display area A1, which is beneficial to shortening the winding length of the data line and avoiding the uneven display caused by excessive differences in the loads of different data lines. The remaining description of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0154] FIG9 is another partial schematic diagram of the display area of ​​a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG9 , the first display area A1 may be in the shape of a racetrack hole extending along the first direction X. The first display area A1 may include: a plurality of island areas A13 spaced apart from each other; a transmissive area (e.g., including a plurality of first transmissive areas A14a and a plurality of second transmissive areas A14b) located between adjacent island areas A13; and an inter-island connecting area connecting adjacent island areas A13.

[0155] In some examples, multiple island areas A13 can be regularly arranged along the first direction X and the second direction Y. Multiple second light-emitting elements 12 can be disposed in the first transmission area A14a. The multiple second light-emitting elements 12 can be connected to the multiple second pixel circuits 22 located in the second display area A2 via multiple first conductive connection lines 31 extending along the second direction Y. Within the second display area A2, a row of reserved pixel circuits can be arranged every two rows of in-situ pixel circuits 23 along the second direction Y. At least one row of reserved pixel circuits can include multiple second pixel circuits 22 and multiple inactive pixel circuits 24. No light-emitting elements or pixel circuits can be disposed in the second transmission area A14b to improve the light transmittance of the first display area A1.

[0156] In some examples, the second transmission region A14b may be surrounded by four island regions A13 and four inter-island connecting regions. The first transmission region A14a may be surrounded by multiple (e.g., eight) island regions A13 and multiple inter-island connecting regions. The second transmission region A14b and the first transmission region A14a may be spaced apart along the first direction X. The area of ​​a single first transmission region A14a may be larger than the area of ​​a single second transmission region A14b. For example, the length of a single first transmission region A14a along the second direction Y may be larger than the length of a single second transmission region A14b along the second direction Y, and the length of a single first transmission region A14a along the first direction X may be larger than the length of a single second transmission region A14b along the first direction X. The maximum length of a single first transmission region A14a along the first direction X may be larger than the maximum length along the second direction Y.

[0157] In the first display area of ​​this example, the island area A13 adopts a built-in pixel circuit method, serving as a built-in pixel circuit area; the first transmission area A14a adopts an external pixel circuit method, serving as an external pixel circuit area; and the second transmission area A14b does not have a pixel circuit or a light-emitting element, which can help improve the display uniformity and light transmittance of the first display area A1. Moreover, the insertion of the third pixel circuit 23 into the second direction Y in combination with the second pixel circuit 22 can extend the first conductive connection line 31 along the second direction Y, which helps shorten the length of the first conductive connection line 31. In addition, multiple data lines (such as multiple first data lines separated by the first display area A1) can be arranged in the island area A13 and the inter-island connection area, without having to bypass the edge of the first display area A1. This helps shorten the winding length of the data line and avoids display unevenness caused by excessive differences in loads between different data lines. The remaining description of the display substrate of this example can refer to the description of the previous embodiment, so it will not be repeated here.

[0158] FIG10 is another partial schematic diagram of the first display area of ​​a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG10 , the first display area A1 may include: a plurality of island areas A13, a plurality of transmissive areas (e.g., a plurality of first transmissive areas A14a and a plurality of second transmissive areas A14b), and a plurality of inter-island connecting areas (e.g., a plurality of first inter-island connecting areas A15a and a plurality of second inter-island connecting areas A15b).

[0159] In some examples, a plurality of first light-emitting elements 11 and a plurality of first pixel circuits 21 are provided in the island area A13. For example, three first pixel circuits 21 may be provided in a single island area A13, and the three first pixel circuits 21 may be arranged in sequence along the first direction X. Three first light-emitting elements may be provided in a single island area A13, and the three first light-emitting elements are electrically connected to the three first pixel circuits 21 in a one-to-one correspondence; or, four first light-emitting elements may be provided in a single island area A13 (for example, including a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and two first light-emitting elements emitting a third color light), a first light-emitting element emitting the first color light is connected to a first pixel circuit, a first light-emitting element emitting the second color light is connected to a first pixel circuit, and two first light-emitting elements emitting the third color light may be connected to the same first pixel circuit.

[0160] In some examples, a plurality of second light-emitting elements 12 are disposed within the first transmission region A14a, while no light-emitting elements or pixel circuits are disposed within the second transmission region A14b. A single second transmission region A14b can be surrounded by four island regions A13, two first inter-island connecting regions A15a, and two second inter-island connecting regions A15b. A single first transmission region A14a can be surrounded by four island regions A13, two first inter-island connecting regions A15a, and two second inter-island connecting regions A15b. The plurality of first transmission regions A14a and the plurality of second transmission regions A14b can be arranged in a spaced arrangement along the first direction X. For example, a column of first transmission regions can be arranged every two columns of second transmission regions.

[0161] In some examples, the maximum length of the first transmission region A14a along the first direction X can be greater than the maximum length along the second direction Y. The maximum length of the first transmission region A14a along the first direction X can be greater than the maximum length of the second transmission region A14b along the first direction X, and the maximum length of the first transmission region A14a along the second direction Y can be the same as the maximum length of the second transmission region A14b along the second direction Y. The length of the first inter-island connecting region A15a adjacent to the first transmission region A14a along the first direction X can be greater than the length of the first inter-island connecting region A15a adjacent to the second transmission region A14b along the first direction X.

[0162] In some examples, the plurality of second light-emitting elements 12 within the first transmission area A14a can be connected to the plurality of second pixel circuits within the second display area A2 via the plurality of first conductive connection lines 31. The plurality of first conductive connection lines 31 can extend along the second direction Y. For example, the first display area A1 can have a first center line O1 extending along the first direction X. The plurality of second light-emitting elements 12 located above the first center line O1 can be connected to the plurality of second pixel circuits within the second display area above the first display area A1, and the plurality of second light-emitting elements 12 located below the first center line O1 can be connected to the plurality of second pixel circuits within the second display area below the first display area A1.

[0163] FIG11 is a partial schematic diagram of the shielding layer of the first display area in FIG10 . In some examples, as shown in FIG10 and FIG11 , the display substrate may further include: a shielding layer located in the first display area A1. The shielding layer may include: a first shielding layer 421 and a second shielding layer 422. The orthographic projection of the first shielding layer 421 on the substrate may cover the orthographic projections of the multiple first pixel circuits 21 and the multiple first light-emitting elements 11 in the island area A13 on the substrate, and may also cover the orthographic projections of the wiring of the multiple inter-island connection areas on the substrate. The second shielding layer 422 may be located in the first transmission area A14a, and its orthographic projection on the substrate may cover the orthographic projections of the multiple second light-emitting elements 12 in the first transmission area A14a on the substrate. The first shielding layer 421 and the second shielding layer 422 may be an integral structure.

[0164] In some examples, the integrated structure of the first shielding layer 421 and the second shielding layer 422 can be used to pattern the cathode layer of the first display area A1. For example, a patterned cathode layer can be obtained by laser irradiation of the cathode film covered by the first shielding layer 421 and the second shielding layer 422. In other examples, the display substrate may be provided with only the first shielding layer or the second shielding layer.

[0165] This example utilizes a shielding layer to shield the pixel circuits, light-emitting elements, and traces in the first display area, thereby reducing diffraction in the first display area and improving the display quality of the first display area. The remaining description of the display substrate in this example can be found in the description of the previous embodiment and will not be repeated here.

[0166] Figure 12 is a schematic partial cross-sectional view of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 12 , in a direction perpendicular to the display substrate, the display substrate may include: a substrate 40, and a circuit structure layer, a light-emitting structure layer, and an encapsulation structure layer sequentially disposed on substrate 40. In some examples, the display substrate may also include other film layers, such as a touch structure layer and a color filter layer. This embodiment is not limited to this.

[0167] In some examples, the circuit structure layer of the first display area A1 may include: a first pixel circuit 21 located in the island area A13; the light-emitting structure layer of the first display area A1 may include: a first light-emitting element 11 located in the island area A13 and a second light-emitting element 12 located in the first transmission area A14a. The circuit structure layer of the second display area A2 may include: a second pixel circuit, an in-situ pixel circuit 23, and a third light-emitting element 13. Figure 12 illustrates one transistor and one third light-emitting element 13 of one in-situ pixel circuit 23 in the second display area A2, and one transistor and one first light-emitting element 11, as well as two second light-emitting elements 12 of the first pixel circuit 21 in the first display area A1.

[0168] In some examples, the circuit structure layer may include: a first blocking layer 421, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a first transparent conductive connection layer disposed on a substrate 40. A first insulating layer 411 (also referred to as a first buffer layer) may be disposed between the first blocking layer 421 and the substrate 40, a second insulating layer 412 (also referred to as a second buffer layer) may be disposed between the first blocking layer 421 and the semiconductor layer, a third insulating layer 413 (also referred to as a first gate insulating layer) may be disposed between the semiconductor layer and the first conductive layer, a fourth insulating layer 414 (also referred to as a second gate insulating layer) may be disposed between the first conductive layer and the second conductive layer, a fifth insulating layer 415 (also referred to as an interlayer insulating layer) may be disposed between the second conductive layer and the third conductive layer, a sixth insulating layer 416 (also referred to as a first planarizing layer) may be disposed between the third conductive layer and the first transparent conductive connection layer, and a seventh insulating layer 417 (also referred to as a second planarizing layer) may be disposed on the side of the first transparent conductive connection layer away from the substrate 40. The first conductive layer may also be referred to as a first gate metal layer, the second conductive layer may also be referred to as a second gate metal layer, and the third conductive layer may also be referred to as a first source / drain metal layer. In some examples, the first shielding layer 421, the first conductive layer, the second conductive layer, and the third conductive layer may be made of a metal material, and the first transparent conductive connection layer may be made of a transparent conductive material, such as ITO.

[0169] In some examples, the first to fifth insulating layers 411 to 415 may be inorganic insulating layers, and the sixth and seventh insulating layers 416 and 417 may be organic insulating layers. However, this embodiment is not limited thereto. In other examples, an inorganic insulating layer may be further disposed between the sixth insulating layer 416 and the third conductive layer.

[0170] In some examples, the first shielding layer 421 may be located in the island area A13 and the inter-island connection area of ​​the first display area A1. The orthographic projection of the first shielding layer 421 on the substrate 40 may cover the orthographic projection of the active layer of at least one transistor of the first pixel circuit 21 in the island area A13 on the substrate 40. For example, if the first pixel circuit 21 includes multiple transistors, the orthographic projection of the first shielding layer 421 on the substrate may cover the orthographic projection of the active layers of all transistors of the first pixel circuit 21 on the substrate. In this example, by providing the first shielding layer 421 in the island area A13 to cover the active layers of the transistors of the first pixel circuit 21, interference with the transistors of the first pixel circuit 21 by external light can be prevented, thereby ensuring the performance of the transistors of the first pixel circuit 21.

[0171] In some examples, the semiconductor layer may include at least: an active layer of a transistor of the first pixel circuit 21 located in the island area A13, and an active layer of a transistor of the in-situ pixel circuit 23 located in the second display area A2. The first conductive layer may include at least: a gate electrode of the transistor of the first pixel circuit 21 located in the island area A13 and a first electrode of a storage capacitor (not shown), and a gate electrode of the transistor of the in-situ pixel circuit 23 located in the second display area A2 and a first electrode of a storage capacitor (not shown). The second conductive layer may include at least: a second electrode of the storage capacitor of the first pixel circuit 21 (not shown), and a second electrode of the storage capacitor of the in-situ pixel circuit 23 (not shown). The third conductive layer may include at least: a first electrode 2101 and a second electrode 2102 of the transistor of the first pixel circuit 21, and a first electrode 2301 and a second electrode 2302 of the transistor of the in-situ pixel circuit 23. The transparent conductive connection layer may include: a plurality of first anode connection electrodes 331 located in the first display area A1, a plurality of second anode connection electrodes 332 located in the second display area A2, and a plurality of first conductive connection lines 31. One end of the first conductive connection line 31 may be connected to the second light emitting element 12 , and the other end may extend to the second display area A2 and be connected to the second pixel circuit of the second display area A2 .

[0172] In some examples, the light-emitting structure layer may include an anode layer, a pixel definition layer 434, an organic functional layer, and a cathode layer, arranged in sequence. The anode layer may include at least the anode 121 of the second light-emitting element 12 located in the first transmission area A14a, the anode 111 of the first light-emitting element 11 located in the island area A13, and the anode 131 of the third light-emitting element 13 located in the second display area A2. The organic functional layer may include at least the organic light-emitting layer 122 of the second light-emitting element 12 located in the first transmission area A14a, the organic light-emitting layer 112 of the first light-emitting element 11 located in the island area A13, and the organic light-emitting layer 132 of the third light-emitting element 13 located in the second display area A2. The cathode layer may include at least the cathode 123 of the second light-emitting element 12 located in the first transmission area A14a, the cathode 113 of the first light-emitting element 11 located in the island area A13, and the cathode 133 of the third light-emitting element 13 located in the second display area A2.

[0173] In some examples, the anode 131 of the third light-emitting element 13 can be located on the seventh insulating layer 417 and connected to the second anode connection electrode 332 through a via hole defined in the seventh insulating layer 417. The second anode connection electrode 332 can be connected to the third pixel circuit 23 through a via hole defined in the sixth insulating layer 416. The pixel definition layer 434 can have a third pixel opening defined in the second display area A2. The third pixel opening can expose at least a portion of the surface of the anode 131 of the third light-emitting element 13. The organic light-emitting layer 132 and cathode 133 of the third light-emitting element 13 can be sequentially stacked on the anode 131 exposed by the third pixel opening.

[0174] In some examples, the anode 121 of the second light-emitting element 12 can be located on the seventh insulating layer 417 and connected to the first conductive connection line 31 through a via hole defined in the seventh insulating layer 417. The first conductive connection line 31 can extend to the second display area A2 and connect to the second pixel circuit located in the second display area A2 through a via hole defined in the sixth insulating layer 416. The pixel definition layer 434 can have a second pixel opening defined in the first transmission area A14a of the first display area A1. The second pixel opening can expose at least a portion of the surface of the anode 121 of the second light-emitting element 12. The organic light-emitting layer 122 and cathode 123 of the second light-emitting element 12 can be sequentially stacked on the anode 121 exposed by the second pixel opening.

[0175] In some examples, the anode 111 of the first light-emitting element 11 can be located on the seventh insulating layer 417 and connected to the first anode connection electrode 331 through a via hole defined in the seventh insulating layer 417. The first anode connection electrode 331 can be connected to the first pixel circuit 21 through a via hole defined in the sixth insulating layer 416. The pixel definition layer 434 can have a first pixel opening defined in the island area A13 of the first display area A1. The first pixel opening can expose at least a portion of the surface of the anode 111 of the first light-emitting element 11. The organic light-emitting layer 112 and the cathode 113 of the first light-emitting element 11 can be sequentially stacked on the anode 111 exposed by the first pixel opening.

[0176] In some examples, the cathode 133 of the third light-emitting element 13, the cathode 113 of the first light-emitting element 11, and the cathode 123 of the second light-emitting element 12 can be interconnected as an integral structure. The cathode layer of the second display area A2 can be a solid structure, and the cathode layer of the first display area A1 can be patterned. For example, the pattern of the cathode layer of the first display area A1 can be as shown in Figure 11. The cathode film in the second transmission area A14b of the first display area A1 can be removed, and the cathode film in the area of ​​the first light-transmitting area A14a other than the second light-emitting element 12 can be removed to improve the light transmittance of the first display area A1.

[0177] In some examples, the encapsulation structure layer may include a stacked first encapsulation layer 441, a second encapsulation layer 442, and a third encapsulation layer 443. The first encapsulation layer 441 and the third encapsulation layer 443 may be made of inorganic materials, and the second encapsulation layer 442 may be made of organic materials. The second encapsulation layer 442 may be arranged between the first encapsulation layer 441 and the third encapsulation layer 443 to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer.

[0178] In some examples, a sensor 50 may be disposed on the non-display surface of the display substrate, and the orthographic projection of the sensor 50 on the display substrate may overlap with the first display area A1 of the display substrate. For example, the orthographic projection of the sensor 50 on the display substrate may be located within the first display area A1. For example, the sensor 50 may include a camera or an infrared sensor.

[0179] In this example, the anode 121 of the second light-emitting element 12 and the anode 111 of the first light-emitting element 11 are both disposed on the side of the seventh insulating layer 417 away from the substrate 40. This ensures the flatness of the first light-emitting element 11 and the second light-emitting element 12 in the first display area A1, thereby facilitating the display effect of the first display area A1. The remaining description of the display substrate of this example can be found in the description of the aforementioned embodiment, and will not be repeated here.

[0180] Figure 13 is another partial cross-sectional schematic diagram of a display substrate of at least one embodiment of the present disclosure. In some examples, as shown in Figure 13, in a direction perpendicular to the display substrate, the display substrate may include: a substrate 40, and a circuit structure layer, a light-emitting structure layer, and an encapsulation structure layer sequentially arranged on the substrate 40. The circuit structure layer may include: a first shielding layer 421, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first transparent conductive connection layer, and a second transparent conductive connection layer arranged on the substrate 40. A seventh insulating layer 417 may be provided between the first transparent conductive connection layer and the second transparent conductive connection layer, and an eighth insulating layer (also referred to as a third flat layer) 418 may be provided on the side of the second transparent conductive connection layer away from the substrate 40. The sixth insulating layer 416 to the eighth insulating layer 418 may be organic insulating layers, and the first insulating layer 411 to the fifth insulating layer 415 may be inorganic insulating layers. The first transparent conductive connection layer and the second transparent conductive connection layer may be made of a transparent conductive material, such as ITO.

[0181] In some examples, the first transparent conductive connection layer may include: a second anode connection electrode 332 located in the second display area A2; and a first anode connection electrode 331 located in the first display area A1. The second transparent conductive connection layer may include: a fourth anode connection electrode 334 located in the second display area A2; and a third anode connection electrode 333 located in the first display area A1. The anode 131 of the third light-emitting element 13 and the anode 111 of the first light-emitting element 11 may be located on the eighth insulating layer 418. The anode 131 of the third light-emitting element 13 may be connected to the fourth anode connection electrode 334 via a via hole provided in the eighth insulating layer 418, and the fourth anode connection electrode 334 may be connected to the second anode connection electrode 332 via a via hole provided in the seventh insulating layer 417. The anode 111 of the first light-emitting element 11 may be connected to the third anode connection electrode 333 via a via hole provided in the eighth insulating layer 418, and the third anode connection electrode 333 may be connected to the first anode connection electrode 331 via a via hole provided in the seventh insulating layer 417.

[0182] In some examples, the first conductive connecting line can be a co-layer structure with the anode layer. The anode 121 of the second light-emitting element 12 and the first conductive connecting line to which it is connected can be an integral structure. The anode 121 of the second light-emitting element 12 can be located on the second insulating layer 412. For example, after the eighth insulating layer 418 is prepared, the eighth insulating layer 418, the seventh insulating layer 417, the sixth insulating layer 416, the fifth insulating layer 415, the fourth insulating layer 414 and the third insulating layer 413 in the first transmission area A14a can be removed, so that the anode 121 of the second light-emitting element 12 can be formed on the second insulating layer 412. However, this embodiment is not limited to this. In other examples, the anode 121 of the second light-emitting element 12 can be located on the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer or the seventh insulating layer. In other examples, the conductive connecting line connected to the anode 121 of the second light-emitting element 12 can be located on the first transparent conductive connecting layer or the second transparent conductive connecting layer.

[0183] In this example, the anode 111 of the first light-emitting element 11 and the anode 121 of the second light-emitting element 12 can be located on different insulating layers. By removing multiple insulating layers on the side of the second light-emitting element 12 near the substrate 40 within the first transmission region A14a, the light transmittance of the first transmission region can be improved. The remaining description of the display substrate of this example can be found in the description of the previous embodiment and is not repeated here.

[0184] Figure 14 is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 14 , the display substrate may include, in a direction perpendicular to the display substrate, a substrate 40, and a circuit structure layer, a light-emitting structure layer, and an encapsulation structure layer sequentially disposed on substrate 40. The conductive connection line (e.g., first conductive connection line 31) connected to the anode 121 of the second light-emitting element 12 may be disposed in the same layer as the first shielding layer 421. The anode 121 of the second light-emitting element 12 may be located on the second insulating layer 412.

[0185] In this example, the anode 111 of the first light-emitting element 11 and the anode 121 of the second light-emitting element 12 can be located on different insulating layers. By removing multiple insulating layers on the side of the second light-emitting element 12 close to the substrate 40 in the first transmission area A14a, and arranging the conductive connection line (such as the first conductive connection line 31) connected to the second light-emitting element 12 on the same layer as the first shielding layer 421, it is not only beneficial to the arrangement of the conductive connection line, but also to improve the light transmittance of the first transmission area. The rest of the description of the display substrate of this example can be referred to the description of the previous embodiment, so it will not be repeated here.

[0186] Figure 15 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this example can be a 7T1C structure, which can include seven transistors (e.g., first transistor T1 to seventh transistor T7) and a capacitor (e.g., storage capacitor Cst). The pixel circuit can be electrically connected to the first scan line GL1, the second scan line GL2, the third scan line GL3, the emission control line EML, the first initial signal line INIT1, the second initial signal line INIT2, the data line DL, and the first power line VDD. The light-emitting element EL can be connected to the pixel circuit and the second power line VSS.

[0187] In some examples, the first power line VDD can be configured to provide a constant first voltage signal to the pixel circuit, the second power line VSS can be configured to provide a constant second voltage signal to the pixel circuit, and the first voltage signal can be greater than the second voltage signal. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit; the data line DL can be configured to provide a data signal to the pixel circuit; the emission control line EML can be configured to provide an emission control signal EM to the pixel circuit; the second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit; and the third scan line GL3 can be configured to provide a third scan signal SCAN3 to the pixel circuit.

[0188] In some examples, the second scan line GL2 electrically connected to the pixel circuit in the nth row can be electrically connected to the first scan line GL1 electrically connected to the pixel circuit in the n-1th row, so as to be input with the first scan signal SCAN1(n-1), that is, the second scan signal SCAN2(n) and the first scan signal SCAN1(n-1) can be the same. The third scan line GL3 of the pixel circuit in the nth row can be electrically connected to the first scan line GL1 of the pixel circuit in the nth row, so as to be input with the first scan signal SCAN1(n), that is, the third scan signal SCAN3(n) and the first scan signal SCAN1(n) can be the same. Wherein, n is an integer greater than 0. In this way, the signal lines of the display substrate can be reduced, and a narrow-frame design of the display substrate can be achieved. However, this embodiment is not limited to this.

[0189] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. In some examples, the first initial signal and the second initial signal line can be the same, and only the first initial signal line can be set to provide the first initial signal. However, this embodiment is not limited to this. In other examples, the first initial signal can be different from the second initial signal. The first initial signal and the second initial signal can be constant voltage signals, and their magnitudes can be, for example, between the first voltage signal and the second voltage signal, but are not limited thereto.

[0190] In some examples, the first transistor T1 may also be referred to as a first reset transistor, the second transistor T2 may also be referred to as a threshold compensation transistor, the third transistor T3 may also be referred to as a driving transistor, the fourth transistor T4 may also be referred to as a data writing transistor, the fifth transistor T5 may also be referred to as a first emission control transistor, the sixth transistor T6 may also be referred to as a second emission control transistor, and the seventh transistor T7 may also be referred to as a second reset transistor. The light-emitting device EL may be an organic electroluminescent diode (OLED), including a stacked first electrode (e.g., an anode), an organic light-emitting layer, and a second electrode (e.g., a cathode).

[0191] In some examples, the first transistor T1 to the seventh transistor T7 may be of the same transistor type, for example, all P-type transistors, or all N-type transistors. However, this embodiment is not limited to this. In other examples, the first transistor T1 and the second transistor T2 may be N-type transistors, and the third transistor T3 to the seventh transistor T7 may be P-type transistors.

[0192] In some examples, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon thin film transistors. Alternatively, the first transistor T1 and the second transistor T2 may be oxide thin film transistors, and the third transistor T3 to the seventh transistor T7 may be low-temperature polysilicon thin film transistors. The active layer of the low-temperature polysilicon thin film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0193] In some examples, the first electrode of the storage capacitor Cst is connected to the first node N1, that is, the first electrode of the storage capacitor Cst is connected to the gate of the third transistor T3, and the second electrode of the storage capacitor Cst is connected to the first power line VDD.

[0194] In some examples, a gate of the first transistor T1 is connected to the second scan line GL2, a first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and a second electrode of the first transistor T1 is connected to the first node N1. When an on-level signal is applied to the second scan line GL2, the first transistor T1 transmits the first initial signal provided by the first initial signal line INIT1 to the gate of the third transistor T3, so as to initialize the charge amount of the gate of the third transistor T3.

[0195] In some examples, the gate of the second transistor T2 is connected to the first scan line GL1, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1. When an on-level signal is applied to the first scan line GL1, the second transistor T2 connects the gate of the third transistor T3 to the second electrode.

[0196] In some examples, the gate of the third transistor T3 is connected to the first node N1, that is, the gate of the third transistor T3 is connected to the first electrode of the storage capacitor Cst, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 determines the amount of drive current flowing between the first power line VDD and the second power line VSS based on the potential difference between the gate and the first electrode. The first power line VDD can be configured to transmit a first voltage signal, and the second power line VSS can be configured to transmit a second voltage signal. The first voltage signal can be greater than the second voltage signal.

[0197] In some examples, a gate electrode of the fourth transistor T4 is connected to the first scan line GL1, a first electrode of the fourth transistor T4 is connected to the data line DL, and a second electrode of the fourth transistor T4 is connected to the second node N2. When an on-level signal is applied to the first scan line GL1, the fourth transistor T4 enables the data voltage of the data line DL to be input to the pixel circuit.

[0198] In some examples, the gate of the fifth transistor T5 is connected to the emission control line EML, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The gate of the sixth transistor T6 is connected to the emission control line EML, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4. When an on-level signal is applied to the emission control line EML, the fifth transistor T5 and the sixth transistor T6 form a drive current transmission path between the first power line VDD and the second power line VSS, thereby causing the light-emitting device to emit light.

[0199] In some examples, a gate electrode of the seventh transistor T7 is connected to the third scan line GL3, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4. When an on-level signal is applied to the third scan line GL3, the seventh transistor T7 transmits the second initial signal provided by the second initial signal line INIT2 to the first electrode of the light-emitting element EL, so as to initialize or release the charge accumulated in the first electrode of the light-emitting element EL.

[0200] In some examples, the second electrode of the light-emitting element EL is connected to the second power line VSS. The first scan line GL1 is a scan line in the pixel circuit of the current display row, and the second scan line GL2 can be a scan line in the pixel circuit of the previous display row. That is, for the nth display row, the first scan line GL1 is GL1(n), and the second scan line GL2 is GL1(n-1). The second scan line GL2 of the current display row and the first scan line GL1 in the pixel circuit of the previous display row can be the same signal line, thereby reducing the number of signal lines of the display panel and achieving a narrow bezel of the display panel.

[0201] In some examples, as shown in FIG2 , the first node N1 may be a connection point between the second electrode of the first transistor T1, the second electrode of the second transistor T2, the gate of the third transistor T3, and the first electrode of the storage capacitor Cst. The second node N2 may be a connection point between the second electrode of the fifth transistor T5, the second electrode of the fourth transistor T4, and the first electrode of the third transistor T3. The third node N3 may be a connection point between the second electrode of the third transistor T3, the first electrode of the second transistor T2, and the first electrode of the sixth transistor T6. The fourth node N4 may be a connection point between the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7, and the first electrode of the light-emitting element EL.

[0202] The operation process of the pixel circuit is described below. The pixel circuit shown in FIG15 includes a plurality of transistors, all of which are P-type transistors. In this example, the third scan signal provided by the third scan line GL3 can be the same as the first scan signal provided by the first scan line GL1.

[0203] In some examples, during a frame display period, the operation process of the pixel circuit may include: a first stage, a second stage, and a third stage.

[0204] The first phase is called the reset phase. The second scan signal SCAN2 provided by the second scan line GL2 can be a low-level signal, turning on the first transistor T1. The first initial signal provided by the first initial signal line INIT1 is provided to the first node N1, initializing the first node N1 and clearing the existing data voltage in the storage capacitor Cst. The first scan signal SCAN1 provided by the first scan line GL1 can be a high-level signal, and the emission control signal EM provided by the emission control line EML can be a high-level signal, turning off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this phase, the light-emitting element EL does not emit light.

[0205] The second phase is called the data writing phase or the threshold compensation phase. The first scan signal SCAN1 provided by the first scan line GL1 can be a low-level signal, the second scan signal SCAN2 provided by the second scan line GL2, and the emission control signal EM provided by the emission control line EML can both be high-level signals, and the data line DL outputs the data signal DATA. During this phase, since the first plate of the storage capacitor Cst is at a low level, the third transistor T3 is turned on. The first scan signal SCAN1 is a low-level signal, turning on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on, causing the data voltage Vdata output by the data line DL to be provided to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is then charged into the storage capacitor Cst. The voltage on the first plate of the storage capacitor Cst (i.e., the first node N1) is Vdata - |Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, so that the second initialization signal provided by the second initialization signal line INIT2 is provided to the anode of the light-emitting element EL, initializing (resetting) the anode of the light-emitting element EL and clearing the pre-stored voltage therein, completing the initialization and ensuring that the light-emitting element EL does not emit light. The second scan signal SCAN2 provided by the second scan line GL2 can be a high-level signal, turning off the first transistor T1. The emission control signal EM provided by the emission control signal line EML is a high-level signal, turning off the fifth transistor T5 and the sixth transistor T6.

[0206] The third phase is called the light-emitting phase. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, while the first scan signal SCAN1 provided by the first scan line GL1 and the second scan signal SCAN2 provided by the second scan line GL2 are high-level signals. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The first voltage signal output from the first power line VDD provides a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element EL to emit light.

[0207] During the pixel circuit driving process, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0208] I=K×(Vgs-Vth) 2=K×[(Vdd-Vdata+|Vth|)-Vth] 2 =K×[Vdd-Vdata] 2 .

[0209] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and Vdd is the first voltage signal output by the first power line VDD.

[0210] It can be seen from the above formula that the current flowing through the light emitting element EL has nothing to do with the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3.

[0211] The following illustrates the film structure of the display substrate by taking an example of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0212] In some examples, the preparation process of the display substrate may include the following operations. The pixel circuit of the display area takes the 7T1C structure shown in FIG. 15 as an example. The multiple pixel circuits in the display area include: multiple first-area pixel circuits located in the first display area A1, and multiple second-area pixel circuits located in the second display area A2; the multiple first-area pixel circuits include multiple first pixel circuits, and the multiple second-area pixel circuits include: multiple second pixel circuits, multiple in-situ pixel circuits, and multiple inactive pixel circuits. The following description uses the first pixel circuit in the first display area and the second-area pixel circuit in the second display area as examples.

[0213] In some examples, the first pixel circuit of the island area A13 of the first display area A1 may include: a first transistor 51, a second transistor 52, a third transistor 53, a fourth transistor 54, a fifth transistor 55, a sixth transistor 56, a seventh transistor 57 and a storage capacitor; the second area pixel circuit of the second display area A2 may include a first transistor 61, a second transistor 62, a third transistor 63, a fourth transistor 64, a fifth transistor 65, a sixth transistor 66, a seventh transistor 67 and a storage capacitor.

[0214] (1) Provide a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNy, y>0) or silicon oxide (SiOx, x>0), etc., to improve the substrate's resistance to water and oxygen.

[0215] (2) Forming a semiconductor layer. In some examples, a buffer film and a semiconductor film are sequentially deposited on a substrate, and the semiconductor film is patterned by a patterning process to form a buffer layer disposed on the substrate and a semiconductor layer disposed on the buffer layer. In some examples, the semiconductor layer can be made of amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene.

[0216] Figure 16 is a partial schematic diagram of a semiconductor layer in a display region according to at least one embodiment of the present disclosure. Figure 16 shows a partial boundary region between the first display region A1 and the second display region A2. In some examples, as shown in FIG16 , the semiconductor layer of the display area may include at least: active layers of multiple transistors of multiple first pixel circuits (for example, three first pixel circuits are provided in each island area) located in the first display area A1 (for example, including: the active layer 510 of the first transistor of the first pixel circuit, the active layer 520 of the second transistor, the active layer 530 of the third transistor, the active layer 540 of the fourth transistor, the active layer 550 of the fifth transistor, the active layer 560 of the sixth transistor, and the active layer 570 of the seventh transistor), and active layers of multiple transistors of multiple second-area pixel circuits located in the second display area (for example, including: the active layer 610 of the first transistor, the active layer 620 of the second transistor, the active layer 630 of the third transistor, the active layer 640 of the fourth transistor, the active layer 650 of the fifth transistor, the active layer 660 of the sixth transistor, and the active layer 670 of the seventh transistor).

[0217] In some examples, the active layers of the first to seventh transistors of each first pixel circuit may be interconnected as an integrated structure. The active layers of the first to seventh transistors of each third pixel circuit may be interconnected as an integrated structure.

[0218] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region located between the first region and the second region. The material of the semiconductor layer may include, for example, polysilicon. The channel region may not be doped with impurities and have semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region, and are doped with impurities and therefore have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as wiring doped with impurities, which can be used to electrically connect the transistors. This embodiment is not limited to this.

[0219] (3) Forming a first conductive layer. In some examples, a first gate insulating film and a first conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon, and the first conductive film is patterned by a patterning process to form a first gate insulating layer disposed on the semiconductor layer and a first conductive layer disposed on the first gate insulating layer.

[0220] FIG17A is a partial schematic diagram of a display area after forming a first conductive layer in at least one embodiment of the present disclosure. FIG17B is a schematic diagram of the first conductive layer in FIG17A. In some examples, as shown in FIG17A and FIG17B, the first conductive layer in the display area may include at least: a plurality of first scan lines (e.g., including first scan lines GL1(n) and GL1(n+1)), a plurality of second scan lines (e.g., including second scan lines GL2(n) and GL2(n+1)), a plurality of emission control lines (e.g., including emission control line EML(n)), a first plate 581 of a storage capacitor of a first pixel circuit, and a first plate 681 of a storage capacitor of a second region pixel circuit.

[0221] In some examples, the first plate 581 of the storage capacitor of the first pixel circuit can also serve as the gate of the third transistor 53. The first plate 681 of the storage capacitor of the second region pixel circuit can also serve as the gate of the third transistor 63.

[0222] In some examples, two rows of second-region pixel circuits within the second display area can correspond to a row of first pixel circuits within the first display area A1. The first scan line GL1(n), the second scan line GL2(n), and the emission control line EML(n) can be connected to the second-region pixel circuits in the nth row; the first scan line GL1(n), the emission control line EML(n), and the first scan line GL1(n+1) can be connected to the first pixel circuits in the nth row, and the second scan line GL2(n+1) can be configured to be connected to the seventh transistor of the first pixel circuit in the nth row. The first scan line GL1(n+1) is connected to the second-region pixel circuits in the n+1th row and bypasses the first pixel circuits in the nth row on the side opposite to the second direction Y.

[0223] In some examples, the shape of the second scan line GL2(n) can be substantially a zigzag line extending along the first direction X. The overlapping region of the second scan line GL2(n) and the active layer 610 of the first transistor 61 of the pixel circuit in the second region of the n-th row can serve as the gate of the first transistor 61. The overlapping region of the second scan line GL2(n) and the active layer 510 of the first transistor 51 of the first pixel circuit in the n-th row can serve as the gate of the first transistor 51.

[0224] In some examples, the shape of the first scan line GL1(n) can be substantially a straight line extending along the first direction X. The overlapping region of the first scan line GL1(n) with the active layer 620 of the second transistor 62 of the second region pixel circuit in the n-th row can serve as the gate of the second transistor 62, and the overlapping region of the first scan line GL1(n) with the active layer 640 of the fourth transistor 64 can serve as the gate of the fourth transistor 64. The overlapping region of the first scan line GL1(n) with the active layer 520 of the second transistor 52 of the first pixel circuit in the n-th row can serve as the gate of the second transistor 52, and the overlapping region of the first scan line GL1(n) with the active layer 540 of the fourth transistor 54 can serve as the gate of the fourth transistor 54.

[0225] In some examples, the shape of the emission control line EML(n) can be substantially a zigzag line extending along the first direction X. The overlapping region of the emission control line EML(n) with the active layer 650 of the fifth transistor 65 in the second-region pixel circuit in the n-th row can serve as the gate of the fifth transistor 65, and the overlapping region of the emission control line EML(n) with the active layer 660 of the sixth transistor 66 can serve as the gate of the sixth transistor 66. The overlapping region of the emission control line EML(n) with the active layer 550 of the fifth transistor 55 in the first pixel circuit in the n-th row can serve as the gate of the fifth transistor 55, and the overlapping region of the emission control line EML(n) with the active layer 560 of the sixth transistor 56 can serve as the gate of the sixth transistor 56.

[0226] In some examples, the shape of the second scan line GL2(n+1) can be substantially a zigzag line extending along the first direction X. An overlapping region of the second scan line GL2(n+1) and the active layer 570 of the seventh transistor 57 of the first pixel circuit in the n-th row can serve as a gate of the seventh transistor 57 .

[0227] In some examples, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the area blocked by the first conductive layer forms the channel region of the transistor, and the semiconductor layer in the area not blocked by the first conductive layer can be conducted, that is, the first area and the second area of ​​the active layer can both be conducted.

[0228] (4) Forming a second conductive layer. In some examples, a second gate insulating film and a second conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon, and the second conductive film is patterned by a patterning process to form a second gate insulating layer disposed on the first conductive layer and a second conductive layer disposed on the second gate insulating layer.

[0229] FIG18A is a partial schematic diagram of the display area after forming the second conductive layer in at least one embodiment of the present disclosure. FIG18B is a schematic diagram of the second conductive layer in FIG18A . In some examples, as shown in FIG18A and FIG18B , the second conductive layer in the display area may include at least: a plurality of first initial signal lines (e.g., including first initial signal lines INIT1(n) and INIT1(n+1)), a first initial connection segment 591, a second plate 582 of a storage capacitor of a first pixel circuit, and a second plate 682 of a storage capacitor of a second region pixel circuit.

[0230] In some examples, the orthographic projection of the second plate 582 of the storage capacitor of the first pixel circuit on the substrate overlaps the orthographic projection of the first plate 581. The second plates 582 of the storage capacitors of the three first pixel circuits in one island region can be interconnected and integrated.

[0231] In some examples, the orthographic projection of the second plate 682 of the storage capacitor of the second region pixel circuit on the substrate overlaps the orthographic projection of the first plate 681. The second plates 682 of the storage capacitors of multiple second region pixel circuits in the same row can be interconnected and integrated.

[0232] In some examples, the first initial connection segment 591 may be located in the island region and be in a strip shape extending along the first direction X. The first initial connection segment 591 may be located on one side of the semiconductor layers of the three first pixel circuits in the island region in the opposite direction to the second direction.

[0233] In some examples, the shape of the first initial signal line INIT1(n) can be substantially a zigzag line extending along the first direction X. The first initial signal line INIT1(n) can extend from the second display area to the first display area A1, and the first initial signal line INIT1(n+1) does not extend to the first display area A1. The first initial signal line of this example can be configured to provide an initial signal to the first transistor and the seventh transistor.

[0234] (5) Forming a third conductive layer. In some examples, an interlayer insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the interlayer insulating film is patterned by a patterning process to form an interlayer insulating layer. The interlayer insulating layer in the display area may be provided with a plurality of vias, and the plurality of vias may, for example, expose a portion of the surface of the semiconductor layer, a portion of the surface of the first conductive layer, and a portion of the surface of the second conductive layer. Subsequently, a third conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the third conductive film is patterned by a patterning process to form a third conductive layer provided on the interlayer insulating layer.

[0235] FIG19A is a partial schematic diagram of the display area after the third conductive layer is formed in at least one embodiment of the present disclosure. FIG19B is a schematic diagram of the third conductive layer in FIG19A . In some examples, as shown in FIG19A and FIG19B , the third conductive layer in the display area may include at least: a plurality of data lines (e.g., data lines 711, 712, and 713), a plurality of first power lines (e.g., first power lines 721, 722, and 723), and a plurality of connection electrodes (e.g., a first connection electrode 501, a second connection electrode 502, a third connection electrode 503, a fourth connection electrode 504, a fifth connection electrode 601, a sixth connection electrode 602, and a seventh connection electrode 603).

[0236] In some examples, the first connection electrode 501, the second connection electrode 502, the third connection electrode 503, and the fourth connection electrode 504 may be located within the island region. The first connection electrode 501 may be connected to the active layer 520 of the second transistor 52 of the first pixel circuit, and may also be connected to the gate of the third transistor 53. The first connection electrode 501 may serve as the first node of the first pixel circuit. The second connection electrode 502 may be connected to the first initial signal line INIT1(n), the active layer 510 of the first transistor 51, the active layer 570 of the seventh transistor 57, and the first initial connection segment 591. The second connection electrode 502 may electrically connect the first initial signal line to the first transistor 51 and the seventh transistor 57. The third connection electrode 503 may be connected to the active layer 560 of the sixth transistor 56. The fourth connection electrode 504 may be connected to the active layer 550 of the fifth transistor 55.

[0237] In some examples, the fifth connection electrode 601, the sixth connection electrode 602, and the seventh connection electrode 603 can be located in the second display area. The fifth connection electrode 601 can be connected to the active layer 620 of the second transistor 62 of the second region pixel circuit and can also be connected to the gate of the third transistor 63. The sixth connection electrode 602 can be connected to the first initial signal line INIT1(n), the active layer 610 of the first transistor 61 of the second region pixel circuit in the nth row, and the active layer 670 of the seventh transistor 67 of the second region pixel circuit in the (n-1)th row. The seventh connection electrode 603 can be connected to the active layer 660 of the sixth transistor 66 of the second region pixel circuit.

[0238] In some examples, in the second direction Y, six columns of second-region pixel circuits may correspond to three columns of first pixel circuits. Data line 711 may extend from the second display area into the first display area A1 and connect to the active layer 540 of the fourth transistor 54 of the first pixel circuit in the island area. Data line 711 may be generally zigzag or straight, extending along the second direction Y. Data line 712 may be located in the second display area and connect to the active layer 640 of the fourth transistor 64 of multiple second-region pixel circuits arranged along the second direction Y. Data line 713 may be located in the second display area and connect to a data transfer line located in the fourth conductive layer at the interface between the second display area and the first display area A1. In the first direction X, the three data lines 713 and the three data lines 711 may be arranged alternately. The three data lines 713 may bypass one side of the first pixel circuit via the data transfer line, and the three data lines 711 may be connected to the three first pixel circuits in the island area, respectively, to achieve data signal transmission.

[0239] In some examples, the first power line 721 can extend from the second display area to the island area within the adjacent first display area A1 and connect to the active layer 550 of the fifth transistor 55 of the first pixel circuit within the island area to achieve transmission of the first voltage signal. The first power lines 722 and 723 can be located in the second display area and connect to the active layer 650 of the fifth transistor 65 of multiple second region pixel circuits arranged along the second direction Y to achieve vertical transmission of the first voltage signal within the second display area. In the first direction X, the three first power lines 723 and the three first power lines 721 can be arranged alternately in sequence.

[0240] (6) Forming a fourth conductive layer. In some examples, a passivation insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the passivation insulating film is patterned by a patterning process to form a passivation layer. The passivation layer may be provided with a plurality of vias, and the plurality of vias may expose a portion of the surface of the third conductive layer. Subsequently, a fourth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer disposed on the passivation layer. In some examples, the fourth conductive layer may also be referred to as a second source / drain metal layer.

[0241] Figure 20A is a partial schematic diagram of the display area after the fourth conductive layer is formed in at least one embodiment of the present disclosure. Figure 20B is a schematic diagram of the fourth conductive layer in Figure 20A. In some examples, as shown in Figures 20A and 20B, the fourth conductive layer in the display area may include at least: a plurality of connecting electrodes (for example, including the eighth connecting electrode 505 and the ninth connecting electrode 605) and a plurality of data transfer lines 731.

[0242] In some examples, the eighth connection electrode 505 is located in the island region of the first display area A1 and is connected to the third connection electrode 503 to achieve a connection with the sixth transistor of the first pixel circuit. The ninth connection electrode 605 can be located in the second display area and is connected to the seventh connection electrode 603 to achieve a connection with the sixth transistor of the second region pixel circuit.

[0243] In some examples, the data transfer line 731 can be located in the first display area A1. The data transfer line 731 can be roughly in the shape of a broken line extending along the second direction Y. One end of the data transfer line 731 can be connected to the end of the data line 713 in the second display area above the first display area A1, and the other end can be connected to the end of the data line 713 in the second display area below the first display area A1, thereby enabling the transmission of data signals in the second display areas above and below the first display area A1. Three data transfer lines 731 can be grouped together and located on one side of the three first pixel circuits opposite the first direction X.

[0244] (7) Forming an anode layer. In some examples, a flat thin film is coated on the substrate having the aforementioned pattern, and a flat layer is formed by a patterning process. Subsequently, an anode thin film is deposited on the substrate having the aforementioned pattern, and the anode thin film is patterned by a patterning process to form an anode layer.

[0245] Figure 21A is a partial schematic diagram of the display area after the anode layer is formed in at least one embodiment of the present disclosure. Figure 21B is a schematic diagram of the anode layer in Figure 21A. In some examples, as shown in Figures 21A and 21B, the anode layer may include: anodes 111a, 111b, and 111c of the first light-emitting element located in island area A13 of the first display area A1, and anodes 131a, 131b, and 131c of the third light-emitting element located in the second display area.

[0246] In some examples, the anode 131b of the third light-emitting element can be connected to the sixth transistor of the second region pixel circuit through the ninth connection electrode 605. The anode 111a of the first light-emitting element can be connected to the eighth connection electrode 505 to electrically connect to the sixth transistor of the first pixel circuit.

[0247] In some examples, the anode layer may include: a stacked first sub-conductive layer, a second sub-conductive layer, and a third sub-conductive layer. The first sub-conductive layer and the third sub-conductive layer may be made of the same material, for example, a transparent conductive material such as indium tin oxide (ITO); the second sub-conductive layer may be made of a metal material such as silver (Ag). For example, the first conductive connecting line may be in the same layer structure as the first sub-conductive layer of the anode layer to achieve electrical connection between the second pixel circuit and the second light-emitting element. However, this embodiment is not limited to this.

[0248] Subsequently, a pixel definition layer, an organic light-emitting layer, a cathode layer, and an encapsulation structure layer are sequentially formed. In some examples, the pixel definition layer can form multiple pixel openings, and organic light-emitting layers can be formed in each of the multiple pixel openings. The organic light-emitting layers are connected to corresponding anodes, and the cathode layer can be connected to the organic light-emitting layer. In some examples, the cathode layer in the first display area can be patterned, and the cathode layer in the second transmission area A14b and the cathode layer in the first transmission area except for the area where the second light-emitting element is located can be removed to increase the light transmittance of the first display area.

[0249] In some examples, as shown in FIG21A , the display substrate may include a first shielding layer 421 located in the first display area A1. The orthographic projection of the first shielding layer 421 on the substrate may cover the orthographic projections of the island area A13 and the inter-island connecting area (including the first inter-island connecting area A15a and the second inter-island connecting area A15b). The first shielding layer 421 may not overlap with the second transmissive area A14b. The boundaries between the island area A13, the first inter-island connecting area A15a, and the second inter-island connecting area A15b may be defined by the first shielding layer 421, for example.

[0250] In some examples, the first shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, and the passivation layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The planar layer can be made of an organic material such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of an organic material such as polyimide, acrylic, or polyethylene terephthalate. However, this embodiment is not limited to this.

[0251] The structure of the display substrate of this embodiment and its preparation process are merely exemplary. In some examples, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. In other examples, the fourth conductive layer can be omitted, and the data line 713 located in the third conductive layer can be directly extended to the first display area, avoiding the first pixel circuit by bending the line. In other examples, at least one transparent conductive connection layer can be provided between the fourth conductive layer and the anode layer, and multiple first conductive connection lines can be located in the same transparent conductive connection layer; or, multiple first conductive connection lines can be arranged in multiple different transparent conductive connection layers. In other examples, a shielding layer can be provided on the side of the semiconductor layer close to the substrate. This embodiment is not limited to this.

[0252] The preparation process of this exemplary embodiment can be realized by using currently mature preparation equipment and is well compatible with existing preparation processes. The process is simple to realize, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0253] The display substrate provided in this example can increase the pixel density of the first display area while ensuring light transmittance by setting a second light-emitting element in the first transmission area using an external pixel circuit, thereby achieving high PPI display.

[0254] FIG22 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in FIG22 , the first display area A1 may include: a plurality of island areas A13 disposed independently of one another, a plurality of transmissive areas (e.g., a plurality of first transmissive areas A14a and a plurality of second transmissive areas A14b), and a plurality of inter-island connecting areas (e.g., a plurality of first inter-island connecting areas A15a, a plurality of second inter-island connecting areas A15b, and a plurality of third inter-island connecting areas A15c).

[0255] In some examples, the first transmission region A14a is provided with a plurality of second light-emitting elements 12. The plurality of second light-emitting elements 12 can be connected to a plurality of second pixel circuits located in the second display region via a plurality of first conductive connection lines 31 extending along the second direction Y. The second transmission region A14b may not be provided with a light-emitting element or a pixel circuit.

[0256] In some examples, the plurality of first transmission regions A14a may be aligned along the second direction Y, and the first transmission regions A14a and the second transmission regions A14b may be spaced apart along the first direction X. The maximum length of the first transmission regions A14a along the second direction Y may be greater than the maximum length of the second transmission regions A14b along the second direction Y, and the maximum length of the first transmission regions A14a along the first direction X may be greater than the maximum length of the second transmission regions A14b along the first direction X.

[0257] In some examples, the third inter-island connection region A15c may be a zigzag region extending along the first direction X. The maximum length of the third inter-island connection region A15c along the second direction Y may be greater than the maximum length of the first inter-island connection region A15a along the second direction Y, and the maximum length of the third inter-island connection region A15c along the first direction X may be greater than the maximum length of the first inter-island connection region A15a along the first direction X. The third inter-island connection region A15c in this example may be formed by merging the traces of two or three adjacent first inter-island connection regions.

[0258] In this example, by placing the wiring between islands closer together, the size of the first transmission area can be increased, which is beneficial to improving the light transmittance of the first display area. The rest of the description of the display substrate of this example can be referred to the description of the previous embodiment, so it will not be repeated here.

[0259] FIG23 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in FIG23 , the first display area A1 may include: a plurality of island areas A13, a plurality of transmissive areas (e.g., a plurality of first transmissive areas A14a and a plurality of second transmissive areas A14b), and a plurality of inter-island connecting areas (e.g., a plurality of first inter-island connecting areas A15a, a plurality of second inter-island connecting areas A15b, and a plurality of third inter-island connecting areas A15c).

[0260] In some examples, the plurality of first conductive connection lines 31a and 31b connected to the plurality of second light-emitting elements 12 in the first transmission region A14a can extend along the second direction. For example, the second light-emitting element 12 near the third inter-island connection region A15c can be connected to the first conductive connection line 31a.

[0261] In some examples, the second light-emitting element 12 and the second pixel circuit can be connected in a manner of close to close, far to far. The second pixel circuit connected to the second light-emitting element 12 close to the second display area is located on the side of the second pixel circuit connected to the second light-emitting element 12 far from the second display area close to the first display area. In other words, the second pixel circuit connected to the second light-emitting element 12 close to the junction of the first display area and the second display area is close to the junction of the first display area and the second display area, and the second pixel circuit connected to the second light-emitting element 12 far from the junction of the first display area and the second display area is far from the junction of the first display area and the second display area. In other examples, the second light-emitting element 12 and the second pixel circuit can be connected in a manner of close to far, close to far. The second pixel circuit connected to the second light-emitting element 12 close to the second display area is located on the side of the second pixel circuit connected to the second light-emitting element 12 far from the second display area far from the first display area. For example, the second pixel circuits in the first to n-th rows of the second display area are arranged in a direction away from the junction of the first display area and the second display area. The second pixel circuit connected to the second light-emitting element closest to the junction of the first display area and the second display area can be located in the n-th row of second pixel circuits, and the second pixel circuit connected to the second light-emitting element farthest from the junction of the first display area and the second display area can be located in the first row of second pixel circuits. In this way, the lengths of the multiple first conductive connection lines connecting the multiple second light-emitting elements and the multiple second pixel circuits can be made consistent. The connection method of the second light-emitting elements and the second pixel circuits in this example is also applicable to the other embodiments.

[0262] In some examples, the first conductive connection line 31a can be made of a metal material. For example, the first conductive connection line 31a can be located in the shielding layer. The orthographic projection of the first conductive connection line 31a on the substrate can overlap with the portion of the third inter-island connection area A15c extending along the third direction or the fourth direction. The third direction can intersect both the first direction X and the second direction Y, the fourth direction can intersect both the first direction X and the second direction Y, and the third direction and the fourth direction can intersect. In other examples, the first conductive connection line 31a can be located in the first conductive layer, or the second conductive layer or other conductive layers. In other examples, the first conductive connection line 31a may include: a first connecting segment located in the third inter-island connection area A15c, a second connecting segment located in the transmission area (for example, the first transmission area A14a), the first connecting segment is connected to the second connecting segment, the first connecting segment can be made of a metal material, and the second connecting segment can be made of a transparent conductive material.

[0263] In some examples, the material of the first conductive connection line 31 b may include a transparent conductive material, for example, may be located in the first transparent conductive layer or the second transparent conductive layer.

[0264] The multiple first conductive connecting lines of this example are made of metal and transparent conductive materials, which can optimize the wiring arrangement space and help improve the light transmittance of the first display area. The remaining description of the display substrate of this example can be referred to the description of the previous embodiment, so it will not be repeated here.

[0265] FIG24 is another partial schematic diagram of the display area of ​​at least one embodiment of the present disclosure. FIG24 illustrates only the first conductive connecting lines 31 between the second light-emitting elements 12 and the second pixel circuits 22. Subsequent figures illustrate only some of the first conductive connecting lines as examples.

[0266] In some examples, as shown in FIG. 24 , the first display area A1 may include: a plurality of island areas A13 independently arranged from each other, a plurality of transmission areas (for example, including a plurality of first transmission areas A14a and a plurality of second transmission areas A14b), and a plurality of inter-island connection areas (for example, including a plurality of first inter-island connection areas A15a and a plurality of second inter-island connection areas A15b).

[0267] In some examples, the first transmission area A14a is provided with a plurality of second light-emitting elements 12, which can be connected to the plurality of second pixel circuits 22 in the second display area A2 via a plurality of first conductive connection lines 31 extending along the second direction Y. The second transmission area A14b is provided with no light-emitting elements or pixel circuits. The first transmission area A14a or the second transmission area A14b can be surrounded by four island areas A13, two first inter-island connecting areas A15a, and two second inter-island connecting areas A15b. The size of the second transmission area A14b can be smaller than that of the first transmission area A14a. For example, the maximum length of the first transmission area A14a along the first direction X can be greater than the maximum length of the second transmission area A14b along the first direction X, and the maximum length of the first transmission area A14a along the second direction Y can be greater than the maximum length of the second transmission area A14b along the second direction Y.

[0268] In some examples, the first transmission areas A14a and the second transmission areas A14b may be arranged at intervals along the first direction X and at intervals along the second direction Y. The arrangement of this example may help improve display uniformity.

[0269] In some examples, the first inter-island connection region A15a can be an arc-shaped region extending along the first direction X, connecting adjacent island regions A13 along the first direction X; the second inter-island connection region A15b can be an arc-shaped region extending along the second direction Y, connecting adjacent island regions A13 along the second direction Y. The traces within the first inter-island connection region A15a and the second inter-island connection region A15b can be arc-shaped to reduce diffraction. In other examples, the traces within the first inter-island connection region A15a and the second inter-island connection region A15b can be serpentine. The remaining description of the display substrate of this example can be referred to the description of the previous embodiment, and is not repeated here.

[0270] FIG25 is another partial schematic diagram of a display area according to at least one embodiment of the present disclosure. In some examples, as shown in FIG25 , the first display area A1 may include: a plurality of island areas A13, a plurality of transmissive areas A14, and a plurality of inter-island connecting areas (e.g., a plurality of first inter-island connecting areas A15a and a plurality of second inter-island connecting areas A15b) independently arranged from one another.

[0271] In some examples, the island area A13 may be provided with multiple first pixel circuits and multiple first light-emitting elements. The inter-island connection area may be provided with multiple second light-emitting elements 12. For example, both the first inter-island connection area A15a and the second inter-island connection area A15b may be provided with multiple second light-emitting elements 12. The multiple second light-emitting elements 12 may be connected to the multiple second pixel circuits 22 in the second display area A2 via multiple first conductive connection lines 31 extending along the second direction Y. The transmissive area A14 may not be provided with any light-emitting elements or pixel circuits. In other examples, the multiple second light-emitting elements may be provided in the first inter-island connection area A15a or the second inter-island connection area A15b.

[0272] In this example, the second light-emitting element, which is external to the pixel circuit, is placed in the inter-island connection area to prevent shading of the transmissive area, thereby improving the light transmittance of the first display area. The remaining description of the display substrate of this example can be referred to the description of the previous embodiment, so it will not be repeated here.

[0273] FIG26 is another partial schematic diagram of a display area according to at least one embodiment of the present disclosure. In some examples, as shown in FIG26 , the first display area A1 may include: a plurality of island areas A13 independently arranged from each other, a plurality of transmissive areas (e.g., a plurality of first transmissive areas A14a and a plurality of second transmissive areas A14b), and a plurality of inter-island connecting areas (e.g., a plurality of first inter-island connecting areas A15a and a plurality of second inter-island connecting areas A15b).

[0274] In some examples, the island area A13 may be provided with a plurality of first pixel circuits and a plurality of first light-emitting elements. The first transmission area A14a and the inter-island connection area may be provided with a plurality of second light-emitting elements 12. The second transmission area A14b may not be provided with light-emitting elements and pixel circuits. The plurality of second light-emitting elements 12 may be connected to the plurality of second pixel circuits 22 in the second display area A2 through a plurality of first conductive connecting lines 31 extending along the second direction Y, and may also be connected to the plurality of second pixel circuits 22 through a plurality of second conductive connecting lines (not shown) extending along the first direction X. In the second display area A2, along the second direction Y, a row of reserved pixel circuits may be arranged every m rows of in-situ pixel circuits 23, and at least one row of reserved pixel circuits may include a plurality of second pixel circuits 22; along the first direction X, a column of reserved pixel circuits may be arranged every n columns of in-situ pixel circuits, for example, n and m are both 2. In other examples, all transmission areas in the first display area A1 may be provided with second light-emitting elements.

[0275] In this example, multiple second light-emitting elements are placed outside the pixel circuit at the same time in the inter-island connection area and the first transmission area to achieve high PPI. The remaining description of the display substrate of this example can refer to the description of the previous embodiment, so it will not be repeated here.

[0276] Figure 27 is another partial schematic diagram of the display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 27, the first display area A1 can be in the shape of a runway hole extending along the first direction X. The first display area A1 can include: a display edge area A101 and a display middle area. The display edge area A101 surrounds the display middle area and is located between the display middle area and the second display area A2. The display middle area can include: a plurality of island areas A13 arranged independently of each other, a transmissive area A14 located between adjacent island areas, and an inter-island connecting area connecting adjacent island areas (for example, including a first inter-island connecting area A15a extending along the first direction X and a second inter-island connecting area A15b extending along the second direction Y).

[0277] In some examples, multiple island regions A13 are arranged in an array along the first direction X and the second direction Y. No light-emitting elements or pixel circuits are provided in the transmissive region A14. The first inter-island connection region A15a may be a straight strip region extending along the first direction X, and the second inter-island connection region A15b may be a straight strip region extending along the second direction Y.

[0278] In some examples, multiple second light-emitting elements 12 can be located in the display edge area A101. The second light-emitting elements 12 in the display edge area A101 extending along the first direction X can be connected to the second pixel circuits 22 in the second display area A2 via first conductive connecting lines 31. The second light-emitting elements 12 in the display edge area A101 extending along the second direction Y can be connected to the second pixel circuits 22 in the second display area A2 via second conductive connecting lines. Within the second display area A2, along the second direction Y, a row of reserved pixel circuits can be arranged every m rows of in-situ pixel circuits 23, and at least one row of reserved pixel circuits can include multiple second pixel circuits 22. Along the first direction X, a column of reserved pixel circuits can be arranged every n columns of in-situ pixel circuits, for example, where n and m are both 2.

[0279] In this example, a second light-emitting element external to the pixel circuit is positioned in the display edge region. A second conductive connection line extending along a first direction and a first conductive connection line extending along a second direction are combined to achieve electrical connection between the second light-emitting element and the second pixel circuit, which can help reduce the length of the conductive connection lines. The remaining description of the display substrate of this example can be found in the description of the previous embodiment and will not be repeated here.

[0280] Figure 28 is another partial schematic diagram of the display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 28, the first display area A1 is in the shape of a runway hole extending along the first direction X. The first display area A1 may include: a plurality of island areas A13 arranged independently of each other, a transmissive area located between adjacent island areas (for example, including a first transmissive area A14a and a plurality of second transmissive areas A14b), and an inter-island connecting area connecting adjacent island areas (for example, including a first inter-island connecting area A15a extending along the first direction X and a second inter-island connecting area A15b extending along the second direction Y).

[0281] In some examples, the first transmission area A14a can be located at the center of the first display area A1. A plurality of second light-emitting elements 12 are disposed in the first transmission area A14a. No pixel circuits or light-emitting elements are disposed in the second transmission area A14b. The size of the first transmission area A14a can be larger than the size of the second transmission area A14b. For example, the maximum length of the first transmission area A14a along the first direction X can be larger than the maximum length of the second transmission area A14b along the first direction X, and the maximum length of the first transmission area A14a along the second direction Y can be larger than the maximum length of the second transmission area A14b along the second direction Y.

[0282] In this example, the second light-emitting element external to the pixel circuit is disposed in the first transmission area at the center of the first display area, which can help optimize the wiring space. The remaining description of the display substrate of this example can refer to the description of the previous embodiment, so it is not repeated here.

[0283] Figure 29 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 29 , the display area AA may include a first display area A1 and a second display area A2 disposed around the first display area A1. The first display area A1 may have an elliptical shape. The maximum length of the first display area A1 along the first direction X may be greater than the maximum length along the second direction Y. The arrangement of the plurality of first pixel circuits, the plurality of first light-emitting elements, and the plurality of second light-emitting elements within the first display area A1 can be described in the same manner as described in the previous embodiments, and will not be further elaborated here.

[0284] Figure 30 is another partial schematic diagram of the display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 30, the first display area A1 is in the shape of a circular hole. For example, the maximum length of the first display area A1 along the first direction X and the maximum length along the second direction Y can be the same. The first display area A1 may include: a plurality of island areas A13 arranged independently of each other; a transmissive area located between adjacent island areas (for example, including a first transmissive area A14a and a plurality of second transmissive areas A14b); and an inter-island connecting area connecting adjacent island areas (for example, including a first inter-island connecting area extending along the first direction X and a second inter-island connecting area extending along the second direction Y).

[0285] In some examples, the first transmission area A14a can be located at the center of the first display area A1. For example, the maximum length of the first transmission area A14a along the first direction X can be greater than its maximum length along the second direction Y. The first transmission area A14a is provided with a plurality of second light-emitting elements 12. The second transmission area A14b is not provided with pixel circuits or light-emitting elements. The size of the first transmission area A14a can be greater than the size of the second transmission area A14b. For example, the maximum length of the first transmission area A14a along the first direction X can be greater than the maximum length of the second transmission area A14b along the first direction X, and the maximum length of the first transmission area A14a along the second direction Y can be greater than the maximum length of the second transmission area A14b along the second direction Y.

[0286] In some examples, within the second display area A2, a row of reserved pixel circuits can be arranged every m rows of in-situ pixel circuits 23 along the second direction Y, and at least one row of reserved pixel circuits can include multiple second pixel circuits 22. Along the first direction X, a column of reserved pixel circuits can be arranged every n columns of in-situ pixel circuits, for example, n and m can be the same. The multiple second light-emitting elements 12 can be connected to the multiple second pixel circuits 22 via multiple first conductive connection lines 31 extending along the second direction Y and multiple second conductive connection lines (not shown) extending along the first direction X.

[0287] In this example, the second light-emitting element, which is external to the pixel circuit, is placed in the first transmission area at the center of the circular hole-shaped first display area, which can help optimize wiring space. The remaining description of the display substrate of this example can be referred to the description of the previous embodiment, so it will not be repeated here.

[0288] Figure 31 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 32 is another partial schematic diagram of a display region according to at least one embodiment of the present disclosure.

[0289] In some examples, as shown in Figures 31 and 32, the display area AA may include four first display areas A1a, A1b, A1c, and A1d, and a second display area A2 arranged around the multiple first display areas. The first display areas A1a, A1b, A1c, and A1d may have the same shape, such as a circle. The four first display areas A1a, A1b, A1c, and A1d may be located in the top center area of ​​the display area AA. The four first display areas A1a, A1b, A1c, and A1d may be interconnected and arranged in two rows, with the two rows of first display areas staggered along a first direction X. For example, the first display areas A1a and A1b are adjacent and aligned along the first direction X, the first display areas A1c and A1d are adjacent and aligned along the first direction X, the first display areas A1a and A1c are staggered along the second direction Y, and the first display areas A1b and A1d are staggered along the second direction Y. Center points of the first display areas A1a, A1b, and A1c may be connected to form an equilateral triangle, and center points of the first display areas A1c, A1b, and A1d may be connected to form an equilateral triangle.

[0290] In some examples, at least one first display area may be provided with a plurality of first light-emitting elements 11, a plurality of first pixel circuits 21, and a plurality of second light-emitting elements 12. For example, a first display area A1a may include a first region A1a-1 and a second region A1a-2 arranged along a first direction X, wherein the first region A1a-1 is adjacent to the second display area A2 in the first direction X, and the second region A1a-2 is adjacent to another first display area A1b in the first direction X. The second light-emitting elements 12 within the first display area A1a may be located on at least one side of the first light-emitting element 11 that is adjacent to the second display area A2. For example, the second region A1a-2 of the first display area A1a may be provided with a plurality of first pixel circuits 21 and a plurality of first light-emitting elements 11, and the first region A1a-1 may be provided with a plurality of second light-emitting elements 12. The second region A1d-2 of the first display area A1d may be provided with a plurality of first pixel circuits 21 and a plurality of first light-emitting elements 11, and the first region A1d-1 may be provided with a plurality of second light-emitting elements 12. The second light emitting elements 12 can be connected to the second pixel circuits 22 of the second display area A2 through the first conductive connection lines 31 extending along the second direction Y. The first display areas A1b and A1c can be provided with the first light emitting elements 11 and the first pixel circuits 21 .

[0291] In some examples, the second signal lines extending along the second direction Y may include multiple data lines, and the multiple data lines may include: multiple first data lines DL1, multiple second data lines DL2, and multiple third data lines DL3. The multiple third data lines DL3 are located in the second display area A2. The multiple first data lines DL1 are separated by one first display area (for example, by the first display area A1a or A1d). The multiple second data lines DL2 pass through two first display areas, for example, through the alignment area of ​​the first display areas A1a and A1c along the second direction Y, or through the alignment area of ​​the first display areas A1b and A1c along the second direction Y, or through the alignment area of ​​the first display areas A1b and A1d along the second direction Y. The multiple first data lines DL1 can be arranged by winding from the edge of the first display area, for example, from the side of the first display area A1a away from the first display area A1b, or from the side of the first display area A1d away from the first display area A1c. The plurality of second data lines DL2 may be connected to the plurality of first pixel circuits 21 arranged along the second direction Y and disposed in the aligned regions of the two first display areas.

[0292] In this example, multiple first data lines DL1 are routed around the first display area using a winding method. This increases the routing length of the first data lines DL1 and their resistance. Multiple second data lines DL2 are connected in series with the first pixel circuits and pass through the first display area. The second data lines DL2 are connected to multiple first pixel circuits, which also increases their resistance. This helps reduce the load differences between the multiple first data lines and the multiple second data lines, making the resistance of different data lines more consistent. The remaining description of the display substrate of this example can be referred to the description of the previous embodiment and is not repeated here.

[0293] Figure 33 is another schematic diagram of the arrangement of multiple second light-emitting elements in the second sub-area of ​​the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 33, the multiple second light-emitting elements 12 in the first display area may include: multiple second light-emitting elements 12a emitting first color light, multiple second light-emitting elements 12b emitting second color light, and multiple second light-emitting elements 12c and 12d emitting third color light. A pixel unit in the second sub-area may include: one second light-emitting element 12a emitting first color light, one second light-emitting element 12b emitting second color light, and two second light-emitting elements 12c and 12d emitting third color light. For example, the first color light may be red light, the second color light may be blue light, and the third color light may be green light.

[0294] In some examples, a plurality of second light-emitting elements 12a emitting first color light and a plurality of second light-emitting elements 12b emitting second color light may be arranged at intervals along the first direction X and at intervals along the second direction Y; a plurality of second light-emitting elements 12c and 12d emitting third color light may be arranged at intervals along the first direction X and at intervals along the second direction Y. The second light-emitting elements 12a and 12b may be staggered with the second light-emitting elements 12c and 12d in the first direction X, and the second light-emitting elements 12a and 12b may be staggered with the second light-emitting elements 12c and 12d in the second direction Y.

[0295] In some examples, the orthographic projections of the light-emitting regions of the second light-emitting elements 12a, 12b, 12c, and 12d onto the substrate can be substantially circular. The light-emitting region of a single second light-emitting element 12a can be smaller than the light-emitting region of a single second light-emitting element 12b, and the light-emitting region of a single second light-emitting element 12c or 12d can be smaller than the light-emitting region of a single second light-emitting element 12a. The light-emitting region of a single second light-emitting element 12c can be the same as the light-emitting region of a single second light-emitting element 12d.

[0296] In this example, the arrangement of the multiple first light-emitting elements in the first sub-area and the arrangement of the multiple third light-emitting elements in the second display area can refer to the arrangement of the multiple second light-emitting elements in the second sub-area, so they are not repeated here.

[0297] Figure 34 is another partial schematic diagram of a display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 34, the display area AA may include four first display areas A1a, A1b, A1c, and A1d. At least one first display area may be provided with a plurality of first light-emitting elements 11, a plurality of first pixel circuits 21, and a plurality of second light-emitting elements 12. For example, the first display area A1a may include a first area A1a-1 and a second area A1a-2 arranged along a first direction X, wherein the first area A1a-1 is adjacent to the second display area A2 in the first direction X, and the second area A1a-2 is adjacent to another first display area A1b in the first direction X. The second area A1a-2 of the first display area A1a can be provided with multiple first pixel circuits 21 and multiple first light-emitting elements 11, and the first area A1a-1 can be provided with multiple second light-emitting elements 12; the second area A1b-2 of the first display area A1b can be provided with multiple first pixel circuits 21 and multiple first light-emitting elements 11, and the first area A1b-1 can be provided with multiple second light-emitting elements 12; the middle area of ​​the first display area A1c along the first direction X can be provided with multiple second light-emitting elements 12, and the two side areas along the first direction X can be provided with multiple first light-emitting elements 11 and multiple first pixel circuits 21; the first display area A1d can be provided with multiple first pixel circuits 21 and multiple first light-emitting elements 11.

[0298] In some examples, the plurality of second light emitting elements 12 may be connected to the plurality of second pixel circuits 22 of the second display area A2 via a plurality of first conductive connection lines 31 extending along the second direction Y.

[0299] In some examples, the second signal lines extending along the second direction Y may include multiple data lines, and the multiple data lines may include: multiple first data lines DL1, multiple second data lines DL2, and multiple third data lines DL3. The multiple third data lines DL3 are located in the second display area A2. The multiple first data lines DL1 are separated by a first display area (for example, by the first display area A1a, A1b, or A1c). The multiple second data lines DL2 pass through at least one first display area, for example, through the alignment area of ​​the first display areas A1a and A1c along the second direction Y, or through the alignment area of ​​the first display areas A1b and A1c along the second direction Y, or through the first display area A1d. The multiple first data lines DL1 can be arranged by winding around an edge of the first display area, for example, from the side of the first display area A1a away from the first display area A1b, or from the side of the first display area A1b away from the first display area A1a, or from the side of the first display area A1c away from the first display area A1d. The first data lines DL1 that are routed from the first display area A1b away from the side of the first display area A1a can be connected to the multiple first pixel circuits 21 arranged along the second direction Y in the first display area A1d. The multiple second data lines DL2 can be connected to the multiple first pixel circuits 21 arranged along the second direction Y in at least one first display area. For example, the multiple second data lines DL2 can be connected to the multiple first pixel circuits 21 within the alignment area of ​​the first display areas A1a and A1c along the second direction Y, or can be connected to the multiple first pixel circuits 21 within the alignment area of ​​the first display areas A1b and A1c along the second direction Y, or can be connected to the multiple first pixel circuits 21 arranged along the second direction Y in the first display area A1d.

[0300] In this example, multiple first data lines DL1 are routed around the first display area using a winding method, or a combination of winding and connection to first pixel circuits, thereby increasing the resistance of the first data lines DL1. Multiple second data lines DL2 are routed through the first display area using a series connection to the first pixel circuits. The second data lines DL2 are connected to the multiple first pixel circuits, increasing their resistance. This helps reduce the load differences between the multiple first data lines and the multiple second data lines, making the resistance of the different data lines more consistent. The remaining description of the display substrate of this example can be found in the description of the previous embodiment, and is therefore not repeated here.

[0301] In other examples, each first display area may be provided with a plurality of first light-emitting elements, a plurality of first pixel circuits, and a plurality of second light-emitting elements. The arrangement positions of the first light-emitting elements and the second light-emitting elements in the first display area may be set based on the shortest data line winding. This embodiment is not limited to this.

[0302] Figure 35 is another partial schematic diagram of the display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 35, the display area may include three first display areas A1a, A1b, and A1c. The shapes of the first display areas A1a, A1b, and A1c can be the same, for example, circular. The three first display areas A1a, A1b, and A1c can be located in the top middle area of ​​the display area AA. The three first display areas A1a, A1b, and A1c can be connected to each other. For example, the first display areas A1a and A1b are adjacent and aligned along the first direction X, and the first display area A1c is located below the first display areas A1a and A1b along the second direction Y and is staggered with the first display areas A1a and A1b along the second direction Y. The center points of the first display areas A1a, A1b, and A1c can be connected to form an equilateral triangle.

[0303] In some examples, each of the three first display areas is provided with a plurality of first light-emitting elements 11, a plurality of first pixel circuits 21, and a plurality of second light-emitting elements 12. For example, the first display area A1a may include a first region A1a-1 and a second region A1a-2 arranged along a first direction X, wherein the first region A1a-1 is adjacent to the second display area A2 in the first direction X, and the second region A1a-2 is adjacent to another first display area A1b in the first direction X. The second region A1a-2 of the first display area A1a may be provided with a plurality of first pixel circuits 21 and a plurality of first light-emitting elements 11, and the first region A1a-1 may be provided with a plurality of second light-emitting elements 12. The second region A1b-2 of the first display area A1b may be provided with a plurality of first pixel circuits 21 and a plurality of first light-emitting elements 11, and the first region A1b-1 may be provided with a plurality of second light-emitting elements 12. The middle region of the first display area A1c along the first direction X may be provided with a plurality of second light-emitting elements 12, and the regions on both sides along the first direction X may be provided with a plurality of first light-emitting elements and a plurality of first pixel circuits 21.

[0304] In some examples, the plurality of second light emitting elements 12 may be connected to the plurality of second pixel circuits 22 of the second display area A2 via a plurality of first conductive connection lines 31 extending along the second direction Y.

[0305] In some examples, the second signal lines extending along the second direction Y may include multiple data lines, and the multiple data lines may include: multiple first data lines DL1, multiple second data lines DL2, and multiple third data lines DL3. The multiple third data lines DL3 are located in the second display area A2. The multiple first data lines DL1 are separated by a first display area (for example, separated by the first display area A1a, A1b, or A1c). The multiple second data lines DL2 pass through two first display areas, for example, through the alignment area of ​​the first display areas A1a and A1c along the second direction Y, or through the alignment area of ​​the first display areas A1b and A1c along the second direction Y. The multiple first data lines DL1 can be arranged by winding from an edge of a first display area, for example, from the side of the first display area A1a away from the first display area A1b, or from the side of the first display area A1b away from the first display area A1a, or from the side of the first display area A1c. The plurality of second data lines DL2 may be connected to the plurality of first pixel circuits 21 arranged in the two first display areas along the second direction Y. For example, the plurality of second data lines DL2 may be connected to the plurality of first pixel circuits 21 in an area where the first display areas A1a and A1c are aligned along the second direction Y, or may be connected to the plurality of first pixel circuits 21 in an area where the first display areas A1b and A1c are aligned along the second direction Y.

[0306] In this example, multiple first data lines DL1 are routed around the first display area using a winding method, increasing the resistance of the first data lines DL1. Multiple second data lines DL2 are connected in series with the first pixel circuits and pass through the first display area. The second data lines DL2 are connected to the multiple first pixel circuits, increasing their resistance. This helps reduce the load differences between the multiple first data lines and the multiple second data lines, making the resistance of the different data lines more consistent. The remaining description of the display substrate of this example can be referred to the description of the previous embodiment, and is not repeated here.

[0307] Figure 36 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 36, the display area may include three first display areas A1a, A1b, and A1c. The first display areas A1a, A1b, and A1c may have the same shape, such as a circle. The three first display areas A1a, A1b, and A1c may be located in the top middle area of ​​the display area AA. The three first display areas A1a, A1b, and A1c may be connected to each other. For example, the first display areas A1a and A1b may be adjacent and aligned along a first direction X, and the first display area A1c may be located above the first display areas A1a and A1b along a second direction Y and may be offset from the first display areas A1a and A1b along the second direction Y. The center points of the first display areas A1a, A1b, and A1c may be connected to form an equilateral triangle.

[0308] In this example, multiple first light-emitting elements, multiple first pixel circuits, and multiple second light-emitting elements can be set in each of the three first display areas. The arrangement of the pixel circuits and light-emitting elements in the three first display areas can refer to the description of the previous embodiment, so it will not be repeated here.

[0309] FIG37 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG37 , the display area AA may include: a plurality of first display areas (e.g., three first display areas A1a, A1b, and A1c) arranged along a second direction Y. The three first display areas A1a, A1b, and A1c may be aligned and arranged along the second direction Y. The three first display areas A1a, A1b, and A1c may have the same shape, for example, each being circular. Each first display area may be provided with a plurality of first light-emitting elements, a plurality of first pixel circuits, and a plurality of second light-emitting elements. Within each first display area, the plurality of second light-emitting elements may be located on either side of the plurality of first light-emitting elements along the first direction X to reduce the length of the conductive connection lines between the second light-emitting elements and the second pixel circuits of the second display area. Furthermore, second signal lines (e.g., including data lines) extending along the second direction Y may pass through the first display area by bypassing the first display area or by being connected in series with the first pixel circuits of the first display area. This allows the increased resistance of the data lines to be uniform, thereby reducing the load differences between different data lines. The rest of the description about the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0310] Figure 38 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 38, the display area AA may include: multiple first display areas (e.g., three first display areas A1a, A1b, and A1c) arranged along a first direction X. The three first display areas A1a, A1b, and A1c may be aligned along the first direction X. The three first display areas A1a, A1b, and A1c may have the same shape, for example, all circular. For example, the first display area A1b may be provided with multiple second light-emitting elements, and the first display areas A1a and A1c may be provided with multiple first light-emitting elements and multiple first pixel circuits. The multiple second light-emitting elements may be connected to the multiple second pixel circuits in the second display area via first conductive connecting lines extending along the second direction. This arrangement can reduce the number of second signal lines (e.g., including data lines) extending along the second direction Y. The second signal lines (e.g., including data lines) may pass through the first display area by bypassing the first display area or by being connected in series with the first pixel circuits in the first display area, thereby making the added resistance of the data lines more consistent, thereby reducing the load differences between different data lines. The rest of the description about the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0311] Figure 39 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 39 , a gate drive circuit is provided in the second peripheral region. For example, the gate drive circuit may include: a plurality of first drive units GOA1 located in, for example, the left border region B3 and the right border region B4. For example, the gate drive circuit may be configured to provide a first scan signal or a second scan signal. A first drive unit GOA1 in the left border region B3 and a first drive unit GOA1 in the right border region B4 may provide gate signals to the same row of pixel circuits, thereby achieving bilateral drive of the pixel circuits.

[0312] In some examples, the two ends of the gate line GLa connected to a row of in-situ pixel circuits 23 in the display area are respectively connected to the first drive unit GOA1 in the left frame B3 and the first drive circuit GOA1 in the right frame B4. The gate line GLb connected to the multiple second pixel circuits 22 in a row of reserved pixel circuits in the display area is connected to the gate signal transfer line 251; the gate signal transfer line 251 extends along the second direction Y and is connected to the gate line GLc connected to the first pixel circuit 21 connected to the first light-emitting element 12 in the same row as the second pixel circuit 22, so that the first pixel circuit 21 connected to the first light-emitting element and the second pixel circuit connected to the second light-emitting element 12 in the same row receive the same gate signal. The multiple invalid pixel circuits 24 in a row of reserved pixel circuits can be connected to the invalid gate line, and the invalid gate line can be not connected to the gate line GLb connected to the multiple second pixel circuits 22 in the reserved pixel circuit in the row.

[0313] In this example, the gate line connected to the second pixel circuit is connected to the gate line connected to the corresponding first pixel circuit via a gate signal adapter line, which can reduce the number of required driving units. The remaining description of the display substrate of this example can refer to the description of the previous embodiment, so it is not repeated here.

[0314] Figure 40 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 40 , a gate drive circuit is provided in the second peripheral region, for example, in the left border region B3 and the right border region B4. The gate drive circuit can be configured to provide a first scan signal or a second scan signal.

[0315] In some examples, the gate drive circuit may include: multiple first drive units GOA1 and multiple second drive units GOA2. The first drive unit GOA1 can provide gate signals to the first pixel circuits 21 and the in-situ pixel circuits 23 in the display area, and the second drive unit GOA2 can provide gate signals to the multiple second pixel circuits 22 in the display area. For example, a row of in-situ pixel circuits or the in-situ pixel circuits 23 and the first pixel circuits 21 in the same row are driven by the first drive unit GOA1, and a row of reserved pixel circuits are driven by the second drive unit GOA2.

[0316] This example drives the pixel circuits in the display area by providing two sets of drive units (a first drive unit and a second drive unit), thereby reducing the number of patch cords in the display area. The remaining description of the display substrate in this example can be found in the description of the previous embodiment and will not be repeated here.

[0317] This embodiment also provides a display substrate, comprising: a plurality of first display areas and a second display area located on at least one side of the plurality of first display areas; the plurality of first display areas are arranged staggered along a first direction or a second direction. The display substrate comprises: a substrate, a plurality of pixel circuits disposed on the substrate, and a plurality of light-emitting elements. The plurality of pixel circuits comprises a plurality of first pixel circuits located in at least one first display area among the plurality of first display areas, and a plurality of reserved pixel circuits and a plurality of in-situ pixel circuits located in the second display area; the plurality of reserved pixel circuits comprises a plurality of second pixel circuits; in the second display area, the plurality of reserved pixel circuits arranged along the first direction constitute a row of reserved pixel circuits, the plurality of in-situ pixel circuits arranged along the first direction constitute a row of in-situ pixel circuits, and along the second direction, a row of reserved pixel circuits is arranged every m rows of in-situ pixel circuits, where m is an integer greater than 1. The plurality of light-emitting elements comprises: a plurality of first light-emitting elements and a plurality of second light-emitting elements located in the at least one first display area, and a plurality of third light-emitting elements located in the second display area. The at least one first display area includes a first region and a second region arranged along the first direction, the first region being adjacent to the second display area in the first direction, and the second region being adjacent to another first display area in the first direction. The plurality of second light-emitting elements are located in the first region, and the plurality of first pixel circuits and the plurality of first light-emitting elements are located in the second region. At least one first pixel circuit among the plurality of first pixel circuits is connected to at least one first light-emitting element among the plurality of first light-emitting elements, and the orthographic projection of the at least one first pixel circuit on the substrate at least partially overlaps with the orthographic projection of the at least one first light-emitting element to which it is connected. At least one second pixel circuit among the plurality of second pixel circuits is connected to at least one second light-emitting element among the plurality of second light-emitting elements via at least one first conductive connecting line extending along the second direction, and the orthographic projection of the at least one second pixel circuit on the substrate does not overlap with the orthographic projection of the at least one second light-emitting element to which it is connected. At least one in-situ pixel circuit among the plurality of in-situ pixel circuits is connected to at least one third light-emitting element among the plurality of third light-emitting elements, and the orthographic projection of the at least one in-situ pixel circuit on the substrate at least partially overlaps with the orthographic projection of the at least one third light-emitting element to which it is connected.

[0318] The display substrate of this embodiment combines both external and internal pixel circuits in the first display area, ensuring light transmittance in the first display area while also allowing for increased size. For example, this example can be adapted to the design requirements of multiple under-screen camera areas.

[0319] In some exemplary embodiments, the display substrate includes three first display areas, two of which are aligned along a first direction, and a third first display area is located on the same side of the two first display areas along a second direction. Each first display area is provided with a plurality of first light-emitting elements, a plurality of second light-emitting elements, and a plurality of first pixel circuits. Within two first display areas located in the same row, the plurality of second light-emitting elements are located in a first region of the first display area along the first direction, and the plurality of first pixel circuits and the plurality of first light-emitting elements are located in a second region of the first display area along the first direction. Within the third first display area, the plurality of second light-emitting elements are located between the plurality of first light-emitting elements along the first direction.

[0320] In some exemplary embodiments, the display substrate includes: four first display areas, the four first display areas are arranged in two rows, and the two rows of first display areas are staggered along the first direction; two first display areas in at least one row are each provided with a plurality of first light-emitting elements, a plurality of second light-emitting elements and a plurality of first pixel circuits; or, one first display area in one row is provided with a plurality of first light-emitting elements, a plurality of second light-emitting elements and a plurality of first pixel circuits.

[0321] The remaining structures of the display substrate of this example can be referred to the description of the aforementioned embodiment, and thus will not be described again here.

[0322] Figure 41 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 41 , this embodiment provides a display device comprising: a display substrate 91; and a sensor 50 located on a light-emitting side of a light-emitting structure layer, away from the display substrate 91. The sensor 50 can be located on the non-display side of the display substrate 91. The orthographic projection of the sensor 50 on the display substrate 91 can at least partially overlap with the orthographic projection of the first display area A1 on the display substrate 91. For example, the orthographic projection of the sensor 50 on the display substrate 91 can be located within the orthographic projection of the first display area A1 on the display substrate 91.

[0323] In some examples, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function. For example, the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as business query equipment for e-government, banks, hospitals, power departments, etc.), a monitor, and the like. For another example, the display device may also be a microdisplay, a VR device or an AR device containing a microdisplay, and the like.

[0324] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be noted that the above-mentioned embodiments or implementation methods are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents shown and described in detail herein. Various modifications, replacements or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A display substrate, comprising: at least one first display area and a second display area located at least on one side of the first display area; The maximum length of the first display area along a first direction is different from the maximum length along a second direction, and the first direction intersects the second direction; The display substrate comprises: substrate; A plurality of pixel circuits are arranged on the substrate, including: a plurality of first pixel circuits located in the first display area, and a plurality of reserved pixel circuits and a plurality of in-situ pixel circuits located in the second display area; the plurality of reserved pixel circuits include a plurality of second pixel circuits; in the second display area, the plurality of reserved pixel circuits arranged along the first direction form a row of reserved pixel circuits, the plurality of in-situ pixel circuits arranged along the first direction form a row of in-situ pixel circuits, and along the second direction, a row of reserved pixel circuits is arranged every m rows of in-situ pixel circuits, where m is an integer greater than 1; A plurality of light emitting elements, arranged on the substrate, including: a plurality of first light emitting elements and a plurality of second light emitting elements located in the first display area, and a plurality of third light emitting elements located in the second display area; At least one first pixel circuit among the plurality of first pixel circuits is connected to at least one first light-emitting element among the plurality of first light-emitting elements, and an orthographic projection of the at least one first pixel circuit on the substrate at least partially overlaps with an orthographic projection of the at least one first light-emitting element connected thereto on the substrate; At least one second pixel circuit among the plurality of second pixel circuits is connected to at least one second light-emitting element among the plurality of second light-emitting elements through at least one first conductive connection line extending along the second direction, and an orthographic projection of the at least one second pixel circuit on the substrate does not overlap with an orthographic projection of the at least one second light-emitting element connected thereto on the substrate; At least one of the multiple in-situ pixel circuits is connected to at least one of the multiple third light-emitting elements, and the orthographic projection of the at least one in-situ pixel circuit on the substrate at least partially overlaps with the orthographic projection of the connected at least one third light-emitting element on the substrate.

2. The display substrate according to claim 1, wherein: The maximum length of the first display area along the first direction is greater than the maximum length along the second direction; The first display area includes: a+1 first sub-areas and a second sub-areas; the a+1 first sub-areas and the a second sub-areas are arranged at intervals along the first direction, and a is an integer greater than 0; in the first direction, at least one of the first sub-areas is arranged between the second sub-area and the second display area; The first sub-area is provided with the plurality of first pixel circuits and the plurality of first light-emitting elements, and the second sub-area is provided with the plurality of second light-emitting elements.

3. The display substrate according to claim 2, further comprising: A plurality of data lines are connected to the plurality of pixel circuits and configured to provide data signals to the plurality of pixel circuits, the plurality of data lines are arranged along the first direction and extend along the second direction; the plurality of data lines include: a plurality of first data lines, a plurality of second data lines and a plurality of third data lines, the plurality of first data lines are separated by the first display area and bypass the second sub-area from both sides of the second sub-area along the first direction, the plurality of second data lines are connected to the plurality of first pixel circuits of the first sub-area, and the plurality of third data lines are located in the second display area.

4. The display substrate according to claim 2, wherein: a is 1 or 3.

5. The display substrate according to claim 1, wherein: The maximum length of the first display area along the second direction is greater than the maximum length along the first direction; The first display area includes: b first sub-areas and b+1 second sub-areas; the b first sub-areas and the b+1 second sub-areas are arranged at intervals along the second direction, where b is an integer greater than 0; in the second direction, at least one second sub-area is arranged between the first sub-area and the second display area; The first sub-area is provided with the plurality of first pixel circuits and the plurality of first light-emitting elements, and the second sub-area is provided with the plurality of second light-emitting elements.

6. The display substrate according to claim 5, wherein: In the second display area, a plurality of reserved pixel circuits sequentially arranged along the second direction is a column of reserved pixel circuits, a plurality of in-situ pixel circuits sequentially arranged along the second direction is a column of in-situ pixel circuits, and along the first direction, a column of reserved pixel circuits is arranged every n columns of in-situ pixel circuits, where n is an integer greater than 1; A plurality of second light-emitting elements arranged in a second sub-area between the second display area and the first sub-area in the second direction are connected to a plurality of second pixel circuits in the second display area through a plurality of first conductive connection lines; A plurality of second light-emitting elements arranged in the second sub-area between two adjacent first sub-areas in the second direction are connected to a plurality of second pixel circuits in the second display area through a plurality of second conductive connecting lines extending along the first direction.

7. The display substrate according to claim 1, wherein: The first display area includes: a plurality of island areas, a transmission area located between adjacent island areas, and an inter-island connection area connecting adjacent island areas; the light transmittance of the transmission area is greater than the light transmittance of the island area; The island area is provided with the plurality of first pixel circuits and the plurality of first light emitting elements; The first display area satisfies at least one of the following conditions: the transmission area is provided with the plurality of second light-emitting elements; and the inter-island connection area is provided with the plurality of second light-emitting elements.

8. The display substrate according to claim 7, wherein: The first display area includes a plurality of transmission areas, the plurality of transmission areas include: at least one first transmission area and a plurality of second transmission areas, the first transmission area is provided with the plurality of second light emitting elements; the light transmittance of the second transmission area is greater than the light transmittance of the first transmission area; the second transmission area and the first transmission area are arranged at intervals along the first direction or the second direction; The first display area satisfies at least one of the following: The maximum length of the first transmission area along the first direction is greater than the maximum length of the second transmission area along the first direction; The maximum length of the first transmission area along the first direction is equal to the maximum length of the second transmission area along the first direction; The maximum length of the first transmission area along the second direction is greater than the maximum length of the second transmission area along the second direction; A maximum length of the first transmission region along the second direction is equal to a maximum length of the second transmission region along the second direction.

9. The display substrate according to claim 8, further comprising: A shielding layer located in the first display area, wherein the shielding layer is located on a side of the plurality of first pixel circuits close to the substrate; The orthographic projection of the shielding layer on the substrate covers the orthographic projections of the plurality of island regions, the plurality of inter-island connecting regions, and the plurality of second light-emitting elements in the first transmission region on the substrate.

10. The display substrate according to claim 9, wherein: The at least one first conductive connection line is arranged in the same layer as the shielding layer.

11. The display substrate according to claim 8, wherein: The first transmission area is located in a central area of ​​the first display area, and a maximum length of the first transmission area along the first direction is greater than a maximum length of the first transmission area along the second direction.

12. The display substrate according to claim 8, wherein: The first display area includes a plurality of inter-island connection areas, the plurality of inter-island connection areas include a plurality of first inter-island connection areas, a plurality of second inter-island connection areas, and a plurality of third inter-island connection areas; the plurality of first inter-island connection areas and the plurality of third inter-island connection areas extend along the first direction, and the plurality of second inter-island connection areas extend along the second direction; the first inter-island connection areas are adjacent to the second transmission areas along the second direction, and the third inter-island connection areas are adjacent to the first transmission areas along the second direction; A maximum length of the third inter-island connecting region along the first direction is greater than a maximum length of the first inter-island connecting region along the first direction.

13. The display substrate according to claim 12, wherein: A maximum length of the third inter-island connecting region along the second direction is greater than or equal to a maximum length of the first inter-island connecting region along the second direction.

14. The display substrate according to claim 7, wherein: The minimum distance between the second light emitting element located in the transmission area and the substrate is less than or equal to the minimum distance between the first light emitting element located in the island area and the substrate.

15. The display substrate according to claim 7, wherein: The inter-island connection area is provided with a plurality of routing lines, and the plurality of routing lines are straight line segments extending along the first direction or the second direction, or arc line segments extending along the first direction or the second direction.

16. The display substrate according to claim 1, wherein: The first display area includes: a display edge area and a display middle area, the display edge area surrounds the display middle area, and the display middle area includes: a plurality of island areas, a transmission area located between adjacent island areas, and an inter-island connection area connecting adjacent island areas; The plurality of second light emitting elements are located in the display edge area.

17. The display substrate according to claim 1, comprising: a plurality of first display areas, at least one of the plurality of first display areas being provided with the plurality of first pixel circuits, the plurality of first light-emitting elements, and the plurality of second light-emitting elements; The plurality of first display areas are arranged in a staggered manner along the first direction or in a staggered manner along the second direction.

18. The display substrate according to claim 1, further comprising: a peripheral region located on at least one side of the second display area, the peripheral region comprising: a first peripheral region located on one side of the second display area along the second direction and a second peripheral region located on the remaining sides of the second display area; The display substrate further includes: a gate driving circuit located in the second peripheral area, the gate driving circuit including a plurality of first driving units; the plurality of first driving units are configured to provide gate signals to a plurality of rows of in-situ pixel circuits and a plurality of rows of reserved pixel circuits.

19. The display substrate according to claim 1, further comprising: a peripheral region located on at least one side of the second display area, the peripheral region comprising: a first peripheral region located on one side of the second display area along the second direction and a second peripheral region located on the remaining sides of the second display area; The display substrate also includes: a gate driving circuit located in the second peripheral area, the gate driving circuit includes: a plurality of first driving units and a plurality of second driving units, the plurality of first driving units are configured to provide gate signals to a plurality of rows of in-situ pixel circuits, and the plurality of second driving units are configured to provide gate signals to a plurality of rows of reserved pixel circuits.

20. The display substrate according to any one of claims 1 to 19, wherein: The first display area is in the shape of a runway hole.

21. The display substrate according to any one of claims 1 to 19, wherein: The plurality of second light emitting elements in the first display area are connected to the plurality of second pixel circuits in the second display area via a plurality of first conductive connecting lines, and the plurality of first conductive connecting lines are located in the same conductive layer.

22. A display device, comprising a display substrate as described in any one of claims 1 to 21, and a sensor located on a non-display surface side of the display substrate, wherein the orthographic projection of the sensor on the substrate of the display substrate at least partially overlaps with the orthographic projection of the first display area of ​​the display substrate on the substrate.

23. A display substrate, comprising: A plurality of first display areas and a second display area located at at least one side of the plurality of first display areas; The plurality of first display areas are arranged in a staggered manner along a first direction or a second direction, and the first direction intersects with the second direction; The display substrate comprises: substrate; A plurality of pixel circuits, including a plurality of first pixel circuits located in at least one first display area of ​​the plurality of first display areas, and a plurality of reserved pixel circuits and a plurality of in-situ pixel circuits located in the second display area; the plurality of reserved pixel circuits include a plurality of second pixel circuits; in the second display area, the plurality of reserved pixel circuits arranged along the first direction are a row of reserved pixel circuits, the plurality of in-situ pixel circuits arranged along the first direction are a row of in-situ pixel circuits, and along the second direction, a row of reserved pixel circuits is arranged every m rows of in-situ pixel circuits, where m is an integer greater than 1; A plurality of light emitting elements, including: a plurality of first light emitting elements and a plurality of second light emitting elements located in the at least one first display area, and a plurality of third light emitting elements located in the second display area; The at least one first display area includes: a first area and a second area arranged along the first direction, the first area is adjacent to the second display area in the first direction, the second area is adjacent to another first display area in the first direction, the plurality of second light-emitting elements are located in the first area, and the plurality of first pixel circuits and the plurality of first light-emitting elements are located in the second area; At least one first pixel circuit among the plurality of first pixel circuits is connected to at least one first light-emitting element among the plurality of first light-emitting elements, and an orthographic projection of the at least one first pixel circuit on the substrate at least partially overlaps with an orthographic projection of the at least one first light-emitting element connected thereto on the substrate; At least one second pixel circuit among the plurality of second pixel circuits is connected to at least one second light-emitting element among the plurality of second light-emitting elements through at least one first conductive connection line extending along the second direction, and an orthographic projection of the at least one second pixel circuit on the substrate does not overlap with an orthographic projection of the at least one second light-emitting element connected thereto on the substrate; At least one of the multiple in-situ pixel circuits is connected to at least one of the multiple third light-emitting elements, and the orthographic projection of the in-situ pixel circuit on the substrate at least partially overlaps with the orthographic projection of the connected at least one third light-emitting element on the substrate.

24. The display substrate according to claim 23, wherein: The display substrate comprises three first display areas, two of which are aligned along the first direction, and the third first display area is located on the same side of the two first display areas along the second direction; each first display area is provided with the plurality of first light-emitting elements, the plurality of second light-emitting elements and the plurality of first pixel circuits; In two first display areas located in the same row, the plurality of second light-emitting elements are located in a first area of ​​the first display area in the first direction, and the plurality of first pixel circuits and the plurality of first light-emitting elements are located in a second area of ​​the first display area in the first direction; In the third first display area, the plurality of second light-emitting elements are located in the middle of the plurality of first light-emitting elements in the first direction.

25. The display substrate according to claim 23, wherein: The display substrate comprises: four first display areas, the four first display areas are arranged in two rows, and the two rows of first display areas are staggered along the first direction; Two first display areas in at least one row are provided with the multiple first light-emitting elements, the multiple second light-emitting elements and the multiple first pixel circuits; or, one first display area in one row is provided with the multiple first light-emitting elements, the multiple second light-emitting elements and the multiple first pixel circuits.

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