Refreshing method and device for double basic input and output systems, electronic equipment and medium

Abstract

The invention discloses a refreshing method and device of a double basic input and output system, electronic equipment and a medium, and relates to the technical field of storage systems, and the refreshing method comprises the steps of firstly upgrading firmware of a standby memory, switching to a main memory and restarting, then upgrading the firmware of the main memory, automatically executing sequential upgrading, and avoiding missing refreshing. And after firmware upgrading of the main memory is completed, executing a watchdog register erasing instruction, and clearing dirty data possibly existing in a data area of the EEPROM register, so that the dirty data is prevented from interfering with system operation. The consistency of versions is verified by detecting that the versions of the double firmware are the same, it is ensured that dirty data are removed by detecting that a watchdog erasing instruction takes effect, it is confirmed that upgrading succeeds and the system state is clean through double verification, and performance fluctuation, stability decline or reliability risks caused by the dirty data are eliminated from the source.

Description

Technical Field

[0001] The present application relates to the technical field of storage systems, and in particular, to a method, device, electronic device and medium for refreshing a dual basic input / output system. Background Art

[0002] With the rapid development of information technology, the enterprise data volume has increased exponentially, posing higher requirements for the stability and reliability of unified storage systems. As the underlying firmware of a computer system, the Basic Input / Output System (BIOS) and its refresh and recovery mechanisms directly affect the availability of the system. The traditional single-BIOS architecture has a risk of single-point failure during the refresh process. If the refresh fails, the system may not be able to start and requires manual intervention for recovery, seriously affecting the business continuity of enterprises. Therefore, the dual-BIOS redundant design emerged, improving the system fault tolerance through the switching mechanism of the primary and standby BIOSs.

[0003] The traditional dual-BIOS upgrade process usually requires independent operations on the primary and standby BIOSs respectively. Due to the cumbersome steps, it is very easy to miss refreshing one of the dual-BIOS Flash chips within the limited operation time, thus affecting the overall performance and stability of the system. In addition, the BIOS configuration data stored in the Electrically Erasable Programmable Read-Only Memory (EEPROM) register of the watchdog may generate dirty data due to interruption or abnormality during the upgrade process, affecting the system's correct judgment of the BIOS status. Therefore, the reliability of the traditional dual-BIOS solution is limited in practical applications, and there is an urgent need for a more efficient and secure dual-BIOS refresh method. Summary of the Invention

[0004] The present application provides a method, device, electronic device and medium for refreshing a dual basic input / output system, so as to at least solve the problems in the related art that the dual-BIOS upgrade process is cumbersome and prone to missing refreshing, and there are dirty data in the watchdog EEPROM register data area, affecting the system performance, stability and reliability.

[0005] The present application provides a method for refreshing a dual basic input / output system. The dual basic input / output system includes a main memory and a standby memory sharing a physical storage chip, and the method includes: When triggering the refresh test item of the dual basic input / output system, detecting whether the currently activated memory serial number is the first serial number corresponding to the main memory; If not, upgrading the second firmware corresponding to the standby memory; Switch from the backup memory to the main memory and perform a power-off restart operation; After the power-off restart, upgrade the first firmware corresponding to the main memory; Execute a watchdog register erase instruction and perform a power-off restart operation; the watchdog register erase instruction is used to write a first value to the watchdog register; When it is detected after the power-off restart that the versions of the first firmware and the second firmware are the same and the value of the watchdog register is the first value, determine that the dual basic input / output system refresh is completed.

[0006] This application also provides a dual basic input / output system refresh device. The dual basic input / output system includes a main memory and a backup memory sharing a physical storage chip, and includes: A memory detection module, used to detect whether the currently activated memory serial number is the first serial number corresponding to the main memory when triggering the refresh test item of the dual basic input / output system; A second firmware upgrade module, used to upgrade the second firmware corresponding to the backup memory if not; A memory switching module, used to switch from the backup memory to the main memory and perform a power-off restart operation; A first firmware upgrade module, used to upgrade the first firmware corresponding to the main memory after the power-off restart; An erase module, used to execute a watchdog register erase instruction and perform a power-off restart operation; the watchdog register erase instruction is used to write a first value to the watchdog register; A verification module, used to determine that the dual basic input / output system refresh is completed when it is detected after the power-off restart that the versions of the first firmware and the second firmware are the same and the value of the watchdog register is the first value.

[0007] This application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any of the above dual basic input / output system refresh methods when executing the computer program.

[0008] This application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above dual basic input / output system refresh methods are implemented.

[0009] This application also provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of any of the above dual basic input / output system refresh methods are implemented.

[0010] In this application, the firmware of the backup memory is first upgraded, then switched to the main memory and restarted, and then the firmware of the main memory is upgraded. The sequential upgrade is automatically executed to avoid missed flashing. After the firmware upgrade of the main memory is completed, a watchdog register erase instruction is executed to clear the possible dirty data in the EEPROM register data area, avoiding interference with the system operation. The consistency of the version is verified by detecting that the two firmware versions are the same, and the effectiveness of the watchdog erase instruction is detected to ensure that the dirty data has been cleared. The dual verification confirms that the upgrade is successful and the system state is clean, eliminating the performance fluctuations, stability degradation or reliability risks caused by dirty data at the root cause. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0012] Figure 1A FIG. is a schematic diagram of the production and detection process of the unified storage machine; Figure 1B FIG. is a schematic diagram of the process flow of functional testing, aging testing, and inspection testing; Figure 2 FIG. 1 is a schematic flow chart of a method for refreshing a dual basic input / output system provided by an embodiment of the present application; Figure 3 FIG. is a logical schematic diagram of a method for refreshing a dual basic input / output system provided by an embodiment of the present application; Figure 4 FIG. is a schematic flow chart of a method for refreshing a dual basic input / output system provided by an embodiment of the present application Figure 2 ; Figure 5 FIG. is a schematic flow chart of a method for refreshing a dual basic input / output system provided by an embodiment of the present application Figure 3 ; Figure 6 FIG. is a schematic structural diagram of a device for refreshing a dual basic input / output system provided by an embodiment of the present application; Figure 7 FIG. is a schematic structural diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0013] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0014] It should be noted that, in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0015] In order to more clearly illustrate the embodiments of the present application, the following briefly introduces the technical terms required to be used in the embodiments: Unified storage is a storage system that can run and manage files and applications on a single device. Unified storage systems integrate file-based and block-based access on a single storage platform, supporting Fibre Channel-based storage area networks (SAN), IP-based SAN, and network attached storage (NAS). Unified storage devices are usually equipped with a single BIOS Flash chip. BIOS is a set of programs fixed on the motherboard, responsible for power-on self-test, hardware initialization, and providing the operating system with a low-level hardware control interface.

[0016] The traditional single BIOS architecture has a single point of failure risk during the refresh process. If the refresh fails, the system may not be able to start and manual intervention is required to recover, which seriously affects the business continuity of the enterprise. Therefore, the dual BIOS redundancy design came into being, which improves the fault tolerance of the unified storage system through the switching mechanism of the main and standby BIOS.

[0017] Unify the production and testing process of storage machines such as Figure 1A As shown, it includes pre-processing, assembly line, functional testing, aging testing, inspection testing, packaging, outgoing quality control (OQC) sampling, finished product warehousing and shipment. Among them, the functional test is a functional test of the assembled product to verify whether the product can achieve the predetermined function. If the functional test fails, it is necessary to return to the pre-processing, assembly line and other links to troubleshoot the problem; if it passes, proceed to the next step. Aging testing simulates the use scenarios of the product under specific conditions such as long time and high load, and detects the stability and reliability of the product during long-term operation. Inspection testing is a comprehensive quality inspection of products that have undergone aging testing, including appearance, performance and other aspects to ensure that the product meets quality standards.

[0018] like Figure 1BThe process flows of the function test, aging test, and inspection test shown are uniformly stored. After the machine assembly is completed, the firmware (FW) of each component such as BIOS, Baseboard Management Controller (BMC), and external plug-in cards is refreshed at the front-end workstation (i.e., the function test workstation); the information of the Field Replaceable Unit (FRU), Vital Product Data (VPD), and System Management BIOS (SMBIOS) is refreshed; configuration detection, health detection, and function test are carried out. At the aging test workstation, Alternating Current (AC), Direct Current (DC) tests, storage of the overall machine function and performance tests, storage of each component stress tests, mixed stress tests, and overall machine stress tests are carried out. Exemplarily, the test environment: normal temperature; 1 / 100 is extracted for high-temperature aging, and the temperature in the greenhouse is 5 - 55 degrees Celsius. The test time is 48H - 60H, and the hard disk aging test time is 25H. At the inspection test workstation, information inspection, storage cluster creation and detection, function detection, and creation of the overall machine snapshot are carried out.

[0019] A Complex Programmable Logic Device (CPLD) is an integrated circuit that can implement logical functions through programming and is commonly used in the motherboard to implement functions such as hardware logic control and signal routing.

[0020] The BMC is an independent management chip on the motherboard, which is used to monitor the hardware status (such as temperature, voltage, fan speed), remote management (such as power on / off, firmware upgrade), etc.

[0021] An Electrically-Erasable Programmable Read Only Memory (EEPROM) is a non-volatile memory that can erase and rewrite data through electrical signals and is commonly used to store system configuration parameters, and the data is not lost after power-off.

[0022] The watchdog is a hardware or software timer used to detect the system running status. If the system does not "feed the dog" regularly, the watchdog will trigger a system restart to prevent system crashes. After the watchdog is started, it starts to count down, and the system needs to "feed the dog" (reset the timer) regularly. If the dog is not fed on time, the system is considered abnormal and a reset is triggered.

[0023] In order to enable those skilled in the art of this technical field to better understand the solution of this application, the following further detailed description of this application will be given in conjunction with the accompanying drawings and specific embodiments.

[0024] In combination with the specific application environment architecture or specific hardware architecture on which the execution of the refresh method of the dual basic input / output system depends, the specific application environment architecture or specific hardware architecture is described herein.

[0025] The hardware architecture includes: dual BIOS chips, a switching control circuit, a system bus, and a watchdog circuit.

[0026] Among them, the dual BIOS chips: There are two BIOS chips equipped on the motherboard, usually the main BIOS and the standby BIOS. The chip type is generally flash memory (Flash ROM), and this kind of chip can perform read and write operations under the working voltage. The data lines, address lines, and some control lines of the two chips are connected in parallel, and the chip select terminal is used to determine which chip works. When the chip select terminal is at a low level, the chip is selected to work, and when it is at a high level, it is in a high-impedance state and does not work.

[0027] The switching control circuit: Some motherboards achieve the switching of BIOS chips through jumpers (Jumper). The system can be booted with the standby BIOS by adjusting the jumper to the "RESCUEROM" position. There are also some motherboards that use an electronic switching circuit, which is controlled by the BIOS settings or a specific control program for switching, without the need to manually operate the jumper.

[0028] The system bus: The BIOS chip is connected to other components on the motherboard through the system bus, such as the CPU, memory, south bridge chip, etc. When refreshing the BIOS, data is transmitted between the BIOS chip, memory, and CPU through the system bus. The CPU executes the refresh program to write the new firmware data from the memory into the specified BIOS chip.

[0029] The watchdog circuit: There is a watchdog circuit in the system, which includes a watchdog register. This circuit is used to monitor the running state of the system and can trigger operations such as restart when the system has an abnormality. During the dual BIOS refresh process, specific values (the first value) are written to the watchdog register to clear the possible dirty data, ensuring its normal operation and not affecting the system performance and stability.

[0030] The software environment includes a BIOS refresh program, operating system support, and a network environment.

[0031] The BIOS refresh program: A dedicated BIOS refresh program is required, which can run in the DOS or Windows environment.

[0032] Operating System Support: If refreshing in a Windows environment, the operating system needs to provide corresponding interfaces and permission support so that the refreshing program can access the BIOS chip and related system resources. At the same time, the operating system also needs to be able to recognize and manage the dual BIOS system to ensure that no conflicts or errors occur during the refreshing process.

[0033] Network Environment: If it is necessary to obtain the BIOS image file from a remote server for refreshing, network environment support is also required. Connect to the server through a network protocol to download the latest BIOS firmware.

[0034] Embodiments of the present application provide a method for refreshing a dual basic input / output system. Combining the execution process of the method for refreshing the dual basic input / output system, the method is described in detail.

[0035] As Figure 2 shown, Figure 2 FIG. 1 is a schematic flowchart of a method for refreshing a dual basic input / output system provided by an embodiment of the present application. The method includes the following steps S201 to S206: S201. When triggering the refresh test item of the dual basic input / output system, detect whether the currently activated memory serial number is the first serial number corresponding to the main memory.

[0036] The dual basic input / output system (BIOS) includes a main memory (Flash0) and a standby memory (Flash1) that share a physical storage chip. The refresh test item of the dual BIOS is used to test the firmware program update of the dual BIOS. The refresh test item of the dual BIOS is a test item in the functional test of the storage whole machine.

[0037] When triggering the refresh test item of the dual BIOS, detect whether the currently activated memory serial number is the first serial number 0 corresponding to the main memory. If so, it means that the currently activated memory is the main memory Flash0. If not, it means that the currently activated memory is the standby memory Flash1, and further execute the subsequent step S202.

[0038] In some embodiments, the memory serial number is read from the target register, and then it is detected whether the memory serial number is the first serial number. Among them, the target register is a register provided by a complex programmable logic device to the baseboard management controller, indicating that the target register is defined and maintained by the complex programmable logic device, and the baseboard management controller can read the data in the target register through the bus. The address identifier of the target register is 0x69. By defining the data interaction interface with a fixed address (0x69), the communication between the BMC and the CPLD is standardized, reducing the software adaptation complexity.

[0039] Optionally, upload the read memory serial number to the database to record the initial state, which is convenient for rolling back by comparing the serial numbers before and after in case of memory switching failure.

[0040] In the above embodiment, by reading the Flash serial number, the primary and standby Flash are distinguished to prevent misflashing. The cooperation between the complex programmable logic device and the baseboard management controller realizes the data interaction between the hardware layer (Flash) and the management layer (BMC), enabling the refresh test item to monitor the hardware status in real time and improving the accuracy of the automated test.

[0041] S202: If not, upgrade the second firmware corresponding to the standby memory.

[0042] When it is detected that the currently activated is the standby memory, upgrade the second firmware (Flash1_BIOS_FirmWare) corresponding to the standby memory.

[0043] As Figure 3 shown, Figure 3 is a logical schematic diagram of the refresh method for the dual basic input / output system provided by the embodiment of the present application. When it is detected that the currently activated is the standby memory Flash1, upgrade the second firmware corresponding to the standby memory Flash1.

[0044] S203: Switch from the standby memory to the primary memory and perform a power-off restart operation.

[0045] As Figure 3 shown, switch to the primary memory Flash0, and then make the power-off restart (ac_cycle, AC) take effect.

[0046] In some embodiments, switching from the standby memory to the primary memory includes: executing a memory switching instruction and writing a second value to the switching control register. Here, the naming of the second value is only used to distinguish it from the first value written to the watchdog register. Among them, the storage units with addresses 0x2000 and 0x2002 in the EEPROM are called the switching control register, indicating that the memory switching instruction operates on the storage units with addresses 0x2000 and 0x2002 in the EEPROM. The switching control register is used to store control parameters or status flags related to Flash switching. The address identifiers of the switching control register are 0x2000 and 0x2002. Write the second value 0xff to the switching control register to trigger the Flash switching logic and notify the motherboard controller to prepare to switch to the primary memory.

[0047] Then perform a power-off and restart operation (ac_cycle), cut off the device power supply (power down), and then reconnect the power supply (power up) to make the hardware configuration change take effect, thus ensuring the consistency of the firmware and hardware states. The power-off and restart completely cuts off the alternating current, causing the hardware to lose power completely, resetting the hardware registers, and changing the hardware configuration. If the ac_cycle is not performed, the write operation of the switching control register may not be recognized by the motherboard controller, resulting in the memory switching instruction and firmware burning not taking effect.

[0048] In the above embodiment, by writing 0xff to the switching control register, operating the switching control register to switch to the main memory, then powering down and powering up to re-initialize the motherboard controller, and reading the latest switching control register data, it is ensured that the operation is completed in one go, guaranteeing the synchronization of the firmware and hardware states and avoiding the standby memory being in a semi-written state due to a mid-way power cut.

[0049] S204. Upgrade the first firmware corresponding to the main memory after a power-off and restart.

[0050] In some embodiments, it is detected whether the memory serial number after a power-off and restart is the first serial number. If so, the first firmware corresponding to the main memory is upgraded. Specifically, after a power-off and restart, the memory serial number is read from the target register 0x69, and then it is detected whether the memory serial number is the first serial number 0 corresponding to the main memory. If so, the first firmware (Flash0_BIOS_FirmWare) corresponding to the main memory Flash0 is upgraded.

[0051] If it is detected that the memory serial number after a power-off and restart is not the first serial number, an error message is generated to help engineers quickly locate problems, such as CPLD logic errors, Flash chip failures, bus communication anomalies, etc.

[0052] As Figure 3 shown, after a power-off and restart, it is detected whether the activated memory is the main memory Flash0. If so, the first firmware corresponding to the main memory Flash0 is upgraded. If not, an error is reported. By performing the power-off and restart operation, it is ensured that each firmware upgrade and memory switch can take effect, and the whole process has strong coherence, reducing the uncertain factors in manual intervention.

[0053] The above embodiments take the serial number of the currently activated memory as the starting point for judgment and construct a clear operation path. If the current one is not the main memory, first upgrade the firmware of the standby memory, then switch to the main memory and power off and restart, and then upgrade the firmware of the main memory. This sequential operation method makes the upgrade steps clear and avoids the missed flashing situation caused by chaotic steps. For example, in the conventional dual-BIOS upgrade, it may be easy to forget to upgrade a certain BIOS due to complex operations. However, this method ensures that each BIOS can be processed by clarifying the sequence, solving the problem of cumbersome and error-prone dual-BIOS upgrade process.

[0054] S205. Execute the watchdog register erase instruction and perform a power-off restart operation.

[0055] As Figure 3 shown, after upgrading the first firmware corresponding to the main memory Flash0, clear the EEPROM and the AC takes effect.

[0056] Among them, the watchdog register erase instruction is used to write a first value into the watchdog register. The address identifier of the watchdog register is 0x2000~0x2007. The storage units in the EEPROM with addresses represented as 0x2000~0x2007 are called watchdog registers, indicating that the watchdog register erase instruction operates on the storage units in the EEPROM with addresses 0x2000~0x2007.

[0057] In some embodiments, when executing the watchdog register erase instruction, first clear the original values of the watchdog register 0x2000~0x2007, and then write the first value 0xff into the watchdog register 0x2000~0x2007. It can be understood that the count of the watchdog register addresses 0x2000~0x2007 is erased and reset to 0xff. Then perform a power-off restart operation (ac_cycle) to make the first firmware burning and the watchdog register erase instruction take effect.

[0058] In the above embodiments, when executing the watchdog register erase instruction and writing the first value into the watchdog register, this operation directly clears the possible dirty data. For example, during the long-term operation of the device, the watchdog register may record error or invalid count information, etc. By writing a specific value, it can be restored to the initial or normal state.

[0059] In some embodiments, detect whether to execute the watchdog register erase instruction when the watchdog countdown ends; if not, trigger a dual-BIOS system reset. The watchdog countdown can be 10 seconds. It can be understood that after a power-off restart, it is necessary to upgrade the first firmware corresponding to the memory and execute the watchdog register erase instruction within 10s. If it is not completed within 10s, trigger a dual-BIOS system reset.

[0060] S206. When it is detected that the first firmware and the second firmware have the same version and the value of the watchdog register is the first value after a power-off restart, it is determined that the dual basic input / output system refresh is completed.

[0061] As Figure 3 shown, after a power-off restart, the BIOS version is detected and the EEPROM is checked. Specifically, it is detected whether the versions of the first firmware and the second firmware are the same, and whether the values of the watchdog register from 0x2000 to 0x2007 are the first value 0xff. When both of these conditions are met, it is determined that the refresh test item of the dual BIOS is completed.

[0062] Optionally, it is detected whether the versions of the first firmware and the second firmware are the same as the firmware versions issued in the R & D stage of the production process. If the firmware versions are the same, the dual BIOS firmware burning is successful. By detecting whether the two firmware versions are the same to confirm the completion of the upgrade, an operation closed-loop is formed, reducing the risk of missed flashing from the process design.

[0063] If the values of the watchdog register from 0x2000 to 0x2007 are not the first value 0xff, it indicates that the erasure is not successful or there are hardware problems, triggering an error reporting process to avoid the residual dirty data affecting the subsequent operation.

[0064] The above embodiments verify whether the upgrade is successful by detecting whether the dual BIOS versions are correct, and verify whether the erasure operation is successful by determining whether the watchdog EEPROM addresses from 0x2000 to 0x2007 are 0xff. After a power-off restart, it is checked whether the value of the watchdog register is the first written value. If it is this value, it indicates that the erasure operation is successful, and there is no dirty data in the watchdog register data area, ensuring the normal operation of the subsequent watchdog-based monitoring and management functions of the system, thereby improving the system performance, stability and reliability. It realizes automatic quality inspection, reduces manual intervention, and improves the test efficiency.

[0065] In summary, the embodiment of the present application provides a method for refreshing a dual BIOS system. First, the firmware of the spare memory is upgraded, switched to the main memory and restarted, and then the firmware of the main memory is upgraded, automatically performing sequential upgrades to avoid missed flashing; after the firmware upgrade of the main memory is completed, a watchdog register erasure instruction is executed to clear the possible dirty data in the EEPROM register data area to avoid interfering with the system operation. By detecting that the dual firmware versions are the same to verify the version consistency, and detecting that the watchdog erasure instruction takes effect to ensure that the dirty data has been cleared, double verification confirms that the upgrade is successful and the system state is clean, eliminating the performance fluctuations, stability degradation or reliability risks caused by dirty data from the root.

[0066] As Figure 4 shownFigure 4 Flow schematic of the refresh method for the dual basic input / output system provided by the embodiment of the present application Figure 2 This method includes the following steps S401 to S406: S401. If it is detected that the currently activated memory serial number is the first serial number corresponding to the main memory, upgrade the first firmware corresponding to the main memory.

[0067] After step S201, if it is detected that the currently activated memory serial number is the first serial number 0 corresponding to the main memory, indicating that the currently activated memory is the main memory Flash0, then upgrade the first firmware (Flash0_BIOS_FirmWare) corresponding to the main memory. As Figure 3 shown, detect whether the currently activated one is the main memory Flash0. If so, upgrade the first firmware corresponding to the main memory Flash0.

[0068] S402. Switch from the main memory to the backup memory and perform a power-off restart operation.

[0069] As Figure 3 shown, switch to the backup memory Flash1, and then the AC takes effect.

[0070] In some embodiments, switching from the main memory to the backup memory includes: executing a memory switching instruction, writing a third value 0x33 to the switching control register 0x2000 to trigger the Flash switching logic and notify the motherboard controller to prepare to switch to the backup memory Flash1. Then perform a power-off restart operation (ac_cycle) to make the firmware burning of the main memory and the backup memory switching take effect.

[0071] S403. After the power-off restart, upgrade the second firmware corresponding to the backup memory.

[0072] In some embodiments, detect whether the memory serial number after the power-off restart is the second serial number. If so, upgrade the second firmware corresponding to the backup memory. Specifically, after the power-off restart, read the memory serial number from the target register, and then detect whether the memory serial number is the second serial number 1 corresponding to the backup memory Flash1. If so, it indicates that the memory switching is successful, and then upgrade the second firmware (Flash1_BIOS_FirmWare) corresponding to the backup memory Flash1.

[0073] If it is detected that the memory serial number after the power-off restart is not the second serial number, generate an error message. As Figure 3 shown, after the power-off restart, detect whether the currently activated memory is the backup memory Flash1. If so, upgrade the second firmware corresponding to the backup memory Flash1. If not, report an error.

[0074] S404. Switch back from the backup memory to the main memory.

[0075] Switching back from the backup memory Flash1 to the main memory Flash0 includes executing a memory switching instruction and writing a fourth value to the switching control register. The address identifiers of the switching control register include: 0x2000 and 0x2002. Write the fourth value 0xff to the switching control registers 0x2000 and 0x2002.

[0076] S405. Execute the watchdog register erasure instruction and perform a power-off restart operation.

[0077] As Figure 3 shown, after switching back to the main memory Flash0, clear the EEPROM and the AC takes effect.

[0078] When executing the watchdog register erasure instruction, first clear the original value of the watchdog register, and then write the first value 0xff to the watchdog registers 0x2000 to 0x2007. Then perform a power-off restart operation (ac_cycle) to make the second firmware burning, main memory switching, and watchdog register erasure instructions take effect.

[0079] In some embodiments, detect whether the watchdog register erasure instruction is executed when the watchdog countdown ends; if not, trigger a dual-BIOS system reset. The watchdog countdown can be 10 seconds. Writing the second value 0xff to the switching control registers 0x2000 and 0x2002 and writing the first value 0xff to the watchdog registers 0x2000 to 0x2007 are related operations and need to be completed within a preset duration (10s) to ensure consistent hardware states and avoid interference with the register states by other processes due to too long an operation interval. If the operation time exceeds the preset duration, trigger a dual-BIOS system reset.

[0080] S406. After a power-off restart, when it is detected that the versions of the first firmware and the second firmware are the same and the value of the watchdog register is the first value, determine that the dual basic input / output system refresh is completed.

[0081] As Figure 3 shown, after a power-off restart, detect the BIOS version and check the EEPROM. Specifically, detect whether the versions of the first firmware and the second firmware are the same, and detect whether the values of the watchdog registers 0x2000 to 0x2007 are the first value 0xff. When both of these conditions are met, determine that the refresh test item of the dual BIOS is completed. Optionally, detect whether the versions of the first firmware and the second firmware are the same as the firmware versions issued in the R & D stage of the production process. If the firmware versions are the same, the dual-BIOS firmware burning is successful.

[0082] The above embodiments verify whether the upgrade is successful by detecting whether the dual BIOS versions are correct, and verify whether the erasure operation is successful by determining whether the watchdog EEPROM addresses 0x2000 to 0x2007 are 0xff. This realizes automated quality inspection, reduces manual intervention, and improves testing efficiency.

[0083] An embodiment of the present application provides a method for refreshing a dual basic input / output system. First, upgrade the firmware of the main memory, switch to the standby memory and restart, then upgrade the firmware of the standby memory, and automatically perform sequential upgrades to avoid missed flashing. After the firmware upgrade of the standby memory is completed, switch back to the main memory and execute the watchdog register erasure instruction to clear the possible dirty data in the EEPROM register data area to avoid interfering with system operation. Verify the version consistency by detecting that the dual firmware versions are the same, and ensure that the dirty data has been cleared by detecting that the watchdog erasure instruction takes effect. Double verification confirms that the upgrade is successful and the system state is clean, eliminating performance fluctuations, stability degradation, or reliability risks caused by dirty data at the source.

[0084] As Figure 5 shown, Figure 5 is a flowchart of a method for refreshing a dual basic input / output system provided by an embodiment of the present application. Figure 3 This method includes the following steps S501 to S510: S501. Read the currently active memory serial number from the target register.

[0085] The target register is a register provided by the complex programmable logic device to the baseboard management controller. The dual BIOS system's currently active main memory or standby memory is distinguished by the memory serial number.

[0086] Exemplarily, read the current memory serial number from the target register 0x69.

[0087] Detect whether the memory serial number is the first serial number of the main memory. The main memory is Flash0, and the first serial number is 0. If not, it means the current memory is the standby memory, and then execute S502b.

[0088] The above steps automatically select the upgrade path by monitoring the currently active memory serial number. This adaptive process avoids step omissions that may be caused by manual intervention, ensuring that both BIOSs can be upgraded in an orderly manner regardless of the initial state.

[0089] S502a. If the memory serial number is the first serial number corresponding to the main memory, upgrade the first firmware corresponding to the main memory.

[0090] S503a. Execute the memory switch instruction to switch from the main memory to the standby memory.

[0091] Write 0x33 to the switching control register 0x2000 to switch from the main memory Flash0 to the backup memory Flash1.

[0092] S504a. Perform a power-off restart operation.

[0093] Perform a power-off restart operation (ac_cycle) to make the first firmware burning and memory switching instructions take effect.

[0094] Perform a power-off restart after each memory switch to ensure that the firmware change takes full effect and avoid interference from cached data.

[0095] S505a. Detect whether the memory number after the power-off restart is the second number corresponding to the backup memory.

[0096] If not, it means that the memory switch fails and an error message is generated. Determine to reread the memory number after restart. This closed-loop design prevents the upgrade from being interrupted due to state asynchronization.

[0097] S506a. If so, upgrade the second firmware corresponding to the backup memory.

[0098] Detect that the memory number after restart is the second number 1 corresponding to the backup memory Flash1, indicating that the memory switch is successful, and then upgrade the second firmware corresponding to the backup memory Flash1.

[0099] S507. Switch back from the backup memory to the main memory.

[0100] Specifically, write 0xff to the switching control registers 0x2000 and 0x2002. Then perform the subsequent steps S508 - S510.

[0101] The above steps ensure redundancy by alternately upgrading the two memories in a dual-BIOS system.

[0102] In the case where it is detected that the currently active memory number is not the first number 0 corresponding to the main memory Flash0, it means that the currently active in the dual-BIOS system is the backup memory Flash1, then perform step S502b. Upgrade the second firmware corresponding to the backup memory.

[0103] S503b. Execute the memory switching instruction to switch from the backup memory to the main memory.

[0104] Specifically, write 0xff to the switching control registers 0x2000 and 0x2002.

[0105] S504b. Perform a power-off restart operation.

[0106] Perform a power-off and restart operation (ac_cycle) to make the second firmware burn and the memory switch instruction take effect.

[0107] S505b. Detect whether the memory serial number after restart is the first serial number corresponding to the main memory.

[0108] If not, it indicates that the memory switch fails, and an error message is generated.

[0109] S506b. If so, upgrade the first firmware corresponding to the main memory.

[0110] Detecting that the memory serial number after restart is the first serial number 0 corresponding to the main memory Flash0 indicates that the memory switch is successful, and then upgrade the first firmware corresponding to the main memory Flash0.

[0111] After upgrading the first firmware corresponding to the main memory Flash0, continue with S508. Execute the watchdog register erase instruction.

[0112] Specifically, first clear the original values stored in the watchdog register from 0x2000 to 0x2007, and then write 0xff. This clears the residual configuration and restores the initial state of the watchdog register, avoiding interference from dirty data.

[0113] S509. Perform a power-off and restart operation.

[0114] Here, perform a power-off and restart operation (ac_cycle) to make the second firmware burn, the memory switch instruction, and the watchdog register erase instruction take effect.

[0115] The above watchdog register erase instruction is executed after all firmware upgrades are completed and is ensured to take effect through a power-off and restart. This avoids the watchdog triggering a restart and interrupting the upgrade due to dirty data during the upgrade process, and also avoids the timing conflict between the erase operation and the firmware write operation, preventing the erased dirty data from being overwritten by old data, and achieving a deep coupling between the erase operation and the firmware upgrade process.

[0116] S510. Detect whether the versions of the first firmware and the second firmware are the same after restart, and whether the value of the watchdog register is the first value.

[0117] If so, it indicates that the dual BIOS refresh is completed.

[0118] When the firmware versions of the main / backup memories are consistent, confirm that the upgrade is completed to prevent missed flashing and also verify whether the firmware is completely written during the switch process.

[0119] Complete the dual BIOS refresh test item in the functional test phase through the above steps. Subsequently, other test items of the functional test can be tested, which is beneficial to improving the test efficiency.

[0120] By alternately upgrading, switching, and verifying the two Flash chips as described above, using AC operations to ensure the effectiveness of the operations, and relying on steps such as EEPROM cleaning and inspection, the reliability of the BIOS firmware upgrade process is guaranteed, and possible errors can be detected and handled in a timely manner.

[0121] A method for refreshing a dual basic input / output system provided by an embodiment of the present application embeds the erasure of the watchdog register into the refresh process of the dual BIOS, preventing the memory from being missed during the refresh and avoiding the dirty data of the watchdog register, thereby improving the refresh efficiency.

[0122] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0123] An embodiment of the present application also provides a refreshing device for a dual basic input / output system, as Figure 6 shown. The dual basic input / output system includes a main memory and a backup memory sharing a physical storage chip. The device includes: A memory detection module 601, configured to detect whether the serial number of the currently activated memory is the first serial number corresponding to the main memory when triggering the refresh test item of the dual basic input / output system; A second firmware upgrade module 602, configured to upgrade the second firmware corresponding to the backup memory if the answer is no; A memory switching module 603, configured to switch from the backup memory to the main memory and perform a power-off restart operation; A first firmware upgrade module 604, configured to upgrade the first firmware corresponding to the main memory after the power-off restart; An erasure module 605, configured to execute a watchdog register erasure instruction and perform a power-off restart operation; the watchdog register erasure instruction is used to write a first value to the watchdog register; A verification module 606, configured to determine that the refresh of the dual basic input / output system is completed when it is detected after the power-off restart that the versions of the first firmware and the second firmware are the same and the value of the watchdog register is the first value.

[0124] As an optional implementation manner provided by an embodiment of the present application, the first firmware upgrade module 604, after detecting whether the serial number of the currently activated memory is the first serial number corresponding to the main memory when triggering the refresh test item of the dual basic input / output system, is further configured to upgrade the first firmware corresponding to the main memory if the answer is yes; The memory switching module 603 is further configured to switch from the main memory to the backup memory and perform a power-off restart operation; The second firmware upgrade module 602 is further configured to upgrade the second firmware corresponding to the backup memory after a power-off restart; The memory switching module 603 is further configured to switch back from the backup memory to the main memory; The erasing module 605 is configured to execute a watchdog register erasing instruction and perform a power-off restart operation; The verification module 606 is configured to determine that the dual basic input / output system refresh is completed when it is detected after a power-off restart that the versions of the first firmware and the second firmware are the same and the value of the watchdog register is the first value.

[0125] As an optional implementation manner provided in an embodiment of the present application, the memory detection module 601 is configured to: read a memory serial number from a target register, where the target register is a register provided by a complex programmable logic device to a baseboard management controller; and detect whether the memory serial number is the first serial number.

[0126] As an optional implementation manner provided in an embodiment of the present application, the first firmware upgrade module 604 is configured to: detect whether the memory serial number after a power-off restart is the first serial number; if so, upgrade the first firmware corresponding to the main memory.

[0127] As an optional implementation manner provided in an embodiment of the present application, the first firmware upgrade module 604 is further configured to: generate an error message if the memory serial number after a power-off restart is not the first serial number.

[0128] As an optional implementation manner provided in an embodiment of the present application, the erasing module 605 is specifically configured to: clear the original value of the watchdog register; and write the first value to the watchdog register.

[0129] As an optional implementation manner provided in an embodiment of the present application, the erasing module 605 is further configured to detect whether a watchdog register erasing instruction is executed when the watchdog countdown ends; if not, trigger a dual basic input / output system reset.

[0130] For the description of the features in the embodiments corresponding to the dual basic input / output system refresh device, reference may be made to the relevant description in the embodiments corresponding to the dual basic input / output system refresh method, which will not be elaborated here one by one.

[0131] An embodiment of the present application further provides an electronic device, as Figure 7 shown. The electronic device includes a memory 701 and a processor 702. A computer program is stored in the memory 701, and the processor 702 is configured to run the computer program to execute the steps in any one of the embodiments of the above dual basic input / output system refresh method.

[0132] Embodiments of the present application also provide a computer-readable storage medium storing a computer program, where the computer program is configured to execute the steps in any of the above-described embodiments of the method for refreshing a dual basic input / output system when running.

[0133] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as USB flash drives, read-only memories (ROM), random access memories (RAM), external hard drives, magnetic disks, or optical discs that can store computer programs.

[0134] Embodiments of the present application also provide a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-described embodiments of the method for refreshing a dual basic input / output system.

[0135] Embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-described embodiments of the method for refreshing a dual basic input / output system.

[0136] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled artisans can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0137] The above has introduced in detail a method, apparatus, electronic device, and medium for refreshing a dual basic input / output system provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A method for refreshing a dual basic input / output system, characterized in that, The dual basic input / output system includes a main memory and a spare memory that share a physical storage chip, and the method includes: When triggering the refresh test item of the dual basic input / output system, detecting whether the currently activated memory serial number is the first serial number corresponding to the main memory; If not, upgrading the second firmware corresponding to the spare memory; Switching from the spare memory to the main memory and performing a power-off restart operation; Upgrading the first firmware corresponding to the main memory after the power-off restart; Executing a watchdog register erase instruction and performing a power-off restart operation; the watchdog register erase instruction is used to write a first value to the watchdog register; When it is detected that the versions of the first firmware and the second firmware are the same and the value of the watchdog register is the first value after the power-off restart, determining that the refresh of the dual basic input / output system is completed.

2. The method according to claim 1, characterized in that, After detecting whether the currently activated memory serial number is the first serial number corresponding to the main memory when triggering the refresh test item of the dual basic input / output system, the method further includes: If so, upgrading the first firmware corresponding to the main memory; Switching from the main memory to the spare memory and performing a power-off restart operation; Upgrading the second firmware corresponding to the spare memory after the power-off restart; Switching back from the spare memory to the main memory; Executing the watchdog register erase instruction and performing a power-off restart operation; When it is detected that the versions of the first firmware and the second firmware are the same and the value of the watchdog register is the first value after the power-off restart, determining that the refresh of the dual basic input / output system is completed.

3. The method according to claim 1, characterized in that, The detecting whether the currently activated memory serial number is the first serial number corresponding to the main memory includes: Reading the memory serial number from a target register, where the target register is a register provided by a complex programmable logic device to a baseboard management controller; Detecting whether the memory serial number is the first serial number.

4. The method according to claim 1, characterized in that The upgrading the first firmware corresponding to the main memory after the power-off restart includes: Detecting whether the memory serial number after the power-off restart is the first serial number; If so, upgrading the first firmware corresponding to the main memory.

5. The method according to claim 4, wherein The method further includes: if the memory serial number after the power-off restart is not the first serial number, generating an error message.

6. The method according to claim 1 or 2, characterized in that, The executing the watchdog register erase instruction includes: Clearing the original value of the watchdog register; Writing the first value to the watchdog register.

7. The method according to claim 1 or 2, characterized in that, The method further includes: Detecting whether the watchdog register erase instruction is executed when the watchdog countdown ends; If not, triggering a reset of the dual basic input / output system.

8. A refresh device for a dual basic input / output system, characterized in that, The dual basic input / output system includes a main memory and a spare memory that share a physical storage chip, and the device includes: A memory detection module, configured to detect whether the currently activated memory serial number is the first serial number corresponding to the main memory when triggering the refresh test item of the dual basic input / output system; A second firmware upgrade module, configured to upgrade the second firmware corresponding to the spare memory if not; A memory switching module, configured to switch from the spare memory to the main memory and perform a power-off restart operation; The first firmware upgrade module is used to upgrade the first firmware corresponding to the main memory after a power-off restart; The erasure module is used to execute a watchdog register erasure instruction and perform a power-off restart operation; the watchdog register erasure instruction is used to write a first value to the watchdog register; The verification module is used to determine that the dual basic input / output system refresh is completed when it is detected after a power-off restart that the versions of the first firmware and the second firmware are the same and the value of the watchdog register is the first value.

9. An electronic device, characterized in that, Comprising: A memory for storing a computer program; A processor, when executing the computer program, is used to implement the steps of the dual basic input / output system refresh method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein when the computer program is executed by a processor, the steps of the dual basic input / output system refresh method according to any one of claims 1 to 7 are implemented.

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