Multi-chip integrated embedded system architecture simplification method, device, equipment and medium

Abstract

The present invention provides a multi-chip integrated embedded system architecture degenerate method, device, equipment and medium, including: generating target system resource constraints; generating a constraint space, and randomly generating a candidate solution matrix in the constraint space. X ; Evaluate candidate solutions based on fitness; Matrix of candidate solutions X Perform replacement sampling to obtain the evolution matrix E ; Random sampling candidate solution matrix X , get matrix A and matrix B; determine the starting point of evolution P ; Evolution matrix E Perform evolution; traverse the evolution matrix after evolution E , for the evolution matrix E Each evolutionary solution in the matrix is ​​evaluated for fitness, and the evolutionary solution with the smallest fitness value is selected to replace the candidate solution matrix X The candidate solution with the larger fitness value is selected; whether the number of iterations is greater than a preset maximum number of iterations is determined; and the output solution is decoded to obtain a multi-chip integrated embedded system with a simplified architecture. The simplified architecture system obtained by the present invention optimizes resource allocation, reduces system size, and reduces system cost.

Description

Technical Field

[0001] The present invention relates to the technical field of embedded systems, and in particular to a method, device, equipment and medium for degenerating a multi-chip integrated embedded system architecture. Background Art

[0002] Embedded systems are application-centric, based on computer and integrated circuit technology, with customizable software and hardware to adapt to application systems with strict requirements on functionality, reliability, cost, size, power consumption and other indicators. They are widely used in many fields such as smartphones, smart home appliances, industrial automation, automotive electronics, etc.

[0003] Currently, embedded system architecture design primarily utilizes software-hardware collaborative design, encompassing three key aspects: processing unit allocation, task partitioning, and task scheduling. The core concept is to coordinate and plan software and hardware design, treating them as a whole. This approach comprehensively considers system requirements and performance targets, leading to parallel, collaborative design to achieve optimal system implementation.

[0004] Chiplets are a technology that modularizes and miniaturizes chips with different functions. Each chiplet can implement specific functions, such as CPU, GPU, storage, and communications. With the rapid development of information technology, the method of building embedded processors such as SoCs and SIPs using mature chiplets has gained widespread application. Experts in the field of embedded systems have proposed the concept of system architecture degeneration, which involves tailoring existing system resources to minimize resource overhead and size while meeting user product requirements to build embedded processors such as SoCs and SIPs. However, existing hardware and software co-design methods, such as genetic algorithms and particle swarm algorithms, cannot yet solve the problem of system architecture degeneration and suffer from shortcomings such as slow convergence and insufficient global optimization capabilities.

[0005] α Alpha Evolution (AE) uses an adaptive basis vector with random and adaptive step sizes. α The algorithm uses the operator to update the solution, which has excellent characteristics such as fast convergence, global optimization and scale invariance. However, the algorithm has not been applied to system architecture design. Therefore, specific improvements are needed to solve the degeneracy problem of embedded system architecture with multi-chip integration. Summary of the Invention

[0006] In view of the defects in the prior art, the present invention provides a method, device, equipment and medium for degenerating the architecture of a multi-chip integrated embedded system.

[0007] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] In one aspect, the present invention provides a method for degenerating a multi-chip integrated embedded system architecture, comprising the following steps:

[0009] S1. Generate target system resource constraints based on multi-chip integrated embedded system information;

[0010] S2. Generate a constraint space based on the existing resources of the multi-chip integrated embedded system, randomly generate system architecture design schemes within the constraint space, and encode the design schemes to obtain a candidate solution matrix X , the candidate solutions include a processing resource allocation information segment, a communication resource allocation information segment, and a task assignment information segment;

[0011] S3, evaluating the candidate solution according to the fitness. If the fitness value of the candidate solution is less than the preset value, the candidate solution is output; if the fitness value of the candidate solution is greater than the preset value, the process goes to S4;

[0012] S4, candidate solution matrix X Perform replacement sampling to obtain the evolution matrix E , the evolution matrix is ​​obtained according to the following formula E The random step length , and calculate the attenuation factor α :

[0013] ;

[0014] ;

[0015] in, is the current iteration number; is the maximum number of iterations set; is the upper limit of the constraint space; is the lower limit of the constraint space; 、 A random real number matrix generated by rand(0,1[N,D]), where N is the candidate solution matrix X The number of candidate solutions in , D is the number of problem dimensions that the candidate solutions solve; A random integer matrix containing only 0 or 1 generated by randi(0,1[N,D]); Indicates the processing resource allocation information segment; Indicates a communication resource allocation information segment; Indicates the task assignment information segment;

[0016] S5. Random sampling candidate solution matrix X , get matrix A and matrix B;

[0017] S6. Determine the evolutionary starting point based on matrix A and matrix B P ;

[0018] S7, by attenuation factor α Evolution Matrix E To evolve:

[0019] ;

[0020] in, Evolution Matrix E Iterated t The second i an evolutionary solution; is the adaptive step size, generated by rand(0,1); 、 is the candidate solution matrix X Random sampling in ;

[0021] S8. Traverse the evolution matrix after evolution E , for the evolution matrix E Each evolutionary solution in the matrix is ​​evaluated for fitness, and the evolutionary solution with the smallest fitness value is selected to replace the candidate solution matrix X The candidate solution with the larger fitness value;

[0022] S9, determining whether the number of iterations is greater than the preset maximum number of iterations. If the maximum number of iterations is reached, the iteration is stopped and the solution with the best fitness is output; if the maximum number of iterations is less than the maximum number of iterations, the process returns to S5;

[0023] S10. Decode the output solution to obtain a system architecture design scheme after architecture degeneration, and obtain a multi-chip integrated embedded system after architecture degeneration according to the design scheme.

[0024] Furthermore, it also includes performing boundary constraints, rounding and legality correction before performing the fitness evaluation.

[0025] Furthermore, the legality amendment includes:

[0026] Traverse the task assignment information segments of the solutions, including the evolved solutions and candidate solutions, and check whether the task is assigned to a processor that exists in the solution. If the task is assigned to a processor that has been completely pruned, randomly reassign the task to a processor that exists in the solution. If all processors of the solution have been completely pruned, eliminate the solution.

[0027] After the task assignment is modified, the processor resource allocation information segment of the solution is traversed again to delete the communication resources with the processors that have been completely pruned.

[0028] Furthermore, the fitness value is calculated according to the following formula:

[0029] ;

[0030] in, For the i The fitness value of each solution; For the i The target system power consumption of each solution; For the i The execution time of a solution; For the i The cost of a solution; 、 、 is the weight coefficient.

[0031] Furthermore, the evolutionary starting point P Determined according to the following formula:

[0032] ;

[0033] in, 、 is the evolutionary starting point of the tth iteration; for The learning rate; for The learning rate; is the diagonal matrix of matrix A; is the weight matrix of matrix B.

[0034] Furthermore, the 、 Need to meet ,in, Respectively 、 、 The fitness value of .

[0035] Furthermore, the upper limit of the constraint space Determined by the existing resources of the system; the lower limit of the constraint space It is the default value, and the minimum value is 0.

[0036] In another aspect, the present invention provides a multi-chip integrated embedded system architecture degenerate device, comprising:

[0037] The first module is used to generate target system resource constraints based on multi-chip integrated embedded system information;

[0038] The second module is used to generate a constraint space based on the existing resources of the multi-chip integrated embedded system, randomly generate system architecture design schemes within the constraint space, and encode the design schemes to obtain a candidate solution matrix. X , the candidate solutions include a processing resource allocation information segment, a communication resource allocation information segment, and a task assignment information segment;

[0039] The third module is used to evaluate the candidate solution according to the fitness value. If the fitness value of the candidate solution is less than the preset value, the candidate solution is output; if the fitness value of the candidate solution is greater than the preset value, the fourth module is transferred;

[0040] The fourth module is used to solve the candidate matrix X Perform replacement sampling to obtain the evolution matrix E , the evolution matrix is ​​obtained according to the following formula E The random step length , and calculate the attenuation factor α :

[0041] ;

[0042] ;

[0043] in, is the current iteration number; is the maximum number of iterations set; is the upper limit of the constraint space; is the lower limit of the constraint space; 、 A random real number matrix generated by rand(0,1[N,D]), where N is the candidate solution matrix X The number of candidate solutions in , D is the number of problem dimensions that the candidate solutions solve; A random integer matrix containing only 0 or 1 generated by randi(0,1[N,D]); Indicates the processing resource allocation information segment; Indicates a communication resource allocation information segment; Indicates the task assignment information segment;

[0044] The fifth module is used to randomly sample candidate solution matrices X , get matrix A and matrix B;

[0045] The sixth module is used to determine the evolutionary starting point based on matrix A and matrix B P ;

[0046] The seventh module is used to pass the attenuation factor α Evolution Matrix E To evolve:

[0047] ;

[0048] in, Evolution Matrix E Iterated t The second i an evolutionary solution; is the adaptive step size, generated by rand(0,1); 、 is the candidate solution matrix X Random sampling in ;

[0049] The eighth module is used to traverse the evolution matrix after evolution E , for the evolution matrix E Each evolutionary solution in the matrix is ​​evaluated for fitness, and the evolutionary solution with the smallest fitness value is selected to replace the candidate solution matrix X The candidate solution with the larger fitness value;

[0050] The ninth module is used to determine whether the number of iterations is greater than the preset maximum number of iterations. If the maximum number of iterations is reached, the iteration is stopped and the solution with the best fitness is output; if the maximum number of iterations is less than the maximum number of iterations, the solution returns to the fifth module.

[0051] The tenth module is used to decode the output solution to obtain a system architecture design scheme after architecture degeneration, and obtain a multi-chip integrated embedded system after architecture degeneration based on the design scheme.

[0052] On the other hand, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the multi-chip integrated embedded system architecture degeneration method are implemented.

[0053] On the other hand, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of a multi-chip integrated embedded system architecture degeneration method.

[0054] Compared with the prior art, the beneficial technical effects of the present invention are:

[0055] The present invention provides a multi-chip integrated embedded system architecture degenerate method, device, equipment and medium, application α Evolutionary algorithms and making specific improvements to α Evolutionary algorithms can be applied to solve the embedded system architecture design problem of multi-chip integration, and improve the convergence speed of the embedded system architecture design of multi-chip integration. By encoding the system architecture and comprehensively considering the processing resources, communication resources and task allocation of the multi-chip integration system, the global optimization capability of the embedded system architecture design of multi-chip integration is improved. α The evolutionary algorithm introduces two distinct evolutionary paths to increase the correlation between successive iterative steps, enhancing robustness and accelerating convergence. The resulting architecturally degenerate system optimizes resource allocation, reduces system size, and reduces system cost. It also addresses the challenges of chiplet selection and resource tailoring in the design of embedded systems transitioning from multi-chiplet integrated systems to higher-density integrated systems like SOCs or SIPs. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0057] Figure 1 A schematic flow chart of a multi-chip integrated embedded system architecture simplification method according to an embodiment;

[0058] Figure 2 A schematic diagram of candidate solutions provided for an embodiment;

[0059] Figure 3 A schematic diagram of constructing an evolutionary matrix provided in an embodiment;

[0060] Figure 4 An embodiment provides and Construct a schematic diagram, where Figure 4 (a) Build a schematic diagram, Figure 4 (b) Build the schematic. DETAILED DESCRIPTION

[0061] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0062] Reference Figure 1 One embodiment provides a method for degenerating a multi-chip integrated embedded system architecture, comprising the following steps:

[0063] S1. Generate target system resource constraints based on multi-chip integrated embedded system information;

[0064] S2. Generate a constraint space based on the existing resources of the multi-chip integrated embedded system, randomly generate system architecture design schemes within the constraint space, and encode the design schemes to obtain a candidate solution matrix X ,like Figure 2 As shown, the candidate solution includes a processing resource allocation information segment, a communication resource allocation information segment, and a task assignment information segment;

[0065] S3, evaluating the candidate solution according to the fitness. If the fitness value of the candidate solution is less than the preset value, the candidate solution is output; if the fitness value of the candidate solution is greater than the preset value, the process goes to S4;

[0066] S4, reference Figure 3 , for the candidate solution matrix X Perform replacement sampling to obtain the evolution matrix E Since different components in the candidate solution have different meanings, the search step size needs to be constrained when performing random search in the evolution matrix. The evolution matrix is ​​obtained according to the following formula E The random step length , and calculate the attenuation factor α :

[0067] ;

[0068] ;

[0069] in, is the current iteration number; is the maximum number of iterations set; is the upper limit of the constraint space; is the lower limit of the constraint space; 、 A random real number matrix generated by rand(0,1[N,D]) used to generate perturbations, where N is the candidate solution matrix X The number of candidate solutions in , D is the number of problem dimensions that the candidate solutions solve; A random integer matrix containing only 0 or 1 generated by randi(0,1[N,D]); Indicates the processing resource allocation information segment; Indicates a communication resource allocation information segment; Indicates the task assignment information segment;

[0070] S5. Random sampling candidate solution matrix X , get matrix A and matrix B;

[0071] S6. Determine the evolutionary starting point based on matrix A and matrix B P ;

[0072] S7, by attenuation factor α Evolution Matrix E To evolve:

[0073] ;

[0074] in, Evolution Matrix E Iterated t The second i an evolutionary solution; is the adaptive step size, generated by rand(0,1); 、 is the candidate solution matrix X Random sampling in ;

[0075] S8. Traverse the evolution matrix after evolution E , for the evolution matrix E Each evolutionary solution in the matrix is ​​evaluated for fitness, and the evolutionary solution with the smallest fitness value is selected to replace the candidate solution matrix X The candidate solution with the larger fitness value;

[0076] S9, determining whether the number of iterations is greater than the preset maximum number of iterations. If the maximum number of iterations is reached, the iteration is stopped and the solution with the best fitness is output; if the maximum number of iterations is less than the maximum number of iterations, the process returns to S5;

[0077] S10. Decode the output solution to obtain a system architecture design scheme after architecture degeneration, and obtain a multi-chip integrated embedded system after architecture degeneration according to the design scheme.

[0078] By encoding the system architecture and comprehensively considering the multi-chip integrated system processing resources, communication resources and task allocation, the global optimization capability of the multi-chip integrated embedded system architecture design is improved. α The evolutionary algorithm introduces two different evolutionary paths to increase the correlation between consecutive iterative steps, increase robustness, and improve convergence speed.

[0079] described 、 Need to meet ,in, Respectively 、 、 The fitness value of .

[0080] The upper limit of the constraint space Determined by the existing resources of the system; the lower limit of the constraint space It is the default value, and the minimum value is 0 (i.e. the optimal architecture), which means that after degeneration, the minimum value of a certain resource in the system is 0.

[0081] In a preferred embodiment, the method further includes performing boundary constraints, rounding, and legality correction before performing the fitness evaluation. The legality correction includes:

[0082] Traverse the task assignment information segments of the solution, including the evolved solution and the candidate solution, and check whether the task is assigned to a processor that exists in the solution. If the task is assigned to a fully pruned processor (i.e., the number of processors in the solution is 0), randomly reassign the task to a processor that exists in the solution. If all processors in the solution are fully pruned, eliminate the solution.

[0083] After the task assignment is modified, the processor resource allocation information segment of the solution is traversed again, and the communication resource allocation information between the processors that have been completely pruned is deleted.

[0084] Through bound constraints and rounding operations, we ensure that candidate solutions can be correctly decoded to obtain the system architecture solution. At the same time, since the system resources after degeneration may be zero, a task may be deployed on a non-existent processor. After the architecture is degenerated, the system resources must ensure that the system can normally execute the given task. Therefore, the legality of the candidate solutions is corrected to avoid illegal solutions.

[0085] In one embodiment, the fitness value is calculated according to the following formula:

[0086] ;

[0087] in, For the i The fitness value of each solution; For the i The target system power consumption of each solution; For the i The execution time of a solution; For the i The cost of a solution; 、 、 is the weight coefficient.

[0088] The fitness value is a weighted combination of the target system's power consumption, execution time, and cost. A smaller fitness value indicates better fitness.

[0089] In one embodiment, the evolutionary starting point P Determined according to the following formula:

[0090] ;

[0091] in, 、 is the evolutionary starting point of the tth iteration; for The learning rate; for The learning rate, and The values ​​of ; is the diagonal matrix of matrix A; is the weight matrix of matrix B. Figure 4 ,for and The construction diagram of is a matrix B Middle i The weight of the solution.

[0092] According to the above formula, the starting point of evolution is determined by randomly generating a number between 0 and 1. P , which can increase the correlation between consecutive iterative steps, avoid the loss of evolutionary information due to the lack of connection between iterations, and can effectively increase robustness and improve the convergence speed.

[0093] In one embodiment, a multi-chip integrated embedded system architecture degenerate device is provided, comprising:

[0094] The first module is used to generate target system resource constraints based on multi-chip integrated embedded system information;

[0095] The second module is used to generate a constraint space based on the existing resources of the multi-chip integrated embedded system, randomly generate system architecture design schemes within the constraint space, and encode the design schemes to obtain a candidate solution matrix. X , the candidate solutions include a processing resource allocation information segment, a communication resource allocation information segment, and a task assignment information segment;

[0096] The third module is used to evaluate the candidate solution according to the fitness value. If the fitness value of the candidate solution is less than the preset value, the candidate solution is output; if the fitness value of the candidate solution is greater than the preset value, the fourth module is transferred;

[0097] The fourth module is used to solve the candidate matrix X Perform replacement sampling to obtain the evolution matrix E , the evolution matrix is ​​obtained according to the following formula E The random step length , and calculate the attenuation factor α :

[0098] ;

[0099] ;

[0100] in, is the current iteration number; is the maximum number of iterations set; is the upper limit of the constraint space; is the lower limit of the constraint space; 、 A random real number matrix generated by rand(0,1[N,D]), where N is the candidate solution matrix X The number of candidate solutions in , D is the number of problem dimensions that the candidate solutions solve; A random integer matrix containing only 0 or 1 generated by randi(0,1[N,D]); Indicates the processing resource allocation information segment; Indicates a communication resource allocation information segment; Indicates the task assignment information segment;

[0101] The fifth module is used to randomly sample candidate solution matrices X , get matrix A and matrix B;

[0102] The sixth module is used to determine the evolutionary starting point based on matrix A and matrix B P ;

[0103] The seventh module is used to pass the attenuation factor α Evolution Matrix E To evolve:

[0104] ;

[0105] in, Evolution Matrix E Iterated t The second i an evolutionary solution; is the adaptive step size, generated by rand(0,1); 、 is the candidate solution matrix X Random sampling in ;

[0106] The eighth module is used to traverse the evolution matrix after evolution E , for the evolution matrix E Each evolutionary solution in the matrix is ​​evaluated for fitness, and the evolutionary solution with the smallest fitness value is selected to replace the candidate solution matrix X The candidate solution with the larger fitness value;

[0107] The ninth module is used to determine whether the number of iterations is greater than the preset maximum number of iterations. If the maximum number of iterations is reached, the iteration is stopped and the solution with the best fitness is output; if the maximum number of iterations is less than the maximum number of iterations, the solution returns to the fifth module.

[0108] The tenth module is used to decode the output solution to obtain a system architecture design scheme after architecture degeneration, and obtain a multi-chip integrated embedded system after architecture degeneration based on the design scheme.

[0109] On the other hand, the present invention provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the multi-chip integrated embedded system architecture simplification method provided in any of the above embodiments are implemented. The computer device may be a server. The computer device comprises a processor, a memory, a network interface, and a database connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device comprises a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store sample data. The network interface of the computer device is used to communicate with an external terminal via a network connection.

[0110] On the other hand, the present invention provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the multi-chip integrated embedded system architecture degeneration method provided in any of the above embodiments are implemented.

[0111] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0112] Matters not covered by the present invention are known technologies.

[0113] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0114] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and such modifications and improvements are intended to fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

[0115] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A multi-chip integrated embedded system architecture degeneracy method, characterized in that: The following steps are involved: S1. Generate target system resource constraints based on multi-chip integrated embedded system information; S2. Generate a constraint space based on the existing resources of the multi-chip integrated embedded system, randomly generate system architecture design schemes within the constraint space, and encode the design schemes to obtain a candidate solution matrix X , the candidate solutions include a processing resource allocation information segment, a communication resource allocation information segment, and a task assignment information segment; S3, evaluating the candidate solution according to the fitness. If the fitness value of the candidate solution is less than the preset value, the candidate solution is output; if the fitness value of the candidate solution is greater than the preset value, the process goes to S4; S4, candidate solution matrix X Perform replacement sampling to obtain the evolution matrix E , the evolution matrix is ​​obtained according to the following formula E The random step length , and calculate the attenuation factor α : ； ； in, is the current iteration number; is the maximum number of iterations set; is the upper limit of the constraint space; is the lower limit of the constraint space; 、 A random real number matrix generated by rand(0,1[N,D]), where N is the candidate solution matrix X The number of candidate solutions in , D is the number of problem dimensions that the candidate solutions solve; A random integer matrix containing only 0 or 1 generated by randi(0,1[N,D]); Indicates a processing resource allocation information segment; Indicates a communication resource allocation information segment; Indicates the task assignment information segment; S5. Random sampling candidate solution matrix X , get matrix A and matrix B; S6. Determine the evolutionary starting point based on matrix A and matrix B P ; S7, by attenuation factor α Evolution Matrix E To evolve: ； in, Evolution Matrix E Iterated t The second i an evolutionary solution; is the adaptive step size, generated by rand(0,1); 、 is the candidate solution matrix X Random sampling in ; S8. Traverse the evolution matrix after evolution E , for the evolution matrix E Each evolutionary solution in the matrix is ​​evaluated for fitness, and the evolutionary solution with the smallest fitness value is selected to replace the candidate solution matrix X The candidate solution with the larger fitness value is selected; and boundary constraints, rounding and legality correction are performed before performing the fitness evaluation; The legality amendments include: Traverse the task assignment information segments of the solutions, including the evolved solutions and candidate solutions, and check whether the task is assigned to a processor that exists in the solution. If the task is assigned to a processor that has been completely pruned, randomly reassign the task to a processor that exists in the solution. If all processors of the solution have been completely pruned, eliminate the solution. After correcting the task assignment, the processor resource allocation information segment of the solution is traversed again to delete the communication resources with the processors that have been completely pruned; S9, determining whether the number of iterations is greater than the preset maximum number of iterations. If the maximum number of iterations is reached, the iteration is stopped and the solution with the best fitness is output; if the maximum number of iterations is less than the maximum number of iterations, the process returns to S5; S10. Decode the output solution to obtain a system architecture design scheme after architecture degeneration, and obtain a multi-chip integrated embedded system after architecture degeneration according to the design scheme.

2. The multi-chip integrated embedded system architecture degeneration method according to claim 1, characterized in that: The fitness value is calculated according to the following formula: ； in, For the i The fitness value of each solution; For the i The target system power consumption of each solution; For the i The execution time of a solution; For the i The cost of a solution; 、 、 is the weight coefficient.

3. The multi-chip integrated embedded system architecture degeneration method according to claim 1, characterized in that: The evolutionary starting point P Determined according to the following formula: ； in, 、 is the evolutionary starting point of the tth iteration; for The learning rate; for The learning rate; is the diagonal matrix of matrix A; is the weight matrix of matrix B.

4. The multi-chip integrated embedded system architecture degeneration method according to claim 1, characterized in that: described 、 Need to meet ,in, Respectively 、 、 The fitness value of For the i An evolutionary solution.

5. The multi-chip integrated embedded system architecture degeneration method according to claim 1, characterized in that: The upper limit of the constraint space Determined by the existing resources of the system; the lower limit of the constraint space It is the default value, and the minimum value is 0.

6. A multi-chip integrated embedded system architecture degenerate device, characterized in that: include: The first module is used to generate target system resource constraints based on multi-chip integrated embedded system information; The second module is used to generate a constraint space based on the existing resources of the multi-chip integrated embedded system, randomly generate system architecture design schemes within the constraint space, and encode the design schemes to obtain a candidate solution matrix. X , the candidate solutions include a processing resource allocation information segment, a communication resource allocation information segment, and a task assignment information segment; The third module is used to evaluate the candidate solution according to the fitness value. If the fitness value of the candidate solution is less than the preset value, the candidate solution is output; if the fitness value of the candidate solution is greater than the preset value, the fourth module is transferred; The fourth module is used to solve the candidate matrix X Perform replacement sampling to obtain the evolution matrix E , the evolution matrix is ​​obtained according to the following formula E The random step length , and calculate the attenuation factor α : ； ； in, is the current iteration number; is the maximum number of iterations set; is the upper limit of the constraint space; is the lower limit of the constraint space; 、 A random real number matrix generated by rand(0,1[N,D]), where N is the candidate solution matrix X The number of candidate solutions in , D is the number of problem dimensions that the candidate solutions solve; A random integer matrix containing only 0 or 1 generated by randi(0,1[N,D]); Indicates a processing resource allocation information segment; Indicates a communication resource allocation information segment; Indicates the task assignment information segment; The fifth module is used to randomly sample candidate solution matrices X , get matrix A and matrix B; The sixth module is used to determine the evolutionary starting point based on matrix A and matrix B P ; The seventh module is used to pass the attenuation factor α Evolution Matrix E To evolve: ； in, Evolution Matrix E Iterated t The second i an evolutionary solution; is the adaptive step size, generated by rand(0,1); 、 is the candidate solution matrix X Random sampling in ; The eighth module is used to traverse the evolution matrix after evolution E , for the evolution matrix E Each evolutionary solution in the matrix is ​​evaluated for fitness, and the evolutionary solution with the smallest fitness value is selected to replace the candidate solution matrix X The candidate solution with the larger fitness value is selected; and boundary constraints, rounding and legality correction are performed before performing the fitness evaluation; The legality amendments include: Traverse the task assignment information segments of the solutions, including the evolved solutions and candidate solutions, and check whether the task is assigned to a processor that exists in the solution. If the task is assigned to a processor that has been completely pruned, randomly reassign the task to a processor that exists in the solution. If all processors of the solution have been completely pruned, eliminate the solution. After correcting the task assignment, the processor resource allocation information segment of the solution is traversed again to delete the communication resources with the processors that have been completely pruned; The ninth module is used to determine whether the number of iterations is greater than the preset maximum number of iterations. If the maximum number of iterations is reached, the iteration is stopped and the solution with the best fitness is output; if the maximum number of iterations is less than the maximum number of iterations, the solution returns to the fifth module. The tenth module is used to decode the output solution to obtain a system architecture design scheme after architecture degeneration, and obtain a multi-chip integrated embedded system after architecture degeneration based on the design scheme.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the multi-chip integrated embedded system architecture degeneration method according to any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium, characterized in that A computer program is stored thereon, and when the computer program is executed by a processor, the steps of the multi-chip integrated embedded system architecture degeneration method according to any one of claims 1 to 5 are implemented.

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