Display device

Abstract

A display device includes: a display panel including a display area including a transmissive area and a non-display area adjacent to the display area; and an input sensor on the display panel and including a plurality of conductive patterns, in which the plurality of conductive patterns includes: a first sensing electrode including a plurality of first sensing patterns arranged along a first direction and a plurality of bridge patterns configured to connect adjacent two of the plurality of first sensing patterns to each other; a second sensing electrode spaced apart from the first sensing electrode and including a plurality of second sensing patterns arranged along a second direction crossing the first direction; and a transparent electrode electrically connected to at least a portion of the first sensing electrode and the second sensing electrode.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0195534, filed on December 28, 2023, the entire content of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display device herein, and more particularly, to a display device having improved transmittance and improved sensing sensitivity of external inputs. Background art

[0004] Multimedia devices such as televisions, mobile phones, tablet computers, navigation devices, gaming consoles, etc. include display devices, each of which displays an image to a user through a display screen. Such a display device may include a display panel that generates an image and an input sensor that detects a user's touch.

[0005] Recently, due to technological advancements, transparent display devices have been developed in which a transmissive area within a display area is transparent. The input sensor may include conductors that detect external inputs, and the conductors of the input sensor disposed on the display panel may affect the emission efficiency and / or transmittance of the display device. Summary of the invention

[0006] The present disclosure provides a display device that improves the sensing sensitivity of external inputs of an input sensor while increasing the transmittance of a display area.

[0007] One or more embodiments of the present disclosure provide a display device including: a display panel including a display area including a transmissive area and a non - display area adjacent to the display area; and an input sensor on the display panel and including a plurality of conductive patterns, wherein the plurality of conductive patterns include: a first sensing electrode including a plurality of first sensing patterns arranged along a first direction and a plurality of bridging patterns configured to connect adjacent two of the plurality of first sensing patterns to each other; a second sensing electrode spaced apart from the first sensing electrode and including a plurality of second sensing patterns arranged along a second direction intersecting the first direction; and a transparent electrode electrically connected to at least a portion of the first sensing electrode and the second sensing electrode, wherein each of the plurality of first sensing patterns and the plurality of second sensing patterns includes a plurality of grid lines in which transmissive openings overlapping the transmissive area are located, and wherein the transparent electrode overlaps at least a portion of the transmissive area.

[0008] In one or more embodiments, the display area further includes: a plurality of pixel areas adjacent to the transmissive area and configured to emit light.

[0009] In one or more embodiments, in a display area, a ratio of an area of a transmissive area to a total area of the transmissive area and a plurality of pixel areas is about 60% or more.

[0010] In one or more embodiments, the input sensor further includes: a covering insulating layer, between the first sensing electrode and the second sensing electrode and the transparent electrode, and wherein the transparent electrode is electrically connected to at least a part of the first sensing electrode and the second sensing electrode through an upper contact hole passing through the covering insulating layer.

[0011] In one or more embodiments, the transparent electrode overlaps at least a part of each of the transmissive area and the plurality of pixel areas.

[0012] In one or more embodiments, the plurality of conductive patterns further includes: dummy patterns, at the same layer as the transparent electrode, and insulated from the first sensing electrode and the second sensing electrode.

[0013] In one or more embodiments, the plurality of pixel areas includes a first pixel area, a second pixel area, and a third pixel area, and the transmissive area is adjacent to each of the first pixel area, the second pixel area, and the third pixel area along a first direction.

[0014] In one or more embodiments, the transparent electrode includes a transparent conductive oxide (TCO).

[0015] In one or more embodiments, the display panel includes a light-emitting element configured to emit source light and at least overlap with a corresponding one of the plurality of pixel areas, and the light-emitting element includes: a first electrode; a first light-emitting stack on the first electrode; a second light-emitting stack on the first light-emitting stack; a third light-emitting stack on the second light-emitting stack; a fourth light-emitting stack on the third light-emitting stack; a second electrode on the fourth light-emitting stack; and charge generation layers respectively between the first light-emitting stack, the second light-emitting stack, the third light-emitting stack, and the fourth light-emitting stack, wherein each of the first light-emitting stack to the fourth light-emitting stack includes at least one emission layer.

[0016] In one or more embodiments, the display device further includes: a light control layer on the light-emitting element to transmit the source light or convert the source light into light having a wavelength different from that of the source light.

[0017] In one or more embodiments, the light control layer includes: dams including a plurality of dam openings; and a plurality of light control patterns respectively in the plurality of dam openings, wherein the plurality of light control patterns do not overlap with the transmissive area.

[0018] In one or more embodiments, at least one emission layer in each of the first light-emitting stack to the fourth light-emitting stack does not overlap with the transmissive area.

[0019] In one or more embodiments, the second sensing electrode further includes: a connection pattern between two adjacent second sensing patterns among the plurality of second sensing patterns, and having a shape integral with the plurality of second sensing patterns.

[0020] In one or more embodiments, the input sensor further includes: a sensing insulating layer between the plurality of bridging patterns and the plurality of first sensing patterns, wherein each of the plurality of bridging patterns is electrically connected to a corresponding one of the plurality of first sensing patterns through a lower contact hole defined in the sensing insulating layer.

[0021] In one or more embodiments, the transmissive region includes: a first transmissive region overlapping the transparent electrode in a plane; and a second transmissive region not overlapping the transparent electrode in a plane.

[0022] In one or more embodiments, a display device includes: a display panel including a display region having a transmissive region and a non-display region adjacent to the display region; and an input sensor on the display panel and including a plurality of conductive patterns, wherein the plurality of conductive patterns include: a plurality of unit sensing patterns arranged along a first direction and a second direction intersecting the first direction and insulated from each other; and a plurality of unit signal lines respectively connected to at least some of the plurality of unit sensing patterns, wherein each of the plurality of unit sensing patterns includes a plurality of grid lines having a transmissive opening defined therein at least overlapping the transmissive region, and each of the plurality of unit signal lines includes a plurality of sub-signal lines, the sub-signal lines being connected to a corresponding one of the plurality of unit sensing patterns and extending in the first direction.

[0023] In one or more embodiments, the plurality of sub-signal lines include: a first sub-signal line connected to a first unit sensing pattern, the first unit sensing pattern being one of the plurality of unit sensing patterns and extending in the first direction; a second sub-signal line connected to the first unit sensing pattern, extending in the first direction, and spaced apart from the first sub-signal line in the second direction; and a third sub-signal line connected to the first unit sensing pattern, extending in the first direction, and spaced apart from the first sub-signal line and the second sub-signal line in the second direction.

[0024] In one or more embodiments, each of the plurality of sub-signal lines has a width of about 1 micrometer or more and about 5 micrometers or less, and the distance between the plurality of sub-signal lines is about 3 micrometers or more and about 7 micrometers or less.

[0025] In one or more embodiments, the plurality of conductive patterns further include: an additional signal line having a shape integral with a part of the plurality of unit sensing patterns, electrically connected to this part of the plurality of unit sensing patterns, and overlapping the non-display region.

[0026] In one or more embodiments, the input sensor further includes: a sensing insulating layer between the plurality of unit sensing patterns and the plurality of unit signal lines, and each of the plurality of unit signal lines is electrically connected to a corresponding one of the plurality of unit sensing patterns through a unit contact hole passing through the sensing insulating layer.

[0027] In one or more embodiments, the display area further includes: a plurality of pixel areas adjacent to the transmissive area and configured to emit light.

[0028] In one or more embodiments, in the display area, the ratio of the area of the transmissive area to the total area of the transmissive area and the plurality of pixel areas is about 60% or more.

[0029] In one or more embodiments, the plurality of pixel areas include a first pixel area, a second pixel area, and a third pixel area, and the transmissive area is adjacent to each of the first pixel area, the second pixel area, and the third pixel area along a second direction.

[0030] In one or more embodiments, the display panel includes a light-emitting element configured to emit source light and at least overlapping a corresponding one of the plurality of pixel areas, and the light-emitting element includes: a first electrode; a first light-emitting stack on the first electrode; a second light-emitting stack on the first light-emitting stack; a third light-emitting stack on the second light-emitting stack; a fourth light-emitting stack on the third light-emitting stack; a second electrode on the fourth light-emitting stack; and charge generation layers respectively between the first light-emitting stack, the second light-emitting stack, the third light-emitting stack, and the fourth light-emitting stack, wherein each of the first light-emitting stack to the fourth light-emitting stack includes at least one emission layer.

[0031] In one or more embodiments, the display device further includes: a light control layer on the light-emitting element to transmit the source light or convert the source light into light having a wavelength different from that of the source light.

[0032] In one or more embodiments, the light control layer includes: dams having a plurality of dam openings; and a plurality of light control patterns respectively in the plurality of dam openings, wherein the plurality of light control patterns do not overlap with the transmissive area.

[0033] In one or more embodiments, at least one emission layer in each of the first light-emitting stack to the fourth light-emitting stack does not overlap with the transmissive area.

[0034] In one or more embodiments, a display device includes: a display panel including a display area and a non-display area adjacent to the display area, the display area having a transmissive area and a plurality of pixel areas adjacent to the transmissive area; and an input sensor on the display panel and including a plurality of conductive patterns, wherein the plurality of conductive patterns include a plurality of sensing patterns arranged along a first direction and a second direction intersecting the first direction, wherein the sensing patterns include a plurality of grid lines, wherein transmissive openings overlapping the transmissive area and a plurality of pixel openings respectively overlapping the plurality of pixel areas are in the plurality of grid lines, and wherein in the display area, a ratio of an area of the transmissive area to a total area of the transmissive area and the plurality of pixel areas is about 60% or more. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles and / or scope of the present disclosure. In the drawings:

[0036] Figure 1A is a perspective view of an electronic device according to one or more embodiments of the present disclosure;

[0037] Figure 1B is a perspective view of a curved electronic device according to one or more embodiments of the present disclosure;

[0038] Figure 2 is a cross-sectional view of a display device according to one or more embodiments of the present disclosure;

[0039] Figure 3A is a plan view of a display device according to one or more embodiments of the present disclosure;

[0040] Figure 3B is an enlarged plan view illustrating a part of a display device according to one or more embodiments of the present disclosure;

[0041] Figure 4 is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure;

[0042] Figure 5 and Figure 6 is a cross-sectional view of a display device according to one or more embodiments of the present disclosure;

[0043] Figure 7 is a cross-sectional view of a light-emitting element according to one or more embodiments of the present disclosure;

[0044] Figure 8 is a plan view of an input sensor according to one or more embodiments of the present disclosure;

[0045] Figure 9A and Figure 9B is an enlarged plan view of a part of an input sensor according to one or more embodiments of the present disclosure;

[0046] Figure 9C and Figure 9D is an enlarged cross-sectional view of a part of an input sensor according to one or more embodiments of the present disclosure;

[0047] Figures 10A to 10C is an enlarged plan view of a part of a display device according to one or more embodiments of the present disclosure;

[0048] Figure 11 is a plan view of an input sensor according to one or more embodiments of the present disclosure;

[0049] Figure 12A is an enlarged plan view of a part of an input sensor according to one or more embodiments of the present disclosure;

[0050] Figure 12B is an enlarged plan view of some configurations in the configuration of an input sensor according to one or more embodiments of the present disclosure;

[0051] Figure 12C is an enlarged cross-sectional view of a part of an input sensor according to one or more embodiments of the present disclosure; and

[0052] Figure 13 is a plan view of an input sensor according to one or more embodiments of the present disclosure. Detailed Description

[0053] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0054] In this specification, it will also be understood that when a component (or region, layer, part, etc.) is referred to as being "on" another component, "connected to" or "coupled to" another component, it can be directly on the other component, directly connected or coupled to the other component, or there may also be an intervening third component.

[0055] The same reference numerals refer to the same elements throughout. In addition, in the drawings, the thickness, ratio, and dimensions of the components are exaggerated for clarity of illustration. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0056] It will be understood that although terms such as "first" and "second" are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one component from other components. For example, an element referred to as the first element in one embodiment may be referred to as the second element in another embodiment without departing from the spirit or scope of the appended claims. Unless otherwise indicated to the contrary, terms in the singular form may include the plural form.

[0057] In addition, terms such as "below", "beneath", "above", and "on top of" are used to illustrate the relative relationship of components shown in the drawings. These terms may be relative concepts and may be described based on the directions expressed in the drawings.

[0058] The meaning of "comprising" or "including" indicates the presence of attributes, fixed numbers, steps, operations, elements, components, or combinations thereof, but does not exclude other attributes, fixed numbers, steps, operations, elements, components, or combinations thereof.

[0059] In this specification, "directly disposed" may mean that there is no layer, film, region, and / or plate, etc. between a part of a layer, film, region, and / or plate, etc. and another part. For example, "directly disposed" may mean that no additional component (such as an adhesive component) is used between two layers or two members for the disposition.

[0060] Unless otherwise defined, all terms used herein (including technical terms and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Additionally, terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with the context of the relevant art, and unless clearly defined herein, they are not to be interpreted as having overly ideal or overly formal meanings.

[0061] In the specification and claims, the term "and / or" is intended, for purposes of its meaning and interpretation, to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunctive or disjunctive sense and may be understood as equivalent to "and / or". In the specification and claims, the phrase "at least one of" is intended, for purposes of its meaning and interpretation, to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0062] Those of ordinary skill in the art will appreciate that, given the overall content of the present disclosure, each appropriate feature of each of the various embodiments of the present disclosure can be partially or fully combined or combined with each other, and can be interlocked and operated technically in various appropriate ways, and each embodiment can be implemented independently of each other or combined with each other in any appropriate way, unless otherwise stated or implied.

[0063] Hereinafter, a display device according to one or more embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0064] Figure 1A is a perspective view of an electronic device according to one or more embodiments of the present disclosure. Figure 1B is a perspective view of a curved electronic device according to one or more embodiments of the present disclosure. Figure 2 is a cross-sectional view of a display device according to one or more embodiments of the present disclosure.

[0065] Figure 1A and Figure 1B Each of the electronic devices ED and ED-1 illustrated in and may include a display device DD and a housing HU that houses at least a part of the display device DD. For example, a part of the lower end of the display device DD may be housed in the housing HU.

[0066] Referring to Figure 1A , the display device DD may display an image through the front surface D-U. The top surface of the member provided on the uppermost side of the display device DD may be defined as the front surface D-U of the display device DD. According to the present disclosure, Figure 2 the top surface of the window WD illustrated in may be defined as the front surface D-U of the display device DD.

[0067] In this embodiment, the front surface D-U may be parallel to the plane defined by the first direction DR1 and the second direction DR2. The normal direction of the front surface D-U (i.e., the thickness direction of the display device DD) may be indicated by the third direction DR3. The front surface (or top surface) and the rear surface (or bottom surface) of each of the layers or units to be described below are distinguished by the third direction DR3.

[0068] The display device DD according to the present disclosure may be a transparent display device DD. The transparent display device DD may display information in a state where an object PD provided on the rear surface D-B of the display device DD is transparently mapped on the front surface D-U of the display device DD. Therefore, the user can recognize the object PD provided on the rear surface D-B of the display device DD from the front surface D-U of the display device DD. The information is not limited to any one of an image, content, a playback screen, an application execution screen, a web browser screen, and various graphic objects. In Figure 1AIn the figure, the vase is shown as an example of the object PD, but the object PD is not limited thereto. The object PD may have a specific shape and is not limited to any one object.

[0069] The housing HU can protect the display device DD from external impacts or the intrusion of foreign objects. The housing HU can be made of materials such as plastic or metal. However, this is only an example and is not limited thereto, as long as the housing HU can protect the display device DD from external impacts or the intrusion of foreign objects. In the electronic device ED according to one or more embodiments, the housing HU can be omitted. However, the display device DD can be curled through a separate hinge member to be disposed within the housing HU and is not limited to the embodiments.

[0070] Reference Figure 1B , the electronic device ED-1 according to one or more embodiments can be bent along the second direction DR2 based on a virtual axis AX extending in the first direction DR1. Thus, the display device DD can be bent with an appropriate curvature (e.g., a predetermined curvature), and the housing HU can have a corresponding curvature. This is not limited thereto, and the axis can extend in the second direction DR2, or can be bent based on a plurality of axes extending in different directions.

[0071] In addition, the display device DD can be a rollable display panel, a foldable display panel, and / or a slidable display panel, and the entire display device DD can be disposed inside the housing HU in one operating state. Thus, the display device DD can include a curved display surface and / or a three-dimensional display surface. The three-dimensional display surface can include a plurality of display regions indicating different directions.

[0072] Reference Figure 2 , the display device DD according to one or more embodiments of the present disclosure can include a display panel DP, an input sensor IS, an optical layer OSL, and a window WD. The display panel DP can include a base substrate BS, a circuit element layer DP-CL disposed on the base substrate BS, a display element layer DP-OLED, and a packaging layer TFE. The display device DD can further include functional layers such as an antireflection layer and / or a refractive index control layer.

[0073] The display panel DP can be an emissive display panel and can include one of a liquid crystal display panel, an electrophoretic display panel, a microelectromechanical systems (MEMS) display panel, an electro-wetting display panel, an organic light-emitting display panel, an inorganic light-emitting display panel, and a quantum dot display panel, but is not particularly limited thereto.

[0074] The base substrate BS may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide resin layer, and the material of the synthetic resin layer is not particularly limited. The synthetic resin layer may include an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a silicone resin, a polyamide resin, and / or a perylene resin. In addition, the base substrate BS may include a glass substrate, a metal substrate, and / or an organic / inorganic composite substrate.

[0075] The circuit element layer DP-CL includes at least a plurality of insulating layers and circuit elements. The insulating layers described below may include an organic layer and / or an inorganic layer. The circuit element layer DP-CL forms the insulating layer, the semiconductor layer, and the conductive layer by processes such as coating and deposition. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by a photolithography process and an etching process. Through this process, a semiconductor pattern, a conductive pattern, and / or a signal line, etc. are formed. The patterns provided in the same layer are formed by the same process.

[0076] The circuit element layer DP-CL includes a driving circuit and / or a signal line constituting a pixel. The display element layer DP-OLED may include a light-emitting element OLED provided in the pixel (see Figure 5 ) and a pixel defining layer PDL (see Figure 5 ).

[0077] The encapsulation layer TFE may be provided on the display element layer DP-OLED to protect the light-emitting element OLED. The encapsulation layer TFE may include an inorganic layer and an organic layer provided between the inorganic layers. The inorganic layer may protect the light-emitting element OLED from the influence of moisture and oxygen, and the organic layer may protect the light-emitting element OLED from foreign substances such as dust particles.

[0078] The input sensor IS may be directly provided on the display panel DP. The input sensor IS may sense a user's input, for example, in an electromagnetic induction manner and / or a capacitive manner. The display panel DP and the input sensor IS may be formed by a continuous process. Here, "directly provided" may mean that no third component is provided between the input sensor IS and the display panel DP. For example, a separate adhesive layer may not be provided between the input sensor IS and the display panel DP.

[0079] The optical layer OSL can be disposed on the input sensor IS and can include a light control pattern capable of changing the optical characteristics of the source light generated by the light emitting element OLED. In addition, the optical layer OSL can reduce the reflectance of external light incident from the upper side of the window WD. The light control pattern can include quantum dots, and the optical layer OSL can include a color filter that selectively transmits the light passing through the light control pattern. According to one or more embodiments, the optical layer OSL can be omitted.

[0080] The window WD can be disposed on the display panel DP (e.g., can be disposed on the optical layer OSL) to transmit an image provided from the display panel DP to the outside. The window WD can include a base layer and a functional layer disposed on the base layer. The functional layer can include a protective layer and / or an anti-fingerprint layer, etc. The base layer of the window WD can be made of glass, sapphire, and / or plastic.

[0081] Figure 3A is a plan view of a display device according to one or more embodiments of the present disclosure. Figure 3B is an enlarged plan view illustrating a part of a display device according to one or more embodiments of the present disclosure.

[0082] Reference Figure 3A and Figure 3B , a display device DD according to one or more embodiments can include pixels disposed in a cell region PU, a gate driving circuit GDC connected to the pixels, and signal lines.

[0083] The display device DD can include a display area DA and a non-display area NDA around the edge or periphery of the display area DA. The emission layer of the pixels disposed in the cell region PU can be disposed in the display area DA, and the emission layer can not be disposed in the non-display area NDA. The non-display area NDA can surround the display area DA. In one or more embodiments of the present disclosure, the non-display area NDA can be omitted, or can be disposed only on one side of the display area DA. In Figure 3A , as an example, the shapes in which the display area DA and the non-display area NDA are defined in the display device DD are provided, and the display area DA and the non-display area NDA can be defined to correspond to the display panel DP included in the display device DD.

[0084] A plurality of cell regions PU can be provided within the display area DA. The cell regions PU can be arranged along a first direction DR1 and a second direction DR2. The cell region PU can include: an emission region through which the display panel DP provides information to the user; a transmission region for improving the transparency of the display panel DP so that an object PD disposed on the rear surface D-B of the display device DD is transmitted to the user; and a line region in which signal lines connected to the pixels are disposed.

[0085] Figure 3B An example in which the first unit area PU1 and the second unit area PU2 of the unit area PU shown therein are arranged along the second direction DR2. Figure 3A The first unit area PU1 may include pixel areas PXA1-1, PXA2-1, and PXA3-1 that are spaced apart from each other (e.g., separated) along the first direction DR1 and a transmissive area TA1 that is spaced apart (e.g., separated) from the pixel areas PXA1-1, PXA2-1, and PXA3-1 along the second direction DR2.

[0086] The second unit area PU2 may include pixel areas PXA1-2, PXA2-2, and PXA3-2 that are spaced apart from each other (e.g., separated) along the first direction DR1 and a transmissive area TA2 that is spaced apart (e.g., separated) from the pixel areas PXA1-2, PXA2-2, and PXA3-2 along the second direction DR2.

[0087] The non-pixel area NPXA may be around each of the pixel area PXA and the transmissive area TA adjacent to the pixel area PXA (e.g., may surround each of the pixel area PXA and the transmissive area TA adjacent to the pixel area PXA). In one or more embodiments, the display area DA may further include a line area adjacent to the pixel area PXA and the transmissive area TA. Lines such as sensing lines, power lines, and scanning lines may be provided in the line area.

[0088] According to one or more embodiments of the present disclosure, the wavelengths of the source light provided in the pixel area PXA may be different from each other. Each of the pixel areas PXA may be defined by a light-emitting opening PDL-OP included in the pixel defining layer PDL (see

[0089] ) and the transmissive area TA may be defined by a transmissive opening T-OP defined at least in the pixel defining layer PDL (see Figure 5 )). This will be described later. Figure 6

[0090] In the display area DA of the display device DD according to one or more embodiments, the planar area of each of the transmissive areas TA may be greater than the planar area of each of the pixel areas PXA. The planar area of each of the transmissive areas TA may be greater than the sum of the planar areas of the pixel areas PXA. In one or more embodiments, the planar area of the transmissive area TA1 included in the first unit area PU1 may be greater than the sum of the planar areas of the pixel areas PXA1-1, PXA2-1, and PXA3-1. The planar area of the transmissive area TA2 included in the second unit area PU2 may be greater than the sum of the planar areas of the pixel areas PXA1-2, PXA2-2, and PXA3-2. Based on the total area of the transmissive area TA and the pixel area PXA, the planar area of the transmissive area TA may be about 60% or more. In the first unit area PU1, based on the total area of the transmissive area TA1 and the pixel areas PXA1-1, PXA2-1, and PXA3-1, the planar area of the transmissive area TA1 may be about 60% or more. In the second unit area PU2, based on the total area of the transmissive area TA2 and the pixel areas PXA1-2, PXA2-2, and PXA3-2, the planar area of the transmissive area TA2 may be about 60% or more. The display device according to one or more embodiments may include a transmissive area larger than the emission area, such that the transmittance of the display device increases and the display device can be used as a transparent display device.

[0091] The grid line MSL may overlap with the non-pixel area NPXA of the display area DA. The grid line MSL may be included in the sensing patterns SP1 and SP2 (see Figure 8 ), and the sensing patterns SP1 and SP2 are included in the sensing electrodes SE1 and SE2 (see Figure 8 ) of the input sensor IS (see Figure 8 ) which will be described later in more detail. The shape and arrangement of the grid line MSL will be described in more detail later.

[0092] Referring again to Figure 3A , the gate driving circuit GDC may be disposed in the non-display area NDA. The gate driving circuit GDC may be integrated with the display panel DP by an oxide silicon gate driving circuit (OSG) process and / or an amorphous silicon gate driving circuit (ASG) process.

[0093] Figure 4 is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure.

[0094] Figure 4 As an example, the circuit diagram of one pixel PXij of the unit area PU (see Figure 3A ) is illustrated.

[0095] Referring to Figure 4, the pixel PXij may include a pixel circuit PC and a light-emitting element OLED. The pixel circuit PC may include a plurality of transistors T1 to T3 and a capacitor Cst.

[0096] The plurality of transistors T1 to T3 may be formed by a low-temperature polysilicon (LTPS) process or a low-temperature polycrystalline oxide (LTPO) process. Each of the first transistor T1 to the third transistor T3 may include a silicon semiconductor and / or an oxide semiconductor. Here, the oxide semiconductor may include a crystalline oxide semiconductor and / or an amorphous oxide semiconductor, and the silicon semiconductor may include amorphous silicon and / or polysilicon, etc., but is not limited to any one embodiment.

[0097] Hereinafter, each of the first transistor T1 to the third transistor T3 is described as an N-type transistor, but is not limited thereto. For example, each of the first transistor T1 to the third transistor T3 may be a P-type transistor or an N-type transistor according to the applied signal. Here, the source and drain of the P-type transistor may correspond to the drain and source of the N-type transistor, respectively.

[0098] Figure 4 As an example, the pixel PXij connected to the i-th scan line SCLi, the i-th sense line SSLi, the j-th data line DLj, and the j-th reference line IRj is illustrated.

[0099] Figure 4 The pixel PXij illustrated in may correspond to any one of the pixels included in the cell region PU (see Figure 3A ). The pixel circuit PC may include a first transistor T1 (e.g., a driving transistor), a second transistor T2 (e.g., a switching transistor), a third transistor T3 (e.g., a sensing transistor), and a capacitor Cst. However, the pixel circuit PC may further include additional transistors and additional capacitors, and is not limited to any one embodiment.

[0100] Each of the first transistor T1 to the third transistor T3 may include a source S1, S2, or S3, a drain D1, D2, or D3, and a gate G1, G2, or G3.

[0101] The light-emitting element OLED may be an organic light-emitting element or an inorganic light-emitting element including an anode (e.g., a first electrode) and a cathode (e.g., a second electrode). The anode of the light-emitting element OLED may receive a first voltage ELVDD through the first transistor T1, and the cathode of the light-emitting element OLED may receive a second voltage ELVSS. The light-emitting element OLED may receive the first voltage ELVDD and the second voltage ELVSS to emit light.

[0102] The first transistor T1 may include a drain D1 receiving a first voltage ELVDD, a source S1 connected to an anode of a light-emitting element OLED, and a gate G1 connected to a capacitor Cst. The first transistor T1 may control a driving current flowing through the light-emitting element OLED from the first voltage ELVDD in response to a value of a voltage stored in the capacitor Cst.

[0103] The second transistor T2 may include a drain D2 connected to the j-th data line DLj, a source S2 connected to the capacitor Cst, and a gate G2 receiving the i-th write scan signal SCi. The second transistor T2 supplies a data voltage Vd to the first transistor T1 in response to the i-th write scan signal SCi.

[0104] The third transistor T3 may include a source S3 connected to the j-th reference line IRj, a drain D3 connected to the anode of the light-emitting element OLED, and a gate G3 receiving the i-th sampling scan signal SSi. The j-th reference line IRj may receive a reference voltage Vr.

[0105] The capacitor Cst may store voltage differences having various values according to an input signal. For example, the capacitor Cst may store a voltage corresponding to a difference between a voltage transmitted from the second transistor T2 and the first voltage ELVDD.

[0106] In the present disclosure, the equivalent circuit of the pixel PXij is not limited to Figure 4 the equivalent circuit illustrated in. According to another embodiment of the present disclosure, the pixel PXij may have various shapes to allow the light-emitting element OLED to emit light.

[0107] Figure 5 and Figure 6 are cross-sectional views of a display device according to one or more embodiments of the present disclosure. Figure 5 is a cross-sectional view taken along line I-I’ of Figure 3B . Figure 6 is a cross-sectional view taken along line II-II’ of Figure 3B . Figure 5 Only a part of the configuration of the display device DD is illustrated, and configurations such as a window WD (see Figure 2 ) are omitted.

[0108] Referring to Figure 5 , the display device DD may include a display panel DP, an input sensor IS disposed on the display panel DP, and an optical layer OSL disposed on the input sensor IS.

[0109] The display panel DP may include a substrate substrate BS, a circuit element layer DP-CL disposed on the substrate substrate BS, a display element layer DP-OLED, and a packaging layer TFE.

[0110] The base substrate BS may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may include an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and / or a perylene resin. In addition, the base substrate BS may include a glass substrate, a metal substrate, and / or an organic / inorganic composite substrate.

[0111] The insulating layer, the semiconductor layer, and the conductive layer may be formed by processes such as coating and deposition. Thereafter, the insulating layer, the semiconductor layer, and / or the conductive layer may be selectively patterned by a photolithography process and / or an etching process. Through this process, a semiconductor pattern, a conductive pattern, and / or signal lines, etc. are formed, and thus a circuit element layer DP-CL is formed. Patterns provided on the same layer (e.g., provided at the same layer) are formed by the same process.

[0112] The circuit element layer DP-CL may include a driving circuit or signal lines constituting a pixel. The display element layer DP-OLED may include a light-emitting element OLED provided in the pixel and a pixel defining layer PDL.

[0113] The circuit element layer DP-CL may include a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, and a fifth insulating layer 50, as well as a conductive pattern. According to one or more embodiments, the first insulating layer 10 to the fourth insulating layer 40 may be inorganic layers including a single layer or multiple layers, and the fifth insulating layer 50 may be an organic layer.

[0114] The light-shielding pattern BML may be provided on the base substrate BS. According to one or more embodiments, the light-shielding pattern BML may be connected to the semiconductor pattern of the overlapping first transistor T1 and receive a signal applied to the semiconductor pattern to provide a synchronous structure under the semiconductor pattern. According to one or more embodiments, the light-shielding pattern BML may include sequentially stacked metal layers, where the first layer may include titanium and the second layer may include copper.

[0115] The first insulating layer 10 may be provided on the base substrate BS to cover the light-shielding pattern BML. According to one or more embodiments, the first insulating layer 10 may include sequentially stacked inorganic layers, where the first layer may include silicon nitride and the second layer may include silicon oxide.

[0116] The semiconductor pattern of the first transistor T1 may be provided on the first insulating layer 10. The semiconductor pattern may include a source region S1, a channel region A1 (or an active region), and a drain region D1. According to one or more embodiments, the semiconductor pattern may include indium gallium zinc oxide (IGZO).

[0117] The second insulating layer 20 may be disposed on the first insulating layer 10 and the semiconductor pattern, and between the semiconductor pattern and the gate G1. The second insulating layer 20 may expose an area of the semiconductor pattern other than the active region A1. The second insulating layer 20 may be patterned using the gate G1 as a mask. According to one or more embodiments, the second insulating layer 20 may include silicon oxide.

[0118] The gate G1 may be disposed on the second insulating layer 20. According to one or more embodiments, the gate G1 may include sequentially stacked metal layers, where the first layer may include titanium and the second layer may include copper.

[0119] The third insulating layer 30 may be disposed on the first insulating layer 10 and the second insulating layer 20 to cover the gate G1, and in one or more embodiments, to cover the semiconductor pattern exposed from the gate G1. According to one or more embodiments, the third insulating layer 30 may include silicon oxynitride.

[0120] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the source region S1 through contact holes defined in the third insulating layer 30 and the second insulating layer 20. According to one or more embodiments, the first connection electrode CNE1 may include sequentially stacked metal layers, where the first layer may include titanium, the second layer may include copper, and the third layer may include indium tin oxide (ITO).

[0121] The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first connection electrode CNE1. According to one or more embodiments, the fourth insulating layer 40 may include silicon nitride. A layer containing silicon nitride may have a higher film density compared to a layer containing silicon oxide and / or silicon oxynitride, thereby reducing the transmittance. Therefore, in order to increase the transmittance of the transparent display device DD according to the present disclosure, it may be necessary to remove the silicon nitride from the transmissive region TA.

[0122] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through contact holes defined in the fourth insulating layer 40. According to one or more embodiments, the second connection electrode CNE2 may include the same material as the first connection electrode CNE1. The display panel DP according to one or more embodiments may omit the second connection electrode CNE2 and is not limited to any one embodiment.

[0123] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. In one or more embodiments, the fifth insulating layer 50 may include an organic material. For example, the fifth insulating layer 50 may include photosensitive polyimide (PSPI).

[0124] The display element layer DP-OLED may be disposed on the fifth insulating layer 50. The display element layer DP-OLED may include a light-emitting element OLED and a pixel defining layer PDL. The light-emitting element OLED may include a first electrode AE, a functional layer FNL, and a second electrode CE. The functional layer FNL of the light-emitting element OLED according to one or more embodiments may include at least one emission layer.

[0125] The pixel defining layer PDL may be disposed on the fifth insulating layer 50 to at least partially cover the first electrode AE of the light-emitting element OLED disposed on the fifth insulating layer 50. The pixel defining layer PDL may include an organic material. For example, the pixel defining layer PDL may include photosensitive polyimide (PSPI). The pixel defining layer PDL may include a light-emitting opening PDL-OP. The light-emitting openings PDL-OP of the pixel defining layer PDL may be provided in plurality, and each of the light-emitting openings PDL-OP may be defined as Figure 3B the emission region described in

[0126] The first electrode AE of the light-emitting element OLED is disposed on the fifth insulating layer 50. The light-emitting opening PDL-OP of the pixel defining layer PDL may expose at least a portion of the first electrode AE. According to one or more embodiments, the first electrode AE may include a conductive material layer stacked in sequence. For example, the first electrode AE may include a three-layer conductive material layer. The first layer of the first electrode AE may include indium tin oxide (ITO), the second layer may include silver, and the third layer may include indium tin oxide (ITO).

[0127] The functional layer FNL of the light-emitting element OLED may include at least one organic material layer. The functional layer FNL may include at least one emission layer. The emission layer may generate light having a specific wavelength. The emission layer may include an organic light-emitting material and / or an inorganic light-emitting material.

[0128] The functional layer FNL may further include a hole control layer and an electron control layer. At least one organic material layer included in the functional layer FNL may be commonly disposed in the emission region and the non-emission region. At least one organic material layer included in the functional layer FNL may be commonly disposed in each pixel. In the present disclosure, a layer provided as a common layer may be entirely disposed in the display area DA (see Figure 3A ) and the non-display area NDA (see Figure 3A ). A layer provided as a common layer may be defined as a "common layer".

[0129] The second electrode CE of the light-emitting element OLED can be disposed on the functional layer FNL. According to one or more embodiments, the second electrode CE can include any suitable conductive material known to those skilled in the art.

[0130] The encapsulation layer TFE can be disposed on the display element layer DP-OLED to protect the light-emitting element OLED. The encapsulation layer TFE can include an inorganic layer and an organic layer disposed between the inorganic layers. The inorganic layer can protect the light-emitting element OLED from moisture and / or oxygen, and the organic layer can protect the light-emitting element OLED from foreign substances such as dust particles.

[0131] The inorganic layer can prevent external moisture and / or oxygen from penetrating into the functional layer FNL of the light-emitting element OLED. The inorganic layer can include silicon nitride, silicon oxide, and / or a combination thereof. The inorganic layer can be formed by a deposition process.

[0132] The organic layer can provide a flat surface on the inorganic layer. The ripples formed on the top surface of the inorganic layer or the particles present on the inorganic layer can be covered by the organic layer to prevent the surface condition of the top surface of the inorganic layer from affecting the components disposed on the organic layer. The organic layer can include an organic material.

[0133] The input sensor IS can include a plurality of conductive patterns. The input sensor IS can include at least one conductive layer (or at least one sensor conductive layer) including a plurality of conductive patterns and at least one insulating layer (or at least one sensor insulating layer). In this embodiment, the input sensor IS can include a first insulating layer IS-IL1 (or a first sensor insulating layer), a first conductive layer IS-CL1 (or a first sensor conductive layer), a second insulating layer IS-IL2 (or a second sensor insulating layer), a second conductive layer IS-CL2 (or a second sensor conductive layer), and a third insulating layer IS-IL3 (or a third sensor insulating layer). In Figure 5 which, the plurality of conductive patterns provided in each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 are briefly illustrated.

[0134] The first insulating layer IS-IL1 may be directly disposed on the display panel DP. The first insulating layer IS-IL1 may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. Each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may have a single-layer structure or a multi-layer structure in which a plurality of layers are stacked in the third direction DR3. The wires of the first conductive layer IS-CL1 and the wires of the second conductive layer IS-CL2 may be connected to each other or may not be connected to each other through contact holes passing through the second insulating layer IS-IL2 depending on their positions.

[0135] Each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, and / or an alloy thereof. The transparent conductive layer may include transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), and / or indium zinc tin oxide (IZTO). In addition, the transparent conductive layer may include conductive polymers such as PEDOT, metal nanowires, and / or graphene.

[0136] Each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 having a multi-layer structure may include a metal layer. The metal layer may have a three-layer structure of titanium / aluminum / titanium. The conductive layer having a multi-layer structure may include at least one metal layer and at least one transparent conductive layer. The second insulating layer IS-IL2 may be disposed on the first insulating layer IS-IL1 and between the first conductive layer IS-CL1 and the second conductive layer IS-CL2. In this specification, the second insulating layer IS-IL2 disposed between the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may be described as a "sensing insulating layer". The third insulating layer IS-IL3 may cover the second conductive layer IS-CL2. In one or more embodiments of the present disclosure, the first insulating layer IS-IL1 may be omitted. Each of the second insulating layer IS-IL2 and the third insulating layer IS-IL3 may include an inorganic layer and / or an organic layer.

[0137] The optical layer OSL may convert the color of light provided from the display panel DP. The optical layer OSL may include a light control pattern and a structure for improving the light conversion efficiency.

[0138] The optical layer OSL can be disposed on the input sensor IS. The optical layer OSL can include a light control layer CCL, a color filter layer CFL, a base layer BL, a second barrier layer CAP2, and a filling layer FML. In one or more embodiments, the optical layer OSL may further include a low refractive index layer (not shown). In this specification, the optical layer OSL may be referred to as the upper panel.

[0139] The light control layer CCL can be disposed on the display element layer DP - OLED including the light emitting element OLED. For example, the second barrier layer CAP2 of the optical layer OSL can be disposed on the input sensor IS, and the light control layer CCL can be disposed on the second barrier layer CAP2. The light control layer CCL can include a bank BMP, a first light control pattern CCP - R, and a first barrier layer CAP1.

[0140] The bank BMP can include a base resin and additives. Generally, the base resin can include various resin compositions known as binders. The additives can include a coupling agent and / or a photoinitiator. The additives can further include a dispersant.

[0141] The bank BMP can include a black colorant to block light. The bank BMP can include a black dye and / or a black pigment mixed with the base resin. In one or more embodiments, the black component can include carbon black and / or can include a metal such as chromium or its oxide.

[0142] The bank BMP can include a first bank opening BOH1 corresponding to the light emitting opening PDL - OP. In a plan view, the first bank opening BOH1 can overlap with the light emitting opening PDL - OP and have a planar area larger than the planar area of the light emitting opening PDL - OP. That is, the first bank opening BOH1 can have a planar area larger than the planar area of the first emission region EA1 (see Figure 6 ) defined by the light emitting opening PDL - OP. In this specification, "corresponding" means that two components overlap with each other when observed in the third direction DR3 of the display panel DP, but is not limited to the same area.

[0143] The first light control pattern CCP - R can be disposed within the first bank opening BOH1. The first light control pattern CCP - R can change the optical characteristics of the source light.

[0144] The first light control pattern CCP - R can include quantum dots that change the optical characteristics of the source light. The first light control pattern CCP - R can include first quantum dots that convert the source light into light having a wavelength different from the wavelength of the source light. In the first light control pattern CCP - R overlapping with the first pixel region PXA1, the first quantum dots can convert the source light into red light.

[0145] In this specification, a "quantum dot" refers to a crystal of a semiconductor compound. Quantum dots can emit light with various emission wavelengths depending on the size of the crystal. By adjusting the elemental ratio in the quantum dot compound, quantum dots can emit light with various emission wavelengths.

[0146] The diameter of the quantum dot can be, for example, about 1 nm to about 10 nm.

[0147] Quantum dots can be synthesized by a wet chemical process, a metalorganic chemical vapor deposition process, a molecular beam epitaxy process, and / or a similar process.

[0148] The wet chemical process can be a method of growing quantum dot particle crystals after mixing an organic solvent and a precursor material. When the crystals grow, the organic solvent can naturally act as a dispersant that coordinates with the surface of the quantum dot crystals and can control the growth of the crystals. Therefore, the wet chemical process can be easier than vapor deposition methods such as metalorganic chemical vapor deposition (MOCVD) and / or molecular beam epitaxy (MBE), and the growth of quantum dot particles can be controlled by a low-cost process.

[0149] The core of the quantum dot can be selected from group II-VI compounds, I-II-VI compounds, II-IV-VI compounds, I-II-IV-VI compounds, III-V compounds, III-VI compounds, I-III-VI compounds, III-II-V compounds, II-IV-V compounds, IV-VI compounds, group IV elements, group IV compounds, and / or combinations thereof.

[0150] The II-VI group compounds can be selected from binary compounds, ternary compounds, and quaternary compounds. The binary compounds are selected from the group consisting of CdSe, CdTe, CdS, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and combinations thereof; the ternary compounds are selected from the group consisting of CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS, and combinations thereof; the quaternary compounds are selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe, and combinations thereof. The II-VI group compounds can further include Group I metals and / or Group IV elements. The I-II-VI group compounds can be selected from CuSnS and CuZnS, and the II-IV-VI group compounds can be selected from ZnSnS, etc. The I-II-IV-VI group compounds can be selected from quaternary compounds, and the quaternary compounds are selected from the group consisting of Cu2ZnSnS2, Cu2ZnSnS4, Cu2ZnSnSe4, Ag2ZnSnS2, and mixtures thereof.

[0151] The III-VI group compounds can include binary compounds such as In2S3 and In2Se3; ternary compounds such as InGaS3 and InGaSe3; or any combination thereof.

[0152] The I-III-VI group compounds can be selected from ternary compounds and quaternary compounds. The ternary compounds are selected from the group consisting of AgInS, AgInS2, CuInS, CuInS2, AgGaS2, CuGaS2, CuGaO2, AgGaO2, AgAlO2, and mixtures thereof, and the quaternary compounds such as AgInGaS2 and CuInGaS2.

[0153] III-V compounds can be selected from binary compounds, ternary compounds, and quaternary compounds. The binary compounds are selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and combinations thereof; the ternary compounds are selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InAlP, InNP, InNAs, InNSb, InPAs, InPSb, and combinations thereof; the quaternary compounds are selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and combinations thereof. The III-V compounds can further include Group II metals. For example, InZnP etc. can be selected as III-II-V compounds.

[0154] IV-VI compounds can be selected from binary compounds, ternary compounds, and quaternary compounds. The binary compounds are selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe, and combinations thereof; the ternary compounds are selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and combinations thereof; the quaternary compounds are selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe, and combinations thereof.

[0155] Examples of II-IV-V compounds can be ternary compounds selected from the group consisting of ZnSnP, ZnSnP2, ZnSnAs2, ZnGeP2, ZnGeAs2, CdSnP2, and CdGeP2, and mixtures thereof.

[0156] Group IV elements can be selected from the group consisting of Si, Ge, and combinations thereof. Group IV compounds can be binary compounds selected from the group consisting of SiC, SiGe, and combinations thereof.

[0157] Each element included in multi-component compounds such as binary compounds, ternary compounds, and quaternary compounds can exist in the particles at a uniform concentration or a non-uniform concentration. That is, the above chemical formulas can refer to the types of elements included in the compounds, and the element ratios in the compounds can be different from each other. For example, AgInGaS2 can represent AgIn x Ga1-x S2 (where x is a real number between 0 and 1).

[0158] Here, the binary compound, ternary compound, and quaternary compound may exist in the particles at a uniform concentration, or may exist in the particles in a state where the concentration distribution is divided into partially different states. Alternatively, the quantum dots may have a core-shell structure in which one quantum dot is around other quantum dots (e.g., surrounding other quantum dots). The core-shell structure may have a concentration gradient in which the element present in the shell has a gradually decreasing concentration towards the core.

[0159] In one or more embodiments, the quantum dots may have a core-shell structure including a core containing the above-described nanocrystals and a shell surrounding the core. The shell of the quantum dots may serve as a protective layer to prevent or protect the core from chemical changes and thus maintain semiconductor characteristics, and / or may serve as a charging layer for imparting electrophoretic characteristics to the quantum dots. The shell may be a single layer or multiple layers. For example, the shell of the quantum dots may include oxides of metals or non-metals, semiconductor compounds, and / or combinations thereof.

[0160] For example, the oxides of metals or non-metals may include binary compounds such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, and / or NiO, or ternary compounds such as MgAl2O4, CoFe2O4, NiFe2O4, and / or CoMn2O4, but the present disclosure is not limited thereto.

[0161] In addition, the semiconductor compounds may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, and AlSb, etc., but the present disclosure is not limited thereto.

[0162] The quantum dots may have a full width at half maximum (FWHM) of the emission wavelength spectrum of about 45 nm or less, preferably about 40 nm or less, and more preferably about 30 nm or less. Within this range, color purity or color reproducibility can be improved. In addition, the light emitted by the quantum dots can be emitted in all directions to improve the optical viewing angle.

[0163] In addition, the quantum dots have a shape commonly used in the art, and the shape is not particularly limited. However, the quantum dots may have a spherical shape, a pyramid shape, a multi-arm shape, a cubic nanoparticle shape, a nanotube shape, a nanowire shape, a nanofiber shape, and / or a nanoplate shape, etc.

[0164] The band gap of the quantum dots can be adjusted by adjusting the size of the quantum dots or the elemental ratio in the quantum dot compound, and thus, light having various wavelengths can be obtained from the quantum dot emission layer. Accordingly, the quantum dots (quantum dots of different sizes or quantum dots having different elemental ratios in the quantum dot compound) as described above can be used to implement a light-emitting element that emits light having various wavelengths. Specifically, the size of the quantum dots or the control of the elemental ratio in the quantum dot compound can be selected to emit red, green, and / or blue light. In addition, the quantum dots can be configured to emit white light by combining light having various colors.

[0165] In one or more embodiments, the quantum dots included in the first light control pattern CCP-R overlapping with the first pixel region PXA1 may have a red emission color. As the particle size of each of the quantum dots decreases, light in the short wavelength region can be emitted. For example, the particle size of each of the quantum dots emitting green light among the quantum dots having the same core may be smaller than the particle size of each of the quantum dots emitting red light. In addition, the particle size of each of the quantum dots emitting blue light among the quantum dots having the same core may be smaller than the particle size of each of the quantum dots emitting green light. However, the present disclosure is not limited thereto, and even among the quantum dots having the same core, the particle size can be adjusted according to the material used for forming the shell and the thickness of the shell.

[0166] When the quantum dots have various emission colors such as blue, red, and / or green colors, the quantum dots having different emission colors may have different core materials.

[0167] The first light control pattern CCP-R may further include a scatterer. The first light control pattern CCP-R may include first quantum dots that convert blue light into red light and a scatterer that scatters light.

[0168] The scatterer may be inorganic particles. For example, the scatterer may include at least one of TiO2, ZnO, Al2O3, SiO2, and hollow silica. The scatterer may include TiO2, ZnO, Al2O3, SiO2, and / or hollow silica, and / or may be a mixture of two or more materials selected from TiO2, ZnO, Al2O3, SiO2, and hollow silica.

[0169] The first light control pattern CCP-R may include a base resin in which the first quantum dots and the scatterer are dispersed. The base resin may be a medium in which the first quantum dots and / or the scatterer are dispersed. Generally, the base resin may include various resin compositions called binders. For example, the base resin may include acrylic resins, urethane resins, silicone resins, and / or epoxy resins. The base resin may be a transparent resin.

[0170] In this embodiment, the first light control pattern CCP-R can be formed by an inkjet process. The liquid composition can be provided within the first bank opening BOH1. The volume of the composition polymerized by a thermal curing process or a photo-curing process can be reduced after curing.

[0171] The light control layer CCL can include a first barrier layer CAP1 disposed on one surface of the first light control pattern CCP-R and the bank BMP. The first barrier layer CAP1 can be used to prevent or reduce the penetration of moisture and / or oxygen (hereinafter referred to as "moisture / oxygen"), and improve the optical characteristics of the optical layer OSL by adjusting the refractive index. The first barrier layer CAP1 can be disposed on one surface of the upper portion or the lower portion of the first light control pattern CCP-R to prevent the first light control pattern CCP-R from being exposed to moisture / oxygen. In particular, the quantum dots included in the first light control pattern CCP-R can be prevented from being exposed to moisture / oxygen. The first barrier layer CAP1 can also protect the first light control pattern CCP-R from the influence of external shocks.

[0172] In one or more embodiments, the first barrier layer CAP1 can be disposed to be spaced apart (e.g., separated) from the display element layer DP-OLED, with the first light control pattern CCP-R therebetween. That is, the first barrier layer CAP1 can be disposed on the top surface of the first light control pattern CCP-R. In one or more embodiments, the optical layer OSL can include a second barrier layer CAP2 disposed between the first light control pattern CCP-R and the display element layer DP-OLED. The first barrier layer CAP1 can cover the top surface of the first light control pattern CCP-R adjacent to the low refractive index layer, and the second barrier layer CAP2 can cover the bottom surface of the first light control pattern CCP-R adjacent to the display element layer DP-OLED. In this specification, the "top surface" can be the surface disposed in the upper portion based on the third direction DR3, and the "bottom surface" can be the surface disposed in the lower portion based on the third direction DR3.

[0173] In addition, the first barrier layer CAP1 and the second barrier layer CAP2 can cover one surface of the bank BMP in addition to covering the first light control pattern CCP-R.

[0174] The first barrier layer CAP1 may cover one surface of the bank BMP adjacent to the low refractive index layer and one surface of the first light control pattern CCP-R adjacent to the low refractive index layer. The first barrier layer CAP1 may be directly disposed on the lower portion of the low refractive index layer. The second barrier layer CAP2 may be directly disposed on the input sensor IS disposed on the upper portion of the encapsulation layer TFE. In one or more other embodiments, the second barrier layer CAP2 may be directly disposed on the upper portion of the encapsulation layer TFE. The light control layer CCL may be disposed on the display element layer DP-OLED, the encapsulation layer TFE, and the input sensor IS, wherein the second barrier layer CAP2 is interposed between the light control layer CCL and the display element layer DP-OLED, the encapsulation layer TFE, and the input sensor IS. The light control patterns CCP-R, CCP-G, and CCP-B of the light control layer CCL (e.g., see Figure 6 ) may be formed on the second barrier layer CAP2 disposed on the encapsulation layer TFE and the input sensor IS through a continuous process.

[0175] Each of the first barrier layer CAP1 and the second barrier layer CAP2 may include an inorganic material. In the display device DD according to one or more embodiments, the first barrier layer CAP1 may include silicon oxynitride (SiO x N y ). Each of the first barrier layer CAP1 and the second barrier layer CAP2 may include silicon oxynitride. However, the present disclosure is not limited thereto, and each of the first barrier layer CAP1 and the second barrier layer CAP2 may include silicon oxide (SiO x ) and / or silicon nitride (SiN x ). In one or more embodiments, the first barrier layer CAP1 disposed on the upper portion of the first light control pattern CCP-R may include silicon oxynitride, and the second barrier layer CAP2 disposed on the lower portion of the first light control pattern CCP-R may include silicon oxide.

[0176] The color filter layer CFL may be disposed on the light control layer CCL. The color filter layer CFL may include at least one color filter. The color filter may transmit light within a specific wavelength range and block light outside the specific wavelength range. The first color filter CF1 corresponding to the first pixel region PXA1 may transmit red light and block green light and blue light.

[0177] The first color filter CF1 may include a base resin and dyes and / or pigments dispersed in the base resin. The base resin may be a medium in which the dyes and / or pigments are dispersed. Generally, the base resin may include various resin compositions called binders.

[0178] The first color filter CF1 may have a uniform thickness within the first pixel region PXA1. The light that is converted from the source light, which is blue light, to red light by the first light control pattern CCP-R may be provided to the outside with a uniform brightness within the first pixel region PXA1.

[0179] The optical layer OSL may further include a filling layer FML disposed between the light control layer CCL and the color filter layer CFL. In one or more embodiments, the filling layer FML may be filled between the light control layer CCL and the color filter layer CFL. The filling layer FML may be directly disposed on the first barrier layer CAP1, and the color filter layer CFL may be directly disposed on the filling layer FML. The bottom surface of the filling layer FML may be in contact with the top surface of the first barrier layer CAP1, and the top surface of the filling layer FML may be in contact with the bottom surfaces of the color filters CF1, CF2, and CF3 of the color filter layer CFL.

[0180] The filling layer FML may serve as a buffer layer between the light control layer CCL and the color filter layer CFL. In one or more embodiments, the filling layer FML may perform functions such as shock absorption and may allow an increase in the strength of the display device DD. The filling layer FML may be made of a filling resin including a polymer resin. For example, the filling layer FML may be made of a filling layer resin including an acrylic resin and / or an epoxy resin.

[0181] The filling layer FML may serve as an optical functional layer disposed between the light control layer CCL and the color filter layer CFL to improve light extraction efficiency or prevent or reduce the incidence of reflected light into the light control layer CCL. The filling layer FML may be a layer having a refractive index lower than that of adjacent layers.

[0182] In one or more embodiments, the display device DD may further include a base layer BL disposed on the color filter layer CFL. The base layer BL may be a member that provides a reference surface on which the color filter layer CFL, the low refractive index layer, and the light control layer CCL are disposed. The base layer BL may include a glass substrate, a metal substrate, and / or a plastic substrate, etc. However, the present disclosure is not limited thereto. For example, the base layer BL may be an inorganic layer, an organic layer, and / or a composite layer. In addition, different from the illustrated configuration, in one or more embodiments, the base layer BL may be omitted.

[0183] In one or more embodiments, an anti-reflection layer may be disposed on the base layer BL. The anti-reflection layer may be a layer that reduces the reflectance of external light incident from the outside. The anti-reflection layer may be a layer that selectively transmits light emitted from the display panel DP. In one or more embodiments, the anti-reflection layer may be a single layer including dyes and / or pigments dispersed in a base resin. The anti-reflection layer may be provided as a continuous layer that completely overlaps the entire pixel region PXA (see Figure 3B )

[0184] The anti-reflection layer may not include a polarization layer. Accordingly, the light passing through the anti-reflection layer and incident on the display element layer DP-OLED may be unpolarized light. The display element layer DP-OLED may receive the unpolarized light from the upper portion of the anti-reflection layer.

[0185] Reference Figure 6 , the display panel DP may include a base substrate BS and a circuit element layer DP-CL disposed on the base substrate BS. The circuit element layer DP-CL may be disposed on the base substrate BS. The circuit element layer DP-CL may include an insulating layer, a semiconductor pattern, a conductive pattern, and / or signal lines. The insulating layer, semiconductor layer, and conductive layer may be disposed on the base substrate BS by means such as coating and / or deposition, and subsequently, the insulating layer, semiconductor layer, and conductive layer may be selectively patterned through a plurality of photolithography processes. Thereafter, the semiconductor pattern, conductive pattern, and signal lines included in the circuit element layer DP-CL may be provided. In one or more embodiments, the circuit element layer DP-CL may include transistors, buffer layers, and / or a plurality of insulating layers.

[0186] The light-emitting element OLED according to one or more embodiments may include a first electrode AE, a second electrode CE facing the first electrode AE, and a functional layer FNL disposed between the first electrode AE and the second electrode CE. The functional layer FNL included in the light-emitting element OLED may at least include an emission layer. The emission layer may include an organic light-emitting material and / or quantum dots. The functional layer FNL may further include a hole control layer and an electron control layer. In one or more embodiments, the light-emitting element OLED may further include a capping layer disposed on the second electrode CE.

[0187] The pixel defining layer PDL may be disposed on the circuit element layer DP-CL and may cover a part of the first electrode AE. A light-emitting opening PDL-OP may be defined in the pixel defining layer PDL. The light-emitting opening PDL-OP of the pixel defining layer PDL may expose at least a part of the first electrode AE. In this embodiment, the emission regions EA1, EA2, and EA3 may be defined to correspond to the partial regions of the first electrode AE exposed by the light-emitting opening PDL-OP.

[0188] The display element layer DP-OLED may include a first emission region EA1, a second emission region EA2, and a third emission region EA3. The first emission region EA1, the second emission region EA2, and the third emission region EA3 may be regions divided by the pixel defining layer PDL. The first emission region EA1, the second emission region EA2, and the third emission region EA3 may respectively correspond to a first pixel region PXA1, a second pixel region PXA2, and a third pixel region PXA3.

[0189] The emission regions EA1, EA2, and EA3 may overlap with the pixel regions PXA1, PXA2, and PXA3, respectively. When viewed in a plane, the planar area of each of the pixel regions PXA1, PXA2, and PXA3 divided by the color filters CF1, CF2, and CF3 may be greater than the planar area of each of the emission regions EA1, EA2, and EA3 divided by the pixel defining layer PDL. However, the present disclosure is not limited thereto, and the planar area of each of the pixel regions PXA1, PXA2, and PXA3 may be substantially the same as the planar area of the corresponding one of the emission regions EA1, EA2, and EA3.

[0190] In the light-emitting element OLED, the first electrode AE may be disposed on the circuit element layer DP-CL. The first electrode AE may be an anode or a cathode. In addition, the first electrode AE may be a pixel electrode. The second electrode CE may be a transmissive electrode, a semi-transmissive electrode, and / or a reflective electrode. In one or more embodiments, the transmissive region TA may be defined by at least the transmissive opening T-OP defined in the pixel defining layer PDL. In addition, in one or more embodiments, the optical layer OSL may further include a filling pattern FLP overlapping with the transmissive region TA.

[0191] Figure 7 is a cross-sectional view of a light-emitting element according to one or more embodiments of the present disclosure. In Figure 7 According to Figure 5 and Figure 6 the configuration of the functional layer FNL in the light-emitting element OLED according to one or more embodiments illustrated in Figure 7 As an example, a light-emitting element OLED including a plurality of light-emitting stacks ST1, ST2, ST3, and ST4 disposed between the first electrode AE and the second electrode CE is illustrated.

[0192] Referring to Figure 7 , according to one or more embodiments, the light-emitting element OLED may include a first electrode AE, a second electrode CE facing the first electrode AE, and a first light-emitting stack ST1, a second light-emitting stack ST2, a third light-emitting stack ST3, and a fourth light-emitting stack ST4 disposed between the first electrode AE and the second electrode CE. Figure 7 An example in which the light-emitting element OLED includes four light-emitting stacks is illustrated, but the number of light-emitting stacks included in the light-emitting element OLED may be less than or more than four.

[0193] The light-emitting element OLED may further include a first charge generation layer CGL1, a second charge generation layer CGL2, and a third charge generation layer CGL3 disposed between the first light-emitting stack ST1, the second light-emitting stack ST2, the third light-emitting stack ST3, and the fourth light-emitting stack ST4.

[0194] When a voltage is applied, each of the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may generate charges (e.g., electrons and holes) by forming an adhesive via a redox reaction. Thereafter, the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may respectively supply the generated charges to the adjacent light-emitting stacks ST1, ST2, ST3, and ST4. The first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may double the efficiency of the current generated in the adjacent light-emitting stacks ST1, ST2, ST3, and ST4 and may be used to control the charge balance between the adjacent light-emitting stacks ST1, ST2, ST3, and ST4.

[0195] Each of the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may include an n-type layer and a p-type layer. The first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may have a structure in which the n-type layer and the p-type layer are combined with each other. However, the present disclosure is not limited thereto, and the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may include only one of the n-type layer and the p-type layer. The n-type layer may be a charge generation layer that supplies electrons to the adjacent stack. The n-type layer may be a layer in which an n-type dopant is doped in a base material. The p-type layer may be a charge generation layer that supplies holes to the adjacent stack.

[0196] In one or more embodiments, the thickness of each of the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may be in the range from about to about . The concentration of the n-type dopant doped in the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may be about 0.1% or more and about 3% or less and specifically about 1% or less. If the concentration is less than about 0.1%, the effect of the charge balance of the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may not occur. If the concentration is greater than about 3%, the light efficiency of the light-emitting element OLED may deteriorate.

[0197] Each of the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may include a charge generation compound made of an arylamine organic compound, a metal, a metal oxide, a metal carbide, a metal fluoride, and / or a mixture thereof. For example, the arylamine organic compound may include α-NPD, 2-TNATA, TDATA, MTDATA, spiro-TAD, and / or spiro-NPB. The metal may include cesium (Cs), molybdenum (Mo), vanadium (V), titanium (Ti), tungsten (W), barium (Ba), and / or lithium (Li). The metal oxide, metal carbide, and / or metal fluoride may include Re2O7, MoO3, V2O5, WO3, TiO2, Cs2CO3, BaF2, LiF, and / or CsF. However, the materials of the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 are not limited to the above examples.

[0198] Each of the first light-emitting stack ST1, the second light-emitting stack ST2, the third light-emitting stack ST3, and the fourth light-emitting stack ST4 may include an emission layer. The first light-emitting stack ST1 may include a first emission layer BEML-1, the second light-emitting stack ST2 may include a second emission layer BEML-2, the third light-emitting stack ST3 may include a third emission layer BEML-3, and the fourth light-emitting stack ST4 may include a fourth emission layer GEML. Some of the emission layers included in the first light-emitting stack ST1, the second light-emitting stack ST2, the third light-emitting stack ST3, and the fourth light-emitting stack ST4 may emit light having substantially the same color, and some emission layers may emit light having different colors.

[0199] In one or more embodiments, the first emission layer BEML-1, the second emission layer BEML-2, and the third emission layer BEML-3 of the first light-emitting stack ST1, the second light-emitting stack ST2, and the third light-emitting stack ST3 may emit substantially the same first color light. For example, the first color light may be blue light, which is the above-mentioned source light. Therefore, the first emission layer BEML-1, the second emission layer BEML-2, and the third emission layer BEML-3 are also referred to as blue emission layers. The wavelength range of the light emitted from the first emission layer BEML-1, the second emission layer BEML-2, and the third emission layer BEML-3 may be about 420 nm or more and about 480 nm or less.

[0200] The fourth emission layer GEML of the fourth light-emitting stack ST4 may emit a second color light different from the first color light. For example, the second color light may be green light. Therefore, the fourth emission layer GEML is also referred to as a green emission layer. The wavelength range of the light emitted from the fourth emission layer GEML may be about 520 nm or more and about 600 nm or less.

[0201] The light-emitting element OLED can emit light from the first electrode AE toward the second electrode CE (e.g., in the direction of the second electrode CE). In the light-emitting element OLED according to one or more embodiments, each of the plurality of light-emitting stacks ST1, ST2, ST3, and ST4 can include a hole transport region HTR, MHTR1, MHTR2, or MHTR3 and an electron transport region METL1, METL2, METL3, or ETR. The hole transport regions HTR, MHTR1, MHTR2, and MHTR3 can transport holes provided from the first electrode AE or the charge generation layer to the emission layer. The electron transport regions METL1, METL2, METL3, and ETR can transport electrons provided from the second electrode CE or the charge generation layer to the emission layer.

[0202] As an example, the light-emitting element OLED according to one or more embodiments has the following structure, in which, based on the direction of light emission, the hole transport regions HTR, MHTR1, MHTR2, and MHTR3 are respectively disposed below the emission layers BEML-1, BEML-2, BEML-3, and GEML included in the plurality of light-emitting stacks ST1, ST2, ST3, and ST4, and the electron transport regions METL1, METL2, METL3, and ETR are respectively disposed above the emission layers BEML-1, BEML-2, BEML-3, and GEML included in the plurality of light-emitting stacks ST1, ST2, ST3, and ST4. That is, the light-emitting element OLED according to one or more embodiments can have a forward element structure, but is not limited thereto. For example, the light-emitting element OLED can have an inverted structure, in which, based on the direction of light emission, the electron transport regions METL1, METL2, METL3, and ETR are respectively disposed below the emission layers BEML-1, BEML-2, BEML-3, and GEML included in the plurality of light-emitting stacks ST1, ST2, ST3, and ST4, and the hole transport regions HTR, MHTR1, MHTR2, and MHTR3 are respectively disposed above the emission layers BEML-1, BEML-2, BEML-3, and GEML included in the plurality of light-emitting stacks ST1, ST2, ST3, and ST4.

[0203] The hole transport regions HTR, MHTR1, MHTR2, and MHTR3 may respectively include a hole injection layer HIL, MHIL1, MHIL2, and MHIL3 and a hole transport layer HTL, MHTL1, MHTL2, and MHTL3 disposed on the hole injection layers HIL, MHIL1, MHIL2, and MHIL3. The hole transport layers HTL, MHTL1, MHTL2, and MHTL3 may be in contact with the bottom surface of the emission layer. However, the present disclosure is not limited thereto, and the hole transport regions HTR, MHTR1, MHTR2, and MHTR3 may further include a hole-side additional layer disposed on the hole transport layers HTL, MHTL1, MHTL2, and MHTL3. The hole-side additional layer may include at least one of a hole buffer layer, a light emission assist layer, and an electron blocking layer. The hole buffer layer may be a layer that compensates for the resonance distance according to the wavelength of light emitted from the emission layer to improve the light emission efficiency. The electron blocking layer may be a layer for preventing electrons from being injected from the electron transport region into the hole transport region.

[0204] Each of the electron transport regions METL1, METL2, METL3, and ETR may include an electron transport layer. Each of the electron transport regions METL1, METL2, METL3, and ETR may further include an electron injection layer disposed on the electron transport layer. For example, the fourth electron transport region ETR included in the fourth light-emitting stack ST4 may further include a fourth electron injection layer EIL disposed on the fourth electron transport layer ETL. Each of the electron transport regions METL1, METL2, METL3, and ETR may further include an electron-side additional layer disposed between the electron transport layer and the emission layer. The electron-side additional layer may include at least one of an electron buffer layer and a hole blocking layer.

[0205] In a light-emitting element OLED according to one or more embodiments, the first electrode AE may be a reflective electrode. For example, the first electrode AE may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, In, Zn, Sn, and / or a compound thereof (e.g., LiF) or a mixture thereof (e.g., a mixture of Ag and Mg) each having a high reflectivity, or a multilayer structure such as LiF / Ca or LiF / Al. Alternatively, the first electrode AE may include a reflective layer made of the above materials and a transparent conductive film including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and / or indium tin zinc oxide (ITZO). For example, the first electrode AE may have a two-layer structure of ITO / Ag and a three-layer structure of ITO / Ag / ITO, but is not limited thereto. In addition, this embodiment is not limited thereto. For example, the first electrode AE may include the above metal materials, a combination of two or more metal materials selected from the above metal materials, or oxides of the above metal materials. The thickness of the first electrode AE may be about 70 nm to about 1000 nm. For example, the thickness of the first electrode AE may be about 100 nm to about 300 nm.

[0206] In a light-emitting element OLED according to one or more embodiments, each of the hole transport regions HTR, MHTR1, MHTR2, and MHTR3 may have a single-layer structure made of a single material, a single-layer structure made of a plurality of different materials, or a multilayer structure having a plurality of layers made of a plurality of different materials.

[0207] Each of the hole transport regions HTR, MHTR1, MHTR2, and MHTR3 may be formed by using various methods such as a vacuum deposition method, a spin coating method, a casting method, a Langmuir-Blodgett (LB) method, an inkjet printing method, a laser printing method, and / or a laser-induced thermal imaging (LITI) method.

[0208] Each of the hole transport regions HTR, MHTR1, MHTR2, and MHTR3 may include phthalocyanine compounds such as copper phthalocyanine, N1,N1'-([1,1'-biphenyl]-4,4'-diyl)bis(N1-phenyl-N4,N4-dim-tolylbenzene-1,4-diamine) (DNTPD), 4,4',4''-[tris(3-methylphenyl)phenylamino]triphenylamine (m-MTDATA), 4,4'4''-tris(N,N-diphenylamino)triphenylamine (TDATA), 2-TNATA (4,4',4''-tris[N(2-naphthyl)-N-phenylamino]-triphenylamine), poly(3,4-ethylenedioxythiophene) / poly(4-styrenesulfonate) (PEDOT / PSS), polyaniline / dodecylbenzenesulfonic acid (PANI / DBSA), polyaniline / camphorsulfonic acid (PANI / CSA), polyaniline / poly(4-styrenesulfonate) (PANI / PSS), N,N'-di(naphthalen-1-yl)-N,N'-diphenyl-benzidine (NPB), triphenylamine-containing polyether ketone (TPAPEK), 4-isopropyl-4'-methyldiphenyliodonium [tetrakis(pentafluorophenyl)borate], and / or dipyrazino[2,3-f:2',3'-h]quinoxaline-2,3,6,7,10,11-hexacarbonitrile (HATCN), etc.

[0209] Each of the hole transport regions HTR, MHTR1, MHTR2, and MHTR3 may include carbazole derivatives such as N-phenylcarbazole and polyvinylcarbazole, fluorene derivatives, triphenylamine derivatives such as N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1-biphenyl]-4,4'-diamine (TPd) and 4,4',4''-tris(N-carbazolyl)triphenylamine (TCTA), N,N'-di(naphthalen-1-yl)-N,N'-diphenyl-benzidine (NPB), 4,4'-cyclohexylidenebis[N,N-bis(4-methylphenyl)aniline] (TAPC), 4,4'-bis[N,N'-(3-tolyl)amino]-3,3'-dimethylbiphenyl (HMTPD), and / or mCP (1,3-bis(N-carbazolyl)benzene), etc.

[0210] In addition, each of the hole transport regions HTR, MHTR1, MHTR2, and MHTR3 may include 9-(4-tert-butylphenyl)-3,6-bis(triphenylsilyl)-9H-carbazole (CzSi), 9-phenyl-9H-3,9'-bicarbazole (CCP), or 1,3-bis(1,8-dimethyl-9H-carbazol-9-yl)benzene (mDCP).

[0211] The hole transport regions HTR, MHTR1, MHTR2, and MHTR3 may include the compounds of the above hole transport regions in at least one of the hole injection layers HIL, MHIL1, MHIL2, and MHIL3, the hole transport layers HTL, MHTL1, MHTL2, and MHTL3, and the hole-side additional layers.

[0212] The thickness of each of the hole transport regions HTR, MHTR1, MHTR2, and MHTR3 may be from about 10 nm to about 1000 nm, for example, from about 10 nm to about 500 nm. The thickness of each of the hole injection layers HIL, MHIL1, MHIL2, and MHIL3 may be, for example, from about 5 nm to about 100 nm. Each of the hole transport layers HTL, MHTL1, MHTL2, and MHTL3 may have a thickness of from about 5 nm to about 100 nm. When each of the hole transport regions HTR, MHTR1, MHTR2, and MHTR3 includes a hole-side additional layer, the thickness of the hole-side additional layer may be from about 1 nm to about 100 nm. When each of the hole transport regions HTR, MHTR1, MHTR2, and MHTR3 and each layer included therein have thicknesses satisfying the above ranges, satisfactory hole transport characteristics can be obtained without significantly increasing the driving voltage.

[0213] In addition to the above materials, each of the hole transport regions HTR, MHTR1, MHTR2, and MHTR3 may further include a charge generation material to improve conductivity. The charge generation material may be uniformly or non-uniformly dispersed within the hole transport regions HTR, MHTR1, MHTR2, and MHTR3. For example, the charge generation material may be a p-type dopant. The p-type dopant may include at least one of metal halide compounds, quinone derivatives, metal oxides, and cyano-containing compounds, but is not limited thereto. For example, the p-type dopant may include metal halide compounds such as CuI and RbI, quinone derivatives such as tetracyanoquinodimethane (TCNQ) and 2,3,5,6-tetrafluoro-tetracyanoquinodimethane (F4-TCNQ), and / or metal oxides such as tungsten oxide and molybdenum oxide, but is not limited thereto.

[0214] Each of the blue emission layers BEML-1, BEML-2, and BEML-3 and the green emission layer GEML may include a host material and a dopant material. Each of the blue emission layers BEML-1, BEML-2, and BEML-3 and the green emission layer GEML may include a material containing a carbazole derivative moiety or an amine derivative moiety as a hole-transporting host material. Each of the blue emission layers BEML-1, BEML-2, and BEML-3 and the green emission layer GEML may include a nitrogen-containing aromatic ring structure such as a pyridine derivative moiety, a pyridazine derivative moiety, a pyrimidine derivative moiety, a pyrazine derivative moiety, and / or a triazine derivative moiety as an electron-transporting host material.

[0215] Each of the blue emission layers BEML-1, BEML-2, and BEML-3 and the green emission layer GEML may include an anthracene derivative, a pyrene derivative, a fluoranthene derivative, a chrysene derivative, a dihydrobenz[a]anthracene derivative, and / or a triphenylene derivative as a host material. In addition, each of the blue emission layers BEML-1, BEML-2, and BEML-3 and the green emission layer GEML may further include common materials known in the art as host materials. For example, each of the blue emission layers BEML-1, BEML-2, and BEML-3 and the green emission layer GEML may include bis[2-(diphenylphosphino)phenyl] ether oxide (DPEPO), 4,4'-bis(carbazol-9-yl)biphenyl (CBP), 1,3-bis(carbazol-9-yl)benzene (mCP), 2,8-bis(diphenylphosphoryl)dibenz[b,d]furan (PPF), 4,4',4''-tris(carbazol-9-yl)-triphenylamine (TCTA), or 1,3,5-tris(1-phenyl-1H-benzo[d]imidazol-2-yl)benzene (TPBi) as a host material. However, this embodiment is not limited thereto. For example, tris(8-hydroxyquinolinato)aluminum (Alq3), poly(N-vinylcarbazole) (PVK), 9,10-bis(naphthalen-2-yl)anthracene (ADN), 2-tert-butyl-9,10-bis(naphthalen-2-yl)anthracene (TBADN), distyrylarylene (DSA), 4,4'-bis(9-carbazolyl)-2,2'-dimethyl-biphenyl (CDBP), 2-methyl-9,10-bis(naphthalen-2-yl)anthracene (MADN), hexaphenylcyclotriphosphazene (CP1), 1,4-bis(triphenylsilyl)benzene (UGH2), hexaphenylcyclotrisiloxane (DPSiO3), and / or octaphenylcyclotetrasiloxane (DPSiO4) etc. may be used as host materials.

[0216] In one or more embodiments, each of the blue emission layers BEML-1, BEML-2, and BEML-3 may include styryl derivatives (e.g., 1,4-bis[2-(3-N-ethylcarbazolyl)vinyl]benzene (BCzVB), 4-(di-p-tolylamino)-4'-[(di-p-tolylamino)styryl]stilbene (DPAVB), N-(4-((E)-2-(6-((E)-4-(diphenylamino)styryl)naphthalen-2-yl)vinyl)phenyl)-N-phenylaniline (N-BDAVBi), 4,4'-bis[2-(4-(N,N-diphenylamino)phenyl)vinyl]biphenyl (DPAVBi)), perylene and / or its derivatives (e.g., 2,5,8,11-tetra-tert-butylperylene (TBP)), pyrene and / or their derivatives (e.g., 1,1-dipyrene, 1,4-dipyrenylbenzene, 1,4-bis(N,N-diphenylamino)pyrene) as known fluorescent dopant materials.

[0217] The green emission layer GEML may include known phosphorescent dopant materials. For example, metal complexes containing iridium (Ir), platinum (Pt), osmium (Os), gold (Au), titanium (Ti), zirconium (Zr), hafnium (Hf), europium (Eu), terbium (Tb), and / or thulium (Tm) may be used as phosphorescent dopants. In particular, FIrpic (iridium(III) bis(4,6-difluorophenylpyridinato-N,C2') picolinate), Fir6 (bis(2,4-difluorophenylpyridinato)-tris(1-pyrazolyl)borate iridium(III)), and / or platinum octaethylporphyrin (PtOEP) may be used as phosphorescent dopants.

[0218] Each of the electron transport regions METL1, METL2, METL3, and ETR may have a single-layer structure made of a single material, a single-layer structure made of different materials from each other, or a multi-layer structure including multiple layers made of different materials from each other. For example, at least a part of the electron transport regions METL1, METL2, METL3, and ETR may include an electron transport layer and an electron injection layer.

[0219] Each of the electron transport regions METL1, METL2, METL3, and ETR may be formed by using various methods such as vacuum deposition method, spin coating method, casting method, Langmuir-Blodgett (LB) method, injection printing method, laser printing method, and / or laser-induced thermal imaging (LITI) method.

[0220] The electron transport regions METL1, METL2, METL3, and ETR may include anthracene compounds. However, this embodiment is not limited thereto. For example, each of the electron transport regions METL1, METL2, METL3, and ETR may include, for example, tris(8-hydroxyquinoline) aluminum (Alq3), 1,3,5-tris[(3-pyridinyl)-phenyl-3-yl]benzene, T2T (2,4,6-tris(3'-(pyridin-3-yl)biphenyl-3-yl)-1,3,5-triazine), 2-(4-(N-phenylbenzimidazol-1-yl)phenyl)-9,10-dinaphthoanthracene, 1,3,5-tris(1-phenyl-1H-benzo[d]imidazol-2-yl)benzene (TPBi), 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP), 4,7-diphenyl-1,10-phenanthroline (Bphen), 3-(4-biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole (TAZ), 4-(naphthalen-1-yl)-3,5-diphenyl-4H-1,2,4-triazole (NTAZ), 2-(4-biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (tBu-PBD), bis(2-methyl-8-hydroxyquinoline-N1,O8)-(1,1'-biphenyl-4-olato) aluminum (BAlq), bis(benzoquinolin-10-olato)beryllium (Bebq2), 9,10-di(naphthalen-2-yl)anthracene (ADN), 1,3-bis[3,5-bis(pyridin-3-yl)phenyl]benzene (BmPyPhB), and / or mixtures thereof.

[0221] In addition, each of the electron transport regions METL1, METL2, METL3, and ETR may include metal halides such as LiF, NaCl, CsF, RbCl, RbI, CuI, and / or KI, lanthanide metals such as Yb, and / or co-deposited materials of the above metal halides and lanthanide metals. For example, each of the electron transport regions METL1, METL2, METL3, and ETR may include KI:Yb and / or RbI:Yb, etc. as co-deposited materials. Each of the electron transport regions METL1, METL2, METL3, and ETR may include two or more materials selected from Mg, Ag, Yb, and Al. For example, each of the electron transport regions METL1, METL2, METL3, and ETR may include Mg and / or Yb.

[0222] As the electron transport regions METL1, METL2, METL3, and ETR, metal oxides such as Li2O and BaO, or lithium 8-hydroxyquinoline (Liq), etc. can be used, but the present disclosure is not limited thereto. In addition, each of the electron transport regions METL1, METL2, METL3, and ETR can be made of a mixture of an electron transport material and an organometallic salt having insulating properties. The organometallic salt can be a material having a band gap of about 4 eV or more. For example, the organometallic salt can include metal acetates, metal benzoates, metal acetoacetates, metal acetylacetonates, and / or metal stearates.

[0223] In addition to the above materials, each of the electron transport regions METL1, METL2, METL3, and ETR can further include at least one of 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP) and 4,7-diphenyl-1,10-phenanthroline (Bphen), but the present disclosure is not limited thereto.

[0224] In the electron transport regions METL1, METL2, METL3, and ETR, the compounds in the above electron transport regions can be included in the electron injection layer or the electron transport layer. When the electron transport regions METL1, METL2, METL3, and ETR include an electron-side additional layer, the above materials can be included in the electron-side additional layer. In one or more embodiments, the electron injection layer can be made of two or more materials selected from Mg, Ag, Yb, and Al. The electron injection layer can be made of a mixture of, for example, Mg and Yb.

[0225] The thickness of each of the electron transport regions METL1, METL2, METL3, and ETR can be, for example, about 10 nm to about 150 nm. The thickness of the electron transport layer can be about 0.1 nm to about 100 nm, for example, about 0.3 nm to about 50 nm. When the electron transport layer has a thickness within the above range, satisfactory electron injection characteristics can be achieved without significantly increasing the driving voltage.

[0226] The second electrode CE can be provided on the plurality of light-emitting stacks ST1, ST2, ST3, and ST4. The second electrode CE can be a common electrode. The second electrode CE can be a cathode or an anode, but the present disclosure is not limited thereto. For example, when the first electrode AE is an anode, the second electrode CE can be a cathode, and when the first electrode AE is a cathode, the second electrode CE can be an anode.

[0227] The second electrode CE can be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. When the second electrode CE is a transmissive electrode, the second electrode CE can be made of a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and / or indium tin zinc oxide (ITZO).

[0228] When the second electrode CE is a semi-transmissive electrode or a reflective electrode, the second electrode CE can include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, Yb, W, In, Zn, Sn, and / or their compounds (e.g., LiF) and / or mixtures (e.g., AgYb or MgAg), or a multilayer structure such as LiF / Ca or LiF / Al. Alternatively, the second electrode CE can include a reflective layer or a semi-transmissive layer made of the above materials and a transparent conductive film including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and / or indium tin zinc oxide (ITZO). For example, the second electrode CE can include the above metal materials, a combination of two or more metal materials selected from the above metal materials, or oxides of the above metal materials.

[0229] In one or more embodiments, the second electrode CE can be connected to an auxiliary electrode. When the second electrode CE is connected to the auxiliary electrode, the resistance of the second electrode CE can be reduced.

[0230] In one or more embodiments, a capping layer CPL can be further provided on the second electrode CE of the light-emitting element OLED according to one or more embodiments. The capping layer CPL can include multiple layers or a single layer.

[0231] In one or more embodiments, the capping layer CPL can be an organic layer and / or an inorganic layer. For example, when the capping layer CPL includes an inorganic material, the inorganic material can include an alkali metal compound such as LiF and / or an alkaline earth metal compound such as MgF2, SiO x N y 、SiN x 、SiO y etc.

[0232] For example, when the capping layer CPL includes an organic material, the organic material can include α-NPD, NPB, TPD, m-MTDATA, Alq3, CuPc, N4,N4,N4’,N4’-tetrakis(biphenyl-4-yl)biphenyl-4,4’-diamine (TPD15), and / or 4,4’,4”-tris(carbazol-9-yl)triphenylamine (TCTA), etc., and can include an epoxy resin and / or an acrylic such as methacrylate.

[0233] In one or more embodiments, the capping layer CPL may have a refractive index of more than about 1.6. In particular, for light having a wavelength range of more than about 550 nm and less than about 660 nm, the capping layer CPL may have a refractive index of more than about 1.6.

[0234] Referring again to Figure 5 , in the light-emitting element OLED according to one or more embodiments, the functional layer FNL may be disposed between the first electrode AE and the second electrode CE. Referring to Figure 5 and Figure 6 , the functional layer FNL may be set as a common layer to completely overlap with the emission regions EA1, EA2, and EA3 and the pixel defining layer PDL that separates the emission regions EA1, EA2, and EA3 from each other. However, the present disclosure is not limited thereto, and the functional layer FNL may be patterned to be separately disposed corresponding to a corresponding one of the emission regions EA1, EA2, and EA3. Alternatively, some of the plurality of organic layers included in the functional layer FNL may be patterned to be separated and disposed corresponding to a corresponding one of the emission regions EA1, EA2, and EA3, and the remaining portions may be set as a common layer to overlap with the emission regions EA1, EA2, and EA3 and the entire pixel defining layer PDL.

[0235] The second electrode CE may be provided on the functional layer FNL. The second electrode CE may be a common electrode. The second electrode CE may be a cathode or an anode, but the present disclosure is not limited thereto. For example, when the first electrode AE is an anode, the second electrode CE may be a cathode, and when the first electrode AE is a cathode, the second electrode CE may be an anode. The second electrode CE may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0236] The encapsulation layer TFE may be disposed on the light-emitting element OLED. For example, in one or more embodiments, the encapsulation layer TFE may be disposed on the second electrode CE. In addition, when the light-emitting element OLED includes the capping layer CPL, the encapsulation layer TFE may be disposed on the capping layer CPL. As described above, the encapsulation layer TFE may include at least one organic layer and at least one inorganic layer, and the inorganic layer and the organic layer may be alternately disposed.

[0237] The display device DD according to one or more embodiments may include an optical layer OSL disposed on the display element layer DP-OLED. The optical layer OSL may at least include a light control layer CCL, a color filter layer CFL, and a base layer BL.

[0238] The light control layer CCL may include a light converter. The light converter may be a quantum dot or a phosphor. The light converter may convert the wavelength of the received light to emit light having a converted wavelength. That is, the light control layer CCL may be a layer including quantum dots in at least a part thereof or a layer including a phosphor.

[0239] The light control layer CCL may include a plurality of light control patterns CCP-R, CCP-G, and CCP-B (for example, see Figure 6 ). The light control patterns CCP-R, CCP-G, and CCP-B may be spaced apart from each other (for example, separated). The light control patterns CCP-R, CCP-G, and CCP-B may be arranged to be spaced apart from each other (for example, separated) by the dam BMP. The light control patterns CCP-R, CCP-G, and CCP-B may be respectively disposed within dam openings BOH1, BOH2, and BOH3 defined in the dam BMP. However, the present disclosure is not limited thereto. In Figure 6 , the dam BMP may have a rectangular shape in cross section and is illustrated as not overlapping with the light control patterns CCP-R, CCP-G, and CCP-B, but the edges of a part of the light control patterns CCP-R, CCP-G, and CCP-B may overlap with the dam BMP. For example, in one or more embodiments, the edge of the third light control pattern CCP-B may be arranged to overlap with the dam BMP in a plane. The dam BMP may have a trapezoidal shape in cross section. The dam BMP may have a shape in which its cross-sectional width increases as it approaches the display element layer DP-OLED.

[0240] The light control patterns CCP-R, CCP-G, and CCP-B may be parts that convert the wavelength of the light provided from the display element layer DP-OLED or transmit the provided light.

[0241] The light control layer CCL may include a first light control pattern CCP-R that provides red light which is the first light, a second light control pattern CCP-G that provides green light which is the second light, and a third light control pattern CCP-B that provides blue light which is the third light. The light control layer CCL may include a first light control pattern CCP-R that converts the source light provided from the light-emitting element OLED into the first light, a second light control pattern CCP-G that converts the source light into the second light, and a third light control pattern CCP-B that transmits the source light. At least some of the light control patterns CCP-R, CCP-G, and CCP-B may include quantum dots that convert the source light into light having a specific wavelength.

[0242] At least some of the light control patterns CCP-R, CCP-G, and CCP-B may be formed by an inkjet process. Alternatively, some of the light control patterns CCP-R, CCP-G, and CCP-B may be formed by a photoresist process.

[0243] The light control layer CCL may further include a scatterer. The first light control pattern CCP-R may include a first quantum dot and a scatterer, the second light control pattern CCP-G may include a second quantum dot and a scatterer, and the third light control pattern CCP-B may not include a quantum dot and a scatterer. Each of the first light control pattern CCP-R, the second light control pattern CCP-G, and the third light control pattern CCP-B may include a base resin in which the quantum dots and the scatterer are dispersed. The third light control pattern CCP-B may be formed by a photoresist process, as will be described later, and may include a photosensitive resin.

[0244] The light control layer CCL may further include a first barrier layer CAP1 provided on one surface of the first light control pattern CCP-R. The optical layer OSL may include the first barrier layer CAP1 spaced apart (e.g., separated) from the display element layer DP-OLED (where the first light control pattern CCP-R is interposed between the first barrier layer CAP1 and the display element layer DP-OLED) and a second barrier layer CAP2 adjacent to the display element layer DP-OLED.

[0245] In the display device DD, the optical layer OSL may include a color filter layer CFL provided on the light control layer CCL. The color filter layer CFL may include color filters CF1, CF2, and CF3. The color filter layer CFL may include a first color filter CF1 that transmits first light, a second color filter CF2 that transmits second light, and a third color filter CF3 that transmits source light. In one or more embodiments, the first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter.

[0246] Each of the color filters CF1, CF2, and CF3 includes a polymer photosensitive resin and a colorant. The first color filter CF1 may include a red colorant, the second color filter CF2 may include a green colorant, and the third color filter CF3 may include a blue colorant. The first color filter CF1 may include a red pigment or a red dye, the second color filter CF2 may include a green pigment or a green dye, and the third color filter CF3 may include a blue pigment or a blue dye.

[0247] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be arranged to correspond to the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3, respectively (e.g., see Figure 6 ). In addition, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be arranged to correspond to the first light control pattern CCP-R, the second light control pattern CCP-G, and the third light control pattern CCP-B, respectively (e.g., seeFigure 6 )。

[0248] In addition, a plurality of color filters CF1, CF2, and CF3 that transmit different lights can be set to overlap each other and correspond to a non-pixel region NPXA provided between pixel regions PXA1, PXA2, and PXA3. The plurality of color filters CF1, CF2, and CF3 can be set to overlap each other in a third direction DR3 that is the thickness direction, so as to distinguish boundaries between adjacent pixel regions PXA1, PXA2, and PXA3. Different from the illustrated configuration, the color filter layer CFL can include a light-shielding portion that defines boundaries between adjacent color filters CF1, CF2, and CF3. The light-shielding portion can be provided as a blue color filter, or include an organic light-shielding material and / or an inorganic light-shielding material containing a black pigment or dye.

[0249] The optical layer OSL can include a filling layer FML provided between the light control layer CCL and the color filter layer CFL. The filling layer FML can be provided between the light control patterns CCP-R, CCP-G, and CCP-B and the color filters CF1, CF2, and CF3 (for example, see Figure 6 )。The filling layer FML can be provided above the light control layer CCL to prevent the light control patterns CCP-R, CCP-G, and CCP-B from being exposed to moisture / oxygen. In addition, the filling layer FML can be used as an optical function layer provided between the light control patterns CCP-R, CCP-G, and CCP-B and the color filters CF1, CF2, and CF3 to improve light extraction efficiency or prevent reflected light from entering the light control layer CCL. The filling layer FML can be a layer having a lower refractive index than other adjacent layers.

[0250] In one or more embodiments, the optical layer OSL can further include a base layer BL provided on the color filter layer CFL. The base layer BL can be a member that provides a base surface on which the color filter layer CFL and the light control layer CCL are provided. The base layer BL can include a glass substrate, a metal substrate, and / or a plastic substrate, etc. However, the present disclosure is not limited thereto. For example, the base layer BL can be an inorganic layer, an organic layer, and / or a composite layer. In addition, different from the illustrated configuration, in an embodiment, the base layer BL can be omitted.

[0251] The optical layer OSL may further include a filling pattern FLP overlapping with the transmissive region TA. A portion of the optical layer OSL overlapping with the transmissive region TA may not overlap with the light control patterns CCP-R, CCP-G, and CCP-B, the bank BMP, the color filters CF1, CF2, and CF3, etc., and the filling pattern FLP may be disposed on this portion of the optical layer OSL. The filling pattern FLP may be disposed to overlap with the transmissive region TA to serve as an optical functional layer for improving the light extraction efficiency or preventing or reducing the downward incidence of reflected light. The filling pattern FLP may be a pattern having a lower refractive index than other adjacent layers.

[0252] In order to improve the transmittance of the transmissive region TA in the display panel DP, at least a part of the insulating layer disposed in the transmissive region TA may be removed.

[0253] According to this embodiment, the base substrate BS, the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 may be disposed in the transmissive region TA. A transmissive opening T-OP overlapping with the transmissive region TA may be defined in the fourth insulating layer 40, the fifth insulating layer 50, the pixel defining layer PDL, and the light emitting element OLED. The transmissive opening T-OP may be defined by side surfaces passing through portions of the fourth insulating layer 40, the fifth insulating layer 50, the pixel defining layer PDL, and the light emitting element OLED that overlap with the transmissive region TA. The transmissive opening T-OP may be defined by removing some of the fourth insulating layer 40, the fifth insulating layer 50, the pixel defining layer PDL, and the light emitting element OLED via a dry etching process. At least a part of the functional layer FNL included in the light emitting element OLED may be removed by an etching process. As described above, the light emitting element OLED may include a plurality of light emitting stacks ST1, ST2, ST3, and ST4 respectively including emission layers BEML-1, BEML-2, BEML-3, and GEML, and at least a part of the plurality of light emitting stacks ST1, ST2, ST3, and ST4 may be removed from the transmissive region TA corresponding to the transmissive opening T-OP. Therefore, at least a part of the emission layers BEML-1, BEML-2, BEML-3, and GEML included in the plurality of light emitting stacks ST1, ST2, ST3, and ST4 may not overlap with the transmissive region TA.

[0254] In this embodiment, the top surface of the third insulating layer 30 may be exposed from the fourth insulating layer 40, the fifth insulating layer 50, the pixel defining layer PDL, and the light emitting element OLED through the transmissive opening T-OP. An inorganic layer included in the encapsulation layer TFE may be disposed on the top surface of the third insulating layer 30.

[0255] The description of the above transmissive region TA may be commonly applied to Figure 3AThe unit region PU described therein. Thus, on a plane (e.g., in a plan view), a plurality of openings arranged to be spaced apart from each other (e.g., separated) in a first direction DR1 and a second direction DR2 can be defined in the fourth insulating layer 40, the fifth insulating layer 50, the pixel defining layer PDL, and the light-emitting element OLED. These openings can be arranged along the first direction DR1 and the second direction DR2 on the plane.

[0256] According to one or more embodiments of the present disclosure, the fourth insulating layer 40 including silicon nitride may not be provided in the transmissive region TA of the display panel DP included in the transparent display device. Thus, the transmittance of the transmissive region TA can be improved.

[0257] In Figure 6 a transmissive opening T-OP corresponding to the transmissive region TA can be defined in each of the fourth insulating layer 40, the fifth insulating layer 50, the pixel defining layer PDL, and the light-emitting element OLED, but is not limited thereto. For example, the transmissive opening T-OP can be additionally defined in other insulating layers included in the circuit element layer DP-CL. Alternatively, the transmissive opening T-OP may not be defined in some of the fourth insulating layer 40, the fifth insulating layer 50, the pixel defining layer PDL, and the light-emitting element OLED. For example, some optical transparent layers of the functional layer FNL included in the light-emitting element OLED may not be removed from the portion corresponding to the transmissive opening T-OP.

[0258] Figure 8 is a plan view of an input sensor according to one or more embodiments of the present disclosure.

[0259] As Figure 8 illustrated therein, the input sensor IS can include a sensing region IS-DA and a non-sensing region IS-NDA adjacent to the sensing region IS-DA and surrounding the sensing region IS-DA along the edge or periphery of the sensing region IS-DA. The sensing region IS-DA and the non-sensing region IS-NDA can respectively correspond to Figure 3A the display region DA and the non-display region NDA illustrated therein.

[0260] The input sensor IS can include the above-described plurality of conductive patterns. The plurality of conductive patterns can include a first electrode SE1 (or a first sensing electrode), a second electrode SE2 (or a second sensing electrode), a first signal line SL1 (or a first sensor signal line), and a second signal line SL2 (or a second sensor signal line).

[0261] A first sensing electrode SE1 and a second sensing electrode SE2 that are insulated from each other and cross each other may be provided in a sensing region IS-DA. A first signal line SL1 connected to the first sensing electrode SE1 and a second signal line SL2 electrically connected to the second sensing electrode SE2 may be provided in a non-sensing region IS-NDA. One of the first signal line SL1 and the second signal line SL2 transmits a driving signal for detecting an external input from an external circuit to the corresponding electrode, and the other outputs a sensing signal. A change in mutual capacitance between the first sensing electrode SE1 and the second sensing electrode SE2 may be measured based on the sensing signal. The input sensor IS illustrated in this embodiment may be referred to as a "mutual capacitance type" input sensor.

[0262] The first sensing electrode SE1 may be provided as a plurality of rows. The first sensing electrode SE1 may include a first row sensing electrode E1-1, a second row sensing element E1-2, a third row sensing electrode E1-3, and a fourth row sensing electrode E1-4. Different from what is illustrated in Figure 8 , the first sensing electrode SE1 may include two or three rows of sensing electrodes, or may include five or more rows of sensing electrodes.

[0263] The second sensing electrode SE2 may be provided as a plurality of columns. The second sensing electrode SE2 may include a first column sensing electrode E2-1, a second column sensing electrode E2-2, a third column sensing electrode E2-3, a fourth column sensing electrode E2-4, a fifth column sensing electrode E2-5, a sixth column sensing electrode E2-6, and a seventh column sensing electrode E2-7. Different from what is illustrated in Figure 8 , the second sensing electrode SE2 may include six or fewer columns of sensing electrodes, or may include eight or more columns of sensing electrodes.

[0264] The second sensing electrode SE2 may include a second sensing pattern SP2 and a connection pattern CP2. Each of the second sensing patterns SP2 may have a planar area larger than that of each of the connection patterns CP2 and may have a rhombus shape. Each of the connection patterns CP2 may be provided between two adjacent second sensing patterns SP2. The length of each of the connection patterns CP2 may be relatively shorter than the length of each of the second sensing patterns SP2.

[0265] Each of the first sensing electrodes SE1 may include a first sensing pattern SP1 and a bridging pattern CP1. Two adjacent first sensing patterns SP1 may be connected to two bridging patterns CP1, but the number of bridging patterns connecting two adjacent first sensing patterns SP1 is not limited.

[0266] In this embodiment, Figure 8 each of the first signal line SL1 and the second signal line SL2 may be fromFigure 5 is provided by the first conductive layer IS-CL1. However, the present disclosure is not limited thereto, and each of the first signal line SL1 and the second signal line SL2 may be provided from the second conductive layer IS-CL2. Each of the first signal line SL1 and the second signal line SL2 may include a dual-line structure including both a line provided from the first conductive layer IS-CL1 and a line provided from the second conductive layer IS-CL2.

[0267] The second sensing electrode SE2 and the first sensing pattern SP1 may be disposed on the same layer. The bridging pattern CP1 may be disposed on a layer different from the layer on which the second sensing electrode SE2 and the first sensing pattern SP1 are disposed. In the input sensor IS according to one or more embodiments, the bridging pattern CP1 may be included in the first conductive layer IS-CL1 described above and may be disposed on the first insulating layer IS-IL1, and the second electrode SE2 and the first sensing pattern SP1 may be included in the second conductive layer IS-CL2 and may be disposed on the second insulating layer IS-IL2. Alternatively, the bridging pattern CP1 may be included in the second conductive layer IS-CL2 and may be disposed on the second insulating layer IS-IL2, and the second electrode SE2 and the first sensing pattern SP1 may be included in the first conductive layer IS-CL1 and may be disposed on the first insulating layer IS-IL1. Figure 5 As illustrated in, each of the first sensing electrode SE1 and the second sensing electrode SE2 may have a mesh shape in which a plurality of openings are defined. For example, the plurality of openings may overlap corresponding emission regions and transmission regions TA in the plurality of pixel regions PXA illustrated in. The second sensing electrode SE2 may be insulated from and cross the first sensing electrode SE1. The mesh shape of each of the first sensing electrode SE1 and the second sensing electrode SE2 will be described later in the description of, etc.

[0268] As Figure 8 illustrated, each of the first sensing electrode SE1 and the second sensing electrode SE2 may have a mesh shape in which a plurality of openings are defined. For example, the plurality of openings may overlap corresponding emission regions and transmission regions TA in the plurality of pixel regions PXA illustrated in. The second sensing electrode SE2 may be insulated from and cross the first sensing electrode SE1. The mesh shape of each of the first sensing electrode SE1 and the second sensing electrode SE2 will be described later in the description of, etc. Figure 3B As illustrated in, each of the first sensing electrode SE1 and the second sensing electrode SE2 may have a mesh shape in which a plurality of openings are defined. For example, the plurality of openings may overlap corresponding emission regions and transmission regions TA in the plurality of pixel regions PXA illustrated in. The second sensing electrode SE2 may be insulated from and cross the first sensing electrode SE1. The mesh shape of each of the first sensing electrode SE1 and the second sensing electrode SE2 will be described later in the description of, etc. Figure 9A As illustrated in, each of the first sensing electrode SE1 and the second sensing electrode SE2 may have a mesh shape in which a plurality of openings are defined. For example, the plurality of openings may overlap corresponding emission regions and transmission regions TA in the plurality of pixel regions PXA illustrated in. The second sensing electrode SE2 may be insulated from and cross the first sensing electrode SE1. The mesh shape of each of the first sensing electrode SE1 and the second sensing electrode SE2 will be described later in the description of, etc.

[0269] One of the first sensing electrode SE1 and the second sensing electrode SE2 may have an integral shape. In the present embodiment, the second sensing electrode SE2 having an integral shape is illustrated as an example.

[0270] Figure 9A And Figure 9B are enlarged plan views illustrating a part of an input sensor according to one or more embodiments of the present disclosure. Figure 9C And Figure 9D are enlarged cross-sectional views illustrating a part of an input sensor according to one or more embodiments of the present disclosure. Figure 9A And Figure 9B Are Figure 8An enlarged view of the area AA shown in the figure. Figure 9C is a cross-sectional view taken along line Figure 9A III-III'. Figure 9D is a cross-sectional view taken along line Figure 9B IV-IV'.

[0271] Referring together to Figure 9A and Figure 9B , a plurality of pixel openings POP and transmissive openings TOP can be defined in each of the first sensing pattern SP1 and the second sensing pattern SP2.

[0272] The plurality of pixel openings POP can include a first pixel opening POP1, a second pixel opening POP2, and a third pixel opening POP3 that are arranged to be spaced apart (e.g., separated) along a first direction DR1. The transmissive opening TOP can be spaced apart (e.g., separated) from each of the first pixel opening POP1, the second pixel opening POP2, and the third pixel opening POP3 along a second direction DR2.

[0273] The plurality of pixel openings POP can be openings corresponding to the above-described pixel region PXA. The transmissive opening TOP can be an opening corresponding to the above-described transmissive region TA. In the present embodiment, a first pixel region PXA1 can be provided within the first pixel opening POP1, a second pixel region PXA2 can be provided within the second pixel opening POP2, and a third pixel region PXA3 can be provided within the three-pixel opening POP3.

[0274] Each of the first sensing pattern SP1 and the second sensing pattern SP2 can include a plurality of grid lines MSL that define a plurality of pixel openings POP and a plurality of transmissive openings TOP. The plurality of grid lines MSL can include a plurality of grid members extending in each of the first direction DR1 and the second direction DR2. The plurality of grid members included in the plurality of grid lines MSL can have the same width. However, the present disclosure is not limited thereto, and one of the grid members included in the grid lines MSL can be wider than the other grid members. For example, in the grid lines MSL, a grid member extending in one direction can have a width greater than the width of a grid member extending in the other direction. The width of the grid lines MSL can be, for example, about 15 micrometers or more and about 25 micrometers or less.

[0275] Each of the plurality of pixel openings POP may have a planar area larger than the planar area of the overlapping emission region. For example, the planar area of the first pixel opening POP1 may be larger than the planar area of the first pixel region PXA1, the planar area of the second pixel opening POP2 may be larger than the planar area of the second pixel region PXA2, and the planar area of the third pixel opening POP3 may be larger than the planar area of the third pixel region PXA3. Accordingly, the plurality of grid lines MSL defining the plurality of pixel openings POP may not reduce the emission efficiency of the light emitted through the pixel regions.

[0276] The transmissive opening TOP may have a planar area larger than the planar area of the overlapping transmissive region TA. The planar area of the transmissive opening TOP may be larger than the planar area of the transmissive region TA. Accordingly, the plurality of grid lines MSL defining the transmissive opening TOP may not reduce the transmittance of the display device DD.

[0277] The arrangement and shape of the grid lines MSL may be changed according to the arrangement and planar area of the plurality of pixel openings POP and transmissive openings TOP defined in the grid lines MSL. In addition, the arrangement and planar area of the plurality of pixel openings POP and transmissive openings TOP may be changed according to the arrangement and area of the corresponding pixel regions PXA and transmissive regions TA.

[0278] For ease of explanation, the plurality of grid lines MSL defining the plurality of pixel openings POP and the plurality of transmissive openings TOP may be connected to each other and thus have an integral shape. That is, the plurality of grid lines MSL may be provided by patterning the plurality of pixel openings POP and the plurality of transmissive openings TOP on an integral conductive layer.

[0279] Refer together Figure 8 and Figure 9A , the input sensor IS includes a plurality of conductive patterns, and the plurality of conductive patterns include a first sensing electrode SE1 and a second sensing electrode SE2. The first sensing electrode SE1 may include a first sensing pattern SP1 and a bridging pattern CP1. The second sensing electrode SE2 may include a second sensing pattern SP2 and a connecting pattern CP2. Figure 9A is an enlarged plan view showing two first sensing patterns SP1 included in the first sensing electrode SE1 and a bridging pattern CP1 connecting the first sensing patterns SP1 and two second sensing patterns SP2 included in the second sensing electrode SE2 and a connecting pattern CP2 connecting the second sensing patterns SP2 (for example, see Figure 8 ).

[0280] In an input sensor IS according to one or more embodiments, a boundary portion CTL may be defined between a first sensing pattern SP1 and a second sensing electrode SE2. The boundary portion CTL may be a portion from which at least some of the mesh lines MSL are removed. The boundary portion CTL may be provided to insulate the first sensing pattern SP1 and the second sensing electrode SE2 from each other. The boundary portion CTL may be provided to insulate the first sensing pattern SP1 and the second sensing pattern SP2 from each other and to insulate the first sensing pattern SP1 and the connection pattern CP2 from each other.

[0281] Each of the second sensing pattern SP2 and the connection pattern CP2 included in the second sensing electrode SE2 may include mesh lines MSL and have an integral shape. The connection pattern CP2 may be disposed between two adjacent second sensing patterns SP2 and may have a shape integral with each of the two second sensing patterns SP2. Figure 8 and Figure 9A Each of the plurality of second sensing patterns SP2 and the connection pattern CP2 illustrated in may include mesh lines MSL, and two adjacent second sensing patterns SP2 among the plurality of second sensing patterns SP2 and the connection pattern CP2 may have an integral shape.

[0282] The bridging pattern CP1 may electrically connect two adjacent first sensing patterns SP1 to each other. The bridging pattern CP1 may overlap with the lower contact hole CH-L (see Figure 9C ) in a plane and may electrically connect two adjacent first sensing patterns SP1 to each other through the lower contact hole CH-L.

[0283] The plurality of conductive patterns included in the input sensor IS may further include at least one transparent electrode TPE. The plurality of conductive patterns may include a plurality of transparent electrodes TPE spaced apart (e.g., separated) from each other in a plane. The transparent electrodes TPE may be provided in plurality and may be disposed throughout the sensing area IS-DA.

[0284] The transparent electrode TPE may include an optically transparent material. The transparent electrode TPE may include, for example, a transparent conductive oxide (TCO). The transparent electrode TPE may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ) and / or indium zinc tin oxide (IZTO). For example, the transparent electrode TPE may include indium tin oxide (ITO).

[0285] The transparent electrode TPE can overlap at least a portion of the first sensing electrode SE1 and the second sensing electrode SE2 in a plane. The transparent electrode TPE can overlap at least a portion of the first sensing pattern SP1, the second sensing pattern SP2, and the connection pattern CP2 in a plane. The transparent electrode TPE can be electrically connected to portions of the first sensing pattern SP1, the second sensing pattern SP2, and the connection pattern CP2 that overlap the transparent electrode TPE in a plane.

[0286] The transparent electrode TPE can overlap at least a portion of the transmissive opening TOP in a plane. The transparent electrode TPE can overlap at least a portion of the plurality of pixel openings POP in a plane. The transparent electrode TPE can overlap the transmissive opening TOP and at least a portion of the corresponding transmissive region TA. The transmissive region TA can include a first transmissive region TA-1 that does not overlap the transparent electrode TPE in a plane and a second transmissive region TA-2 that overlaps the transparent electrode TPE in a plane. The transparent electrode TPE can overlap the pixel opening POP and can overlap at least a portion of the corresponding pixel region PXA.

[0287] Reference Figure 9A and Figure 9C , the transparent electrode TPE can be disposed on a layer different from the layer on which the first sensing electrode SE1 and the second sensing electrode SE2 are disposed. In one or more embodiments, the transparent electrode TPE can be disposed above the first sensing electrode SE1 and the second sensing electrode SE2. As Figure 9C illustrated, the transparent electrode TPE can be disposed on the third insulating layer IS-IL3. The transparent electrode TPE can be spaced apart (e.g., separated) from the first sensing pattern SP1, the second sensing pattern SP2, and the connection pattern CP2, where the third insulating layer IS-IL3 is interposed between the transparent electrode TPE and the first sensing pattern SP1, the second sensing pattern SP2, and the connection pattern CP2. The transparent electrode TPE can be electrically connected to corresponding portions of the first sensing pattern SP1, the second sensing pattern SP2, and the connection pattern CP2 disposed below the third insulating layer IS-IL3 through upper contact holes CH-U defined in the third insulating layer IS-IL3. In the present disclosure, the third insulating layer IS-IL3 disposed between the transparent electrode TPE and the first sensing electrode SE1 and the second sensing electrode SE2 can be described as a "covering insulating layer".

[0288] An input sensor IS according to one or more embodiments can include a transparent electrode TPE electrically connected to each of the first sensing electrode SE1 and the second sensing electrode SE2 and overlapping at least a portion of the transmissive region TA and the pixel region PXA to achieve high sensing sensitivity while maintaining a high transmittance.

[0289] Specifically, based on the total area of the transmissive region TA and the pixel region PXA, a display device having a planar area of the transmissive region TA of more than about 60% can be used as a transparent display device, but may have a low density and low sensing sensitivity in the grid lines MSL. However, the input sensor IS according to one or more embodiments and the display device DD including the input sensor IS may include a transparent electrode TPE electrically connected to the grid lines MSL of each of the first sensing electrode SE1 and the second sensing electrode SE2, and thus, the planar area and density of the conductive pattern for sensing an external input can be increased, thereby improving the sensing sensitivity. Accordingly, the sensing performance of the display device DD including the input sensor IS can be improved.

[0290] Reference Figure 9B and Figure 9D , the plurality of conductive patterns included in the input sensor IS may further include at least one dummy pattern DPE. The plurality of conductive patterns may include a plurality of dummy patterns DPE spaced apart (e.g., separated) from each other on a plane. The dummy patterns DPE may be provided as a plurality and may be arranged throughout the sensing region IS-DA. The dummy patterns DPE may be spaced apart (e.g., separated) from the transparent electrode TPE on a plane.

[0291] The dummy pattern DPE may include an optically transparent material. The dummy pattern DPE may include the same material as the transparent electrode TPE. The dummy pattern DPE may include, for example, a transparent conductive oxide (TCO). The dummy pattern DPE may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ) and / or indium zinc tin oxide (IZTO). For example, the dummy pattern DPE may include indium tin oxide (ITO).

[0292] The dummy pattern DPE may overlap at least a portion of the first sensing electrode SE1 and the second sensing electrode SE2 on a plane. The dummy pattern DPE may overlap at least a portion of the first sensing pattern SP1, the second sensing pattern SP2, and the connection pattern CP2 on a plane. The dummy pattern DPE may be an isolated floating electrode not electrically connected to the sensing electrodes SE1 and SE2 and the transparent electrode TPE.

[0293] The dummy pattern DPE may overlap at least a portion of the transmissive opening TOP on a plane. The dummy pattern DPE may overlap at least a portion of the plurality of pixel openings POP on a plane. The dummy pattern DPE may overlap the transmissive opening TOP to overlap at least a portion of the corresponding transmissive region TA. The dummy pattern DPE may overlap the pixel opening POP to overlap at least a portion of the corresponding pixel region PXA.

[0294] The dummy pattern DPE may be disposed on a layer different from the layer on which the first sensing electrode SE1 and the second sensing electrode SE2 are disposed. In one or more embodiments, the dummy pattern DPE may be disposed above the first sensing electrode SE1 and the second sensing electrode SE2. The dummy pattern DPE may be disposed on the same layer as the transparent electrode TPE (e.g., at the same layer as the transparent electrode TPE). The dummy pattern DPE may be disposed on the same layer as the transparent electrode TPE (e.g., at the same layer as the transparent electrode TPE), and may be formed by the same process. The dummy pattern DPE may include the same material as the transparent electrode TPE. As Figure 9D Illustrated, the dummy pattern DPE may be disposed on the third insulating layer IS-IL3. The dummy pattern DPE may be separated (e.g., spaced apart) from the first sensing pattern SP1, the second sensing pattern SP2, and the connection pattern CP2, where the third insulating layer IS-IL3 is interposed between the dummy pattern DPE and the first sensing pattern SP1, the second sensing pattern SP2, and the connection pattern CP2. In one or more embodiments, the transparent electrode TPE may be electrically connected to corresponding portions of the first sensing pattern SP1, the second sensing pattern SP2, and the connection pattern CP2 disposed below the third insulator IS-IL3 through an upper contact hole CH-U defined in the third insulating layer IS-IL3, but no separate contact hole may be defined at the lower portion of the dummy pattern DPE, and it may be insulated from the first sensing pattern SP1, the second sensing pattern SP2, and the connection pattern CP2 disposed below it.

[0295] The input sensor IS according to one or more embodiments may further include a dummy pattern DPE that is floated and separated (e.g., spaced apart) from the transparent electrode TPE in a plane to reduce the transmittance difference between a portion where the transparent electrode TPE is disposed and a portion where the transparent electrode TPE is not disposed. Accordingly, the visibility of the display device DD including the input sensor IS may be improved.

[0296] Figures 10A to 10C is an enlarged plan view showing a part of a display device according to one or more embodiments of the present disclosure. In Figures 10A to 10C it, the overlapping relationship between the above-described pixel region PXA, the transmissive region TA, and the transparent electrode TPE is illustrated in more detail.

[0297] Referring to Figure 10A , the arrangement of the pixel region PXA and the transmissive region TA may be the same as that described above in Figure 3BThe transparent electrode TPE according to one or more embodiments may overlap a portion of the pixel area PXA and a portion of the transmission area TA. The transparent electrode TPE may overlap a portion of the transmission area TA and may not overlap the remaining portion of the transmission area TA. The transparent electrode TPE may overlap a portion of the pixel area PXA and may not overlap the remaining portion of the pixel area PXA.

[0298] refer to Figure 10B ,and Figure 3B Unlike illustrated in FIG. 1 , a portion of the transmission area TA may overlap the pixel area PXA in the first direction DR1. A portion of the transmission area TA may be arranged side by side with the pixel area PXA in the second direction DR2, and the remaining portion may extend to be arranged side by side with the pixel area PXA in the first direction DR1.

[0299] The transparent electrode TPE' may overlap the pixel area PXA and may overlap a portion of the transmission area TA. The transparent electrode TPE' may overlap a portion of the transmission area TA and may not overlap the remaining portion of the transmission area TA. The transparent electrode TPE' may overlap the entire pixel area PXA. The transparent electrode TPE' may overlap a portion of the transmission area TA that is disposed side by side with the pixel area PXA in the first direction DR1.

[0300] refer to Figure 10C ,and Figure 3B Unlike illustrated in FIG. 1 , a portion of the transmission area TA may overlap the pixel area PXA in the first direction DR1. A portion of the transmission area TA may be arranged side by side with the pixel area PXA in the second direction DR2, and the remaining portion may extend to be arranged side by side with the pixel area PXA in the first direction DR1.

[0301] In addition, each of the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 may have Figure 3B In one or more embodiments, the first pixel region PXA1 and the second pixel region PXA2 may be arranged side by side in the second direction DR2, and the third pixel region PXA3 may be disposed side by side with each of the first pixel region PXA1 and the second pixel region PXA2 in the first direction DR1.

[0302] The display area DA according to one or more embodiments may further include a spacer area CSA. The spacer area CSA may be an area in which a spacer is defined. The spacer may be included in the display panel DP (see Figure 6 ) so that the display panel DP (see Figure 6) and an input sensor IS (see Figure 6 ) and an optical layer OSL (see Figure 6 ), which are separated (e.g., spaced apart). The spacer region CSA may be arranged side by side with the third pixel region PXA3 in the second direction DR2.

[0303] The transparent electrode TPE’ may overlap with the pixel region PXA and may overlap with a part of the transmissive region TA. The transparent electrode TPE’ may overlap with the spacer region CSA. The transparent electrode TPE’ may overlap with a part of the transmissive region TA and may not overlap with the remaining part of the transmissive region TA. The transparent electrode TPE’ may overlap with the entire pixel region PXA and the spacer region CSA. The transparent electrode TPE’ may overlap with the part of the transmissive region TA that is arranged side by side with the pixel region PXA and the spacer region CSA in the first direction DR1.

[0304] Figure 11 is a plan view of an input sensor according to one or more embodiments of the present disclosure. In Figure 11 , a plan shape of an input sensor IS different from the input sensor IS according to one or more embodiments illustrated in Figure 8 is illustrated according to one or more embodiments.

[0305] As Figure 11 is illustrated, the input sensor IS may include a sensing region IS-DA and a non-sensing region IS-NDA adjacent to the sensing region IS-DA. The sensing region IS-DA and the non-sensing region IS-NDA may respectively correspond to Figure 3A the display region DA and the non-display region NDA illustrated in

[0306] The input sensor IS may include the above-mentioned plurality of conductive patterns. The plurality of conductive patterns may include sensing patterns and signal lines. The sensing patterns may include a plurality of unit sensing patterns SP-U. The signal lines may include a plurality of unit signal lines SL-U.

[0307] A plurality of unit sensing patterns SP-U insulated from each other may be provided in the sensing region IS-DA. Each of the plurality of unit sensing patterns SP-U may be provided in the form of a separate sensing electrode, and each of the plurality of unit sensing patterns SP-U may operate by the “self-capacitance method” to sense an input. The input sensor IS according to one or more embodiments may sense an external input by sensing the self-capacitance voltage charged in each of the plurality of unit sensing patterns SP-U.

[0308] The plurality of unit sensing patterns SP-U may be electrically separated from each other. The plurality of unit sensing patterns SP-U may be spaced apart from each other in a plane (e.g., spaced apart).Figure 11 Each of the plurality of unit sensing patterns SP-U is illustrated as having a rectangular shape in a plane, but is not limited thereto, and each of the unit sensing patterns SP-U may have other planar shapes of polygons, circles, or ellipses in addition to the rectangular shape.

[0309] Each of the plurality of unit sensing patterns SP-U may be connected to a corresponding one of a plurality of unit signal lines SL-U. Each of the plurality of unit signal lines SL-U is connected to a corresponding one of the plurality of unit sensing patterns SP-U and extends along a first direction DR1.

[0310] The plurality of unit sensing patterns SP-U may be provided in multiple rows. The plurality of unit sensing patterns SP-U may include a first row of sensing electrodes E1-1, a second row of sensing electrodes E1-2, a third row of sensing electrodes E1-3, a fourth row of sensing electrodes E1-4, and a fifth row of sensing electrodes E1-5. Different from Figure 11 that illustrated in, the first sensing electrode SE1 may include two to four rows of sensing electrodes, or may include six or more rows of sensing electrodes.

[0311] The plurality of unit sensing patterns SP-U may be provided in multiple columns. The plurality of unit sensing patterns SP-U may include a first column of sensing electrodes E2-1, a second column of sensing electrodes E2-2, a third column of sensing electrodes E2-3, a fourth column of sensing electrodes E2-4, a fifth column of sensing electrodes E2-5, a sixth column of sensing electrodes E2-6, a seventh column of sensing electrodes E2-7, and an eighth column of sensing electrodes E2-8. Different from Figure 11 that illustrated in, the second sensing electrode SE2 may include seven or fewer columns of sensing electrodes, or may include nine or more columns of sensing electrodes.

[0312] In this embodiment, Figure 11 each of the plurality of unit signal lines SL-U may be provided from Figure 5 the first conductive layer IS-CL1. However, the present disclosure is not limited thereto, and each of the plurality of unit signal lines SL-U may be provided from a second conductive layer IS-CL2. Each of the plurality of unit signal lines SL-U may have a dual-line structure including both a line provided from the first conductive layer IS-CL1 and a line provided from the second conductive layer IS-CL2.

[0313] Multiple unit sensing patterns SP-U may be disposed on the same layer (e.g., disposed at the same layer). In an input sensor IS according to one or more embodiments, each of the multiple unit sensing patterns SP-U may be included in a second conductive layer IS-CL2 and may be disposed on a second insulating layer IS-IL2. Each of the multiple unit sensing patterns SP-U may be included in a first conductive layer IS-CL1 and may be disposed on a first insulating layer IS-IL1. Each of the multiple unit sensing patterns SP-U may be disposed on a layer different from the layer on which each of the multiple unit signal lines SL-U is disposed.

[0314] As Figure 11 illustrated, each of the multiple unit sensing patterns SP-U may have a grid shape in which a plurality of opening regions are defined. For example, the plurality of opening regions may overlap corresponding emission regions and transmission regions TA in a plurality of pixel regions PXA of Figure 3B .

[0315] Figure 12A is an enlarged plan view illustrating a part of an input sensor according to one or more embodiments of the present disclosure. Figure 12B is an enlarged plan view illustrating some configurations in the configuration of an input sensor according to one or more embodiments of the present disclosure. Figure 12C is an enlarged cross-sectional view illustrating a part of an input sensor according to one or more embodiments of the present disclosure. Figure 12A is illustrated in relation to Figure 11 an enlarged view of a portion corresponding to region BB illustrated in Figure 12B Briefly illustrates Figure 12A the planar shape of the unit signal line SL-U illustrated in Figure 12C Illustrates a cross-sectional view taken along line V-V' illustrated in Figure 12A .

[0316] Referring together to Figure 11 and Figure 12A , the input sensor IS may include a plurality of conductive patterns, and the plurality of conductive patterns may include a plurality of unit sensing patterns SP-U and a plurality of unit signal lines SL-U. Figure 12A is an enlarged view illustrating the shapes of nine unit sensing patterns SP-U among the plurality of unit sensing patterns SP-U and nine unit signal lines SL-U respectively connected to the nine unit sensing patterns SP-U.

[0317] A plurality of pixel openings POP and a plurality of transmission openings TOP may be defined in each of the plurality of unit sensing patterns SP-U.

[0318] The plurality of pixel openings POP may include a first pixel opening POP1, a second pixel opening POP2, and a third pixel opening POP3 that are arranged to be spaced apart (e.g., separated) along a first direction DR1. The transmissive opening TOP may be spaced apart (e.g., separated) from each of the first pixel opening POP1, the second pixel opening POP2, and the third pixel opening POP3 along a second direction DR2.

[0319] The plurality of pixel openings POP may be openings corresponding to the pixel region PXA described in Figure 3B . The transmissive opening TOP may be an opening corresponding to the transmissive region TA described in Figure 3B . In the present embodiment, a first pixel region PXA1 may be disposed within the first pixel opening POP1, a second pixel region PXA2 may be disposed within the second pixel opening POP2, and a third pixel region PXA3 may be disposed within the third pixel opening POP3.

[0320] Each of the plurality of unit sensing patterns SP-U may include a plurality of grid lines MSL that define the plurality of pixel openings POP and the plurality of transmissive openings TOP. The plurality of grid lines MSL may include a plurality of grid members extending in each of the first direction DR1 and the second direction DR2. The plurality of grid members included in the plurality of grid lines MSL may have the same width. However, the present disclosure is not limited thereto, and one of the grid members included in the grid lines MSL may be wider than the other grid members. For example, in the grid lines MSL, a grid member extending in one direction may have a width greater than the width of the grid members extending in the other direction.

[0321] Each of the plurality of pixel openings POP may have a planar area larger than the planar area of the overlapping emission region. For example, the planar area of the first pixel opening POP1 may be greater than the planar area of the first pixel region PXA1, the planar area of the second pixel opening POP2 may be greater than the planar area of the second pixel region PXA2, and the planar area of the third pixel opening POP3 may be greater than the planar area of the third pixel region PXA3. Accordingly, the plurality of grid lines MSL defining the plurality of pixel openings POP may not reduce the emission efficiency of the light emitted through the emission region.

[0322] The transmissive opening TOP may have a planar area larger than the planar area of the overlapping transmissive region TA. The planar area of the transmissive opening TOP may be greater than the planar area of the transmissive region TA. Accordingly, the plurality of grid lines MSL defining the transmissive opening TOP may not reduce the transmittance of the display device.

[0323] The arrangement and shape of the grid lines MSL can be changed according to the arrangement and planar area of a plurality of pixel openings POP and transmissive openings TOP defined in the grid lines MSL. In addition, the arrangement and planar area of the plurality of pixel openings POP and transmissive openings TOP can be changed according to the arrangement and area of the corresponding pixel regions PXA and transmissive regions TA.

[0324] For ease of explanation, a plurality of grid lines MSL defining a plurality of pixel openings POP and a plurality of transmissive openings TOP can be connected to each other and thus have an integral shape. That is, a plurality of grid lines MSL can be provided by patterning a plurality of pixel openings POP and a plurality of transmissive openings TOP on an integral conductive layer.

[0325] The input sensor IS can include a plurality of conductive patterns, and the plurality of conductive patterns can include a plurality of unit sensing patterns SP-U and a plurality of unit signal lines SL-U. Each of the plurality of unit signal lines SL-U can be electrically connected to a corresponding unit sensing pattern SP-U. Each of the plurality of unit signal lines SL-U can be electrically connected to each of the grid lines MSL of a corresponding unit sensing pattern SP-U.

[0326] Figure 12B is an enlarged view of the planar shape of one of the plurality of unit signal lines SL-U.

[0327] Reference Figure 12A and Figure 12B , each of the unit signal lines SL-U can include a plurality of sub-signal lines SL-S1, SL-S2, and SL-S3. The plurality of sub-signal lines SL-S1, SL-S2, and SL-S3 can extend along a first direction DR1. The plurality of sub-signal lines SL-S1, SL-S2, and SL-S3 can be spaced apart (e.g., separated) from each other along a second direction DR2.

[0328] Each of the plurality of unit signal lines SL-U can include, for example, three sub-signal lines SL-S1, SL-S2, and SL-S3. The plurality of unit signal lines SL-U can include a first sub-signal line SL-S1, a second sub-signal line SL-S2, and a third sub-signal line SL-S3. The first sub-signal line SL-S1, the second sub-signal line SL-S2, and the third sub-signal line SL-S3 can extend along a first direction DR1 and can be spaced apart (e.g., separated) from each other in a second direction DR2.

[0329] The width of each of the plurality of sub-signal lines SL-S1, SL-S2, and SL-S3 can be about 1 micrometer or more and about 5 micrometers or less. Each of the width W1 of the first sub-signal line SL-S1, the width W2 of the second sub-signal line SL-S2, and the width W3 of the third sub-signal line SL-S3 can be about 1 micrometer or more and about 5 micrometers or less. The width of each of the plurality of sub-signal lines SL-S1, SL-S2, and SL-S3 can be less than the width of the grid line MSL.

[0330] The spacing distance between the plurality of sub-signal lines SL-S1, SL-S2, and SL-S3 can be about 3 micrometers or more and about 7 micrometers or less. Each of the spacing distance L1 between the first sub-signal line SL-S1 and the second sub-signal line SL-S2 and the spacing distance L2 between the second sub-signal line SL-S2 and the third sub-signal line SL-S3 can be about 3 micrometers or more and about 7 micrometers or less.

[0331] In the input sensor IS according to one or more embodiments, each of the unit signal lines SL-U electrically connected to the grid lines MSL of the corresponding unit sensing pattern SP-U can include a plurality of sub-signal lines SL-S1, SL-S2, and SL-S3 to achieve excellent sensitivity while reducing or minimizing the planar area occupied by each unit signal line SL-U. Accordingly, an input sensor having excellent sensitivity while reducing or minimizing a dead zone and a display device including the input sensor can be provided.

[0332] Reference Figures 12A to 12C , the plurality of sub-signal lines SL-S1, SL-S2, and SL-S3 included in each of the plurality of unit signal lines SL-U can be connected to the corresponding unit sensing pattern SP-U.

[0333] Each of the plurality of unit signal lines SL-U may be disposed on a layer different from the layer on which the plurality of unit sensing patterns SP-U are disposed. In one or more embodiments, each of the plurality of unit signal lines SL-U may be disposed on a first insulating layer IS-IL1, and the plurality of unit sensing patterns SP-U may be disposed on a second insulating layer IS-IL2. Each of the plurality of unit signal lines SL-U may be connected to a corresponding unit sensing pattern SP-U through a unit contact hole CH-N defined in the second insulating layer IS-IL2. Each of the plurality of sub-signal lines SL-S1, SL-S2, and SL-S3 may be connected to a corresponding unit sensing pattern SP-U through a unit contact hole CH-N defined in the second insulating layer IS-IL2. Each of the first sub-signal line SL-S1, the second sub-signal line SL-S2, and the third sub-signal line SL-S3 may be connected to a corresponding one of the unit sensing patterns SP-U through a unit contact hole CH-N defined in the second insulating layer IS-IL2.

[0334] Figure 13 is a plan view of an input sensor according to one or more embodiments of the present disclosure. Figure 13 illustrates an input sensor different from the input sensor IS according to Figure 11 one or more embodiments illustrated therein.

[0335] Refer to Figure 13 , different from the input sensor IS illustrated in Figure 11 , an input sensor according to one or more embodiments may further include an additional signal line SL-A.

[0336] The additional signal line SL-A may have a shape integral with a part of the plurality of unit sensing patterns SP-U. The additional signal line SL-A may be electrically connected to a part of the plurality of unit sensing patterns SP-U. In Figure 13 , an example is illustrated in which the eighth column sensing electrode E2-8 has an integral shape with the additional signal line SL-A and the eighth column sensing electrode E2-8 is electrically connected to the additional signal line SL-A, but is not limited thereto. For example, the additional signal line SL-A may have a shape integral with a part of the plurality of unit sensing patterns SP-U provided in a plurality of rows and a plurality of columns, and may be electrically connected to the unit sensing pattern SP-U.

[0337] The additional signal line SL-A can be disposed on the same layer as the plurality of unit sensing patterns SP-U (e.g., disposed at the same layer). In the input sensor IS according to one or more embodiments, the plurality of unit sensing patterns SP-U and the additional signal line SL-A can be included in the second conductive layer IS-CL2 and can be disposed on the second insulating layer IS-IL2. Alternatively, the plurality of unit sensing patterns SP-U and the additional signal line SL-A can be included in the first conductive layer IS-CL1 and can be disposed on the first insulating layer IS-IL1. The additional signal line SL-A can be disposed on a layer different from the layer on which each of the plurality of unit signal lines SL-U is disposed.

[0338] In Figure 13 an example is illustrated in which the unit signal line SL-U is not connected to the eighth column sensing electrode E2-8 to which the additional signal line SL-A is connected, but is not limited thereto. For example, the unit signal lines SL-U can be respectively connected to the eighth column sensing electrode E2-8 to which the additional signal line SL-A is connected.

[0339] Hereinafter, the characteristics of the input sensor according to one or more embodiments and the input sensor according to the comparative example are compared and shown in Table 1 below. In Table 1 below, Example 1 shows the sensitivity of the input sensor having the mutual capacitance type input sensor structure illustrated in Figure 8 and including the transparent electrodes illustrated in Figure 9A . Example 2 shows the sensitivity of the following input sensor having the self-capacitance type input sensor structure illustrated in Figure 11 and in which, as illustrated in Figures 12A to 12C , the unit signal lines are respectively connected to the unit sensing patterns and each of the unit signal lines includes three sub-signal lines. Comparative Example 1 shows the sensitivity of the input sensor having the mutual capacitance type input sensor structure illustrated in Figure 8 but not including the transparent electrodes illustrated in Figure 9A .

[0340] [Table 1]

[0341] Example 1 Example 2 Comparative Example 1 Grid line width (μm) 18.9 18.9 18.9 Capacitance change (fF) 40 415 17

[0342] Referring to the results in Table 1, it is seen that although the input sensor according to one or more embodiments has the same grid line width as that of Comparative Example 1, the capacitance change value is significantly increased compared to the capacitance change value of Comparative Example 1. Therefore, it is confirmed that the input sensor according to one or more embodiments is applied to a transparent display device in which the planar area of the transmissive region is about 60% or more based on the total area of the transmissive region and the pixel region and has excellent sensitivity.

[0343] According to an embodiment of the present disclosure, the ratio of the transmissive region in the display region can be increased to improve the transmittance of the display device, and the capacitance change range of the input sensor can be significantly ensured to improve the sensing performance of the input sensor and the display device including the input sensor.

[0344] Those skilled in the art will understand that various modifications and changes can be made in the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations of the embodiments as long as they fall within the scope of the claims and their equivalents. Therefore, the technical scope of the present disclosure is not limited to the content described in the specific embodiments of this specification, but should be determined by the claims and their equivalents.

Claims

1. A display device, comprising: The display panel comprises a display area including a transmission area and a non-display area adjacent to the display area; as well as an input sensor, on the display panel, and comprising a plurality of conductive patterns, The plurality of conductive patterns include: a first sensing electrode including a plurality of first sensing patterns arranged along a first direction and a plurality of bridge patterns configured to connect two adjacent first sensing patterns of the plurality of first sensing patterns to each other; a second sensing electrode spaced apart from the first sensing electrode and including a plurality of second sensing patterns arranged along a second direction crossing the first direction; and a transparent electrode electrically connected to at least a portion of the first sensing electrode and the second sensing electrode, wherein each of the plurality of first sensing patterns and the plurality of second sensing patterns comprises a plurality of grid lines, a transmission opening overlapping the transmission area is located in the plurality of grid lines, and The transparent electrode overlaps at least a portion of the transmission area.

2. The display device according to claim 1, wherein: The display area further includes: A plurality of pixel regions are adjacent to the transmission region and are configured to emit light.

3. The display device according to claim 2, wherein: In the display region, a ratio of an area of ​​the transmission region to a total area of ​​the transmission region and the plurality of pixel regions is 60% or more.

4. The display device according to claim 1, wherein: The input sensor further comprises: A covering insulating layer is provided between the first sensing electrode, the second sensing electrode and the transparent electrode, and The transparent electrode is electrically connected to at least a portion of the first sensing electrode and the second sensing electrode through an upper contact hole penetrating the cover insulating layer.

5. The display device according to claim 2, wherein: The transparent electrode overlaps at least a portion of each of the transmission region and the plurality of pixel regions.

6. The display device according to claim 1, wherein: The plurality of conductive patterns further include: The dummy pattern is at the same layer as the transparent electrode and is insulated from the first sensing electrode and the second sensing electrode.

7. The display device according to claim 2, wherein: The plurality of pixel regions include a first pixel region, a second pixel region, and a third pixel region, and The transmission region is adjacent to each of the first pixel region, the second pixel region, and the third pixel region along the first direction.

8. The display device according to claim 1, wherein: The transparent electrode includes a transparent conductive oxide.

9. The display device according to claim 2, wherein: The display panel includes a light emitting element configured to emit source light and overlap at least one of the plurality of pixel regions, and The light emitting element comprises: a first electrode; a first light emitting stack on the first electrode; a second light emitting stack on the first light emitting stack; a third light emitting stack on the second light emitting stack; a fourth light emitting stack on the third light emitting stack; a second electrode on the fourth light emitting stack; and a charge generation layer, respectively between the first light-emitting stack, the second light-emitting stack, the third light-emitting stack and the fourth light-emitting stack, Each of the first to fourth light-emitting stacks includes at least one emission layer.

10. The display device according to claim 9, further comprising: A light control layer is provided on the light emitting element to transmit the source light or convert the source light into light having a wavelength different from that of the source light.

11. The display device according to claim 10, wherein: The light control layer comprises: a dike comprising a plurality of dike openings; and A plurality of light control patterns are respectively located in the plurality of bank openings, The plurality of light-controlling patterns do not overlap with the transmission area.

12. The display device according to claim 9, wherein: The at least one emission layer in each of the first to fourth light emitting stacks does not overlap the transmission region.

13. The display device according to claim 1, wherein: The second sensing electrode further comprises: The connecting pattern is between two adjacent second sensing patterns among the plurality of second sensing patterns and has a shape integrated with the plurality of second sensing patterns.

14. The display device according to claim 1, wherein: The input sensor further comprises: a sensing insulating layer between the plurality of bridge patterns and the plurality of first sensing patterns, Each of the plurality of bridge patterns is electrically connected to a corresponding one of the plurality of first sensing patterns through a lower contact hole defined in the sensing insulating layer.

15. The display device according to any one of claims 1 to 14, wherein: The transmission area includes: A first transmission region overlaps with the transparent electrode in a plane; and The second transmission area does not overlap with the transparent electrode on the plane.

16. A display device, comprising: A display panel including a display area having a transmissive area and a non-display area adjacent to the display area; as well as an input sensor, on the display panel, and comprising a plurality of conductive patterns, The plurality of conductive patterns include: a plurality of unit sensing patterns arranged along a first direction and a second direction crossing the first direction and insulated from each other; and a plurality of unit signal lines, respectively connected to at least some of the plurality of unit sensing patterns, wherein each of the plurality of unit sensing patterns comprises a plurality of grid lines, at least a transmission opening overlapping the transmission area is defined in the plurality of grid lines, and Each of the plurality of unit signal lines includes a plurality of sub-signal lines connected to a corresponding one of the plurality of unit sensing patterns and extending in the first direction.

17. The display device according to claim 16, wherein: The plurality of sub-signal lines include: a first sub-signal line connected to a first unit sensing pattern that is one of the plurality of unit sensing patterns and extending in the first direction; a second sub-signal line connected to the first unit sensing pattern, extending in the first direction, and spaced apart from the first sub-signal line in the second direction; and A third sub signal line is connected to the first unit sensing pattern, extends in the first direction, and is spaced apart from the first sub signal line and the second sub signal line in the second direction.

18. The display device according to claim 16, wherein: Each of the plurality of signal sub-lines has a width of 1 micrometer or more and 5 micrometers or less, and The distance between the plurality of sub-signal lines is greater than or equal to 3 micrometers and less than or equal to 7 micrometers.

19. The display device according to claim 16, wherein: The plurality of conductive patterns further include: An additional signal line has a shape integrated with a portion of the plurality of unit sensing patterns, is electrically connected to the portion of the plurality of unit sensing patterns, and overlaps the non-display area.

20. The display device according to claim 16, wherein: The input sensor further comprises: a sensing insulating layer between the plurality of unit sensing patterns and the plurality of unit signal lines, and Each of the plurality of unit signal lines is electrically connected to a corresponding one of the plurality of unit sensing patterns through a unit contact hole penetrating the sensing insulating layer.

21. The display device according to claim 16, wherein: The display area further includes: A plurality of pixel regions are adjacent to the transmission region and are configured to emit light.

22. The display device according to claim 21, wherein: In the display region, a ratio of an area of ​​the transmission region to a total area of ​​the transmission region and the plurality of pixel regions is 60% or more.

23. The display device according to claim 21, wherein: The plurality of pixel regions include a first pixel region, a second pixel region, and a third pixel region, and The transmission region is adjacent to each of the first pixel region, the second pixel region, and the third pixel region along the second direction.

24. The display device according to claim 21, wherein: The display panel includes a light emitting element configured to emit source light and overlap at least one of the plurality of pixel regions, and The light emitting element comprises: a first electrode; a first light emitting stack on the first electrode; a second light emitting stack on the first light emitting stack; a third light emitting stack on the second light emitting stack; a fourth light emitting stack on the third light emitting stack; a second electrode on the fourth light emitting stack; and a charge generation layer, respectively between the first light-emitting stack, the second light-emitting stack, the third light-emitting stack and the fourth light-emitting stack, Each of the first to fourth light-emitting stacks includes at least one emission layer.

25. The display device according to claim 24, further comprising: A light control layer is provided on the light emitting element to transmit the source light or convert the source light into light having a wavelength different from that of the source light.

26. The display device according to claim 25, wherein: The light control layer comprises: a dike having a plurality of dike openings; and A plurality of light control patterns are respectively located in the plurality of bank openings, The plurality of light-controlling patterns do not overlap with the transmission area.

27. The display device according to claim 24, wherein: The at least one emission layer in each of the first to fourth light emitting stacks does not overlap the transmission region.

28. A display device comprising: A display panel, comprising a display area and a non-display area adjacent to the display area, wherein the display area has a transmission area and a plurality of pixel areas adjacent to the transmission area; as well as an input sensor, on the display panel, and comprising a plurality of conductive patterns, wherein the plurality of conductive patterns include a plurality of sensing patterns arranged along a first direction and a second direction crossing the first direction, wherein the sensing pattern comprises a plurality of grid lines, wherein a transmission opening overlapping the transmission area and a plurality of pixel openings respectively overlapping the plurality of pixel areas are in the plurality of grid lines, and In the display region, a ratio of an area of ​​the transmission region to a total area of ​​the transmission region and the plurality of pixel regions is greater than 60%.

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