Global sensing current generation circuit and display device including the same

Abstract

The present embodiment relates to a global sensing current generation circuit and a display device including the same, and more particularly, to a global sensing current generation circuit that senses a global current in a display area, and a display device that compensates for fluctuations in the global current based on a current value of the sensed global current.

Description

Technical Field

[0001] The present disclosure relates to a global sensing current generation circuit and a display device including the global sensing current generation circuit. Background Art

[0002] The driving circuit of a display device includes a data driving circuit that provides a data voltage to a data line, a gate driving circuit that provides a scan signal (or a gate signal) to a gate line (or a scan line), and the like. The gate driving circuit may be directly formed on the same substrate together with circuit elements of a pixel array that constitutes a screen.

[0003] The circuit elements of the pixel array constitute a pixel circuit, and the pixel circuit is formed in each pixel defined in a matrix form by the data line and the gate line of the pixel array.

[0004] Here, each circuit element of the pixel array includes a plurality of transistors. That is, one pixel circuit includes a plurality of transistors.

[0005] Generally, as the driving time of the display device accumulates, electrical characteristics such as the threshold voltage of a transistor change.

[0006] When the electrical characteristics of the transistor change, the global current, which is the total current flowing through the pixel array, fluctuates, and this can reduce the brightness of the display device. Summary of the Invention

[0007] The present disclosure provides a global sensing current generation circuit that senses a global current in a display area, and a display device that compensates for fluctuations in the global current based on a current value of the sensed global current.

[0008] The problems to be solved in the present embodiment are not limited to the above problems, and those skilled in the art will clearly understand other problems not mentioned herein according to the following description.

[0009] The present embodiment provides a global sensing current generation circuit, including: a plurality of sensing current generation circuits; and a single current sensing line, the single current sensing line being connected to the plurality of sensing current generation circuits, and the sensing current generated by the plurality of sensing current generation circuits flowing through the single current sensing line during a current sensing period, wherein each of the sensing current generation circuits includes: a driving transistor configured to generate the sensing current based on its gate-source voltage; a capacitor configured to charge the gate-source voltage of the driving transistor; and a plurality of switching transistors electrically connected to the driving transistor and the capacitor and configured to sample the threshold voltage of the driving transistor.

[0010] The global sense current generation circuit may further include: a current summing circuit configured to receive the sense currents generated by the plurality of sense current generation circuits through the single current sense line and output a global current sense value obtained by summing the current values of the sense currents during the current sense period.

[0011] The global sense current generation circuit may further include: a switch circuit configured to electrically connect the single current sense line to the current summing circuit during the current sense period and electrically connect the single current sense line to a low-voltage power supply line commonly connected to a plurality of pixel circuits during a period other than the current sense period.

[0012] The global sense current generation circuit may further include: a current sense data line connected to the plurality of sense current generation circuits and configured to provide a current sense data voltage to the plurality of sense current generation circuits during the current sense period.

[0013] The driving transistor is the same type of transistor as the driving transistor included in the pixel circuit, and the plurality of switching transistors are the same type of transistors as the plurality of switching transistors included in the pixel circuit.

[0014] The plurality of switching transistors and the plurality of switching transistors included in the pixel circuit are oxide transistors.

[0015] When driving the pixel circuit while the low-voltage power supply line and the single current sense line are electrically connected through the switch circuit, at least one of a positive bias stress and a negative bias stress accumulates in the plurality of switching transistors and the plurality of switching transistors included in the pixel circuit.

[0016] The sense current generation circuit does not include a light-emitting element.

[0017] The sense current generation circuit may also be used as a repair pixel circuit for repairing defective pixel circuits included in the display area.

[0018] The global sense current generation circuit further includes: a current sense data line connected to the plurality of sense current generation circuits and configured to provide a current sense data voltage to the plurality of sense current generation circuits during the current sense period. When the Nth (N is a natural number greater than or equal to 1) sense current generation circuit among the plurality of sense current generation circuits is used as the repair pixel circuit, the current sense data voltage is not provided to the Nth sense current generation circuit during the current sense period.

[0019] The current summing circuit may include an analog-to-digital converter (ADC) circuit configured to sum the current values of the sensed currents as analog values and output a sum value as the global current sensed value (which is a digital value) during the current sensing period.

[0020] In another aspect, the present embodiment provides a display device including: a global sensed current generation circuit including: a plurality of sensed current generation circuits disposed adjacent to one side of a display area; a single current sensing line connected to the plurality of sensed current generation circuits, and through which the sensed currents generated by the plurality of sensed current generation circuits flow during a current sensing period; a current summing circuit configured to receive the sensed currents generated by the plurality of sensed current generation circuits through the single current sensing line and output a global current sensed value obtained by summing the current values of the sensed currents during the current sensing period; and a timing controller configured to receive the global current sensed value output from the current summing circuit, check a global current fluctuation amount in the display area using the global current sensed value, and compensate for the global current fluctuation amount.

[0021] The timing controller may compensate for the global current fluctuation amount by increasing the brightness value of the image data displayed in the display area as a whole.

[0022] The timing controller may increase the brightness value of the image data as a whole by using a gain value corresponding to the global current sensed value in a pre-stored look-up table.

[0023] The current summing circuit may include a single-slope analog-to-digital converter (ADC) circuit configured to sum the current values of the sensed currents as analog values during the current sensing period and output a sum value as the global current sensed value (which is a digital value).

[0024] A plurality of pixel circuits included in the display area may be in a driving state during the current sensing period.

[0025] The sensed current generation circuit may include: a driving transistor configured to generate the sensed current based on its gate-source voltage; a capacitor configured to charge the gate-source voltage of the driving transistor; and a plurality of switching transistors electrically connected to the driving transistor and the capacitor and configured to sample the threshold voltage of the driving transistor.

[0026] As described above, according to the present embodiment, the display device can sense the global current flowing through the pixel array and compensate for the fluctuation of the global current based on the current value of the sensed global current, thereby improving the brightness degradation caused by the accumulation of the usage time of the display device.

[0027] Various useful advantages and effects of the embodiment are not limited to the above, and will be more easily understood according to the description of the specific embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by referring to the following detailed description of the exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0029] Figure 1 and Figure 2 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0030] Figure 3 is a diagram showing the configuration of a gate driving circuit according to an embodiment of the present disclosure;

[0031] Figure 4 is a cross-sectional view showing a stacked configuration of a display device according to an embodiment of the present disclosure;

[0032] Figure 5 and Figure 6 is a diagram showing the arrangement position of a sensing region according to an embodiment of the present disclosure;

[0033] Figure 7 is a diagram exemplarily showing a general pixel circuit;

[0034] Figure 8 is a diagram exemplarily showing a sensing current generation circuit according to an embodiment of the present disclosure;

[0035] Figure 9 is a diagram showing a driving method of a global sensing current generation circuit according to an embodiment of the present disclosure;

[0036] Figure 10 and Figure 11 is a diagram showing the fluctuation of the global current according to the accumulation of the usage of the display device;

[0037] Figure 12 is a diagram showing a method of compensating for the fluctuation of the global current in a display device according to an embodiment of the present disclosure;

[0038] Figure 13is a diagram exemplarily showing a look-up table stored in a display device according to an embodiment of the present disclosure;

[0039] Figure 14 is a diagram showing waveforms of a scan signal and an EM signal generated to drive a sense current generation circuit;

[0040] Figures 15 to 19 is a circuit diagram showing a step-by-step operation of a sense current generation circuit during a driving period of the sense current generation circuit;

[0041] Figure 20 is a block diagram showing a global sense current generation circuit according to another embodiment of the present disclosure;

[0042] Figure 21 and Figure 22 is a diagram exemplarily showing a sense current generation circuit according to another embodiment of the present disclosure;

[0043] Figure 23 is a diagram showing a driving method of a global sense current generation circuit according to another embodiment of the present disclosure;

[0044] Figure 24 is a block diagram showing a global sense current generation circuit according to still another embodiment of the present disclosure; and

[0045] Figure 25 is a diagram exemplarily showing a sense current generation circuit according to still another embodiment of the present disclosure. Detailed Description

[0046] Advantages and features of the present disclosure and methods for implementing the same will be more clearly understood according to the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments and can be implemented in various different forms. On the contrary, these embodiments will make the disclosure of the present disclosure complete and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is defined only within the scope of the appended claims.

[0047] Shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings for describing embodiments of the present disclosure are exemplary, and the present disclosure is not limited to the items shown. The same reference numerals always refer to the same elements. Additionally, when describing the present disclosure, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present disclosure, the detailed description thereof will be omitted.

[0048] Terms such as "comprising", "including", "having", and "consisting of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular may include the plural unless otherwise expressly stated.

[0049] Even if not expressly stated, components are construed to include a normal range of error.

[0050] In the description of positional relationships, for example, when the positional relationship and the relationship of mutual connection between two parts are described as "on", "above", "below", "next to", "connected or coupled", "crossed or intersected", etc., unless the terms "immediately" or "directly" are used in the expression, one or more other parts may be inserted therebetween.

[0051] Terms such as "first", "second", etc. may be used to distinguish components from each other, but the functions or structures of the components are not limited by the ordinal numbers or component names in front of the components. Since the claims are written around the basic components, the ordinal numbers in front of the component names in the claims may not match the ordinal numbers in front of the component names in the embodiments.

[0052] The following embodiments may be partially or completely combined or combined with each other, and may be connected and operated in various technical ways. The embodiments may be executed independently of each other or in association with each other.

[0053] In the display device of the present disclosure, a display panel driving circuit, a pixel circuit, a level shifter, etc. may include transistors. The transistors may be implemented as oxide thin film transistors including an oxide semiconductor, polycrystalline thin film transistors including low temperature polycrystalline silicon (LTPS), etc.

[0054] A transistor is a three-terminal element including a gate, a source, and a drain. The source is a terminal that supplies carriers to the transistor. In the transistor, carriers start to flow out from the source. The drain is a terminal where carriers flow out of the transistor. The carrier flow in the transistor flows from the source to the drain. In the case of an N-channel transistor, since the carriers are electrons, the source voltage has a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. In an N-channel transistor, current flows from the drain to the source. In the case of a P-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a P-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain may change according to the applied voltage. Therefore, the present invention is not limited to the source and drain of the transistor. In the following description, the source and drain of the transistor are referred to as the first terminal and the second terminal.

[0055] The scan signal swings between a gate-on voltage and a gate-off voltage. The gate-off voltage can be interpreted as a first voltage, and the gate-on voltage can be interpreted as a second voltage. The transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an N-channel transistor, the gate-on voltage can be a gate-high voltage (VGH), and the gate-off voltage can be a gate-low voltage (VGL). In the case of a P-channel transistor, the gate-on voltage can be a gate-low voltage (VGL), and the gate-off voltage can be a gate-high voltage (VGH).

[0056] The present disclosure is applicable to any flat panel display device that requires integrated circuits and power circuits for driving pixels, such as an organic light emitting display (OLED), etc.

[0057] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0058] Figure 1 and Figure 2 is a block diagram showing a display device according to an embodiment of the present disclosure.

[0059] Referring Figure 1 and Figure 2 , a display device according to an embodiment includes a display panel 100 and a display panel driving circuit.

[0060] The display area AA of the display panel 100 includes a pixel array for displaying an image. A data voltage corresponding to image data is input to the pixel circuit P of the pixel array. The pixel array includes data lines DL, a plurality of gate lines GL intersecting the data lines DL, and pixel circuits P arranged in a matrix form. The display panel 100 may further include a power supply line commonly connected to the pixel circuit P. Here, the power supply line may include a low-voltage power supply line LVL for providing a low-voltage power supply ELVSS and a high-voltage power supply line (not shown) for providing a high-voltage power supply ELVDD.

[0061] When the resolution of the pixel array is n (n is a natural number) × m (m is a natural number), the pixel array includes n pixel columns and m pixel rows intersecting the pixel columns. The pixel rows include pixel circuits P arranged along a first direction X. The pixel columns include pixel circuits P arranged along a second direction Y. Generally, one horizontal period 1H can be a time obtained by dividing one frame period by m, where m is the number of pixel rows. In one horizontal period 1H, a data voltage can be input to the pixel circuits P of one pixel row.

[0062] The pixel circuit P can be divided into two or more sub-pixel circuits to achieve colors. For example, three pixel circuits arranged in sequence in the first direction X can be divided into a red sub-pixel circuit, a green sub-pixel circuit, and a blue sub-pixel circuit.

[0063] In addition, four pixel circuits arranged in sequence in the first direction X can be divided into a red sub-pixel circuit, a green sub-pixel circuit, a blue sub-pixel circuit, and a white sub-pixel circuit.

[0064] The above pixel circuit P is connected to a data line DL and a gate line GL. In one embodiment, when the display device is an organic light-emitting display device, the pixel circuit P is as Figure 7 shown.

[0065] Referring Figure 7 , the pixel circuit P may include a light-emitting element EL, a driving transistor DT that generates a driving current based on its gate-source voltage and supplies the driving current to the light-emitting element EL, a capacitor Cst connected between a second node n2 and a node on a power line through which a high-voltage power supply ELVDD is provided to charge the gate-source voltage of the driving transistor DT, a plurality of switching transistors (e.g., ST1 and ST2) electrically connected to the driving transistor DT and the capacitor Cst to sample the threshold voltage of the driving transistor DT, and the remaining switching transistors for driving the pixel. Although the pixel circuit P is shown in the drawings of the present disclosure as being composed of eight transistors and one capacitor, the present disclosure is not limited thereto. That is, the pixel circuit P may include three or more transistors and one or more capacitors.

[0066] In Figure 7 , the light-emitting element EL may be implemented as an OLED including an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, and an electron injection layer EIL, but is not limited thereto. When a voltage is applied to the anode and cathode terminals of the OLED, holes that have passed through the hole transport layer HTL and electrons that have passed through the electron transport layer ETL move to the emission layer EML to form excitons, and thus visible light is emitted from the emission layer EML. The OLED used as the light-emitting element may have a tandem structure in which a plurality of emission layers are stacked. The OLED having a tandem structure can improve the brightness and lifetime of the pixel.

[0067] The display panel 100 may further include a touch sensor. Here, the touch sensor may be provided on the screen of the display panel 100 in an on-cell type or an add-on type.

[0068] The touch sensor may be implemented in an in-cell type, where they are embedded in the pixel array.

[0069] In the present disclosure, a display panel driving circuit writes image data into a pixel circuit P of a display panel 100 under the control of a timing controller 130. The display panel driving circuit may include a data driving circuit 110, a gate driving circuit 120, a timing controller 130 for controlling the operation timing of the driving circuits 110 and 120, and a level shifter 140 connected between the timing controller 130 and the gate driving circuit 120. The display panel driving circuit may also include a power supply (not shown) for outputting a low-voltage power supply ELVSS, a high-voltage power supply ELVDD, etc. Here, the level shifter 140 may be included in the timing controller 130.

[0070] The data driving circuit 110 converts the image data received from the timing controller 130 as a digital signal into an analog gamma-compensated voltage for each frame to output a data voltage. The data voltage output from the data driving circuit 110 is supplied to a corresponding data line. The data driving circuit 110 uses a digital-to-analog converter that converts a digital signal into an analog gamma-compensated voltage to output the data voltage.

[0071] The data driving circuit 110 may be integrated into a source driver integrated circuit (SDIC). The source driver IC may be connected to a bonding pad of the display panel 100 using a tape automated bonding (TAB) method or a chip on glass (COG) method. The source driver IC may also be implemented using a chip on film (COF) method.

[0072] When the display panel 100 further includes a touch sensor, a touch sensor driving circuit for driving the touch sensor may be embedded in the source driver IC.

[0073] The gate driving circuit 120 may be formed in a non-display area (e.g., a border area) of the display panel 100 where no image is displayed, or may be at least partially disposed in the display area AA. The gate driving circuit 120 receives a clock signal from the level shifter 140 and outputs a scan signal to the gate line GL.

[0074] A switching transistor of the pixel circuit P connected to the gate line GL may be turned on in response to the gate-on voltage of the scan signal and turned off in response to the gate-off voltage.

[0075] The gate driving circuit 120 may include a configuration as Figure 3 shown.

[0076] Refer to Figure 3, the gate driving circuit 120 includes a transmission control signal driving circuit 310 and a scan driving circuit. The scan driving circuit may be composed of first to fourth scan driving circuits 321, 322, 323, and 324. Additionally, the second scan driving circuit 322 may be composed of an odd-numbered second scan driving circuit 322_O and an even-numbered second scan driving circuit 322_E.

[0077] The gate driving circuit 120 may be symmetrically configured such that shift registers are formed on both sides of the display area AA. In addition, the gate driving circuit 120 may be configured such that the shift register on one side of the display area AA includes the second scan driving circuits 322_O and 322_E, the fourth scan driving circuit 324, and the transmission control signal driving circuit 310, and the shift register on the other side of the display area AA includes the first scan driving circuit 321, the second scan driving circuits 322_O and 322_E, and the third scan driving circuit 323. However, the present disclosure is not limited thereto, and the transmission control signal driving circuit 310 and the first to fourth scan driving circuits 321, 322, 323, and 324 may be arranged differently according to embodiments.

[0078] The stages STG1 to STGn of the shift register may respectively include first scan signal generation circuits SC1(1) to SC1(n), second scan signal generation circuits SC2_O(1) to SC2_O(n) and SC2_E(1) to SC2_E(n), third scan signal generation circuits SC3(1) to SC3(n), fourth scan signal generation circuits SC4(1) to SC4(n), and transmission control signal generation circuits EM(1) to EM(n).

[0079] The first scan signal generation circuits SC1(1) to SC1(n) output first scan signals SC1(1) to SC1(n) through the first gate lines of the display panel 100. The second scan signal generation circuits SC2(1) to SC2(n) output second scan signals SC2(1) to SC2(n) through the second gate lines of the display panel 100. The third scan signal generation circuits SC3(1) to SC3(n) output third scan signals SC3(1) to SC3(n) through the third gate lines of the display panel 100. The fourth scan signal generation circuits SC4(1) to SC4(n) output fourth scan signals SC4(1) to SC4(n) through the fourth gate lines of the display panel 100. The transmission control signal generation circuits EM(1) to EM(n) output transmission control signals EM(1) to EM(n) through the emission control lines of the display panel 100.

[0080] The first scan signals SC1(1) to SC1(n) can be used as signals for driving a first transistor (e.g., a compensation transistor, etc.) included in the pixel circuit. The second scan signals SC2(1) to SC2(n) can be used as signals for driving a second transistor (e.g., a data supply transistor, etc.) included in the pixel circuit. The third scan signals SC3(1) to SC3(n) can be used as signals for driving a third transistor (e.g., a bias transistor, etc.) included in the pixel circuit. The fourth scan signals SC4(1) to SC4(n) can be used as signals for driving a fourth transistor (e.g., an initialization transistor, etc.) included in the pixel circuit. The emission control signals EM(1) to EM(n) can be used as signals for driving a fifth transistor (e.g., an emission control transistor, etc.) included in the pixel circuit. For example, when the emission control transistors of the pixels are controlled using the emission control signals EM(1) to EM(n), the emission time of the light-emitting elements changes.

[0081] Reference Figure 3 , a bias voltage bus VobsL, a first initialization voltage bus VarL, and a second initialization voltage bus ViniL can be provided between the gate driver circuit 120 and the display area AA.

[0082] The bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL can supply a bias voltage Vobs, a first initialization voltage Var, and a second initialization voltage Vini to the pixel circuit from a power supply circuit of the display device, respectively.

[0083] In the figure, the bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL are shown as being located only on one side (left or right) of the display area AA, but are not limited thereto, and they can be located on both sides of the display area AA. Further, even when they are located on one side, their positions are not limited to the left or right.

[0084] Reference Figure 3 , one or more optical areas OA1 and OA2 can be provided in the display area AA.

[0085] One or more optical areas OA1 and OA2 can be provided to overlap with one or more optoelectronic devices, such as an imaging device, such as a camera (image sensor), or a detection sensor, such as a proximity sensor and an illuminance sensor.

[0086] For the operation of an optoelectronic device, one or more optical regions OA1 and OA2 may have a light-transmitting structure formed therein to have a transmittance equal to or higher than a specific level. That is, the number of pixels per unit area in one or more optical regions OA1 and OA2 may be less than the number of pixels per unit area in a general region other than the optical regions OA1 and OA2 in the display region AA. That is, the resolution of one or more optical regions OA1 and OA2 may be lower than the resolution of the general region in the display region AA.

[0087] In one or more optical regions OA1 and OA2, a light-transmitting structure may be formed by patterning a cathode electrode in a portion where no pixel is provided. In this case, the patterned cathode electrode may be removed using a laser, or a material such as a cathode deposition prevention layer may be used to selectively form and pattern the cathode electrode.

[0088] Alternatively, a light-transmitting structure in one or more optical regions OA1 and OA2 may be formed by separating a light-emitting element EL from a pixel circuit in a pixel. That is, the light-emitting element EL of the pixel may be located on the optical regions OA1 and OA2, and a plurality of transistors TFT constituting the pixel circuit may be provided on the periphery of the optical regions OA1 and OA2 such that the light-emitting element EL and the pixel circuit are electrically connected through a transparent metal layer.

[0089] The timing controller 130 may multiply an input frame frequency by i (i is a natural number) to control the operation timing of the display panel driving circuits 110 and 120 at a frame frequency of input frame frequency × i Hz. The input frame frequency may be 60 Hz in the National Television Standards Committee (NTSC) method and may be 50 Hz in the Phase Alternating Line (PAL) method.

[0090] The timing controller 130 receives image data and a timing signal synchronized therewith from the host system 200. The image data received by the timing controller 130 is a digital signal. The timing controller 130 may convert the image data into a data format used by the data driving circuit 110 and transmit it to the data driving circuit 110. Here, the timing signal may include a vertical synchronization signal, a horizontal synchronization signal, a clock signal, a data enable signal, etc. Here, the data enable signal has a period of one horizontal period 1H.

[0091] Based on the timing signal received from the host system 200, the timing controller 130 may generate a data timing control signal for controlling the data driving circuit 110, a gate timing control signal for controlling the gate driving circuit 120, etc. The gate timing control signal may be generated as a clock of a digital signal voltage level.

[0092] The host system 200 can be any one of a television, a set-top box, a navigation system, a personal computer (PC), a home theater, a mobile system, and a wearable system. In mobile devices and wearable devices, the data driving circuit 110, the timing controller 130, the level shifter 140, etc. can be integrated into a single driving IC (not shown). In a mobile system, the host system 200 can be implemented as an application processor (AP). The host system 200 can transmit image data to the driving IC through a Mobile Industry Processor Interface (MIPI). The host system 200 can be connected to the driving IC through a flexible printed circuit board (FPCB).

[0093] In the present disclosure, the switching transistors of the pixel circuit P can be implemented as N-channel oxide thin film transistors.

[0094] In addition, some of the switching transistors of the pixel circuit P can be implemented as oxide thin film transistors having a low cut-off current, while other switching transistors can be implemented as polycrystalline thin film transistors having a high on-current characteristic.

[0095] For example, in Figure 7 , the switching transistors ST1 and ST2 (shown in a dotted rectangle) electrically connected to the driving transistor DT and the capacitor Cst can be implemented as oxide thin film transistors, while the remaining transistors ST3 to ST7 can be implemented as polycrystalline thin film transistors.

[0096] Here, the cut-off current can refer to the leakage current of the transistor. In addition, the oxide thin film transistor can be an N-channel transistor, and the polycrystalline thin film transistor can be a P-channel or N-channel transistor.

[0097] The gate on-voltage of the N-channel oxide thin film transistor or the N-channel polycrystalline thin film transistor can be the gate high voltage, and its gate off-voltage can be the gate low voltage.

[0098] The gate on-voltage of the P-channel polycrystalline thin film transistor can be the gate low voltage, and its gate off-voltage can be the gate high voltage.

[0099] As described above, when the switching transistors are composed of oxide thin film transistors or polycrystalline thin film transistors, the display panel 100 can have the cross-sectional structure as shown below.

[0100] Figure 4 is a cross-sectional view showing a stacked configuration of a display device according to an embodiment of the present disclosure.

[0101] In Figure 4 , the switching transistors will be referred to as switching thin film transistors.

[0102] Figure 4The cross-sectional view includes two switching thin-film transistors TFT1 and TFT2 and a capacitor CST. The two switching thin-film transistors TFT1 and TFT2 include a polycrystalline thin-film transistor TFT1 containing a polycrystalline semiconductor material and an oxide thin-film transistor TFT2 containing an oxide semiconductor material.

[0103] Figure 4 The polycrystalline thin-film transistor TFT1 shown is an emission switching thin-film transistor connected to the light-emitting element EL, and the oxide thin-film transistor TFT2 is any one of the switching thin-film transistors connected to the capacitor CST.

[0104] In Figure 4 a pixel includes a light-emitting element EL and a pixel driving circuit that applies a driving current to the light-emitting element EL. The pixel driving circuit is provided on the substrate 411, and the light-emitting element EL is provided on the pixel driving circuit. In addition, an encapsulation layer 420 is provided on the light-emitting element EL. The encapsulation layer 420 protects the light-emitting element EL.

[0105] The pixel driving circuit may refer to a pixel array portion including a driving thin-film transistor, a switching thin-film transistor, and a capacitor. In addition, the light-emitting element EL may refer to an array portion for light emission, including an anode electrode, a cathode electrode, and an emission layer provided between the anode electrode and the cathode electrode.

[0106] The substrate 411 can be implemented as a multilayer stack of alternating organic and inorganic layers. For example, the substrate 411 can be formed by alternately stacking an organic layer such as polyimide and an inorganic layer such as silicon oxide (SiO2).

[0107] A lower buffer layer 412a is formed on the substrate 411. The lower buffer layer 412a is used to block moisture and the like that may penetrate from the outside, and can be used by stacking silicon oxide (SiO2) layers and the like in multiple layers. An auxiliary buffer layer 412b can be further provided on the lower buffer layer 412a to protect the elements from moisture penetration.

[0108] The polycrystalline thin-film transistor TFT1 is formed above the substrate 411. The polycrystalline thin-film transistor TFT1 can use a polycrystalline semiconductor as the active layer. The polycrystalline thin-film transistor TFT1 includes a first active layer ACT1 having a channel through which electrons or holes move, a first gate electrode GE1, a first source electrode SD1, and a first drain electrode SD2.

[0109] The first active layer ACT1 includes a first channel region, a first source region provided on one side of the first channel region, and a first drain region provided on the other side of the first channel region.

[0110] The first source region and the first drain region are regions formed by doping Group 5 or Group 3 impurity ions (such as phosphorus (P) or boron (B)) into an intrinsic polycrystalline semiconductor material at a predetermined concentration to form a conductor. The first channel region provides a path for electrons or holes to move through by maintaining the intrinsic state of the polycrystalline semiconductor material.

[0111] Meanwhile, the polycrystalline thin film transistor TFT1 includes a first gate electrode GE1 overlapping with the first channel region of the first active layer ACT1. A first gate insulating layer 413 is disposed between the first gate electrode GE1 and the first active layer ACT1. The first gate insulating layer 413 can be used as a single-layer or multi-layer inorganic layer, such as a silicon oxide (SiO2) layer, a silicon nitride (SiN x ) layer, etc.

[0112] In one embodiment, the polycrystalline thin film transistor TFT1 has a top-gate structure, in which the first gate electrode GE1 is located above the first active layer ACT1. Therefore, the first electrode CST1 included in the capacitor CST and the light-shielding layer LS included in the oxide thin film transistor TFT2 can be formed of the same material as the first gate electrode GE1. Forming the first gate electrode GE1, the first electrode CST1, and the light-shielding layer LS through a single mask process can reduce the mask process. However, the present disclosure is not limited thereto, and the light-shielding layer LS can be formed on the lower buffer layer 412a and the auxiliary buffer layer 412b through a separate mask process. In this case, the light-shielding layer LS can be formed under any transistor, not limited to the oxide thin film transistor TFT2. Additionally, the light-shielding layer LS can be disposed under the capacitor CST to overlap therewith to form a double capacitor.

[0113] The first gate electrode GE1 is made of a metal material. For example, the first gate electrode GE1 can be a single-layer or multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but is not limited thereto.

[0114] A first interlayer insulating layer 414 is disposed on the first gate electrode GE1. The first interlayer insulating layer 414 can be formed of silicon oxide (SiO2), silicon nitride (SiN x ) and the like.

[0115] The display panel 100 may further include an upper buffer layer 415, a second gate insulating layer 416, and a second interlayer insulating layer 417 sequentially disposed on the first interlayer insulating layer 414. The polycrystalline thin film transistor TFT1 includes a first source electrode SD1 and a first drain electrode SD2 formed on the second interlayer insulating layer 417 and respectively connected to the first source region and the first drain region.

[0116] The first source electrode SD1 and the first drain electrode SD2 can be a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but are not limited thereto.

[0117] The upper buffer layer 415 separates the second active layer ACT2 of the oxide thin film transistor TFT2 made of an oxide semiconductor material from the first active layer ACT1 made of a polycrystalline semiconductor material, and provides a basis for forming the second active layer ACT2.

[0118] The second gate insulating layer 416 covers the second active layer ACT2 of the oxide thin film transistor TFT2. The second gate insulating layer 416 is formed on the second active layer ACT2 made of an oxide semiconductor material, and is thus realized as an inorganic layer. For example, the second gate insulating layer 416 can be formed of silicon oxide (SiO2), silicon nitride (SiN x ) and the like.

[0119] The second gate electrode GE2 is made of a metal material. For example, the second gate electrode GE2 can be a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0120] Meanwhile, the oxide thin film transistor TFT2 includes a second active layer ACT2 formed on the upper buffer layer 415 and made of an oxide semiconductor material, a second gate electrode GE2 disposed on the second gate insulating layer 416, and a second source electrode SD3 and a second drain electrode SD4 disposed on the second interlayer insulating layer 417.

[0121] The second active layer ACT2 is made of an oxide semiconductor material, and includes an intrinsic second channel region not doped with impurities, and a second source region and a second drain region doped with impurities to become conductors.

[0122] The oxide thin film transistor TFT2 further includes a light shielding layer LS located below the upper buffer layer 415 and overlapping with the second active layer ACT2. The light shielding layer LS can block light incident on the second active layer ACT2 to ensure the reliability of the oxide thin film transistor TFT2. The light shielding layer LS is made of the same material as the first gate electrode GE1, and can be formed on the top surface of the first gate insulating layer 413. The light shielding layer LS can be electrically connected to the second gate electrode GE2 to form a double gate.

[0123] The second source electrode SD3 and the second drain electrode SD4 can be formed simultaneously on the second interlayer insulating layer 417 using the same material as the first source electrode SD1 and the first drain electrode SD2, thereby reducing the number of mask processes.

[0124] Meanwhile, the capacitor CST can be implemented by disposing a second electrode CST2 on the first interlayer insulating layer 414 to overlap with the first electrode CST1. The second electrode CST2 can be a single layer or a multi-layer made of any one of, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0125] The capacitor CST stores the data voltage applied through the data line DL for a specific period of time and supplies it to the light-emitting element EL. The capacitor CST includes two electrodes corresponding to each other and a dielectric disposed therebetween. The first interlayer insulating layer 414 is located between the first electrode CST1 and the second electrode CST2.

[0126] The first electrode CST1 or the second electrode CST2 of the capacitor CST can be electrically connected to the second source electrode SD3 or the second drain electrode SD4 of the oxide thin film transistor TFT2. However, the present disclosure is not limited thereto, and the connection relationship of the capacitor CST can vary according to the pixel driving circuit.

[0127] Meanwhile, the first planarization layer 418 and the second planarization layer 419 are sequentially disposed on the pixel driving circuit to planarize the top of the pixel driving circuit. The first planarization layer 418 and the second planarization layer 419 can be organic layers such as polyimide or acrylic resin.

[0128] Then, the light-emitting element EL is formed on the second planarization layer 419.

[0129] The light-emitting element EL includes an anode electrode ANO, a cathode electrode CAT, and an emission layer LEL disposed between the anode electrode ANO and the cathode electrode CAT. When implemented in a pixel driving circuit that commonly uses a low potential voltage connected to the cathode electrode CAT, the anode electrode ANO is set as the individual electrode for each sub-pixel. When implemented in a pixel driving circuit that commonly uses a high potential voltage, the cathode electrode CAT can be set as the individual electrode for each sub-pixel.

[0130] The light-emitting element EL is electrically connected to the driving element through an intermediate electrode CNE disposed on the first planarization layer 418. Specifically, the anode electrode ANO of the light-emitting element EL and the first source electrode SD1 of the polycrystalline thin film transistor TFT1 constituting the pixel driving circuit are connected to each other through the intermediate electrode CNE.

[0131] The anode electrode ANO is connected to the intermediate electrode CNE exposed through the contact hole penetrating the second planarization layer 419. Additionally, the intermediate electrode CNE is connected to the first source electrode SD1 exposed through the contact hole penetrating the first planarization layer 418.

[0132] The intermediate electrode CNE serves as a medium for connecting the first source electrode SD1 to the anode electrode ANO. The intermediate electrode CNE can be made of a conductive material such as copper (Cu), silver (Ag), molybdenum (Mo), or titanium (Ti).

[0133] The anode electrode ANO can be formed as a multi-layer structure including a transparent conductive layer and an opaque conductive layer with high reflection efficiency. The transparent conductive layer can be made of a material such as indium tin oxide (ITO) or indium zinc oxide (IZO) having a relatively large work function value, while the opaque conductive layer can be formed as a single-layer or multi-layer structure containing aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or an alloy thereof. For example, the anode electrode ANO can be formed as a structure in which the transparent conductive layer, the opaque conductive layer, and the transparent conductive layer are stacked in sequence, or a structure in which the transparent conductive layer and the opaque conductive layer are stacked in sequence.

[0134] The emission layer LEL is formed by stacking a hole-related layer, an organic emission layer, and an electron-related layer in this order or in the reverse order on the anode electrode ANO.

[0135] The bank layer BNK can be a pixel defining layer that exposes the anode electrode ANO of each pixel. The bank layer BNK can be made of an opaque material (e.g., black) to prevent light interference between adjacent pixels. In this case, the bank layer BNK includes a light-shielding material made of at least one of a color pigment, an organic black, and carbon. Spacers can be further provided on the bank layer BNK.

[0136] The cathode electrode CAT is formed opposite to the anode electrode ANO, with the emission layer LEL interposed between the cathode electrode CAT and the anode electrode ANO, and the cathode electrode CAT is formed on the top surface and the side surface of the emission layer LEL. The cathode electrode CAT can be integrally formed above the entire display area AA. When applied to a top-emission type organic light-emitting display device, the cathode electrode CAT can be formed of a transparent conductive layer such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0137] An encapsulation layer 420 for suppressing moisture penetration can be further provided on the cathode electrode CAT.

[0138] The encapsulation layer 420 can block the penetration of external moisture or oxygen into the light-emitting element EL that is vulnerable to external moisture or oxygen. To achieve this, the encapsulation layer 420 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, but is not limited thereto. In the present disclosure, the structure of the encapsulation layer 420 in which the first encapsulation layer 421, the second encapsulation layer 422, and the third encapsulation layer 423 are sequentially stacked will be described as an example.

[0139] The first encapsulation layer 421 is formed above the substrate 411 on which the cathode electrode CAT is formed. The third encapsulation layer 423 is formed above the substrate 411 on which the second encapsulation layer 422 is formed, and may be formed to surround the top surface, bottom surface, and side surface of the second encapsulation layer 422 together with the first encapsulation layer 421. The first encapsulation layer 421 and the third encapsulation layer 423 can minimize or prevent the penetration of external moisture or oxygen into the light-emitting element EL. The first encapsulation layer 421 and the third encapsulation layer 423 may be made of an inorganic insulating material capable of low-temperature deposition, such as silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Since the first encapsulation layer 421 and the third encapsulation layer 423 are deposited in a low-temperature atmosphere, the light-emitting element EL vulnerable to a high-temperature atmosphere can be prevented from being damaged during the deposition of the first encapsulation layer 421 and the third encapsulation layer 423.

[0140] The second encapsulation layer 422 can be used as a buffer layer to relieve the stress between the layers caused by the bending of the display device 40 and can flatten the step difference between the layers. The second encapsulation layer 422 may be formed of a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon oxycarbide (SiOC) or a photosensitive organic insulating material such as photoacrylic above the substrate 411 on which the first encapsulation layer 421 is formed, but is not limited thereto. When the second encapsulation layer 422 is formed by an inkjet method, a dam DAM may be provided to prevent the second encapsulation layer 422 in liquid form from spreading to the edge of the substrate 411. The DAM may be provided closer to the edge of the substrate 411 than the second encapsulation layer 422. Due to the dam DAM, the second encapsulation layer 422 can be prevented from spreading to the pad area having a conductive pad provided at the outermost portion of the substrate.

[0141] The dam DAM is designed to prevent the spread of the second encapsulation layer 422. However, if the second encapsulation layer 422 is formed to exceed the height of the dam DAM during the process, the second encapsulation layer 422 as an organic layer may be exposed to the outside, which can facilitate the penetration of moisture and the like into the light-emitting element. Therefore, to prevent this, at least ten or more dams DAM may be formed in an overlapping manner.

[0142] The dam DAM can be disposed on the second interlayer insulating layer 417 of the non-display area NA.

[0143] In addition, the dam DAM can be formed simultaneously with the first planarization layer 418 and the second planarization layer 419. When forming the first planarization layer 418, the lower layer of the dam DAM can be formed together, and when forming the second planarization layer 419, the upper layer of the dam DAM can be formed together, and they can be stacked in a double structure.

[0144] Therefore, the dam DAM can be made of the same material as the first planarization layer 418 and the second planarization layer 419, but is not limited thereto.

[0145] The DAM can be formed to overlap with the low-voltage power line LVL. For example, in the non-display area NA, the low-voltage power line LVL can be formed in the lower layer of the area where the dam DAM is located.

[0146] The low-voltage power line LVL and the gate driving circuit 120 configured in the form of the gate in panel (GIP) can be formed around the outer periphery of the display panel, and the low-voltage power line LVL can be located at a position more outward than the gate driving circuit 120. In addition, the low-voltage power line LVL can be connected to the cathode electrode CAT to apply a common voltage. The gate driving circuit 120 is simply shown in the plan view and cross-sectional view of the drawings, but the gate driving circuit 120 can be configured using thin film transistors having the same structure as the thin film transistors in the display area AA.

[0147] The low-voltage power line LVL is disposed more outward than the gate driving circuit 120. The low-voltage power line LVL is disposed more outward than the gate driving circuit 120 and surrounds the display area AA. For example, the low-voltage power line LVL can be made of the same material as the first gate electrode GE1, but is not limited thereto, and can be made of the same material as the second electrode CST2 or the first source electrode SD1 and the first drain electrode SD2, but is not limited thereto.

[0148] In addition, the low-voltage power line LVL can be electrically connected to the cathode electrode CAT. The low-voltage power line LVL can supply the low-voltage power ELVSS to the pixels in the display area AA.

[0149] The touch layer can be disposed on the encapsulation layer 420. In the touch layer, the touch buffer layer 451 can be located between the touch sensor metal including the touch electrode connection lines 452 and 454 and the touch electrodes 455 and 456 and the cathode electrode CAT of the light-emitting element EL.

[0150] The touch buffer layer 451 can prevent chemical solutions (developer, etchant, etc.) used in the manufacturing process of the touch sensor metal disposed on the touch buffer layer 451, moisture from the outside, etc. from penetrating the light-emitting layer LEL containing organic materials. Therefore, the touch buffer layer 451 can prevent damage to the light-emitting element LEL vulnerable to chemical solutions or moisture.

[0151] The touch buffer layer 451 can be formed of an organic insulating material capable of being formed at a low temperature equal to or lower than a specific temperature (e.g., 100 °C) and having a low dielectric constant of 1 to 3 to prevent damage to the light-emitting layer LEL containing organic materials vulnerable to high temperatures. For example, the touch buffer layer 451 can be formed of an acrylic-based, epoxy-based, or silicone-based material. The touch buffer layer 451 made of an organic insulating material and having a planarization property can prevent damage to the encapsulation layer 420 caused by the bending of the organic light-emitting display device and the rupture of the touch sensor metal formed on the touch buffer layer 451.

[0152] According to the mutual capacitance-based touch sensor structure, the touch electrodes 455 and 456 can be disposed above the touch buffer layer 451, and the touch electrodes 455 and 456 can be arranged to cross each other.

[0153] The touch electrode connection lines 452 and 454 can electrically connect the touch electrodes 455 and 456 to each other. The touch electrode connection lines 452 and 454 and the touch electrodes 455 and 456 can be located on different layers, with a touch insulating layer 453 interposed therebetween.

[0154] The touch electrode connection lines 452 and 454 can be arranged to overlap with the bank layer BNK to prevent a reduction in the aperture ratio.

[0155] Meanwhile, a part of the touch electrode connection line 452 can be electrically connected to a touch driving circuit (not shown) through a touch pad PAD that extends beyond the top portion and side surfaces of the encapsulation layer 420 and the top portion and side surfaces of the dam DAM.

[0156] A part of the touch electrode connection line 452 can receive a touch driving signal from the touch driving circuit and transmit it to the touch electrodes 455 and 456, and can also transmit a touch sensing signal from the touch electrodes 455 and 456 to the touch driving circuit.

[0157] The touch passivation layer 457 can be disposed on the touch electrodes 455 and 456. Although the touch passivation layer 457 is shown as being disposed only on the touch electrodes 455 and 456, the present disclosure is not limited thereto, and the touch passivation layer 457 can extend before or after the dam DAM to be disposed on the touch electrode connection line 452.

[0158] In addition, a color filter (not shown) may be further disposed on the encapsulation layer 420. The color filter may be located on the touch layer or may be located between the encapsulation layer 420 and the touch layer.

[0159] On the other hand, since oxide thin film transistors are subject to more stress from temperature, light, etc. than polycrystalline thin film transistors, electrical characteristics such as the threshold voltage of oxide thin film transistors change as the usage time of the display device accumulates.

[0160] When the electrical characteristics of the oxide thin film transistors change, the global current, which is the total current flowing through the pixel array in the display area AA, may decrease, resulting in an overall deterioration of the brightness of the display device. Here, the stress may be one or more of positive bias temperature stress (PBTS), negative bias temperature stress (NBTS), and negative bias temperature illumination stress (NBTiS).

[0161] In the present disclosure, a plurality of sensing current generation circuits CG for sensing the global current of the pixel array (i.e., the global current of the display area AA) may be disposed on one side of the display area AA to sense the global current of the display area AA. Here, the global current of the display area AA may gradually decrease as the usage time of the display device accumulates. Therefore, by repeatedly sensing the global current at time intervals, the fluctuation of the global current of the display area AA can be checked, and the fluctuation of the global current can be compensated.

[0162] Specifically, a display device according to an embodiment of the present disclosure may include a global sensing current generation circuit capable of sensing the global current in the display area AA.

[0163] Reference Figure 1 , the global sensing current generation circuit may include a plurality of sensing current generation circuits CG, a single current sensing line GCL_S, a switching circuit SW_sel, a current sensing data line DL_S, and a current summing circuit 112.

[0164] In an embodiment of the present disclosure, the sensing area SA where a plurality of sensing current generation circuits CG are provided may be located on one side of the display area AA as shown in Figure 1 and Figure 5 , or may be located on the other side of the display area AA as shown in Figure 2 and Figure 6 .

[0165] When the sensing area SA is located on one side and the other side of the display area AA, as shown in Figure 2 , a plurality of sensing current generation circuits CG, a single current sensing line GCL_S, a switching circuit SW_sel, and a current sensing data line DL_S may be provided on both sides of the display area AA.

[0166] A plurality of sense current generation circuits CG may be disposed adjacent to one side of the display area AA, and may be supplied with a sense current data voltage during a current sensing period.

[0167] Alternatively, a plurality of sense current generation circuits CG may be disposed adjacent to both sides of the display area AA, and may be supplied with a sense current data voltage during a current sensing period. Here, the plurality of sense current generation circuits CG may be disposed on one or both sides of the display area AA in the second direction Y. That is, the plurality of sense current generation circuits CG may be disposed in the form of pixel columns. Although Figure 1 and Figure 2 illustrates that the plurality of sense current generation circuits CG are disposed on one or both sides of the display area AA in the form of one pixel column, but the present disclosure is not limited thereto, and the plurality of sense current generation circuits CG may be disposed in the form of two or more pixel columns.

[0168] In the present disclosure, when the display area AA includes m pixel rows, since one or more sense current generation circuits CG may be disposed on one or both sides of each pixel row, the number of sense current generation circuits CG may be an integer multiple of m.

[0169] Here, a plurality of pixel circuits P are disposed in the display area AA. As Figure 7 shown, the pixel circuit P may include a light-emitting element EL, a capacitor Cst, a driving transistor DT, a plurality of switching transistors (e.g., ST1 and ST2), and the remaining switching transistors ST3 to ST7.

[0170] As Figure 8 shown, the sense current generation circuit CG includes a sense driving transistor DT_S that generates a sense current based on its gate-source voltage, a sense capacitor Cst_S that charges the gate-source voltage of the sense driving transistor DT_S, a plurality of sense switching transistors (e.g., ST1_S and ST2_S) electrically connected to the sense driving transistor DT_S and the sense capacitor Cst_S to sample the threshold voltage of the sense driving transistor, and the remaining sense switching transistors ST3_S to ST7_S. In addition, the sense current generation circuit CG does not include a light-emitting element.

[0171] The sense driving transistor DT_S is the same type of transistor as the driving transistor DT, and the plurality of sense switching transistors ST1_S and ST2_S are the same type of transistors as the plurality of switching transistors ST1 and ST2. The remaining sense switching transistors ST3_S to ST7_S are also the same type of transistors as the remaining switching transistors ST3 to ST7.

[0172] The number of sensing switch transistors ST1_S and ST2_S is the same as the number of switch transistors ST1 and ST2, and the number of the remaining sensing switch transistors ST3_S to ST7_S is the same as the number of the remaining switch transistors ST3 to ST7.

[0173] In addition, a plurality of switch transistors ST1 and ST2 and one or more sensing switch transistors ST1_S and ST2_S may be oxide thin film transistors, while the remaining switch transistors ST3 to ST7 and the remaining sensing switch transistors ST3_S to ST7_S may be polycrystalline thin film transistors.

[0174] That is, except for the light emitting element, the sensing current generation circuit CG has the same components as the pixel circuit P.

[0175] In Figure 1 a single current sensing line GCL_S is commonly connected to a plurality of sensing current generation circuits CG.

[0176] A switch circuit SW_sel is provided at one end of the single current sensing line GCL_S.

[0177] The switch circuit SW_sel electrically connects the single current sensing line GCL_S to the current summing circuit 112 during the current sensing period, and electrically connects the single current sensing line GCL_S to the low voltage power supply line LVL commonly connected to a plurality of pixel circuits during periods other than the current sensing period. Here, the low voltage power supply line LVL is a line for providing a low voltage power supply ELVSS. The low voltage power supply ELVSS may be set to -5V, but is not limited thereto.

[0178] Although not shown in Figure 1 a gate line GL for providing a scan signal, a high voltage power supply line (not shown) for providing a high voltage power supply ELVDD, etc. are also connected to the pixel circuit P and the sensing current generation circuit CG.

[0179] Therefore, when driving a plurality of pixel circuits P while the switch circuit SW_sel electrically connects the low voltage power supply line LVL to the single current sensing line GCL_S, the transistors of the plurality of sensing current generation circuits CG and the transistors of the plurality of pixel circuits P disposed adjacent to the display area AA can operate in the same manner.

[0180] As a result, the oxide thin film transistors in the sensing current generation circuit CG are subjected to the same level of stress as the oxide thin film transistors in the pixel circuit P.

[0181] That is, when driving a plurality of pixel circuits P while the low-voltage power line LVL and a single current sensing line GCL_S are electrically connected through a switching circuit SW_sel, at least one of a positive bias stress and a negative bias stress can be accumulated in a plurality of switching transistors ST1 and ST2 and a plurality of sensing switching transistors ST1_S and ST2_S. Here, the positive bias stress can be a positive bias temperature stress (PBTS), a positive bias temperature illumination stress (PBTiS), etc., and the negative bias stress can be a negative bias temperature stress (NBTS), a negative bias temperature illumination stress (NBTiS), etc.

[0182] Meanwhile, the current sensing data lines DL_S are commonly connected to a plurality of sense current generation circuits CG, and a current sensing data voltage is provided to the plurality of sense current generation circuits CG during a current sensing period. Here, the current sensing data voltage can be output from the data driving circuit 110.

[0183] The current summing circuit 112 receives the sense currents generated by the plurality of sense current generation circuits CG during the current sensing period through a single current sensing line GCL_S, and outputs a global current sensing value obtained by summing the current values of the sense currents.

[0184] Here, since the plurality of sense current generation circuits CG are arranged in the form of pixel columns and connected to the corresponding gate lines GL, the sense currents can be sequentially generated and output in a direction from the top to the bottom or from the bottom to the top of the display panel 100. In addition, the current summing circuit 112 can sequentially receive the sense currents through a single current sensing line GCL_S.

[0185] The current summing circuit 112 can include an analog-to-digital converter (ADC) circuit that sums the current values of the sense currents as analog values, and outputs the sum value as a global current sensing value (which is a digital value) during the current sensing period. Here, the ADC circuit can be a single-slope ADC circuit, which is an integrating ADC circuit. In addition, the sense current can be a driving current of the sense current generation circuit CG, which reflects the stress accumulated in one or more sensing switching transistors (i.e., one or more oxide thin film transistors).

[0186] In the above global sense current generation circuit, the plurality of sense current generation circuits CG, the single current sensing line GCL_S, and the current sensing data lines DL_S can be provided in the display panel 100 including the display area AA, and the switching circuit SW_sel and the current summing circuit 112 can be provided in the data driving circuit 110 that provides data voltages to the plurality of pixel circuits P.

[0187] Meanwhile, the global current sensing value output from the current summing circuit 112 can be received by the timing controller 130.

[0188] When receiving the global current sensing value, the timing controller 130 may use the global current sensing value to check the amount of global current fluctuation in the display area AA. Then, the timing controller 130 may compensate for the amount of global current fluctuation. Details will be provided with reference to Figure 12 and Figure 13 which will be described in detail.

[0189] Hereinafter, a driving method of the global sensing current generation circuit will be described.

[0190] Figure 9 is a diagram showing a driving method of the global sensing current generation circuit according to an embodiment of the present disclosure.

[0191] Reference Figure 9 , during a normal period (normal timing), a switching signal of a first voltage level Lv1 may be input to the switching circuit SW_sel of the global sensing current generation circuit. The normal period is a period other than the current sensing period (GC sensing timing). The switching circuit SW_sel that has received the switching signal of the first voltage level Lv1 may electrically connect a single current sensing line GCL_S to the low-voltage power supply line LVL.

[0192] In addition, during the normal period (normal timing), the current sensing data voltage Vdata_S is not provided to the plurality of sensing current generation circuits CG.

[0193] However, when driving the plurality of pixel circuits P, the scan signal, the high-voltage power supply ELVDD, etc. provided to the plurality of pixel circuits P are also provided to the plurality of sensing current generation circuits CG. Therefore, when driving the plurality of pixel circuits P during the normal period (normal timing), the transistors of the plurality of sensing current generation circuits CG and the transistors of the plurality of pixel circuits P disposed adjacent to the display area AA may operate in the same manner.

[0194] Therefore, stress at the same level as the positive bias stress or negative bias stress accumulated in the oxide thin film transistor of the pixel circuit P is also accumulated in the oxide thin film transistor of the sensing current generation circuit CG. Here, during the normal period (normal timing), the data voltage Vdata is provided to the plurality of pixel circuits P, and the current sensing data voltage Vdata_S is not provided to the plurality of sensing current generation circuits CG. However, whether the data voltage is provided may not significantly affect the stress of the oxide thin film transistor.

[0195] This is because the oxide thin film transistor is sensitive to the negative bias stress received when the transistor is turned off, and thus changes in electrical characteristics mainly occur due to the negative bias stress.

[0196] As described above, when the switch circuit SW_sel electrically connects the single current sensing line GCL_S to the low-voltage power line LVL during the normal period (normal timing), stress at the same level as that of the plurality of pixel circuits P can accumulate in the plurality of sense current generation circuits CG.

[0197] On the other hand, during the current sensing period (GC sensing timing), a switching signal of the second voltage level Lv2 can be input to the switch circuit SW_sel. The switch circuit SW_sel that has received the switching signal of the second voltage level Lv2 can electrically connect the single current sensing line GCL_S to the current summing circuit 112.

[0198] In addition, during the current sensing period (GC sensing timing), the current sensing data voltage Vdata_S can be provided to the plurality of sense current generation circuits CG. Here, the current sensing data voltage Vdata_S provided to each of the plurality of sense current generation circuits CG can have the same voltage value. For example, the current sensing data voltage Vdata_S can have a voltage value corresponding to a luminance of 600 nits.

[0199] In addition, the current sensing data voltage Vdata_S can be sequentially provided to the plurality of sense current generation circuits CG by the scan signals sequentially output by the gate driving circuit 120.

[0200] The plurality of sense current generation circuits CG provided with the current sensing data voltage Vdata_S can each generate a sense current.

[0201] The sense currents generated by the plurality of sense current generation circuits CG are input to the current summing circuit 112 through the single current sensing line GCL_S. Here, the plurality of sense current generation circuits CG can sequentially generate and output sense currents, and the current summing circuit 112 can sequentially receive the sense currents through the single current sensing line GCL_S. Here, the sense current can be a drive current of the sense current generation circuit CG, which reflects the stress accumulated in one or more sense switching transistors (i.e., one or more oxide thin film transistors) included in the sense current generation circuit CG.

[0202] The current summing circuit 112 that has received the sense current sums the current values of the sense currents and outputs the sum value as the global current sensing value GC Sen. Here, since the sense currents are input sequentially, the global current sensing value GCSen can increase linearly during the current sensing period (GC sensing timing).

[0203] In addition, at the end of the current sensing period (GC sensing timing) when all the sensed currents are input to the current summing circuit 112, the global current sensing value GC Sen output from the current summing circuit 112 can be used as the global current sensing value for the display area AA.

[0204] That is, since the pixel circuits P and the sensed current generation circuits CG included in each pixel row have the same transistor configuration and accumulate the same level of stress, the drive currents generated in the multiple pixel circuits P and the sensed currents generated in the multiple sensed current generation circuits CG can be the same or very similar. Therefore, the global current value of the display area AA can be replaced with the value obtained by summing all the sensed currents generated in the multiple sensed current generation circuits CG.

[0205] The global sensing current generation circuit can sense the global current value of the display area AA by the above method. In addition, the global sensing current generation circuit can repeat the current sensing period (GC sensing timing) with a time difference. Here, the time difference can be a constant period or an irregular period, such as the turn-on time point or the turn-off time point of the display device.

[0206] On the other hand, the multiple sensed current generation circuits CG do not emit light through the sensed current data voltage because they do not include the light emitting element EL. Therefore, the current sensing period (GC sensing timing) can be performed independently of the driving of the multiple pixel circuits P.

[0207] That is, as Figure 9 shown, the current sensing period (GC sensing timing) can be continued while driving the multiple pixel circuits P with the data voltage Vdata, or the current sensing period (GC sensing timing) can be continued while not driving the multiple pixel circuits P.

[0208] Figure 10 and Figure 11 are diagrams showing the fluctuations of the accumulated global current according to the use of the display device.

[0209] Referring to Figure 10 , the global current value can generally be optimal at the time point T1, which is the initial use time point of the display device. Then, the global current can decrease as the use time of the display device accumulates.

[0210] Therefore, the global current value at the time point T2 after the accumulated use time of the display device has passed a specific time or longer can be less than the global current value at the time point T1.

[0211] Since the global sensing current generation circuit of the display device repeats the current sensing period with a time difference, as Figure 11As shown, it can output the global current sensing value GC Sen at time point T1, and can also output the global current sensing value GC Sen at time point T2. Here, the global current sensing value at time point T2 can be less than the global current sensing value at time point T1.

[0212] That is, the global current sensing value can gradually decrease as the cumulative usage time of the display device increases.

[0213] The timing controller 130 of the display device can receive the global current sensing value according to the cumulative usage time from the global sensing current generation circuit, check the global current fluctuation amount in the display area AA as follows, and compensate for the global current fluctuation amount.

[0214] Figure 12 It is a diagram showing a method for compensating for fluctuations in the global current in a display device according to an embodiment of the present disclosure.

[0215] The timing controller 130 can store the optimal global current value of the display device as a reference value.

[0216] Then, the timing controller 130 can compare the global current sensing value received from the global sensing current generation circuit with the reference value to check the global current fluctuation amount in the display area AA.

[0217] Subsequently, the timing controller 130 can compensate for the global current fluctuation amount in the display area AA by using a compensation gain corresponding to the global current fluctuation amount. As a result, regardless of the cumulative usage time of the display device, the global current in the display area AA can be maintained at the reference value.

[0218] Here, the timing controller 130 can store a Figure 13 lookup table as shown, and can use the lookup table to compensate for the global current fluctuation amount.

[0219] Specifically, the timing controller 130 can use the reference value and the global current sensing value to calculate the global current reduction ratio as the global current fluctuation amount.

[0220] Then, the timing controller 130 can use the compensation gain corresponding to the calculated global current reduction ratio to globally increase the brightness value of the image data.

[0221] Thereafter, the timing controller 130 can transmit the image data with the globally increased brightness value (i.e., the compensated image data) to the data driving circuit 110.

[0222] The data driving circuit 110 can increase the data voltage according to the compensated image data. Therefore, the global current in the display area AA can be maintained at the reference value.

[0223] For example, when the global current reduction ratio is 40%, the timing controller 130 can increase the brightness value of the image data as a whole by using a compensation gain of 1.67 (which corresponds to Figure 13 the 40% global current reduction ratio in the look-up table shown).

[0224] This can keep the global current in the display area AA at 100%.

[0225] Hereinafter, a driving method of the sense current generation circuit CG will be described.

[0226] Figure 14 is a diagram showing waveforms of a scan signal and an EM signal generated to drive the sense current generation circuit. Figures 15 to 19 is a circuit diagram showing step-by-step operations of the sense current generation circuit during a driving period of the sense current generation circuit.

[0227] Referring to Figure 14 , the driving period of the sense current generation circuit CG can be divided into an initialization period INI, a sampling period SAM, an on-bias period OBS, a hold period HOLD, and an emission period EMI.

[0228] During the initialization period INI, the voltages of the scan signals SC1, SC2, SC3(n), SC3(n + 1), and SC4 and the EM signal EM are the gate high voltage VGH. Therefore, during the initialization period INI, as Figure 15 shown, the first sense switch transistor ST1_S and the second sense switch transistor ST2_S are turned on to apply the initialization voltage Vinit to the second node n2 and the third node n3. In addition, the initialization voltage Vinit can also be applied to the first node n1 through the sense driving transistor DT_S held in the on state.

[0229] During the initialization period INI, the voltages at the second node n2, the third node n3, and the first node n1 are the initialization voltage Vinit. During the initialization period INI, the fifth sense switch transistor ST5_S and the sixth sense switch transistor ST6_S are in the off state, so that the fourth node n4 floats to maintain its previous state. Here, the first sense switch transistor ST1_S and the second sense switch transistor ST2_S can be N-channel transistors that are turned on at the gate high voltage VGH. The initialization voltage Vinit can be set to -5V, but is not limited thereto.

[0230] During the sampling period SAM, the voltage of the second scan signal SC2 is reversed from the gate high voltage VGH to the gate low voltage VGL.

[0231] During the sampling period SAM, the voltages of the first scan signal SC1 and the EM signal EM are the gate high voltage VGH, and the voltage of the fourth scan signal SC4 is the gate low voltage VGL. When the third sense switch transistor ST3_S is turned on in response to the gate low voltage VGL of the second scan signal SC2 during the sampling period SAM, as Figure 16 shown, the current sense data voltage Vdata_S is applied to the first node n1, and is also applied to the third node n3 and the second node n2 through the sense driving transistor DT_S in the on state. In this case, the voltage at the first node n1 is the current sense data voltage Vdata_S, and the voltage at each of the third node n3 and the second node n2 is Vdata_S + Vth + α obtained by adding the threshold voltage Vth of the driving element DT and the threshold voltage change value α of the oxide thin film transistor to the current sense data voltage Vdata_S. Here, the threshold voltage change value α of the oxide thin film transistor may be the amount of decrease in the threshold voltage of the oxide thin film transistor due to the stress accumulated in the oxide thin film transistor. The threshold voltage change value α may be a negative number.

[0232] Meanwhile, during the sampling period SAM, the fourth node n4 is in a floating state. Here, the third sense switch transistor ST3_S may be a P-channel transistor that is turned on at the gate low voltage VGL. The current sense data voltage Vdata_S may be set to a voltage between 0V and 4V, but is not limited thereto.

[0233] During the conduction bias period OBS, the voltages of the third n-th scan signal SC3(n) and the third (n + 1)-th scan signal SC3(n + 1) are inverted from the gate high voltage VGH to the gate low voltage VGL.

[0234] The fourth sense switch transistor ST4_S is turned on in response to the gate low voltage VGL of the third n-th scan signal SC3(n) during the conduction bias period OBS.

[0235] Then, the fifth sense switch transistor ST5_S is turned on in response to the gate low voltage VGL of the third (n + 1)-th scan signal SC3(n + 1) during the conduction bias period OBS. As a result, as Figure 17 shown, the first compensation voltage VOBS is applied to the first node n1 and the third node n3, and the second compensation voltage VAR is applied to the fourth node n4.

[0236] In this case, the voltages at the first node n1 and the third node n3 are the first compensation voltage VOBS, and the voltage at the fourth node n4 is the second compensation voltage VAR. The voltage at the second node n2 can be a voltage of Vdata_S + Vth + α by maintaining its previous state. Here, the fourth sense switch transistor ST4_S and the fifth sense switch transistor ST5_S can be P-channel transistors that conduct under a low gate voltage VGL. The first compensation voltage VOBS and the second compensation voltage VAR can each be set to -4.5V, but are not limited thereto.

[0237] During the hold period HOLD, the voltages of the first scan signal SC1 and the fourth scan signal SC4 are the low gate voltage VGL, and the voltages of the second scan signal SC2, the third (n) scan signal SC3(n), and the third (n + 1) scan signal SC3(n + 1) are the high gate voltage VGH. During the hold period HOLD, the voltage of the EM signal EM is the high gate voltage VGH. Therefore, as Figure 18 shown, the first sense switch transistor ST1_S to the seventh sense switch transistor ST7_S are all in the off state, so the first node n1 to the fourth node n4 float to maintain their previous states.

[0238] During the emission period EMI, the voltages of the first scan signal SC1, the fourth scan signal SC4, and the EM signal EM are the low gate voltage VGL, and the voltages of the second scan signal SC2, the third (n) scan signal SC3(n), and the third (n + 1) scan signal SC3(n + 1) are the high gate voltage VGH. As Figure 19 shown, the sixth sense switch transistor ST6_S and the seventh sense switch transistor ST7_S conduct in response to the low gate voltage VGL of the EM signal EM. Therefore, during the emission period EMI, a current path is formed between the high-voltage power supply ELVDD and the fourth node n4.

[0239] During the emission period EMI, a sense current generated based on the gate-source voltage Vdata_S + Vth + α of the sense driving transistor DT_S can be output to a single current sense line GCL_S. Here, the sixth sense switch transistor ST6_S and the seventh sense switch transistor ST7_S can be P-channel transistors that conduct under a low gate voltage VGL. The high-voltage power supply ELVDD can be set to 6V, but is not limited thereto.

[0240] Through the operation of the sense current generation circuit CG as described above, a sense current reflecting the stress accumulated in the plurality of sense switch transistors that are oxide thin film transistors can be generated in the sense current generation circuit CG.

[0241] As described above, in one embodiment of the present disclosure, a plurality of sense current generation circuits CG may be configured to undergo the same level of stress as the plurality of pixel circuits P, and may sum the sense currents output from the plurality of sense current generation circuits CG to derive a global current value of the display area AA.

[0242] In one embodiment of the present disclosure, the sense current generation circuit has been described as only performing the function of generating a sense current. However, the present disclosure is not limited thereto, and the sense current generation circuit may also perform other functions. That is, the sense current generation circuit may also be used for other purposes.

[0243] Figure 20 is a block diagram showing a global sense current generation circuit according to another embodiment of the present disclosure. Figure 21 and Figure 22 is a diagram exemplarily showing a sense current generation circuit according to another embodiment of the present disclosure.

[0244] Reference Figure 20 , in another embodiment of the present disclosure, the global sense current generation circuit may include a plurality of repair / current generation circuits R / CG, which also serve as repair pixel circuits for repairing defective pixel circuits DP included in the plurality of pixel circuits P. Although Figure 20 shows that the plurality of repair / current generation circuits R / CG are arranged in the form of one pixel column on one side of the display area AA, the present disclosure is not limited thereto, and the plurality of repair / current generation circuits R / CG may be arranged in the form of two or more pixel columns. Alternatively, the plurality of repair / current generation circuits R / CG may be arranged on both sides of the display area AA.

[0245] The repair / current generation circuit R / CG as a sense current generation circuit according to another embodiment of the present disclosure is composed of the same transistors as the pixel circuit, as Figure 21 and Figure 22 shown. That is, the repair / current generation circuit R / CG may include one or more oxide thin film transistors (for example, ST1 and ST2).

[0246] In addition, the light emitting element EL is not connected to the fourth node n4, and a single current sense line GCL_S is connected to the fourth node n4.

[0247] The current sense data line DL_S may be provided with a current sense data voltage Vdata_S as Figure 21 shown, or may be provided with a repair data voltage Vdata_re as Figure 22 shown.

[0248] The repair line can be provided between one or more pixel circuits P forming a pixel row and the repair / current generation circuit R / CG.

[0249] As Figure 21 shown, the normal pixel circuit (normal pixel) and the repair / current generation circuit R / CG are not electrically connected through the repair wire.

[0250] In addition, during the current sensing period of the global sense current generation circuit, the current sense data voltage Vdata_S can be provided to the repair / current generation circuit R / CG.

[0251] On the other hand, as Figure 22 shown, the defective pixel circuit (defective pixel) and the repair / current generation circuit R / CG are electrically connected through the repair wire. Here, the fourth node n4 of the repair / current generation circuit R / CG is electrically connected to the repair wire by soldering or the like, and the fourth node n4 of the defective pixel circuit (defective pixel) is electrically connected to the repair wire by soldering or the like.

[0252] The repair / current generation circuit R / CG and the single current sense line GCL_S are disconnected. In addition, in the defective pixel circuit (defective pixel), the power supply line supplying the high voltage power supply ELVDD, the line connecting the fourth node n4 to the fifth switching transistor ST5, and the line connecting the fourth node n4 to the sixth switching transistor ST6 are also disconnected.

[0253] Up to as Figure 22 shown, when the repair / current generation circuit R / CG is electrically connected to the defective pixel circuit (defective pixel), the repair data voltage Vdata_re is provided to the current sense data line DL_S. Here, the repair data voltage Vdata_re is the data voltage provided to the defective pixel circuit (defective pixel).

[0254] For example, as Figure 20 shown, when the defective pixel circuit DP is on the third row (3rd Line), the data voltage Vdata_3rd of the third row can be provided as the repair data voltage Vdata_re.

[0255] This allows the drive current corresponding to the image data (data_3rd) of the third row to flow through the repair wire to the light emitting element EL of the defective pixel circuit (defective pixel).

[0256] As described above, the current sense data voltage Vdata_S is not provided to the repair / current generation circuit R / CG electrically connected to the defective pixel circuit (defective pixel).

[0257] For example, as Figure 20 shown, when the repair / current generation circuit R / CG of the third row is connected to the defective pixel circuit DP of the third row (3rd Line), as Figure 23 shown, during the current sensing period (GC sensing timing), the current sensing data voltage Vdata_S is not supplied to the repair / current generation circuit R / CG of the third row (3rd Line). Therefore, the light-emitting element EL of the defective pixel circuit (defective pixel) electrically connected to the repair / current generation circuit R / CG of the third row (3rd Line) does not emit light through the current sensing data voltage Vdata_S.

[0258] Here, the global current sensing value GC Sen is the sum of the sensing currents output from multiple repair / current generation circuits R / CG. Therefore, even if several of the multiple repair / current generation circuits R / CG are used as repair pixel circuits, the reliability of the global current sensing value GC Sen will not be significantly reduced.

[0259] Figure 24 is a block diagram showing a global sensing current generation circuit according to another embodiment of the present disclosure. Figure 25 is a diagram exemplarily showing a sensing current generation circuit according to another embodiment of the present disclosure.

[0260] Referring to Figure 24 , in another embodiment of the present disclosure, the global sensing current generation circuit may include a dummy / current generation circuit D / CG, which also serves as a dummy pixel circuit driven during the track driving of the display device. Here, track driving refers to a driving method of reducing the deterioration and afterimage of multiple pixel circuits P by moving the entire display image according to a predetermined period.

[0261] Although Figure 24 shows that multiple dummy / current generation circuits D / CG are arranged in the form of two pixel columns on one side of the display area AA, the present disclosure is not limited thereto, and multiple dummy / current generation circuits D / CG may be arranged in the form of one or three or more pixel columns. Alternatively, multiple dummy / current generation circuits D / CG may be arranged on both sides of the display area AA.

[0262] The dummy / current generation circuit D / CG of the sensing current generation circuit according to another embodiment of the present disclosure is composed of the same transistors as the pixel circuit, as Figure 25 shown. That is, the dummy / current generation circuit D / CG may include one or more oxide thin film transistors (for example, ST1 and ST2).

[0263] In addition, the light-emitting element EL is connected to the fourth node n4, and a single current sensing line GCL_S is connected to the cathode of the light-emitting element EL.

[0264] A current sensing data voltage Vdata_S or a rail driving data voltage Vdata_O may be provided to the current sensing data line DL_S. Here, the current sensing data voltage Vdata_S is provided during a current sensing period, and the rail driving data voltage Vdata_O is provided during a rail driving period.

[0265] In still another embodiment of the present disclosure, since the dummy / current generation circuit D / CG includes the light-emitting element EL, when the current sensing data voltage Vdata_S is provided to the dummy / current generation circuit D / CG during the current sensing period, the light-emitting element EL of the dummy / current generation circuit D / CG can emit light.

[0266] Therefore, in still another embodiment of the present disclosure, the current sensing period may be a turn-on time point of the display device, a turn-off time point of the display device, an operation time point of a screen saver, etc. Additionally, in the current sensing period, an image suitable for the light-emitting patterns of a plurality of dummy / current generation circuits D / CG may be displayed in the display area AA.

[0267] The objects to be achieved by the present disclosure, the means for achieving the objects, and the effects of the above-described present disclosure do not specify the essential features of the claims. Therefore, the scope of the claims is not limited to the content disclosed in the present disclosure.

[0268] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided only for illustrative purposes and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all aspects and do not limit the present disclosure. The protection scope of the present disclosure should be construed based on the appended claims, and all technical concepts within the equivalent scope thereof should be construed as falling within the scope of the present disclosure.

[0269] [Description of Reference Numerals]

[0270] 100: Display panel 110: Data driving circuit

[0271] 112: Current summing circuit 120: Gate driving circuit

[0272] 130: Timing controller 200: Host system

Claims

1. An integrated circuit, comprising: a plurality of sense current generating circuits; as well as a single current sensing line connected to the plurality of sensing current generating circuits and through which sense currents generated by the plurality of sensing current generating circuits flow during a current sensing period, Wherein, each of the sensing current generating circuits comprises: a drive transistor configured to generate the sense current based on a gate-source voltage; a capacitor configured to charge the gate-source voltage of the drive transistor; and A plurality of switch transistors are electrically connected to the drive transistor and the capacitor and are configured to sample a threshold voltage of the drive transistor.

2. The integrated circuit of claim 1 , further comprising: A current summing circuit is configured to receive the sense currents generated by the plurality of sense current generating circuits through the single current sensing line and output a global current sensing value obtained by summing current values ​​of the sense currents during the current sensing period.

3. The integrated circuit of claim 2, further comprising: A switch circuit is configured to electrically connect the single current sensing line to the current summing circuit during the current sensing period, and to electrically connect the single current sensing line to a low voltage power line commonly connected to a plurality of pixel circuits during periods other than the current sensing period.

4. The integrated circuit of claim 3, further comprising: A current sensing data line is connected to the plurality of sensing current generating circuits and is configured to provide a current sensing data voltage to the plurality of sensing current generating circuits during the current sensing period.

5. The integrated circuit according to claim 3, wherein: The driving transistor is a transistor of the same type as a driving transistor included in a pixel circuit, and the plurality of switching transistors are transistors of the same type as a plurality of switching transistors included in the pixel circuit.

6. The integrated circuit according to claim 5, wherein: The plurality of switch transistors of the sense current generating circuit and the plurality of switch transistors of the pixel circuit are oxide transistors.

7. The integrated circuit according to claim 6, wherein: The plurality of switch transistors of the sensing current generating circuit and the plurality of switch transistors of the pixel circuit have the same number.

8. The integrated circuit according to claim 6, wherein: When the pixel circuit is driven while the low voltage power line and the single current sensing line are electrically connected through the switching circuit, at least one of positive bias stress and negative bias stress accumulates in the multiple switching transistors of the sensing current generating circuit and the multiple switching transistors of the pixel circuit.

9. The integrated circuit of claim 1, wherein: The sensing current generating circuit does not include a light emitting element.

10. The integrated circuit of claim 9, wherein: The sensing current generating circuit also functions as a repair pixel circuit for repairing a defective pixel circuit included in a display area.

11. The integrated circuit of claim 10, further comprising: a current sensing data line connected to the plurality of sensing current generating circuits and configured to provide a current sensing data voltage to the plurality of sensing current generating circuits during the current sensing period, When an Nth sensing current generating circuit among the plurality of sensing current generating circuits is used as the repair pixel circuit, the current sensing data voltage is not provided to the Nth sensing current generating circuit during the current sensing period, and N is a natural number of 1 or greater.

12. The integrated circuit of claim 2, wherein: The current summing circuit includes an analog-to-digital converter (ADC) circuit configured to sum current values ​​of the sensed current as analog values ​​during the current sensing period and output the summed value as the global current sensing value, wherein the global current sensing value is a digital value.

13. The integrated circuit of claim 1 , further comprising: A dummy / current generating circuit includes a light emitting element (EL), wherein the dummy / current generating circuit also functions as a dummy pixel circuit.

14. A display device, comprising: An integrated circuit comprising: a plurality of sensing current generating circuits disposed adjacent to one side of a display area; a single current sensing line connected to the plurality of sensing current generating circuits and through which sensing currents generated by the plurality of sensing current generating circuits flow during a current sensing period; and a current summing circuit configured to receive the sensing currents generated by the plurality of sensing current generating circuits through the single current sensing line and output a global current sensing value obtained by summing current values ​​of the sensing currents during the current sensing period; and A timing controller is configured to receive the global current sensing value output from the current summing circuit, check a global current fluctuation amount in the display area using the global current sensing value, and compensate for the global current fluctuation amount.

15. The display device according to claim 14, wherein: The timing controller compensates for the global current fluctuation amount by increasing a brightness value of image data displayed in the display area as a whole.

16. The display device according to claim 15, wherein: The timing controller increases the brightness value of the image data as a whole by using a gain value corresponding to the global current sensing value in a pre-stored lookup table.

17. The display device according to claim 14, wherein: The current summing circuit includes an analog-to-digital converter (ADC) circuit configured to sum current values ​​of the sensed current as analog values ​​during the current sensing period and output the summed value as the global current sensing value, wherein the global current sensing value is a digital value.

18. The display device according to claim 17, wherein: The analog-to-digital converter (ADC) circuit is a single-slope analog-to-digital converter (ADC) circuit.

19. The display device according to claim 14, further comprising: A plurality of pixel circuits are included in the display area, and the plurality of pixel circuits are in a driving state during the current sensing period.

20. The display device according to claim 14, wherein: The sensing current generating circuit comprises: a drive transistor configured to generate the sense current based on a gate-source voltage; a capacitor configured to charge the gate-source voltage of the drive transistor; and A plurality of switch transistors are electrically connected to the drive transistor and the capacitor and are configured to sample a threshold voltage of the drive transistor.

21. The display device according to claim 20, wherein: The driving transistor is a transistor of the same type as a driving transistor included in a pixel circuit, and the plurality of switching transistors are transistors of the same type as a plurality of switching transistors included in the pixel circuit.

22. The display device according to claim 21, wherein: The plurality of switch transistors of the sense current generating circuit and the plurality of switch transistors of the pixel circuit are oxide transistors.

23. The display device according to claim 22, wherein: The plurality of switch transistors of the sensing current generating circuit and the plurality of switch transistors of the pixel circuit have the same number.

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