Level shifter and display device including same

Abstract

Disclosed are a level shifter and a display device including the same. The display apparatus includes: a display panel configured to display an image; a level shifter configured to extract and output data from a data map of the memory based on an enable signal and divide a serial output signal output to the level shifter into parallel output signals to output a periodic signal; and a shift register configured to output a gate signal to be applied to the display panel based on the periodic signal output from the level shifter.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2023-0197308, filed on December 29, 2023, which is incorporated herein by reference in its entirety as if fully set forth herein. Technical Field

[0002] The present invention relates to a level shifter and a display device including the level shifter. Background Art

[0003] With the development of information technology, the market for display devices, which are connection media between users and information, is expanding day by day. Accordingly, the use of display devices such as light-emitting display devices, quantum dot display (QDD) devices, and liquid crystal display (LCD) devices is increasing.

[0004] The above-described display device includes: a display panel including a plurality of sub-pixels; a driver that outputs a driving signal for driving the display panel; and a power supply that generates power to be provided to the display panel or the driver.

[0005] In these display devices, when a driving signal (e.g., a scan signal and a data signal) is provided to each sub-pixel provided in the display panel, the selected sub-pixel may transmit light or may emit light itself, thereby displaying an image. Summary of the Invention

[0006] The present invention can generate a clock signal for simplifying a control signal of a level shifter based on a data map (sequence-based logical values) stored in a memory, and can also reduce the number of input pins. In addition, the present invention can monitor a driving state of the level shifter based on communication between a timing controller and the level shifter, and can easily change and control output conditions of the level shifter to enhance the general purpose of the device. Further, the present invention can store a marker for addressing a specific clock signal, can implement a repetitive sequence by using an enable signal and a drive selection signal, and can specify an output timing.

[0007] To achieve these objects and other advantages, according to an aspect of the present invention, as embodied and broadly described herein, a display device includes: a display panel configured to display an image; a level shifter configured to extract and output data from a data map of a memory based on an enable signal and to divide a serial output signal output to the level shifter into parallel output signals to output a periodic signal; and a shift register configured to output a gate signal to be applied to the display panel based on the periodic signal output from the level shifter.

[0008] The level shifter may include: a controller configured to generate a count signal for extracting data from a data map of the memory based on the enable signal; and a bit splitting circuit configured to split the serial output signal into the parallel output signal.

[0009] The data map may include data whose logical values are sequentially stored, where the logical values are output through channels of each address.

[0010] As long as the enable signal is applied as a first logic, the level shifter may shift the address value of the data map, and as long as the enable signal is applied as a second logic opposite to the first logic, the level shifter may extract the data included in the address value of the data map as an output signal to output the output signal as the periodic signal.

[0011] The level shifter may include a selector configured to generate a selection signal for selecting an operation condition of the controller based on the enable signal and a drive selection signal.

[0012] The controller may include: a plurality of flags configured to store address values distinguishable from each other; a counter configured to generate a count signal based on the enable signal; and a demultiplexer configured to: based on the selection signal, output an enable control signal for controlling an enable switch so that the enable signal is applied to the counter, and output a flag control signal for turning on one of a plurality of flag switches so that the address value included in one of the plurality of flags is applied to an address signal input terminal of the counter.

[0013] The enable signal and the drive selection signal may be output from a timing controller connected to the level shifter, and input or output conditions of the level shifter may be changed based on bidirectional data communication with the timing controller.

[0014] As long as the enable signal is applied as a first logic, the level shifter may shift the address value of the data map, and as long as the enable signal is applied as a second logic opposite to the first logic, the level shifter may extract the data included in the address value of the data map as an output signal to output the output signal as the periodic signal, and when the enable signal is applied as the first logic, the flag control signal may be applied as a pulse type.

[0015] In another aspect of the present invention, a level shifter includes: a memory including a data map in which logical values are stored in sequence, and the logical values are output through channels of each address; a controller configured to generate a count signal based on an enable signal and extract data from the data map of the memory; and a bit splitting circuit configured to split a serial output signal output from the memory into a parallel output signal.

[0016] As long as the enable signal is applied as a first logic, the controller can shift the address value of the data map, and as long as the enable signal is applied as a second logic opposite to the first logic, the controller can extract the data included in the address value of the data map as an output signal to output the output signal as a periodic signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings that provide a further understanding of the present invention and are incorporated into and constitute a part of this application illustrate embodiments of the present invention and, together with the description, are used to explain the principles of the present invention. In the drawings:

[0018] Figure 1 is a block diagram schematically illustrating a light-emitting display device, Figure 2 is schematically illustrating Figure 1 a block diagram of the sub-pixel shown;

[0019] Figure 3 and 4 is a diagram for describing the structure of a gate driver of a gate-in-panel (GIP) type;

[0020] Figure 5 is a diagram illustrating a modular light-emitting display device according to a first embodiment, Figure 6 is a block diagram illustrating a level shifter according to a first embodiment, Figure 7 is illustrating that it is possible to be based on Figure 6 a block diagram of a shift register driven by the level shifter of, Figure 8 is illustrating that it is possible to be based on Figure 7 a block diagram of a sub-pixel driven by the shift register of;

[0021] Figure 9 and 10 is a diagram more detailedly illustrating elements included in the level shifter according to a first embodiment;

[0022] Figure 11 is a diagram illustrating a process of outputting a first clock signal from the level shifter; Figure 12 is a diagram illustrating a process of outputting a second clock signal from the level shifter;

[0023] Figure 13FIG. is a more detailed diagram illustrating elements included in a controller according to a modified embodiment of the first embodiment;

[0024] Figure 14 FIG. is a block diagram illustrating a level shifter according to the second embodiment, Figure 15 FIG. is a block diagram illustrating a shift register that can be driven based on a Figure 14 level shifter, Figure 16 FIG. is a block diagram illustrating a sub-pixel that can be driven based on a Figure 15 shift register;

[0025] Figure 17 and 18 FIG. is a more detailed diagram illustrating elements included in a level shifter according to the second embodiment;

[0026] Figure 19 FIG. is a diagram illustrating a process of outputting a first clock signal from a level shifter; Figure 20 FIG. is a diagram illustrating a process of outputting a second clock signal from a level shifter;

[0027] Figure 21 FIG. is a more detailed diagram illustrating elements included in a controller according to a modified embodiment of the second embodiment. DETAILED DESCRIPTION

[0028] Hereinafter, the present invention will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present invention are shown. However, the present invention can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0029] The display device according to the present invention can be applied to a television (TV), a video player, a personal computer (PC), a home theater, a vehicle electronic device, and a smart phone, but is not limited thereto. The display device according to the present invention can be implemented as a light-emitting display device, a quantum dot display (QDD) device, or a liquid crystal display (LCD) device. Hereinafter, for ease of description, a light-emitting display device that emits light by using an inorganic light-emitting diode or an organic light-emitting diode will be described as an example.

[0030] In addition, the transistors described below can be implemented using n-type transistors, p-type transistors, or a combination of n-type transistors and p-type transistors. A transistor can be a three-electrode element including a gate, a source, and a drain. The source can be an electrode that provides carriers to the transistor. In a transistor, carriers can flow starting from the source. The drain can be an electrode through which carriers flow out of the transistor. That is, in a transistor, carriers flow from the source to the drain.

[0031] In a p-type transistor, since the carriers are holes, the source voltage can be higher than the drain voltage, causing the holes to flow from the source to the drain. In a p-type transistor, since the holes flow from the source to the drain, the current can flow from the source to the drain. On the other hand, in an n-type transistor, since the carriers are electrons, the source electrode can be lower than the drain voltage, so that the electrons flow from the source to the drain. In an n-type transistor, since the electrons flow from the source to the drain, the current can flow from the drain to the source. However, the source and drain of a transistor can be switched with each other based on the applied voltage. Based on the above, in the following description, one of the source and the drain will be described as the first electrode, and the other of the source and the drain will be described as the second electrode.

[0032] Figure 1 is a block diagram schematically illustrating a light-emitting display device, Figure 2 is a schematic illustration Figure 1 of the sub-pixel shown.

[0033] As Figure 1 and 2 shown, a light-emitting display device according to an embodiment of the present invention may include: a video providing unit 110; a timing controller 120; a gate driver (gate driving circuit) 130; a data driver (data driving circuit) 140; a display panel 150; and a power supply 180.

[0034] The video providing unit 110 (set or host system) may output a video data signal provided from the outside or an image data signal stored in its internal memory. The video providing unit 110 may provide a data signal and various driving signals to the timing controller 120.

[0035] The timing controller 120 may output a gate timing control signal GDC for controlling the operation timing of the gate driver 130, a data timing control signal DDC for controlling the operation timing of the data driver 140, and various synchronization signals. The timing controller 120 may provide the data signal DATA provided from the video providing unit 110 and the data timing control signal DDC to the data driver 140. The timing controller 120 may be implemented as an integrated circuit (IC) type and may be mounted on a printed circuit board (PCB), but is not limited thereto.

[0036] The gate driver 130 may output a gate signal (or gate voltage) in response to the gate timing control signal GDC provided from the timing controller 120. The gate driver 130 may provide the gate signal to a plurality of sub-pixels included in the display panel 150 via a plurality of gate lines GL1 to GLm. The gate driver 130 may be implemented as an IC type, or may be directly provided on the display panel 150 in a gate-in-panel (GIP) type, but is not limited thereto.

[0037] In response to a data timing control signal DDC provided from a timing controller 120, a data driver 140 may sample and latch a data signal DATA, convert a digital data signal into an analog data voltage based on a gamma reference voltage, and output the analog data voltage. The data driver 140 may provide data voltages to sub-pixels of a display panel 150 via a plurality of data lines DL1 to DLn, respectively. The data driver 140 may be implemented as an IC type or may be mounted on the display panel 150 or a PCB, but is not limited thereto.

[0038] A power supply 180 may generate a high-level voltage and a low-level voltage based on an external input voltage provided from the outside, and may output the high-level voltage and the low-level voltage via a high-level power supply line EVDD and a low-level power supply line EVSS. In addition to the high-level voltage and the low-level voltage, the power supply 180 may also generate and output a voltage required to drive the gate driver 130 (e.g., a gate high voltage and a gate low voltage) or a voltage required to drive the data driver 140.

[0039] The display panel 150 may display an image (video) based on a driving voltage including a high-level voltage and a low-level voltage and a driving signal including a gate signal and a data voltage. Each of the sub-pixels of the display panel 150 may emit light by itself. The display panel 150 may be manufactured based on a substrate such as glass, silicon, or polyimide having rigidity or flexibility. In addition, the sub-pixels emitting light may include pixels having red, green, and blue, or may include pixels having red, green, blue, and white.

[0040] For example, one sub-pixel SP may be connected to a first data line DL1, a first gate line GL1, a high-level power supply line EVDD, and a low-level power supply line EVSS, and may include a switching transistor, a driving transistor, a capacitor, and an organic light-emitting diode. The sub-pixel SP used in a light-emitting display device may emit light by itself and may be relatively complex in circuit configuration. In addition, in addition to the light-emitting organic light-emitting diode, a compensation circuit may be implemented in various ways, where the compensation circuit is for compensating for degradation in the driving transistor that provides a driving current required to drive the organic light-emitting diode. Therefore, the sub-pixel SP is simply illustrated in the form of a block.

[0041] In the above description, each of the timing controller 120, the gate driver 130, and the data driver 140 is described as a separate element. However, based on the implementation type of the light-emitting display device, one or more of the timing controller 120, the gate driver 130, and the data driver 140 may be integrated into one IC.

[0042] Figure 3 and 4 is a diagram for describing the configuration of a gate driver of the GIP type.

[0043] As shown Figure 3 in FIG. 1, the GIP type gate driver 130 may include a shift register 131 and a level shifter 135. The level shifter 135 may generate clock signals Clks and a start signal Vst based on signals and voltages output from a timing controller 120 and a power supply 180.

[0044] The clock signals Clks may be output via clock signal lines, and the start signal Vst may be output via a start signal line. The shift register 131 may operate based on the clock signals Clks and the start signal Vst, and may output gate signals Gout[1] to Gout[m].

[0045] As shown Figure 4 in FIG. 2, in the GIP type gate driver, a first shift register 131a and a second shift register 131b that output gate signals may be disposed in a left non-display area NA and a right non-display area NA with respect to a display area AA, where the display area AA uses a display panel 150 to display an image. The first shift register 131a and the second shift register 131b may be formed as a thin film type in the display panel 150 based on the GIP type.

[0046] Figure 5 FIG. 3 is a diagram illustrating a modular light-emitting display device according to a first embodiment, Figure 6 FIG. 4 is a block diagram illustrating a level shifter according to a first embodiment, Figure 7 FIG. 5 is a block diagram illustrating a shift register capable of being driven based on the Figure 6 level shifter, Figure 8 FIG. 6 is a block diagram illustrating a sub-pixel capable of being driven based on the Figure 7 shift register.

[0047] As shown Figure 5 in FIG. 7, the light-emitting display device according to the first embodiment may be modularized based on a control board 126, a first connector 121, a source plate 148, second connectors 141a to 141d, and a display panel 150. Figure 5 This is only for helping to understand the modular light-emitting display device, and the embodiments are not limited thereto.

[0048] The control board 126 may include a timing controller 120 and a power supply 180. The first connector 121 may electrically connect the control board 126 to the source plate 148. The source plate 148 may include a level shifter 135. The second connectors 141a to 141d may electrically connect the source plate 148 to the display panel 150. The second connectors 141a to 141d may include data drivers 140a to 140d.

[0049] As shown Figure 6As shown, the level shifter 135 according to the first embodiment can operate based on the enable signal EN output from the timing controller 120, and can output a periodic signal through the first to Nth output channels CH1 to CHn. Hereinafter, for ease of description, an example in which the level shifter 135 outputs a clock signal as the periodic signal will be described. In addition, for better understanding, the data map of the data written in the Figure 6 memory MEM may be described.

[0050] The level shifter 135 may include a controller CON, a memory MEM, a bit split circuit BSC, and an output circuit LSC to output a clock signal based on the enable signal EN.

[0051] The memory MEM may include data in which its clock signal is stored in a sequence status, where the clock signal is applied to the shift register. For example, the memory MEM may include a data map in which logical values H or L distinguished and output for each channel CH0 to CH7 for each address 0x00 to 0xFF are sequentially stored.

[0052] The controller CON can operate based on the enable signal EN applied via the enable signal input terminal ENA, and can extract and output the data of the data map from the memory MEM based on the signal output via the signal output terminal OUT. The bit split circuit BSC can sort the serial output signal output from the memory MEM to split it into a parallel output signal. The output circuit LSC may include a circuit LS that shifts up the level of the output signal output from the bit split circuit BSC and outputs it. As long as the enable signal EN is applied as the first logic, the controller CON can shift the address value of the data map, and as long as the enable signal EN is applied as the second logic opposite to the first logic, the controller CON can extract the data included in the address value of the data map as an output signal and output the output signal as a periodic signal.

[0053] As Figures 6 to 8 shown, the shift register 131a can operate based on the clock signal output from the level shifter 135. The clock signal output from the level shifter 135 can be applied to the shift register 131a via the clock signal lines CLKS1 and CLKS2. Each of the clock signal lines CLKS1 and CLKS2 includes two or more clock signal lines.

[0054] The shift register 131a may include: first scan signal generators SCG1[1] to SCG1[m] that output first scan signals Gout1[1] to Gout1[m]; and second scan signal generators SCG2[1] to SCG2[m] that output second scan signals Gout2[1] to Gout2[m]. The first scan signal generators SCG1[1] to SCG1[m] and the second scan signal generators SCG2[1] to SCG2[m] may be separately provided for each stage (e.g., the first to the M-th stage) STG[1] to STG[m].

[0055] The first scan signal generator SCG1[1] and the second scan signal generator SCG2[1] provided in the first stage STG1 may respectively output a first scan signal Gout1[1] and a second scan signal Gout2[1] for driving the first gate line GL1. The 1M scan signal generator SCG1[m] and the 2M scan signal generator SCG2[m] provided in the M-th stage STGm may respectively output a 1M scan signal Gout1[m] and a 2M scan signal Gout2[m] for driving the M-th gate line GLm.

[0056] Each of the first scan signal generators SCG1[1] to SCG1[m] and the second scan signal generators SCG2[1] to SCG2[m] may operate sequentially based on a clock signal output from the level shifter 135. However, this may be only one embodiment, and the first scan signal generators SCG1[1] to SCG1[m] and the second scan signal generators SCG2[1] to SCG2[m] may operate sequentially, in a reverse order, or randomly.

[0057] The sub-pixel SP may be connected to a first gate line GL1 including a first scan line GL1a and a second scan line GL1b, a first data line DL1, a high-level power supply line EVDD, and a low-level power supply line EVSS. The sub-pixel SP may store a data voltage in response to a first scan signal Gout1[1] applied via the first scan line GL1a, and perform a sensing operation or a light-emitting operation in response to a second scan signal Gout2[1] applied via the second scan line GL1b. However, this may be only one embodiment, and the embodiments are not limited thereto.

[0058] In addition, the shift register 131a may further include a virtual signal generator that outputs a virtual gate signal to the previous end with respect to the first scan signal generators SCG1[1] and SCG2[1] and to the next end with respect to the 1M scan signal generators SCG1[m] and the 2M scan signal generators SCG2[m], but its illustration may be omitted.

[0059] In addition, in Figure 6 an example is shown and described in which an n-bit signal is output from the controller CON and the memory MEM. However, hereinafter, an example will be described in which eight clock signals can be output based on an 8-bit output signal.

[0060] Figure 9 and 10 are diagrams that more specifically illustrate the elements included in the level shifter according to the first embodiment.

[0061] As Figure 9 shown, according to the first embodiment, the controller CON included in the level shifter may include a clock generator CLKG and an up-counter Up-CNT.

[0062] The clock generator CLKG may generate a clock to be applied to the up-counter Up-CNT. The up-counter Up-CNT may include an enable signal input terminal ENA, a clock input terminal CL1, a count signal output terminal OUT, an overflow signal output terminal OVR, and a reset input terminal RST. The up-counter Up-CNT may be implemented as an 8-bit up-counter.

[0063] The up-counter Up-CNT may generate a count signal that increases based on the clock output from the clock generator CLKG. The up-counter Up-CNT may activate or deactivate the counting operation based on the enable signal EN applied to the enable signal input terminal ENA. For example, the up-counter Up-CNT may activate the counting operation when the enable signal EN corresponding to a low logic is applied.

[0064] For example, the up-counter Up-CNT may include a maximum number register corresponding to 0x09 or 0x29. The up-counter Up-CNT may start counting from 0x00, and when the counted number is greater than the number corresponding to the maximum count of 0x09 or 0x29, the up-counter Up-CNT may output an overflow signal via the overflow signal output terminal OVR. When an overflow signal is input via the reset input terminal RST, the up-counter Up-CNT may reset the count signal to return it to 0x00.

[0065] When a count signal is output from the up-counter Up-CNT of the controller CON, the memory MEM may extract and output data corresponding thereto from the data map. The memory MEM may include an input terminal ADD to which the count signal is applied and an output terminal DO that outputs an output signal SDAT. The process of outputting a clock signal from the level shifter will be described hereinafter with reference to Figure 11 and 12

[0066] As Figure 10 shown, according to the first embodiment, the bit-splitting circuit BSC included in the level shifter may include a shift register SRC and a buffer BUF.

[0067] The shift register SRC may split the serial output signal SDAT output from the memory MEM into a parallel output signal based on a bit-splitting operation. The buffer BUF may transmit the output signal output from the shift register SRC to the output circuit LSC. The output circuit LSC may up-shift the level of the output signal output via the buffer BUF and output it.

[0068] In addition, Figure 10 the state is shown when the shift register SRC outputs a high logic corresponding to 1 via the first channel CH1 and low logics corresponding to 0 via the second to eighth channels CH2 to CH8.

[0069] Hereinafter, the process of outputting a clock signal from the level shifter will be additionally described under the condition that the clock signals applied to the first scan signal generators SCG1[1] to SCG1[m] and the second scan signal generators SCG2[1] to SCG2[m] shown are limited to 5 channels. Figure 7 Figure 7

[0070] Figure 11 is a diagram illustrating the process of outputting the first clock signal from the level shifter; Figure 12 is a diagram illustrating the process of outputting the second clock signal from the level shifter.

[0071] As Figure 9 、 10 and 11 shown, in the up-counter Up-CNT of the level shifter, the maximum number register (Max number register) may be selected as the first address value "0x00 to 0x09" to output the first clock signal CLKS1 to be applied to the first scan signal generators SCG1[1] to SCG1[m] shown. Figure 7 Figure 7

[0072] First, when a first enable signal EN1 having a low logic is applied to the level shifter, address 0x00 may be selected in the data map of the memory MEM. At this time, since 11111XX is recorded in the corresponding address, a clock signal having a high logic H may be output to the first to fifth channels CH1 to CH5 of the level shifter. Here, XX may indicate no output (unused output) to provide an example of using only a total of 5 channels.

[0073] Subsequently, when a first enable signal EN1 with low logic is applied after a high logic is applied to the level shifter, address 0x01 can be selected in the data map of the memory MEM. At this time, since 01111XX is recorded in the corresponding address, a clock signal with low logic L can be output to the first channel CH1, and a clock signal with high logic H can be output to the second to fifth channels CH2 to CH5.

[0074] The level shifter can operate in this order. Then, after address 0x09 is selected in the data map of the memory MEM, an overflow signal can be generated. The level shifter can reset the count value to address 0x00 based on the overflow signal. Therefore, the level shifter can operate based on the above process and can repeatedly output the clock signals included in addresses 0x00 to 0x09. For example, the first clock signal output via the first channel CH1 can be applied via the first clock signal line, and the second clock signal output via the second channel CH2 can be applied via the second clock signal line. In this way, the clock signals output via the third to fifth channels CH3 to CH5 can be output via the third to fifth clock signal lines respectively.

[0075] As Figure 9 、 10 and shown in 12, in the up-counter Up-CNT of the level shifter, the maximum number register (Max number register) can be selected as the second address value "0x20 to 0x29" to output the second clock signal CLKS2 to be applied to Figure 7 the second scan signal generators SCG2[1] to SCG2[m] shown in.

[0076] First, when a second enable signal EN2 with low logic is applied to the level shifter, address 0x20 can be selected in the data map of the memory MEM. At this time, since 01110XX is recorded in the corresponding address, a clock signal with high logic H can be output to the second to fourth channels CH2 to CH4 of the level shifter, and a clock signal with low logic L can be output to the first channel CH1 and the fifth channel CH5 of the level shifter. Here, XX can represent no output (not using the output) to provide an example of using only a total of 5 channels.

[0077] Subsequently, when a second enable signal EN2 with low logic is applied after a high logic is applied to the level shifter, address 0x21 can be selected in the data map of the memory MEM. At this time, since 01111XX is recorded in the corresponding address, a clock signal with low logic L can be output to the first channel CH1, and a clock signal with high logic H can be output to the second to fifth channels CH2 to CH5.

[0078] The level shifter can operate in this order. Then, after selecting the address 0x29 in the data map of the memory MEM, an overflow signal can be generated. The level shifter can reset the count value to the address 0x20 based on the overflow signal. Therefore, the level shifter can operate based on the above process and can repeatedly output the clock signals included from the address 0x20 to the address 0x29.

[0079] Figure 13 FIG. is a more detailed diagram illustrating the elements included in the controller of a modified embodiment according to the first embodiment.

[0080] As Figure 13 shown, according to a modified embodiment of the first embodiment, the controller CON of the level shifter may further include an interface INF and a register REG. The controller CON according to the modified embodiment of the first embodiment can perform bidirectional data communication with the timing controller based on the interface INF. For this purpose, the communication data DAT and the communication clock CLK can be input to the interface INF. The register REG can store the current states of the devices (such as an adder counter and a memory) included in the level shifter.

[0081] Therefore, according to a modified embodiment of the first embodiment, the level shifter can monitor the driving state based on the mutual communication with the timing controller, and in addition, the output conditions can be changed. That is, the input / output of the level shifter can be controlled by the timing controller.

[0082] Figure 14 FIG. is a block diagram illustrating a level shifter according to the second embodiment. Figure 15 FIG. is a diagram illustrating Figure 14 a shift register capable of driving based on the level shifter. Figure 16 FIG. is a diagram illustrating Figure 15 a sub-pixel capable of driving based on the shift register.

[0083] As Figure 14 shown, the level shifter 135 according to the second embodiment can operate based on the enable signals EN1 to EN3 and the drive selection signals OPR1 to OPR3 output from the timing controller 120, and can output periodic signals via the output channels CH1 to CH8, CH1' to CH8', and CH1" to CH8", respectively. Hereinafter, for ease of description, an example in which the level shifter 135 outputs a clock signal as a periodic signal will be described. In addition, for better understanding, the data map written in the first memory MEM1 in Figure 14 will be described.

[0084] The level shifter 135 may include first to third clock signal generators 135a to 135c. The first to third clock signal generators 135a to 135c may respectively include selectors SELC1 to SELC3, controllers CON1 to CON3, memories MEM1 to MEM3, bit split circuits BSC1 to BSC3, and output circuits LSC1 to LSC3 to output clock signals based on enable signals EN1 to EN3 and drive select signals OPR1 to OPR3.

[0085] The selectors SELC1 to SELC3 may generate selection signals Sel1 to Sel3 for selecting the operating conditions of the controllers CON1 to CON3 based on the enable signals EN1 to EN3 and the drive select signals OPR1 to OPR3.

[0086] The memories MEM1 to MEM3 may include data in which their clock signals are stored in a sequential state, where the clock signals are applied to the shift register. For example, the memories MEM1 to MEM3 may include data maps in which their logical values H or L are sequentially stored, where the logical values H or L are distinguished and output for each channel CH0 to CH7 of each address 0x00 to 0xFF.

[0087] The controllers CON1 to CON3 may operate based on the enable signals EN1 to EN3 and may extract and output the data of the data maps from the memories MEM1 to MEM3. The bit split circuits BSC1 to BSC3 may sort the serial output signals output from the memories MEM1 to MEM3 to split them into parallel output signals. The output circuits LSC1 to LSC3 may shift up the levels of the output signals output from the bit split circuits BSC1 to BSC3 and output them.

[0088] As Figures 14 to 16 shown, the shift register 131a may operate based on the clock signals output from the level shifter 135. The clock signals output from the level shifter 135 may be applied to the shift register 131a via clock signal lines CLKS1 to CLKS3.

[0089] The shift register 131a may include: first scan signal generators SCG1[1] to SCG1[m] that output first scan signals Gout1[1] to Gout1[m]; second scan signal generators SCG2[1] to SCG2[m] that output second scan signals Gout2[1] to Gout2[m]; and third scan signal generators EMG[1] to EMG[m] that output third scan signals Em[1] to Em[m]. Accordingly, it may be defined that: the first memory MEM1 includes a first scan signal generation data map MEM1_Scan1, the second memory MEM2 includes a second scan signal generation data map MEM2_Scan2, and the third memory MEM3 includes a third scan signal generation data map MEM3_Em.

[0090] The first scan signal generators SCG1[1] to SCG1[m], the second scan signal generators SCG2[1] to SCG2[m], and the third scan signal generators EMG[1] to EMG[m] may be separately provided for each stage STG[1] to STG[m]. The first scan signal generator SCG1[1], the second scan signal generator SCG2[1], and the third scan signal generator EMG[1] provided in the first stage STG1 may output the first scan signal Gout1[1], the second scan signal Gout2[1], and the third scan signal Em[1] for driving the first gate line GL1, respectively. The 1M scan signal generator SCG1[m], the 2M scan signal generator SCG2[m], and the 3M scan signal generator EMG[m] provided in the Mth stage STGm may output the 1M scan signal Gout1[m], the 2M scan signal Gout2[m], and the 3M scan signal EM[m] for driving the Mth gate line GLm, respectively.

[0091] Each of the first scan signal generators SCG1[1] to SCG1[m], the second scan signal generators SCG2[1] to SCG2[m], and the third scan signal generators EMG[1] to EMG[m] may operate sequentially based on a clock signal output from the level shifter 135. However, this may be only one embodiment, and the first scan signal generators SCG1[1] to SCG1[m], the second scan signal generators SCG2[1] to SCG2[m], and the third scan signal generators EMG[1] to EMG[m] may operate sequentially, in a reverse order, or randomly.

[0092] The sub-pixel SP can be connected to a first gate line GL1 including a first scan line GL1a, a second scan line GL1b, and a third scan line GLc, a first data line DL1, a high-level power supply line EVDD, and a low-level power supply line EVSS. The sub-pixel SP can store a data voltage in response to a first scan signal Gout1[1] applied via the first scan line GL1a, can perform a sensing operation (or a compensation operation) in response to a second scan signal Gout2[1] applied via the second scan line GL1b, and can perform a light-emitting operation in response to a third scan signal Em[1]. However, this can be only one embodiment, and the embodiments are not limited thereto.

[0093] In addition, the shift register 131a can further include a virtual signal generator that outputs a virtual gate signal at the front end with respect to the first scan signal generator SCG1[1], the second scan signal generator SCG2[1], and the third scan signal generator EMG[1], and at the rear end with respect to the 1Mth scan signal generator SCG1[m], the 2Mth scan signal generator SCG2[m], and the 3Mth scan signal generator EMG[m], but its illustration can be omitted.

[0094] In addition, in Figure 14 , an example in which an n-bit signal is output from the controllers CON1 to CON3 and the memories MEM1 to MEM3 is shown and described. However, hereinafter, an example in which eight clock signals can be output based on an 8-bit output signal will be described as an example.

[0095] In addition, the first to third clock signal generators 135a to 135c included in the level shifter 135 can include the same elements. Therefore, hereinafter, the first clock signal generator 135a will be described as an example.

[0096] Figure 17 and 18 are diagrams that more detailedly illustrate the elements included in the level shifter according to the second embodiment.

[0097] As Figure 17 shown, according to the second embodiment, the first selector SELC1 included in the level shifter can generate a first selection signal Sel1 for selecting an operation condition of the first controller CON1 based on a first enable signal EN1 and a first drive selection signal OPR1.

[0098] The first selector SELC1 can be implemented as an a-bit edge counter. For example, a can be an integer of 3 or greater. In this case, the first selector SELC1 can be implemented as a 3-bit edge counter. The first selector SELC1 can include an enable signal input terminal ENA, a reset input terminal RST, a clock input terminal CL1, a drive selection signal input terminal OPI, and a selection signal output terminal SEL.

[0099] The first selector SELC1 can generate a count signal that increases based on the clock output from the clock generator CLKG. When the enable signal EN corresponding to low logic is applied to the first selector SELC1, the first selector SELC1 can start the counting operation. The first selector SELC1 can start or stop the counting operation based on the enable signal EN applied to the enable signal input terminal ENA. The first selector SELC1 can reset the counting operation based on the enable signal EN applied to the reset input terminal RST. The first selector SELC1 can change the bit value of the first selection signal Sel1 to be output via the selection signal output terminal SEL based on the first drive selection signal OPR1 applied to the drive selection signal input terminal OPI.

[0100] According to the second embodiment, the first controller CON1 included in the level shifter can include a clock generator CLKG, an up-counter Up-CNT, an enable switch ES, a demultiplexer De-MUX, markers MAK1 to MAK4, and marker switches MS1 to MS4.

[0101] The clock generator CLKG can generate a clock to be applied to the first selector SELC1 and the up-counter Up-CNT. The up-counter Up-CNT can include an enable signal input terminal ENA, a clock input terminal CLI, a count signal output terminal OUT, and an address signal input terminal IN. The up-counter Up-CNT can be implemented as an 8-bit up-counter.

[0102] The enable switch ES can be turned on or off based on the enable control signal Ec output from the demultiplexer De-MUX. The up-counter Up-CNT can generate a count signal that increases based on the clock output from the clock generator CLKG. The up-counter Up-CNT can activate or deactivate the counting operation based on the enable signal EN applied to the enable signal input terminal ENA. When the enable signal EN corresponding to low logic is applied to the enable switch ES, the up-counter Up-CNT can activate the counting operation. That is, the up-counter Up-CNT can start counting simultaneously with the first selector SELC1, or may not start.

[0103] When an enable signal EN corresponding to a high logic is applied, the demultiplexer De-MUX can output an enable control signal Ec and marker control signals Mc1 to Mc4 based on the bit values of the first selection signal Sel1. When the enable signal EN is applied as a first logic, the marker control signals can be applied as a pulse type.

[0104] The markers MAK1 to MAK4 can respectively include a first address value (value: 0x00), a second address value (value: 0x09), a third address value (value: 0x20), and a fourth address value (value: 0x29). One of the address values can be selected through marker switches MS1 to MS4 turned on based on the marker control signals Mc1 to Mc4, and the markers MAK1 to MAK4 can apply the selected address value to the address signal input terminal IN of the up-counter Up-CNT.

[0105] For example, when the enable switch ES is turned on along with the output of the enable control signal Ec, the up-counter Up-CNT can activate a counting operation. In addition, when the first marker switch MS1 is turned on along with the output of the first marker control signal Mc1, the up-counter Up-CNT can start counting from the first address value (value: 0x00) stored in the first marker MAK1. On the other hand, when the second marker switch MS2 is turned on along with the output of the second marker control signal Mc2, the up-counter Up-CNT can start counting from the second address value (value: 0x09) stored in the second marker MAK2. On the other hand, when the third marker switch MS3 is turned on along with the output of the third marker control signal Mc3, the up-counter Up-CNT can start counting from the third address value (value: 0x20) stored in the third marker MAK3. On the other hand, when the fourth marker switch MS4 is turned on along with the output of the fourth marker control signal Mc4, the up-counter Up-CNT can start counting from the fourth address value (value: 0x29) stored in the fourth marker MAK4.

[0106] When a first count signal is output from the up-counter Up-CNT of the first controller CON1, the first memory MEM1 can extract and output corresponding data from the data map. The first memory MEM1 can include an input terminal ADD to which the first count signal is applied and an output terminal DO that outputs a first output signal SDAT1. The following will be described with reference to Figure 19 and 20 the process of outputting a clock signal from the level shifter.

[0107] As Figure 18 shown, the first bit splitting circuit BSC1 according to the second embodiment can include a shift register SRC and a buffer BUF.

[0108] The shift register SRC can divide the serial output signal SDAT1 output from the first memory MEM1 into a parallel first output signal based on a bit-splitting operation. The buffer BUF can transmit the first output signal output from the shift register SRC to the first output circuit LSC1. The first output circuit LSC1 can include a circuit LS that raises the level of the first output signal output via the buffer BUF and outputs it.

[0109] In addition, Figure 18 The state is shown when the shift register SRC outputs a high logic corresponding to 1 via the first channel CH1 and low logics corresponding to 0 via the second to eighth channels CH2 to CH8.

[0110] Hereinafter, the process of outputting a clock signal from the level shifter will be additionally described under the condition that the clock signals applied to the Figure 15 shown first scan signal generators SCG1[1] to SCG1[m] and second scan signal generators SCG2[1] to SCG2[m] are limited to 5 channels.

[0111] Figure 19 is a diagram illustrating the process of outputting the first clock signal from the level shifter; Figure 20 is a diagram illustrating the process of outputting the second clock signal from the level shifter.

[0112] As Figure 17 , 18 and 19 show, in the up-counter Up-CNT of the level shifter, the address value for outputting the first clock signal CLKS1 to be applied to the Figure 15 shown first scan signal generators SCG1[1] to SCG1[m] can be preferentially selected.

[0113] First, when the first marker signal Mak1 corresponding to two pulses is applied to the first drive selection signal OPR1 in the state of applying the first enable signal EN1 having a high logic, the level shifter can be set to use the first address value "0x00 to 0x09" stored in the first marker MAK1.

[0114] Subsequently, when the first enable signal EN1 having a low logic is applied to the level shifter, the address 0x00 specified by the first address value can be selected in the data map of the first memory MEM1. At this time, since 11111XX is recorded in the corresponding address, a clock signal having a high logic H can be output to the first to fifth channels CH1 to CH5 of the level shifter. Here, XX can indicate no output (not using the output) to provide an example of using only a total of 5 channels.

[0115] Subsequently, when the up-count signal Upc corresponding to a pulse is applied to the first drive selection signal OPR1 while the first enable signal EN1 with high logic is applied to the level shifter, the address 0x01 after 0x00 can be selected in the data map of the first memory MEM1. At this time, since 01111XX is recorded in the corresponding address, the clock signal with low logic L can be output to the first channel CH1, and the clock signals with high logic H can be output to the second to fifth channels CH2 to CH5.

[0116] The level shifter can operate in this order. Then, after the address 0x09 is selected in the data map of the first memory MEM1, the first marker signal Mak1 corresponding to two pulses is applied to the first drive selection signal OPR1. When the first marker signal Mak1 is applied again, the level shifter can reset the count value to the address 0x00. Therefore, the level shifter can operate based on the above process and can repeatedly output the clock signals included in the addresses from 0x00 to 0x09.

[0117] As Figure 17 , 18 shown in Figure 15 and 20, in the up-counter Up-CNT of the level shifter, the address value for outputting the second clock signal CLKS2 to be applied to the second scan signal generators SCG2[1] to SCG2[m] shown in

[0118] First, when the third marker signal Mak3 corresponding to four pulses is applied to the second drive selection signal OPR2 while the second enable signal EN2 with high logic is applied, the level shifter can be set to use the third address value "0x20 to 0x29" stored in the third marker MAK3.

[0119] Subsequently, when the second enable signal EN2 with low logic is applied to the level shifter, the address 0x20 specified by the third address value can be selected in the data map of the second memory MEM2. At this time, since 01110XX is recorded in the corresponding address, the clock signals with high logic H can be output to the second to fourth channels CH2 to CH4 of the level shifter, and the clock signals with low logic L can be output to the first channel CH1 and the fifth channel CH5 of the level shifter.

[0120] Subsequently, when the addition count signal Upc corresponding to one pulse is applied to the second drive selection signal OPR2 in a state where the second enable signal EN2 having a high logic is applied to the level shifter, the address 0x21 after 0x20 can be selected in the data map of the second memory MEM2. At this time, since 01111XX is recorded in the corresponding address, the clock signal having a low logic L can be output to the first channel CH1, and the clock signal having a high logic H can be output to the second to fifth channels CH2 to CH5.

[0121] The level shifter can operate in this order. Then, after the address 0x29 is selected in the data map of the second memory MEM2, the third marker signal Mak3 corresponding to four pulses is applied to the second drive selection signal OPR2. When the third marker signal Mak3 is applied again, the level shifter can reset the count value to the address 0x20. Therefore, the level shifter can operate based on the above process and can repeatedly output the clock signals included in the addresses from 0x20 to 0x29.

[0122] The level shifter according to the second embodiment can select / control the operating conditions of the controller based on the enable signal and the drive selection signal. Thus, the data map can be configured to include each sequence, thereby enhancing the general purpose. In addition, the data map can be configured to operate in various drive environments. Thus, the level shifter according to the second embodiment can adaptively drive the data map.

[0123] Figure 21 is a diagram showing in more detail the elements included in the controller of the modified embodiment according to the second embodiment.

[0124] As Figure 21 shown, according to the modified embodiment of the second embodiment, the first controller CON1 included in the level shifter may include an interface INF and a register REG. In addition to the first controller CON1, Figure 14 the second controller CON2 and the third controller CON3 may be the same.

[0125] Therefore, according to the modified embodiment of the second embodiment, the level shifter can monitor the drive state based on the mutual communication with the timing controller, and in addition, the output conditions can be changed. That is, the input / output of the level shifter can be controlled by the timing controller.

[0126] As described above, the present invention can generate a clock signal for simplifying the control signal of the level shifter based on a data map (sequence-based logical values) stored in a memory, and can also reduce the number of input pins. In addition, the present invention can monitor the driving state of the level shifter based on the communication between the timing controller and the level shifter, and can easily change and control the output conditions of the level shifter to enhance the general purpose of the device. Further, the present invention can store tags for addressing specific clock signals, can use enable signals and drive selection signals to implement repetitive sequences, and can specify output timing.

[0127] The effects according to the present invention are not limited to the above examples, and various other effects may be included in this specification.

[0128] Although the present invention has been specifically shown and described with reference to its exemplary embodiments, those of ordinary skill in the art will understand that various changes in form and detail may be made in the present invention without departing from the spirit of the invention as defined by the appended claims.

Claims

1. A display device, comprising: a display panel configured to display an image; a level shifter configured to extract and output data from a data map of a memory and divide a serial output signal output to the level shifter into parallel output signals based on an enable signal to output a periodic signal; as well as A shift register is configured to output a gate signal to be applied to the display panel based on the periodic signal output from the level shifter.

2. The display device according to claim 1, wherein the level shifter comprises: a controller configured to generate a count signal for extracting data from a data map of the memory based on the enable signal; as well as A bit division circuit is configured to divide the serial output signal into the parallel output signals. 3 . The display device according to claim 1 , wherein the data map includes data whose logic values ​​are sequentially stored, wherein the logic values ​​are output through a channel of each address.

4. The display device according to claim 1, wherein the level shifter shifts the address value of the data map as long as the enable signal is applied as a first logic, and extracts the data included in the address value of the data map as an output signal as long as the enable signal is applied as a second logic opposite to the first logic to output the output signal as the periodic signal. 5 . The display device according to claim 1 , wherein the level shifter comprises a selector configured to generate a selection signal for selecting an operation condition of the controller based on the enable signal and a driving selection signal.

6. The display device according to claim 5, wherein the controller comprises: a plurality of tags configured to respectively store address values ​​distinguishable from one another; a counter configured to generate a count signal based on the enable signal; as well as A demultiplexer, the demultiplexer being configured to: based on the selection signal, output an enable control signal for controlling the enable switch so that the enable signal is applied to the counter, and output a tag control signal for turning on one of a plurality of tag switches so that an address value included in one of the plurality of tags is applied to an address signal input terminal of the counter.

7. The display device according to claim 5, wherein the enable signal and the drive selection signal are output from a timing controller connected to the level shifter, An input or output condition of the level shifter is changed based on bidirectional data communication with the timing controller.

8. The display device according to claim 6, wherein the level shifter shifts the address value of the data map as long as the enable signal is applied as a first logic, and extracts data included in the address value of the data map as an output signal to output the output signal as the periodic signal as long as the enable signal is applied as a second logic opposite to the first logic, When the enable signal is applied as the first logic, the flag control signal is applied as a pulse type.

9. The display device according to claim 2, wherein the controller comprises a clock generator and an adder counter, wherein the clock generator is configured to generate a clock to be applied to the adder counter, The adding counter is configured to generate a count signal which increases based on a clock output from the clock generator. 10 . The display device according to claim 9 , wherein the adding counter is further configured to output an overflow signal via an overflow signal output terminal, and when the overflow signal is input via a reset input terminal of the adding counter, the adding counter resets the count signal.

11. The display device according to claim 2, wherein the level shifter further comprises an output circuit, and the bit division circuit comprises a shift register and a buffer, wherein the shift register in the bit division circuit is configured to divide the serial output signal output from the memory into the parallel output signal based on a bit division operation, The buffer is configured to transfer an output signal output from the shift register in the bit division circuit to the output circuit. 12 . The display device according to claim 11 , wherein the output circuit is configured to shift up a level of an output signal output via the buffer and output the output signal.

13. The display device according to claim 7, wherein the controller further comprises an interface and a register, wherein the controller is further configured to perform bidirectional data communication with the timing controller based on the interface, Wherein the register is configured to store a current state of a memory included in the level shifter.

14. A level shifter comprising: A memory including a data map in which logic values ​​are sequentially stored, the logic values ​​being output via a channel for each address; a controller configured to generate a count signal based on an enable signal and extract data from a data map of the memory; as well as A bit division circuit is configured to divide a serial output signal output from the memory into parallel output signals.

15. The level shifter of claim 14, wherein the controller shifts the address value of the data map whenever the enable signal is applied as a first logic, and extracts data included in the address value of the data map as an output signal to output the output signal as a periodic signal whenever the enable signal is applied as a second logic opposite to the first logic. 16 . The level shifter of claim 14 , wherein the data map includes data whose logic values ​​are sequentially stored, wherein the logic value of the data is output through a channel for each address. 17 . The level shifter according to claim 14 , further comprising a selector configured to generate a selection signal for selecting an operating condition of the controller based on the enable signal and a driving selection signal.

18. The level shifter according to claim 17, wherein the controller comprises: a plurality of tags configured to respectively store address values ​​distinguishable from one another; a counter configured to generate a count signal based on the enable signal; as well as A demultiplexer, the demultiplexer being configured to: based on the selection signal, output an enable control signal for controlling the enable switch so that the enable signal is applied to the counter, and output a tag control signal for turning on one of a plurality of tag switches so that an address value included in one of the plurality of tags is applied to an address signal input terminal of the counter.

19. The level shifter according to claim 18, wherein the level shifter shifts the address value of the data map as long as the enable signal is applied as a first logic, and extracts data included in the address value of the data map as an output signal to output the output signal as the periodic signal as long as the enable signal is applied as a second logic opposite to the first logic, When the enable signal is applied as the first logic, the flag control signal is applied as a pulse type.

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