Display driving circuit and driving method thereof, and display panel

Abstract

The application discloses a display driving circuit and a driving method thereof and a display panel. The display driving circuit comprises an Nth row of pixel capacitors, wherein N is a positive integer; an (N+1)th row of pixel capacitors connected in cascade with the Nth row of pixel capacitors; and a switching control circuit connected with the Nth row of pixel capacitors and the (N+1)th row of pixel capacitors and used for switching between a first display mode and a second display mode. In the first display mode, data signals input to the Nth row of pixel capacitors and the (N+1)th row of pixel capacitors are written row by row. In the second display mode, the data signals input to the Nth row of pixel capacitors and the (N+1)th row of pixel capacitors are written simultaneously. Through the above-mentioned circuit, switching between the first display mode and the second display mode is realized, and display switching power consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display panels, and in particular to a display driving circuit and a driving method thereof, and a display panel. Background Art

[0002] With the continuous advancement of TFT display technology, market demand for higher refresh rates is growing, especially in the gaming display sector, where esports players are particularly drawn. High refresh rate monitors offer smoother gameplay, but with higher refresh rates comes increased power consumption. To address this issue, frequency doubling technologies, such as DLG (Dual Line Gate) and HSR (Hardware Super Resolution), have been introduced, building upon existing display technologies such as Normal. These technologies include DLG (Dual Line Gate) and HSR (Hardware Super Resolution). DLG replaces the traditional progressive scanning method with a two-line scan method. This means both gates are open simultaneously, and both source lines output the same data (both lines contain the same content). This doubles the pixel charging time and thus the refresh rate. HSR, another type of frequency doubling technology, primarily achieves differential display through timing adjustments. In each frame, only pixels from either odd or even rows are rendered, while the other row is displayed by combining information from two adjacent rows.

[0003] Taking UHD (Ultra High Definition) 3840*2160 resolution 240Hz refresh rate products as an example, the frequency doubling display technology reduces the display resolution to half, that is, two rows of pixels display the same data, and the refresh rate will increase to 480Hz, which is twice the original, but the overall data transmission rate remains unchanged.

[0004] Although this solution reduces the total amount of data logic by half, two rows of the same data still need to be sent out twice, so there is still room for power consumption to be reduced. Summary of the Invention

[0005] The main technical problem solved by the present application is to provide a display driving circuit and its driving method, and a display panel to realize switching between a first display mode and a second display mode, reduce the power consumption of DLG display switching, and specifically reduce the power consumption in the DLG display mode.

[0006] To solve the above problems, the present application provides a display driving circuit in the first aspect, wherein the display driving circuit includes: an Nth row of pixel capacitors; wherein N is a positive integer; an N+1th row of pixel capacitors, cascaded with the Nth row of pixel capacitors; a switching control circuit, connected to the Nth row of pixel capacitors and the N+1th row of pixel capacitors, for realizing switching between a first display mode and a second display mode; wherein, in the first display mode, data signals input to the Nth row of pixel capacitors and the N+1th row of pixel capacitors are written row by row; and in the second display mode, data signals input to the Nth row of pixel capacitors and the N+1th row of pixel capacitors are written simultaneously.

[0007] The switching control circuit is used to realize polarity switching of the pixel capacitors in the Nth row or the pixel capacitors in the N+1th row, thereby realizing switching between the first display mode and the second display mode.

[0008] Among them, the first plate of the pixel capacitor in the Nth row is connected to the data line in the Nth row and to the common electrode line through the switching control circuit, and the second plate of the pixel capacitor in the Nth row is connected to the common electrode line; the first plate of the pixel capacitor in the N+1th row is connected to the data line in the N+1th row and to the second plate of the pixel capacitor in the Nth row through the switching control circuit, and the second plate of the pixel capacitor in the N+1th row is connected to the common electrode line.

[0009] In which, the switching control circuit includes: a first switching unit, arranged between the first plate of the N-th row pixel capacitor and the common electrode line, for controlling the common electrode line to charge the common voltage to the first plate of the N-th row pixel capacitor in the second display mode; a second switching unit, arranged between the second plate of the N-th row pixel capacitor and the first plate of the N+1-th row pixel capacitor and the N+1-th row data line, for controlling the N+1-th row data line to charge the second plate of the N-th row pixel capacitor with the same data voltage as the N+1-th row pixel capacitor in the second display mode.

[0010] The switching control circuit further includes: a control unit connected to the control ends of the first switch unit and the second switch unit, and configured to control the on / off of the first switch unit and the second switch unit.

[0011] In which, the control unit is arranged between the N+1th row data line and the control ends of the first switch unit and the second switch unit, the control end of the control unit is connected to the switching signal line, the first path end is connected to the N+1th row data line, and the second path end is connected to the control ends of the first switch unit and the second switch unit, and is used to control the on / off of the first switch unit and the second switch unit according to the switching signal on the switching signal line and the data signal on the N+1th row data line.

[0012] In which, the display driving circuit also includes: a data writing transistor; the N-th row data writing transistor is arranged between the first plate of the N-th row pixel capacitor and the N-th row data line, and is used to control the N-th row data line to write a data signal to the first plate of the N-th row pixel capacitor; the N+1-th row data writing transistor is arranged between the first plate of the N+1-th row pixel capacitor and the N+1-th row data line, and is used to control the N+1-th row data line to write a data signal to the first plate of the N+1-th row pixel capacitor.

[0013] Among them, the control end of the Nth row data write transistor is connected to the Nth row scan line, and is used to control the Nth row data line to write a data signal to the first plate of the Nth row pixel capacitor according to the scan signal on the Nth row scan line; the control end of the N+1th row data write transistor is connected to the N+1th row scan line, and is used to control the N+1th row data line to write a data signal to the first plate of the N+1th row pixel capacitor according to the scan signal on the N+1th row scan line.

[0014] To solve the above problems, the present application provides a driving method for a display driving circuit in the second aspect, wherein the driving method for the display driving circuit includes: in a first display mode, writing a data voltage to each row of pixel capacitors in sequence so that each row of pixels is displayed in sequence; in a second display mode, writing the same data voltage to every two rows of pixel capacitors by switching the control circuit so that two adjacent rows of pixels are displayed simultaneously.

[0015] To solve the above problem, the present application provides a display panel in a third aspect, wherein the display panel includes the display driving circuit described in any embodiment of the first aspect.

[0016] The beneficial effect of the present application is that by cascading the pixel capacitors of two adjacent rows through a switching control circuit, the display polarity signal switching and display data switching of one of the two adjacent rows of pixels can be realized, thereby realizing the switching between the first display mode and the second display mode of the entire display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 A schematic structural diagram of an embodiment of a display driving circuit provided in this application;

[0019] Figure 2 This is a timing diagram of an embodiment of the first display mode provided by this application;

[0020] Figure 3 This is a timing diagram of an embodiment of the second display mode provided by this application;

[0021] Figure 4 A schematic structural diagram of a first specific embodiment of a display driving circuit provided in this application;

[0022] Figure 5 A schematic structural diagram of a second specific embodiment of the display driving circuit provided in this application;

[0023] Figure 6 A schematic structural diagram of a third specific embodiment of the display driving circuit provided in this application;

[0024] Figure 7 A schematic structural diagram of a fourth specific embodiment of the display driving circuit provided in this application;

[0025] Figure 8 A schematic structural diagram of a fifth specific embodiment of the display driving circuit provided in this application;

[0026] Figure 9 A schematic diagram of the circuit structure of a specific embodiment of the display driving circuit provided by this application;

[0027] Figure 10 A driving timing diagram of a specific embodiment of the display driving circuit provided by this application;

[0028] Figure 11 A circuit diagram of the first driving stage of the display driving circuit provided by this application in the first display mode;

[0029] Figure 12 A circuit diagram of the second driving stage of the display driving circuit provided by this application in the first display mode;

[0030] Figure 13 A circuit diagram of the third driving stage of the display driving circuit provided by this application in the first display mode;

[0031] Figure 14 A circuit diagram of the first driving stage of the display driving circuit provided by this application in the second display mode;

[0032] Figure 15 A circuit diagram of the second driving stage of the display driving circuit provided by this application in the second display mode;

[0033] Figure 16 This is a circuit diagram of the third driving stage of the display driving circuit provided by this application in the second display mode.

[0034] Explanation of symbols:

[0035] Pixel capacitor Cst(n) of the Nth row; pixel capacitor Cst(n+1) of the N+1th row; switching control circuit 11; data line Data(n) of the Nth row; data line Data(n+1) of the N+1th row; common electrode line COM; scan line Scan(n) of the Nth row; scan line Scan(n+1) of the N+1th row; first switch unit 111; second switch unit 112; third switch unit 113; control unit 110; switching signal line DLG; data write transistor T(n) of the Nth row; data write transistor T(n+1) of the N+1th row; common electrode transistor Q(n) of the Nth row; common electrode transistor Q(n+1) of the N+1th row; first transistor Q1, second transistor Q2, third transistor Q3, fourth transistor Q4. DETAILED DESCRIPTION

[0036] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0037] The terms used in the examples of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a," "the," and "the" used in the examples of this application and the appended claims are also intended to include plural forms. Unless otherwise clearly indicated above, "a plurality" generally includes at least two, but does not exclude the inclusion of at least one.

[0038] It should be understood that the term "and / or" as used herein is merely a description of the association relationship between associated objects, indicating that three possible relationships exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship. The terms "first," "second," etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0039] It should be understood that the terms "comprises," "comprising," or any other variations thereof as used herein are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0040] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), such directional indications are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0041] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in every place in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0042] The present application provides a display driving circuit, which includes: two adjacent rows of cascaded pixel capacitors and a switching control circuit that controls the display switching of the two adjacent rows of pixel capacitors. Figure 1 , Figure 1 This is a schematic diagram of the structure of an embodiment of the display driving circuit provided by the present application. The Nth row of pixels and the N+1th row of pixels are used as an example for explanation. Figure 1As shown, the display driving circuit includes an N-th row pixel capacitor Cst(n) and an N+1-th row pixel capacitor Cst(n+1) connected to each other. The N-th row pixel capacitor Cst(n) is the capacitor in the N-th row pixel, and the N+1-th row pixel capacitor Cst(n) is the capacitor in the N+1-th row pixel. It should be noted that in the pixel circuit, the storage capacitor and the liquid crystal capacitor are connected in parallel, and the storage capacitor and the liquid crystal capacitor together constitute the pixel capacitor Cst.

[0043] In this embodiment, the display driving circuit further includes a switching control circuit 11, which is connected to the pixel capacitors Cst(n) of the Nth row and the pixel capacitors Cst(n+1) of the N+1th row to realize switching between the first display mode and the second display mode.

[0044] In the first display mode, the switching control circuit 11 controls the data signals input to the pixel capacitors Cst(n) in the Nth row and the pixel capacitors Cst(n+1) in the N+1th row to be written row by row. In the second display mode, the switching control circuit 11 controls the data signals input to the pixel capacitors Cst(n) in the Nth row and the pixel capacitors Cst(n+1) in the N+1th row to be written simultaneously, and the polarities of the data signals written to the pixel capacitors Cst(n) in the Nth row and the pixel capacitors Cst(n+1) in the N+1th row are opposite.

[0045] Specifically, the switching control circuit 11 is used to implement polarity switching of the pixel capacitor Cst(n) in the Nth row or the pixel capacitor Cst(n+1) in the N+1th row, thereby implementing switching between the first display mode and the second display mode.

[0046] It should be noted that the first display mode is normal mode, which is progressive scan display. Figure 2 , Figure 2 This is a timing diagram of an embodiment of the first display mode provided by this application. STV is the start scan signal, G1 is the scan signal for the first row of pixel units, G2 is the scan signal for the second row of pixel units, and so on. In the first display mode, the scan signal controls each row of pixel units to turn on row by row, thereby charging the data signal into each row of pixel capacitors Cst(n) row by row, thereby achieving progressive scanning and progressive display.

[0047] The second display mode is DLG mode, please refer to Figure 3 , Figure 3 This is a timing diagram of an embodiment of the second display mode provided by this application. Figure 3As shown, in the second display mode, every two rows of pixel units are turned on at the same time, and the same data is charged to every two rows of pixel units, so that every two rows of pixel units display the same brightness. The second display mode can reduce the display resolution to half, and the refresh rate is doubled. For example, in the first display mode, the refresh rate of the display panel is 240Hz, and the refresh rate of the display panel in the second display mode is 480Hz, which is twice the original, but the total data transmission rate remains unchanged.

[0048] Specifically, the first electrode of the Nth row of pixel capacitors Cst(n) is connected with the Nth row of data lines Data(n) and the common electrode line COM through the switching control circuit 11, and the second electrode of the Nth row of pixel capacitors Cst(n) is connected with the common electrode line COM.

[0049] The first electrode plate of the N+1th row of pixel capacitors Cst(n+1) is connected with the N+1th row of data lines Data(n+1) and the second electrode plate of the Nth row of pixel capacitors Cst(n) through the switching control circuit 11, and the second electrode plate of the N+1th row of pixel capacitors Cst(n+1) is connected with the common electrode line COM.

[0050] For details, please further refer to Figure 4 , Figure 4 The structure diagram of the first specific embodiment of the display driving circuit provided in the present application is shown in FIG. 1. Figure 4 As shown, the switching control circuit 11 includes a first switch unit 111 and a second switch unit 112. Specifically, the first switch unit 111 is arranged between the second electrode plate of the Nth row of pixel capacitors Cst(n) and the first electrode plate of the N+1th row of pixel capacitors Cst(n+1). Since the first electrode plate of the N+1th row of pixel capacitors Cst(n+1) is also connected with the N+1th row of data lines Data(n+1), the first switch unit 111 is also arranged between the second electrode plate of the Nth row of pixel capacitors Cst(n) and the N+1th row of data lines Data(n+1). The first switch unit 111 controls the N+1th row of data lines Data(n+1) to charge the data signal to the second electrode plate of the Nth row of pixel capacitors Cst(n), or controls the data signal stored in the first electrode plate of the N+1th row of pixel capacitors Cst(n+1) to be charged to the second electrode plate of the Nth row of pixel capacitors Cst(n). It should be noted that the N+1th row of data lines Data(n+1) can first charge the data voltage to the first electrode plate of the N+1th row of pixel capacitors Cst(n+1), and then the data signal stored in the first electrode plate of the N+1th row of pixel capacitors Cst(n+1) is charged to the second electrode plate of the Nth row of pixel capacitors Cst(n). The charging can be simultaneous or sequential, which is not limited herein.

[0051] The second switch unit 112 is disposed between the first plate of the N-th row pixel capacitor Cst(n) and the common electrode line COM, and is used to control the common electrode line COM to charge the common voltage Vcom to the first plate of the N-th row pixel capacitor Cst(n) in the second display mode.

[0052] Furthermore, the switching control circuit 11 further includes a third switch unit 113, which is disposed between the second electrode plate of the pixel capacitor Cst(n) in the Nth row and the common electrode line COM, and is used to control the common electrode line COM to charge the common voltage Vcom to the second electrode plate of the pixel capacitor in the Nth row in the first display mode and the second display mode. Figure 5 , Figure 5 This is a structural diagram of the second specific embodiment of the display driving circuit provided in the present application. In this embodiment, when the first switch unit 111 and the second switch unit 112 are working, the third switch unit 113 is not working; when the first switch unit 111 and the second switch unit 112 are not working, the third switch unit 113 is working; working means that the transistors in the unit are turned on. In a specific embodiment, the driving characteristics of the transistors in the first switch unit 111, the second switch unit 112 and the third switch unit 113 are opposite. Specifically, the transistors in the first switch unit 111 and the second switch unit 112 are Pmos tubes, and the transistors in the third switch unit 113 are Nmos tubes. In other embodiments, the transistors in the first switch unit 111 and the second switch unit 112 are Nmos tubes, and the transistors in the third switch unit 113 are Pmos tubes, which are not specifically limited here, and the level signals on the corresponding scan lines are also opposite.

[0053] Furthermore, the switching control circuit 11 further includes a control unit 110, which is connected to the control terminals of the first switch unit 111 and the second switch unit 112, and is used to control the first switch unit 111 and the second switch unit 112 to work, so as to switch the display mode. Figure 6 , Figure 6 This is a schematic diagram of the structure of the third specific embodiment of the display driving circuit provided by this application. Figure 6As shown, the switching control circuit 11 includes a control unit 110. The control unit 110 is arranged between the N+1th row scan line Scan(n+1) and the control ends of the first switch unit 111 and the second switch unit 112. Specifically, the control end of the control unit 110 is connected to the switching signal line DLG, the first path end is connected to the N+1th row scan line Scan(n+1), and the second path end is connected to the control ends of the first switch unit 111 and the second switch unit 112. It is used to control the on / off of the first switch unit 111 and the second switch unit 112 according to the switching signal on the switching signal line DLG and the scan signal on the N+1th row scan line Scan(n+1). Among them, the switching signal and the scan signal refer to high / low levels. It should be noted that the first path end can also be called an input end, and the second path end can also be called an output end, specifically the source / drain of the transistor, and the control end is also the gate of the transistor.

[0054] In this preferred embodiment, the control terminal of the third switch unit 113 is connected to the N+1th row scan line Scan(n+1), so that the third switch unit 113 is always in the on state during the non-scanning phase of the N+1th row pixels (that is, when Scan(n+1) is at a low potential), thereby controlling the writing of the common voltage to the second plate of the Nth row pixel capacitor Cst(n). In other embodiments, the control terminal of the third switch unit 113 can also be connected to the control unit 110, and the switching signal on the switching signal line DLG connected to the control terminal of the control unit 110 is a jump signal, which can be specifically designed according to actual conditions.

[0055] In a preferred embodiment, the display driving circuit further includes a data writing transistor. Each row of pixels includes a data writing transistor. Figure 7 , Figure 7 This is a schematic diagram of the structure of the fourth specific embodiment of the display driver circuit provided by the present application. The Nth row of pixels includes the Nth row of data write transistors T(n), and the N+1th row of pixels includes the Nth row of data write transistors T(n+1). The gate of the data write transistor is connected to the scan line, the source is connected to the data line, and the drain is connected to the pixel capacitor. Specifically, the gate of the data write transistor in each row is connected to the scan line in each row, the source is connected to the data line in each row, and the drain is connected to the pixel capacitor in each row.

[0056] Specifically, the N-th row data write transistor T(n) is arranged between the first plate of the N-th row pixel capacitor Cst(n) and the N-th row data line Data(n), the control end of the N-th row data write transistor T(n) is connected to the N-th row scan line Scan(n), the input end is connected to the N-th row data line Data(n), and the output end is connected to the first plate of the N-th row pixel capacitor Cst(n), and is used to control the N-th row data line Data(n) to write the data signal Vdata to the first plate of the N-th row pixel capacitor Cst(n).

[0057] The N+1th row data write transistor T(n+1) is arranged between the first plate of the N+1th row pixel capacitor Cst(n+1) and the N+1th row data line Data(n+1). The control end of the N+1th row data write transistor T(n+1) is connected to the N+1th row scan line Scan(n+1), the input end is connected to the N+1th row data line Data(n+1), and the output end is connected to the first plate of the N+1th row pixel capacitor Cst(n+1), and is used to control the N+1th row data line Data(n+1) to write the data signal Vdata to the first plate of the N+1th row pixel capacitor Cst(n+1).

[0058] It should be noted that the present application may also not set up a data writing transistor, and the driver (IC) controls the signal on the data line Data to be transmitted in time sequence, and the data voltage is written in sequence, which is not limited here.

[0059] In another preferred embodiment, the display driving circuit further includes a common electrode transistor, Figure 8 This is a schematic diagram of the structure of the fifth specific embodiment of the display driving circuit provided by this application. Figure 8 As shown, each row of common electrode transistors is disposed between the second electrode plate of each row of pixel capacitors and each row of data lines, and is used to control the writing of the common voltage to the pixel capacitors. The gate of each row of common electrode transistors is connected to the scan signal of the next row, and the driving characteristics of the common electrode transistors and the data writing transistors are opposite, so that the common electrode transistors and the data writing transistors are turned on at the same time, thereby enabling the writing of the data voltage and the common voltage to the storage capacitor in the first display mode.

[0060] Specifically, the N-th row common electrode transistor Q(n) is disposed between the second electrode plate of the N-th row pixel capacitor Cst(n) and the common electrode line COM. The gate of the N-th row common electrode transistor Q(n) is connected to the N+1-th row scan line Scan(n+1). A first path end is connected to the common electrode line COM, and a second path end is connected to the second electrode plate of the N-th row pixel capacitor Cst(n). The transistor is configured to control the common electrode line COM to write a common voltage Vcom to the second electrode plate of the N-th row pixel capacitor Cst(n).

[0061] The common electrode transistor Q(n+1) of the N+1th row is arranged between the second plate of the pixel capacitor Cst(n+1) of the N+1th row and the common electrode line COM. The gate of the common electrode transistor Q(n+1) of the N+1th row is connected to the scan line Scan(n+2) of the N+2th row. The first path end is connected to the common electrode line COM, and the second path end is connected to the second plate of the pixel capacitor Cst(n+1) of the N+1th row, and is used to control the common electrode line COM to write the common voltage Vcom to the second plate of the pixel capacitor Cst(n+1) of the N+1th row.

[0062] It should be noted that the third switch unit 113 in the fourth embodiment is equivalent to the Nth row common electrode transistor Q(n) in the fifth embodiment, and the fourth embodiment omits the N+1th row common electrode transistor Q(n+1) compared to the fifth embodiment. The fifth embodiment can be a solution for implementing display mode switching by adding a first switch unit 111 and a second switch unit 112 and a control unit 110 to two adjacent pixel units in the basic pixel unit. In the basic pixel unit, each row of pixel units includes a data write transistor and a common electrode transistor to control the writing of the display signal on the pixel capacitor through the data write transistor and the common electrode transistor, thereby controlling the display of the pixel.

[0063] This application also provides a circuit structure diagram of a display driving circuit. Figure 9 , Figure 9 This is a circuit diagram of a specific embodiment of the display driving circuit provided by this application. Figure 9 shown.

[0064] The first switch unit 111 includes a first transistor Q1 ; the second switch unit 112 includes a second transistor Q2 ; the third switch unit 113 includes a third transistor Q3 ; and the control unit 110 includes a fourth transistor Q4 .

[0065] See also Figure 10 , Figure 10 This is a driving timing diagram of a specific embodiment of the display driving circuit provided by this application. Figures 11-16 ,in, Figure 11-13 This is a circuit diagram of the display driving circuit provided by the present application in the driving phase in the first display mode. Specifically, Figure 11 This is a circuit diagram of the first driving stage of the display driving circuit provided by this application in the first display mode. Figure 12 This is a circuit diagram of the second driving stage of the display driving circuit provided by this application in the first display mode. Figure 13 This is a circuit diagram of the third driving stage of the display driving circuit provided by this application in the first display mode. Figure 14-16 This is a circuit diagram of the display driving circuit provided by the present application in the driving phase in the second display mode. Specifically, Figure 14 This is a circuit diagram of the first driving stage of the display driving circuit provided by this application in the second display mode. Figure 15 This is a circuit diagram of the second driving stage of the display driving circuit provided by this application in the second display mode. Figure 16 This is a circuit diagram of the third driving stage of the display driving circuit provided by this application in the second display mode.

[0066] The first display mode includes an N-th row pixel sampling phase, an N+1-th row pixel sampling phase, and a holding phase.

[0067] In the first display mode, during the sampling phase of the Nth row of pixels, the switching signal line DLG transmits a low-potential signal. At this time, the Nth row scan line Scan(n) transmits a high potential, and the N+1th row scan line Scan(n+1) transmits a low potential. Only the Nth row data write transistor T(n) and the third transistor Q3 are turned on. The Nth row data line Data(n) charges the Nth row pixel capacitor Cst(n) with the data voltage. The potential of point Q (the first plate of the Nth row pixel capacitor Cst(n)) is Vdata(n). Please refer to Figure 11 .

[0068] In the N+1th row pixel sampling phase in the first display mode, the Nth row scan line Scan(n) transmits a low potential, the N+1th row scan line Scan(n+1) transmits a high potential, only the Nth row data write transistor T(n) is turned on, the N+1th row data line Data(n+1) charges the N+1th row pixel capacitor Cst(n+1) with the data voltage, and the potential of point P (the first plate of the N+1th row pixel capacitor Cst(n+1)) is Vdata(n+1). Please refer to Figure 12 .

[0069] In the hold phase of the first display mode, the scan signals transmitted by the Nth row scan line Scan(n) and the N+1th row scan line Scan(n+1) are both at low potential. At this time, only the fourth transistor Q4 in the circuit is turned on, and the potential at point Q remains at Vdata(n), and the potential at point P remains at Vdata(n+1), thereby maintaining the display state of the display panel. Figure 13 .

[0070] The second display mode also includes an Nth row pixel sampling phase, an N+1th row pixel sampling phase, and a holding phase.

[0071] In the Nth row pixel sampling phase in the second display mode, the switching signal line DLG transmits a high potential, and the second transistor Q2 in the circuit is turned on. When the Nth row scan line Scan(n) sampling phase begins, the Nth row scan line Scan(n) transmits a high potential, and the N+1th row scan line Scan(n+1) transmits a low potential. Only the Nth row data is written into the transistor T(n), and the second transistor Q2 and the fourth transistor Q4 are turned on. According to the design scheme, at this time, the Nth row data line Data(n) has no action (that is, no data signal), and the Nth row pixel capacitor Cst(n) and the N+1th row pixel capacitor Cst(n+1) are not charged. Please refer to Figure 14 .

[0072] In the N+1th row pixel sampling phase in the second display mode, when entering the N+1th row pixel sampling phase, the Nth row scan line Scan(n) transmits a low potential, and the N+1th row scan line Scan(n+1) transmits a high potential. At this time, the first transistor Q1, the second transistor Q2, and the N+1th row data write transistor T(n+1) are turned on, and the fourth transistor Q4 and the Nth row data write transistor T(n) are turned off. At this time, the potential of point Q is Vcom, and the N+1th row data line Data(n+1) charges point P. At this time, the potential of point P and the second plate of the Nth row pixel capacitor Cst(n) is Vdata, and the potential difference between the first plate and the second plate of the Nth row pixel capacitor Cst(n) is Vcom-Vdata. Figure 15 shown.

[0073] In the holding phase of the second display mode, when entering the holding phase, the scan signals transmitted by the Nth row scan line Scan(n) and the N+1th row scan line Scan(n+1) are both low potential. At this time, only the fourth transistor Q4 and the second transistor Q2 are turned on in the circuit, and the potential of point P is Vdata(n+1). According to the KVL (Kirchhoff's voltage law) formula, the potential of point Q at this time is VQ=2×Vcom-Vdata(n+1), as shown in the following example: Figure 16 At this time, the potential difference across the N+1th row of liquid crystal is Vdata(n+1)-Vcom, and the potential difference across the Nth row of liquid crystal is Vcom-Vdata(n+1). The above circuit is used to charge the same data voltage into the two adjacent rows of pixels, and make the polarity of the two adjacent rows of pixels opposite, thereby achieving the polarity reversal of the Nth row of pixels, and then achieving the same display data but opposite display polarity of the two adjacent rows of pixels, thereby achieving the design goal.

[0074] The present application also provides a display panel, wherein the display panel includes pixel units arranged in an array, each row of pixel units includes pixel capacitors, and two adjacent rows of pixel capacitors are connected using the display driving circuit described in any of the above embodiments.

[0075] It should be noted that in the above embodiment, the third transistor Q3 is a PMOS transistor, the rest are NMOS transistors, Scan is a high-potential pulse with a normally low potential, and VCOM is a common potential. In other embodiments, the third transistor Q3 may be an NMOS transistor, the rest are PMOS transistors, and Scan is a low-potential pulse with a normally high potential, which is not limited here.

[0076] The beneficial effect of the present application is that by cascading the pixel capacitors of two adjacent rows through a switching control circuit, the display polarity signal switching and display data switching of one of the two adjacent rows of pixels can be realized, thereby realizing the switching between the first display mode and the second display mode of the entire display panel, and this display mode switching is automatically achieved through a switching signal line, reducing the power consumption in the second display mode.

[0077] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A display driving circuit, characterized in that: include: An N-th row of pixel capacitors, wherein a first electrode plate of the N-th row of pixel capacitors is connected to an N-th row of data lines, and a second electrode plate of the N-th row of pixel capacitors is connected to a common electrode line; wherein N is a positive integer; an N+1th row of pixel capacitors, wherein a first electrode plate of the N+1th row of pixel capacitors is connected to an N+1th row of data lines and is cascade-connected to a second electrode plate of the Nth row of pixel capacitors, and the second electrode plate of the N+1th row of pixel capacitors is connected to the common electrode line; a switching control circuit connected to the pixel capacitors in the Nth row and the pixel capacitors in the N+1th row, for implementing switching between the first display mode and the second display mode; the switching control circuit includes a first switch unit and a second switch unit, the first switch unit being arranged between the second plate of the pixel capacitors in the Nth row, the first plate of the pixel capacitors in the N+1th row, and the data line in the N+1th row; and the second switch unit being arranged between the first plate of the pixel capacitors in the Nth row and the common electrode line; Wherein, in the first display mode, the data signals input to the pixel capacitors in the Nth row and the pixel capacitors in the N+1th row are written row by row; In the second display mode, the first switch unit controls the N+1th row data line to charge the second plate of the Nth row pixel capacitor with the same data voltage as the N+1th row pixel capacitor, and at the same time controls the common electrode line to charge the first plate of the Nth row pixel capacitor with a common voltage, so that the data signals input to the Nth row pixel capacitor and the N+1th row pixel capacitor are the same.

2. The display driving circuit according to claim 1, wherein: The switching control circuit is used to realize polarity switching of the pixel capacitors in the Nth row, thereby realizing switching between the first display mode and the second display mode.

3. The display driving circuit according to claim 1, wherein: The switching control circuit includes: The third switching transistor is arranged between the second plate of the pixel capacitor in the Nth row and the common electrode line, and is used to control the common electrode line to charge the second plate of the pixel capacitor in the Nth row into a common voltage in the first display mode and the second display mode.

4. The display driving circuit according to claim 1, wherein: The switching control circuit further includes: A control unit is connected to the control ends of the first switch unit and the second switch unit, and is used to control the first switch unit and the second switch unit to operate.

5. The display driving circuit according to claim 4, wherein: The control unit is arranged between the N+1th row scan line and the control ends of the first switch unit and the second switch unit, the control end of the control unit is connected to the switching signal line, the first path end of the control unit is connected to the N+1th row scan line, and the second path end of the control unit is connected to the control ends of the first switch unit and the second switch unit, and is used to control the on / off of the first switch unit and the second switch unit according to the switching signal on the switching signal line and the scan signal on the N+1th row scan line.

6. The display driving circuit according to claim 1, wherein: The display driving circuit further includes: a data writing transistor; The Nth row data writing transistor is disposed between the first electrode plate of the Nth row pixel capacitor and the Nth row data line, and is used to control the Nth row data line to write a data signal to the first electrode plate of the Nth row pixel capacitor; The N+1th row data writing transistor is arranged between the first plate of the N+1th row pixel capacitor and the N+1th row data line, and is used to control the N+1th row data line to write a data signal to the first plate of the N+1th row pixel capacitor.

7. The display driving circuit according to claim 6, wherein: The control end of the N-th row data writing transistor is connected to the N-th row scan line, and is used to control the N-th row data line to write a data signal to the first electrode plate of the N-th row pixel capacitor according to the scan signal on the N-th row scan line; The control end of the N+1th row data writing transistor is connected to the N+1th row scan line, and is used to control the N+1th row data line to write a data signal to the first electrode plate of the N+1th row pixel capacitor according to the scan signal on the N+1th row scan line.

8. A driving method for a display driving circuit according to any one of claims 1 to 7, characterized in that: The driving method of the display driving circuit includes: In the first display mode, the display driving circuit writes data voltages to each row of pixel capacitors in sequence, so that each row of pixels is displayed in sequence; In the second display mode, the display driving circuit writes the same data voltage to every two rows of pixel capacitors through the switching control circuit, so that two adjacent rows of pixels are displayed simultaneously.

9. A display panel, characterized in that: The display panel includes the display driving circuit according to any one of claims 1 to 7.

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