Pseudo signal generator and display device including same

Abstract

A display device includes: a display panel configured to display an image; a shift register configured to output a gate signal to be applied to the display panel based on a periodic signal output from the level shifter; a dummy generator configured to sense the periodic signal to convert it into a current and invert a phase to output a dummy signal of an inverted current type; and a dummy pattern portion disposed on the display panel, the dummy pattern portion including a pattern to which the dummy signal is applied.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2023 - 0197122, filed on December 29, 2023, which is incorporated herein by reference in its entirety as if fully set forth herein. Technical field

[0003] The present disclosure relates to a pseudo signal generator and a display device including the same. Background art

[0004] With the development of information technology, the market for display devices as a connection medium between users and information has gradually grown. Accordingly, the use of display devices such as light - emitting display devices, quantum dot display (QDD) devices, and liquid crystal display (LCD) devices has gradually increased.

[0005] The above - mentioned display device includes: a display panel including a plurality of sub - pixels, a driver that outputs a driving signal for driving the display panel, and a power supply that generates power to be provided to the display panel or the driver.

[0006] In such a display device, when a driving signal (e.g., a scan signal and a data signal) is provided to each sub - pixel provided in the display panel, the selected sub - pixel can transmit light or can emit light itself, and thus an image can be displayed. Summary of the invention

[0007] The present disclosure can solve the problem of radiation mismatching caused by the load difference between a shift register and a pseudo - pattern unit, can enhance the robustness to noise, and can cancel or minimize an electric field causing electromagnetic interference (EMI). In addition, the present disclosure can generate a current - type pseudo signal corresponding to a clock signal and can accumulate at least one of the pseudo signals, thereby not only implementing an integrated design of the pseudo - pattern unit but also reducing the area occupied by the pseudo - pattern unit, thereby reducing the bezel area of the display panel.

[0008] To achieve these objects and other advantages and in accordance with the purpose of the present disclosure, as specifically and generally described herein, a display device includes: a display panel configured to display an image; a shift register configured to output a gate signal to be applied to the display panel based on a periodic signal output from a level shifter; a pseudo generator configured to sense the periodic signal to convert it into a current and invert the phase to output a pseudo signal of an inverted current type; and a pseudo pattern portion provided on the display panel, the pseudo pattern portion including a pattern to which the pseudo signal is applied.

[0009] The pseudo pattern portion may include a pattern that cancels an electric field generated by the periodic signal based on the pseudo signal.

[0010] The pseudo generator may include: a current sensing circuit configured to sense the periodic signal; and a phase inversion circuit configured to invert the phase of the sensed current to output a pseudo signal of the inverted current type.

[0011] The pseudo generator may include a current sensing and phase inversion circuit, and the current sensing and phase inversion circuit includes: a first transistor configured to sense the periodic signal to convert it into a current; and a second transistor configured to operate in the same manner as the first transistor and invert the phase of the sensed current to output a pseudo signal of the inverted current type.

[0012] The first transistor and the second transistor may be configured in a current mirror type.

[0013] The first transistor may include a first electrode connected to an input terminal, a second electrode connected to an output terminal, and a gate electrode connected to the output terminal and the gate electrode of the second transistor, and the second transistor may include a first electrode connected to the pseudo pattern portion, a second electrode connected to a ground terminal, and a gate electrode connected to the output terminal and the gate electrode of the first transistor.

[0014] The pseudo generator may further include a current accumulation circuit configured to accumulate one or more inverted currents to generate a pseudo signal of an accumulated current type.

[0015] The pseudo generator and the pseudo pattern portion may be provided in a non-display area of the display panel.

[0016] The periodic signal may include a clock signal.

[0017] In another aspect of the present disclosure, a pseudo-signal generator includes: a pseudo-generator configured to sense a periodic signal to convert it into a current and invert the phase to output a pseudo-signal of an inverted current type; and a pseudo-pattern portion including a pattern that cancels an electric field generated by the periodic signal based on the pseudo-signal.

[0018] The pseudo-generator may include: a first transistor configured to sense the periodic signal to convert it into a current; and a second transistor configured to operate in the same manner as the first transistor and invert the phase of the sensed current to output the pseudo-signal of the inverted current type.

[0019] The first transistor may include a first electrode connected to an input terminal, a second electrode connected to an output terminal, and a gate electrode connected to the output terminal and a gate electrode of the second transistor, and the second transistor may include a first electrode connected to the pseudo-pattern portion, a second electrode connected to a ground terminal, and a gate electrode connected to the output terminal and a gate electrode of the first transistor.

[0020] At least one of the pseudo-generator and the pseudo-pattern portion may include a current accumulation circuit configured to accumulate one or more inverted currents to generate a pseudo-signal of an accumulated current type. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. In the drawings:

[0022] Figure 1 is a block diagram schematically illustrating a light-emitting display device;

[0023] Figure 2 is schematically illustrated Figure 1 a view of a sub-pixel shown in;

[0024] Figure 3 and Figure 4 is a view describing a configuration of a gate driver of a gate-in-panel (GIP) type;

[0025] Figure 5 is a view illustrating an arrangement example of a GIP type gate driver;

[0026] Figure 6 is a plan view schematically illustrating a part of a light-emitting display device according to a first embodiment;

[0027] Figure 7 is schematically illustrated Figure 6Block diagram of the pseudo generator shown in;

[0028] Figure 8 is a view depicting the input / output variations of the pseudo generator according to the first embodiment;

[0029] Figure 9 is a plan view illustrating a part of the light-emitting display device according to the second embodiment;

[0030] Figure 10 is to illustrate Figure 9 the block diagram of the pseudo generator shown in;

[0031] Figure 11 is a circuit configuration diagram of the pseudo generator according to the second embodiment;

[0032] Figures 12 to 17 is an application Figure 11 view of an example of the pseudo generator and a view depicting the input / output variations based thereon;

[0033] Figures 18 to 20 is a view depicting the electric field cancellation efficiency of the pseudo generator according to the second embodiment. Detailed Description of the Invention

[0034] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the present disclosure to those skilled in the art.

[0035] The display device according to the present disclosure can be applied to a television (TV), a video player, a personal computer (PC), a home theater, an electronic device of a vehicle, and a smart phone, but is not limited thereto. The display device according to the present disclosure can be implemented as a light-emitting display device, a quantum dot display (QDD) device, or a liquid crystal display (LCD) device. Hereinafter, for convenience of description, a light-emitting display device that emits light by itself using an inorganic light-emitting diode or an organic light-emitting diode will be described as an example.

[0036] In addition, the transistors described below can be implemented by an n-type transistor, a p-type transistor, or a combination of an n-type transistor and a p-type transistor. A transistor can be a three-electrode element including a gate, a source, and a drain. The source can be an electrode that supplies carriers to the transistor. In the transistor, carriers can start flowing from the source. The drain can be an electrode through which carriers flow out of the transistor. That is, in the transistor, carriers flow from the source to the drain.

[0037] In a p-type transistor, since the carriers are holes, the source electrode can be at a higher voltage than the drain voltage, causing holes to flow from the source to the drain. In a p-type transistor, since holes flow from the source to the drain, current can flow from the source to the drain. On the other hand, in an n-type transistor, since the carriers are electrons, the source voltage can be lower than the drain voltage, causing electrons to flow from the drain to the source. In an n-type transistor, since electrons flow from the drain to the source, current can flow from the drain to the source. However, the source and drain of a transistor can be switched between based on the applied voltage. Based on this, in the following description, one of the source and drain will be described as the first electrode, and the other of the source and drain will be described as the second electrode.

[0038] Figure 1 is a block diagram schematically illustrating a light-emitting display device, Figure 2 is a schematic illustration Figure 1 of the sub-pixels shown in

[0039] As Figure 1 and Figure 2 shown, a light-emitting display device according to an embodiment of the present disclosure may include a timing controller 120, a gate driver (gate driving circuit) 130, a data driver (data driving circuit) 140, a display panel 150, and a power supply 180.

[0040] A video providing unit 110 (a set-top or host system) may output a video data signal provided from the outside or an image data signal (video data signal) stored in its internal memory together with various driving signals. The video providing unit 110 may provide the data signal and various driving signals to the timing controller 120.

[0041] The timing controller 120 may output a gate timing control signal GDC for controlling the operation timing of the gate driver 130, a data timing control signal DDC for controlling the operation timing of the data driver 140, and various synchronization signals. The timing controller 120 may provide the data timing control signal DDC and the data signal DATA provided from the video providing unit 110 to the data driver 140. The timing controller 120 may be implemented as an integrated circuit (IC) type and may be mounted on a printed circuit board (PCB), but is not limited thereto.

[0042] The gate driver 130 may output a gate signal (or gate voltage) in response to the gate timing control signal GDC provided from the timing controller 120. The gate driver 130 may provide the gate signal to a plurality of sub-pixels included in the display panel 150 through a plurality of gate lines GL1 to GLm. The gate driver 130 may be implemented as an IC type or may be directly provided on the display panel 150 in a gate in panel (GIP) type, but is not limited thereto.

[0043] The data driver 140 may sample and latch a data signal DATA in response to a data timing control signal DDC provided from the timing controller 120, convert a digital data signal into an analog data voltage based on a gamma reference voltage, and output the analog data voltage. The data driver 140 may provide the data voltages to sub-pixels of the display panel 150 through a plurality of data lines DL1 to DLn, respectively. The data driver 140 may be implemented as an IC type or may be mounted on the display panel 150 or a PCB, but is not limited thereto.

[0044] The power supply 180 may generate a high-level voltage and a low-level voltage based on an externally provided external input voltage, and may output the high-level voltage and the low-level voltage through a high-level power supply line EVDD and a low-level power supply line EVSS. In addition to the high-level voltage and the low-level voltage, the power supply 180 may also generate and output a voltage required for driving the gate driver 130 (a gate high voltage and a gate low voltage) or a voltage required for driving the data driver 140.

[0045] The display panel 150 may display an image (video) based on a driving voltage including a high-level voltage and a low-level voltage and a driving signal including a gate signal and a data voltage. Each of the sub-pixels of the display panel 150 may emit light by itself. The display panel 150 may be manufactured based on a substrate having rigidity or flexibility, such as glass, silicon, or polyimide. In addition, the light-emitting sub-pixels may include sub-pixels that emit red, green, and blue, or may include sub-pixels that emit red, green, blue, and white.

[0046] For example, one sub-pixel SP may be connected to a first data line DL1, a first gate line GL1, a high-level power supply line EVDD, and a low-level power supply line EVSS and may include a pixel circuit including a switching transistor, a driving transistor, a capacitor, and an organic light-emitting diode. The sub-pixel SP used in the light-emitting display device may emit light by itself and the configuration of the circuit is complicated. In addition, there may be various types of light-emitting organic light-emitting diodes, and there may be various types of compensation circuits for compensating for deterioration of the driving transistor that provides a driving current required for driving the organic light-emitting diode. Therefore, the sub-pixel SP may be simply shown in a box shape.

[0047] In the above, each of the timing controller 120, the gate driver 130, and the data driver 140 is described as a separate element. However, depending on the implementation of the light-emitting display device, one or more of the timing controller 120, the gate driver 130, and the data driver 140 may be integrated into one IC.

[0048] Figure 3 and Figure 4 is a view illustrating the configuration of the GIP type gate driver 130,Figure 5 It is a view showing an example of the arrangement of a GIP type gate driver.

[0049] As Figure 3 shown, the GIP type gate driver 130 may include a shift register 131 and a level shifter 135. The level shifter 135 may generate a clock signal CLKS and a start signal VST based on signals and voltages output from a timing controller 120 and a power supply 180.

[0050] The clock signal CLKS may be output through a clock signal line, and the start signal VST may be output through a start signal line. The shift register 131 may operate based on the clock signal CLKS and the start signal VST and may output gate signals Gout[1] to Gout[m].

[0051] As Figure 3 and 4 shown, different from the shift register 131, the level shifter 135 may be separately set as an IC type, or may be included in the power supply 180. However, this is only one embodiment, and the embodiments of the present disclosure are not limited thereto.

[0052] As Figure 5 shown, in the GIP type gate driver 130, a first shift register 131a and a second shift register 131b that output gate signals may be respectively disposed in left and right non-display regions NA with respect to a display region AA where an image is displayed in a display panel 150. Based on the GIP type, the first shift register 131a and the second shift register 131b may be formed as a thin film type in the display panel 150.

[0053] Hereinafter, examples in which the first shift register 131a and the second shift register 131b are respectively disposed in the left and right non-display regions NA of the display panel 150 will be described, but the embodiments of the present disclosure are not limited thereto.

[0054] Figure 6 It is a plan view showing a part of a light-emitting display device according to a first embodiment, Figure 7 It is a block diagram showing a Figure 6 pseudo generator shown in Figure 8 It is a view showing the input / output change of the pseudo generator according to the first embodiment.

[0055] As Figure 6 shown, the light-emitting display device according to the first embodiment may include a pseudo generator 133 (or a pseudo signal generator) and pseudo pattern portions 134a, 134b. The pseudo generator 133 and the pseudo pattern portions 134a, 134b may be disposed in the non-display region NA of the display panel 150.

[0056] The dummy generator 133 may be disposed in the non-display area NA located above the display area AA, and the dummy pattern portions 134a and 134b may be respectively disposed in the non-display areas NA located on the left and right sides of the display area AA. The dummy pattern portions 134a and 134b may include a first dummy pattern portion 134a and a second dummy pattern portion 134b that are respectively disposed corresponding to the first shift register 131a and the second shift register 131b. The first dummy pattern portion 134a and the second dummy pattern portion 134b may be implemented by conductive patterns forming a specific shape to cancel out and minimize the electric field causing electromagnetic interference (EMI).

[0057] In Figure 6 it is illustrated that the first dummy pattern portion 134a and the second dummy pattern portion 134b are adjacent to the first shift register 131a and the second shift register 131b respectively and are arranged to be distinguishable from each other. However, Figure 6 it is merely for showing that the first dummy pattern portion 134a and the second dummy pattern portion 134b are adjacent to the first shift register 131a and the second shift register 131b. For example, the first dummy pattern portion 134a may be included in the first shift register 131a or may be disposed between the first shift register 131a and the display area AA, and the second dummy pattern portion 134b may be included in the second shift register 131b or may be disposed between the second shift register 131b and the display area AA.

[0058] As Figure 6 and Figure 7 shown in, according to the first embodiment, the dummy generator 133 may solve the problem of radiation mismatch between the dummy signals generated from the dummy pattern portions 134a and 134b and the clock signals output from the level shifter 135 and applied to the first shift register 131a and the second shift register 131b.

[0059] The dummy generator 133 may include a current sensing circuit 133a, a phase inverting circuit 133b, and a current summation circuit 133c.

[0060] The current sensing circuit 133a can sense the clock signal output from the level shifter 135 and applied to the first shift register 131a and the second shift register 131b, and output it in current form. The current sensing circuit 133a can include an input terminal connected to the clock signal output terminal of the level shifter 135 and an output terminal connected to the clock signal input terminal of each of the first shift register 131a and the second shift register 131b. That is to say, the clock signal line CLKL for transmitting the clock signal can be arranged between the level shifter 135 and the first shift register 131a and the second shift register 131b, and can pass through the current sensing circuit 133a.

[0061] The phase inversion circuit 133b can invert the phase of the clock signal sensed by the current sensing circuit 133a and output in current form (invert 180 degrees), so that the clock signal can be output in inverted current form.

[0062] The current accumulation circuit 133c can accumulate one or more of the inverted currents of the clock signal output through the inversion of the phase inversion circuit 133b and output. The accumulated current output from the current accumulation circuit 133c can be applied to the first pseudo pattern unit 134a and the second pseudo pattern unit 134b.

[0063] As Figure 7 and 8 shown, for example, the total four clock signals CLK1 to CLK4 applied to the pseudo generator 133 can be in voltage form. The four clock signals CLK1 to CLK4 in voltage form can be converted into current form through the sensing operation of the current sensing circuit 133a of the pseudo generator 133. The four clock signals CLK1 to CLK4 in current form can be phase-inverted based on the phase inversion operation and current accumulation operation of the phase inversion circuit 133b and the current accumulation circuit 133c of the pseudo generator 133 and can be output as one current-form pseudo signal.

[0064] Hereinafter, based on the second embodiment, the part related to the pseudo generator 133 will be specifically described and its effects will be described.

[0065] Figure 9 is a plan view illustrating a part of the light-emitting display device according to the second embodiment, Figure 10 is an illustration Figure 9 of the block diagram of the pseudo generator shown in Figure 11 is a circuit configuration diagram of the pseudo generator according to the second embodiment.

[0066] As Figure 9 and Figure 10As shown in [figure], the light-emitting display device according to the second embodiment may include a control board CPCB, a first connector CNT1, a source board SPCB, a second connector CNT2, and a display panel 150.

[0067] The control board CPCB may include a timing controller 120 and a level shifter 135. The timing controller 120 may output clock signals CLKS including a first clock signal G1, a second clock signal G2, and a third clock signal EM. For example, the first clock signal G1 may be used as a clock signal for generating a first scan signal among gate signals, the second clock signal G2 may be used as a clock signal for generating a second scan signal among gate signals, and the third clock signal EM may be used as a clock signal for generating an emission signal among gate signals.

[0068] The level shifter 135 may shift up and output the level of the clock signal CLKS. The level shifter 135 may shift up the level of the clock signal CLKS based on a gate high voltage and a gate low voltage output from a power supply, but embodiments of the present disclosure are not limited thereto.

[0069] Hereinafter, in the second embodiment, an example in which a four-phase first clock signal G1, a five-phase second clock signal G2, and a two-phase third clock signal EM are output from the timing controller 120 will be described.

[0070] The control board CPCB and the source board SPCB may be electrically connected to each other through the first connector CNT1. The source board SPCB and the display panel 150 may be electrically connected to each other through the second connector CNT2.

[0071] A clock signal line CLKL for transmitting the clock signal CLKS may be provided in the first connector CNT1, the source board SPCB, the second connector CNT2, and the display panel 150. An example in which the clock signal line CLKL is branched and provided on the source board SPCB to smoothly transmit the clock signal to a first shift register 131a and a second shift register 131b respectively provided in left and right non-display regions NA of the display panel 150 may be described.

[0072] The display panel 150 may include a first shift register 131a, a second shift register 131b, a dummy generator 133, a first dummy pattern portion 134a, and a second dummy pattern portion 134b. The dummy generator 133 may solve a problem of radiation mismatch between dummy signals generated from the dummy pattern portions 134a and 134b and the clock signal output from the level shifter 135 and applied to the first shift register 131a and the second shift register 131b.

[0073] The pseudo generator 133 may include a current sensing circuit 133a, a phase inversion circuit 133b, and a current accumulation circuit 133c. The functions of each of the current sensing circuit 133a, the phase inversion circuit 133b, and the current accumulation circuit 133c may be referred to the first embodiment.

[0074] As Figure 10 and Figure 11 shown in, according to the second embodiment, the current sensing and phase inversion circuit 133a&133b may be integrated into one circuit. The current sensing and phase inversion circuit 133a&133b may sense the clock signal output from the level shifter 135 and applied to the first shift register 131a and the second shift register 131b to convert it into a current type, and may invert the phase to output an inverted current type.

[0075] The current sensing and phase inversion circuit 133a&133b may be implemented as a current mirror type. The current sensing and phase inversion circuit 133a&133b may include a first transistor FET1 and a second transistor FET2.

[0076] The first transistor FET1 may include a first electrode (source electrode) connected to the input terminal, a second electrode (drain electrode) connected to the output terminal, and a gate electrode connected to the output terminal and the gate electrode of the second transistor FET2. The second transistor FET2 may include a first electrode (source electrode) connected to the first pseudo pattern portion 134a or the second pseudo pattern portion 134b, a second electrode (drain electrode) connected to the ground terminal, and a gate electrode connected to the output terminal and the gate electrode of the first transistor FET1.

[0077] Hereinafter, the operation of outputting the first clock signal applied to the current sensing and phase inversion circuit 133a&133b as an inverted current type will be described.

[0078] The first clock signal CLK1 input in a voltage type may be generated as a first reference current Iref based on the operation of the first transistor FET1 and may be output through the first shift register 131a or the second shift register 131b.

[0079] The second transistor FET2 can operate in the same manner as the first transistor FET1, and can perform a sensing operation (current mirror operation) of generating a first mirror current Imr equal to the first reference current Iref through the second electrode and outputting it to the ground terminal. In addition, the second transistor FET2 can perform a phase inversion operation of generating a first inverted current Ips opposite to the first reference current Iref through the first electrode and outputting it to the first pseudo-pattern section 134a or the second pseudo-pattern section 134b. Contrary to the first transistor FET1, since the first electrode (source electrode) of the second transistor FET2 is connected to the first pseudo-pattern section 134a or the second pseudo-pattern section 134b, current can flow in the opposite direction to the sensed current, and thus the second transistor FET2 can generate a phase-inverted current.

[0080] As described above, the current sensing and phase inversion circuits 133a&133b can sense the current flowing in the clock signal through a current mirror, and can make the current flow in the opposite direction to the sensed current, thus phase-inverting the input current to output a phase-inverted current.

[0081] Hereinafter, as an example of applying the pseudo-generator 133 according to the second embodiment, the operation of generating a pseudo-signal corresponding to the clock signal output from the Figure 9 level shifter 135 shown will be described.

[0082] Figures 12 to 17 is an example view of applying the Figure 11 pseudo-generator and a view describing the input / output changes based thereon.

[0083] As Figure 9 , Figure 12 and Figure 13 shown, the level of the four-phase first clock signal G1 output from the timing controller 120 can be shifted upward by the level shifter 135 and thus can be converted into the first clock signals G1_CLK1 to G1_CLK4. Then, the first clock signals G1_CLK1 to G1_CLK4 can be applied to the current sensing and phase inversion circuits 133a&133b.

[0084] The first reference currents Iref1 to Iref4, the first mirror currents Imr1 to Imr4, and the first inverted currents Ips1 to Ips4 can be generated from the first clock signals G1_CLK1 to G1_CLK4 by the current sensing and phase inversion circuits 133a&133b. In addition, the first inverted currents Ips1 to Ips4 can be applied to the first pseudo-pattern section 134a or the second pseudo-pattern section 134b and then accumulated (Ipsum), thus generating a pseudo-signal (Pseudo).

[0085] As Figure 9, Figure 14 and Figure 15 As shown in Figure 14 and Figure 15 , the level of the five-phase second clock signal G2 output from the timing controller 120 can be shifted upward by the level shifter 135 and thus can be converted into second clock signals G2_CLK1 to G2_CLK5. Then, the second clock signals G2_CLK1 to G2_CLK5 can be applied to the current sensing and phase inversion circuits 133a&133b.

[0086] The 1'st reference currents Iref1' to Iref5', the 1'st mirror currents Imr1' to Imr5', and the 1'st inversion currents Ips1' to Ips5' can be generated from the second clock signals G2_CLK1 to G2_CLK5 by the current sensing and phase inversion circuits 133a&133b. In addition, the 1'st inversion currents Ips1' to Ips5' can be applied to the first pseudo-pattern part 134a or the second pseudo-pattern part 134b and then be accumulated (Ipsum'), and thus a pseudo signal (Pseudo) can be generated.

[0087] As Figure 9 , Figure 16 and Figure 17 As shown in Figure 9 , Figure 16 and Figure 17 , the level of the two-phase third clock signal EM output from the timing controller 120 can be shifted upward by the level shifter 135 and thus can be converted into third clock signals EM_CLK1 and EM_CLK2. Then, the third clock signals EM_CLK1 and EM_CLK2 can be applied to the current sensing and phase inversion circuits 133a&133b.

[0088] The 1'' reference currents Iref1'' and Iref2'', the 1'' mirror currents Imr1'' and Imr2'', and the 1'' inversion currents Ips1'' and Ips2'' can be generated from the third clock signals EM_CLK1 and EM_CLK2 by the current sensing and phase inversion circuits 133a&133b. In addition, the 1'' inversion currents Ips1'' and Ips2'' can be applied to the first pseudo-pattern part 134a or the second pseudo-pattern part 134b and then be accumulated (Ipsum''), and thus a pseudo signal (Pseudo) can be generated.

[0089] In Figure 12 , Figure 14 and Figure 16 Examples are illustrated in Figure 12 , Figure 14 and Figure 16 in which the current accumulation circuit is included in the first pseudo-pattern part 134a or the second pseudo-pattern part 134b (integrated structure of the current accumulation circuit and the pseudo-pattern part) and the corresponding current accumulation circuit is simply implemented in a straight line. However, the current accumulation circuit and the pseudo-pattern part can be implemented in various forms based on the characteristics of the signal (radiation), the material of the electrode or wire, the manufacturing process, and the peripheral circuit. Therefore, in Figure 12 , Figure 14 andFigure 16 In [the figure], the current accumulation circuit and the dummy pattern part are shown as straight lines to help understand current accumulation.

[0090] In addition, dummy signals can be used to cancel or minimize the electric fields that cause electromagnetic interference (EMI) in pulse-type signals (such as the first clock signals G1_CLK1 to G1_CLK4, the second clock signals G2_CLK1 to G2_CLK5, and the third clock signals EM_CLK1 and EM_CLK2) that repeat with a specific periodicity. Voltage-type dummy signals can be used, but problems of radiation mismatch may occur due to various reasons such as line load, driving environment, and peripheral circuits.

[0091] For example, the first shift register 131a and the second shift register 131b have a large load because they are connected to the sub-pixels included in the display area, but the first dummy pattern part 134a and the second dummy pattern part 134b have a small load because they are connected to the patterns included in the non-display area (occupying a relatively small area). Therefore, in the case of generating voltage-type dummy signals, problems of radiation mismatch may occur due to the mismatch in the consumed current caused by the load difference between the first shift register 131a and the second shift register 131b and the first dummy pattern part 134a and the second dummy pattern part 134b (which is due to the reduced efficiency of using dummy signals to cancel the electric field).

[0092] However, compared to voltage-type dummy signals, current-type dummy signals have strong robustness against the causes of signal variation. Therefore, when a current-type dummy signal is generated based on the dummy generator 133 according to the first embodiment and applied to the first dummy pattern part 134a and the second dummy pattern part 134b, the robustness against load difference and noise can be enhanced, and the electric fields that cause electromagnetic interference (EMI) can be canceled or minimized.

[0093] In addition, when the dummy signals corresponding to the clock signals are generated as current-type and at least one of the dummy signals is accumulated into one, an integrated design of the dummy pattern parts 134a and 134b can be performed, and the area occupied by the dummy pattern parts 134a and 134b can be reduced, thereby reducing the border area of the display panel.

[0094] Figures 18 to 20 It is a view for describing the electric field cancellation efficiency of the dummy generator according to the second embodiment.

[0095] Figure 18 It is a chart showing the results obtained by measuring the radiation amount of the clock signal applied to the shift register. Figure 19 It is a chart showing the results obtained by measuring the radiation amount of the dummy signal generated based on the dummy generator according to the second embodiment. Figure 20 It is a view showing byFigure 18 Application of the clock signal Figure 19 Chart of the result obtained by the dummy signal

[0096] By Figure 18 The chart of Figure 19 From the comparison between the chart of and the chart of, when the dummy generator according to the second embodiment is applied to the display device, the radiation amount of the clock signal applied to the shift register and the radiation amount of the dummy signal generated from the dummy generator can be adjusted to be almost similar to each other.

[0097] This is because, as shown in Figure 20 As a result of applying the dummy signal to the clock signal of Figure 18 Application of the clock signal Figure 19 the degree of matching between the two signals and the electric field cancellation efficiency are enhanced, and thus the radiation difference is reduced.

[0098] In addition, in the present disclosure, an example of generating a dummy signal only for the clock signal is illustrated and described. However, in addition to the clock signal, the dummy generator can also be applied to a pulse-type signal that repeats periodically, such as a multiplexer signal required for driving a display panel.

[0099] As described above, the present disclosure can solve the problem of radiation mismatch caused by the load difference between the shift register and the dummy pattern portion, can enhance the robustness to noise, and can cancel or minimize the electric field causing electromagnetic interference (EMI). In addition, the present disclosure can generate a current-type dummy signal corresponding to the clock signal, and can accumulate at least one of the dummy signals, thereby not only realizing the integrated design of the dummy pattern portion, but also reducing the area occupied by the dummy pattern portion, thereby reducing the border area of the display panel.

[0100] The effects according to the present disclosure are not limited to the above examples, and other special effects may be included in this application.

[0101] Although the present disclosure has been specifically shown and described with reference to the exemplary embodiments of the present disclosure, those of ordinary skill in the art will understand that various changes in form and detail can be made without departing from the spirit and scope of the present disclosure defined by the following claims.

Claims

1. A display device, comprising: a display panel configured to display an image; a shift register configured to output a gate signal to be applied to the display panel based on the periodic signal output from the level shifter; a pseudo generator configured to sense the periodic signal to convert it into a current and invert the phase to output a pseudo signal of an inverted current type; and A dummy pattern portion is provided on the display panel, and includes a pattern to which the dummy signal is applied. 2 . The display device according to claim 1 , wherein the dummy pattern part includes a pattern that cancels an electric field generated by the periodic signal based on the dummy signal.

3. The display device according to claim 1, wherein the dummy generator comprises: a current sensing circuit configured to sense the periodic signal; and A phase inversion circuit is configured to invert the phase of the sensed current to output a pseudo signal of the inverted current type.

4. The display device according to claim 1, wherein the dummy generator comprises a current sensing and phase inversion circuit, the current sensing and phase inversion circuit comprising: a first transistor configured to sense the periodic signal to convert it into a current; and a second transistor configured to operate identically to the first transistor and to invert a phase of the sensed current to output a pseudo signal of the inverted current type. 5 . The display device according to claim 4 , wherein the first transistor and the second transistor are configured as a current mirror type.

6. The display device according to claim 4, wherein the first transistor comprises a first electrode connected to an input terminal, a second electrode connected to an output terminal, and a gate electrode connected to the output terminal and a gate electrode of the second transistor, and The second transistor includes a first electrode connected to the dummy pattern portion, a second electrode connected to a ground terminal, and a gate electrode connected to the output terminal and a gate electrode of the first transistor. 7 . The display device according to claim 3 , wherein the pseudo generator further comprises a current accumulation circuit configured to accumulate one or more inverted currents to generate an accumulated current type pseudo signal. 8 . The display device of claim 1 , wherein the dummy generator and the dummy pattern part are disposed in a non-display area of ​​the display panel.

9. The display device according to claim 1, wherein the periodic signal comprises a clock signal.

10. A pseudo signal generator, comprising: a pseudo generator configured to sense a periodic signal to convert it into a current and invert a phase to output a pseudo signal of an inverted current type; and A dummy pattern section includes a pattern that cancels an electric field generated by the periodic signal based on the dummy signal.

11. The pseudo signal generator according to claim 10, wherein the pseudo generator comprises: a first transistor configured to sense the periodic signal to convert it into a current; and a second transistor configured to operate identically to the first transistor and to invert a phase of the sensed current to output a pseudo signal of the inverted current type.

12. The pseudo signal generator according to claim 11, wherein the first transistor comprises a first electrode connected to an input terminal, a second electrode connected to an output terminal, and a gate electrode connected to the output terminal and a gate electrode of the second transistor, and The second transistor includes a first electrode connected to the dummy pattern portion, a second electrode connected to a ground terminal, and a gate electrode connected to the output terminal and a gate electrode of the first transistor. 13 . The pseudo signal generator according to claim 10 , wherein at least one of the pseudo generator and the pseudo pattern section comprises a current accumulation circuit configured to accumulate one or more inverted currents to generate an accumulated current type pseudo signal.

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