Pixel circuit and driving method thereof, display substrate and display device

Abstract

A pixel circuit comprises a driving sub-circuit (11), a data writing sub-circuit (13), a compensation sub-circuit (12), a coupling sub-circuit (14) and a first control sub-circuit (15). The coupling sub-circuit (14) is coupled with the first node (N1) and the third node (N3). The first control sub-circuit (15) is configured to write a first reference voltage signal provided by a first reference voltage line (REF1) to the third node (N3) under the control of the first control line (S1) after the data write-in sub-circuit (13) writes the data signal into the third node (N3), so that the data signal is coupled to the first node (N1) through the coupling sub-circuit (14).

Description

[0001] This application is a divisional application of the application with the application date of July 30, 2024, application number 202480001490.9, and invention title "Pixel Circuit and Its Driving Method, Display Substrate and Display Device". Technical Field

[0002] This document relates to, but is not limited to, the field of display technologies, and particularly refers to a pixel circuit and its driving method, a display substrate, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) have the advantages of being ultra-thin, having a large viewing angle, being self-luminous, having high brightness, having continuously adjustable emission colors, low cost, fast response speed, low power consumption, a wide operating temperature range, and being flexible for display. They have gradually become the next-generation display technology with great development prospects and have received increasing attention. According to different driving methods, OLEDs can be divided into two types: passive matrix driving (PM) type and active matrix driving (AM) type. AMOLEDs are current-driven devices, and each sub-pixel is controlled by an independent thin film transistor (TFT), and each sub-pixel can be continuously and independently driven to emit light. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the scope of protection of the claims.

[0005] This embodiment provides a pixel circuit and its driving method, a display substrate, and a display device.

[0006] On the one hand, this embodiment provides a pixel circuit, including: a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a coupling sub-circuit, and a first control sub-circuit. Among them, the driving sub-circuit is coupled to the first node, the fourth node, and the fifth node, and is configured to provide a driving signal to the fourth node under the control of the first node. The compensation sub-circuit is coupled to the second scan line, the first node, and the fourth node, and is configured to turn on the first node and the fourth node under the control of the second scan line, so that the threshold voltage of the driving sub-circuit is written into the first node. The coupling sub-circuit is coupled to the first node and the third node. The data writing sub-circuit is coupled to the first scan line, the data line, and the third node, and is configured to provide the data signal on the data line to the third node under the control of the first scan line. The first control sub-circuit is coupled to the first control line, the third node, and the first reference voltage line, and is configured to write the first reference voltage signal provided by the first reference voltage line to the third node under the control of the first control line after the data writing sub-circuit writes the data signal to the third node, so that the data signal is coupled to the first node through the coupling sub-circuit.

[0007] In some exemplary embodiments, the duration for the data writing sub-circuit to write the data signal to the third node is less than the duration for the compensation sub-circuit to write the threshold voltage of the driving sub-circuit to the first node; the start time for the data writing sub-circuit to write the data signal to the third node is later than the start time for the compensation sub-circuit to write the threshold voltage of the driving sub-circuit to the first node.

[0008] In some exemplary embodiments, the valid level signal provided by the second scan line is configured to control the compensation sub-circuit to write the threshold voltage of the driving sub-circuit to the first node. The end time for the data writing sub-circuit to write the data signal to the third node is a first duration from the start time of the valid level signal provided by the second scan line, and the end time for the data writing sub-circuit to write the data signal to the third node is a second duration from the end time of the valid level signal provided by the second scan line; the second duration is less than the first duration.

[0009] In some exemplary embodiments, the valid level signal provided by the second scan line is configured to control the compensation sub-circuit to write the threshold voltage of the driving sub-circuit to the first node. The valid level signal provided by the second scan line includes the following three equal division stages: the first signal stage, the second signal stage, and the third signal stage, and the start time of the valid level signal provided by the first scan line is after the first signal stage.

[0010] In some exemplary embodiments, the coupling sub-circuit includes: a first coupling sub-circuit and a second coupling sub-circuit; the first coupling sub-circuit is coupled to the first node and the second node, and the second coupling sub-circuit is coupled to the second node and the third node. The pixel circuit further includes: a second control sub-circuit, coupled to a second control line, the second node, and a first voltage terminal, configured to conduct the second node and the first voltage terminal under the control of the second control line, such that the second coupling sub-circuit stores a data signal written to the third node.

[0011] In some exemplary embodiments, the first coupling sub-circuit includes: a first capacitor; a first electrode of the first capacitor is coupled to the first node, and a second electrode of the first capacitor is coupled to the second node; the second coupling sub-circuit includes: a second capacitor; a first electrode of the second capacitor is coupled to the second node, and a second electrode of the second capacitor is coupled to the third node. The compensation sub-circuit includes: a compensation transistor, a gate of the compensation transistor is coupled to the second scan line, a first pole of the compensation transistor is coupled to the fourth node, and a second pole of the compensation transistor is coupled to the first node. The second control sub-circuit includes: a second control transistor, a gate of the second control transistor is coupled to the second control line, a first pole of the second control transistor is coupled to the first voltage terminal, the first voltage terminal is coupled to a first power supply line, and a second pole of the second control transistor is coupled to the second node.

[0012] In some exemplary embodiments, the compensation transistor and the second control transistor are oxide thin film transistors, and the second control line and the second scan line are configured to provide the same signal.

[0013] In some exemplary embodiments, the data writing sub-circuit includes: a data writing transistor, a gate of the data writing transistor is coupled to the first scan line, a first pole of the data writing transistor is coupled to the data line, and a second pole of the data writing transistor is coupled to the third node. The first control sub-circuit includes: a first control transistor, a gate of the first control transistor is coupled to the first control line, a first pole of the first control transistor is coupled to the first reference voltage line, and a second pole of the first control transistor is coupled to the third node. The compensation sub-circuit includes: a compensation transistor, a gate of the compensation transistor is coupled to the second scan line, a first pole of the compensation transistor is coupled to the fourth node, and a second pole of the compensation transistor is coupled to the first node.

[0014] In some exemplary embodiments, the data writing transistor and the first control transistor have the same transistor type, which is different from the transistor type of the compensation transistor. The first control line and the second scan line are configured to provide the same signal.

[0015] In some exemplary embodiments, the pixel circuit further includes: a first light emission control sub-circuit, coupled to a first light emission control line, a first power supply line, and the fifth node, configured to write a first power supply signal provided by the first power supply line to the fifth node under the control of the first light emission control line. The first control line and the first light emission control line are configured to provide the same signal.

[0016] In some exemplary embodiments, the data writing transistor and the first control transistor have different transistor types, and the data writing transistor and the compensation transistor have the same transistor type.

[0017] In some exemplary embodiments, the first control line and the first scan line are configured to transmit the same signal.

[0018] In some exemplary embodiments, the pixel circuit further includes: a second light emission control sub-circuit and a fourth reset sub-circuit. The second light emission control sub-circuit is coupled to a second light emission control line, the fourth node, and the sixth node, and is configured to conduct the fourth node and the sixth node under the control of the second light emission control line, and the sixth node is coupled to a first electrode of the light emitting element. The fourth reset sub-circuit is coupled to the third node, the first reference voltage line, and a third reset control line, and is configured to write a first reference voltage signal provided by the first reference voltage line to the third node under the control of the third reset control line.

[0019] In some exemplary embodiments, the first control line and the second light emission control line are configured to provide the same signal.

[0020] In some exemplary embodiments, the pixel circuit further includes: a first reset sub-circuit and a second reset sub-circuit. The first reset sub-circuit is coupled to a first reset control line, a first reset voltage line, and the fourth node, and is configured to write a first reset voltage signal provided by the first reset voltage line to the fourth node under the control of the first reset control line; alternatively, the first reset sub-circuit is coupled to the first reset control line, the first reset voltage line, and the first node, and is configured to write a first reset voltage signal provided by the first reset voltage line to the first node under the control of the first reset control line. The second reset sub-circuit is coupled to a second reset control line, a second reset voltage line, and the sixth node, and is configured to write a second reset voltage signal provided by the second reset voltage line to the sixth node under the control of the second reset control line, and the sixth node is coupled to a first electrode of the light-emitting element.

[0021] In some exemplary embodiments, the pixel circuit further includes: a third reset sub-circuit, coupled to the second reset control line, a second reference voltage line, and the fifth node, and configured to write a second reference voltage signal provided by the second reference voltage line to the fifth node under the control of the second reset control line.

[0022] In some exemplary embodiments, the pixel circuit further includes: a third capacitor, a first electrode of the third capacitor is coupled to a first bias signal line, and a second electrode of the third capacitor is coupled to the first node or the second node.

[0023] In some exemplary embodiments, the pixel circuit further includes: a fourth capacitor, a first electrode of the fourth capacitor is coupled to a second bias signal line, and a second electrode of the fourth capacitor is coupled to the fourth node or the fifth node.

[0024] On the other hand, the present embodiment provides a driving method for a pixel circuit, which is applied to the pixel circuit as described above. The driving method includes: the compensation sub-circuit conducts the first node and the fourth node under the control of the second scan line, so that the threshold voltage of the driving sub-circuit is written into the first node; the data writing sub-circuit writes a data signal provided by the data line into the third node under the control of the first scan line; the first control sub-circuit writes a first reference voltage signal provided by the first reference voltage line to the third node under the control of the first control line, so that the data signal is coupled to the first node through the coupling sub-circuit; the driving sub-circuit provides a driving signal to the fourth node under the control of the first node.

[0025] On the other hand, this embodiment provides a display substrate, including: a plurality of sub-pixels and at least one first scan driving circuit. At least one of the plurality of sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light. The first scan driving circuit includes: a plurality of first scan driving units. The pixel circuit is the pixel circuit as described above. The nth-level first scan driving unit is configured to provide a first scan signal to the pixel circuits of the sub-pixels in the nth row; n is an integer greater than 0. Among them, the (2i - 1)th-level first scan driving unit is cascaded with the (2i + 1)th-level first scan driving unit, and the 2ith-level first scan driving unit is cascaded with the (2i + 2)th-level first scan driving unit, where i is an integer greater than 0.

[0026] In some exemplary embodiments, the display substrate further includes: a first light-emitting driving circuit, and the first light-emitting driving circuit includes a plurality of cascaded first light-emitting driving units. The nth-level first light-emitting driving unit is configured to provide a first light-emitting control signal to the pixel circuits of the sub-pixels in the nth row; or, configured to provide a first light-emitting control signal to the pixel circuits of the sub-pixels in the (2n - 1)th row and the 2nth row.

[0027] In some exemplary embodiments, the display substrate further includes: a second scan driving circuit and a second light-emitting driving circuit. The second scan driving circuit includes a plurality of cascaded second scan driving units. The second light-emitting driving circuit includes a plurality of cascaded second light-emitting driving units. The nth-level second scan driving circuit is configured to provide a second scan signal to the pixel circuits of the sub-pixels in the (2n - 1)th row and the 2nth row. The nth-level second light-emitting driving circuit is configured to provide a second light-emitting control signal to the pixel circuits of the sub-pixels in the (2n - 1)th row and the 2nth row. Among them, the second scan driving circuit and the second light-emitting driving circuit are located on the same side of the plurality of sub-pixels along the row direction of the sub-pixels.

[0028] In some exemplary embodiments, the display substrate further includes: a first reset driving circuit and a second reset driving circuit. The first reset driving circuit includes a plurality of cascaded first reset driving units. The second reset driving circuit includes a plurality of cascaded second reset driving units. The nth-level first reset driving circuit is configured to provide a first reset control signal to the pixel circuits of the sub-pixels in the (2n - 1)th row and the 2nth row. The nth-level second reset driving circuit is configured to provide a second reset control signal to the pixel circuits of the sub-pixels in the (2n - 1)th row and the 2nth row. Among them, the first reset driving circuit and the second reset driving circuit are located on different sides of the plurality of sub-pixels along the row direction of the sub-pixels.

[0029] On the other hand, this embodiment provides a display device, including the display substrate as described above.

[0030] Other aspects will be apparent upon reading and understanding the accompanying drawings and the detailed description. Description of the Drawings

[0031] The accompanying drawings are used to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0032] Figure 1 Is an equivalent circuit diagram of a pixel circuit; Figure 2 Is a schematic structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Figure 3 Is another schematic structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Figure 4 Is another schematic structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Figure 5 Is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Figure 6 Is Figure 5 The working timing diagram of the pixel circuit shown; Figure 7 Is a schematic diagram of the driving architecture of a pixel circuit according to at least one embodiment of the present disclosure; Figure 8 Is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Figure 9 Is Figure 8 The working timing diagram of the pixel circuit shown; Figure 10 Is another schematic diagram of the driving architecture of a pixel circuit according to at least one embodiment of the present disclosure; Figure 11 Is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Figure 12 Is Figure 11 The working timing diagram of the pixel circuit shown; Figure 13 Is another schematic diagram of the driving architecture of a pixel circuit according to at least one embodiment of the present disclosure; Figure 14 Is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Figure 15 Is Figure 14 The working timing diagram of the pixel circuit shown; Figure 16 Is another schematic structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Figure 17Another equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure; Figure 18 is Figure 17 The timing diagram of the pixel circuit shown; Figure 19 Another equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure; Figure 20 is Figure 19 The timing diagram of the pixel circuit shown; Figure 21 Another structural schematic diagram of the pixel circuit according to at least one embodiment of the present disclosure; Figure 22 Another equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure; Figure 23 Another equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure; Figure 24 is Figure 23 The timing diagram of the pixel circuit shown; Figure 25 Another driving architecture schematic diagram of the pixel circuit according to at least one embodiment of the present disclosure; Figure 26 Another equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure; Figure 27 Another equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure; Figure 28 is Figure 27 The timing diagram of the pixel circuit shown; Figure 29 Another equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure; Figure 30 The flowchart of the driving method of the pixel circuit according to at least one embodiment of the present disclosure; Figure 31 The schematic diagram of the display device according to at least one embodiment of the present disclosure. Detailed implementation manners

[0033] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The implementation manners can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the manners and contents can be transformed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following implementation manners. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined arbitrarily with each other.

[0034] In the drawings, for clarity, the size of one or more constituent elements, the thickness of a layer, or a region may be exaggerated. Thus, one aspect of the present disclosure is not necessarily limited to such dimensions, and the shape and size of one or more components in the drawings do not reflect the true scale. Further, the drawings schematically show ideal examples, and one aspect of the present disclosure is not limited to the shapes or values shown in the drawings, etc.

[0035] Ordinal numbers such as "first", "second", "third", etc. in this specification are provided to avoid confusion of constituent elements and are not intended to limit in terms of quantity. "A plurality of" in the present disclosure means two or more in number.

[0036] In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of constituent elements with reference to the drawings, and are merely for facilitating the description of this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation on the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of the described constituent elements. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the circumstances.

[0037] In this specification, unless otherwise clearly specified and limited, the terms "mounted", "connected", "coupled" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or a connection; it may be a direct connection, or an indirect connection through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the meanings of the above terms in the present disclosure can be understood according to the circumstances. Among them, "coupled" may include "electrically connected", and "electrically connected" may include the case where constituent elements are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transmit electrical signals between the constituent elements to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0038] In this specification, a transistor refers to an element including at least three terminals: a gate (gate electrode), a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region where current mainly flows.

[0039] In this specification, the first pole may be the drain, the second pole may be the source, or the first pole may be the source and the second pole may be the drain. Additionally, the gate may also be referred to as the control pole. In cases where transistors with opposite polarities are used or the direction of current flow changes during circuit operation, etc., the functions of the "source" and "drain" sometimes swap with each other. Therefore, in this specification, the "source" and "drain" can be swapped with each other.

[0040] The terms "about" and "substantially" in this specification mean that the boundaries are not strictly defined and allow for cases within the process and measurement errors. In this disclosure, "the same" includes cases where the numerical difference is within 10%, such as cases where the numerical difference is within 5%.

[0041] In this disclosure, the effective level signal includes the level signal for turning on the transistor. For example, the effective level signal for turning on a P-type transistor is a low-level signal, and the effective level signal for turning on an N-type transistor is a high-level signal.

[0042] Figure 1 It is an equivalent circuit diagram of a pixel circuit. As Figure 1 shown, the pixel circuit includes seven transistors (i.e., transistors T01 to T07) and a storage capacitor Cst. The transistor types of the seven transistors are the same. For example, all seven transistors are P-type transistors. Among them, the gates of transistors T02 and T04 are both connected to the first gate line GATE1, the gate of transistor T01 is connected to the second gate line GATE2, the gate of transistor T07 is connected to the third gate line GATE3, and the gates of transistors T05 and T06 are both connected to the emission control line EML. In this pixel circuit, the data voltage provided by the data signal line DATA can drive transistor T03 to write the data voltage and compensate for the threshold voltage Vth. During the data writing stage, transistors T02 and T04 use the same scan signal provided by the first gate line GATE1 to achieve data writing and threshold voltage compensation.

[0043] However, as the resolution and frequency of the display device increase, the above-mentioned scheme for compensating the threshold voltage using the data voltage will encounter a driving bottleneck. For example, as the display refresh rate increases, the data writing duration (1H) of a single-row pixel circuit within one frame will gradually decrease. As the data writing duration decreases, phenomena such as difficult data writing and insufficient threshold voltage compensation will occur.

[0044] This embodiment provides a pixel circuit, its driving method, a display substrate, and a display device, which can improve the compensation effect of the threshold voltage, thereby improving the display performance.

[0045] Figure 2 It is a schematic structural diagram of the pixel circuit of at least one embodiment of the present disclosure. In some examples, as Figure 2As shown in the figure, the pixel circuit of this embodiment may at least include: a driving sub-circuit 11, a data writing sub-circuit 13, a compensation sub-circuit 12, a coupling sub-circuit 14, and a first control sub-circuit 15. Among them, the driving sub-circuit 11 is coupled to the first node N1, the fourth node N4, and the fifth node N5, and is configured to provide a driving signal to the fourth node N4 under the control of the first node N1. The compensation sub-circuit 12 is coupled to the second scan line GL2, the first node N1, and the fourth node N4, and is configured to conduct the first node N1 and the fourth node N4 under the control of the second scan line GL2, so that the threshold voltage of the driving sub-circuit 11 is written into the first node N1. The coupling sub-circuit 14 is coupled to the first node N1 and the third node N3. The data writing sub-circuit 13 is coupled to the first scan line GL1, the data line DL, and the third node N3, and is configured to provide the data signal on the data line DL to the third node N3 under the control of the first scan line GL1. The first control sub-circuit 15 is coupled to the first control line S1, the third node N3, and the first reference voltage line REF1, and is configured to write the first reference voltage signal provided by the first reference voltage line REF1 to the third node N3 under the control of the first control line S1 after the data writing sub-circuit 13 writes the data signal to the third node N3, so that the data signal is coupled to the first node N1 through the coupling sub-circuit 14.

[0046] For the pixel circuit provided in this embodiment, by setting the coupling sub-circuit, the data writing process and the threshold voltage compensation process can be separated, which is beneficial to improving the compensation effect of the threshold voltage, and thus beneficial to improving the display performance.

[0047] In some examples, the duration for the data writing sub-circuit 13 to write the data signal to the third node N3 may be less than the duration for the compensation sub-circuit 12 to write the threshold voltage of the driving sub-circuit 11 to the first node N1. The start time for the data writing sub-circuit 13 to write the data signal to the third node N3 may be later than the start time for the compensation sub-circuit 12 to write the threshold voltage of the driving sub-circuit 11 to the first node N1. This example can separately control the data writing process and the threshold voltage compensation process. By increasing the compensation duration of the threshold voltage, it is beneficial to improving the compensation effect of the threshold voltage, and thus beneficial to improving the uniformity of the screen display. Moreover, the writing time of the data signal being later than the writing time of the threshold voltage can be beneficial to ensuring the validity of the data signal.

[0048] In some examples, the first scan line GL1 can be configured to provide a first scan signal, and the second scan line GL2 can be configured to provide a second scan signal. The first scan signal can be configured to control the data writing sub-circuit 13 to write a data signal into the third node N3, and the second scan signal can be configured to control the compensation sub-circuit 12 to write the threshold voltage of the driving sub-circuit 11 into the first node N1. The first scan signal can be different from the second scan signal. For example, the duration of the active level signal of the first scan signal can be less than the duration of the active level signal of the second scan signal. The first scan signal and the second scan signal can be provided by different scan driving circuits; for example, the first scan signal can be provided by the first scan driving circuit, and the second scan signal can be provided by the second scan driving circuit. In this example, by separating the data signal writing and the threshold voltage compensation phases, the compensation duration for the threshold voltage can be increased, ensuring sufficient threshold voltage compensation time and facilitating the improvement of the threshold voltage compensation effect.

[0049] In some examples, the active level signal provided by the second scan line GL2 can be configured to control the compensation sub-circuit 12 to write the threshold voltage of the driving sub-circuit 11 into the first node N1. The end time of the data writing sub-circuit 13 writing the data signal into the third node N3 is the first duration from the start time of the active level signal provided by the second scan line GL2, and the end time of the data writing sub-circuit 13 writing the data signal into the third node N3 is the second duration from the end time of the active level signal provided by the second scan line GL2; the second duration is less than the first duration. In this example, the data writing process can be carried out in the second half of the threshold voltage compensation phase, which can increase the compensation duration for the threshold voltage, ensuring sufficient threshold voltage compensation time and facilitating the improvement of the threshold voltage compensation effect.

[0050] In some examples, the active level signal provided by the second scan line GL2 can be configured to control the compensation sub-circuit 12 to write the threshold voltage of the driving sub-circuit 11 into the first node N1. The active level signal provided by the second scan line GL2 can include the following three equal division phases: the first signal phase, the second signal phase, and the third signal phase, and the start time of the active level signal provided by the first scan line GL1 can be after the first signal phase. In this example, the data writing process can be carried out in the second half of the threshold voltage compensation phase, which can increase the compensation duration for the threshold voltage, ensuring sufficient threshold voltage compensation time and facilitating the improvement of the threshold voltage compensation effect.

[0051] Figure 3 Another structural schematic diagram of the pixel circuit according to at least one embodiment of the present disclosure. In some examples, such as Figure 3As shown, the pixel circuit of this embodiment may at least include: a driving sub-circuit 11, a data writing sub-circuit 13, a compensation sub-circuit 12, a coupling sub-circuit 14, a first control sub-circuit 15, and a second control sub-circuit 16.

[0052] In some examples, the coupling sub-circuit 14 may include: a first coupling sub-circuit 141 and a second coupling sub-circuit 142. The first coupling sub-circuit 141 is coupled to a first node N1 and a second node N2, and the second coupling sub-circuit 142 is coupled to the second node N2 and a third node N3. The second control sub-circuit 16 is coupled to a second control line S2, the second node N2, and a first voltage terminal VL, and is configured to conduct the second node N2 and the first voltage terminal VL under the control of the second control line S2, so that the second coupling sub-circuit 142 stores the data signal written to the third node N3. For the remaining structure of the pixel circuit in this example, reference may be made to the description of the foregoing embodiment, and thus it will not be elaborated herein.

[0053] In some examples, the first control line S1 may be configured to provide a first control signal, and the second control line S2 may be configured to provide a second control signal. The first control signal may be configured to control writing a first reference voltage signal to the third node N3, and the second control signal may be configured to control writing the voltage signal provided by the first voltage terminal VL to the second node N2. The second control signal may be the same as the second scan signal. The first control signal may be the same as or different from the second control signal. For example, the duration of the active level signal of the first control signal may be greater than or equal to the duration of the active level signal of the second control signal. In some examples, the first control signal, the second control signal, and the second scan signal may be the same. By using the first control signal provided by the first control line S1 to control the potential of the third node N3 in this example, the leakage of the third node can be improved.

[0054] Figure 4 It is another schematic structural diagram of the pixel circuit of at least one embodiment of the present disclosure. In some examples, as Figure 4 shown, the pixel circuit of this embodiment may include: a driving sub-circuit 11, a compensation sub-circuit 12, a data writing sub-circuit 13, a first coupling sub-circuit 141, a second coupling sub-circuit 142, a first control sub-circuit 15, a second control sub-circuit 16, a first light-emitting control sub-circuit 21, a second light-emitting control sub-circuit 22, a first reset sub-circuit 23, a second reset sub-circuit 24, and a third reset sub-circuit 25.

[0055] In some examples, the first light-emitting control sub-circuit 21 is coupled to the first light-emitting control line EM1, the first power supply line VDD, and the fifth node N5, and is configured to write the first power supply signal provided by the first power supply line VDD to the fifth node N5 under the control of the first light-emitting control line EM1. The second light-emitting control sub-circuit 22 is coupled to the second light-emitting control line EM2, the fourth node N4, and the sixth node N6, and is configured to conduct the fourth node N4 and the sixth node N6 under the control of the second light-emitting control line EM2. The first reset sub-circuit 23 is coupled to the first reset control line RST1, the first reset voltage line INIT1, and the fourth node N4, and is configured to write the first reset voltage signal provided by the first reset voltage line INIT1 to the fourth node N4 under the control of the first reset control line RST1. The second reset sub-circuit 24 is coupled to the second reset control line RST2, the second reset voltage line INIT2, and the sixth node N6, and is configured to write the second reset voltage signal provided by the second reset voltage line INIT2 to the sixth node N6 under the control of the second reset control line RST2. The third reset sub-circuit 25 is coupled to the second reset control line RST2, the second reference voltage line REF2, and the fifth node N5, and is configured to write the second reference voltage provided by the second reference voltage line REF2 to the fifth node N5 under the control of the second reset control line RST2. The first electrode of the light-emitting element is coupled to the sixth node N6, and the second electrode of the light-emitting element is coupled to the second power supply line VSS. For the remaining structure of the pixel circuit in this example, reference may be made to the description of the foregoing embodiments, and thus it will not be elaborated herein.

[0056] In some examples, the light-emitting element may be an organic light-emitting diode (OLED). The first electrode of the light-emitting element may be an anode, and the second electrode may be a cathode. However, this embodiment is not limited thereto.

[0057] In some examples, the second reset sub-circuit 24 resets the sixth node N6, which can eliminate the leakage current of the second light-emitting control sub-circuit 22, can prevent the light-emitting element from being affected by the leakage current and emitting light in the dark state, and can improve the display quality; moreover, it can eliminate the residual positive charges on the surface of the first electrode of the light-emitting element and can improve the lifespan of the light-emitting element. The third reset sub-circuit 25 can write the second reference voltage to the fifth node N5 to reset the fifth node N5. The first reset sub-circuit 23 can reset the fourth node N4.

[0058] In some examples, the first light emission control line EM1 can be configured to provide a first light emission control signal, and the second light emission control line EM2 can be configured to provide a second light emission control signal. The first light emission control signal can be configured to control the first light emission control sub-circuit 21 to write a first power signal to the fifth node N5, and the second light emission control signal can be configured to control the second light emission control sub-circuit 22 to turn on the fourth node N4 and the sixth node N6 to provide a driving signal to the light-emitting element, so that the light-emitting element emits light. The first light emission control signal can be different from the second light emission control signal. For example, the first control signal can be the same as the first light emission control signal, or the first control signal can be the same as the second light emission control signal. The first light emission control signal and the second light emission control signal can be provided by different light emission driving circuits; for example, the first light emission control signal can be provided by the first light emission driving circuit, and the second light emission control signal can be provided by the second light emission driving circuit.

[0059] In some examples, the first reset control line RST1 can be configured to provide a first reset control signal, and the second reset control line RST2 can be configured to provide a second reset control signal. The first reset control signal can be configured to control the first reset sub-circuit 23 to reset the fourth node N4, and the second reset control signal can be configured to control the second reset sub-circuit 24 to reset the sixth node N6, and control the third reset sub-circuit 25 to reset the fifth node N5. The first reset control signal can be different from the second reset control signal. The first reset control signal and the second reset control signal can be provided by different reset driving circuits; for example, the first reset control signal can be provided by the first reset driving circuit, and the second reset control signal can be provided by the second reset driving circuit.

[0060] In some examples, the first power supply line VDD can continuously provide a constant high-level signal. For example, the first power supply line VDD can provide a first power signal. The second power supply line VSS can continuously provide a constant low-level signal. For example, the second power supply line VSS can provide a second power signal. The first power signal can be greater than the second power signal.

[0061] In some examples, the first voltage terminal VL can be coupled to a trace that provides a voltage stabilizing signal for stabilizing the potential of the second node N2. For example, the first voltage terminal VL can be coupled to the first power supply line VDD.

[0062] In some examples, the first reference voltage line REF1 can be configured to provide a first reference voltage signal, and the second reference voltage line REF2 can be configured to provide a second reference voltage signal. The first reference voltage signal and the second reference voltage signal can be different. For example, both the first reference voltage signal and the second reference voltage signal can be less than the first power signal.

[0063] In some examples, the first reset voltage line INIT1 can be configured to provide a first reset voltage signal, and the second reset voltage line INIT2 can be configured to provide a second reset voltage signal. The first reset voltage signal and the second reset voltage signal can be the same or different. This embodiment does not limit this.

[0064] Figure 5 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 5 shown, the driving sub-circuit 11 may include: a driving transistor T3; the compensation sub-circuit 12 may include: a compensation transistor T2; the data writing sub-circuit 13 may include: a data writing transistor T4; the first coupling sub-circuit 141 may include: a first capacitor C1; the second coupling sub-circuit 142 may include: a second capacitor C2; the first control sub-circuit 15 may include: a first control transistor T10; the second control sub-circuit 16 may include: a second control transistor T9; the first light-emitting control sub-circuit 21 may include: a first light-emitting control transistor T5; the second light-emitting control sub-circuit 22 may include: a second light-emitting control transistor T6; the first reset sub-circuit 23 may include: a first reset transistor T1; the second reset sub-circuit 24 may include: a second reset transistor T7; the third reset sub-circuit 25 may include: a third reset transistor T8.

[0065] In some examples, as Figure 5As shown, the gate of driving transistor T3 is coupled to the first node N1, the first pole of driving transistor T3 is coupled to the fifth node N5, and the second pole of driving transistor T3 is coupled to the fourth node T4. The gate of compensation transistor T2 is coupled to the second scan line GL2, the first pole of compensation transistor T2 is coupled to the fourth node N4, and the second pole of compensation transistor T2 is coupled to the first node N1. The gate of data writing transistor T4 is coupled to the first scan line GL1, the first pole of data writing transistor T4 is coupled to the data line DL, and the second pole of data writing transistor T4 is coupled to the third node N3. The first electrode of the first capacitor C1 is coupled to the first node N1, and the second electrode of the first capacitor C1 is coupled to the second node N2. The first electrode of the second capacitor C2 is coupled to the second node N2, and the second electrode of the second capacitor C2 is coupled to the third node N3. The gate of the second control transistor T9 is coupled to the second control line S2, the first pole of the second control transistor T9 is coupled to the first power supply line VDD, that is, the first voltage terminal is coupled to the first power supply line VDD, and the second pole of the second control transistor T9 is coupled to the second node N2. The gate of the first control transistor T10 is coupled to the first control line S1, the first pole of the first control transistor T10 is coupled to the first reference voltage line REF1, and the second pole of the first control transistor T10 is coupled to the third node N3. The gate of the first light-emitting control transistor T5 is coupled to the first light-emitting control line EM1, the first pole of the first light-emitting control transistor T5 is coupled to the first power supply line VDD, and the second pole of the first light-emitting control transistor T5 is coupled to the fifth node N5. The gate of the second light-emitting control transistor T6 is coupled to the second light-emitting control line EM2, the first pole of the second light-emitting control transistor T6 is coupled to the fourth node N4, and the second pole of the second light-emitting control transistor T6 is coupled to the sixth node N6. The gate of the first reset transistor T1 is coupled to the first reset control line RST1, the first pole of the first reset transistor T1 is coupled to the first reset voltage line INIT1, and the second pole of the first reset transistor T1 is coupled to the fourth node N4. The gate of the second reset transistor T7 is coupled to the second reset control line RST2, the first pole of the second reset transistor T7 is coupled to the second reset voltage line INIT2, and the second pole of the second reset transistor T7 is coupled to the sixth node N6. The gate of the third reset transistor T8 is coupled to the second reset control line RST2, the first pole of the third reset transistor T8 is coupled to the second reference voltage line REF2, and the second pole of the third reset transistor T8 is coupled to the fifth node N5. The first electrode of the light-emitting element EL is coupled to the sixth node N6, and the second electrode of the light-emitting element EL is coupled to the second power supply line VSS.

[0066] In some examples, the first node N1 is the connection point of the first capacitor C1, the compensation transistor T2, and the driving transistor T3. The second node N2 is the connection point of the first capacitor C1, the second capacitor C2, and the second control transistor T9. The third node N3 is the connection point of the second capacitor C2, the data writing transistor T4, and the first control transistor T10. The fourth node N4 is the connection point of the first reset transistor T1, the compensation transistor T2, the driving transistor T3, and the second light-emitting control transistor T6. The fifth node N5 is the connection point of the first light-emitting control transistor T5, the third reset transistor T8, and the driving transistor T3. The sixth node N6 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7, and the light-emitting element EL.

[0067] Figure 5 An exemplary structure of the driving sub-circuit 11, the compensation sub-circuit 12, the data writing sub-circuit 13, the first coupling sub-circuit 141, the second coupling sub-circuit 142, the first control sub-circuit 15, the second control sub-circuit 16, the first light-emitting control sub-circuit 21, the second light-emitting control sub-circuit 22, the first reset sub-circuit 23, the second reset sub-circuit 24, and the third reset sub-circuit 25 is shown. It is easy for those skilled in the art to understand that the implementation manners of the above sub-circuits are not limited thereto, as long as their functions can be realized.

[0068] In some examples, as Figure 5 shown, the compensation transistor T2 and the second control transistor T9 can be N-type thin-film transistors, for example, oxide thin-film transistors can be used; the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, the third reset transistor T8, and the first control transistor T10 can be P-type thin-film transistors, for example, low-temperature polycrystalline silicon thin-film transistors can be used. The active layer of the low-temperature polycrystalline silicon thin-film transistor can use low-temperature poly-silicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin-film transistor can use oxide semiconductor (Oxide). The low-temperature polycrystalline silicon thin-film transistor has advantages such as high mobility and fast charging, and the oxide thin-film transistor has advantages such as low leakage current. Integrating the low-temperature polycrystalline silicon thin-film transistor and the oxide thin-film transistor on a display substrate to form a low-temperature polycrystalline oxide (LTPO, Low Temperature Polycrystalline Oxide) display substrate can utilize the advantages of both, reduce power consumption, and improve display quality.

[0069] Figure 6 is Figure 5 the working timing diagram of the pixel circuit shown. As Figure 5As shown, the pixel circuit of this example may include: 10 transistors (i.e., transistors T1 to T10), 2 capacitor units (i.e., first capacitor C1 and second capacitor C2), 13 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, first control line S1, second control line S2, first emission control line EM1, second emission control line EM2, first reset control line RST1, second reset control line RST2, first reference voltage line REF1, second reference voltage line REF2, first reset voltage line INIT1, and second reset voltage line INIT2), and 2 power supply terminals (i.e., first power supply line VDD and second power supply line VSS).

[0070] In some examples, as Figure 6 shown, within a frame time period, the operation process of the pixel circuit may include the following stages. In this example, the second control line S2 and the second scan line GL2 may be configured to provide the same signal, that is, the second control signal provided by the second control line S2 and the second scan signal provided by the second scan line GL2 may be the same. Among them, the gate of the second control transistor T9 may be coupled to the second scan line GL2, and the first pole of the second control transistor T9 may be coupled to the first power supply line VDD.

[0071] The first stage t11 may also be referred to as the first reset stage. The first reset signal provided by the first reset control line RST1 is at a low level, and the first reset transistor T1 is turned on; the second scan signal provided by the second scan line GL2 is at a high level, and both the compensation transistor T2 and the second control transistor T9 are turned on. The first reset voltage signal provided by the first reset voltage line INIT1 may be provided to the first node N1 through the turned-on first reset transistor T1 and compensation transistor T2, so that the first node N1 is reset to the first reset voltage Vinit1. The first power signal provided by the first power supply line VDD may be provided to the second node N2 through the turned-on second control transistor T9, and the voltage of the second node N2 is the first power supply voltage Vdd. The first control signal provided by the first control line S1 is at a low level, the first control transistor T10 is turned on, and the first reference voltage signal provided by the first reference voltage line REF1 is provided to the third node N3, and the voltage of the third node N3 is the first reference voltage Vref1.

[0072] In the first stage t11, the first emission control signal provided by the first emission control line EM1 is at a high level, and the first emission control transistor T5 is turned off; the second emission control signal provided by the second emission control line EM2 is at a high level, and the second emission control transistor T6 is turned off; the second reset control signal provided by the second reset control line RST2 is at a high level, and both the second reset transistor T7 and the third reset transistor T8 are turned off; the first scan signal provided by the first scan line GL1 is at a high level, and the data writing transistor T4 is turned off.

[0073] During the transition stage between the first stage t11 and the second stage t12, the second scan signal provided by the second scan line GL2 jumps to a low level, the first reset control signal provided by the first reset control line RST1 jumps to a high level, the second reset control signal provided by the second reset control line RST2 jumps to a low level, and the remaining signals maintain the state of the first stage t11.

[0074] The second stage t12 can also be referred to as the second reset stage or the first bias stage. The second reset control signal provided by the second reset control line RST2 is at a low level, and both the second reset transistor T7 and the third reset transistor T8 are turned on. The second reset voltage signal provided by the second reset voltage line INIT2 is written into the sixth node N6 through the turned-on second reset transistor T7, and the voltage of the sixth node N6 is the second reset voltage Vinit2 to reset the first electrode of the light-emitting element EL; the second reference voltage signal provided by the second reference voltage line REF2 is written into the fifth node N5 through the turned-on third reset transistor T8, and the voltage of the fifth node N5 is the second reference voltage Vref2. The second scan signal provided by the second scan line GL2 is at a low level, and both the compensation transistor T2 and the second control transistor T9 are turned off. The first reset control signal provided by the first reset control line RST1 is at a high level, and the first reset transistor T1 is turned off. In this stage, the driving transistor T3 is in a biased state.

[0075] During the transition stage between the second stage t12 and the third stage t13, the first light-emitting control signal provided by the first light-emitting control line EM1 jumps to a low level, the second scan signal provided by the second scan line GL2 jumps to a high level, the second reset control signal provided by the second reset control line RST2 jumps to a high level, and the remaining signals maintain the state of the second stage t12.

[0076] The third stage t13 can also be referred to as the threshold compensation stage. The second scan signal provided by the second scan line GL2 is at a high level, and both the compensation transistor T2 and the second control transistor T9 are turned on. The first node N1 and the fourth node N4 are connected through the turned-on compensation transistor T2. The first power signal provided by the first power supply line VDD can be provided to the second node N2 through the turned-on second control transistor T9, and the voltage of the second node N2 is the first power supply voltage Vdd. The first light emission control signal provided by the first light emission control line EM1 is at a low level, the first light emission control transistor T5 is turned on, and the first power signal provided by the first power supply line VDD is provided to the fifth node N5 through the turned-on first light emission control transistor T5. In this stage, the driving transistor T3 is turned on, and the driving transistor T3 is threshold-compensated using the first power signal provided by the first power supply line VDD, and the threshold voltage Vth of the driving transistor T3 is written into the first node N1. The voltage of the first node N1 is Vdd + Vth, where Vdd is the first power supply voltage of the first power signal provided by the first power supply line VDD. The second reset control signal provided by the second reset control line RST2 is at a high level, and the second reset transistor T7 and the third reset transistor T8 are turned off. The remaining transistors maintain the state of the second stage t12.

[0077] The fourth stage t14 can also be referred to as the data writing stage. The first scan signal provided by the first scan line GL1 jumps to a low level, the data writing transistor T4 is turned on, and the data signal provided by the data line DL is written into the third node N3 through the turned-on data writing transistor T4. The first control signal provided by the first control line S1 is at a high level, and the first control transistor T10 is turned off. The remaining transistors maintain the state of the third stage t13.

[0078] In the transition stage between the fourth stage t14 and the fifth stage t15, the first scan signal provided by the first scan line GL1 jumps to a high level, the second scan signal provided by the second scan line GL2 jumps to a low level, the first control signal provided by the first control line S1 jumps to a low level, the first light emission control signal provided by the first light emission control line EM1 jumps to a high level, and the second reset control signal provided by the second reset control line RST2 jumps to a low level. The remaining signals maintain the state of the fourth stage t14.

[0079] The fifth stage t15 can also be referred to as the second biasing stage. The second reset control signal provided by the second reset control line RST2 is at a low level, and both the second reset transistor T7 and the third reset transistor T8 are turned on. The second scan signal provided by the second scan line GL2 is at a low level, and both the compensation transistor T2 and the second control transistor T9 are turned off. The first scan signal provided by the first scan line GL1 is at a high level, and the data writing transistor T4 is turned off. The first emission control signal provided by the first emission control line EM1 is at a high level, and the first emission control transistor T5 is turned off. The first control signal provided by the first control line S1 is at a low level, and the first control transistor T10 is turned on. The second reference voltage signal provided by the second reference voltage line REF2 can be provided to the third node N3 through the turned-on first control transistor T10. The second control transistor T9 is turned off, and the second node N2 is floating. The data signal written to the third node N3 during the data writing stage can be coupled to the first node N1 through the second capacitor C2 and the first capacitor C1. In this stage, the driving transistor T3 is in a biased state. The second emission control transistor T6 is in an off state, and the first reset transistor T1 is in an off state.

[0080] The sixth stage t16 can also be referred to as the emission stage. The first control signal provided by the first control line S1 is at a low level, the first control transistor T10 is turned on, and the voltage of the third node N3 remains at the first reference voltage Vref1. The first emission control signal provided by the first emission control line EM1 is at a low level, and the first emission control transistor T5 is turned on; the second emission control signal provided by the second emission control line EM2 is at a low level, and the second emission control transistor T6 is turned on. The compensation transistor T2, the second control transistor T9, the data writing transistor T4, the first reset transistor T1, the second reset transistor T7, and the third reset transistor T8 are all turned off. In this stage, the driving transistor T3 is turned on. The first node N1 can record the compensation information of both the data voltage and the threshold voltage simultaneously. The voltage of the first node N1 is Vdd + Vth + Vref1 - Vdata, where Vdata is the data voltage. The gate-source voltage difference Vgs of the driving transistor T3 is Vdd + Vth + Vref1 - Vdata - Vdd = Vth + Vref1 - Vdata. During the driving process of the pixel circuit, the driving current flowing through the driving transistor T3 is determined by its gate-source voltage difference. Therefore, the driving current of the driving transistor T3 is: Id = 0.5×K×(Vgs - Vth) 2 = 0.5×K×(Vth + Vref1 - Vdata - Vth) 2 = 0.5×K×(Vref1 - Vdata) 2 。

[0081] Where K is a constant.

[0082] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving the display effect.

[0083] In the working timing of the pixel circuit of this example, in the first bias stage (i.e., the second stage t12) and the second bias stage (i.e., the fifth stage t15), the driving transistor T3 can be in a biased state, which can play a role in calibrating the voltage and improving the afterimage. In some other examples, only the first bias stage or the second bias stage can be set in the working timing of the pixel circuit.

[0084] In the working timing of the pixel circuit of this example, the threshold voltage of the driving transistor T3 and the data signal can be written into the first node N1 and the third node N3 respectively. Through the control of the second control transistor T9 over the second node N2 and the control of the first control transistor T10 over the third node N3, the data signal can be written from the third node N3 to the first node N1, realizing the writing of the data signal. This example can separate the charging process of writing the data signal into the first node and the compensation process of the threshold voltage, and can flexibly control the threshold compensation duration, improving the threshold voltage compensation effect.

[0085] In some examples, the effective level signal provided by the first scan line GL1 (a low level signal in this example) can be configured to control the data writing transistor T4 to write the data signal into the third node N3. The effective level signal provided by the second scan line GL2 (a high level signal in this example) can be configured to control the compensation transistor T2 to write the threshold voltage of the driving transistor T3 into the first node N1. Among them, the end moment of the data writing transistor T4 writing the data signal into the third node N3 is the first duration L1 from the start moment of the effective level signal provided by the second scan line GL2, and the end moment of the data writing transistor T4 writing the data signal into the third node N3 is the second duration L2 from the end moment of the effective level signal provided by the second scan line GL2. Among them, the second duration L2 is less than the first duration L1. For example, the second duration L2 can be 0.

[0086] In some examples, the effective level signal provided by the second scan line GL2 can include the following three equal division stages: the first signal stage X1, the second signal stage X2, and the third signal stage X3, and the start moment of the effective level signal provided by the first scan line GL1 is after the first signal stage X1. For example, the start moment of the effective level signal provided by the first scan line GL1 can be after the second signal stage X2.

[0087] In this example, the data writing process is carried out in the second half of the threshold voltage compensation stage, which can increase the compensation duration for the threshold voltage, making the threshold voltage compensation time sufficient and conducive to improving the compensation effect of the threshold voltage.

[0088] In this example, by setting the first capacitor C1 and the second capacitor C2, the written data signal can be effectively maintained, ensuring the writing effect of the data signal.

[0089] In the pixel circuit provided in this example, the compensation transistor T2 and the second control transistor T9 adopt oxide thin film transistors, which can prevent leakage of the first node N1 and the second node N2, and are conducive to ensuring the circuit performance.

[0090] Figure 7 It is a schematic diagram of a driving architecture of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 7 shown, the display substrate may include a plurality of sub-pixels and a plurality of gate driving circuits. The plurality of sub-pixels may be arranged in an array along a first direction X and a second direction Y. Among them, the first direction X may intersect with the second direction Y. For example, the first direction X may be perpendicular to the second direction Y. The plurality of sub-pixels arranged along the first direction X are a row of sub-pixels, and the plurality of sub-pixels arranged along the second direction Y are a column of sub-pixels. The first direction X may also be referred to as the row direction, and the second direction Y may also be referred to as the column direction. A sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may be configured to drive the light-emitting element to emit light.

[0091] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element can emit red light, green light, blue light, or white light, etc. under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined according to needs. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited thereto.

[0092] In some examples, the display substrate may include a display area and a border area located on at least one side of the display area. A plurality of sub-pixels may be located in the display area, and a plurality of gate driving circuits may be located in the border areas on both sides of the display area along the first direction X. However, this embodiment is not limited thereto. In other examples, a plurality of sub-pixels and a plurality of gate driving circuits may both be located in the display area to achieve a narrow border design.

[0093] In some examples, take the pixel circuit included in the sub-pixel as Figure 5 shown as an example. As Figure 7 shown, the plurality of gate driving circuits may include: a first scan driving circuit (for example, including first scan driving circuits 31a and 31b), a second scan driving circuit 32, a first light-emitting driving circuit 33, a second light-emitting driving circuit 34, a first reset driving circuit 35, a second reset driving circuit 36, and a first control driving circuit 37.

[0094] In some examples, the first scan driving circuits 31a and 31b may be configured to provide a first scan signal to the pixel circuits of the plurality of sub-pixels through a first scan line; the second scan driving circuit 32 may be configured to provide a second scan signal to the pixel circuits of the plurality of sub-pixels through a second scan line; the first light-emitting driving circuit 33 may be configured to provide a first light-emitting control signal to the pixel circuits of the plurality of sub-pixels through a first light-emitting control line; the second light-emitting driving circuit 34 may be configured to provide a second light-emitting control signal to the pixel circuits of the plurality of sub-pixels through a second light-emitting control line; the first reset driving circuit 35 may be configured to provide a first reset control signal to the pixel circuits of the plurality of sub-pixels through a first reset control line; the second reset driving circuit 36 may be configured to provide a second reset control signal to the pixel circuits of the plurality of sub-pixels through a second reset control line; the first control driving circuit 37 may be configured to provide a first control signal to the pixel circuits of the plurality of sub-pixels through a first control line. In this example, the second control signal may be the same as the second scan signal.

[0095] In some examples, as Figure 7 shown, the first scan driving circuits 31a and 31b may be located on both sides of the plurality of sub-pixels along the first direction X, for example, within the border areas on both sides of the display area along the first direction X. For example, the first scan driving circuit 31a may be located in the left border area, and the first scan driving circuit 31b may be located in the right border area. The first light-emitting driving circuit 33 and the second light-emitting driving circuit 34 may be located on different sides of the plurality of sub-pixels along the first direction X; the first reset driving circuit 35 and the second reset driving circuit 36 may be located on different sides of the plurality of sub-pixels along the first direction X.

[0096] In some examples, the first scan driving circuit 31a, the first light-emitting driving circuit 33, the first control driving circuit 37, and the second reset driving circuit 36 may be located on the same side of a plurality of sub-pixels along the first direction X, for example, all located in the left border area. Within the left border area, the first scan driving circuit 31a, the first light-emitting driving circuit 33, the first control driving circuit 37, and the second reset driving circuit 36 may be sequentially arranged along a direction away from the sub-pixels. The first scan driving circuit 31b, the second light-emitting driving circuit 34, the first reset driving circuit 35, and the second scan driving circuit 32 may be located on the same side of a plurality of sub-pixels along the first direction X, for example, all located in the right border area. Within the right border area, the first scan driving circuit 31b, the second light-emitting driving circuit 34, the first reset driving circuit 35, and the second scan driving circuit 32 may be sequentially arranged along a direction away from the sub-pixels. The first scan signal in this example may adopt bilateral driving, and the remaining signals may adopt unilateral driving. In other examples, the first scan signal may adopt unilateral driving. The arrangement of the plurality of gate driving circuits in this example is beneficial to routing layout.

[0097] In some examples, the first scan driving circuits 31a and 31b may both include: a plurality of first scan driving units. The plurality of first scan driving units may be arranged at intervals along the second direction Y. The nth-stage first scan driving unit may be configured to provide a first scan signal to the pixel circuits of the nth row of sub-pixels, where n is an integer greater than 0. Among them, the (2i - 1)th-stage first scan driving unit is cascaded with the (2i + 1)th-stage first scan driving unit, and the 2ith-stage first scan driving unit is cascaded with the (2i + 2)th-stage first scan driving unit, where i is an integer greater than 0. For example, the first scan driving units of odd rows such as the first row, the third row, the fifth row, and the seventh row may be sequentially cascaded; the first scan driving units of even rows such as the second row, the fourth row, the sixth row, and the eighth row may be sequentially cascaded. The first scan area unit in this example adopts the method of cascading odd and even rows separately, which can make the effective level signals output by adjacent two rows of first scan driving units overlap, can leave sufficient time for writing data signals, and can make the rise time (Tr) / fall time (Tf) of the output signal smaller.

[0098] In some examples, the second scan driving circuit 32 may include: a plurality of cascaded second scan driving units. The nth-stage second scan driving circuit may be configured to provide a second scan signal to the pixel circuits of two rows (for example, the (2n - 1)th row and the 2nth row, such as the nth row and the (n + 1)th row) of sub-pixels; the (n + 1)th-stage second scan driving circuit may be configured to provide a second scan signal to the pixel circuits of two rows (for example, the (n + 2)th row and the (n + 3)th row) of sub-pixels.

[0099] In some examples, the first light-emitting driving circuit 33 may include: a plurality of cascaded first light-emitting driving units. The nth-stage first light-emitting driving unit may be configured to provide a first light-emitting control signal to the pixel circuits of two rows of sub-pixels (for example, the (2n - 1)th row and the 2nth row, such as the nth row and the (n + 1)th row); the (n + 1)th-stage first light-emitting driving unit may be configured to provide a first light-emitting control signal to the pixel circuits of two rows of sub-pixels (for example, the (n + 2)th row and the (n + 3)th row).

[0100] In some examples, the second light-emitting driving circuit 34 may include: a plurality of cascaded second light-emitting driving units. The nth-stage second light-emitting driving unit may be configured to provide a second light-emitting control signal to the pixel circuits of two rows of sub-pixels (for example, the (2n - 1)th row and the 2nth row, such as the nth row and the (n + 1)th row); the (n + 1)th-stage second light-emitting driving unit may be configured to provide a second light-emitting control signal to the pixel circuits of two rows of sub-pixels (for example, the (n + 2)th row and the (n + 3)th row).

[0101] In some examples, the first reset driving circuit 35 may include: a plurality of cascaded first reset driving units. The nth-stage first reset driving unit may be configured to provide a first reset control signal to the pixel circuits of two rows of sub-pixels (for example, the (2n - 1)th row and the 2nth row, such as the nth row and the (n + 1)th row); the (n + 1)th-stage first reset driving unit may be configured to provide a first reset control signal to the pixel circuits of two rows of sub-pixels (for example, the (n + 2)th row and the (n + 3)th row).

[0102] In some examples, the second reset driving circuit 36 may include: a plurality of cascaded second reset driving units. The nth-stage second reset driving unit may be configured to provide a second reset control signal to the pixel circuits of two rows of sub-pixels (for example, the (2n - 1)th row and the 2nth row, such as the nth row and the (n + 1)th row); the (n + 1)th-stage second reset driving unit may be configured to provide a second reset control signal to the pixel circuits of two rows of sub-pixels (for example, the (n + 2)th row and the (n + 3)th row).

[0103] In some examples, the first control driving circuit 37 may include: a plurality of cascaded first control driving units. The nth-stage first control driving unit may be configured to provide a first control signal to the pixel circuits of two rows of sub-pixels (for example, the (2n - 1)th row and the 2nth row, such as the nth row and the (n + 1)th row); the (n + 1)th-stage first control driving unit may be configured to provide a first control signal to the pixel circuits of two rows of sub-pixels (for example, the (n + 2)th row and the (n + 3)th row).

[0104] The first scan driving circuits 31a and 31b of this example can drive the pixel circuits of odd rows and even rows separately. The second scan driving circuit 32, the first light emitting driving circuit 33, the second light emitting driving circuit 34, the first reset driving circuit 35, the second reset driving circuit 36, and the first control driving circuit 37 all use one driving unit to drive the pixel circuits of two rows of sub-pixels. When using one driving unit to drive the pixel circuits of two rows of sub-pixels, the signal generated by the driving unit can be shifted by 2H, and a driving period of 2H can be achieved, which is beneficial to supporting high-frequency display. In some other examples, when using one driving unit to drive the pixel circuits of one row of sub-pixels, the signal generated by the driving unit can be shifted by 1H.

[0105] Figure 8 Another equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 8 shown, the pixel circuit of this example may include: a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1, and a second capacitor C2. Among them, the gates of the first control transistor T10, the second control transistor T9, and the compensation transistor T2 are all coupled to the second scan line GL2. In this example, the second control line S2, the first control line S1, and the second scan line GL2 may be configured to provide the same signal. In other words, the second scan signal, the first control signal, and the second control signal of this example may be the same. For the remaining description of the pixel circuit of this example, reference may be made to the description of the foregoing embodiments, so it will not be repeated here.

[0106] Figure 9 is Figure 8 the timing diagram of the operation of the pixel circuit shown. As Figure 8 shown, the pixel circuit of this example may include: 10 transistors (i.e., transistors T1 to T10), 2 capacitor units (i.e., the first capacitor C1 and the second capacitor C2), 11 input terminals (i.e., the data line DL, the first scan line GL1, the second scan line GL2, the first light emitting control line EM1, the second light emitting control line EM2, the first reset control line RST1, the second reset control line RST2, the first reference voltage line REF1, the second reference voltage line REF2, the first reset voltage line INIT1, and the second reset voltage line INIT2), and 2 power supply terminals (i.e., the first power supply line VDD and the second power supply line VSS). In this example, the compensation transistor T2 and the second control transistor T9 are N-type transistors, and the remaining transistors are P-type transistors.

[0107] In some examples, asFigure 9 As shown, within one frame period, the working process of the pixel circuit may include the following stages. This example illustrates the working process of the pixel circuit of the sub-pixels in the n-th row.

[0108] The first stage t21 may also be referred to as the first reset stage. The first reset control signal provided by the first reset control line RST1 is at a low level, and the first reset transistor T1 is turned on; the second scan signal provided by the second scan line GL2 is at a high level, the compensation transistor T2 and the second control transistor T9 are turned on, and the first control transistor T10 is turned off. The first emission control signal provided by the first emission control line EM1 is at a high level, and the first emission control transistor T5 is turned off. The second emission control signal provided by the second emission control line EM2 is at a high level, and the second emission control transistor T6 is turned off. The second reset control signal provided by the second reset control line RST2 is at a high level, and both the second reset transistor T7 and the third reset transistor T8 are turned off; the first scan signal provided by the first scan line GL1(n) is at a high level, and the data writing transistor T4 is turned off. In this stage, the first node N1 is reset to the first reset voltage Vinit1.

[0109] The second stage t22 may also be referred to as the second reset stage or the first bias stage. The second reset control signal provided by the second reset control line RST2 is at a low level, and both the second reset transistor T7 and the third reset transistor T8 are turned on. The sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. The second scan signal provided by the second scan line GL2 is at a low level, the compensation transistor T2 and the second control transistor T9 are turned off, the first control transistor T10 is turned on, and the voltage of the third node N3 is the first reference voltage Vref1. The data writing transistor T4, the first reset transistor T1, the first emission control transistor T5, and the second emission control transistor T6 are all turned off. In this stage, the driving transistor T3 is in a biased state.

[0110] The third stage t23 may also be referred to as the threshold compensation stage. The second scan signal provided by the second scan line GL2 is at a high level, and both the compensation transistor T2 and the second control transistor T9 are turned on, and the first control transistor T10 is turned off. The first emission control signal provided by the first emission control line EM1 is at a low level, and the first emission control transistor T5 is turned on to write the first power signal provided by the first power line VDD to the fifth node N5. The data writing transistor T4, the second emission control transistor T6, the first reset transistor T1, the second reset transistor T7, and the third reset transistor T8 are all turned off. In this stage, the driving transistor T3 is turned on, and the threshold voltage Vth of the driving transistor T3 is written to the first node N1.

[0111] The fourth stage t24 can also be referred to as the data writing stage. The first scan signal provided by the first scan line GL1(n) jumps to a low level, the data writing transistor T4 is turned on, and the data signal provided by the data line DL is written into the third node N3 through the turned-on data writing transistor T4. The remaining transistors maintain the state of the third stage t23.

[0112] The fifth stage t25 can also be referred to as the second biasing stage. The second reset control signal provided by the second reset control line RST2 is at a low level, and both the second reset transistor T7 and the third reset transistor T8 are turned on. The second scan signal provided by the second scan line GL2 is at a low level, the compensation transistor T2 and the second control transistor T9 are both turned off, the first control transistor T10 is turned on, and the first reference voltage Vref1 is written into the third node N3, causing the data signal to couple to the first node N1. The first light-emitting control transistor T5, the second light-emitting control transistor T6, the first reset transistor T1, and the data writing transistor T4 are all turned off. In this stage, the driving transistor T3 is in a biased state.

[0113] The sixth stage t26 can also be referred to as the light-emitting stage. The second scan signal provided by the second scan line GL2 is at a low level, the compensation transistor T2 and the second control transistor T9 are both turned off, the first control transistor T10 is turned on, and the voltage of the third node N3 remains at the first reference voltage Vref1, which is beneficial to improving the leakage situation of the third node N3. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both turned on; the compensation transistor T2, the second control transistor T9, the data writing transistor T4, the first reset transistor T1, the second reset transistor T7, and the third reset transistor T8 are all turned off. In this stage, the driving transistor T3 is turned on. The gate-source voltage difference of the driving transistor T3 is Vgs = Vdd + Vth + Vref1 - Vdata - Vdd = Vth + Vref1 - Vdata. The driving current of the driving transistor T3 is: Id = 0.5×K×(Vgs - Vth) 2 = 0.5×K×(Vth + Vref1 - Vdata - Vth) 2 = 0.5×K×(Vref1 - Vdata) 2 .

[0114] Where K is a constant, Vdata is the data voltage, Vref1 is the first reference voltage, and Vth is the threshold voltage.

[0115] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving the display effect.

[0116] This example can separate the charging process of writing a data signal to the first node and the compensation process of the threshold voltage, can flexibly control the threshold compensation duration, and improve the threshold voltage compensation effect. In the pixel circuit of this example, the second scan signal is used to control the compensation transistor, the first control transistor, and the second control transistor simultaneously, which is beneficial to saving signal sources and wiring, and is beneficial to improving the leakage situation of the third node N3.

[0117] Figure 10 It is a schematic diagram of another driving architecture of the pixel circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 10 shown, taking the pixel circuit included in the sub-pixel as Figure 8 shown as an example, the multiple gate driving circuits of this example may include: a first scan driving circuit 31, a second scan driving circuit 32, a first light emitting driving circuit 33, a second light emitting driving circuit 34, a first reset driving circuit 35, and a second reset driving circuit 36.

[0118] In some examples, the first scan driving circuit 31 and the second scan driving circuit 32 may be located on different sides of the multiple sub-pixels along the first direction X, the first light emitting driving circuit 33 and the second light emitting driving circuit 34 may be located on different sides of the multiple sub-pixels along the first direction X, and the first reset driving circuit 35 and the second reset driving circuit 36 may be located on different sides of the multiple sub-pixels along the first direction X.

[0119] In some examples, the first scan driving circuit 31, the first light emitting driving circuit 33, and the second reset driving circuit 36 may be located on the same side of the multiple sub-pixels along the first direction X, for example, all located in the left border area. Within the left border area, the first scan driving circuit 31, the first light emitting driving circuit 33, and the second reset driving circuit 36 may be arranged in sequence along the direction away from the sub-pixels. The second scan driving circuit 32, the second light emitting driving circuit 34, and the first reset driving circuit 35 may be located on the same side of the multiple sub-pixels along the first direction X. For example, all located in the right border area. Within the right border area, the second scan driving circuit 32, the second light emitting driving circuit 34, and the first reset driving circuit 35 may be arranged in sequence along the direction away from the sub-pixels. In this example, multiple gate driving circuits may all adopt the single-sided driving method.

[0120] In some examples, as Figure 9 and Figure 10As shown, the first scan driving circuit 31 includes a plurality of first scan driving units. The plurality of first scan driving units may be sequentially arranged along the second direction Y. Among them, the (2i - 1)-th stage first scan driving unit and the (2i + 1)-th stage first scan driving unit may be cascaded, and the 2i-th stage first scan driving unit and the (2i + 2)-th stage first scan driving unit are cascaded, where i is an integer greater than 0. For example, the first scan driving units of odd rows such as the first row, the third row, the fifth row, and the seventh row may be sequentially cascaded; the first scan driving units of even rows such as the second row, the fourth row, the sixth row, and the eighth row may be sequentially cascaded. For example, the first scan signals provided by the first scan driving units of the (n - 1)-th stage to the (n + 2)-th stage through the first scan lines GL1(n - 1) to GL1(n + 2) may be as Figure 9 shown. The first scan area unit in this example adopts a cascading method with odd and even rows separated, which can make the valid level signals (low level signals in this example) output by the first scan driving units of adjacent two rows have an overlapping period, leaving sufficient time for writing the data signal, and can make the rise time (Tr) / fall time (Tf) of the output signal smaller. In some other examples, the first scan driving units of the first scan driving circuit may adopt a conventional cascading method in sequential row order, and the output waveform as Figure 9 shown can also be obtained. This embodiment does not limit this.

[0121] In some examples, as Figure 9 shown, since there is an overlapping period for the valid level signals output by adjacent two-stage first scan driving units (for example, the overlapping period of the output signals of the (n - 1)-th stage first scan driving unit and the n-th stage first scan driving unit is the second period ②), when the pixel circuit of the (n - 1)-th row obtains the data signal transmitted by the data line, the pixel circuit of the n-th row will also obtain the data signal. At this time, after the (n - 1)-th stage first scan driving unit is turned off, the data signal needs to be provided to the pixel circuit of the n-th row, which not only ensures that the writing of the data signal of the previous row is not affected, but also can completely write the data signal of this row. In other words, the data signals transmitted by the data line are respectively provided to the pixel circuits of the (n - 1)-th row, the n-th row, the (n + 1)-th row, and the (n + 2)-th row at the second period ②, the third period ③, the fourth period ④, and the fifth period ⑤ as Figure 9 shown. In this way, since a first scan driving unit outputs a pulse signal of 2H, sufficient time can be left for writing the data signal. Here, it is not the actual writing duration of 2H for the data signal, but there is a sufficient pulse width to be turned on, which is sufficient for writing the data signal.

[0122] The first scan driving circuit of this example can drive the pixel circuits of odd rows and even rows separately. The second scan driving circuit, the first light-emitting driving circuit, the second light-emitting driving circuit, the first reset driving circuit, and the second reset driving circuit all use one driving unit to drive the pixel circuits of two rows of sub-pixels, which can achieve a driving period of 2H, thus facilitating high-frequency display. Moreover, the setting method of the multiple gate driving circuits in this example is beneficial to the routing layout. Other descriptions of the driving architecture of this example can be referred to Figure 7 the description of the illustrated embodiment, so it will not be repeated here.

[0123] Figure 11 Another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure. In some examples, as Figure 11 shown, the pixel circuit of this example may include: a driving transistor T3, a compensating transistor T2, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1, and a second capacitor C2. Among them, the gate of the first control transistor T10 is coupled to the first light-emitting control line EM1, and the gates of the second control transistor T9 and the compensating transistor T2 are both coupled to the second scan line GL2. In this example, the second control line S2 and the second scan line GL2 may be configured to transmit the same signal; the first control line S1 and the first light-emitting control line EM1 may be configured to transmit the same signal. In other words, in this example, the second control signal and the second scan signal may be the same, and the first control signal and the first light-emitting control signal may be the same. The remaining descriptions of the pixel circuit of this example can be referred to the description of the foregoing embodiment, so it will not be repeated here.

[0124] Figure 12 is Figure 11 the timing diagram of the pixel circuit shown. As Figure 12 shown, the pixel circuit of this example may include: 10 transistors (i.e., transistors T1 to T10), 2 capacitor units (i.e., the first capacitor C1 and the second capacitor C2), 11 input terminals (i.e., the data line DL, the first scan line GL1, the second scan line GL2, the first light-emitting control line EM1, the second light-emitting control line EM2, the first reset control line RST1, the second reset control line RST2, the first reference voltage line REF1, the second reference voltage line REF2, the first reset voltage line INIT1, and the second reset voltage line INIT2), and 2 power supply terminals (i.e., the first power supply line VDD and the second power supply line VSS). In some examples, the compensating transistor T2 and the second control transistor T9 are N-type transistors, and the remaining transistors are P-type transistors.

[0125] In some examples, asFigure 12 As shown, within one frame period, the operation process of the pixel circuit may include the following stages.

[0126] The first stage t31 may also be referred to as the first reset stage or the first bias stage. The second reset control signal provided by the second reset control line RST2 is at a low level, turning on the second reset transistor T7 and the third reset transistor T8. The sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. The second scan signal provided by the second scan line GL2 is a high-level signal, turning on both the compensation transistor T2 and the second control transistor T9. The first emission control signal provided by the first emission control line EM1 is at a high level, turning off both the first emission control transistor T5 and the first control transistor T10. The first reset control signal provided by the first reset control line RST1 is at a high level, turning off the first reset transistor T1. The second emission control signal provided by the second emission control line EM2 is at a high level, turning off the second emission control transistor T6. The first scan signal provided by the first scan line GL1 is at a high level, turning off the data writing transistor T4.

[0127] The second stage t32 may also be referred to as the second reset stage. The first reset control signal provided by the first reset control line RST1 is at a low level, turning on the first reset transistor T1. In this stage, the first node N1 is reset to the first reset voltage Vinit1. The second reset control signal provided by the second reset control line RST2 is at a high level, turning off both the second reset transistor T7 and the third reset transistor T8.

[0128] The third stage t33 may also be referred to as the threshold compensation stage. The second scan signal provided by the second scan line GL2 is at a high level, turning on both the compensation transistor T2 and the second control transistor T9, and writing the threshold voltage of the driving transistor T3 to the first node N1. The first reset control signal provided by the first reset control line RST1 is at a low level, turning off the first reset transistor T1. The first emission control signal provided by the first emission control line EM1 is at a low level, turning on both the first emission control transistor T5 and the first control transistor T10. The voltage of the third node N3 is the first reference voltage Vref1.

[0129] The fourth stage t34 may also be referred to as the data writing stage. The first scan signal provided by the first scan line GL1 jumps to a low level, turning on the data writing transistor T4. The data signal provided by the data line DL is written to the third node N3 through the turned-on data writing transistor T4. The first emission control signal provided by the first emission control line EM1 is at a high level, turning off both the first emission control transistor T5 and the first control transistor T10.

[0130] In the fifth stage t35, the first scan signal provided by the first scan line GL1 is at a high level, and the data writing transistor T4 is turned off. The second scan signal provided by the second scan line GL2 is at a low level, and both the compensation transistor T2 and the second control transistor T9 are turned off. The first light emission control signal provided by the first light emission control line EM1 is at a low level, and both the first light emission control transistor T5 and the first control transistor T10 are turned on. Since the second control transistor T9 is turned off and the second node N2 is floating, the data signal written to the third node N3 during the data writing stage can be coupled to the first node N1 through the second capacitor C2 and the first capacitor C1.

[0131] In the sixth stage t36, which can also be referred to as the second bias stage, the second reset control signal provided by the second reset control line RST2 is at a low level, and both the second reset transistor T7 and the third reset transistor T8 are turned on. The sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. The second scan signal provided by the second scan line GL2 is at a low level, and both the compensation transistor T2 and the second control transistor T9 are turned off. The first scan signal provided by the first scan line GL1 is at a high level, and the data writing transistor T4 is turned off. The first light emission control signal provided by the first light emission control line EM1 is at a high level, and both the first light emission control transistor T5 and the first control transistor T10 are turned off. In this stage, the driving transistor T3 is in a biased state.

[0132] In the seventh stage t37, which can also be referred to as the light emission stage, the first light emission control signal provided by the first light emission control line EM1 is at a low level, and both the first light emission control transistor T5 and the first control transistor T10 are turned on. The voltage of the third node N3 is maintained at the first reference voltage Vref1, which helps to improve the leakage situation of the third node N3. The second light emission control signal provided by the second light emission control line EM2 is at a low level, and the second light emission control transistor T6 is turned on. The compensation transistor T2, the second control transistor T9, the data writing transistor T4, the first reset transistor T1, the second reset transistor T7, and the third reset transistor T8 are all turned off. In this stage, the driving transistor T3 is turned on. The voltage of the first node N1 is Vdd + Vth + Vref1 - Vdata, where Vdata is the data voltage. The gate-source voltage difference Vgs of the driving transistor T3 is Vdd + Vth + Vref1 - Vdata - Vdd = Vth + Vref1 - Vdata. The driving current of the driving transistor T3 is: Id = 0.5×K×(Vgs - Vth) 2 = 0.5×K×(Vth + Vref1 - Vdata - Vth) 2 = 0.5×K×(Vref1 - Vdata) 2 .

[0133] Wherein, K is a constant, Vdata is the data voltage, Vref1 is the first reference voltage, and Vth is the threshold voltage.

[0134] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving the display effect.

[0135] This example can separate the charging process of writing the data signal to the first node and the compensation process of the threshold voltage, can flexibly control the threshold compensation duration, and improve the threshold voltage compensation effect. In the pixel circuit of this example, the second scan signal is used to control the compensation transistor and the first control transistor at the same time, and the first light emission control signal is used to control the first light emission control transistor and the second control transistor at the same time, which is beneficial to saving signal sources and wiring, and is also beneficial to improving the leakage of the third node N3.

[0136] Figure 13 It is a schematic diagram of another driving architecture of the pixel circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 13 shown, taking the pixel circuit included in the sub-pixel as Figure 11 shown as an example, the multiple gate driving circuits of this example may include: a first scan driving circuit 31, a second scan driving circuit 32, a first light emission driving circuit 33, a second light emission driving circuit 34, a first reset driving circuit 35, and a second reset driving circuit 36.

[0137] In some examples, the first light emission driving circuit 33 may include: a plurality of cascaded first light emission driving units. The nth-stage first light emission driving unit may be configured to provide a first light emission control signal to the pixel circuit of the nth-row sub-pixels; the (n + 1)th-stage first light emission driving unit may be configured to provide a first light emission control signal to the pixel circuit of the (n + 1)th-row sub-pixels, where n is an integer greater than 0.

[0138] The first light emission driving circuit of this example can drive the pixel circuits of each row of sub-pixels separately, the first scan driving circuit can drive the pixel circuits of odd rows and even rows separately, and the second scan driving circuit, the second light emission driving circuit, the first reset driving circuit, and the second reset driving circuit all use one driving unit to drive the pixel circuits of two rows of sub-pixels, which can achieve a driving period of 2H, thus being beneficial to supporting high-frequency display. Moreover, the first light emission control signal provided by the first light emission driving circuit of this example controls the second control transistor and the first light emission control transistor at the same time, which can be beneficial to improving the leakage of the third node N3. Other descriptions of the driving architecture of this example can refer to the descriptions of the embodiments shown in the foregoing Figure 7 and Figure 10 and will not be elaborated herein.

[0139] Figure 14 Another equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 14 shown, the pixel circuit of this example may include: a driving transistor T3, a compensating transistor T2, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1, and a second capacitor C2. Among them, the gate of the first control transistor T10 is coupled to the first light-emitting control line EM1, and the gates of the second control transistor T9 and the compensating transistor T2 are both coupled to the second scanning line GL2. The driving transistor T3, the compensating transistor T2, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the first reset transistor T1, the second reset transistor T7, the third reset transistor T8, the second control transistor T9, and the first control transistor T10 in this example may all be P-type transistors. For the remaining description of the pixel circuit of this example, reference may be made to the description of the foregoing embodiments, so it will not be repeated here.

[0140] Figure 15 is Figure 14 the timing diagram of the operation of the pixel circuit shown. As Figure 14 shown, the pixel circuit of this example may include: 10 transistors (i.e., transistors T1 to T10), 2 capacitor units (i.e., the first capacitor C1 and the second capacitor C2), 11 input terminals (i.e., the data line DL, the first scanning line GL1, the second scanning line GL2, the first light-emitting control line EM1, the second light-emitting control line EM2, the first reset control line RST1, the second reset control line RST2, the first reference voltage line REF1, the second reference voltage line REF2, the first reset voltage line INIT1, and the second reset voltage line INIT2), and 2 power supply terminals (i.e., the first power supply line VDD and the second power supply line VSS). The 10 transistors in this example are all P-type transistors.

[0141] In some examples, as Figure 15 shown, within one frame period, the operation process of the pixel circuit may include the following stages.

[0142] In the first stage t51, the second reset control signal provided by the second reset control line RST2 is at a low level, the second reset transistor T7 and the third reset transistor T8 are turned on, the sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. The second scan signal provided by the second scan line GL2 is at a high level signal, and both the compensation transistor T2 and the second control transistor T9 are turned on. The first emission control signal provided by the first emission control line EM1 is at a high level, and both the first emission control transistor T5 and the first control transistor T10 are turned off. The first reset control signal provided by the first reset control line RST1 is at a high level, and the first reset transistor T1 is turned off. The second emission control signal provided by the second emission control line EM2 is at a high level, and the second emission control transistor T6 is turned off. The first scan signal provided by the first scan line GL1 is at a high level, and the data writing transistor T4 is turned off.

[0143] In the second stage t52, the first reset control signal provided by the first reset control line RST1 is at a low level, and the first reset transistor T1 is turned on. In this stage, the first node N1 is reset to the first reset voltage Vinit1.

[0144] In the third stage t53, the second reset control signal provided by the second reset control line RST2 is at a low level, the second reset transistor T7 and the third reset transistor T8 are turned on, the sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. The second scan signal provided by the second scan line GL2 is at a high level, and both the compensation transistor T2 and the second control transistor T9 are turned off.

[0145] In the fourth stage t54, the first emission control signal provided by the first emission control line EM1 is at a low level, and both the first emission control transistor T5 and the first control transistor T10 are turned on, and the first reference voltage Vref1 is written to the third node N3. The second scan signal provided by the second scan line GL2 is at a low level, and both the compensation transistor T2 and the second control transistor T9 are turned on, and the threshold voltage of the driving transistor T3 is written to the first node N1.

[0146] In the fifth stage t55, the first scan signal provided by the first scan line GL1 jumps to a low level, the data writing transistor T4 is turned on, and the data signal provided by the data line DL is written to the third node N3 through the turned-on data writing transistor T4. The first emission control signal provided by the first emission control line EM1 is at a high level, and both the first emission control transistor T5 and the first control transistor T10 are turned off.

[0147] In the sixth stage t56, the first light emission control signal provided by the first light emission control line EM1 is at a low level. Both the first light emission control transistor T5 and the first control transistor T10 are turned on, and the first reference voltage Vref1 is written to the third node N3. The second scan signal provided by the second scan line GL2 is at a high level, and both the compensation transistor T2 and the second control transistor T9 are turned off. With the second control transistor T9 turned off, the second node N2 is floating, and the data signal written to the third node N3 during the data writing stage can be coupled to the first node N1 through the second capacitor C2 and the first capacitor C1.

[0148] In the seventh stage t57, the second reset control signal provided by the second reset control line RST2 is at a low level. Both the second reset transistor T7 and the third reset transistor T8 are turned on, and the sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. In this stage, the driving transistor T3 is in a biased state.

[0149] In the eighth stage t58, the first light emission control signal provided by the first light emission control line EM1 is at a low level. Both the first light emission control transistor T5 and the first control transistor T10 are turned on, and the voltage of the third node N3 remains the first reference voltage Vref1, which is beneficial to improving the leakage of the third node N3. The second light emission control signal provided by the second light emission control line EM2 is at a low level, and the second light emission control transistor T6 is turned on. In this stage, the driving transistor T3 is turned on. The voltage of the first node N1 is Vdd + Vth + Vref1 - Vdata, where Vdata is the data voltage. The gate-source voltage difference Vgs of the driving transistor T3 is Vgs = Vdd + Vth + Vref1 - Vdata - Vdd = Vth + Vref1 - Vdata. The driving current of the driving transistor T3 is: Id = 0.5×K×(Vgs - Vth) 2 = 0.5×K×(Vth + Vref1 - Vdata - Vth) 2 = 0.5×K×(Vref1 - Vdata) 2 .

[0150] Where K is a constant, Vdata is the data voltage, Vref1 is the first reference voltage, and Vth is the threshold voltage.

[0151] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving the display effect.

[0152] In some examples, the valid level signal provided by the first scan line GL1 (a low level signal in this example) can be configured to control the data writing transistor T4 to write a data signal to the third node N3. The valid level signal provided by the second scan line GL2 (a low level signal in this example) can be configured to control the compensation transistor T2 to write the threshold voltage of the driving transistor T3 to the first node N1. Among them, the end time of the data writing transistor T4 writing the data signal to the third node N3 can be the first duration L1 from the start time of the valid level signal provided by the second scan line GL2, and the end time of the data writing transistor T4 writing the data signal to the third node N3 can be the second duration L2 from the end time of the valid level signal provided by the second scan line GL2. Among them, the second duration L2 is less than the first duration L1. In this example, the data writing process is performed in the second half of the threshold voltage compensation stage, which can increase the compensation duration of the threshold voltage, make the threshold voltage compensation time sufficient, and is beneficial to improving the compensation effect of the threshold voltage.

[0153] This example can separate the charging process of writing the data signal to the first node and the compensation process of the threshold voltage, can flexibly control the threshold compensation duration, and improve the threshold voltage compensation effect. Moreover, the types of transistors in the pixel circuit of this example are the same, which is beneficial to simplifying the process flow and reducing the process difficulty of the display substrate. The driving architecture of the pixel circuit of this example can refer to Figure 10 and Figure 13 the descriptions of the embodiments shown, so they will not be elaborated here.

[0154] Figure 16 is another structural schematic diagram of the pixel circuit of at least one embodiment of the present disclosure. In some examples, as Figure 16 shown, the pixel circuit of this example may include: a driving sub-circuit 11, a compensation sub-circuit 12, a data writing sub-circuit 13, a first coupling sub-circuit 141, a second coupling sub-circuit 142, a first control sub-circuit 15, a second control sub-circuit 16, a first light emitting control sub-circuit 21, a second light emitting control sub-circuit 22, a first reset sub-circuit 23, a second reset sub-circuit 24, and a third reset sub-circuit 25. Among them, the first reset sub-circuit 23 is coupled to the first reset control line RST1, the first reset voltage line INIT1, and the first node N1, and is configured to write the first reset voltage signal provided by the first reset voltage line INIT1 to the first node N1 under the control of the first reset control line RST1. Regarding the remaining structure of the pixel circuit of this example, reference can be made to the description of the foregoing embodiments, so they will not be elaborated here.

[0155] Figure 17 is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure. In some examples, as Figure 17As shown, the pixel circuit of this example may include: a driving transistor T3, a compensating transistor T2, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1, and a second capacitor C2. Among them, the gate of the first reset transistor T1 is coupled to the first reset control line RST1, the first pole of the first reset transistor T1 is coupled to the first reset voltage line INIT1, and the second pole of the first reset transistor T1 is coupled to the first node N1. The gates of the second control transistor T9 and the compensating transistor T2 are both coupled to the second scan line GL2, the first pole of the second control transistor T9 is coupled to the first power supply line VDD, and the gate of the first control transistor T10 is coupled to the first light-emitting control line EM1. The remaining description of the pixel circuit of this example may refer to the description of the foregoing embodiments, so it will not be repeated here.

[0156] Figure 18 is Figure 17 the timing diagram of the operation of the pixel circuit shown. As Figure 17 shown, the pixel circuit of this example may include: 10 transistors (i.e., transistors T1 to T10), 2 capacitor units (i.e., the first capacitor C1 and the second capacitor C2), 11 input terminals (i.e., the data line DL, the first scan line GL1, the second scan line GL2, the first light-emitting control line EM1, the second light-emitting control line EM2, the first reset control line RST1, the second reset control line RST2, the first reference voltage line REF1, the second reference voltage line REF2, the first reset voltage line INIT1, and the second reset voltage line INIT2), and 2 power supply terminals (i.e., the first power supply line VDD and the second power supply line VSS). The transistors T1 to T10 in this example are all P-type transistors.

[0157] In some examples, as Figure 18 shown, within a frame period, the operation process of the pixel circuit may include the following stages. This example will be described by taking the operation process of the pixel circuit in the (n - 1)-th row as an example.

[0158] In the first stage t41, the second reset control line RST2 provides a low-level second reset control signal, and both the second reset transistor T7 and the third reset transistor T8 are turned on; the second scan line GL2 provides a low-level second scan signal, and both the compensating transistor T2 and the second control transistor T9 are turned on. The first light-emitting control transistor T5, the second light-emitting control transistor T6, the first control transistor T10, the first reset transistor T1, and the data writing transistor T4 are all turned off.

[0159] In the second stage t42, the first reset control line RST1 provides a first reset control signal at a low level, and the first reset transistor T1 is turned on. The second scan line GL2 provides a second scan signal at a low level, and both the compensation transistor T2 and the second control transistor T9 are turned on. In this stage, the first node N1 is reset to the first reset voltage Vinit1.

[0160] In the third stage t43, both the compensation transistor T2 and the second control transistor T9 are turned on; the first emission control line EM1(n - 1) provides a low-level signal, and both the first emission control transistor T5 and the first control transistor T10 are turned on. The voltage of the third node N3 is the first reference voltage Vref1. In this stage, the driving transistor T3 is turned on, and the threshold voltage Vth of the driving transistor T3 is written into the first node N1.

[0161] In the fourth stage t44, the first scan line GL1(n - 1) provides a first scan signal at a low level, the data writing transistor T4 is turned on, and the data signal provided by the data line DL is written into the third node N3 through the turned-on data writing transistor T4. The first emission control signal provided by the first emission control line EM1 is at a high level, and both the first emission control transistor T5 and the first control transistor T10 are turned off.

[0162] In the fifth stage t45, the first emission control line EM1(n - 1) provides a first emission control signal at a low level, and both the first emission control transistor T5 and the first control transistor T10 are turned on, and the first reference voltage Vref1 is written into the third node N3.

[0163] In the sixth stage t46, the second reset control line RST2 provides a second reset control signal at a low level, and both the second reset transistor T7 and the eighth reset transistor T8 are turned on, the sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2.

[0164] In the seventh stage t47, the first emission control line EM1(n - 1) provides a low-level signal, and both the first emission control transistor T5 and the first control transistor T10 are turned on. The voltage of the third node N3 is maintained at the first reference voltage Vref1, which is beneficial to improving the leakage situation of the third node N3. The second emission control transistor T6 is turned on. In this stage, the driving transistor T3 is turned on. The gate-source voltage difference Vgs of the driving transistor T3 = Vdd + Vth + Vref1 - Vdata - Vdd = Vth + Vref1 - Vdata. The driving current of the driving transistor T3 is: Id = 0.5×K×(Vgs - Vth) 2 = 0.5×K×(Vth + Vref1 - Vdata - Vth) 2=0.5×K×(Vref1 - Vdata) 2 。

[0165] Wherein, K is a constant, Vdata is the data voltage, Vref1 is the first reference voltage, and Vth is the threshold voltage.

[0166] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving the display effect.

[0167] This example can separate the charging process of writing the data signal to the first node and the compensation process of the threshold voltage, and can flexibly control the threshold compensation duration to improve the threshold voltage compensation effect. Moreover, the types of transistors in the pixel circuit of this example are the same, which is beneficial to simplifying the process flow and reducing the process difficulty of the display substrate. The driving architecture of the pixel circuit of this example can refer to Figure 10 and Figure 13 the descriptions of the embodiments shown, so it will not be elaborated here.

[0168] Figure 19 is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure. In some examples, as Figure 19 shown, the pixel circuit of this example may include: a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1, and a second capacitor C2. Among them, the gates of the first control transistor T10 and the data writing transistor T4 are both coupled to the first scan line GL1. The gates of the second control transistor T9 and the compensation transistor T2 are both coupled to the second scan line GL2. In this example, the first control line S1 and the first scan line GL1 can be configured to provide the same signal, and the second control line S2 and the second scan line GL2 can be configured to provide the same signal. In other words, the second scan signal and the second control signal in this example can be the same, and the first scan signal and the first control signal can be the same. In this example, the data writing transistor T4, the compensation transistor T2, and the second control transistor T9 are N-type transistors, and the rest of the transistors are P-type transistors. The remaining descriptions of the pixel circuit of this example can refer to the descriptions of the foregoing embodiments, so it will not be elaborated here.

[0169] Figure 20 is Figure 19 the working timing diagram of the pixel circuit shown. As Figure 19As shown, the pixel circuit of this example may include: 10 transistors (i.e., transistors T1 to T10), 2 capacitor units (i.e., first capacitor C1 and second capacitor C2), 11 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, first emission control line EM1, second emission control line EM2, first reset control line RST1, second reset control line RST2, first reference voltage line REF1, second reference voltage line REF2, first reset voltage line INIT1, and second reset voltage line INIT2), and 2 power supply terminals (i.e., first power supply line VDD and second power supply line VSS).

[0170] In some examples, as Figure 20 shown, within one frame period, the operation process of the pixel circuit may include the following stages.

[0171] The first stage t61 may also be referred to as the first reset stage. The first reset control signal provided by the first reset control line RST1 is at a low level, and the first reset transistor T1 is turned on. The second scan signal provided by the second scan line GL2 is at a high level, and both the compensation transistor T2 and the second control transistor T9 are turned on. The first node N1 is reset to the first reset voltage Vinit1. The first scan signal provided by the first scan line GL1 is at a low level, the data writing transistor T4 is turned off, and the first control transistor T10 is turned on.

[0172] The second stage t62 may also be referred to as the first bias stage or the second reset stage. The second reset control signal provided by the second reset control line RST2 is at a low level, and both the second reset transistor T7 and the third reset transistor T8 are turned on. The sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. In this stage, the driving transistor T3 is in a biased state.

[0173] The third stage t63 may also be referred to as the threshold compensation stage. The second scan signal provided by the second scan line GL2 is at a high level, and both the compensation transistor T2 and the second control transistor T9 are turned on. The first scan signal provided by the first scan line GL1 is at a low level, the first control transistor T10 is turned on, and the data writing transistor T4 is turned off. The first emission control signal provided by the first emission control line EM1 is at a low level, and the first emission control transistor T5 is turned on. In this stage, the driving transistor T3 is turned on, and the threshold voltage Vth of the driving transistor T3 is written into the first node N1. The voltage of the second node N2 is the first power supply voltage Vdd, and the voltage of the third node N3 is the first reference voltage Vref1.

[0174] The fourth stage t64 can also be referred to as the data writing stage. The first scan signal provided by the first scan line GL1 jumps to a high level, the first control transistor T10 is turned off, the data writing transistor T4 is turned on, and the data signal provided by the data line DL is written into the third node N3 through the turned-on data writing transistor T4.

[0175] The fifth stage t65 can also be referred to as the second biasing stage. The second reset control signal provided by the second reset control line RST2 is at a low level, and both the second reset transistor T7 and the third reset transistor T8 are turned on. In this stage, the driving transistor T3 is in a biased state.

[0176] The sixth stage t66 can also be referred to as the light emitting stage. The first scan signal provided by the first scan line GL1 is at a low level, the data writing transistor T4 is turned off, the first control transistor T10 is turned on, and the voltage of the third node N3 remains at the first reference voltage Vref1, which is beneficial to improving the leakage of the third node N3. The first light emitting control transistor T5, the second light emitting control transistor T6, and the driving transistor T3 are all turned on. The gate-source voltage difference of the driving transistor T3 is Vgs = Vdd + Vth + Vref1 - Vdata - Vdd = Vth + Vref1 - Vdata. The driving current of the driving transistor T3 is: Id = 0.5×K×(Vgs - Vth) 2 = 0.5×K×(Vth + Vref1 - Vdata - Vth) 2 = 0.5×K×(Vref1 - Vdata) 2 .

[0177] Where K is a constant, Vdata is the data voltage, Vref1 is the first reference voltage, and Vth is the threshold voltage.

[0178] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving the display effect.

[0179] This example can separate the charging process of writing the data signal into the first node and the compensation process of the threshold voltage, can flexibly control the threshold compensation duration, and improve the threshold voltage compensation effect. In the pixel circuit of this example, the first scan signal is used to control both the data writing transistor and the second control transistor at the same time, which is beneficial to saving signal sources and wiring, and is beneficial to improving the leakage of the third node N3. The driving architecture of the pixel circuit of this example can refer to Figure 10 or Figure 13 the description of the embodiments shown, so it will not be elaborated here.

[0180] Figure 21Another structural schematic diagram of the pixel circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 21 shown, the pixel circuit of this example may include: a driving sub-circuit 11, a compensation sub-circuit 12, a data writing sub-circuit 13, a first coupling sub-circuit 141, a second coupling sub-circuit 142, a first control sub-circuit 15, a second control sub-circuit 16, a first light-emitting control sub-circuit 21, a second light-emitting control sub-circuit 22, a first reset sub-circuit 23, a second reset sub-circuit 24, a third reset sub-circuit 25, and a fourth reset sub-circuit 26. Among them, the fourth reset sub-circuit 26 is coupled to the third reset control line RST3, the first reference voltage line REF1, and the third node N3, and is configured to write the first reference voltage signal provided by the first reference voltage line REF1 to the third node N3 under the control of the third reset control line RST3. For the remaining structure of the pixel circuit of this example, reference may be made to the description of the foregoing embodiment, and thus it will not be elaborated herein.

[0181] Figure 22 Another equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 22 shown, the fourth reset sub-circuit may include a fourth reset transistor T11. The gate of the fourth reset transistor T11 is coupled to the second reset control line RST2, the first pole is coupled to the first reference voltage line REF1, and the second pole is coupled to the third node N3. The second reset control line RST2 and the third reset control line of this example may be configured to provide the same signal. In other words, the second reset control signal and the third reset control signal may be the same. The gate of the first control transistor T10 is coupled to the second light-emitting control line EM2. In other words, the second light-emitting control line EM2 and the first control line may be configured to provide the same signal, that is, the second light-emitting control signal and the first control signal may be the same. The data writing transistor T4, the compensation transistor T2, and the second control transistor T9 in this example may all be N-type transistors, and the remaining transistors are all P-type transistors. For the remaining description of the pixel circuit of this example, reference may be made to the description of the foregoing embodiment, and thus it will not be elaborated herein.

[0182] The working timing of the pixel circuit of this example may refer to Figure 20 the shown working timing diagram. Among them, the first control transistor T10 is turned on in the sixth stage t66 (i.e., the light-emitting stage), which can not only couple the data signal to the first node N1, but also improve the leakage of the third node N3. For the remaining working timing of the pixel circuit, reference may be made to the description of the foregoing embodiment, and thus it will not be elaborated herein.

[0183] This example can separate the charging process of writing a data signal to the first node and the compensation process of the threshold voltage, can flexibly control the threshold compensation duration, and improve the threshold voltage compensation effect. Moreover, using the second light emission control signal to control the second control transistor and the second light emission control transistor simultaneously can help save signal sources and wiring, and can also improve the leakage situation of the third node N3. The driving architecture of the pixel circuit in this example can refer to Figure 10 or Figure 13 the description of the embodiments shown, and thus will not be elaborated here.

[0184] Figure 23 is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure. In some examples, as Figure 23 shown, the pixel circuit of this example may include: a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a second light emission control transistor T6, a first reset transistor T1, a second reset transistor T7, a second control transistor T9, a first control transistor T10, a first capacitor C1, a second capacitor C2, and a third capacitor C3. Among them, the first pole of the driving transistor T3 is coupled to the first power supply line VDD. The fifth node of this example is directly coupled to the first power supply line VDD. The first electrode of the third capacitor C3 is coupled to the first bias signal line V1, and the second electrode is coupled to the first node N1. The gates of the compensation transistor T2, the second control transistor T9, and the first control transistor T10 are all coupled to the second scan line GL2. The second scan line GL2, the first control line, and the second control line in this example can be configured to provide the same signal; in other words, the second scan signal, the first control signal, and the second control signal in this example can be the same. The compensation transistor T2 and the second control transistor T9 in this example can both be N-type transistors, and the rest of the transistors are all P-type transistors. The remaining descriptions of the pixel circuit of this example can refer to the description of the foregoing embodiments, and thus will not be elaborated here.

[0185] Figure 24 is Figure 23 the working timing diagram of the pixel circuit shown. As Figure 23 shown, the pixel circuit of this example may include: 8 transistors (i.e., transistors T1, T2, T3, T4, T6, T7, T9, and T10), 3 capacitor units (i.e., the first capacitor C1, the second capacitor C2, and the third capacitor C3), 10 input terminals (i.e., the data line DL, the first scan line GL1, the second scan line GL2, the second light emission control line EM2, the first reset control line RST1, the second reset control line RST2, the first reference voltage line REF1, the first coupling signal line V1, the first reset voltage line INIT1, and the second reset voltage line INIT2), and 2 power supply terminals (i.e., the first power supply line VDD and the second power supply line VSS).

[0186] In some examples, such as Figure 24 shown, within one frame period, the working process of the pixel circuit may include the following stages. In this example, it is described by taking the case where the first coupling signal line V1 and the second reset control line RST2 provide the same signal as an example. In other words, the first electrode of the third capacitor C3 may be coupled to the second reset control line RST2.

[0187] The first stage t71 may also be referred to as the first reset stage. The first reset control signal provided by the first reset control line RST1 is at a low level, and the first reset transistor T1 is turned on. The second scan signal provided by the second scan line GL2 is at a high level, the compensation transistor T2 and the second control transistor T9 are both turned on, and the first control transistor T10 is turned off. The first node N1 is reset to the first reset voltage Vinit1.

[0188] The second stage t72 may also be referred to as the first bias stage or the second reset stage. The second reset control signal provided by the second reset control line RST2 is at a low level, the second reset transistor T7 is turned on, and the sixth node N6 is reset to the second reset voltage Vinit2. The voltage of the first node N1 is pulled down by the second reset control signal, and the driving transistor T3 is in a biased state. The second scan signal provided by the second scan line GL2 is at a low level, the compensation transistor T2 and the second control transistor T9 are both turned off, the first control transistor T10 is turned on, and the voltage of the third node N3 is the first reference voltage Vref1.

[0189] The third stage t73 may also be referred to as the threshold compensation stage. The second scan signal provided by the second scan line GL2 is at a high level, the compensation transistor T2 and the second control transistor T9 are both turned on, and the first control transistor T10 is turned off. In this stage, the driving transistor T3 is turned on, the threshold voltage Vth of the driving transistor T3 is written into the first node N1, the voltage of the first node N1 is Vdd + Vth, and Vdd is the first power supply voltage provided by the first power supply line VDD. The voltage of the second node N2 is the first power supply voltage Vdd.

[0190] The fourth stage t74 may also be referred to as the data writing stage. The first scan signal provided by the first scan line GL1 jumps to a low level, the data writing transistor T4 is turned on, and the data signal provided by the data line DL is written into the third node N3 through the turned-on data writing transistor T4.

[0191] The fifth stage t75 may also be referred to as the second bias stage. The second reset control signal provided by the second reset control line RST2 is at a low level, the second reset transistor T7 is turned on, and the potential of the first node N1 is pulled down by the second reset control signal, and the driving transistor T3 is in a biased state.

[0192] The sixth stage t76 can also be referred to as the light-emitting stage. The first control transistor T10 is turned on, and the voltage of the third node N3 is the first reference voltage Vref1. The second light-emitting control transistor T6 and the driving transistor T3 are turned on. The voltage of the first node N1 is Vdd + Vth + Vref1 - Vdata. The gate-source voltage difference Vgs of the driving transistor T3 is Vdd + Vth + Vref1 - Vdata - Vdd = Vth + Vref1 - Vdata. The driving current of the driving transistor T3 is: Id = 0.5×K×(Vgs - Vth) 2 = 0.5×K×(Vth + Vref1 - Vdata - Vth) 2 = 0.5×K×(Vref1 - Vdata) 2 .

[0193] Where K is a constant, Vdata is the data voltage, Vref1 is the first reference voltage, and Vth is the threshold voltage.

[0194] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving the display effect.

[0195] This example can separate the charging process of writing the data signal to the first node and the compensation process of the threshold voltage, can flexibly control the threshold compensation duration, and improve the threshold voltage compensation effect. Moreover, the third capacitor C3 and the first bias signal line can be used to control the first node N1 to bias the driving transistor.

[0196] Figure 25 It is a schematic diagram of another driving architecture of the pixel circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 25 shown, taking the pixel circuit included in the sub-pixel as Figure 23 shown as an example, the multiple gate driving circuits in this example may include: a first scan driving circuit (for example, including the first scan driving circuits 31a and 31b), a second scan driving circuit 32, a second light-emitting driving circuit 34, a first reset driving circuit 35, and a second reset driving circuit 36.

[0197] In some examples, the first scan driving circuits 31a and 31b may be located on both sides of the multiple sub-pixels along the first direction X. The first reset driving circuit 35 and the second reset driving circuit 36 may be located on both sides of the multiple sub-pixels along the first direction X. The second scan driving circuit 32 and the second light-emitting driving circuit 34 may be located on both sides of the multiple sub-pixels along the first direction X.

[0198] In some examples, the first scan driving circuit 31a, the second light-emitting driving circuit 34, and the second reset driving circuit 36 may be located on the same side of a plurality of sub-pixels along the first direction X, for example, all in the left border region. Within the left border region, the first scan driving circuit 31a, the second light-emitting driving circuit 34, and the second reset driving circuit 36 may be sequentially arranged along a direction away from the sub-pixels. The first scan driving circuit 31b, the second scan driving circuit 32, and the first reset driving circuit 35 may be located on the same side of a plurality of sub-pixels along the first direction X, for example, all in the right border region. Within the right border region, the first scan driving circuit 31b, the second scan driving circuit 32, and the first reset driving circuit 35 may be sequentially arranged along a direction away from the sub-pixels. The first scan signal in this example may adopt bilateral driving, and the remaining signals may adopt unilateral driving. In other examples, the first scan signal may adopt unilateral driving. The arrangement of the plurality of gate driving circuits in this example is beneficial to routing layout.

[0199] For the remaining descriptions of the driving architecture of the pixel circuit in this example, reference may be made to the descriptions of the foregoing embodiments, and thus will not be elaborated herein.

[0200] Figure 26 This is another equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 26 shown, the pixel circuit in this example may include: a driving transistor T3, a compensating transistor T2, a data writing transistor T4, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a second control transistor T9, a first control transistor T10, a first capacitor C1, a second capacitor C2, and a third capacitor C3. Among them, the first pole of the driving transistor T3 is coupled to the first power supply line VDD. The fifth node in this example is directly coupled to the first power supply line VDD. The first electrode of the third capacitor C3 is coupled to the first bias signal line V1, and the second electrode is coupled to the second node N2. The gates of the compensating transistor T2, the second control transistor T9, and the first control transistor T10 are all coupled to the second scan line GL2. The compensating transistor T2 and the second control transistor T9 in this example may both be N-type transistors, and the remaining transistors are all P-type transistors. For the remaining descriptions of the pixel circuit in this example, reference may be made to the descriptions of the foregoing embodiments, and thus will not be elaborated herein.

[0201] The working timing of the pixel circuit in this example may refer to Figure 24 the shown working timing diagram. This example can use the third capacitor and the first bias signal line to control the second node N2 to bias the driving transistor T3, which is beneficial to improving the afterimage effect. For the description of the working timing and the driving architecture of the pixel circuit in this example, reference may be made to the descriptions of the foregoing embodiments, and thus will not be elaborated herein.

[0202] Figure 27 Another equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 27 shown, the pixel circuit of this example may include: a driving transistor T3, a compensating transistor T2, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a second control transistor T9, a first control transistor T10, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4. Among them, the first electrode of the fourth capacitor C4 is coupled to the second bias signal line V2, and the second electrode is coupled to the fifth node N5. The gates of the compensating transistor T2, the second control transistor T9, and the first control transistor T10 are all coupled to the second scan line GL2. The second reset transistor T7, the compensating transistor T2, and the second control transistor T9 in this example may all be N-type transistors, and the remaining transistors are all P-type transistors. The remaining descriptions of the pixel circuit of this example may refer to the descriptions of the foregoing embodiments, so they will not be repeated here.

[0203] Figure 28 is Figure 27 the timing diagram of the operation of the pixel circuit shown. As Figure 27 shown, the pixel circuit of this example may include: 10 transistors (i.e., transistors T1 to T10), 3 capacitor units (i.e., the first capacitor C1, the second capacitor C2, and the fourth capacitor C4), 11 input terminals (i.e., the data line DL, the first scan line GL1, the second scan line GL2, the first light-emitting control line EM1, the second light-emitting control line EM2, the first reset control line RST1, the second reset control line RST2, the first reference voltage line REF1, the second coupling signal line V2, the first reset voltage line INIT1, and the second reset voltage line INIT2), and 2 power supply terminals (i.e., the first power supply line VDD and the second power supply line VSS).

[0204] In some examples, as Figure 28 shown, within a frame period, the operation process of the pixel circuit may include the following stages. In this example, it is described by taking the second coupling signal line V2 and the second reset control line RST2 providing the same signal as an example. In other words, the first electrode of the fourth capacitor C4 may be coupled to the second reset control line RST2.

[0205] The first stage t81 may also be referred to as the first reset stage. The first reset control signal provided by the first reset control line RST1 is at a low level, and the first reset transistor T1 is turned on. The second scan signal provided by the second scan line GL2 is at a high level, the compensating transistor T2 and the second control transistor T9 are both turned on, and the first control transistor T10 is turned off. The first node N1 is reset to the first reset voltage Vinit1.

[0206] The second stage t82 can also be referred to as the first biasing stage or the second reset stage. The second reset control signal provided by the second reset control line RST2 is at a high level, the second reset transistor T7 is turned on, and the sixth node N6 is reset to the second reset voltage Vinit2. The potential of the fifth node N5 is pulled up by the second reset control signal, driving the transistor T3 into a biased state. The second scan signal provided by the second scan line GL2 is at a low level, the compensation transistor T2 and the second control transistor T9 are both turned off, the first control transistor T10 is turned on, and the voltage of the third node N3 is the first reference voltage Vref1.

[0207] The third stage t83 can also be referred to as the threshold compensation stage. The second scan signal provided by the second scan line GL2 is at a high level, the compensation transistor T2 and the second control transistor T9 are both turned on, and the first control transistor T10 is turned off. In this stage, the driving transistor T3 is turned on, and the threshold voltage Vth of the driving transistor T3 is written into the first node N1. The voltage of the first node N1 is Vdd + Vth, where Vdd is the first power supply voltage provided by the first power supply line VDD. The voltage of the second node N2 is the first power supply voltage Vdd.

[0208] The fourth stage t84 can also be referred to as the data writing stage. The first scan signal provided by the first scan line GL1 jumps to a low level, the data writing transistor T4 is turned on, and the data signal provided by the data line DL is written into the third node N3 through the turned-on data writing transistor T4.

[0209] The fifth stage t85 can also be referred to as the second biasing stage. The second reset control signal provided by the second reset control line RST2 is at a high level, the second reset transistor T7 is turned on, the potential of the fifth node N5 is pulled up by the second reset control signal, and the driving transistor T3 is in a biased state.

[0210] The sixth stage t86 can also be referred to as the light emitting stage. The first control transistor T10 is turned on, and the voltage of the third node N3 is the first reference voltage Vref1. The first light emitting control transistor T5, the second light emitting control transistor T6, and the driving transistor T3 are turned on. The voltage of the first node N1 is Vdd + Vth + Vref1 - Vdata. The gate-source voltage difference Vgs of the driving transistor T3 is Vdd + Vth + Vref1 - Vdata - Vdd = Vth + Vref1 - Vdata. The driving current of the driving transistor T3 is: Id = 0.5×K×(Vgs - Vth) 2 = 0.5×K×(Vth + Vref1 - Vdata - Vth) 2 = 0.5×K×(Vref1 - Vdata) 2 .

[0211] Wherein, K is a constant, Vdata is the data voltage, Vref1 is the first reference voltage, and Vth is the threshold voltage.

[0212] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving the display effect.

[0213] This example can separate the charging process of writing the data signal to the first node and the compensation process of the threshold voltage, can flexibly control the threshold compensation duration, and improve the threshold voltage compensation effect. Moreover, the fourth capacitor and the second bias signal line can be used to control the fifth node N5 to bias the driving transistor T3, which is beneficial to improving the afterimage effect. The driving architecture of the pixel circuit in this example can refer to Figure 10 or Figure 13 the description of the embodiments shown, so it will not be elaborated here.

[0214] Figure 29 is another equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 29 shown, the pixel circuit of this example may include: a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a second control transistor T9, a first control transistor T10, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4. Wherein, the first electrode of the fourth capacitor C4 is coupled to the second bias signal line V2, and the second electrode is coupled to the fourth node N4. The gates of the compensation transistor T2, the second control transistor T9, and the first control transistor T10 are all coupled to the second scan line GL2. The second reset transistor T7, the compensation transistor T2, and the second control transistor T9 in this example may all be N-type transistors, and the rest of the transistors are all P-type transistors. The remaining descriptions of the pixel circuit in this example can refer to the descriptions of the foregoing embodiments, so it will not be elaborated here.

[0215] The working timing of the pixel circuit in this example can refer to Figure 28 the working timing diagram shown. This example can use the fourth capacitor and the second bias signal line to control the fourth node N4 to bias the driving transistor T3. The description of the working timing and the driving architecture of the pixel circuit in this example can refer to the descriptions of the foregoing embodiments, so it will not be elaborated here.

[0216] Figure 30 is a flowchart of the driving method of the pixel circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 30 shown, the driving method of the pixel circuit in this example may include the following steps: Step 701: Under the control of the second scan line, the compensation sub-circuit conducts the first node and the fourth node, so that the threshold voltage of the driving sub-circuit is written into the first node; Step 702: Under the control of the first scan line, the data writing sub-circuit writes the data signal provided by the data line into the third node; Step 703: Under the control of the first control line, the first control sub-circuit writes the first reference voltage signal provided by the first reference voltage line into the third node, so that the data signal is coupled to the first node through the coupling sub-circuit; Step 704: Under the control of the first node, the driving sub-circuit provides a driving signal to the fourth node.

[0217] In some examples, the duration for the data writing sub-circuit to write the data signal into the third node is less than the duration for the compensation sub-circuit to write the threshold voltage of the driving sub-circuit into the first node. The starting time for the data writing sub-circuit to write the data signal into the third node is later than the starting time for the compensation sub-circuit to write the threshold voltage of the driving sub-circuit into the first node. This example can be beneficial to improving the compensation effect of the threshold voltage, thus being beneficial to improving the uniformity of the screen display; moreover, the writing time of the data signal being later than the writing time of the threshold voltage can be beneficial to ensuring the validity of the data signal.

[0218] In some examples, the pixel circuit may further include: a second reset sub-circuit and a third reset sub-circuit; the second reset sub-circuit is coupled to a second reset control line, a second reset voltage line, and a sixth node, and the sixth node is coupled to a first electrode of the light-emitting element; the third reset sub-circuit is coupled to the second reset control line, a second reference voltage line, and a fifth node. The driving method of this example further includes at least one of the following: before the compensation sub-circuit writes the threshold voltage of the driving sub-circuit to the first node, the second reset sub-circuit writes a second reset voltage signal provided by the second reset voltage line to the sixth node under the control of the second reset control line, and the third reset sub-circuit writes a second reference voltage signal provided by the second reference voltage line to the fifth node under the control of the second reset control line; after the data writing sub-circuit writes the data signal provided by the data line to the third node, the second reset sub-circuit writes a second reset voltage signal provided by the second reset voltage line to the sixth node under the control of the second reset control line, and the third reset sub-circuit writes a second reference voltage signal provided by the second reference voltage line to the fifth node under the control of the second reset control line. In this example, before the compensation sub-circuit writes the threshold voltage of the driving sub-circuit to the first node, or after the data writing sub-circuit writes the data signal provided by the data line to the third node, setting the driving transistor in a biased state can play a role in calibrating the voltage and improving the afterimage.

[0219] In some examples, during the process that the driving sub-circuit provides a driving signal to the fourth node under the control of the first node, the first control line continuously provides an effective level signal. In the light-emitting stage of this example, the first control sub-circuit continuously writes a first reference voltage to the third node under the control of the first control line, which can be beneficial to improving the leakage situation of the third node.

[0220] For the driving method of the pixel circuit of this embodiment, reference may be made to the description of the foregoing embodiment, so it will not be elaborated here.

[0221] This embodiment further provides a display substrate, including: a plurality of sub-pixels and at least one first scan driving circuit, at least one of the plurality of sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light; the pixel circuit is the pixel circuit as described in the foregoing embodiment. The first scan driving circuit includes: a plurality of first scan driving units. The nth-level first scan driving unit is configured to provide a first scan signal to the pixel circuit of the nth-row sub-pixels; n is an integer greater than 0. Among them, the (2i - 1)th-level first scan driving unit is cascaded with the (2i + 1)th-level first scan driving unit, and the 2ith-level first scan driving unit is cascaded with the (2i + 2)th-level first scan driving unit, where i is an integer greater than 0.

[0222] In this embodiment, the multiple first scan driving units of the first scan driving circuit of the display substrate adopt a cascading method in which odd rows and even rows are separated, which can make the valid level signals output by adjacent two rows of first scan driving units overlap, leaving sufficient time for writing data signals, and making the Tr / Tf of the output signal smaller.

[0223] In some exemplary embodiments, the display substrate may further include: a first light-emitting driving circuit, the first light-emitting driving circuit including multiple cascaded first light-emitting driving units; the nth-level first light-emitting driving unit is configured to provide a first light-emitting control signal to the pixel circuit of the nth row of sub-pixels; or, configured to provide a first light-emitting control signal to the pixel circuits of the (2n - 1)th row and the 2nth row of sub-pixels.

[0224] In some exemplary embodiments, the display substrate may further include: a second scan driving circuit, a second light-emitting driving circuit; the second scan driving circuit includes multiple cascaded second scan driving units; the second light-emitting driving circuit includes multiple cascaded second light-emitting driving units. The nth-level second scan driving circuit is configured to provide a second scan signal to the pixel circuits of the (2n - 1)th row and the 2nth row of sub-pixels; the nth-level second light-emitting driving circuit is configured to provide a second light-emitting control signal to the pixel circuits of the (2n - 1)th row and the 2nth row of sub-pixels. Wherein, the second scan driving circuit and the second light-emitting driving circuit are located on the same side of the multiple sub-pixels along the row direction of the sub-pixels.

[0225] In some exemplary embodiments, the display substrate may further include: a first reset driving circuit, a second reset driving circuit; the first reset driving circuit includes multiple cascaded first reset driving units; the second reset driving circuit includes multiple cascaded second reset driving units. The nth-level first reset driving circuit is configured to provide a first reset control signal to the pixel circuits of the (2n - 1)th row and the 2nth row of sub-pixels; the nth-level second reset driving circuit is configured to provide a second reset control signal to the pixel circuits of the (2n - 1)th row and the 2nth row of sub-pixels. Wherein, the first reset driving circuit and the second reset driving circuit are located on both sides of the multiple sub-pixels along the row direction of the sub-pixels.

[0226] The description of the display substrate of this embodiment may refer to the description of the foregoing embodiments, so it will not be repeated here.

[0227] Figure 30 It is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, such as Figure 30As shown, this embodiment provides a display device 91, which includes the display substrate 910 of the foregoing embodiment. In some examples, the display substrate 910 may include an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 may be: any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator. However, this embodiment does not limit this.

[0228] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "examples", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0229] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A pixel circuit, comprising: A driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a coupling sub-circuit and a first control sub-circuit; The driving subcircuit is coupled to the first node, the fourth node and the fifth node, and is configured to provide a driving signal to the fourth node under the control of the first node; The data writing subcircuit is coupled to the first scan line, the data line and the third node, and is configured to write the data signal provided by the data line to the third node under the control of the first scan line; The compensation subcircuit is coupled to the second scan line, the first node and the fourth node, and is configured to conduct the first node and the fourth node under the control of the second scan line, so that the threshold voltage of the driving subcircuit is written into the first node; The coupling subcircuit is coupled to the first node and the third node; The first control subcircuit is coupled to the first control line, the third node and the first reference voltage line, and is configured to write the first reference voltage signal provided by the first reference voltage line to the third node under the control of the first control line after the data writing subcircuit writes the data signal to the third node, so that the data signal is coupled to the first node through the coupling subcircuit; The start time of the data writing subcircuit writing the data signal into the third node is later than the start time of the compensation subcircuit writing the threshold voltage of the driving subcircuit into the first node; the duration of the data writing subcircuit writing the data signal into the third node is shorter than the duration of the compensation subcircuit writing the threshold voltage of the driving subcircuit into the first node; The duration from the starting moment when the data writing sub-circuit writes the data signal to the third node to the starting moment when the compensation sub-circuit writes the threshold voltage of the driving sub-circuit to the first node is greater than the duration from the starting moment when the data writing sub-circuit writes the data signal to the third node to the ending moment when the compensation sub-circuit writes the threshold voltage of the driving sub-circuit to the first node.

2. The pixel circuit according to claim 1, wherein: The effective level signal provided by the second scan line is configured to control the compensation subcircuit to write the threshold voltage of the driving subcircuit into the first node; The end time when the data writing sub-circuit writes the data signal to the third node is a first time length away from the start time of the valid level signal provided by the second scan line, and the end time when the data writing sub-circuit writes the data signal to the third node is a second time length away from the end time of the valid level signal provided by the second scan line; the second time length is less than the first time length.

3. The pixel circuit according to claim 2, wherein: The end time of the data writing sub-circuit writing the data signal into the third node is the same as the end time of the effective level signal provided by the second scan line.

4. The pixel circuit according to claim 1, wherein: The effective level signal provided by the second scan line is configured to control the compensation subcircuit to write the threshold voltage of the driving subcircuit into the first node; The effective level signal provided by the second scan line includes the following three equally divided stages: a first signal stage, a second signal stage and a third signal stage, and the starting time of the effective level signal provided by the first scan line is after the first signal stage.

5. The pixel circuit according to claim 4, wherein: The starting time of the effective level signal provided by the first scanning line is located in the third signal stage.

6. The pixel circuit according to any one of claims 1 to 5, wherein: The coupling subcircuit comprises: a first coupling subcircuit and a second coupling subcircuit; the first coupling subcircuit is coupled to the first node and the second node, and the second coupling subcircuit is coupled to the second node and the third node; The pixel circuit also includes: a second control subcircuit, coupled to a second control line, the second node and the first voltage terminal, and configured to, under the control of the second control line, turn on the second node and the first voltage terminal so that the second coupling subcircuit stores the data signal written to the third node.

7. The pixel circuit according to claim 6, wherein: The first coupling subcircuit includes: a first capacitor; a first electrode of the first capacitor is coupled to the first node, and a second electrode of the first capacitor is coupled to the second node; The second coupling subcircuit includes: a second capacitor; a first electrode of the second capacitor is coupled to the second node, and a second electrode of the second capacitor is coupled to the third node; The compensation subcircuit comprises: a compensation transistor, a gate of the compensation transistor is coupled to the second scan line, a first electrode of the compensation transistor is coupled to the fourth node, and a second electrode of the compensation transistor is coupled to the first node; The second control subcircuit comprises: a second control transistor, a gate of the second control transistor is coupled to the second control line, a first electrode of the second control transistor is coupled to the first voltage terminal, a second electrode of the second control transistor is coupled to the second node; the first voltage terminal is coupled to the first power line; The compensation transistor and the second control transistor are oxide thin film transistors, and the second control line and the second scan line are configured to provide the same signal.

8. The pixel circuit according to any one of claims 1 to 5, wherein: The data writing sub-circuit comprises: a data writing transistor, a gate of the data writing transistor is coupled to the first scanning line, a first electrode of the data writing transistor is coupled to the data line, and a second electrode of the data writing transistor is coupled to the third node; The first control subcircuit comprises: a first control transistor, a gate of the first control transistor is coupled to the first control line, a first electrode of the first control transistor is coupled to the first reference voltage line, and a second electrode of the first control transistor is coupled to the third node; The compensation subcircuit includes: a compensation transistor, a gate of the compensation transistor is coupled to the second scan line, a first electrode of the compensation transistor is coupled to the fourth node, and a second electrode of the compensation transistor is coupled to the first node.

9. The pixel circuit according to claim 8, wherein: The data writing transistor and the first control transistor are of the same transistor type and are different from the compensation transistor; the first control line and the second scan line are configured to provide the same signal.

10. The pixel circuit according to claim 8, further comprising: The first light-emitting control subcircuit is coupled to the first light-emitting control line, the first power line and the fifth node, and is configured to write the first power signal provided by the first power line to the fifth node under the control of the first light-emitting control line; the first control line and the first light-emitting control line are configured to provide the same signal.

11. The pixel circuit according to claim 8, wherein: The data writing transistor and the first control transistor are of different transistor types, and the data writing transistor and the compensation transistor are of the same transistor type; The pixel circuit further includes: A second light-emitting control subcircuit is coupled to a second light-emitting control line, the fourth node and the sixth node, and is configured to conduct the fourth node and the sixth node under the control of the second light-emitting control line, wherein the sixth node is coupled to the first electrode of the light-emitting element; A fourth reset subcircuit is coupled to the third node, the first reference voltage line and the third reset control line, and is configured to write the first reference voltage signal provided by the first reference voltage line to the third node under the control of the third reset control line; the first control line and the second light-emitting control line are configured to provide the same signal.

12. The pixel circuit according to any one of claims 1 to 5, further comprising: a first reset subcircuit coupled to the first reset control line, the first reset voltage line and the fourth node, and configured to write the first reset voltage signal provided by the first reset voltage line to the fourth node under the control of the first reset control line; or, the first reset subcircuit coupled to the first reset control line, the first reset voltage line and the first node, and configured to write the first reset voltage signal provided by the first reset voltage line to the first node under the control of the first reset control line; The second reset subcircuit is coupled to the second reset control line, the second reset voltage line and the sixth node, and is configured to write the second reset voltage signal provided by the second reset voltage line to the sixth node under the control of the second reset control line, and the sixth node is coupled to the first electrode of the light-emitting element.

13. The pixel circuit according to claim 12, further comprising: The third reset subcircuit is coupled to the second reset control line, the second reference voltage line and the fifth node, and is configured to write the second reference voltage signal provided by the second reference voltage line to the fifth node under the control of the second reset control line.

14. The pixel circuit according to claim 12, further comprising: A third capacitor, wherein a first electrode of the third capacitor is coupled to the first bias signal line, and a second electrode of the third capacitor is coupled to the first node or the second node.

15. The pixel circuit according to claim 12, further comprising: A fourth capacitor, wherein a first electrode of the fourth capacitor is coupled to the second bias signal line, and a second electrode of the fourth capacitor is coupled to the fourth node or the fifth node.

16. A driving method for a pixel circuit, applied to the pixel circuit according to any one of claims 1 to 15, the driving method comprising: The compensation subcircuit, under the control of the second scan line, conducts the first node and the fourth node, so that the threshold voltage of the driving subcircuit is written into the first node; The data writing subcircuit writes the data signal provided by the data line into the third node under the control of the first scanning line; The first control subcircuit writes the first reference voltage signal provided by the first reference voltage line to the third node under the control of the first control line, so that the data signal is coupled to the first node through the coupling subcircuit; The driving sub-circuit provides a driving signal to the fourth node under the control of the first node.

17. A display substrate, comprising: A plurality of sub-pixels and at least one first scan driving circuit, wherein at least one sub-pixel of the plurality of sub-pixels comprises a light-emitting element and a pixel circuit for driving the light-emitting element to emit light; The pixel circuit is a pixel circuit as claimed in any one of claims 1 to 15; The first scan driving circuit comprises: a plurality of first scan driving units; The n-th level first scan driving unit is configured to provide a first scan signal to the pixel circuit of the n-th row of sub-pixels; n is an integer greater than 0; The 2i-1th first scan driving unit is cascaded with the 2i+1th first scan driving unit, the 2ith first scan driving unit is cascaded with the 2i+2nd first scan driving unit, and i is an integer greater than 0.

18. The display substrate according to claim 17, further comprising: A first light-emitting driving circuit, a second scanning driving circuit, and a second light-emitting driving circuit, wherein the first light-emitting driving circuit comprises a plurality of cascaded first light-emitting driving units; The second scan driving circuit includes a plurality of cascaded second scan driving units; The second light-emitting driving circuit comprises a plurality of cascaded second light-emitting driving units; The n-th stage first light-emitting driving unit is configured to provide a first light-emitting control signal to the pixel circuit of the n-th row of sub-pixels; Alternatively, it is configured to provide the first light emitting control signal to the pixel circuits of the sub-pixels in the 2n-1th row and the 2nth row; The n-th stage second scan driving circuit is configured to provide a second scan signal to the pixel circuits of the sub-pixels in the 2n-1th and 2nth rows; The n-th stage second light-emitting driving circuit is configured to provide a second light-emitting control signal to the pixel circuits of the sub-pixels in the 2n-1th and 2nth rows; The second scanning driving circuit and the second light emitting driving circuit are located on the same side of the plurality of sub-pixels along a row direction of the sub-pixels.

19. The display substrate according to claim 17, further comprising: A first reset driving circuit and a second reset driving circuit; The first reset driving circuit comprises a plurality of cascaded first reset driving units; The second reset drive circuit includes a plurality of cascaded second reset drive units; the n-th level first reset drive circuit is configured to provide a first reset control signal to the pixel circuits of the 2n-1th and 2nth rows of sub-pixels; the n-th level second reset drive circuit is configured to provide a second reset control signal to the pixel circuits of the 2n-1th and 2nth rows of sub-pixels; wherein the first reset drive circuit and the second reset drive circuit are located on different sides of the plurality of sub-pixels along the row direction of the sub-pixels.

20. A display device comprising the display substrate according to any one of claims 17 to 19.

Images