Display device

Abstract

A display device includes a display panel in which a display area is defined and a timing controller. The display panel includes a plurality of blocks each including a plurality of pixels, and the timing controller generates a representative compensation value with respect to each of the blocks. The display area includes a first area and a second area, a boundary line is defined between the first area and the second area, the blocks include a first block adjacent to the boundary line and a second block spaced apart from the boundary line, the timing controller generates a flag signal with respect to the first block, the timing controller generates a first compensation value based on the flag signal, and the timing controller generates a second compensation value based on the first compensation value. And the timing controller generates a second compensation value using the representative compensation value of the second block and a representative compensation value of another block adjacent to the second block among the blocks.

Description

[0001] This application claims the priority of and all rights arising from Korean Patent Application No. 10-2023-0195460, filed on December 28, 2023, the content of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device having improved display quality. Background Art

[0003] A display device includes various electronic components such as a display panel for displaying an image, an input sensor for sensing an external input, and an electronic module. The electronic components are electrically connected to each other through signal lines arranged in various ways. The display panel includes a plurality of pixels. Each of the pixels includes a light-emitting element that generates light and a pixel driving circuit that controls a current flowing through the light-emitting element. Summary of the Invention

[0004] The present disclosure provides a display device having improved display quality.

[0005] Embodiments of the inventive concept provide a display device including a display panel in which a display area is defined and a timing controller. The display panel includes a plurality of blocks each including a plurality of pixels, and the timing controller generates a representative compensation value for each of the plurality of blocks. The display area includes a first area in which a first image is displayed and a second area in which a second image different from the first image is displayed, and the second area is spaced apart from the first area in a predetermined direction. A boundary line is defined between the first area and the second area, the plurality of blocks include a first block adjacent to the boundary line and a second block spaced apart from the boundary line, the timing controller generates a flag signal for the first block, the timing controller generates a first compensation value for the first block based on the flag signal, and the timing controller generates a second compensation value different from the first compensation value for the second block using the representative compensation value of the second block and the representative compensation value of another block adjacent to the second block among the plurality of blocks.

[0006] In an embodiment, the first block is provided as a plurality, and the plurality of first blocks include: a first-first block; and a first-second block spaced apart from the first-first block, with the boundary line being between the first-first block and the first-second block.

[0007] In an embodiment, a plurality of first pixel units each including at least one pixel among the plurality of pixels are defined in the first-first block, a plurality of second pixel units each including at least one pixel among the plurality of pixels are defined in the first-second block, and the timing controller generates a plurality of first pixel compensation values for the plurality of first pixel units respectively, and generates a plurality of second pixel compensation values for the plurality of second pixel units respectively.

[0008] In an embodiment, the first compensation value of the first-first block is the first average value of a plurality of first pixel compensation values, and the first compensation value of the first-second block is the second average value of a plurality of second pixel compensation values.

[0009] In an embodiment, the first-first block is disposed in a first region, the first-second block is disposed in a second region, and the first average value is different from the second average value.

[0010] In an embodiment, the second image is a black image.

[0011] In an embodiment, a plurality of second blocks are provided, and the first block is disposed between the plurality of second blocks.

[0012] In an embodiment, the first block includes a first block portion and a second block portion adjacent to the first block portion, and a boundary line is between the first block portion and the second block portion.

[0013] In an embodiment, a plurality of first pixel units each including at least one pixel among a plurality of pixels are defined in the first block portion, a plurality of second pixel units each including at least one pixel among a plurality of pixels are defined in the second block portion, and the timing controller generates a plurality of first pixel compensation values respectively for the plurality of first pixel units, and generates a plurality of second pixel compensation values respectively for the plurality of second pixel units.

[0014] In an embodiment, the first compensation value of the first block portion is the first average value of a plurality of first pixel compensation values, and the first compensation value of the second block portion is the second average value of a plurality of second pixel compensation values.

[0015] In an embodiment, the timing controller generates the first compensation value only using the representative compensation value of the first block.

[0016] In an embodiment, the first block includes a first block portion and a second block portion adjacent to the first block portion, and the timing controller generates partial compensation values for each of the first block portion and the second block portion.

[0017] In an embodiment, the second compensation value is generated by adding the representative compensation value of the second block and a value obtained by interpolating the representative compensation value of the other block adjacent to the second block among a plurality of blocks.

[0018] Embodiments of the inventive concept provide a display device including a display panel in which a display area is defined and a timing controller. The display panel includes a plurality of blocks each including a plurality of pixels, and the timing controller generates representative compensation values for each of the plurality of blocks. The display area includes a first area in which a first image is displayed and a second area in which a second image different from the first image is displayed, and the second area is spaced apart from the first area in a predetermined direction. A boundary line is defined between the first area and the second area, the plurality of blocks include a first block adjacent to the boundary line and a second block spaced apart from the boundary line, the timing controller generates a first compensation value for the first block in a first unit, and the timing controller generates a second compensation value for the second block in a second unit greater than the first unit.

[0019] In an embodiment, a plurality of first blocks are provided, and the plurality of first blocks include: a first-first block; and a first-second block spaced apart from the first-first block, with the boundary line therebetween.

[0020] In an embodiment, the first unit is defined as a pixel unit including at least one pixel among the plurality of pixels, the pixel unit includes a plurality of first pixel units defined in the first-first block and a plurality of second pixel units defined in the first-second block, and the timing controller generates a plurality of first pixel compensation values for the plurality of first pixel units respectively, and generates a plurality of second pixel compensation values for the plurality of second pixel units respectively.

[0021] In an embodiment, the first compensation value of the first-first block is a first average value of the plurality of first pixel compensation values, and the first compensation value of the first-second block is a second average value of the plurality of second pixel compensation values.

[0022] In an embodiment, the first-first block is disposed in the first area, the first-second block is disposed in the second area, and the first average value is different from the second average value.

[0023] In an embodiment, the second image is a black image.

[0024] In an embodiment, the second compensation value is generated by adding the representative compensation value of the second block and a value obtained by interpolating the representative compensation value of another block adjacent to the second block among the plurality of blocks.

[0025] According to the above, the timing controller generates a first compensation value for a first block adjacent to the boundary line in units of pixels, and generates a second compensation value for a second block spaced apart from the boundary line in units of blocks. Since the compensation process is performed in units of pixels in the block adjacent to the boundary line, a decrease in the compensation value in a portion adjacent to the boundary line in the first region is prevented. Accordingly, an afterimage appearing in the display panel is reduced or eliminated. Consequently, a display device having improved display quality is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other advantages of the present disclosure will become apparent from the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0027] Figure 1A is a perspective view of an embodiment of a display device operating in a first mode according to the present disclosure;

[0028] Figure 1B is a perspective view of an embodiment of a display device operating in a second mode according to the present disclosure;

[0029] Figure 2 is an exploded perspective view of an embodiment of a display device according to the present disclosure;

[0030] Figure 3 is a block diagram of an embodiment of a display device according to the present disclosure;

[0031] Figure 4 is a plan view of an embodiment of a display area of a display panel in a second mode according to the present disclosure;

[0032] Figure 5 is a timing diagram of an embodiment of a display device according to the present disclosure;

[0033] Figure 6 is a plan view of an embodiment of a display area of a display panel in a second mode according to the present disclosure;

[0034] Figure 7 is a timing diagram of an embodiment of a display device according to the present disclosure;

[0035] Figure 8 is a timing diagram of an embodiment of a display device according to the present disclosure; and

[0036] Figure 9 is a timing diagram of an embodiment of a display device according to the present disclosure. DETAILED DESCRIPTION

[0037] In the present disclosure, it will be understood that when an element (or region, layer, or portion) is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present.

[0038] Like reference numerals refer to like elements throughout. In the figures, the thickness, ratios, and dimensions of components are exaggerated for effective description of the technical content. As used herein, the term "and / or" can include any and all combinations of one or more of the associated listed items.

[0039] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "the" are also intended to include the plural forms.

[0040] For ease of description, spatial relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures.

[0041] It will be further understood that when used in this specification, the terms "comprises" and / or "comprising" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0043] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0044] Figure 1A is a perspective view of an embodiment of a display device DD operating in a first mode according to the present disclosure. Figure 1B is a perspective view of an embodiment of a display device DD operating in a second mode according to the present disclosure.

[0045] ReferenceFigure 1A and Figure 1B The display device DD may be a device that is activated in response to an electrical signal. The display device DD may be applied to a television, a monitor, an outdoor billboard, or a vehicle. However, the present disclosure should not be limited to this or restricted by this. The display device DD may be applied to small and medium-sized display devices such as personal computers, laptop computers, personal digital terminals, gaming units, mobile electronic devices, or cameras. The display device DD in the illustrated embodiment may be a flexible electronic device. In an embodiment, the display device DD may be a foldable, rollable, slidable, or stretchable electronic device. However, these are merely illustrative embodiments, and the display device DD may be applied to other electronic devices as long as they do not depart from the concept of the present disclosure.

[0046] The display device DD may have a quadrilateral shape, for example, a rectangular shape defined by a long side extending in a first direction DR1 and a short side extending in a second direction DR2 that intersects the first direction DR1. However, the shape of the display device DD should not be limited to a rectangular shape, and the display device DD may have various shapes. The display device DD may display an image IM toward a third direction DR3 through a display surface IS that is substantially parallel to each of the first direction DR1 and the second direction DR2. The display surface IS through which the image IM is displayed may correspond to the front surface of the display device DD.

[0047] The display device DD in the illustrated embodiment may be a display device for a vehicle. The display device DD may be driven in a first mode when the vehicle is stationary and in a second mode when the vehicle is in motion. As Figure 1A shown, the display device DD may display an image IM through an active area AA during the first mode. When the first mode is switched to the second mode or vice versa, the display device DD may move in the second direction DR2 or the direction opposite to the second direction DR2 to expose a part of the display surface IS. As Figure 1B shown, the display device DD may display a first image IM1 through a part of the active area AA and may display a second image IM2 through another part of the active area AA during the second mode. This will be described in detail later.

[0048] In the illustrated embodiment, the front (or upper) and rear (or lower) surfaces of each member may be defined with respect to the direction in which the image IM is displayed thereon. The front surface and the rear surface may be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be substantially parallel to the third direction DR3.

[0049] The separation distance in the third direction DR3 between the front surface and the rear surface may correspond to the thickness of the display device DD in the third direction DR3. The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 may be relative to each other and may be changed to other directions.

[0050] The display surface IS of the display device DD may include an effective area AA and an ineffective area NAA. The effective area AA may be the area through which the image IM is displayed. The user may view the image IM through the effective area AA. In the illustrated embodiment, the effective area AA may have a quadrilateral shape with rounded vertices. However, this is only one of the embodiments. The effective area AA may have various shapes and should not be particularly limited.

[0051] The non-effective area NAA may be defined adjacent to the effective area AA. In the specification, the term "adjacent to" may mean "substantially close to" (such as "next to"). The ineffective area NAA may have a predetermined color. The ineffective area NAA may surround the effective area AA. Accordingly, the effective area AA may have a shape substantially defined by the ineffective area NAA. However, this is only one of the embodiments. In an embodiment, the ineffective area NAA may be provided adjacent to only one side of the effective area AA or may be omitted. The display device DD may include various embodiments and should not be particularly limited.

[0052] The effective area AA may include a first area AA1 and a second area AA2. The first area AA1 may be the area recognized by the user, and the second area AA2 may be the area not recognized by the user. The display device DD may display the image IM through the effective area AA during the first mode. The display device DD may display the first image IM1 through the first area AA1 during the second mode. The display device DD may display the second image IM2 through the second area AA2 during the second mode. The second image IM2 may be a black image.

[0053] The display device DD may sense an external input applied to it from the outside. The external input may include various forms of input provided from the outside of the display device DD. The display device DD may sense the external input of the user and applied to it. The external input of the user may include one of various forms of external input such as a part of the user's body, light, heat, gaze, or pressure or any combination thereof. Additionally, depending on the structure of the display device DD, the display device DD may sense the external input applied to its side surface or rear surface by the user. However, it should not be particularly limited. In an embodiment, the external input may include the input generated by an input device such as a stylus, an active pen, a touch pen, an electronic pen, or an e-pen.

[0054] The display device DD may have an appearance defined by a window WM and a housing EDC. In an embodiment, the window WM may be combined with the housing EDC to provide an internal space of the housing EDC, and other components of the display device DD (e.g., the display module DM (refer to Figure 2 )) may be accommodated in the internal space of the housing EDC.

[0055] The front surface of the window WM may define a display surface IS of the display device DD. The window WM may include an optically transparent insulating material. In an embodiment, the window WM may include a glass material or a plastic material. The window WM may have a single-layer or multi-layer structure. In an embodiment, the window WM may include a plurality of plastic films bonded to each other by an adhesive, or a glass substrate and a plastic film bonded to the glass substrate by an adhesive.

[0056] The housing EDC may include a material having relatively high rigidity. In an embodiment, the housing EDC may include a plurality of frames and / or plates, the plurality of frames and / or plates including glass, plastic, metal materials or a combination thereof or consisting of glass, plastic, metal materials or a combination thereof. The housing EDC can stably protect the components of the display device DD accommodated in the internal space from external impacts. Although not shown in Figure 1A and Figure 1B , a battery module that supplies power required for the overall operation of the display device DD may be disposed between the display module DM and the housing EDC.

[0057] Figure 2 is an exploded perspective view of the display device DD according to the present disclosure.

[0058] Refer to Figure 2 , the display device DD may include a display module DM and a window WM disposed on the display module DM. The display module DM may include a display panel DP and an input sensing layer ISP.

[0059] The display panel DP may be a light-emitting type display panel. In an embodiment, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots or quantum rods.

[0060] The display panel DP may output an image IM and may display the output image IM through the display surface IS.

[0061] The input sensing layer ISP may be disposed on the display panel DP and may sense an external input. The input sensing layer ISP may be directly disposed on the display panel DP. In the illustrated embodiment, the input sensing layer ISP may be formed on the display panel DP through a continuous process. That is, when the input sensing layer ISP is directly disposed on the display panel DP, an internal adhesive film may not be disposed between the input sensing layer ISP and the display panel DP. However, the internal adhesive film may be disposed between the input sensing layer ISP and the display panel DP. In this case, the input sensing layer ISP may not be manufactured through a continuous process with the display panel DP, and the input sensing layer ISP may be fixed to the upper surface of the display panel DP by the internal adhesive film after being manufactured through a separate process.

[0062] Although not shown in Figure 2 , the non-active area NAA of the display device DD may be provided as an area obtained by printing a material having a predetermined color on the area of the window WM. In an embodiment, the window WM may include a light-shielding pattern to define the non-active area NAA. The light-shielding pattern may be a colored organic layer and may be formed by a coating method.

[0063] The window WM may be bonded to the display module DM through an adhesive film. In an embodiment, the adhesive film may include an optically clear adhesive (OCA) film. However, the adhesive film should not be limited to this or restricted by this, and the adhesive film may include a conventional adhesive. In an embodiment, for example, the adhesive film may include an optically clear resin (OCR) or a pressure-sensitive adhesive (PSA) film.

[0064] An anti-reflection layer may be further disposed between the window WM and the display module DM. The anti-reflection layer may reduce the reflectance of external light incident on it from above the window WM. The anti-reflection layer according to the present disclosure may include a retarder and a polarizer. The retarder may be of a film type or a liquid crystal coating type. The polarizer may be of a film type or a liquid crystal coating type. The film type polarizer and the film type retarder may include a stretched synthetic resin film, and the liquid crystal coating type polarizer and the liquid crystal coating type retarder may include liquid crystals arranged in a predetermined orientation. The retarder and the polarizer may be implemented as one polarizing film.

[0065] In an embodiment, the anti-reflection layer may include a color filter. The arrangement of the color filter may be determined by considering the color of light generated by the pixels PX (refer to Figure 3 ) included in the display panel DP. In this case, the anti-reflection layer may further include a light-shielding pattern disposed between the color filters.

[0066] The display module DM can display an image IM in response to an electrical signal and can send / receive information regarding an external input. The display panel DP can include a display area DA and a non-display area NDA defined therein. The display area DA can be defined as the area through which the image IM provided by the display panel DP exits, i.e., the area through which the image IM is displayed. Additionally, the display area DA can be defined as the area where the input sensing layer ISP senses an external input applied thereto from the outside. In an embodiment, the display area DA of the display module DM can correspond to or overlap at least a part of the active area AA.

[0067] The non-display area NDA can be defined adjacent to the display area DA. The non-display area NDA can be an area where the image IM is not displayed. In an embodiment, for example, the non-display area NDA can surround the display area DA. However, this is only one of the embodiments, and the non-display area NDA can be defined in various shapes and should not be particularly limited. According to an embodiment, the non-display area NDA of the display module DM can correspond to or overlap at least a part of the inactive area NAA.

[0068] The display device DD can further include a plurality of flexible films FF. The data driver DIC can be disposed (e.g., mounted) on each of the flexible films FF. In an embodiment, the data driver DIC can be provided in plurality, and the data driver DIC can be respectively disposed (e.g., mounted) on the flexible films FF.

[0069] The display device DD can further include at least one circuit board PCB coupled to the flexible films FF. Figure 2 A structure is shown in which the display device DD includes two circuit boards PCB. However, the number of the circuit boards PCB should not be limited to two. Among the circuit boards PCB, two circuit boards PCB adjacent to each other can be electrically connected to each other through a connection film CF. Additionally, at least one of the circuit boards PCB can be electrically connected to the main board. The timing controller TCON (refer to Figure 3 ) can be disposed (e.g., mounted) on the circuit board PCB.

[0070] Figure 2 A structure is shown in which the data driver DIC is respectively disposed (e.g., mounted) on the flexible films FF. However, the present disclosure should not be limited to this or restricted by this. In an embodiment, the data driver DIC can be directly disposed (e.g., mounted) on the display panel DP. In this case, the part of the display panel DP on which the data driver DIC is disposed (e.g., mounted) can be bent and can be disposed on the rear surface of the display device DD.

[0071] The input sensing layer ISP can be electrically connected to the circuit board PCB via the flexible film FF. However, the present disclosure should not be limited to this or restricted by this. That is to say, the display module DM can further include a separate flexible film to electrically connect the input sensing layer ISP to the circuit board PCB.

[0072] The outer case EDC can absorb the impact applied to it from the outside and can prevent foreign substances / moisture from entering the display module DM to protect the components housed in the outer case EDC. In an embodiment, the outer case EDC can be obtained by assembling a plurality of housing members.

[0073] The display device DD can further include an electronic module including various functional modules for operating the display module DM, a power supply module (e.g., a battery) for supplying the power required for the overall operation of the display device DD, and a bracket combined with the display module DM and / or the outer case EDC to divide the internal space of the display device DD.

[0074] Figure 3 is a block diagram of an embodiment of the display device DD according to the present disclosure.

[0075] Reference Figure 3 , the display device DD can include a display panel DP, a timing controller TCON, and a data driver DIC.

[0076] The timing controller TCON can receive input data RGB and a control signal D-CS from an external controller (not shown). In an embodiment, the external controller (not shown) can be a graphics processing unit (GPU). The control signal D-CS can include various signals. In an embodiment, the control signal D-CS can include an input vertical synchronization signal, an input horizontal synchronization signal, a main clock, and a data enable signal.

[0077] The timing controller TCON can convert the data format of the input data RGB into a data format suitable for the interface between the data driver DIC and the timing controller TCON and can generate image data DS. In this case, the timing controller TCON can perform an operation to compensate for afterimage to generate the image data DS. The timing controller TCON can generate a representative compensation value for each of a plurality of blocks BLK (reference Figure 4 ). This will be described in detail later.

[0078] The timing controller TCON can generate a scan control signal SCS, a data control signal DCS, and a flag signal FG based on the control signal D-CS (reference Figure 5 ).

[0079] The data driver DIC can output grayscale voltages in response to a data control signal DCS and image data DS from a timing controller TCON to drive a plurality of data lines DL1 to DLm. Here, m is a natural number. The data driver DIC can be implemented as an integrated circuit and can be directly disposed (e.g., mounted) on a predetermined portion of the display panel DP, or can be electrically connected to the display panel DP after being disposed (e.g., mounted) on a separate printed circuit board by a chip-on-film method, but it should not be particularly limited. In an embodiment, the data driver DIC can be formed by the same process as the circuit layer of the display panel DP.

[0080] The display panel DP can include a display area DA and a non-display area NDA. Pixels PX can be arranged in the display area DA, and a scan driver SDC can be disposed in the non-display area NDA.

[0081] The display panel DP can include a plurality of scan lines SL1 to SLn, data lines DL1 to DLm, pixels PX, and a scan driver SDC. Each of the pixels PX can be connected to a corresponding data line among the data lines DL1 to DLm and a corresponding scan line among the scan lines SL1 to SLn. Here, n is a natural number. The display panel DP can further include an emission control line (not shown), and the display device DD can further include an emission driver (not shown) that applies a control signal to the emission control line. The configuration of the display panel DP should not be particularly limited.

[0082] The scan lines SL1 to SLn can extend in a direction parallel to the first direction DR1 and can be substantially parallel to each other. The scan lines SL1 to SLn can be arranged to be spaced apart from each other in the second direction DR2. The data lines DL1 to DLm can extend from the data driver DIC in a direction parallel to the second direction DR2 and can be substantially parallel to each other. The data lines DL1 to DLm can be arranged to be spaced apart from each other in the first direction DR1.

[0083] The pixels PX can be electrically connected to the scan lines SL1 to SLn and the data lines DL1 to DLm. In an embodiment, the pixels arranged in the first row can be connected to the scan line SL1, and the pixels arranged in the first column can be connected to the data line DL1.

[0084] The scan driver SDC can drive scan lines SL1 to SLn in response to a scan control signal SCS. The scan driver SDC can be formed by the same process as the circuit layer of the display panel DP. However, it should not be limited to this or restricted by this. In an embodiment, the scan driver SDC can be implemented as an integrated circuit and can be directly disposed (e.g., mounted) on a predetermined portion of the display panel DP, or can be electrically connected to the display panel DP after being disposed (e.g., mounted) on a separate printed circuit board by a chip-on-film method.

[0085] Figure 4 is a plan view of an embodiment of a display area of the display panel DP in a second mode according to the present disclosure. Figure 4 Shows a structure in which a boundary line BL is defined between two blocks without overlapping the blocks in the second mode.

[0086] Reference Figure 3 and Figure 4 , a display area DA can be defined in the display panel DP. The display area DA can include a first area AA1 and a second area AA2 spaced apart from the first area AA1 in a direction opposite to the second direction DR2. A boundary line BL can be defined between the first area AA1 and the second area AA2.

[0087] A first image IM1 can be displayed through the first area AA1 (reference Figure 1B ), and a second image IM2 different from the first image IM1 can be displayed through the second area AA2 (reference Figure 1B ). In an embodiment, the second image IM2 (reference Figure 1B ) can be a black image.

[0088] The display panel DP can include a plurality of blocks BLK. Each of the blocks BLK can extend in a first direction DR1. The blocks BLK can be arranged in a second direction DR2. Each of the blocks BLK can include a plurality of pixels PX. Each of the blocks BLK can include a plurality of pixel rows arranged in the first direction DR1. The display area DA can be defined by the blocks BLK.

[0089] The block BLK can include at least one first block BLK1 and at least one second block BLK2. The first block BLK1 can be provided adjacent to the boundary line BL, and the second block BLK2 can be spaced apart from the boundary line BL. Each of the first block BLK1 and the second block BLK2 can be provided in plurality. The first block BLK1 can be disposed between the second block BLK2. In Figure 4Among them, the blocks in the block BLK that are arranged at the third position and the fourth position in the direction opposite to the second direction DR2 are shown as the first block BLK1, and the blocks in the block BLK that are arranged at the first position, the second position, the fifth position, and the sixth position in the direction opposite to the second direction DR2 are shown as the second block BLK2.

[0090] The first block BLK1 may include a first-first block BLK1-1 and a first-second block BLK1-2. The first-second block BLK1-2 may be spaced apart from the first-first block BLK1-1, and a boundary line BL is between the first-first block BLK1-1 and the first-second block BLK1-2. The first-first block BLK1-1 may be arranged in the first area AA1, and the first-second block BLK1-2 may be arranged in the second area AA2.

[0091] The timing controller TCON may generate a representative compensation value for each of the blocks BLK. In the illustrated embodiment, when the timing controller TCON performs an afterimage compensation process on the input data RGB, the timing controller TCON may use the representative compensation value compensated in units of blocks (hereinafter, also referred to as block units). The representative compensation value may be a basic compensation value for the luminance difference in each block unit. The amount of calculation processed by the timing controller TCON can be reduced by the representative compensation value. Accordingly, the display quality and reliability of the display device DD can be improved.

[0092] The timing controller TCON may generate a flag signal FG with respect to the first block BLK1 (refer to Figure 5 ). That is, the timing controller TCON may generate a flag signal FG for each of the first-first block BLK1-1 and the first-second block BLK1-2 (refer to Figure 5 ). The flag signal FG (refer to Figure 5 ) may be a signal for defining the first block BLK1 among the blocks BLK that defines the boundary line BL.

[0093] The timing controller TCON may divide both the first-first block BLK1-1 and the first-second block BLK1-2 into a first unit. The first unit may be defined as a unit at the pixel level (hereinafter, also referred to as a pixel unit) including at least one pixel among the pixels PX. The pixel unit may include a plurality of first pixel units PXG1 and a plurality of second pixel units PXG2.

[0094] The first pixel units PXG1 each including at least one pixel among the pixels PX may be defined in the first-first block BLK1-1. Each of the first pixel units PXG1 may include a first-first pixel unit PXG1a and a first-second pixel unit PXG1b. Figure 4As an illustrative embodiment, a structure is shown in which two pixels PX are grouped into one pixel unit PXG1a or PXG1b. However, the number of pixels included in one pixel unit PXG1a or PXG1b should not be limited to this or restricted by this.

[0095] Second pixel units PXG2, each including at least one of the pixels PX, may be defined in the first - second block BLK1 - 2. Each of the second pixel units PXG2 may include a second - first pixel unit PXG2a and a second - second pixel unit PXG2b.

[0096] Figure 5 is a timing diagram of an embodiment of a display device according to the present disclosure.

[0097] Reference Figures 3 to 5 , the timing controller TCON may generate a compensation value CPV for each of the blocks BLK.

[0098] As Figure 5 shown in the timing diagram of, the blocks BLK may operate respectively in sequence in response to a plurality of time periods SS. In an embodiment, the block at the first position among the blocks BLK may operate corresponding to the first time period in the time periods SS. The block at the second position among the blocks BLK may operate corresponding to the second time period in the time periods SS. The block at the third position among the blocks BLK may operate corresponding to the third time period in the time periods SS. The block at the fourth position among the blocks BLK may operate corresponding to the fourth time period in the time periods SS. The block at the fifth position among the blocks BLK may operate corresponding to the fifth time period in the time periods SS. The block at the sixth position among the blocks BLK may operate corresponding to the sixth time period in the time periods SS.

[0099] The timing controller TCON may output image data DS obtained by reflecting the compensation value CPV in the input data RGB to the data driver DIC. The compensation value CPV may include a first compensation value and a second compensation value generated by a method different from the method of generating the first compensation value.

[0100] The flag signal FG may be in an active state in the time period corresponding to the first block BLK1, and may be in an inactive state in the time period corresponding to the second block BLK2.

[0101] The timing controller TCON may generate a first compensation value for the first block BLK1 based on the flag signal FG. When the flag signal FG is in an active state, the timing controller TCON may generate the first compensation value for the corresponding block (the first block BLK1) among the blocks BLK in a first unit.

[0102] The timing controller TCON may generate a plurality of first pixel compensation values for a first pixel unit PXG1 of a first-first block BLK1-1. The timing controller TCON may calculate a first average value of the first pixel compensation values. The timing controller TCON may generate the first average value as a first compensation value applied to the first-first block BLK1-1.

[0103] The timing controller TCON may generate a plurality of second pixel compensation values for a second pixel unit PXG2 of a first-second block BLK1-2. The timing controller TCON may calculate a second average value of the second pixel compensation values. The timing controller TCON may generate the second average value as a second compensation value applied to the first-second block BLK1-2.

[0104] In this case, the first average value may be different from the second average value. In an embodiment, the first average value for compensating the first-first block BLK1-1 in which a first image IM1 including a normal image (or a predetermined display image) is displayed may be greater than the second average value for compensating the first-second block BLK1-2 in which a second image IM2 including a black image is displayed.

[0105] That is, when performing a compensation operation for an afterimage of input data RGB in a first block BLK1 adjacent to a boundary line BL, the timing controller TCON may compensate the first block BLK1 with pixel units that are a first unit.

[0106] The timing controller TCON may generate a second compensation value for a second block BLK2 based on a flag signal FG. When the flag signal FG is in an invalid state, the timing controller TCON may generate the second compensation value for a corresponding block (the second block BLK2) among the blocks BLK with a second unit different from the first unit. In this case, the second unit may be greater than the first unit.

[0107] The timing controller TCON may generate the second compensation value using a representative compensation value of one block among the second block BLK2 and a representative compensation value of another block adjacent to the one block among the blocks BLK.

[0108] The second compensation value may be generated by adding the representative compensation value of the second block BLK2 and a value obtained by interpolating representative compensation values of other blocks adjacent to the second block BLK2 among the blocks BLK. In an embodiment, when the block BLK at the second position is Figure 4 the second block BLK2 in, a value obtained by adding the representative compensation value of the block BLK at the second position and the average value of the representative compensation values of the block BLK at the first position and the third position may be generated as the second compensation value.

[0109] That is, when performing the compensation operation of the afterimage of the input data RGB in the second block BLK2 spaced apart from the boundary line BL, the timing controller TCON may compensate the second block BLK2 in block units that are the second unit.

[0110] Different from the present disclosure, the timing controller may generate a compensation value by interpolating the representative compensation value of each of the blocks BLK and the representative compensation values of other adjacent blocks BLK. Since the predetermined display image is displayed as the first image IM1 and the black image is displayed as the second image IM2 based on the boundary line BL, when generating the compensation value by interpolation processing in the block BLK adjacent to the boundary line BL, the compensation value interpolated by the compensation value of the second image IM2 may be reduced in the portion adjacent to the boundary line BL in the first region AA1, and an afterimage may appear in the display panel. However, according to the present disclosure, the timing controller TCON may generate a first compensation value in pixel units for the first block BLK1 adjacent to the boundary line BL, and may generate a second compensation value in block units for the second block BLK2 spaced apart from the boundary line BL. The compensation operation may be performed in pixel units in the block adjacent to the boundary line BL, and thus, it is possible to prevent the compensation value from being reduced in the portion adjacent to the boundary line BL in the first region AA1. Accordingly, the afterimage appearing in the display panel DP may be reduced or prevented. Therefore, a display device DD with improved display quality can be provided.

[0111] The timing controller TCON may output the image data DS obtained by reflecting the first compensation value and the second compensation value in the input data RGB to the data driver DIC. The data driver DIC may apply a voltage to the first block BLK1 based on the first compensation value, and may apply a voltage to the second block BLK2 based on the second compensation value. That is, the input data RGB may be compensated using the first compensation value in the portion adjacent to the boundary line BL in the display area DA, and the input data RGB may be compensated using the second compensation value in the portion spaced apart from the boundary line BL in the display area DA.

[0112] The compensated luminance value ACL may be the luminance value of the image data DS in which the first compensation value and the second compensation value are reflected. The compensated luminance value ACL may be uniform during the period SS. That is, the first image IM1 and the second image IM2 displayed on the display panel DP may have uniform luminance.

[0113] According to the present disclosure, a timing controller TCON may generate a first compensation value and a second compensation value for a block BLK during a period SS. The timing controller TCON may display an image through a display panel DP based on image data DS in which the first compensation value and the second compensation value are reflected. A compensated luminance value ACL of the image data DS output to the block BLK corresponding to the period SS may be uniform. Accordingly, afterimages that occur in the display panel DP may be reduced or prevented. Therefore, a display device DD having improved display quality may be provided.

[0114] Figure 6 is a plan view of an embodiment of a display area of a display panel in a second mode according to the present disclosure. In Figure 6 , the same reference numerals denote Figure 4 the same elements in Figure 6 and thus, detailed descriptions of the same elements are omitted.

[0115] Referring to Figure 3 and Figure 6 , the display panel DP may include a plurality of blocks BLK. The block BLK may include at least one first block BLK1a and at least one second block BLK2. The first block BLK1a may overlap with a boundary line BL-1, and the second block BLK2 may be spaced apart from the boundary line BL-1. The second block BLK2 may be provided in plurality, and the first block BLK1a may be disposed between the second blocks BLK2. In Figure 6 , the block among the blocks BLK that is disposed at a third position in the opposite direction of the second direction DR2 is shown as the first block BLK1a, and the blocks among the blocks BLK that are disposed at a first position, a second position, a fourth position, a fifth position, and a sixth position in the opposite direction of the second direction DR2 are shown as the second blocks BLK2.

[0116] The first block BLK1a may include a first block portion BLP1 and a second block portion BLP2. The second block portion BLP2 may be spaced apart from the first block portion BLP1, and the boundary line BL-1 may be interposed between the first block portion BLP1 and the second block portion BLP2. The first block portion BLP1 may be disposed in a first region AA1, and the second block portion BLP2 may be disposed in a second region AA2.

[0117] The timing controller TCON may generate a flag signal FG-1 with respect to the first block BLK1a (refer to Figure 7 ). The flag signal FG-1 (refer to Figure 7 ) may be a signal for defining at least one first block BLK1a among the blocks BLK that is the region where the boundary line BL-1 is generated.

[0118] The timing controller TCON may divide the first block portion BLP1 and the second block portion BLP2 in a first unit. The first unit may be defined as a pixel unit including at least one pixel among the pixels PX. The pixel unit may include a plurality of first pixel units PXG1 and a plurality of second pixel units PXG2.

[0119] The first pixel units PXG1 each including at least one pixel among the pixels PX may be defined in the first block portion BLP1. Each of the first pixel units PXG1 may include a first-first pixel unit PXG1a and a first-second pixel unit PXG1b. Figure 6 A structure in which two pixels PX are grouped into one pixel unit PXG1a or PXG1b is shown as an illustrative embodiment. However, the number of pixels included in one pixel unit PXG1a or PXG1b should not be limited to or restricted by this.

[0120] The second pixel units PXG2 each including at least one pixel among the pixels PX may be defined in the second block portion BLP2. The second pixel units PXG2 may include a second-first pixel unit PXG2a and a second-second pixel unit PXG2b.

[0121] Figure 7 is a timing diagram of an embodiment of a display device according to the present disclosure.

[0122] Refer to Figure 3 、 Figure 6 and Figure 7 , the timing controller TCON may generate a compensation value CPV-1 for each of the blocks BLK.

[0123] As Figure 7 shown in the timing diagram of, the blocks BLK may operate corresponding to a plurality of time periods SS, respectively.

[0124] The timing controller TCON may output image data DS obtained by reflecting the compensation value CPV-1 in the input data RGB to the data driver DIC. The compensation value CPV-1 may include a first compensation value and a second compensation value generated by a method different from the method of generating the first compensation value.

[0125] The flag signal FG-1 may be in an active state in a time period corresponding to the first block BLK1a and may be in an inactive state in a time period corresponding to the second block BLK2.

[0126] The period corresponding to the first block BLK1a in the period SS may include a first period SS1 and a second period SS2. The timing controller TCON may generate a first compensation value for the first block BLK1a based on the flag signal FG-1 during the first period SS1 and the second period SS2. When the flag signal FG-1 is in an active state, the timing controller TCON may generate a first compensation value for the corresponding block (the first block BLK1a) in the block BLK in a first unit.

[0127] The timing controller TCON may generate a plurality of first pixel compensation values for the first pixel units PXG1 of the first block portion BLP1 during the first period SS1, respectively. The timing controller TCON may calculate a first average value of the first pixel compensation values. The timing controller TCON may generate the first average value as the first compensation value applied to the first block portion BLP1 during the first period SS1.

[0128] The timing controller TCON may generate a plurality of second pixel compensation values for the second pixel units PXG2 of the second block portion BLP2 during the second period SS2, respectively. The timing controller TCON may calculate a second average value of the second pixel compensation values. The timing controller TCON may generate the second average value as the first compensation value applied to the second block portion BLP2 during the second period SS2.

[0129] In this case, the first average value may be different from the second average value. In an embodiment, the first average value for compensating the first block portion BLP1 of the first image IM1 in which a normal image (or a predetermined display image) is displayed may be greater than the second average value for compensating the second block portion BLP2 of the second image IM2 in which a black image is displayed.

[0130] That is, when performing a compensation operation for an afterimage of the input data RGB in the first block BLK1a adjacent to the boundary line BL-1, the timing controller TCON may compensate the first block BLK1a in a pixel unit that is the first unit.

[0131] The timing controller TCON may generate a second compensation value for the second block BLK2 based on the flag signal FG-1. When the flag signal FG-1 is in an inactive state, the timing controller TCON may generate a second compensation value for the corresponding block (the second block BLK2) in the block BLK in a second unit different from the first unit. In this case, the second unit (block unit) may be greater than the first unit.

[0132] The timing controller TCON may generate the second compensation value using a representative compensation value of one block in the second block BLK2 and a representative compensation value of another block adjacent to the one block in the block BLK and / or the first compensation value.

[0133] The second compensation value can be generated by adding the representative compensation value of the second block BLK2 and the value obtained by interpolating the representative compensation values of other blocks adjacent to the second block BLK2 among the blocks BLK, or the value obtained by interpolating the representative compensation values of other blocks and the first compensation value. In an embodiment, when the block BLK at the second position is the second block BLK2, the value obtained by adding the average value of the representative compensation value of the block BLK at the second position, the representative compensation value of the block BLK at the first position, and the first compensation value of the first block portion BLP1 can be generated as the second compensation value. When the block BLK at the fourth position is the second block BLK2, the value obtained by adding the average value of the representative compensation value of the block BLK at the fourth position, the first compensation value of the second block portion BLP2, and the representative compensation value of the block BLK at the fifth position can be generated as the second compensation value.

[0134] When the block BLK at the fifth position is the second block BLK2, the value obtained by adding the average value of the representative compensation value of the block BLK at the fifth position and the representative compensation values of the block BLK at the fourth and sixth positions can be generated as the second compensation value.

[0135] The timing controller TCON can output the image data DS obtained by reflecting the first compensation value and the second compensation value in the input data RGB to the data driver DIC. The data driver DIC can output a voltage to the first block BLK1a based on the first compensation value and output a voltage to the second block BLK2 based on the second compensation value. That is, the first compensation value can be used to compensate the input data RGB in the portion of the display area DA adjacent to the boundary line BL-1, and the second compensation value can be used to compensate the input data RGB in the portion of the display area DA spaced apart from the boundary line BL-1.

[0136] The compensated luminance value ACL-1 can be the luminance value of the image data DS in which the first compensation value and the second compensation value are reflected. The compensated luminance value ACL-1 can be uniform during the period SS. That is, the first image IM1 and the second image IM2 displayed on the display panel DP can have uniform luminance.

[0137] According to the present disclosure, a timing controller TCON may generate a first compensation value and a second compensation value for a block BLK during a period SS. The timing controller TCON may display an image through a display panel DP based on image data DS in which the first compensation value and the second compensation value are reflected. A compensated luminance value ACL-1 of the image data DS output to the block BLK corresponding to the period SS may be uniform. Accordingly, afterimages that occur in the display panel DP may be reduced or prevented. Therefore, a display device DD having improved display quality may be provided.

[0138] Figure 8 is a timing diagram of an embodiment of a display device according to the present disclosure.

[0139] Refer to Figure 3 、 Figure 4 and Figure 8 , the timing controller TCON may generate a compensation value CPV-2 for each of the blocks BLK.

[0140] In Figure 8 the timing diagram shown, the blocks BLK may operate corresponding to the period SS, respectively.

[0141] The timing controller TCON may output the image data DS obtained by reflecting the compensation value CPV-2 in the input data RGB to the data driver DIC. The compensation value CPV-2 may include a first compensation value and a second compensation value generated by a method different from the method of generating the first compensation value.

[0142] The flag signal FG-2 may be in an inactive state during the period SS.

[0143] The timing controller TCON may generate a representative compensation value for each of the first blocks BLK1 based on the flag signal FG-2. When the flag signal FG-2 is in an inactive state, the timing controller TCON may generate a representative compensation value for the first blocks BLK1.

[0144] The timing controller TCON may generate a representative compensation value for the first-first block BLK1-1. The timing controller TCON may generate the representative compensation value as the first compensation value applied to the first-first block BLK1-1.

[0145] The timing controller TCON may generate a representative compensation value for the first-second block BLK1-2. The timing controller TCON may generate the representative compensation value as the first compensation value applied to the first-second block BLK1-2.

[0146] In this case, the representative compensation value of the first-first block BLK1-1 may be different from the representative compensation value of the first-second block BLK1-2. In an embodiment, the representative compensation value of the first-first block BLK1-1 for compensating the first image IM1 in which a normal image (or a predetermined display image) is displayed may be greater than the representative compensation value of the first-second block BLK1-2 for compensating the second image IM2 in which a black image is displayed.

[0147] That is, the timing controller TCON may generate the first compensation value of the first-first block BLK1-1 only using the representative compensation value of the first-first block BLK1-1, and may generate the first compensation value of the first-second block BLK1-2 only using the representative compensation value of the first-second block BLK1-2.

[0148] The timing controller TCON may generate a second compensation value for the second block BLK2 based on the flag signal FG-2. The timing controller TCON may generate the second compensation value using the representative compensation value of one block among the second block BLK2 and the representative compensation value of another block adjacent to the one block among the blocks BLK.

[0149] The second compensation value may be generated by adding the representative compensation value of the second block BLK2 and a value obtained by interpolating the representative compensation values of other blocks adjacent to the second block BLK2 among the blocks BLK. In an embodiment, when the block BLK at the second position as shown in Figure 4 is the second block BLK2, the value obtained by adding the representative compensation value of the block BLK at the second position and the average value of the representative compensation values of the block BLK at the first position and the third position may be generated as the second compensation value.

[0150] Unlike the present disclosure, a timing controller may generate a compensation value by interpolating a representative compensation value for each of the blocks BLK and representative compensation values of other blocks BLK adjacent thereto. Since a display image based on the boundary line BL is displayed as a first image IM1 and a black image is displayed as a second image IM2, when a compensation value is generated by interpolation processing in a block BLK adjacent to the boundary line BL, the compensation value interpolated from the compensation value of the second image IM2 may be reduced in a portion adjacent to the boundary line BL in the first region AA1, and an afterimage may appear in the display panel. However, according to the present disclosure, the timing controller TCON may generate a first compensation value for the first block BLK1 only using the representative compensation value for each of the first blocks BLK1 adjacent to the boundary line BL, and may generate a second compensation value for the second block BLK2 using the representative compensation value of one block of the second blocks BLK2 spaced apart from the boundary line BL and the representative compensation value of another block adjacent to the one block in the block BLK. A compensation operation may be performed in a block adjacent to the boundary line BL without performing interpolation processing, and thus, it is possible to prevent the compensation value from being reduced in a portion adjacent to the boundary line BL in the first region AA1. Accordingly, an afterimage that appears in the display panel DP may be reduced or prevented. Therefore, a display device DD having improved display quality may be provided.

[0151] The timing controller TCON may output image data DS obtained by reflecting the first compensation value and the second compensation value in the input data RGB to the data driver DIC. The data driver DIC may apply a voltage to the first block BLK1 based on the first compensation value and may apply a voltage to the second block BLK2 based on the second compensation value. That is, the input data RGB may be compensated using the first compensation value in a portion adjacent to the boundary line BL in the display area DA, and the input data RGB may be compensated using the second compensation value in a portion spaced apart from the boundary line BL in the display area DA.

[0152] The compensated luminance value ACL-2 may be the luminance value of the image data DS in which the first compensation value and the second compensation value are reflected. The compensated luminance value ACL-2 may be uniform during the period SS. That is, the first image IM1 and the second image IM2 displayed on the display panel DP may have uniform luminance.

[0153] According to the present disclosure, a timing controller TCON may generate a first compensation value and a second compensation value for a block BLK during a period SS. The timing controller TCON may display an image through a display panel DP based on image data DS in which the first compensation value and the second compensation value are reflected. A compensated luminance value ACL-2 of the image data DS output to the block BLK corresponding to the period SS may be uniform. Accordingly, an afterimage that appears in the display panel DP may be reduced or prevented. Therefore, a display device DD having improved display quality may be provided.

[0154] Figure 9 is a timing diagram of an embodiment of a display device according to the present disclosure.

[0155] Refer to Figure 3 、 Figure 6 and Figure 9 , the timing controller TCON may generate a compensation value CPV-3 for each of the blocks BLK.

[0156] In Figure 9 the timing diagram shown, the blocks BLK may operate corresponding to the periods SS, respectively.

[0157] The timing controller TCON may output the image data DS obtained by reflecting the compensation value CPV-3 in the input data RGB to the data driver DIC. The compensation value CPV-3 may include a first compensation value and a second compensation value generated by a method different from the method of generating the first compensation value.

[0158] The period corresponding to the first block BLK1a may include a first period SS1-1 and a second period SS2-1. The timing controller TCON may generate a partial compensation value for the first block BLK1a based on a flag signal FG-3 during the first period SS1-1 and the second period SS2-1. When the flag signal FG-3 is in an active state, the timing controller TCON may generate a partial compensation value for the corresponding block (the first block BLK1a) among the blocks BLK.

[0159] The timing controller TCON may generate a partial compensation value for a first block portion BLP1 based on the flag signal FG-3 during the first period SS1-1. The timing controller TCON may generate the partial compensation value as a first compensation value applied to the first block portion BLP1 during the first period SS1-1.

[0160] The timing controller TCON may generate a partial compensation value for a second block portion BLP2 based on the flag signal FG-3 during the second period SS2-1. The timing controller TCON may generate the partial compensation value as a first compensation value applied to the second block portion BLP2 during the second period SS2-1.

[0161] In this case, the first compensation value applied to the first block portion BLP1 may be different from the first compensation value applied to the second block portion BLP2. In an embodiment, the first compensation value applied to the first block portion BLP1 in which the first image IM1 showing a normal image (or a predetermined display image) is displayed may be greater than the first compensation value applied to the second block portion BLP2 in which the second image IM2 showing a black image is displayed.

[0162] The timing controller TCON may generate a second compensation value for the second block BLK2 based on the flag signal FG-3. The timing controller TCON may generate the second compensation value using the representative compensation value of one block among the second block BLK2 and the representative compensation value or the first compensation value of another block adjacent to the one block among the blocks BLK.

[0163] The second compensation value may be generated by adding the representative compensation value of the second block BLK2 and the value obtained by interpolating the representative compensation values of other blocks adjacent to the second block BLK2 among the blocks BLK or the value obtained by interpolating the representative compensation values of other blocks and the first compensation value. In an embodiment, when the block BLK at the second position is the second block BLK2, the value obtained by adding the representative compensation value of the block BLK at the second position, the representative compensation value of the block BLK at the first position, and the average value of the first compensation values of the first block portions BLP1 may be generated as the second compensation value.

[0164] When the block BLK at the fourth position is the second block BLK2, the value obtained by adding the representative compensation value of the block BLK at the fourth position, the first compensation value of the second block portion BLP2, and the average value of the representative compensation values of the block BLK at the fifth position may be generated as the second compensation value.

[0165] When the block BLK at the fifth position is the second block BLK2, the value obtained by adding the representative compensation value of the block BLK at the fifth position and the average value of the representative compensation values of the block BLK at the fourth and sixth positions may be generated as the second compensation value.

[0166] The timing controller TCON can output image data DS obtained by reflecting a first compensation value and a second compensation value in the input data RGB to the data driver DIC. The data driver DIC can output a voltage to the first block BLK1a based on the first compensation value and can output a voltage to the second block BLK2 based on the second compensation value. That is, the input data RGB can be compensated using the first compensation value in a portion of the display area DA adjacent to the boundary line BL-1, and the input data RGB can be compensated using the second compensation value in a portion of the display area DA spaced apart from the boundary line BL-1.

[0167] The compensated luminance value ACL-3 can be the luminance value of the image data DS in which the first compensation value and the second compensation value are reflected. The compensated luminance value ACL-3 can be uniform during the period SS. That is, the first image IM1 and the second image IM2 displayed on the display panel DP can have uniform luminance.

[0168] According to the present disclosure, the timing controller TCON can generate a first compensation value and a second compensation value for the block BLK during the period SS. The timing controller TCON can display an image through the display panel DP based on the image data DS in which the first compensation value and the second compensation value are reflected. The compensated luminance value ACL-3 of the image data DS output to the block BLK corresponding to the period SS can be uniform. Accordingly, afterimages that appear in the display panel DP can be reduced or prevented. Therefore, a display device DD having improved display quality can be provided.

[0169] Although embodiments of the present disclosure have been described, it should be understood that the present disclosure should not be limited to these embodiments, but that various changes and modifications can be made by those of ordinary skill in the art within the spirit and scope of the present disclosure as claimed. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, and the scope of the inventive concept should be determined according to the claims.

Claims

1. A display device, comprising: A display panel in which a display area including a first area and a second area spaced apart from the first area in a predetermined direction is defined, the display panel comprising: a plurality of blocks including a first block and a second block, the plurality of blocks each including a plurality of pixels; and a timing controller that generates a representative compensation value with respect to each of the plurality of blocks, Wherein, the first area displays a first image, The second area displays a second image different from the first image, defining a boundary line between the first area and the second area, the first block is adjacent to the boundary line and the second block is spaced apart from the boundary line, The timing controller generates a flag signal with respect to the first block, the timing controller generates a first compensation value with respect to the first block based on the flag signal, and The timing controller generates a second compensation value different from the first compensation value with respect to the second block using the representative compensation value of the second block and the representative compensation value of another block adjacent to the second block among the plurality of blocks.

2. The display device according to claim 1, wherein: The first block is provided in plurality, and The plurality of first blocks include: a first-first block; and a first-second block spaced apart from the first-first block, wherein the boundary line is between the first-first block and the first-second block. wherein a plurality of first pixel units each including at least one pixel among the plurality of pixels are defined in the first-first block, defining a plurality of second pixel units each including at least one pixel among the plurality of pixels in the first-second block, and The timing controller generates a plurality of first pixel compensation values ​​with respect to the plurality of first pixel units, respectively, and generates a plurality of second pixel compensation values ​​with respect to the plurality of second pixel units, respectively.

3. The display device according to claim 2, wherein: The first compensation value of the first-first block is a first average value of the plurality of first pixel compensation values, and the first compensation value of the first-second block is a second average value of the plurality of second pixel compensation values, wherein the first-first block is arranged in the first area, The first-second block is disposed in the second region, and The first average value is different from the second average value.

4. The display device according to claim 1, wherein: The second image is a black image.

5. The display device according to any one of claims 1 to 4, wherein: The second block is provided in plurality, and The first block is disposed between a plurality of second blocks.

6. The display device according to claim 1, wherein: The first block includes a first block portion and a second block portion adjacent to the first block portion, and the boundary line is between the first block portion and the second block portion. wherein a plurality of first pixel units each including at least one pixel among the plurality of pixels are defined in the first block portion, A plurality of second pixel units each including at least one pixel among the plurality of pixels is defined in the second block portion, and The timing controller generates a plurality of first pixel compensation values ​​with respect to the plurality of first pixel units, respectively, and generates a plurality of second pixel compensation values ​​with respect to the plurality of second pixel units, respectively.

7. The display device according to claim 6, wherein: The first compensation value of the first block portion is a first average value of the plurality of first pixel compensation values, and The first compensation value of the second block portion is a second average value of the plurality of second pixel compensation values.

8. The display device according to claim 1, wherein: The timing controller generates the first compensation value using only the representative compensation value of the first block.

9. The display device according to claim 1, wherein: The first block includes a first block portion and a second block portion adjacent to the first block portion, and The timing controller generates a partial compensation value with respect to each of the first block portion and the second block portion.

10. The display device according to claim 1, wherein: The second compensation value is generated by adding the representative compensation value of the second block and a value obtained by interpolating the representative compensation value of the another block adjacent to the second block among the plurality of blocks.

Images