Display device and driving method of display device

Abstract

The embodiment of the invention relates to a display device and a driving method of the display device. More specifically, a gamma voltage compensation circuit for supplying a high reference voltage and a low reference voltage to a reference gamma voltage generation circuit may be electrically connected to a display panel through a first voltage line and a second voltage line, thereby compensating for a voltage drop phenomenon of a driving voltage.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0194626, filed on December 28, 2023, which is incorporated herein by reference in its entirety for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments of the present disclosure relate to a power management circuit, a display device, and a driving method of the display device. Background Art

[0004] As the information society develops, the demand for display devices for displaying images in various forms is increasing. Therefore, in recent years, various display devices such as liquid crystal displays and organic light - emitting display devices have been used.

[0005] To drive a display device, the display device may supply voltages to a display panel, a data driving circuit, a gate driving circuit, and a controller.

[0006] A driving voltage may be supplied to the display panel. A voltage drop of the driving voltage may occur, which may cause non - uniform brightness of the display panel. Summary of the Invention

[0007] Embodiments of the present disclosure may provide a display device and a driving method of the display device that can compensate for a voltage drop phenomenon in a driving voltage.

[0008] Embodiments of the present disclosure may provide a display device and a driving method of the display device that can equalize the brightness of a display panel.

[0009] Embodiments of the present disclosure may provide a display device and a driving method of the display device that can achieve low power consumption by equalizing the brightness of a display panel.

[0010] Embodiments of the present disclosure may provide a display device including: a data driving circuit configured to be supplied with a plurality of gamma voltages; a gamma voltage generation circuit configured to supply the plurality of gamma voltages to the data driving circuit; a reference gamma voltage generation circuit configured to generate a plurality of reference gamma voltages based on a high reference voltage and a low reference voltage and supply the plurality of reference gamma voltages to the gamma voltage generation circuit; and a gamma voltage compensation circuit configured to supply the high reference voltage and the low reference voltage to the reference gamma voltage generation circuit, wherein the gamma voltage compensation circuit is electrically connected to the display panel through a first voltage line and a second voltage line.

[0011] Embodiments of the present disclosure may provide a method for driving a display device, the driving method including: supplying a high reference voltage and a low reference voltage from a gamma voltage compensation circuit to a reference gamma voltage generation circuit, generating a plurality of reference gamma voltages based on the high reference voltage and the low reference voltage and supplying the plurality of reference gamma voltages to a gamma voltage generation circuit, and supplying a plurality of gamma voltages to a data driving circuit based on the plurality of reference gamma voltages, wherein the gamma voltage compensation circuit is electrically connected to a display panel of the display device through a first voltage line and a second voltage line.

[0012] Embodiments of the present disclosure may provide a method for driving a display device, the driving method including: supplying a first reference driving voltage through a first voltage line and a second reference driving voltage through a second voltage line from a display panel of the display device; generating a feedback driving voltage based on the first reference driving voltage and the second reference driving voltage; generating a high reference voltage and a low reference voltage based on the feedback driving voltage; generating a plurality of reference gamma voltages based on the high reference voltage and the low reference voltage; generating a plurality of gamma voltages based on the plurality of reference gamma voltages; and selecting and supplying a gamma voltage corresponding to image data among the plurality of gamma voltages to the display panel.

[0013] Embodiments of the present disclosure may provide a display device and a driving method thereof capable of compensating for a voltage drop phenomenon in a driving voltage.

[0014] Embodiments of the present disclosure may provide a display device and a driving method thereof capable of equalizing the brightness of a display panel.

[0015] Embodiments of the present disclosure may provide a display device and a driving method thereof capable of achieving low power consumption by equalizing the brightness of a display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic configuration of a display device according to an embodiment of the present disclosure is shown.

[0017] Figure 2 A data driving circuit according to an embodiment of the present disclosure is shown.

[0018] Figure 3 A voltage drop phenomenon and feedback of a driving voltage generated in a display panel according to an embodiment of the present disclosure are shown.

[0019] Figure 4 is a diagram for explaining a turn-on pixel ratio according to an embodiment of the present disclosure.

[0020] Figure 5 and Figure 6 is a diagram for explaining a method of compensating for a voltage drop phenomenon in a driving voltage according to an embodiment of the present disclosure.

[0021] Figure 7 Shows a gamma voltage compensation circuit according to an embodiment of the present disclosure.

[0022] Figure 8 Shows a scanning signal supply direction and a 10-bit signal according to an embodiment of the present disclosure.

[0023] Figure 9 Shows a relative bit ratio according to the position of a display panel according to an embodiment of the present disclosure.

[0024] Figures 10 to 13 Shows an operation example of a gamma voltage compensation circuit according to an embodiment of the present disclosure.

[0025] Figures 14 to 20 Shows a voltage line provided on a display panel according to an embodiment of the present disclosure.

[0026] Figure 21 and Figure 22 Shows a reference voltage conversion circuit according to an embodiment of the present disclosure.

[0027] Figure 23 and Figure 24 Is a graph of voltages according to the operations of a feedback drive voltage generation circuit and a reference voltage conversion circuit according to an embodiment of the present disclosure.

[0028] Figure 25 Is a diagram of a driving method of a display device according to an embodiment of the present disclosure. Detailed Description

[0029] In the following description of examples or embodiments of the present invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are illustrated by way of illustration, and in the accompanying drawings, even when the same or similar components are shown in different drawings, the same reference numerals can be used to denote the same or similar components. Further, in the following description of examples or embodiments of the present invention, when it is determined that the description may make the subject matter in some embodiments of the present invention quite unclear, the detailed description of well-known functions and components incorporated herein will be omitted. Terms such as "including", "having", "containing", "constituting", "consisting of", and "formed of" as used herein are generally intended to allow the addition of other components, unless the term is used together with the term "only". As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise.

[0030] Terms such as "first", "second", "A", "B", "(A)", or "(B)" may be used in this document to describe elements of the present invention. Each of these terms is not used to define the nature, order, sequence, number, etc. of the elements, but is only used to distinguish the corresponding elements from other elements.

[0031] When referring to a first element being "connected or coupled to" a second element, "contacting or overlapping" with the second element, etc., it should be understood that not only can the first element be "directly connected or coupled to" the second element, "directly contacting or overlapping" with the second element, but also a third element can be "inserted" between the first element and the second element, or the first element and the second element can be "connected or coupled", "contacting or overlapping", etc. with each other via a fourth element. Here, the second element may be included in at least one of two or more elements that are "connected or coupled" to each other, "contacting or overlapping" with each other, etc.

[0032] When using time-related terms such as "after", "subsequently", "next", "before", etc. to describe the processing or operation of an element or configuration, or the process or steps in an operation, processing, manufacturing method, these terms can be used to describe non-consecutive or non-sequential processing or operations, unless the terms "directly" or "immediately" are used together.

[0033] In addition, when referring to any size, relative size, etc., the numerical value or corresponding information of the element or feature (e.g., level, range, etc.) should be considered to include the tolerance or error range that may be caused by various factors (e.g., processing factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "can".

[0034] Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0035] Figure 1 A schematic configuration of a display device 100 according to an embodiment of the present disclosure is shown.

[0036] Referring to Figure 1 , a display device 100 according to an embodiment of the present disclosure may include: a display panel 110 in which a plurality of gate lines GL and a plurality of data lines DL are provided, and a plurality of sub-pixels SP are arranged in a matrix form; a gate driving circuit 120 for driving the plurality of gate lines GL; a data driving circuit 130 for supplying data voltages through the plurality of data lines DL; a controller 140 for controlling the gate driving circuit 120 and the data driving circuit 130; and a power management circuit 150.

[0037] The display panel 110 may display an image based on a scan signal transmitted from the gate driving circuit 120 through a plurality of gate lines GL and a data voltage transmitted from the data driving circuit 130 through a plurality of data lines DL.

[0038] In the case of an organic light emitting display, the display panel 110 may be implemented in a top emission method, a bottom emission method, or a dual emission method.

[0039] The display panel 110 may include a plurality of pixels arranged in a matrix form, and each pixel may include sub-pixels SP of different colors, such as white sub-pixels, red sub-pixels, green sub-pixels, and blue sub-pixels. In addition, each sub-pixel SP may be defined by a plurality of data lines DL and a plurality of gate lines GL.

[0040] One sub-pixel SP may include a thin film transistor TFT formed in a region where one data line DL and one gate line GL intersect, a light emitting device such as an organic light emitting diode that charges the data voltage, and a storage capacitor electrically connected to the light emitting device to hold the voltage.

[0041] For example, in the case where the display device 100 with a resolution of 2160×3840 includes four sub-pixels of white (W), red (R), green (G), and blue (B), 2160 gate lines GL and a total of 3840×4 = 15360 data lines DL may be provided, and each of the 3840 data lines DL is connected to 4 sub-pixels (WRGB). The sub-pixel SP may be provided at each point where the gate line GL and the data line DL intersect.

[0042] The gate driving circuit 120 may be controlled by the controller 140, and sequentially output a scan signal to a plurality of gate lines GL arranged on the display panel 110 to control the driving timing of the plurality of sub-pixels SP.

[0043] In this case, the gate driving circuit 120 may include one or more gate driving integrated circuits GDIC, and may be located only on one side of the display panel 110 or on both sides of the display panel 110 according to the driving method. Alternatively, the gate driving circuit 120 may be embedded in the border area of the display panel 110 to be implemented in a gate in panel (GIP) type.

[0044] The data driving circuit 130 may receive image data DATA from the controller 140, and convert the received image data DATA into an analog data voltage. Then, the data driving circuit 130 may output the data voltage to each data line DL according to the timing of applying the scan signal through the gate line GL, so that each sub-pixel SP connected to the data line DL can display light having a brightness corresponding to the data voltage.

[0045] Similarly, the data driving circuit 130 may include one or more source driver integrated circuits (SDICs), and the source driver integrated circuit (SDIC) may be connected to the bonding pads of the display panel 110 using a tape automated bonding (TAB) method or a chip on glass (COG) method, or may be directly disposed on the display panel 110.

[0046] Depending on the situation, each source driver integrated circuit (SDIC) may be integrated and disposed on the display panel 110. In addition, each source driver integrated circuit (SDIC) may be implemented in a chip on film (COF) method. In this case, each source driver integrated circuit (SDIC) may be mounted on a circuit film and may be electrically connected to the data lines DL of the display panel 110 through the circuit film.

[0047] The controller 140 may supply various control signals to the gate driving circuit 120 and the data driving circuit 130, and control the operations of the gate driving circuit 120 and the data driving circuit 130. That is, the controller 140 may control the gate driving circuit 120 to output scan signals according to the timing implemented in each frame, and may send the image data DATA received from the outside to the data driving circuit 130.

[0048] In this case, the controller 140 may receive the image data DATA and various timing signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable DE signal, and a main clock MCLK from an external host system 200.

[0049] The host system 200 may be any one of a television system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device.

[0050] Therefore, the controller 140 may generate control signals using the various timing signals received from the host system 200, and send the timing signals to the gate driving circuit 120 and the data driving circuit 130.

[0051] For example, in order to control the gate driving circuit 120, the controller 140 may output various gate control signals including a gate start pulse GSP, a gate clock GCLK, and a gate output enable signal GOE. Here, the gate start pulse GSP may control the operation start timing of one or more gate driver integrated circuits (GDICs) constituting the gate driving circuit 120. In addition, the gate clock GCLK is a clock signal commonly input to one or more gate driver integrated circuits (GDICs), and may control the shift timing of the scan signals. In addition, the gate output enable signal GOE may specify the timing information of one or more gate driver integrated circuits (GDICs).

[0052] In addition, to control the data driving circuit 130, the controller 140 may output various data control signals such as a source start pulse SSP, a source sampling clock SCLK, and a source output enable signal SOE. Here, the source start pulse SSP may control the timing at which one or more source driver integrated circuits SDICs constituting the data driving circuit 130 start sampling data. The source sampling clock SCLK is a clock signal that controls the timing of sampling data in the source driver integrated circuit SDIC. The source output enable signal SOE may control the output timing of the data driving circuit 130.

[0053] The display device 100 may include a power management circuit 150 that supplies various voltages or currents to the display panel 110, the gate driving circuit 120, and the data driving circuit 130, or controls the various voltages or currents to be supplied.

[0054] The power management circuit 150 may adjust the DC input voltage Vin supplied from the host system 200 to generate the power required to drive the display panel 100, the gate driving circuit 120, and the data driving circuit 130. The power management unit 150 may be referred to as a power management integrated circuit (PMIC). The power management circuit 150 may generate voltages such as a driving voltage VDD, a base voltage VSS, a gate high voltage VGH, a gate low voltage VGL, a source driving voltage SVDD, and a reference voltage Vref.

[0055] Meanwhile, the sub-pixel SP may be located at the intersection of the gate line GL and the data line DL, and a light-emitting element may be provided in each sub-pixel SP. For example, an organic light-emitting display device may include a light-emitting element such as an organic light-emitting diode in each sub-pixel SP, and may display an image by controlling the current flowing through the light-emitting element according to the data voltage.

[0056] The display device 100 may be of various types, such as a liquid crystal display, an organic light-emitting display, and a plasma display panel.

[0057] Figure 2 The gate driving circuit 130 according to an embodiment of the present disclosure is shown.

[0058] Referring to Figure 2 , the data driving circuit 130 may include a shift register circuit 131, a latch circuit 132, a digital-to-analog conversion circuit 133, and an output buffer circuit 134.

[0059] The shift register circuit 131 may sequentially output latch pulses to a plurality of latches included in the latch circuit 132. The shift register circuit 131 may include a plurality of shift registers.

[0060] The latch circuit 132 can sequentially store the image data DATA in response to a latch pulse. The latch circuit 132 can include a plurality of latches.

[0061] The digital-to-analog conversion circuit 133 can convert the image data DATA output from the latch circuit 132 into an initial data voltage as an analog voltage. The digital-to-analog conversion circuit 133 can include a plurality of digital-to-analog converters.

[0062] The output buffer circuit 134 can receive the initial data voltage from the digital-to-analog conversion circuit 133 and amplify it to generate a data voltage. Thereafter, the output buffer circuit 134 can output the data voltage to a plurality of data lines DL provided on the display panel 110. The output buffer circuit 134 can include a plurality of output buffers.

[0063] Referring Figure 2 , the gamma voltage generation circuit 160 can output a gamma voltage Vgm to the digital-to-analog conversion circuit 133. The digital-to-analog conversion circuit 133 can select the gamma voltage Vgm corresponding to the image data DATA as the data voltage and output the gamma voltage Vgm to the output buffer circuit 134.

[0064] The reference gamma voltage generation circuit 170 can generate a reference gamma voltage Vrgm and output the reference gamma voltage Vrgm to the gamma voltage generation circuit 160. The gamma voltage generation circuit 160 can generate the gamma voltage Vgm based on the reference gamma voltage Vrgm. The number of the reference gamma voltages Vrgm can be less than the number of the gamma voltages Vgm. For example, the reference gamma voltage Vrgm can include a first reference gamma voltage Vrgm1, a second reference gamma voltage Vrgm2 to a tenth reference gamma voltage Vrgm10. The gamma voltages Vgm generated based on the reference gamma voltage Vrgm can include a first gamma voltage Vgm1, a second gamma voltage Vgm2 to a 256th gamma voltage Vgm256. This is an example, and the numbers of the reference gamma voltage Vrgm and the gamma voltage Vgm can vary according to the design.

[0065] The gamma voltage generation circuit 160 and the reference gamma voltage generation circuit 170 can be supplied with two or more voltages. The gamma voltage generation circuit 160 and the reference gamma voltage generation circuit 170 can divide the two or more voltages by a voltage string. The gamma voltage generation circuit 160 and the reference gamma voltage generation circuit 170 can select one voltage from the divided voltages and output it. In order to select one voltage from the divided voltages and output it, the gamma voltage generation circuit 160 and the reference gamma voltage generation circuit 170 can include a multiplexer circuit or a plurality of switches. The gamma voltage generation circuit 160 and the reference gamma voltage generation circuit 170 can select the voltage to be output through the multiplexer circuit or the plurality of switches.

[0066] Meanwhile, the reference gamma voltage generation circuit 170 may be supplied with a feedback driving voltage Vfb fed back through a feedback line electrically connected to the display panel 110. Hereinafter, the feedback driving voltage Vfb will be described in detail.

[0067] Figure 3 Illustrated are a voltage drop phenomenon and feedback of a driving voltage generated in the display panel 110 according to an embodiment of the present disclosure.

[0068] Referring Figure 3 , a plurality of sub-pixels SP may be provided on the display panel 110.

[0069] Referring Figure 3 , the display panel 110 may be divided into a top region Top, a middle region Mid, and a bottom region Bottom based on the vertical direction.

[0070] A first sub-pixel SP1 may be provided in the top region Top.

[0071] A second sub-pixel SP2 may be provided in the middle region Mid.

[0072] A third sub-pixel SP3 may be provided in the bottom region Bottom.

[0073] Referring Figure 3 , the plurality of sub-pixels SP may be supplied with a driving voltage VDD. The driving voltage VDD may be supplied from both sides or one side of the display panel 110, and hereinafter, it will be assumed that the driving voltage VDD is supplied from both sides of the display panel 100 for description.

[0074] A method of supplying the driving voltage VDD from both sides of the display panel 110 may be referred to as a "dual feed method". Alternatively, a method of supplying the driving voltage VDD from one side of the display panel 110 may be referred to as a "single feed method". Embodiments of the present disclosure may be applicable to both the dual feed method and the single feed method, but for ease of explanation, the single feed method will be described as an example.

[0075] If the driving voltage VDD is supplied to the plurality of sub-pixels SP, a voltage drop phenomenon may occur in the driving voltage VDD.

[0076] Referring Figure 3 , a distance d2 for supplying the driving voltage VDD to the second sub-pixel SP2 may be greater than a distance d1 for supplying the driving voltage VDD to the first sub-pixel SP1. Accordingly, a level of the driving voltage VDD supplied to the second sub-pixel SP2 may be different from a level of the driving voltage VDD supplied to the first sub-pixel SP1.

[0077] ReferringFigure 3 Assume that the second sub-pixel SP2 receives the driving voltage VDD from the bottom of the display panel 110. Then, the distance d2' for supplying the driving voltage VDD to the second sub-pixel SP2 can be longer than the distance d3 for supplying the driving voltage VDD to the third sub-pixel SP3. Therefore, the level of the driving voltage VDD supplied to the second sub-pixel SP2 can be different from the level of the driving voltage VDD supplied to the third sub-pixel SP3.

[0078] Referring to Figure 3 To compensate for the voltage drop phenomenon occurring in the driving voltage VDD supplied to the middle region Mid, the reference gamma voltage generation circuit 170 can receive the feedback of the driving voltage VDD supplied to the sub-pixels SP provided in the middle region Mid. The feedback driving voltage Vfb fed back from the middle region Mid of the display panel 110 can be supplied to the reference gamma voltage generation circuit 170.

[0079] Hereinafter, a method of compensating for the voltage drop occurring in the driving voltage VDD using the feedback driving voltage Vfb will be described.

[0080] Figure 4 is a diagram for explaining the on-pixel ratio according to an embodiment of the present disclosure.

[0081] The "on-pixel ratio (OPR)" can be defined to illustrate the manner of compensating for the voltage drop occurring in the driving voltage VDD.

[0082] Referring to Figure 4 "1% of the on-pixel ratio OPR1" can be the illumination ratio when only some of the multiple sub-pixels emit light. When the display is driven at an on-pixel ratio OPR1 of 1%, the display panel 110 can exhibit a low gray level close to black. 100% of the on-pixel ratio OPR100 can be the illumination ratio when most of the multiple sub-pixels emit light. When driven at an on-pixel ratio OPR100 of 100%, the display panel 110 can exhibit a high gray level close to white.

[0083] If the display panel 110 is driven at an on-pixel ratio OPR1 of 1%, since only some sub-pixels are driven, the drop in the driving voltage VDD may occur relatively weakly. On the other hand, when the display panel 110 is driven at an on-pixel ratio OPR100 of 100%, due to the driving of most sub-pixels, a relatively strong drop may occur in the driving voltage VDD.

[0084] Hereinafter, driving the display panel 110 at a turn-on pixel ratio OPR1 of 1% may be expressed as "OPR1 driving", and driving the display panel 110 at a turn-on pixel ratio OPR100 of 100% may be expressed as "OPR100 driving".

[0085] Figure 5 And Figure 6 is a diagram for explaining a method of voltage reduction phenomenon in a compensated driving voltage according to an embodiment of the present disclosure.

[0086] Referring to Figure 5 , a graph of voltage V according to the position P of the display panel is shown.

[0087] Referring to Figure 5 , the voltage level of the driving voltage distribution VDD_OPR1 of the display panel 110 in the case of OPR1 driving can be maintained at the level of the first feedback driving voltage Vfb1. That is, in the case of OPR1 driving, the driving voltage distribution VDD_OPR1 of the display panel 110 can be uniform over the entire area of the display panel 110. In addition, referring to Figure 5 , the data voltage distribution Vdata_OPR1 in the case of OPR1 driving can be a uniform voltage distribution similar to the driving voltage distribution VDD_OPR1 of the display panel 110 in OPR1 driving.

[0088] Referring to Figure 5 , the driving voltage distribution VDD_OPR100 of the display panel 110 in the case of OPR100 driving can represent a "U"-shaped voltage curve. The driving voltage of the middle region Mid of the display panel 110 can be the second feedback driving voltage Vfb2. As moving from the middle region Mid of the display panel 110 to the top region Top, the driving voltage distribution VDD_OPR100 can become larger than the second feedback voltage Vfb2. In addition, as moving from the middle region Mid of the display panel 110 to the bottom region Bottom, the driving voltage distribution VDD_OPR100 can become larger than the second feedback voltage Vfb2.

[0089] That is, in OPR100 driving, voltage reduction may occur in the driving voltage. To solve the above problem, the second feedback driving voltage Vfb2 fed back from the middle region Mid of the display panel 110 can be supplied to the reference gamma voltage generation circuit 170. After feeding back the second feedback driving voltage Vfb2, a first differential voltage Gap1 can be calculated, and the first differential voltage Gap1 is the differential voltage between the second feedback driving voltage Vfb2 and the first feedback driving voltage Vfb1.

[0090] The data voltage distribution Vdda_OPR100 in the OPR100 drive can be generated by subtracting the first differential voltage Gap1 from the data voltage distribution Vdata_OPR1 in the OPR1 drive. However, in this case, the reduction in the drive voltage in the middle region Mid can be compensated, but the reduction in the drive voltage in other regions may not be compensated.

[0091] Referring Figure 5 , the gate-source voltage Vgs_t of the top region Top can be greater than the gate-source voltage Vgs_m of the middle region Mid. In addition, the gate-source voltage Vgs_b of the bottom region Bot can be greater than the gate-source voltage Vgs_m of the middle region Mid. Since the gate-source voltage Vgs_t of the top region and the gate-source voltage Vgs_b of the bottom region are greater than the target gate-source voltage, overcompensation may occur in the corresponding regions Top and Bot. Since overcompensation occurs in the corresponding regions Top and Bot compared to the middle region Mid, the brightness in the corresponding regions Top and Bot may become brighter, and the image quality characteristics of the display panel 110 may deteriorate.

[0092] That is, there may be a problem of brightness difference between the OPR1 drive and the OPR100 drive due to the voltage reduction phenomenon in the drive voltage. Therefore, the error rate ER can be calculated based on the 1% on-pixel ratio OPR1 and the 100% on-pixel ratio OPR100.

[0093] Referring Figure 6 , an error rate ER curve graph according to the gray level G is shown.

[0094] In all gray levels G, the error rate ER_mid of the middle region Mid can be lower than the error rates ER_top,bottom of the remaining regions Top and Bot. Referring Figure 6 , the error rates ER_top,bottom of the remaining regions Top and Bot can increase from the low gray level G1 to the high gray level G2. This phenomenon occurs because the drive voltage VDD is compensated only based on the feedback drive voltage Vfb fed back from the middle region Mid. Therefore, a brightness non-uniformity problem may occur in the display panel 110.

[0095] That is, as the amount of current flowing through the display panel 110 increases, the voltage reduction phenomenon in the drive voltage VDD may become stronger. Due to the voltage reduction phenomenon in the drive voltage VDD, the drive voltage VDD supplied to the sub-pixel SP may decrease. Therefore, the brightness may be further reduced at the 100% on-pixel ratio OPR100 compared to the 1% on-pixel ratio OPR1.

[0096] Accordingly, embodiments of the present disclosure can provide a display device capable of compensating for a voltage drop in a driving voltage VDD and a method of driving the display device.

[0097] Embodiments of the present disclosure can provide a display device capable of equalizing the brightness of a display panel 110 and a method of driving the display device.

[0098] Embodiments of the present disclosure can provide a display device capable of achieving low power consumption by equalizing the brightness of a display panel 110 and a method of driving the display device. This will be described in detail below.

[0099] Figure 7 A gamma voltage compensation circuit 700 according to an embodiment of the present disclosure is shown.

[0100] The gamma voltage compensation circuit 700 may include a feedback driving voltage generation circuit 710 and a reference voltage conversion circuit 720.

[0101] The feedback driving voltage generation circuit 710 may supply a feedback driving voltage VDDFB based on a top reference driving voltage VDDREF_Top, a middle reference driving voltage VDDREF_Mid, and a bottom reference driving voltage VDDREF_Bot.

[0102] The feedback driving voltage generation circuit 710 may be electrically connected to a first voltage line VL1. The feedback driving voltage generation circuit 710 may receive the top reference driving voltage VDDREF_Top through the first voltage line VL1. The top reference driving voltage VDDREF_Top may be a first reference driving voltage.

[0103] The feedback driving voltage generation circuit 710 may be electrically connected to a second voltage line VL2. The feedback driving voltage generation circuit 710 may receive the middle reference driving voltage VDDREF_Mid through the second voltage line VL2. The middle reference driving voltage VDDREF_Mid may be a second reference driving voltage.

[0104] The feedback driving voltage generation circuit 710 may be electrically connected to a third voltage line VL3. The feedback driving voltage generation circuit 710 may receive the bottom reference driving voltage VDDREF_Bot through the third voltage line VL3. The bottom reference driving voltage VDDREF_Bot may be a third reference driving voltage.

[0105] The feedback-driven voltage generation circuit 710 can output a feedback-driven voltage VDDFB based on the top reference drive voltage VDDREF_Top and the middle reference drive voltage VDDREF_Mid. In addition, the feedback-driven voltage generation circuit 710 can output a feedback-driven voltage VDDFB based on the bottom reference drive voltage VDDREF_Bot and the middle reference drive voltage VDDREF_Mid.

[0106] The feedback-driven voltage generation circuit 710 can include a first buffer 711, a second buffer 712, a third buffer 713, a resistor string 714, a first multiplexer 715, a second multiplexer 716, and a third multiplexer 717.

[0107] Each of the first buffer 711, the second buffer 712, and the third buffer 713 can include an operational amplifier. Each of the first buffer 711, the second buffer 712, and the third buffer 713 can be configured as a circuit that functions as a buffer. That is, each of the first buffer 711, the second buffer 712, and the third buffer 713 can supply the input voltage supplied to the input terminal as an output voltage to the output terminal.

[0108] The first buffer 711 can receive the top reference drive voltage VDDREF_Top from the first input node through the first voltage line VL1. The second input node of the first buffer 711 can be electrically connected to the output node of the first buffer 711. The first buffer 711 can supply the top reference drive voltage VDDREF_Top to the first node N1, which is the top node of the resistor string 714.

[0109] The second buffer 712 can receive the middle reference drive voltage VDDREF_Mid from the first input node through the second voltage line VL2. The second input node of the second buffer 712 can be electrically connected to the output node of the second buffer 712. The second buffer 712 can supply the middle reference drive voltage VDDREF_Mid to the second node N2, which is the middle node of the resistor string 714.

[0110] The third buffer 713 can receive the bottom reference drive voltage VDDREF_Bot from the first input node through the third voltage line VL3. The second input node of the third buffer 713 can be electrically connected to the output node of the third buffer 713. The third buffer 713 can supply the bottom reference drive voltage VDDREF_Bot to the third node N3, which is the bottom node of the resistor string 714.

[0111] Since a relatively large voltage drop may occur in the driving voltage VDD in the middle region Mid of the display panel 110, the middle reference driving voltage VDDREF_Mid may be smaller than the top reference driving voltage VDDREF_Top and the bottom reference driving voltage VDDREF_Bot.

[0112] The resistor string 714 may include a plurality of resistors. The plurality of resistors may be serially connected from a first node N1, which is a top node, to a third node N3, which is a bottom node.

[0113] The resistor string 714 may receive the top reference driving voltage VDDREF_Top from a first node N1, which is a top node. The first node N1 may be referred to as Figure 7 the first node N1 shown in

[0114] The resistor string 714 may receive the middle reference driving voltage VDDREF_Mid from a second node N2, which is a middle node. The second node N2 may be referred to as Figure 7 the second node N2 shown in

[0115] The resistor string 714 may receive the bottom reference driving voltage VDDREF_Bot from a third node N3, which is a bottom node. The third node N3 may be referred to as Figure 7 the third node N3 shown in

[0116] In each of the plurality of resistors disposed between the first node N1 of the resistor string 714 and the second node N2 of the resistor string 714, a divided voltage may be formed by dividing the top reference driving voltage VDDREF_Top and the middle reference driving voltage VDDREF_Mid according to the voltage distribution.

[0117] In each of the plurality of resistors disposed between the third node N3 of the resistor string 714 and the second node N2 of the resistor string 714, a divided voltage may be formed by dividing the bottom reference driving voltage VDDREF_Bot and the middle reference driving voltage VDDREF_Mid according to the voltage distribution.

[0118] The resistor string 714 may be electrically connected to the first multiplexer 715 through a plurality of upper connection lines. The plurality of upper connection lines may be electrically connected between the first node N1 and the second node N2.

[0119] The resistor string 714 can be electrically connected to the second multiplexer 716 through a plurality of lower connection lines. The plurality of lower connection lines can be electrically connected between the second node N2 and the third node N3. For the sake of illustration, if there are 100 upper connection lines and 100 lower connection lines, the upper connection lines can be expressed as the first connection line to the 100th connection line, and the lower connection lines can be expressed as the 101st connection line to the 200th connection line. The number of upper and lower connection lines can be changed according to the designs of the first multiplexer 715 and the second multiplexer 716.

[0120] For example, the number of resistors can be 1024. In this case, each of the plurality of resistors can be electrically connected between adjacent connection lines. For example, the first resistor can be electrically connected between the first connection line CL1 and the second connection line CL2. The 1023rd resistor can be electrically connected between the 1023rd connection line CL1023 and the 1024th connection line CL1024.

[0121] The feedback drive voltage generation circuit 710 can receive a 10-bit signal. The first multiplexer 715, the second multiplexer 716, and the third multiplexer 717 can be controlled based on the 10-bit signal. The most significant bit of the 10-bit signal can be supplied to the third multiplexer 717. The remaining 9-bit signals of the 10-bit signal can be supplied to the first multiplexer 715 and the second multiplexer 716. According to the most significant bit supplied to the third multiplexer 717, the first multiplexer 715 or the second multiplexer 716 can be selected.

[0122] For example, if the most significant bit is 1, the third multiplexer 717 can supply the first output voltage Vo1 to the third output line OL3. If the most significant bit is 0, the third multiplexer 717 can supply the second output voltage Vo2 to the third output line OL3.

[0123] The first multiplexer 715 can be electrically connected to the resistor string 714 through a plurality of upper connection lines. The first multiplexer 715 can select any one of the plurality of upper connection lines according to the 9-bit signal, and can transfer the voltage supplied to the upper connection line to the first output line OL1. That is, the first multiplexer 715 can include a plurality of switches, and can supply the voltage of any one of the upper connection lines to the first output line OL1 according to whether the switch is controlled.

[0124] For example, the first multiplexer 715 may be a 9-bit multiplexer. The first multiplexer 715 may receive a 9-bit signal. Each bit of the 9-bit signal may have a value of 0 or 1. In this case, the number of upper connection lines may be 512, and the first multiplexer 715 may be electrically connected to 512 upper connection lines. The 512 upper connection lines may be expressed as the first connection line CL1 to the 512th connection line CL512. The above 9-bit signal is an example and may be designed to be greater than or less than 9 bits.

[0125] For example, if a 9-bit signal for outputting the voltage of the first connection line CL1 adjacent to the first node N1 is supplied to the first multiplexer 715, the first multiplexer 715 may supply the voltage of the first connection line CL to the first output line OL1. In this case, the 9-bit signal may be 1 1111 1111. In this case, the most significant bit may be 1, and the 10-bit signal may be 11 1111 1111.

[0126] For example, the 9-bit signal for selecting the second connection line CL2 may be 1 1111 1110. In this case, the most significant bit may be 1, and the 10-bit signal may be 11 1111 1110.

[0127] For example, if a 9-bit signal for outputting the voltage of the 512th connection line CL512 adjacent to the second node N2 is supplied to the first multiplexer 715, the first multiplexer 715 may supply the voltage of the 512th connection line CL512 to the first output line OL1. In this case, the 9-bit signal may be 0 0000 0000. In addition, the most significant bit may be 1, and the 10-bit signal may be 10 0000 0000.

[0128] The second multiplexer 716 may be electrically connected to the resistor string 714 through a plurality of lower connection lines. The second multiplexer 716 may select one of the plurality of lower connection lines according to the bit signal and supply the voltage supplied to the lower connection line to the second output line OL2. That is, the second multiplexer 716 may include a plurality of switches and may supply the voltage of one lower connection line to the second output line OL2 according to whether the switch is controlled.

[0129] For example, the second multiplexer 716 may be a 9-bit multiplexer. The second multiplexer 716 may receive a 9-bit signal. Each bit of the 9-bit signal may have a value of 0 or 1. In this case, the number of lower connection lines may be 512, and the second multiplexer 716 may be electrically connected to 512 lower connection lines. The 512 lower connection lines may be expressed as the 513th connection line CL513 to the 1024th connection line CL1024. The above 9-bit signal is an example and may be designed to be greater than or less than 9 bits.

[0130] For example, if a 9-bit signal for outputting the voltage of the first lower connection line adjacent to the second node N2 is supplied to the second multiplexer 716, the second multiplexer 716 may supply the voltage of the 513th connection line CL513 to the second output line OL2. In this case, the 9-bit signal may be 0 0000 0000. Additionally, the most significant bit may be 0, and the 10-bit signal may be 00 00000000.

[0131] For example, if a 9-bit signal for outputting the voltage of the second lower connection line adjacent to the third node N3 is supplied to the second multiplexer 716, the second multiplexer 716 may supply the voltage of the 1024th connection line CL1024 to the second output line OL2. In this case, the 9-bit signal may be 1 1111 1111. Additionally, the most significant bit may be 0, and the 10-bit signal may be 01 11111111.

[0132] The voltage output from the first multiplexer 715 may be the first output voltage Vo1, and the voltage output from the second multiplexer 716 may be the second output voltage Vo2.

[0133] The third multiplexer 717 may be electrically connected to the first output line OL1 and the second output line OL2. The third multiplexer 717 may select one of the first output line OL1 and the second output line OL2 according to the most significant bit.

[0134] For example, the third multiplexer 717 may be a 1-bit multiplexer. The third multiplexer 717 may receive the most significant bit. The most significant bit may have a value of 0 or 1. If the most significant bit is 0, the third multiplexer 717 may supply the first output voltage Vo1 to the third output line OL3. If the most significant bit is 1, the third multiplexer 717 may supply the second output voltage Vo2 to the third output line OL3. The voltage supplied to the third output line OL3 may be referred to as the feedback drive voltage VDDFB.

[0135] The third multiplexer 717 may be electrically connected to the reference voltage conversion circuit 720 through the third output line OL3 to which the feedback drive voltage VDDFB is supplied.

[0136] The reference voltage conversion circuit 720 may generate a high reference voltage Vrg_H1 and a low reference voltage Vrg_L1 based on the feedback drive voltage VDDFB. The reference voltage conversion circuit 720 may supply the high reference voltage Vrg_H1 and the low reference voltage Vrg_L1 to the reference gamma voltage generation circuit 170.

[0137] The reference gamma voltage generation circuit 170 may be supplied with a high reference voltage Vrg_H1 generated based on the feedback driving voltage VDDFB and a low reference voltage Vrg_L1 generated based on the feedback driving voltage VDDFB, so as to compensate the reference gamma voltage Vrgm based on the voltage-reduced driving voltage VDD.

[0138] In addition, since the gamma voltage generation circuit 160 receives the reference gamma voltage Vrgm compensated based on the voltage-reduced driving voltage VDD, the gamma voltage generation circuit 160 may supply the compensated gamma voltage Vgm compensated based on the voltage-reduced driving voltage VDD to the digital-to-analog conversion circuit 133.

[0139] Hereinafter, an example of the operations of the gamma voltage compensation circuit 700, the reference gamma voltage generation circuit 170, and the gamma voltage generation circuit 160 will be described with reference to Figure 8 FIGs.

[0140] Figure 8 FIG. shows a scan signal supply direction and 10-bit signals according to an embodiment of the present disclosure.

[0141] Referring to Figure 8 FIG., the source film SF may be electrically connected between the display panel 110 and the source printed circuit board SPCB. The source film SF may include top source films SFa1, SFa2, SFa3, and SFa4 electrically connected to the top source printed circuit board SPCBa. In addition, the source film SF may include bottom source films SFb1, SFb2, SFb3, and SFb4 electrically connected to the bottom source printed circuit board SPCBb.

[0142] Referring to Figure 8 FIG., a scan signal supply direction, that is, a scan direction, is shown. The scan signals may be sequentially supplied to a plurality of gate lines. The scan direction may be from the top to the bottom of the display panel.

[0143] For example, the position of the display panel 110 is divided into a first row R1, a second row R2, a third row R3, a fourth row R4, a fifth row R5, a sixth row R6, and a seventh row R7. The first row R1 may be a row close to the top of the display panel 110, the seventh row R7 may be a row close to the bottom of the display panel 110, and the fourth row R4 may be a row corresponding to the center of the display panel 110. Referring to Figure 8 FIG., the scan signal supply direction (i.e., the scan direction) may proceed from the first row R1 to the seventh row R7.

[0144] Referring to Figure 8, which shows the most significant bit, 9-bit signal, and relative bit ratio shown in the table. The relative bit ratio may refer to the ratio of the distance from the center to the top (or bottom) of the display panel. Since the voltage drop of the driving voltage varies according to the distance to the top (or bottom) of the display panel, the relative bit ratio may mean the compensation ratio of the driving voltage.

[0145] For example, when a scan signal is supplied to a sub-pixel (not shown) arranged in the first row R1, the relative bit ratio may be 100%. In this case, the feedback driving voltage generation circuit 710 may receive a 10-bit signal of 11 1111 1111. The most significant bit is 1, and the remaining 9 bits may be 1 1111 1111. The binary number 1 1111 1111 corresponds to the decimal number 511, so 100% means the ratio of 511 / 511. Refer to Figure 7 and Figure 8 , a feedback driving voltage VDDFB may be generated based on the 10-bit signal of 11 1111 1111, and a gamma voltage may be generated based on the feedback driving voltage VDDFB. The data driving circuit 130 may output a data voltage to the data line based on the gamma voltage.

[0146] For example, when a scan signal is supplied to a sub-pixel (not shown) arranged in the second row R2, the relative bit ratio may be 34%. In this case, the feedback driving voltage generation circuit 710 may receive a 10-bit signal of 10 1010 1101. The most significant bit is 1, and the remaining 9 bits may be 0 1010 1101. The binary number 0 1010 1101 is the decimal number 173, so 34% may mean the ratio of 173 / 511. Refer to Figure 7 and Figure 8 , a feedback driving voltage VDDFB may be generated based on the 10-bit signal of 10 1010 1101, and a gamma voltage may be generated based on the feedback driving voltage VDDFB. The data driving circuit 130 may output a data voltage to the data line based on the gamma voltage.

[0147] For example, when a scan signal is supplied to a sub-pixel (not shown) arranged in the third row R3, the relative bit ratio may be 15%. In this case, the feedback driving voltage generation circuit 710 may receive a 10-bit signal of 10 0100 1100. The most significant bit is 1, and the remaining 9 bits may be 0 0100 1100. The binary number 0 0100 1100 is the decimal number 76, so 15% means the ratio of 76 / 511. Refer to Figure 7 and Figure 8, a feedback drive voltage VDDFB can be generated based on a 10-bit signal of 10 0100 1100, and a gamma voltage can be generated based on the feedback drive voltage VDDFB. The data drive circuit 130 can output a data voltage to the data line based on the gamma voltage.

[0148] For example, when a scan signal is supplied to a sub-pixel (not shown) arranged in the fourth row R4, the relative bit ratio can be 0%. In this case, the feedback drive voltage generation circuit 710 can receive a 10-bit signal of 00 0000 0000. The most significant bit is 0, and the remaining 9 bits can be 0 0000 0000. The binary number 0 0000 0000 is the decimal number 0, so 15% means a ratio of 0 / 511. Refer to Figure 7 and Figure 8 , a feedback drive voltage VDDFB can be generated based on a 10-bit signal of 00 0000 0000, and a gamma voltage can be generated based on the feedback drive voltage VDDFB. The data drive circuit 130 can output a data voltage to the data line based on the gamma voltage.

[0149] For example, when a scan signal is supplied to a sub-pixel (not shown) arranged in the fifth row R5, the relative bit ratio can be 15%. In this case, the feedback drive voltage generation circuit 710 can receive a 10-bit signal of 00 0100 1100. The most significant bit is 0, and the remaining 9 bits can be 0 0100 1100. The binary number 0 0100 1100 is the decimal number 76, so 15% means a ratio of 76 / 511. Refer to Figure 7 and Figure 8 , a feedback drive voltage VDDFB can be generated based on a 10-bit signal of 00 0100 1100, and a gamma voltage can be generated based on the feedback drive voltage VDDFB. The data drive circuit 130 can output a data voltage to the data line based on the gamma voltage.

[0150] For example, when a scan signal is supplied to a sub-pixel (not shown) arranged in the sixth row R6, the relative bit ratio can be 34%. In this case, the feedback drive voltage generation circuit 710 can receive a 10-bit signal of 00 1010 1101. The most significant bit is 0, and the remaining 9 bits can be 0 1010 1101. The binary number 0 1010 1101 is the decimal number 173, so 34% can mean a ratio of 173 / 511. Refer to Figure 7 and Figure 8 , a feedback drive voltage VDDFB can be generated based on a 10-bit signal of 00 1010 1101, and a gamma voltage can be generated based on the feedback drive voltage VDDFB. The data drive circuit 130 can output a data voltage to the data line based on the gamma voltage.

[0151] For example, when a scan signal is supplied to a sub-pixel (not shown) disposed in the seventh row R7, the relative bit ratio may be 100%. In this case, the feedback driving voltage generation circuit 710 may receive a 10-bit signal of 01 1111 1111. The most significant bit is 0, and the remaining 9 bits may be 1 1111 1111. The binary number 1 1111 1111 corresponds to the decimal number 511. Therefore, 100% means a ratio of 511 / 511. Refer to Figure 7 and Figure 8 , a feedback driving voltage VDDFB may be generated based on the 10-bit signal of 01 1111 1111, and a gamma voltage may be generated based on the feedback driving voltage VDDFB. The data driving circuit 130 may output a data voltage to the data line based on the gamma voltage.

[0152] Figure 9 FIG. shows the relative bit ratio according to the position of the display panel 110 according to an embodiment of the present disclosure.

[0153] Refer to Figure 9 , which shows the compensation ratio of the driving voltage according to the position of the display panel.

[0154] Refer to Figure 9 , Figure 7 The voltage of the first node N1 shown in may be the top reference driving voltage VDDREF_Top. Since the voltage of the first node N1 corresponds to the driving voltage of the highest row of the display panel 110, the voltage of the first node N1 may correspond to the maximum compensated feedback voltage. Therefore, the top reference driving voltage VDDREF_Top may correspond to a relative bit ratio of 100%.

[0155] Figure 7 The voltage of the third node N3 shown in may be the bottom reference driving voltage VDDREF_Bot. Since the voltage of the third node N3 corresponds to the driving voltage of the lowest row of the display panel 110, the voltage of the third node N3 may correspond to the maximum compensated feedback voltage. Therefore, the bottom reference driving voltage VDDREF_Bot may correspond to a relative bit ratio of 100%.

[0156] Figure 7 The voltage of the second node N2 shown in may be the middle reference driving voltage VDDREF_Mid. Since the voltage of the second node N2 corresponds to the driving voltage of the row in the central portion of the display panel 110, the voltage of the second node N2 may correspond to the minimum compensated feedback voltage. Therefore, the middle reference driving voltage VDDREF_Mid may correspond to a relative bit ratio of 0%.

[0157] Refer toFigure 9 The voltage corresponding to the middle position between the first node N1 and the second node N2 may correspond to a relative bit ratio of 50%.

[0158] Refer to Figure 9 The voltage corresponding to the middle position between the second node N2 and the third node N3 may correspond to a relative bit ratio of 50%.

[0159] Figures 10 to 13 An example of the operation of the gamma voltage compensation circuit 700 according to an embodiment of the present disclosure is shown.

[0160] Refer to Figure 10 The first multiplexer 715 may be electrically connected to the resistor string 714 through a plurality of upper connection lines, and the second multiplexer 716 may be electrically connected to the resistor string 714 through a plurality of lower connection lines.

[0161] Refer to Figure 10 To compensate for the voltage drop of the first row driving voltage VDD1, the first multiplexer 715 may select the first connection line CL1 to supply the first row driving voltage VDD1 to the third multiplexer 717. In this case, the third multiplexer 717 may be controlled to receive the first row driving voltage VDD1, and the third multiplexer 717 may supply a feedback driving voltage VDDFB that is the first row driving voltage VDD1 to the reference voltage conversion circuit 720. Thereafter, the reference voltage conversion circuit 720 may generate a high reference voltage Vrg_H1 and a low reference voltage Vrg_L1 based on the feedback driving voltage VDDFB. Since the feedback driving voltage VDDFB is the first row driving voltage VDD1, the high reference voltage Vrg_H1 and the low reference voltage Vrg_L1 may be generated based on the first row driving voltage VDD1. Therefore, the reference gamma voltage Vrgm and the gamma voltage Vgm generated based on the high reference voltage Vrg_H1 and the low reference voltage Vrg_L1 may also be generated based on the first row driving voltage VDD1. The gamma voltage Vgm generated based on the first row driving voltage VDD1 may be selected by the digital-to-analog converter DAC and may be supplied to a plurality of sub-pixels electrically connected to the first gate line GL1.

[0162] Refer to Figure 11, in order to compensate for the voltage drop phenomenon of the second row driving voltage VDD2, the first multiplexer 715 may select the second connection line CL2 to supply the second row driving voltage VDD2 to the third multiplexer 717. In this case, the third multiplexer 717 may be controlled to receive the second row driving voltage VDD2, and the third multiplexer 717 may supply a feedback driving voltage VDDFB, which is the second row driving voltage VDD2, to the reference voltage conversion circuit 720. Thereafter, the reference voltage conversion circuit 720 may generate a high reference voltage Vrg_H1 and a low reference voltage Vrg_L1 based on the feedback driving voltage VDDFB. Since the feedback driving voltage VDDFB is the second row driving voltage VDD2, the high reference voltage Vrg_H1 and the low reference voltage Vrg_L1 may be generated based on the second row driving voltage VDD2. Therefore, the reference gamma voltage Vrgm and the gamma voltage Vgm, which are generated based on the high reference voltage Vrg_H1 and the low reference voltage Vrg_L1, may also be generated based on the second row driving voltage VDD2. The gamma voltage Vgm generated based on the second row driving voltage VDD2 may be selected by the digital-to-analog converter DAC and may be supplied to a plurality of sub-pixels electrically connected to the second gate line GL2.

[0163] Referring to Figure 12 , in order to compensate for the voltage drop phenomenon of the driving voltage occurring in the 513th gate line row, the second multiplexer 716 may select the 513th connection line CL513 to supply the 513th row driving voltage VDD513 to the third multiplexer 717. In this case, the third multiplexer 717 may be controlled to receive the 513th row driving voltage VDD513, and the third multiplexer 717 may supply a feedback driving voltage VDDFB, which is the 513th row driving voltage VDD513, to the reference voltage conversion circuit 720. Thereafter, the reference voltage conversion circuit 720 may generate a high reference voltage Vrg_H1 and a low reference voltage Vrg_L1 based on the feedback driving voltage VDDFB. Since the feedback driving voltage VDDFB is the 513th row driving voltage VDD513, the high reference voltage Vrg_H1 and the low reference voltage Vrg_L1 may be generated based on the 513th row driving voltage VDD513. Therefore, the reference gamma voltage Vrgm and the gamma voltage Vgm, which are generated based on the high reference voltage Vrg_H1 and the low reference voltage Vrg_L1, may also be generated based on the 513th row driving voltage VDD513. The gamma voltage Vgm generated based on the 513th row driving voltage VDD513 may be selected by the digital-to-analog converter DAC and may be supplied to a plurality of sub-pixels electrically connected to the 513th gate line GL513.

[0164] Referring to Figure 13, in order to compensate for the voltage drop phenomenon of the driving voltage that occurs in the 1024th gate line row, the second multiplexer 716 may select the 1024th connection line CL1024 to supply the 1024th row driving voltage VDD1024 to the third multiplexer 717. In this case, the third multiplexer 717 may be controlled to receive the 1024th row driving voltage VDD1024, and the third multiplexer 717 may supply a feedback driving voltage VDDFB, which is the 1024th row driving voltage VDD1024, to the reference voltage conversion circuit 720. Thereafter, the reference voltage conversion circuit 720 may generate a high reference voltage Vrg_H1 and a low reference voltage Vrg_L1 based on the feedback driving voltage VDDFB. Since the feedback driving voltage VDDFB is the 1024th row driving voltage VDD1024, the high reference voltage Vrg_H1 and the low reference voltage Vrg_L1 may be generated based on the 1024th row driving voltage VDD1024. Therefore, the reference gamma voltage Vrgm and the gamma voltage Vgm, which are generated based on the high reference voltage Vrg_H1 and the low reference voltage Vrg_L1, may also be generated based on the 1024th row driving voltage VDD1024. The gamma voltage Vgm generated based on the 1024th row driving voltage VDD1024 may be selected by the digital-to-analog converter DAC and may be supplied to a plurality of sub-pixels electrically connected to the 1024th gate line GL1024.

[0165] Figures 14 to 20 The voltage line VL provided on the display panel 110 according to an embodiment of the present disclosure is shown.

[0166] Referring to Figures 14 to 19 , the source film SF may be electrically connected between the display panel 110 and the source printed circuit board SPCB. The voltage line VL may be provided on the display panel 110, the source film SF, and the source printed circuit board SPCB.

[0167] Referring to Figures 14 to 19 , the source film SF may include top source films SFa1, SFa2, SFa3, and SFa4 electrically connected to the top source printed circuit board SPCBa. In addition, the source film SF may include bottom source films SFb1, SFb2, SFb3, and SFb4 electrically connected to the bottom source printed circuit board SPCBb.

[0168] Referring to Figure 14 , Figure 16 and Figure 19, the first voltage line VL1 can be set parallel to the top TOP of the display panel. The first voltage line VL1 can be set to pass through the display panel 110 and through the first top source film SFa1 and the fourth top source film SFa4. The first voltage line VL1 can be set to transfer from the first top source film SFa1 and the fourth top source film SFa4 to the top source printed circuit board SPCBa. However, referring to Figure 15 , Figure 17 and Figure 18 , the first voltage line VL1 can be set on only one side of the top TOP of the display panel and on the top source printed circuit board SPCBa. One side of the top TOP of the display panel can be any one of the left side, the right side, and the area between the left side and the right side of the display panel 110.

[0169] Referring to Figure 14 , Figure 16 and Figure 19 , the second voltage line VL2 can be set parallel to the middle Mid of the display panel. The second voltage line VL2 can be set to pass through the display panel 110 and through the first top source film SFa1 and the fourth top source film SFa4. The second voltage line VL2 can be set to transfer from the first top source film SFa1 and the fourth top source film SFa4 to the top source printed circuit board SPCBa. In addition, the second voltage line VL2 can be set to pass through the display panel 110 and through the first bottom source film SFb1 and the fourth bottom source film SFb4. The second voltage line VL2 can be set to transfer from the first bottom source film SFb1 and the fourth bottom source film SFb4 to the bottom source printed circuit board SPCBb. However, referring to Figure 16 , Figure 17 and Figure 18 , the second voltage line VL2 can be set to pass through one of the top source films SFa1 and one of the bottom source films SFb4.

[0170] Referring to Figure 14 , Figure 16 and Figure 19 , the third voltage line VL3 can be set parallel to the bottom of the display panel. The third voltage line VL3 can be set to pass through the display panel 110 and through the first bottom source film SFb1 and the fourth bottom source film SFb4. The third voltage line VL3 can be set to transfer from the first bottom source film SFb1 and the fourth bottom source film SFb4 to the bottom source printed circuit board SPCBb. However, referring to Figure 15 , Figure 17 and Figure 18 , the third voltage line VL3 can be set on only one side of the bottom of the display panel and on the bottom source printed circuit board SPCBb. One side of the bottom of the display panel can be one of the left side, the right side, and the area between the left side and the right side of the display panel 110.

[0171] Reference Figure 19 , in addition to the first voltage line VL1 to the third voltage line VL3, the plurality of voltage lines VL may further include a fourth voltage line VL4 and a fifth voltage line VL5. Figure 19 The first voltage line VL1 to the third voltage line VL3 shown in Figure 14 may be the same as the voltage lines shown in Figure 19 Reference

[0172] Reference Figure 19 , the fifth voltage line VL5 may be set to correspond to the rows between the middle Mid and the top Top of the display panel 110. The fifth voltage line VL5 may be set to pass through the first lower source film SFb1 and the fourth lower source film SFb4 from the display panel 110. The fifth voltage line VL5 may be set to be transferred from the first lower source film SFb1 and the fourth lower source film SFb4 to the lower source printed circuit board SPCBb.

[0173] Meanwhile, referring to Figure 20 , the driving voltage VDD may be supplied to the display panel 110 in only one direction. The source films SFa1, SFa2, SFa3, and SFa4 may be electrically disposed between the display panel 110 and the top source printed circuit board SPCBa.

[0174] Reference Figure 20 , the first voltage line VL1 may be set parallel to the top of the display panel. The first voltage line VL1 may be set to pass through the first top source film SFa1 and the fourth top source film SFa4 from the display panel 110. The first voltage line VL1 may be set to be transferred from the first top source film SFa1 and the fourth top source film SFa4 to the top source printed circuit board SPCBa.

[0175] Reference Figure 20 , the second voltage line VL2 may be set parallel to the bottom of the display panel. The second voltage line VL2 may be set to pass through the first top source film SFa1 and the fourth top source film SFa4 from the display panel 110. The second voltage line VL2 may be set to be transferred from the first top source film SFa1 and the fourth top source film SFa4 to the top source printed circuit board SPCBa.

[0176] Figures 14 to 19The driving voltage supply method shown in [reference] can be referred to as a "dual feed method", and Figure 20 The driving voltage supply method shown in [reference] can be referred to as a "single feed method"

[0177] Referring to Figure 20 , in the case of the single feed method, the driving voltage VDD can be supplied from one side of the display panel 110 such that the voltage drop phenomenon of the driving voltage can occur weakest at the top region Top of the display panel 110, while the voltage drop phenomenon of the driving voltage can occur strongest at the bottom region of the display panel 110.

[0178] If the single feed method is applied, the second multiplexer 716 and the lines electrically connected to the second multiplexer 716 can be excluded from the gamma voltage compensation circuit 700. If the dual feed method is applied, the voltage drop of the driving voltage can occur symmetrically on both sides such that the first multiplexer 715 can be designed to receive the driving voltage on one side as feedback, and the second multiplexer 716 can receive the driving voltage on the other side as feedback. In the case of the single feed method, since the driving voltage VDD is supplied to only one side, the second multiplexer 716 and the lines electrically connected to the second multiplexer 716 can be excluded.

[0179] Figure 21 and Figure 22 show a reference voltage conversion circuit 720 according to an embodiment of the present disclosure.

[0180] Referring to Figure 21 and Figure 22 , the reference voltage conversion circuit 720 can receive the feedback driving voltage VDDFB from the gamma voltage compensation circuit 700. The reference voltage conversion circuit 720 can generate a high reference voltage Vrg_H1 and a low reference voltage Vrg_L1 based on the feedback driving voltage VDDFB. The reference voltage conversion circuit 720 can supply the high reference voltage Vrg_H1 and the low reference voltage Vrg_L1 to the reference gamma voltage generation circuit 170.

[0181] Referring to Figure 21 , the reference voltage conversion circuit 720 can include a first comparator circuit 721 and a second comparator circuit 722.

[0182] Referring to Figure 21, the first comparator circuit 721 can be configured as a comparator circuit capable of outputting a first comparison voltage Vrg_H1 based on the voltages supplied to two input terminals. The first comparator circuit 721 can receive a feedback drive voltage VDDFB through the first input terminal. The first comparator circuit 721 can receive an initial high reference voltage Vrg_H0 through the second input terminal. The first comparator circuit 721 can output the first comparison voltage Vrg_H1 based on the feedback drive voltage VDDFB and the initial high reference voltage Vrg_H0. The first comparison voltage Vrg_H1 can be the high reference voltage Vrg_H1. The relationship among the feedback drive voltage VDDFB, the initial high reference voltage Vrg_H0, and the high reference voltage Vrg_H1 can be "Vrg_H1 = 2*(1 / 2*Vrg_H0 + 1 / 2*VDDFB)".

[0183] Referring to Figure 21 , the second comparator circuit 722 can be configured as a comparator circuit capable of outputting a second comparison voltage Vrg_L1 based on the voltages supplied to two input terminals. The second comparator circuit 722 can receive a feedback drive voltage VDDFB through the first input terminal. The second comparator circuit 722 can receive an initial low reference voltage Vrg_L0 through the second input terminal. The second comparator circuit 722 can output the second comparison voltage Vrg_L1 based on the feedback drive voltage VDDFB and the initial low reference voltage Vrg_L0. The second comparison voltage Vrg_L1 can be the low reference voltage Vrg_L1. The relationship among the feedback drive voltage VDDFB, the initial low reference voltage Vrg_L0, and the low reference voltage Vrg_L1 can be "Vrg_L1 = 2*(1 / 2*Vrg_L0 + 1 / 2*VDDFB)".

[0184] Referring to Figure 22 , in addition to the first comparator circuit 721 and the second comparator circuit 722, the reference voltage conversion circuit 720 may further include a third comparator circuit 723.

[0185] Referring to Figure 22 , the third comparator circuit 723 can be configured as a comparator circuit capable of outputting a third comparison voltage VDDFB' based on the voltages supplied to two input terminals. The third comparator circuit 723 can receive a feedback drive voltage VDDFB through the first input terminal. The third comparator circuit 723 can receive an initial drive voltage VDD0 without voltage reduction through the second input terminal. The third comparator circuit 723 can output the third comparison voltage VDDFB' based on the feedback drive voltage VDDFB and the initial drive voltage VDD0. The relationship among the feedback drive voltage VDDFB, the initial drive voltage VDD0, and the third comparison voltage VDDFB' can be "VDDFB' = VDD0 - VDDFB".

[0186] Referring to Figure 22 , a third comparison voltage VDDFB' can be supplied to the first input terminal of the first comparator circuit 721 and the first input terminal of the second comparator circuit 722. Figure 21 The operations of the first comparator circuit 721 and the second comparator circuit 722 shown in Figure 20 can be the same as those of the first comparator circuit 721 and the second comparator circuit 722 shown in. In this case, the relational expression of the high reference voltage Vrg_H1 output from the first comparator circuit 721 can be "Vrg_H1 = Vrg_H0 - (VDD0 - VDDFB)", and the relational expression of the low reference voltage Vrg_L1 output from the second comparator circuit 722 can be "Vrg_L1 = Vrg_L0 - (VDD0 - VDDFB)".

[0187] Figure 23 and Figure 24 are graphs of voltages according to the operations of the feedback drive voltage generation circuit 710 and the reference voltage conversion circuit 720 according to an embodiment of the present disclosure.

[0188] Referring to Figure 23 , the power management circuit 150 can output an initial drive voltage VDD0 having the same voltage level to the display panel 110. A voltage drop may occur in the initial drive voltage VDD0, and the degree of the voltage drop may vary according to the position in the display panel 110. A weak voltage drop may occur in the top region and the bottom region, while the strongest voltage drop may occur in the middle region.

[0189] Referring to Figure 23 , according to the position, a voltage drop may occur in the drive voltage VDD, such that the distribution of the drive voltage VDD according to the position may be in a "U" shape. After the voltage drop occurs in the drive voltage VDD according to the position, the feedback drive voltage generation circuit 710 can operate to supply a feedback drive voltage VDDFB to the reference voltage conversion circuit 720. The reference voltage conversion circuit 720 can generate a high reference voltage Vrg_H1 and a low reference voltage Vrg_L1 based on the feedback drive voltage VDDFB.

[0190] Referring to Figure 24 , since the feedback drive voltage VDDFB reflects the drive voltage VDD having a voltage drop in a "U" shape, the voltage distributions of the high reference voltage Vrg_H1 and the low reference voltage Vrg_L1 can represent a "U" shape.

[0191] Thereafter, the reference voltage conversion circuit 720 can supply the high reference voltage Vrg_H1 and the low reference voltage Vrg_L1 to the reference gamma voltage generation circuit 170.

[0192] The reference gamma voltage generation circuit 170 may be supplied with a high reference voltage Vrg_H1 generated based on the feedback drive voltage VDDFB and a low reference voltage Vrg_L1 generated based on the feedback drive voltage VDDFB, such that the reference gamma voltage Vrgm can be compensated based on the voltage-reduced drive voltage VDD.

[0193] In addition, since the gamma voltage generation circuit 160 receives the reference gamma voltage Vrgm compensated based on the voltage-reduced drive voltage VDD, the gamma voltage generation circuit 160 can supply the compensated gamma voltage Vgm, which is compensated based on the voltage-reduced drive voltage VDD, to the digital-to-analog conversion circuit 133.

[0194] Referring to Figure 23 and Figure 24 , since the gamma voltage Vgm is generated based on the high reference voltage Vrg_H1 and the low reference voltage Vrg_L1 formed in a "U"-shaped voltage distribution, the voltage distribution of the data voltage Vdata can also represent a "U" shape.

[0195] According to an embodiment of the present disclosure, the voltage reduction phenomenon of the drive voltage VDD can be compensated.

[0196] According to an embodiment of the present disclosure, the brightness of the display panel 110 can be equalized.

[0197] According to an embodiment of the present disclosure, low power consumption can be achieved by equalizing the brightness of the display panel 110.

[0198] Figure 25 is a flowchart showing a driving method of a display device according to an embodiment of the present disclosure.

[0199] The driving method of the display device according to an embodiment of the present disclosure may include a gamma voltage compensation circuit driving step (S2510), a reference gamma voltage generation circuit driving step (S2520), and a gamma voltage generation circuit driving step (S2530).

[0200] In the first step, which is the gamma voltage compensation circuit driving step (S2510), the gamma voltage compensation voltage 700 may supply the high reference voltage Vrg_H1 and the low reference voltage Vrg_L1 to the reference gamma voltage generation circuit 170.

[0201] The second step, which is the reference gamma voltage generation circuit driving step (S2520), may be a step of generating a plurality of reference gamma voltages Vrgm based on the high reference voltage Vrg_H1 and the low reference voltage Vrg_L1 and supplying them to the gamma voltage generation circuit 160.

[0202] As a third step of the gamma voltage generation circuit driving step (S2530), it may be a step of supplying a plurality of gamma voltages Vgm to the data driving circuit 130 based on a plurality of reference gamma voltages Vrgm. The gamma voltage compensation circuit 700 may be electrically connected to the display panel through a first voltage line and a second voltage line.

[0203] Embodiments of the present disclosure are briefly described as follows.

[0204] Embodiments of the present disclosure may provide a display device including: a data driving circuit configured to be supplied with a plurality of gamma voltages; a gamma voltage generation circuit configured to supply a plurality of gamma voltages to the data driving circuit; a reference gamma voltage generation circuit configured to generate a plurality of reference gamma voltages based on a high reference voltage and a low reference voltage and supply the plurality of reference gamma voltages to the gamma voltage generation circuit; and a gamma voltage compensation circuit configured to supply the high reference voltage and the low reference voltage to the reference gamma voltage generation circuit, wherein the gamma voltage compensation circuit is electrically connected to the display panel through a first voltage line and a second voltage line.

[0205] The gamma voltage compensation circuit may be supplied with a first reference driving voltage through the first voltage line and supplied with a second reference driving voltage through the second voltage line.

[0206] The gamma voltage compensation circuit may include: a feedback driving voltage generation circuit configured to generate a feedback driving voltage based on the first reference driving voltage and the second reference driving voltage, and a reference voltage conversion circuit configured to generate a high reference voltage and a low reference voltage based on the feedback driving voltage.

[0207] The feedback driving voltage generation circuit may include: a first buffer electrically connected to the first voltage line; a second buffer electrically connected to the second voltage line; a resistor string electrically connected to the first buffer and a first node and electrically connected to the second buffer and a second node; and a multiplexer electrically connected to the resistor string through a plurality of connection lines.

[0208] A plurality of gate lines may be provided on the display panel. When a turn-on scan signal is supplied to the first gate line, the multiplexer may select a first connection line.

[0209] The voltage supplied to the multiplexer through the first connection line may correspond to the driving voltage of the sub-pixel electrically connected to the first gate line.

[0210] The multiplexer may include a plurality of switches, and the multiplexer may control the plurality of switches to select one of the plurality of connection lines.

[0211] The first voltage line may be electrically connected to a first region of the display panel, and the second voltage line may be electrically connected to a second region of the display panel. A driving voltage in the second region may be less than a driving voltage in the first region.

[0212] The first voltage line may be arranged to be parallel to a gate line provided in the first region, and the second voltage line may be arranged to be parallel to a gate line provided in the second region.

[0213] A third voltage line may be electrically connected to a third region of the display panel. The first voltage line may be electrically connected to a gamma voltage compensation circuit through an upper source printed circuit board, and the third voltage line may be electrically connected to the gamma voltage compensation circuit through a lower source printed circuit board.

[0214] The reference voltage conversion circuit may include: a first comparator circuit configured to output a high reference voltage based on a feedback driving voltage and an initial high reference voltage; and a second comparator circuit configured to output a low reference voltage based on the feedback driving voltage and an initial low reference voltage.

[0215] The reference voltage conversion circuit may include: a first comparator circuit configured to output a high reference voltage based on a first input voltage and an initial high reference voltage; a second comparator circuit configured to output a low reference voltage based on the first input voltage and an initial low reference voltage; and a third comparator circuit configured to output the first input voltage based on the feedback driving voltage and an initial driving voltage.

[0216] The display panel may include a plurality of gate lines. A first high reference voltage when a turn-on scan signal is supplied to a first gate line may be greater than a second high reference voltage when a turn-on scan signal is supplied to a second gate line. In addition, a first low reference voltage when a turn-on scan signal is supplied to the first gate line may be greater than a second low reference voltage when a turn-on scan signal is supplied to the second gate line.

[0217] The data driving circuit may select and output a gamma voltage corresponding to image data among a plurality of gamma voltages.

[0218] Embodiments of the present disclosure may provide a driving method of a display device, the driving method including: supplying a high reference voltage and a low reference voltage from a gamma voltage compensation circuit to a reference gamma voltage generation circuit; generating a plurality of reference gamma voltages based on the high reference voltage and the low reference voltage and supplying the plurality of reference gamma voltages to a gamma voltage generation circuit; and supplying a plurality of gamma voltages to a data driving circuit based on the plurality of reference gamma voltages, wherein the gamma voltage compensation circuit is electrically connected to a display panel of the display device through a first voltage line and a second voltage line.

[0219] When supplying a high reference voltage and a low reference voltage, the gamma voltage compensation circuit can be supplied with a first reference driving voltage through a first voltage line and supplied with a second reference driving voltage through a second voltage line.

[0220] The gamma voltage compensation circuit can include: a feedback driving voltage generation circuit configured to generate a feedback driving voltage based on the first reference driving voltage and the second reference driving voltage; and a reference voltage conversion circuit configured to generate a high reference voltage and a low reference voltage based on the feedback driving voltage.

[0221] The feedback driving voltage generation circuit can include: a first buffer electrically connected to the first voltage line; a second buffer electrically connected to the second voltage line; a resistor string electrically connected to the first buffer and a first node and electrically connected to the second buffer and a second node; and a multiplexer electrically connected to the resistor string through a plurality of connection lines.

[0222] A plurality of gate lines can be provided on the display panel. When a turn-on scan signal is supplied to a first gate line, the multiplexer can select a first connection line.

[0223] The first voltage line can be electrically connected to a first area of the display panel, and the second voltage line can be electrically connected to a second area of the display panel. In addition, the driving voltage in the second area can be less than the driving voltage in the first area.

[0224] Embodiments of the present disclosure can provide a driving method of a display device, the driving method including: supplying a first reference driving voltage through a first voltage line and supplying a second reference driving voltage through a second voltage line from a display panel of the display device; generating a feedback driving voltage based on the first reference driving voltage and the second reference driving voltage; generating a high reference voltage and a low reference voltage based on the feedback driving voltage; generating a plurality of reference gamma voltages based on the high reference voltage and the low reference voltage; generating a plurality of gamma voltages based on the plurality of reference gamma voltages; and selecting and supplying a gamma voltage corresponding to image data among the plurality of gamma voltages to the display panel.

[0225] The first voltage line can be electrically connected to a first area of the display panel, and the second voltage line can be electrically connected to a second area of the display panel. In addition, the driving voltage in the second area can be less than the driving voltage in the first area.

[0226] The above description and drawings provide examples of the technical concept of the present disclosure for illustrative purposes only. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. In addition, the disclosed embodiments are intended to illustrate the scope of the technical concept of the present disclosure. Therefore, the scope of the present disclosure is not limited to the embodiments shown.

Claims

1. A display device, comprising: a data driving circuit configured to be supplied with a plurality of gamma voltages; a gamma voltage generating circuit configured to supply the plurality of gamma voltages to the data driving circuit; a reference gamma voltage generating circuit configured to generate a plurality of reference gamma voltages based on a high reference voltage and a low reference voltage and supply the plurality of reference gamma voltages to the gamma voltage generating circuit; as well as a gamma voltage compensation circuit configured to supply the high reference voltage and the low reference voltage to the reference gamma voltage generating circuit, Wherein, the gamma voltage compensation circuit is electrically connected to the display panel through a first voltage line and a second voltage line.

2. The display device according to claim 1, wherein: The gamma voltage compensation circuit is supplied with a first reference driving voltage through the first voltage line, and is supplied with a second reference driving voltage through the second voltage line.

3. The display device according to claim 2, wherein: The gamma voltage compensation circuit comprises: a feedback driving voltage generating circuit configured to generate a feedback driving voltage based on the first reference driving voltage and the second reference driving voltage; and A reference voltage conversion circuit is configured to generate the high reference voltage and the low reference voltage based on the feedback driving voltage.

4. The display device according to claim 3, wherein: The feedback drive voltage generating circuit comprises: a first buffer electrically connected to the first voltage line; a second buffer electrically connected to the second voltage line; a resistor string electrically connected to the first buffer and a first node and electrically connected to the second buffer and a second node; and A multiplexer is electrically connected to the resistor string through a plurality of connection lines.

5. The display device according to claim 4, wherein: A plurality of gate lines are arranged on the display panel. Wherein, when the on scan signal is supplied to the first gate line, the multiplexer selects the first connection line.

6. The display device according to claim 5, wherein: The voltage supplied to the multiplexer through the first connection line corresponds to a driving voltage supplied to the sub-pixel electrically connected to the first gate line.

7. The display device according to claim 4, wherein: The multiplexer includes a plurality of switches, The multiplexer controls the multiple switches to select one of the multiple connection lines.

8. The display device according to claim 1, wherein: The first voltage line is electrically connected to a first area of ​​the display panel, and the second voltage line is electrically connected to a second area of ​​the display panel, Wherein, the driving voltage in the second region is smaller than the driving voltage in the first region.

9. The display device according to claim 8, wherein: The first voltage line is disposed in parallel to a gate line disposed in the first region, and the second voltage line is disposed in parallel to a gate line disposed in the second region.

10. The display device according to claim 8, wherein: The third voltage line is electrically connected to the third area of ​​the display panel, Wherein, the first voltage line is electrically connected to the gamma voltage compensation circuit through an upper source printed circuit board, Wherein, the third voltage line is electrically connected to the gamma voltage compensation circuit through a lower source printed circuit board.

11. The display device according to claim 3, wherein: The reference voltage conversion circuit comprises: a first comparator circuit configured to output the high reference voltage based on the feedback drive voltage and an initial high reference voltage; and A second comparator circuit is configured to output the low reference voltage based on the feedback drive voltage and an initial low reference voltage.

12. The display device according to claim 3, wherein: The reference voltage conversion circuit comprises: a first comparator circuit configured to output the high reference voltage based on a first input voltage and an initial high reference voltage; a second comparator circuit configured to output the low reference voltage based on the first input voltage and an initial low reference voltage; and A third comparator circuit is configured to output the first input voltage based on the feedback driving voltage and an initial driving voltage.

13. The display device according to claim 3, wherein: The display panel includes a plurality of gate lines. wherein a first high reference voltage when a turn-on scan signal is supplied to the first gate line is greater than a second high reference voltage when the turn-on scan signal is supplied to the second gate line, Wherein, a first low reference voltage when the on-scan signal is supplied to the first gate line is greater than a second low reference voltage when the on-scan signal is supplied to the second gate line.

14. The display device according to claim 1, wherein: The data driving circuit selects and outputs a gamma voltage corresponding to image data from among the plurality of gamma voltages.

15. A method for driving a display device, comprising: The gamma voltage compensation circuit supplies a high reference voltage and a low reference voltage to the reference gamma voltage generation circuit; generating a plurality of reference gamma voltages based on the high reference voltage and the low reference voltage and supplying the plurality of reference gamma voltages to a gamma voltage generating circuit; as well as supplying a plurality of gamma voltages to a data driving circuit based on the plurality of reference gamma voltages, The gamma voltage compensation circuit is electrically connected to the display panel of the display device through a first voltage line and a second voltage line.

16. The driving method according to claim 15, wherein: The gamma voltage compensation circuit is supplied with a first reference driving voltage through the first voltage line and is supplied with a second reference driving voltage through the second voltage line when a high reference voltage and a low reference voltage are supplied.

17. The driving method according to claim 16, wherein: The gamma voltage compensation circuit comprises: a feedback driving voltage generating circuit configured to generate a feedback driving voltage based on the first reference driving voltage and the second reference driving voltage; and A reference voltage conversion circuit is configured to generate the high reference voltage and the low reference voltage based on the feedback driving voltage.

18. The driving method according to claim 17, wherein: The feedback drive voltage generating circuit comprises: a first buffer electrically connected to the first voltage line; a second buffer electrically connected to the second voltage line; a resistor string electrically connected to the first buffer and a first node and electrically connected to the second buffer and a second node; and A multiplexer is electrically connected to the resistor string through a plurality of connection lines.

19. The driving method according to claim 18, wherein: A plurality of gate lines are arranged on the display panel. Wherein, when the on scan signal is supplied to the first gate line, the multiplexer selects the first connection line.

20. The driving method according to claim 15, wherein: The first voltage line is electrically connected to a first area of ​​the display panel, and the second voltage line is electrically connected to a second area of ​​the display panel, Wherein, the driving voltage in the second region is smaller than the driving voltage in the first region.

21. A method for driving a display device, comprising: supplying a first reference driving voltage through a first voltage line and a second reference driving voltage through a second voltage line from a display panel of the display device; generating a feedback driving voltage based on the first reference driving voltage and the second reference driving voltage; generating a high reference voltage and a low reference voltage based on the feedback drive voltage; generating a plurality of reference gamma voltages based on the high reference voltage and the low reference voltage; generating a plurality of gamma voltages based on the plurality of reference gamma voltages; as well as A gamma voltage corresponding to image data among the plurality of gamma voltages is selected and supplied to the display panel.

22. The driving method according to claim 21, wherein: The first voltage line is electrically connected to a first area of ​​the display panel, and the second voltage line is electrically connected to a second area of ​​the display panel, Wherein, the driving voltage in the second region is smaller than the driving voltage in the first region.

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