Gate drive circuit and display device

Abstract

The invention discloses a gate drive circuit and a display device. The gate drive circuit includes a first gate drive circuit and a second gate drive circuit. The first gate drive circuit includes first shift registers of first stages to Nth stages respectively configured to output first scanning signals of first stages to Nth stages, and the first scanning signals of first stages to Nth stages are respectively transmitted to N scanning lines. The second gate drive circuit includes first-stage to Nth-stage second shift registers respectively configured to output first-stage to Nth-stage second scanning signals, and the first-stage to Nth-stage second scanning signals are respectively transmitted to the other N scanning lines. And the number of the transistors in each second shift register from the first stage to the Nth stage is smaller than the number of the transistors in each first shift register from the first stage to the Nth stage. The frame width of the display device can be reduced, and the power consumption can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to a gate driving circuit and a display device, and particularly to a gate driving circuit for performing a scanning operation on a display panel and a display device including the gate driving circuit. Background Art

[0002] Flat panel display devices, such as liquid crystal display devices or organic light-emitting diode (OLED) display devices, etc., generally have a plurality of shift registers for controlling the gray scale displayed by each pixel in the display device at the same time point. However, the circuit design of the shift register needs to consider the correctness of the signal output corresponding to each time point to ensure the image display quality of the display device. On the other hand, there are currently many flat panel display devices with shift registers fabricated on an active array substrate, which reduces the use of driving wafers and the process of bonding the driving wafers to the display panel, so the manufacturing cost can be effectively reduced. However, fabricating the shift register on the active array substrate will increase the area of the display device, which is not conducive to the narrow bezel design and is accompanied by higher power consumption. Summary of the Invention

[0003] An object of the present invention is to provide a gate driving circuit and a display device having the gate driving circuit, which can reduce the bezel width of the display device and / or increase the layout area of other circuits in the display device, and can effectively reduce the power consumption.

[0004] According to the above object, the present invention provides a gate driving circuit for driving a plurality of scan lines of a display panel. The gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The first gate driving circuit includes first shift registers of the first stage to the Nth stage, which are respectively configured to output first scan signals of the first stage to the Nth stage, and the first scan signals of the first stage to the Nth stage are respectively transmitted to N scan lines among the plurality of scan lines, where N is a positive integer greater than or equal to 4. The second gate driving circuit includes second shift registers of the first stage to the Nth stage, which are respectively configured to output second scan signals of the first stage to the Nth stage, and the second scan signals of the first stage to the Nth stage are respectively transmitted to another N scan lines among the plurality of scan lines. The number of transistors in each of the first stage to the Nth stage of the second shift registers is less than the number of transistors in each of the first stage to the Nth stage of the first shift registers.

[0005] According to an embodiment of the present invention, each of the first stage to the Nth stage of the first shift registers has a first width, each of the first stage to the Nth stage of the second shift registers has a second width, and the first width is greater than the second width.

[0006] According to another embodiment of the present invention, each of the second shift registers from the first stage to the Nth stage is configured to receive a first input signal, and the first input signal of the ith second shift register among the second shift registers from the first stage to the Nth stage is a corresponding one of the first scan signals from the first stage to the Nth stage, where i is a positive integer greater than or equal to 1 and less than or equal to N.

[0007] According to another embodiment of the present invention, each of the second shift registers from the first stage to the Nth stage is further configured to receive a second input signal, and the second input signal of the jth second shift register among the second shift registers from the first stage to the (N - 1)th stage is a corresponding one of the first scan signals from the first stage to the Nth stage, where j is a positive integer greater than or equal to 1 and less than or equal to (N - 1).

[0008] According to another embodiment of the present invention, the first gate driving circuit further includes a dummy shift register configured to receive one of the first scan signals from the first stage to the Nth stage, and the dummy shift register outputs a dummy scan signal, where the second input signal of the Nth second shift register is the dummy scan signal.

[0009] According to another embodiment of the present invention, the second gate driving circuit further includes a scan control signal line coupled to the Nth second shift register, and the second input signal of the Nth second shift register is a scan control signal provided by the scan control signal line.

[0010] According to another embodiment of the present invention, the second gate driving circuit further includes at least one clock signal line, and the ith second shift register among the second shift registers from the first stage to the Nth stage includes a first transistor, a second transistor, and a third transistor, where i is a positive integer greater than or equal to 1 and less than or equal to N. The first end and the control end of the first transistor are respectively used to receive a first voltage signal and a first input signal, and the second end of the first transistor is coupled to a first node. The first end and the control end of the second transistor are respectively used to receive a second voltage signal and a second input signal, and the second end of the second transistor is coupled to the first node. The first end of the third transistor is used to receive a clock signal provided by a corresponding one of the at least one clock signal line, the second end of the third transistor is coupled to a second node and is used to output the ith second scan signal, and the control end of the third transistor is coupled to the first node.

[0011] According to another embodiment of the present invention, the second shift register of the i-th stage further includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The first end of the fourth transistor is used to receive a reference potential, and the control end of the fourth transistor is coupled to the first node. The first end of the fifth transistor is used to receive a reference potential, and the second end and the control end of the fifth transistor are respectively coupled to the first node and the second end of the fourth transistor. The first end of the sixth transistor is used to receive a reference potential, and the second end and the control end of the sixth transistor are respectively coupled to the second node and the second end of the fourth transistor. The first end and the control end of the seventh transistor are used to receive a voltage signal, and the second end of the seventh transistor is coupled to the second end of the fourth transistor.

[0012] According to the above object, the present invention further provides a display device, including a display panel and a gate driving circuit. The display panel has an active area and a peripheral area, and includes a plurality of scan lines located in the active area. The gate driving circuit is located in the peripheral area and configured to drive the plurality of scan lines of the display panel. It includes a first gate driving circuit and a second gate driving circuit. The first gate driving circuit includes first shift registers of the first stage to the N-th stage, which are respectively configured to output first scan signals of the first stage to the N-th stage, and the first scan signals of the first stage to the N-th stage are respectively transmitted to N scan lines among the plurality of scan lines, where N is a positive integer greater than or equal to 4. The second gate driving circuit includes second shift registers of the first stage to the N-th stage, which are respectively configured to output second scan signals of the first stage to the N-th stage, and the second scan signals of the first stage to the N-th stage are respectively transmitted to another N scan lines among the plurality of scan lines. The number of transistors in each of the second shift registers of the first stage to the N-th stage is less than the number of transistors in each of the first shift registers of the first stage to the N-th stage.

[0013] According to another embodiment of the present invention, the peripheral area includes a first sub-peripheral area and a second sub-peripheral area, which are respectively located outside the opposite sides of the active area. The first gate driving circuit and the second gate driving circuit are respectively located in the first sub-peripheral area and the second sub-peripheral area. Each of the first shift registers of the first stage to the N-th stage has a first width, each of the second shift registers of the first stage to the N-th stage has a second width, and the first width is greater than the second width.

[0014] The beneficial effects of the present invention are at least that, through the special design of the gate driving circuit, the border width of the display device can be reduced and / or the layout area of other circuits in the display device can be increased. Description of the Drawings

[0015] To more fully understand the embodiments and their advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 Schematic diagram of a display device according to embodiments of the present invention;

[0017] Figure 2 For the first embodiment of the present invention Figure 1 A schematic circuit diagram of the active region, the first gate driving circuit, and the second gate driving circuit

[0018] Figure 3A Is Figure 2 An equivalent circuit diagram of the first shift register in the first gate driving circuit of

[0019] Figure 3B Is Figure 2 An equivalent circuit diagram of the dummy shift register in the first gate driving circuit of

[0020] Figure 3C Is Figure 2 An equivalent circuit diagram of the first to (N - 1)th stage second shift registers in the second gate driving circuit of

[0021] Figure 3D Is Figure 2 An equivalent circuit diagram of the Nth stage second shift register in the second gate driving circuit of

[0022] Figure 4 For the second embodiment of the present invention Figure 1 A schematic circuit diagram of the active region, the first gate driving circuit, and the second gate driving circuit

[0023] Figure 5 Is a signal timing diagram of the first gate driving circuit and the second gate driving circuit corresponding to the first and second embodiments of the present invention within one frame period

[0024] Figures 6A to 6D Illustrates the signal flow directions of the respective transistors in the second shift register at different time points

[0025] Figure 7 For the third embodiment of the present invention Figure 1 A schematic circuit diagram of the active region, the first gate driving circuit, and the second gate driving circuit

[0026] Figure 8 Is a signal timing diagram of the first gate driving circuit and the second gate driving circuit corresponding to the third embodiment of the present invention within one frame period

[0027] Figure 9 For the third embodiment of the present invention Figure 1 A schematic circuit diagram of the active region, the first gate driving circuit, and the second gate driving circuit

[0028] Figure 10A signal timing diagram of the first gate driving circuit and the second gate driving circuit corresponding to the third embodiment of the present invention within one frame period;

[0029] Figure 11A is Figure 1 a schematic diagram of the configuration of the active area and the peripheral area in the display panel of;

[0030] Figure 11B is Figure 1 another schematic diagram of the configuration of the active area and the peripheral area in the display panel of. Detailed Embodiments

[0031] The embodiments of the present disclosure are discussed in detail below. However, it can be understood that the embodiments provide many applicable concepts that can be implemented in various specific contexts. The discussed and disclosed embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

[0032] The terms used herein are only for describing specific embodiments and are not intended to limit the scope of the patent application. Unless otherwise restricted, the singular forms of the terms "a" or "the" can also be used to represent the plural forms.

[0033] It can be understood that although the terms "first", "second", etc. can be used herein to describe various features, these terms should not limit these features. These terms are only used to distinguish one feature from another.

[0034] The use of spatially relative terms is to describe the different orientations of elements during use or operation, and is not limited to the directions shown in the drawings. The elements can also be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptions used herein can be interpreted in the same way.

[0035] Figure 1Schematic diagram of a display device 100 according to various embodiments of the present invention. The display device 100 includes a display panel 110, a gate driving circuit 120, and a source driving circuit 130. The display panel 110 can be various types of liquid crystal display panels, such as a twisted nematic (TN) type, an in-plane switching (IPS) type, a fringe-field switching (FFS) type, or a vertical alignment (VA) type, or can be, for example, an organic light-emitting diode (OLED), a mini LED display panel, a micro LED display panel, a quantum dot light-emitting diode (QDLED), or other suitable display panels. The display panel 110 includes an active array substrate 112, and the active array substrate 112 includes a plurality of data lines DL, a plurality of scan lines SL, and a plurality of pixels PX. The gate driving circuit 120 includes a first gate driving circuit 120A and a second gate driving circuit 120B. The first gate driving circuit 120A and the second gate driving circuit 120B are respectively disposed on opposite sides of the display panel 110 and are both electrically connected to the display panel 110. They are used to respectively generate a plurality of scan signals and transmit the plurality of scan signals to the plurality of scan lines SL of the display panel 110. The source driving circuit 130 is electrically connected to the display panel 110. It is used to convert image data into source driving signals and transmit the source driving signals to the plurality of data lines DL of the display panel 110.

[0036] The display panel 110 has an active area 110A and a peripheral area 110B. The plurality of data lines DL, the plurality of scan lines SL, and the plurality of pixels PX are located in the active area 110A. The transistors TFT of each pixel PX are electrically connected to the corresponding scan line SL and data line DL. These pixels PX are driven by the source driving signals and scan signals to display images. The first gate driving circuit 120A and the second gate driving circuit 120B are located in the peripheral area 110B, and the peripheral area 110B has a plurality of wirings (not shown in the figure). They are respectively coupled to the first gate driving circuit 120A, the second gate driving circuit 120B, and the source driving circuit 130, and are respectively coupled to the plurality of data lines DL and the plurality of scan lines SL in the active area 110A to respectively send the source driving signals and scan signals to the transistors TFT of the corresponding pixels PX on the active array substrate 112, so that the pixels PX are controlled by the on / off of the transistors TFT to display the corresponding gray levels at specific times.

[0037] The display device 100 of the present invention may be a system on glass (SOG). In the present invention, the first gate driving circuit 120A and the second gate driving circuit 120B are fabricated in the display panel 110, that is, the active array substrate 112 of the display panel 110 includes the first gate driving circuit 120A and the second gate driving circuit 120B. In this way, the electronic components in the display panel 110, the first gate driving circuit 120A, and the second gate driving circuit 120B can be fabricated simultaneously using the same process. For example, the transistors in the first gate driving circuit 120A and the second gate driving circuit 120B can be fabricated simultaneously with the transistors TFT in the active area 110A of the display panel 110 using the same process. In some embodiments, the source driving circuit 130 may also be fabricated in the peripheral area 110B of the display panel 110, and the electronic components and wirings in the display panel 110, the first gate driving circuit 120A, the second gate driving circuit 120B, and the source driving circuit 130 can be fabricated simultaneously using the same process.

[0038] Figure 2 FIG. is a schematic circuit diagram of the active area 110A, the first gate driving circuit 120A, and the second gate driving circuit 120B according to the first embodiment of the present invention. To simplify the drawings, Figure 2 omitted Figure 1 multiple data lines DL and multiple pixels PX in. As Figure 2 shown, the first gate driving circuit 120A and the second gate driving circuit 120B are respectively located in the peripheral areas (i.e., Figure 1 the peripheral area 110B of) outside the opposite sides of the active area 110A. As Figure 2 shown, the first gate driving circuit 120A includes the first shift registers LSR(1)-LSR(N) of the first stage to the Nth stage, and the second gate driving circuit 120B includes the second shift registers RSR(1)-RSR(N) of the first stage to the Nth stage, where N is a positive integer greater than or equal to 4. The display panel 110 includes 2N scan lines SL (i.e., scan lines SL1-SL 2N ), and the first shift registers LSR(1)-LSR(N) of the first stage to the Nth stage are used to respectively provide the first scan signals LG1-LG N of the ith stage to the Nth stage to N scan lines SL among the 2N scan lines SL, and the second shift registers RSR(1)-RSR(N) of the first stage to the Nth stage are used to respectively provide the second scan signals RG1-RG N of the ith stage to the Nth stage to the other N scan lines SL among the 2N scan lines SL. Specifically, the first shift registers LSR(1)-LSR(N) of the first stage to the Nth stage are used to respectively provide the first scan signals LG1-LGN to the odd-level scan lines (i.e., scan lines SL1, SL3, …, SL (2N-1) ) in the display panel 110, and the first to Nth second shift registers RSR(1)-RSR(N) are used to respectively provide the first to Nth second scan signals RG1-RG N to the even-level scan lines (i.e., scan lines SL2, SL4, …, SL 2N ) in the display panel 110. The scan lines SL1, SL2, …, SL (2N-1) , SL 2N can also be respectively referred to as the first-level scan line, the second-level scan line, …, the (2N-1)th-level scan line and the 2Nth-level scan line. In this embodiment, multiple scan lines SL are arranged along a direction, and the odd-level scan lines (i.e., scan lines SL1, SL3, …, SL (2N-1) ) and the even-level scan lines (i.e., scan lines SL2, SL4, …, SL 2N ) among the multiple scan lines SL are alternately arranged along the direction. In addition, the first to Nth first scan signals LG1-LG N generated by the first to Nth first shift registers LSR(1)-LSR(N) can be transmitted to the first to Nth second shift registers RSR(1)-RSR(N) in addition to being transmitted to the odd-level scan lines in the display panel 110 as input signals of the first to Nth second shift registers RSR(1)-RSR(N). As Figure 2 shown, the first to Nth first shift registers LSR(1)-LSR(N) can respectively provide the first to Nth first scan signals LG1-LG (2N-1) to the first to Nth second shift registers RSR(1)-RSR(N) through the odd-level scan lines SL1, SL3, …, SL N , but the manner in which the first to Nth first scan signals LG1-LG N of this embodiment are transmitted to the first to Nth second shift registers RSR(1)-RSR(N) is not limited thereto. In this embodiment, the first to Nth first shift registers LSR(1)-LSR(N) and the first to Nth second shift registers RSR(1)-RSR(N) can be a gate driver on array (GOA) circuit structure. That is to say, Figure 1 the active array substrate 112 in

[0039] In this embodiment, the first gate driving circuit 120A further includes a dummy shift register DSR, which is used to provide a dummy scan signal DG to the Nth second shift register RSR(N) in the second gate driving circuit 120B as an input signal of the Nth second shift register RSR(N). In the first gate driving circuit 120A, the first shift registers LSR(1)-LSR(N) from the first stage to the Nth stage and the dummy shift register DSR are arranged from top to bottom, and each of the first shift registers LSR(1)-LSR(N) from the first stage to the Nth stage and the dummy shift register DSR has a width W1. In the second gate driving circuit 120B, the second shift registers RSR(1)-RSR(N) from the first stage to the Nth stage are arranged from top to bottom, and each of the second shift registers RSR(1)-RSR(N) from the first stage to the Nth stage has a width W2, where the width W2 is less than the width W1. For the reasons and advantages of the width W2 of the second shift register being less than the width W1 of the first shift register, please refer to the relevant descriptions later.

[0040] The first gate driving circuit 120A further includes clock signal lines CL1-CL4, scan control signal lines STVL1, STVL2, pull-down control signal lines GPWL1, GPWL2, forward scan signal line LFWL, and reverse scan signal line LBWL, which are respectively used to provide clock signals C1-C4, scan control signals STV1, STV2, pull-down control signals GPW1, GPW2, forward scan signal FW, and reverse scan signal BW (please refer to Figure 2 the markings on the left, which use signal lines, arrows, and signals to mark the signals generated by each signal line of the first gate driving circuit 120A). The second gate driving circuit 120B further includes a clock signal line ACL, a forward scan signal line RFWL, and a reverse scan signal line RBWL, which are respectively used to provide a clock signal AC, a forward scan signal FW, and a reverse scan signal BW (please refer to Figure 2 the markings on the right, which use signal lines, arrows, and signals to mark the signals generated by each signal line of the second gate driving circuit 120B). In Figure 2 , the number of clock signal lines of the first gate driving circuit 120A is exemplified by 4 (CL1-CL4), but is not limited thereto. In some embodiments, the number of clock signal lines of the first gate driving circuit 120A may be 2, 6, 8, or other suitable numbers.

[0041] Specifically, when N is a multiple of 4, the clock signal line CL1 is coupled to the first stage, the fifth stage, …, the (N - 3)-th stage of the first shift registers LSR(1), LSR(5), …, LSR(N - 3), the clock signal line CL2 is coupled to the second stage, the sixth stage, …, the (N - 2)-th stage of the first shift registers LSR(2), LSR(6), …, LSR(N - 2), the clock signal line CL3 is coupled to the third stage, the seventh stage, …, the (N - 1)-th stage of the first shift registers LSR(3), LSR(7), …, LSR(N - 1), and the clock signal line CL4 is coupled to the fourth stage, the eighth stage, …, the N-th stage of the first shift registers LSR(4), LSR(8), …, LSR(N). The first shift registers LSR(1)-LSR(N) of the first stage to the N-th stage respectively generate and sequentially output the first scan signals LG1-LG N to the odd-numbered scan lines SL1, SL3, …, SL (2N-1) . The scan control signal line STVL1 is coupled to a part of the first shift registers among the first shift registers LSR(1)-LSR(N) of the first stage to the N-th stage, and the scan control signal line STVL2 is coupled to another part of the first shift registers and the dummy shift register DSR among the first shift registers LSR(1)-LSR(N) of the first stage to the N-th stage. The pull-down control signal lines GPWL1, GPWL2, the forward scan signal line LFWL, and the reverse scan signal line LBWL are coupled to each of the first shift registers LSR(1)-LSR(N) of the first stage to the N-th stage. The clock signal line CL1, the scan control signal line STVL2, the pull-down control signal lines GPWL1, GPWL2, the forward scan signal line LFWL, and the reverse scan signal line LBWL are also coupled to the dummy shift register DSR. The clock signal line ACL, the forward scan signal line RFWL, and the reverse scan signal line RBWL are coupled to each of the second shift registers RSR(1)-RSR(N) of the first stage to the N-th stage.

[0042] Figure 3A is an equivalent circuit diagram of the i-th stage first shift register LSR(i) in the first gate driving circuit 120A, where i is a positive integer from 1 to N. As Figure 3A shown, the i-th stage first shift register LSR(i) includes a pre-charge unit 122A, a pull-up unit 124A, a first pull-down unit 126A1, and a second pull-down unit 126A2. The pre-charge unit 122A is coupled to the node LX1, and each of the pull-up unit 124A, the first pull-down unit 126A1, and the second pull-down unit 126A2 is coupled to the node LX1 and the node LX2. The pre-charge unit 122A outputs a pre-charge signal LP(i) to the node LX1( Figure 3AThe label LX1(LP(i)) in it indicates that the node LX1 has its corresponding pre-charge signal LP(i), and the pull-up unit 124A outputs the first scan signal LG of the i-th stage i to the node LX2. The node LX2 is coupled to the corresponding scan line SL of the display panel 110 (i.e., the scan line SL (2i-1) ), so that the first scan signal LG of the i-th stage i is transmitted to the scan line SL (2i-1) .

[0043] The pre-charge unit 122A receives the input signals IN1, IN2, the forward scan signal FW, and the reverse scan signal BW, and generates and outputs the pre-charge signal LP(i) to the node LX1 according to the input signals IN1, IN2, the forward scan signal FW, and the reverse scan signal BW. The pre-charge unit 122A includes transistors LM1 and LM2. The control terminals of the transistors LM1 and LM2 are respectively used to receive the input signals IN1 and IN2. The first ends of the transistors LM1 and LM2 are respectively used for the first voltage signal and the second voltage signal, and the second ends of the transistors LM1 and LM2 are coupled to the node LX1. In this embodiment, the first gate driving circuit 120A can perform bidirectional scanning (i.e., forward scanning and reverse scanning). Therefore, the first voltage signal can be the forward scan signal FW, and the second voltage signal can be the reverse scan signal BW, but it is not limited thereto. In an embodiment where the first gate driving circuit 120A can only perform unidirectional scanning, the first voltage signal can be a high-potential signal, and the second voltage signal can be a low-potential signal. For example, the first end of the transistor LM1 can be coupled to a voltage source to receive a high potential, and the first end of the transistor LM2 can be coupled to a ground wire or a gate low-potential signal line to receive a low potential. The input signal IN1 of the i-th stage first shift register LSR(i) can be the scan control signal STV1 or the first scan signal LG of the (i-a)-th stage (i-a) , where a is a positive integer less than 4; and the input signal IN2 of the i-th stage first shift register LSR(i) can be the first scan signal LG of the (i+b)-th stage (i+b) or the scan control signal STV2, where b is a positive integer less than 4. Specifically, if i is a positive integer less than or equal to a, the input signals IN1 and IN2 of the i-th stage first shift register LSR(i) can be the scan control signal STV1 and the first scan signal LG of the (i+b)-th stage (i+b) respectively; if i is a positive integer from (a + 1) to (N - b), the input signals IN1 and IN2 of the i-th stage first shift register LSR(i) are respectively the first scan signal LG of the (i-a)-th stage (i-a) and the first scan signal LG of the (i+b)-th stage (i+b); if i is a positive integer from (N - b + 1) to N, the input signals IN1 and IN2 of the i-th stage first shift register LSR(i) are respectively the (i - a)-th stage first scan signal LG (i-a) and the scan control signal STV2. In the following description, a and b are both taken as 2 as an example. When i is 1 or 2, the input signals IN1 and IN2 can be respectively the scan control signal STV1 and the (i + 2)-th stage first scan signal LG (i+2) (Therefore Figure 2 in the scan control signal line STVL1 is coupled to not only the first shift register LSR(1) of the first stage but also the first shift register LSR(2) of the second stage); if i is a positive integer from 3 to (N - 2), the input signals IN1 and IN2 are respectively the (i - 2)-th stage first scan signal LG (i-2) and the (i + 2)-th stage first scan signal LG (i+2) ; if i is (N - 1) or N, the input signals IN1 and IN2 are respectively the (i - 2)-th stage first scan signal LG (i-2) and the scan control signal STV2. Therefore, the scan control signal line STVL2 is coupled to the first shift register LSR(N - 1) of the (N - 1)-th stage and the first shift register LSR(N) of the N-th stage. In this article, the "control terminal", "first terminal" and "second terminal" of a transistor respectively refer to the gate, source and drain of the transistor, or respectively refer to the gate, drain and source of the transistor.

[0044] The pull-up unit 124A is coupled to the precharge unit 122A (both the pull-up unit 124A and the precharge unit 122A are coupled to the node LX1). The pull-up unit 124A receives the precharge signal LP(i) and the clock signal CN, and outputs the i-th stage first scan signal LG i to the node LX2, where the clock signal CN is any one of the clock signals C1 - C4. In an embodiment where N is a multiple of 4, if i is 1, 5,..., (N - 3), the clock signal CN is the clock signal C1; if i is 2, 6,..., (N - 2), the clock signal CN is the clock signal C2; if i is 3, 7,..., (N - 1), the clock signal CN is the clock signal C3; if i is 4, 8,..., N, the clock signal CN is the clock signal C4. The pull-up unit 124A includes a transistor LM3 and a capacitor LC. The control terminal of the transistor LM3 is used to receive the precharge signal LP(i), the first terminal of the transistor LM3 receives the clock signal CN, and the second terminal of the transistor LM3 outputs the i-th stage first scan signal LG iOne end of the capacitor LC is coupled to the control terminal of the transistor LM3, and the other end of the capacitor LC is coupled to the second terminal of the transistor LM3. In some embodiments, the pull-up unit 124A may not include the capacitor LC.

[0045] The first pull-down unit 126A1 is coupled to the pre-charge unit 122A and the pull-up unit 124A (the first pull-down unit 126A1 is coupled to the nodes LX1 and LX2), and controls whether to enable the first pull-down unit 126A1 according to the pre-charge signal LP(i) and the pull-down control signals GPW1 and GPW2. During the display period, each of the pull-down control signals GPW1 and GPW2 is a signal that alternates between a high potential and a low potential, and the pull-down control signals GPW1 and GPW2 are inverted with respect to each other, that is, when one of the pull-down control signals GPW1 and GPW2 is at a high potential, the other is at a low potential. The first pull-down unit 126A1 includes transistors LM4-LM8. The control terminal and the first terminal of the transistor LM4 receive the pull-down control signal GPW1. The control terminal of the transistor LM5 receives the pull-down control signal GPW2, the first terminal of the transistor LM5 is coupled to the gate low potential signal VGL, the second terminal of the transistor LM5 is coupled to the second terminal of the transistor LM4, and the second terminal of the transistor LM5 and the second terminal of the transistor LM4 are coupled to the node P. The control terminal of the transistor LM6 is coupled to the node LX1, the first terminal of the transistor LM6 is coupled to the gate low potential signal VGL, and the second terminal of the transistor LM6 is coupled to the second terminal of the transistor LM4. The control terminal of the transistor LM7 is coupled to the second terminal of the transistor LM6, the first terminal of the transistor LM7 is coupled to the gate low potential signal VGL, and the second terminal of the transistor LM7 is coupled to the node LX1. The control terminal of the transistor LM8 is coupled to the second terminal of the transistor LM6, the first terminal of the transistor LM8 is coupled to the gate low potential signal VGL, and the second terminal of the transistor LM8 is coupled to the node LX2. When the i-th stage of the first shift register LSR(i) outputs the i-th stage of the first scan signal LG i to start the corresponding pixel row, that is, the i-th stage of the first scan signal LG i rises to a high potential and remains at the high potential for a period of time and then drops to a low potential, the node LX1 drops from a high potential to a low potential, so the transistor LM6 is turned off, and it is determined whether the first pull-down unit 126A1 is enabled according to the potentials of the pull-down control signals GPW1 and GPW2. Specifically, when the pull-down control signal GPW1 is at a low potential and the pull-down control signal GPW2 is at a high potential, the node P is in a low potential state, so that the transistors LM7 and LM8 are turned off (i.e., the first pull-down unit 126A1 is disabled); when the pull-down control signal GPW1 is at a high potential and the pull-down control signal GPW2 is at a low potential, the node P is in a high potential state, so that the transistors LM7 and LM8 are turned on to set the potentials of the nodes LX1 and LX2 to the gate low potential signal VGL (i.e., the first pull-down unit 126A1 is enabled).

[0046] The second pull-down unit 126A2 is coupled to the pre-charge unit 122A and the pull-up unit 124A (the second pull-down unit 126A2 is coupled to the node LX1 and the node LX2), and controls whether to enable the second pull-down unit 126A2 according to the pre-charge signal LP(i) and the pull-down control signals GPW1 and GPW2. The second pull-down unit 126A2 includes transistors LM9-LM13. The control terminal and the first terminal of the transistor LM9 receive the pull-down control signal GPW2. The control terminal of the transistor LM10 receives the pull-down control signal GPW1, the first terminal of the transistor LM10 is coupled to the gate low potential signal VGL, the second terminal of the transistor LM10 is coupled to the second terminal of the transistor LM9, and the second terminal of the transistor LM9 and the second terminal of the transistor LM10 are coupled to the node Q. The control terminal of the transistor LM11 is coupled to the node LX1, the first terminal of the transistor LM11 is coupled to the gate low potential signal VGL, and the second terminal of the transistor LM11 is coupled to the second terminal of the transistor LM9. The control terminal of the transistor LM12 is coupled to the second terminal of the transistor LM11, the first terminal of the transistor LM12 is coupled to the gate low potential signal VGL, and the second terminal of the transistor LM12 is coupled to the node LX1. The control terminal of the transistor LM13 is coupled to the second terminal of the transistor LM11, the first terminal of the transistor LM13 is coupled to the gate low potential signal VGL, and the second terminal of the transistor LM13 is coupled to the node LX2. When the first shift register LSR(i) of the i-th stage outputs the first scan signal LG of the i-th stage i to start the corresponding pixel row, that is, the first scan signal LG of the i-th stage i rises to a high potential and remains at the high potential for a period of time and then drops to a low potential, the node LX1 drops from the high potential to the low potential. Therefore, the transistor LM11 is turned off, and it is determined whether the second pull-down unit 126A2 is enabled according to the potentials of the pull-down control signals GPW1 and GPW2. Specifically, when the pull-down control signal GPW1 is at a low potential and the pull-down control signal GPW2 is at a high potential, the node Q is in a high potential state, so that the transistors LM12 and LM13 are turned on to set the potentials of the nodes LX1 and LX2 to the gate low potential signal VGL (that is, the second pull-down unit 126A2 is enabled); when the pull-down control signal GPW1 is at a high potential and the pull-down control signal GPW2 is at a low potential, the node Q is in a low potential state, so that the transistors LM12 and LM13 are turned off (that is, the second pull-down unit 126A2 is disabled). In summary, in one frame time, when the first shift register LSR(i) of the i-th stage outputs the first scan signal LG of the i-th stage i to start the corresponding pixel row, that is, the first scan signal LG of the i-th stage iAfter rising to a high potential and maintaining for a period of time and then dropping to a low potential, if a noise signal is coupled to node LX1 and / or node LX2, the conducting transistors LM7 and LM8 of the first pull-down unit 126A1 or the conducting transistors LM12 and LM13 of the second pull-down unit 126A2 pull nodes LX1 and LX2 to the low potential, that is, pull the i-th stage first scan signal LG i down to and maintain at the low potential, without causing the i-th stage first scan signal LG i to be interfered by noise.

[0047] It should be noted that the i-th stage first shift register LSR(i) of this embodiment includes two pull-down units. During the display screen period, the pull-down control signals GPW1 and GPW2 are periodic and their waveforms are inverted with each other, that is, the waveforms of the pull-down control signals GPW1 and GPW2 will have high potential and low potential changes, and when one of the pull-down control signals GPW1 and GPW2 is at a high potential, the other is at a low potential, so that when one of the first pull-down unit 126A1 and the second pull-down unit 126A2 is enabled, the other is disabled, to avoid the transistors in the first pull-down unit 126A1 and the second pull-down unit 126A2 from conducting for a long time and causing the threshold voltage to drift, and making the first pull-down unit 126A1 and the second pull-down unit 126A2 fail.

[0048] Figure 3B is the equivalent circuit diagram of the dummy shift register DSR in the first gate driving circuit 120A. The dummy shift register DSR has the same circuit structure as the Figure 3A i-th stage first shift register LSR(i). In the dummy shift register DSR, the input signals IN1 and IN2 received by the control terminals of the transistors LM1 and LM2 are the (N - 1)-th stage first scan signal LG (N-1) and the scan control signal STV2 respectively, the control terminal of the transistor LM3 receives the precharge signal LP(N + 1), the first terminal of the transistor LM3 receives the clock signal CN, the clock signal CN can be the clock signal C1, and the second terminal of the transistor LM3 outputs the dummy scan signal DG. For the rest, please refer to the Figure 3A description, which will not be elaborated here.

[0049] Figure 3C is the equivalent circuit diagram of the i-th stage second shift register RSR(i) in the second gate driving circuit 120B, where i is a positive integer from 1 to (N - 1). As shown in Figure 3CAs shown, the second shift register RSR(i) of the i-th stage includes a precharge unit 122B, a pull-up unit 124B, and a pull-down unit 126B. The precharge unit 122B is coupled to node RX1, and each of the pull-up unit 124B and the pull-down unit 126B is coupled to node RX1 and node RX2. The precharge unit 122B outputs a precharge signal RP(i) to node RX1 ( Figure 3C The label RX1(RP(i)) in Figure 3C indicates that node RX1 has its corresponding precharge signal RP(i)), and the pull-up unit 124B outputs the second scan signal RG of the i-th stage i to node RX2. Node RX2 is coupled to the corresponding scan line SL of the display panel 110 (i.e., scan line SL (2i) ), such that the second scan signal RG of the i-th stage i is transmitted to scan line SL (2i) .

[0050] The precharge unit 122B receives input signals IN1’, IN2’, a forward scan signal FW, and a reverse scan signal BW, and generates and outputs a precharge signal RP(i) to node RX1 according to the input signals IN1’, IN2’, the forward scan signal FW, and the reverse scan signal BW. The input signal IN1’ is the i-th stage first scan signal LG generated by the i-th stage first shift register LSR(i) of the first gate driving circuit 120A i , and the input signal IN2’ is the (i + 1)-th stage first scan signal LG generated by the (i + 1)-th stage first shift register LSR(i + 1) of the first gate driving circuit 120A i+1 . The first end of the transistor RM1 is used to receive a first voltage signal, the second end of the transistor RM1 is coupled to node RX1, and the control end of the transistor RM1 is used to receive the input signal IN1’. The first end of the transistor RM2 is used to receive a second voltage signal, the second end of the transistor RM2 is coupled to node RX1, and the control end of the transistor RM2 is used to receive the input signal IN2’. In this embodiment, the second gate driving circuit 120B can perform bidirectional scanning (i.e., forward scanning and reverse scanning), so the first voltage signal can be the forward scan signal FW, and the second voltage signal can be the reverse scan signal BW, but it is not limited thereto. In an embodiment where the second gate driving circuit 120B can only perform unidirectional scanning, the first voltage signal can be a high potential signal, and the second voltage signal can be a low potential signal. For example, the first end of the transistor RM1 can be coupled to a voltage source to receive a high potential, and the first end of the transistor RM2 can be coupled to a ground wire or a gate low potential signal line to receive a low potential.

[0051] The pull-up unit 124B is coupled to the pre-charge unit 122B (both the pull-up unit 124B and the pre-charge unit 122B are coupled to the node RX1), receives the pre-charge signal RP(i) and the clock signal AC, and the pull-up unit 124B outputs the i-th stage second scan signal RG according to the pre-charge signal RP(i) and the clock signal AC. i To the node RX2. The pull-up unit 124A includes a transistor RM3 and a capacitor RC. The first end of the transistor RM3 is used to receive the clock signal AC, the second end of the transistor RM3 is coupled to the node RX2 and is used to output the i-th stage second scan signal RG. i And the control end of the transistor RM3 is coupled to the node RX1 and receives the pre-charge signal RP(i). The first end and the second end of the capacitor RC are respectively coupled to the control end and the second end of the transistor RM3. In some embodiments, the pull-up unit 124B may not include the capacitor RC.

[0052] The pull-down unit 126B is coupled to the pre-charge unit 122B and the pull-up unit 124B (the pull-down unit 126B is coupled to the node RX1 and the node RX2), receives the pre-charge signal RP(i) and the voltage signal DC, and controls whether to enable the pull-down unit 126B according to the pre-charge signal RP(i). The pull-down unit 126B includes transistors RM4-RM7. The first end of the transistor RM4 is used to receive the gate low potential signal VGL (which can also be called the first reference potential), and the control end of the transistor RM4 is coupled to the node RX1. The first end of the transistor RM5 is used to receive the gate low potential signal VGL, the second end of the transistor RM5 is coupled to the node RX1, and the control end of the transistor RM5 is coupled to the second end of the transistor RM4. The first end of the transistor RM6 is used to receive the gate low potential signal VGL, the second end of the transistor RM6 is coupled to the node RX2, and the control end of the transistor RM6 is coupled to the second end of the transistor RM4. The first end and the control end of the transistor RM7 are used to receive the voltage signal DC (which can also be called the second reference potential), the potential of the voltage signal DC is greater than the gate low potential signal VGL, and the second end of the transistor RM7 is coupled to the second end of the transistor RM4. When the i-th stage second shift register RSR(i) outputs the i-th stage second scan signal RG i To start the corresponding pixel row, that is, after the i-th stage second scan signal RG i Rises to a high potential and remains at a high potential for a period of time and then drops to a low potential, the node RX1 drops from a high potential to a low potential, and the pull-down unit 126B is enabled, that is, the transistor RM4 is turned off, and the transistors RM5 and RM6 are turned on, so that the noise generated at the nodes RX1 and RX2 can be dissipated to the gate low potential signal VGL through the transistors RM5 and RM6 respectively.

[0053] Figure 3DIt is an equivalent circuit diagram of the Nth - stage second shift register RSR(N) in the second gate driving circuit 120B. The Nth - stage second shift register RSR(N) has the same circuit structure as any one of the second shift registers RSR(1)-RSR(N - 1) of the 1st to (N - 1)th stages. In the Nth - stage second shift register RSR(N), the input signal IN1’ is the Nth - stage first scan signal LG generated by the Nth - stage first shift register LSR(N) of the first gate driving circuit 120A N , and the input signal IN2’ is the dummy scan signal DG output by the dummy shift register DSR of the first gate driving circuit 120A. Figure 3D For the remaining part, please refer to Figure 3B for the description, which will not be elaborated here. Figure 3D IN2’(DG / STV3) in

[0054] means that the input signal IN2’ can be the dummy scan signal DG output by the dummy shift register DSR of the first gate driving circuit 120A or the scan control signal STV3 of the second embodiment described later. For relevant descriptions, please refer to the second embodiment. Each of the ith - stage first shift register LSR(i) and the dummy shift register DSR has 13 transistors (transistors LM1 - LM13), while the ith - stage second shift register RSR(i) has 7 transistors (transistors RM1 - RM7). That is to say, the number of transistors of each of the first shift registers LSR(1)-LSR(N) and the dummy shift register DSR from the 1st to the Nth stages is greater than the number of transistors of each of the second shift registers RSR(1)-RSR(N) from the 1st to the Nth stages. Therefore, as described before, Figure 2 the width W2 of the second shift register in Figure 2 can be smaller than the width W1 of the first shift register. In addition, as Figure 2 shown, the number of signal lines of the second gate driving circuit 120B (a total of three signal lines: the clock signal line ACL, the forward scan signal line RFWL, and the reverse scan signal line RBWL) is less than the number of signal lines of the first gate driving circuit 120A (a total of ten signal lines: the clock signal lines CL1 - CL4, the scan control signal lines STVL1, STVL2, the pull - down control signal lines GPWL1, GPWL2, the forward scan signal line LFWL, and the reverse scan signal line LBWL). Therefore, the layout width of the second gate driving circuit 120B can be smaller than the layout width of the first gate driving circuit 120A. In this embodiment, the ith - stage first shift register LSR(i) is coupled to the corresponding scan line SL (2i-1) , and the width W1 of the ith - stage first shift register LSR(i) can be the extension direction of the ith - stage first shift register LSR(i) on the scan line SL (2i-1) (for example Figure 2The width in the horizontal direction (in [reference]), the second shift register RSR(i) of the i-th stage is coupled to the corresponding scan line SL (2i) , the width W2 of the second shift register RSR(i) of the i-th stage can be the width of the second shift register RSR(i) of the i-th stage in the extending direction of the scan line SL (2i) (for example Figure 2 the horizontal direction in [reference]). Similarly, the layout width of the first gate driving circuit 120A and the layout width of the second gate driving circuit 120B can be the layout width of the first gate driving circuit 120A in the extending direction of any scan line SL (for example Figure 2 the horizontal direction in [reference]) and the layout width of the second gate driving circuit 120B in the extending direction of any scan line SL (for example Figure 2 the horizontal direction in [reference]).

[0055] In Figure 3A and Figure 3B transistors LM1-LM13, RM1-RM7 can be amorphous silicon thin film transistors, low temperature polysilicon (LTPS) thin film transistors, Indium Gallium Zinc Oxide (IGZO) thin film transistors or other suitable thin film transistors. In some embodiments, transistors LM1-LM13, RM1-RM7 are all n-type thin film transistors.

[0056] In the embodiment of forward scanning, the forward scanning signal FW and the reverse scanning signal BW in the first gate driving circuit 120A and the second gate driving circuit 120B are high potential and low potential respectively, so that the scan signals transmitted to the scan lines SL1-SL 2N are sequentially switched from low potential to high potential and sequentially switched from high potential to low potential (reference the waveforms of the first scan signals LG1-LG Figure 5 , Figure 8 and Figure 10 from the first stage to the N-th stage and the second scan signals RG1-RG N from the first stage to the N-th stage in [reference]). In the embodiment of reverse scanning, the forward scanning signal FW and the reverse scanning signal BW in the first gate driving circuit 120A and the second gate driving circuit 120B are low potential and high potential respectively, so that the scan signals transmitted to the scan lines SL N - SL1 are sequentially switched from low potential to high potential and sequentially switched from high potential to low potential. 2N - SL1 are sequentially switched from low potential to high potential and sequentially switched from high potential to low potential.

[0057] In addition, in an embodiment where the first gate driving circuit 120A and the second gate driving circuit 120B are unidirectional scanning circuits, the first gate driving circuit 120A may not include a forward scanning signal line LFWL and a reverse scanning signal line LBWL, and the second gate driving circuit 120B may not include a forward scanning signal line RFWL and a reverse scanning signal line RBWL. Specifically, in an embodiment where the first gate driving circuit 120A and the second gate driving circuit 120B are unidirectional scanning circuits, the first ends of the transistors LM1 of the first gate driving circuit 120A and the transistors RM1 of the second gate driving circuit 120B may be coupled to a voltage source to receive a high potential, and the first ends of the transistors LM2 of the first gate driving circuit 120A and the transistors RM2 of the second gate driving circuit 120B may be coupled to a ground wire or a gate low potential signal line to receive a low potential, so that the scanning signals transmitted to the scanning lines SL1 - SL 2N are sequentially switched from a low potential to a high potential.

[0058] Figure 4 FIG. is a schematic circuit diagram of the active region 110A, the first gate driving circuit 120A, and the second gate driving circuit 120B according to the second embodiment of the present invention. Figure 4 Differing from Figure 2 is that in Figure 4 , the first gate driving circuit 120A does not include a dummy shift register DSR, and the second gate driving circuit 120B further includes a scan control signal line STVL3, which is coupled to the Nth - stage second shift register RSR(N) to provide a scan control signal STV3 to the Nth - stage second shift register RSR(N) as an input signal IN2' of the Nth - stage second shift register RSR(N). The rest is the same as that shown in Figure 2 and will not be repeated here.

[0059] Figure 5 FIG. is a signal timing diagram of the first gate driving circuit 120A and the second gate driving circuit 120B corresponding to the first and second embodiments of the present invention within one frame period. Figures 6A to 6D Illustrates the signal flow directions of the respective transistors in the second shift register at different time points. For ease of explanation, Figure 5 only shows the timing changes of some signals in the first gate driving circuit 120A and the second gate driving circuit 120B.

[0060] As shown in Figure 5As shown, the cycle time length of each of the clock signals C1 - C4 is 8 unit times H (i.e., 8H). The high - potential duration and the low - potential duration of each of the clock signals C1 - C4 are 1 unit time (i.e., H) and 7 unit times (i.e., 7H) respectively, and the clock signals C1 - C4 generate periodic waveforms in the order of C1, C2, C3, C4. Among them, the clock signal C2 lags behind the clock signal C1 by 1 / 4 of the cycle time length (i.e., 2H), the clock signal C3 lags behind the clock signal C2 by 1 / 4 of the cycle time length (i.e., 2H), and the clock signal C4 lags behind the clock signal C3 by 1 / 4 of the cycle time length (i.e., 2H). For example, during the time points T1 to T9, the clock signals C1 - C4 sequentially rise from low potential to high potential at time points T1, T3, T5, T7, and sequentially fall from high potential to low potential at time points T2, T4, T6, T8. The cycle time length of the clock signal AC is 2 unit times H (i.e., 2H), and the high - potential duration and the low - potential duration of the clock signal AC are both 1 unit time (i.e., H). In this embodiment, when the clock signal AC is at high potential, the clock signals C1 - C4 are at low potential; and when any one of the clock signals C1 - C4 is at high potential, the clock signal AC is at low potential. For example, during the time points T1 to T9, the high - potential duration of the clock signal AC is between time point T2 and time point T3, between time point T4 and time point T5, between time point T6 and time point T7, and between time point T8 and time point T9. It should be noted that the present invention does not limit the time length of the unit time H. The following paragraphs will be described in conjunction with the equivalent circuit diagrams of the first - stage first shift register LSR(i) ( Figure 3A ), the equivalent circuit diagram of the dummy shift register DSR ( Figure 3B ), the equivalent circuit diagrams of the second - stage to the (N - 1) - stage second shift registers RSR(1) - RSR(N - 1) ( Figure 3C ) and the equivalent circuit diagram of the N - stage second shift register RSR(N) ( Figure 3D ). Figure 5 The signal timing diagrams will be described. In addition, the following is an embodiment in which the forward scan signal FW and the reverse scan signal BW in the first gate driving circuit 120A and the second gate driving circuit 120B are at high potential and low potential respectively to illustrate Figure 5 .

[0061] Please refer to Figure 3A and Figure 5。At time point T0, the scan control signal STV1 rises from a low potential to a high potential. As a result, the transistors LM1 in the first shift register LSR(1) of the first stage and the first shift register LSR(2) of the second stage are turned on, and the precharge signals LP(1) in the first shift register LSR(1) of the first stage and LP(2) in the first shift register LSR(2) of the second stage rise from a low potential to a high potential V1 ( Figure 5 only the precharge signal LP(1) is shown and the precharge signal LP(2) is omitted), causing the transistors LM3 in the first shift register LSR(1) of the first stage and the transistors LM3 in the first shift register LSR(2) of the second stage to be turned on.

[0062] Please refer to Figure 3A 、 Figure 3C 、 Figure 5 and Figure 6A 。At time point T1, the scan control signal STV1 drops from a high potential to a low potential, while the clock signal C1 rises from a low potential to a high potential. As a result, the first scan signal LG1 of the first stage output by the first shift register LSR(1) of the first stage rises from a low potential to a high potential, and the precharge signal LP(1) in the first shift register LSR(1) of the first stage rises again from the high potential V1 to a high potential V2 due to the coupling of the capacitor LC, where the high potential V2 is greater than the high potential V1. In addition, the input signal IN1 of the first shift register LSR(3) of the third stage and the input signal IN1' of the second shift register RSR(1) of the first stage are both the first scan signal LG1 with a high potential. Therefore, the transistor LM1 in the first shift register LSR(3) of the third stage is turned on, causing the precharge signal LP(3) to rise from a low potential to a high potential V1 ( Figure 5 the precharge signal LP(3) is omitted from the illustration), and the transistor RM1 in the second shift register RSR(1) of the first stage is turned on, causing the precharge signal RP(1) to rise from a low potential to a high potential V3 (as shown in Figure 5 and Figure 6A , where Figure 6A i in

[0063] Please refer to Figure 3A 、 Figure 3C 、 Figure 5 and Figure 6B. At time point T2, the clock signal AC rises from a low potential to a high potential, while the clock signal C1 falls from a high potential to a low potential. Therefore, the first scan signal LG1 output by the first shift register LSR(1) of the first stage falls from a high potential to a low potential, and the precharge signal LP(1) in the first shift register LSR(1) of the first stage falls from the high potential V2 to the high potential V1. The second scan signal RG1 output by the second shift register RSR(1) of the first stage rises from a low potential to a high potential (as shown in Figure 5 and Figure 6B wherein Figure 6B i in is equal to 1), and the precharge signal RP(1) in the second shift register RSR(1) of the first stage rises from the high potential V3 to the high potential V4 due to the coupling of the capacitor RC, where the high potential V4 is greater than the high potential V3.

[0064] Please refer to Figure 3A , Figure 3C , Figure 5 , Figure 6A and Figure 6C . At time point T3, the clock signal AC falls from a high potential to a low potential, while the clock signal C2 rises from a low potential to a high potential. Therefore, the second scan signal RG1 output by the second shift register RSR(1) of the first stage falls from a high potential to a low potential, the second scan signal LG2 output by the first shift register LSR(2) of the second stage rises from a low potential to a high potential, and the precharge signal LP(2) in the first shift register LSR(1) of the second stage rises from the high potential V1 to the high potential V2 due to the coupling of the capacitor LC. The input signal IN2’ of the second shift register RSR(1) of the first stage is the second scan signal LG2 of the second stage. Therefore, the transistor RM2 in the second shift register RSR(1) of the first stage conducts, causing the precharge signal RP(1) to fall from the high potential V4 to a low potential (as shown in Figure 5 and Figure 6C wherein Figure 6C i in is equal to 1), the transistor RM4 is turned off, and the transistors RM5 and RM6 are turned on. In addition, the input signal IN1 of the first shift register LSR(4) of the fourth stage and the input signal IN1’ of the second shift register RSR(2) of the second stage are both the second scan signal LG2 of the second stage. Therefore, the transistor LM1 in the first shift register LSR(4) of the fourth stage conducts, causing the precharge signal LP(4) to rise from a low potential to the high potential V1 ( Figure 5 the precharge signal LP(4) is omitted from the illustration), and the transistor RM1 in the second shift register RSR(2) of the second stage conducts, causing the precharge signal RP(2) to rise from a low potential to the high potential V3 (as shown in Figure 6A wherein Figure 6A i in is equal to 2; Figure 5The waveform of the precharge signal RP(2) is omitted, so the transistor LM3 in the fourth-stage first shift register LSR(4) and the transistor RM3 in the second-stage second shift register RSR(2) are turned on.

[0065] Please refer to Figure 3A , Figure 3C , Figure 5 , Figure 6B and Figure 6D . At time point T4, the clock signal AC rises from a low level to a high level, while the clock signal C2 falls from a high level to a low level. Therefore, the second-stage first scan signal LG2 output by the second-stage first shift register LSR(2) falls from a high level to a low level, the precharge signal LP(2) in the second-stage first shift register LSR(2) falls from a high level V2 to a high level V1, and the second-stage second scan signal RG2 output by the second-stage second shift register RSR(2) rises from a low level to a high level (as shown in Figure 6B , where Figure 6B i is equal to 2), and the precharge signal RP(2) in the second-stage second shift register RSR(2) rises from a high level V3 to a high level V4 again due to the coupling of the capacitor RC ( Figure 5 not shown). In addition, as shown in Figure 6D (where Figure 6D i is equal to 1), in the first-stage second shift register RSR(1), when the clock signal AC rises to a high level, it may cause noise to be generated at the control terminal (i.e., node RX1) and the second terminal (i.e., node RX2) of the transistor RM3 due to the parasitic capacitance of the transistor RM3. Since the transistor RM4 is turned off and the transistors RM5 and RM6 are both turned on, the noise generated at the nodes RX1 and RX2 can be dissipated to the gate low-potential signal VGL via the transistors RM5 and RM6 respectively.

[0066] Please refer to Figure 3A , Figure 3C , Figure 5 , Figure 6A and Figure 6C . At time point T5, the clock signal AC falls from a high level to a low level, while the clock signal C3 rises from a low level to a high level. Therefore, the second-stage second scan signal RG2 output by the second-stage second shift register RSR(2) falls from a high level to a low level, the third-stage first scan signal LG3 output by the third-stage first shift register LSR(3) rises from a low level to a high level, and the precharge signal LP(3) in the third-stage first shift register LSR(3) rises from a high level V1 to a high level V2 again due to the coupling of the capacitor LC ( Figure 5(not shown). The input signal IN2 of the first shift register LSR(1) at the first stage and the input signal IN2’ of the second shift register RSR(2) at the second stage are both the first scan signal LG3 at the third stage. Therefore, the transistor LM2 in the first shift register LSR(1) at the first stage conducts, causing the precharge signal LP(1) to drop from the high potential V1 to the low potential, while the transistor RM2 in the second shift register RSR(2) at the second stage conducts, causing the precharge signal RP(2) to drop from the high potential V4 to the low potential (as Figure 6C , where Figure 6C i in Figure 5 is equal to 2), the transistor RM4 turns off, and the transistors RM5 and RM6 conduct. In addition, the input signal IN1 of the first shift register LSR(5) at the fifth stage and the input signal IN1’ of the second shift register RSR(3) at the third stage are both the first scan signal LG3 at the third stage. Therefore, the transistor LM1 in the first shift register LSR(5) at the fifth stage conducts, causing the precharge signal LP(5) to rise from the low potential to the high potential V1 ( Figure 6A , where Figure 6A i in

[0067] Please refer to Figure 3B , Figure 3D , Figure 5 and Figure 6D . At the time point T (2N+1) , the clock signal AC drops from the high potential to the low potential, while the clock signal C1 rises from the low potential to the high potential. Therefore, the second scan signal RG N output by the second shift register RSR(N) at the Nth stage drops from the high potential to the low potential, the dummy scan signal DG output by the dummy shift register DSR rises from the low potential to the high potential, and the precharge signal LP(N + 1) in the dummy shift register DSR rises from the high potential V1 to the high potential V2 again due to the coupling of the capacitor LC ( Figure 5 not shown). The input signal IN2’ of the second shift register RSR(N) at the Nth stage is the dummy scan signal DG. Therefore, the transistor RM2 in the second shift register RSR(N) at the Nth stage conducts, causing the precharge signal RP(N) to drop from the high potential V4 to the low potential ( Figure 5 not shown), the transistor RM4 turns off, and the transistors RM5 and RM6 conduct.

[0068] Please refer to Figure 3B and Figure 5 . At the time point T(2N+2) , the clock signal C1 drops from a high potential to a low potential, while the scan control signal STV2 rises from a low potential to a high potential. Therefore, the dummy scan signal DG output by the dummy shift register DSR drops from a high potential to a low potential, and the transistor LM2 in the dummy shift register DSR conducts, causing the pre-charge signal LP(N+1) to drop from the high potential V2 to a low potential ( Figure 5 not shown), to end the display driving of all pixels PX in the active region 110A by the first gate driving circuit 120A and the second gate driving circuit 120B during the frame period.

[0069] At time point T6-T 2N The signal timing description can be deduced from the aforementioned signal timing description at time point T6-T 2N and thus will not be described further.

[0070] From Figure 5 the description, it can be seen that within the same frame period, the i-th stage first scan signal LG i and the i-th stage second scan signal RG i are at a high potential respectively in the time interval from time point T (2i-1) to time point T 2i and in the time interval from time point T 2i to time point T (2i+1) , and the dummy scan signal DG is at a high potential in the time interval from time point T (2N+1) to time point T (2N+2) . That is to say, the 1st stage first scan signal LG1 rises to a high potential at time point T1 and maintains for 1 unit time H, then the 1st stage second scan signal RG1 rises to a high potential at time point T2 and maintains for 1 unit time H, then the 2nd stage first scan signal LG2 rises to a high potential at time point T3 and maintains for 1 unit time H, then the 2nd stage second scan signal RG2 rises to a high potential at time point T4 and maintains for 1 unit time H,..., then the N-th stage second scan signal RG N rises to a high potential at time point T 2N and maintains for 1 unit time H, and then the dummy scan signal DG rises to a high potential at time point T (2N+1) and maintains for 1 unit time H. When the i-th stage first scan signal LG i switches from a high potential to a low potential, the i-th stage second scan signal RG i switches from a low potential to a high potential, and when the (i+1)-th stage first scan signal LG (i+1) switches from a low potential to a high potential, the i-th stage second scan signal RG i switches from a high potential to a low potential; when the dummy scan signal DG switches from a low potential to a high potential, the N-th stage second scan signal RG NSwitch from a high potential to a low potential, so that multiple scan lines SL can be sequentially enabled (i.e., scan lines SL1, SL2, SL3, SL4, …, SL (2N-1) 、SL 2N are sequentially enabled).

[0071] Figure 7 FIG. is a schematic circuit diagram of the active region 110A, the first gate driving circuit 120A, and the second gate driving circuit 120B according to the third embodiment of the present invention. Figure 7 Differing from Figure 2 is that, in Figure 7 , the second gate driving circuit 120B includes two clock signal lines ACL1 and ACL2, wherein the clock signal line ACL1 is coupled to odd-stage second shift registers (i.e., the first-stage second shift register RSR(1), the third-stage second shift register RSR(3), …, and the (N - 1)-th stage second shift register RSR(N - 1)) to provide a clock signal AC1 to the odd-stage second shift registers, and the clock signal line ACL2 is coupled to even-stage second shift registers (i.e., the second-stage second shift register RSR(2), the fourth-stage second shift register RSR(4), …, and the N-th stage second shift register RSR(N)) to provide a clock signal AC2 to the even-stage second shift registers. Specifically, the clock signal line ACL1 is coupled to the first end of the transistor RM3 in each odd-stage second shift register, and the clock signal line ACL2 is coupled to the first end of the transistor RM3 in each even-stage second shift register. The rest is the same as that shown in Figure 2 , so it will not be repeated here. Figure 7 The equivalent circuit diagrams of the first-stage to N-th stage second shift registers RSR(1)-RSR(N) of the second gate driving circuit 120B in Figure 3C and Figure 3D can be similar to those in

[0072] Figure 8 is a signal timing diagram of the first gate driving circuit 120A and the second gate driving circuit 120B corresponding to the third embodiment during a frame period. For ease of explanation,[[]] Figure 8 only shows the timing changes of some signals in the first gate driving circuit 120A and the second gate driving circuit 120B. Figure 8 Differing from Figure 5 in the shown signal timing diagram is that, in Figure 8Among them, the cycle time lengths of the clock signals AC1 and AC2 are both 4 unit times H (i.e., 4H). For each of the clock signals AC1 and AC2, the high-potential duration and the low-potential duration are respectively 1 / 4 and 3 / 4 of the cycle time length (i.e., H and 3H respectively), and the clock signal AC2 lags behind the clock signal AC1 by 1 / 2 of the cycle time length (i.e., 2H). Therefore, the high-potential period of the clock signal AC1 does not overlap with the high-potential period of the clock signal AC2. In this embodiment, when any one of the clock signals AC1 and AC2 is at a high potential, the clock signals C1 - C4 are at a low potential; and when any one of the clock signals C1 - C4 is at a high potential, the clock signals AC1 and AC2 are at a low potential. The clock signal AC1 rises to a high potential at time points T2, T6,..., T (2N-2) such that the odd-level second shift registers (i.e., the 1st-level second shift register RSR(1), the 3rd-level second shift register RSR(3),..., and the (N - 1)th-level second shift register RSR(N - 1)) output odd-level second scan signals (i.e., the 1st-level second scan signal RG1, the 3rd-level second scan signal RG3,..., and the (N - 1)th-level second scan signal RG (N-1) ) rise from a low potential to a high potential at time points T2, T6,..., T (2N-2) respectively. The clock signal AC2 rises to a high potential at time points T4, T8,..., T 2N such that the even-level second shift registers (i.e., the 2nd-level second shift register RSR(2), the 4th-level second shift register RSR(4),..., and the Nth-level second shift register RSR(N)) output even-level second scan signals (i.e., the 2nd-level second scan signal RG2, the 4th-level second scan signal RG4,..., and the Nth-level second scan signal RG N ) rise from a low potential to a high potential at time points T4, T8,..., T 2N respectively. The timing diagrams of the remaining signals are the same as those of the same signals in Figure 5 , so they will not be elaborated here. In addition, in this embodiment, since the second gate driving circuit 120B receives two mutually interleaved clock signals AC1 and AC2, and the low-potential duration of each of the clock signals AC1 and AC2 is 3 / 4 of the cycle time length, compared with the first embodiment that receives one clock signal AC, and the low-potential duration of the clock signal AC is 1 / 2 of the cycle time length, the input signal IN1' of the ith-level second shift register RSR(i) can be the ith-level first scan signal LG i , and the input signal IN2' of the ith-level second shift register RSR(i) can be the (i + 1)th-level first scan signal LG (i+1)Alternatively, for the dummy scan signal DG, the input signal IN1' of the i-th stage second shift register RSR(i) in this embodiment can be the i-th stage first scan signal LG i or the (i - 1)-th stage first scan signal LG (i-1) , and the input signal IN2' of the i-th stage second shift register RSR(i) can be the (i + 1)-th stage first scan signal LG (i+1) , the (i + 2)-th stage first scan signal LG (i+2) or the dummy scan signal DG.

[0073] Figure 9 FIG. is a schematic circuit diagram of the active region 110A, the first gate driving circuit 120A, and the second gate driving circuit 120B according to the fourth embodiment of the present invention. Figure 9 Differing from Figure 2 , in Figure 9 , the second gate driving circuit 120B includes four clock signal lines ACL1 - ACL4. Among them, the clock signal line ACL1 is coupled to the (4K - 3)-th stage second shift register, where K is a positive integer greater than or equal to 1 (i.e., the 1st stage second shift register RSR(1), the 5th stage second shift register RSR(5),..., and the (N - 3)-th stage second shift register RSR(N - 3)) to provide the clock signal AC1 to the (4K - 3)-th stage second shift register; the clock signal line ACL2 is coupled to the (4K - 2)-th stage second shift register (i.e., the 2nd stage second shift register RSR(2), the 6th stage second shift register RSR(6),..., and the (N - 2)-th stage second shift register RSR(N - 2)) to provide the clock signal AC2 to the (4K - 2)-th stage second shift register; the clock signal line ACL3 is coupled to the (4K - 1)-th stage second shift register (i.e., the 3rd stage second shift register RSR(3), the 7th stage second shift register RSR(7),..., and the (N - 1)-th stage second shift register RSR(N - 1)) to provide the clock signal AC3 to the (4K - 1)-th stage second shift register; the clock signal line ACL4 is coupled to the (4K)-th stage second shift register (i.e., the 4th stage second shift register RSR(4), the 8th stage second shift register RSR(8),..., and the N-th stage second shift register RSR(N)) to provide the clock signal AC4 to the (4K)-th stage second shift register. Specifically, the clock signal line ACL1 is coupled to the first end of the transistor RM3 in the (4K - 3)-th stage second shift register, the clock signal line ACL2 is coupled to the first end of the transistor RM3 in the (4K - 2)-th stage second shift register, the clock signal line ACL3 is coupled to the first end of the transistor RM3 in the (4K - 1)-th stage second shift register, and the clock signal line ACL4 is coupled to the first end of the transistor RM3 in the (4K)-th stage second shift register. The rest is the same asFigure 2 The content shown is the same, so it will not be repeated here. Figure 9 The equivalent circuit diagrams of the first to the Nth second shift registers RSR(1)-RSR(N) of the second gate driving circuit 120B in Figure 3C and Figure 3D can be similar to

[0074] Figure 10 FIG. is a signal timing diagram of the first gate driving circuit 120A and the second gate driving circuit 120B corresponding to the fourth embodiment within one frame period. For the convenience of explanation, Figure 10 only the timing changes of some signals in the first gate driving circuit 120A and the second gate driving circuit 120B are shown. Figure 10 Compared with Figure 5 the signal timing diagram shown, the difference is that in Figure 10 , the cycle time lengths of the clock signals AC1-AC4 are all 8 unit times H (i.e., 8H), and the high-potential duration and the low-potential duration of each of the clock signals AC1-AC4 are 1 / 8 and 7 / 8 of the cycle time length respectively (i.e., H and 7H respectively). The clock signals AC1 and AC2 are 1 / 4 of a clock cycle apart, and the clock signal AC2 lags behind the clock signal AC1 by 1 / 4 of a cycle time length (i.e., 2H); the clock signals AC2 and AC3 are 1 / 4 of a clock cycle apart, and the clock signal AC3 lags behind the clock signal AC2 by 1 / 4 of a cycle time length (i.e., 2H); the clock signals AC3 and AC4 are 1 / 4 of a clock cycle apart, and the clock signal AC4 lags behind the clock signal AC3 by 1 / 4 of a cycle time length (i.e., 2H). Therefore, the high-potential periods of the clock signals AC1, AC2, AC3, and AC4 do not overlap with each other. In this embodiment, when any one of the clock signals AC1, AC2, AC3, and AC4 is at a high potential, the clock signals C1-C4 are at a low potential; and when any one of the clock signals C1-C4 is at a high potential, the clock signals AC1, AC2, AC3, and AC4 are at a low potential. The clock signal AC1 is at time points T2, T 10 , …, T (2N-6)Rise to a high potential, such that the (4K - 3)-th stage second shift register (i.e., the 1st stage second shift register RSR(1), the 5th stage second shift register RSR(5), …, and the (N - 3)-th stage second shift register RSR(N - 3)) outputs the (4K - 3)-th stage second scan signal (i.e., the 1st stage second scan signal RG1, the 5th stage second scan signal RG5, …, and the (N - 3)-th stage second scan signal RG (N-3) ) respectively rise from a low potential to a high potential at time points T2, T 10 , …, T (2N-6) . The clock signal AC2 rises to a high potential at time points T4, T 12 , …, T 2N-4 such that the (4K - 2)-th stage second shift register (i.e., the 2nd stage second shift register RSR(2), the 6th stage second shift register RSR(6), …, and the (N - 2)-th stage second shift register RSR(N - 2)) outputs the (4K - 2)-th stage second scan signal (i.e., the 2nd stage second scan signal RG2, the 6th stage second scan signal RG6, …, and the (N - 2)-th stage second scan signal RG N-2 ) respectively rise from a low potential to a high potential at time points T4, T 12 , …, T 2N-4 . The clock signal AC3 rises to a high potential at time points T6, T 14 , …, T 2N-2 such that the (4K - 1)-th stage second shift register (i.e., the 3rd stage second shift register RSR(3), the 7th stage second shift register RSR(7), …, and the (N - 1)-th stage second shift register RSR(N - 1)) outputs the (4K - 1)-th stage second scan signal (i.e., the 3rd stage second scan signal RG3, the 7th stage second scan signal RG7, …, and the (N - 1)-th stage second scan signal RG N-1 ) respectively rise from a low potential to a high potential at time points T6, T 14 , …, T 2N-2 . The clock signal AC4 rises to a high potential at time points T8, T 16 , …, T 2N such that the (4K)-th stage second shift register (i.e., the 4th stage second shift register RSR(4), the 8th stage second shift register RSR(8), …, and the N-th stage second shift register RSR(N)) outputs the (4K)-th stage second scan signal (i.e., the 4th stage second scan signal RG4, the 8th stage second scan signal RG8, …, and the N-th stage second scan signal RG N ) respectively rise from a low potential to a high potential at time points T8, T 16 , …, T 2N . The timing diagrams of the remaining signals are the same as Figure 5The timing diagrams of the same signals are the same, so they will not be elaborated here. In addition, in this embodiment, since the second gate driving circuit 120B receives four mutually interleaved clock signals AC1, AC2, AC3, and AC4, and the low-potential duration of each clock signal AC1, AC2, AC3, and AC4 is 7 / 8 of the cycle time length. Compared with the first embodiment where one clock signal AC is received and the low-potential duration of the clock signal AC is 1 / 2 of the cycle time length, the input signal IN1' of the i-th stage second shift register RSR(i) can be the i-th stage first scan signal LG i and the input signal IN2' of the i-th stage second shift register RSR(i) can be the (i + 1)-th stage first scan signal LG (i+1) or the dummy scan signal DG. The input signal IN1' of the i-th stage second shift register RSR(i) in this embodiment can be the i-th stage first scan signal LG i , the (i - 1)-th stage first scan signal LG (i-1) , the (i - 2)-th stage first scan signal LG (i-2) or the (i - 3)-th stage first scan signal LG (i-3) , and the input signal IN2' of the i-th stage second shift register RSR(i) can be the (i + 1)-th stage first scan signal LG (i+1) , the (i + 2)-th stage first scan signal LG (i+2) , the (i + 3)-th stage first scan signal LG (i+3) , the (i + 4)-th stage first scan signal LG (i+4) or the dummy scan signal DG.

[0075] It should be noted that the third embodiment and the fourth embodiment take the dummy scan signal DG output by the dummy shift register DSR as the input signal IN2' of the N-th stage second shift register RSR(N) as an example, but it is not limited thereto. In the modified embodiments of the third embodiment and the fourth embodiment, the first gate driving circuit 120A does not include the dummy shift register DSR, and the second gate driving circuit 120B further includes a scan control signal line (such as the scan control signal line STVL3 in the second embodiment), which is coupled to the N-th stage second shift register RSR(N) to provide a scan control signal (such as the scan control signal STV3 in the second embodiment) to the N-th stage second shift register RSR(N) as the input signal IN2' of the N-th stage second shift register RSR(N). The rest is the same as that shown in Figure 7 and Figure 9 , so it will not be repeated here.

[0076] Figure 11A is a schematic diagram of the configuration of the active area 110A and the peripheral area 110B in the display panel 110. In Figure 11AIn [description], the peripheral region 110B includes sub-peripheral regions 110B1 and 110B2 respectively located outside opposite sides of the active region 110A, and the first gate driving circuit 120A and the second gate driving circuit 120B are respectively disposed in the sub-peripheral regions 110B1 and 110B2. The sub-peripheral regions 110B1 and 110B2 respectively have a boundary width W LB 、W RB , and the boundary width W LB is substantially equal to the boundary width W RB . In addition, the first gate driving circuit 120A and the second gate driving circuit 120B respectively have a layout width W LG 、W RG . As shown in Figure 2 、 Figure 4 、 Figure 7 and Figure 9 , since the number of signal lines in the first gate driving circuit 120A is greater than the number of signal lines in the second gate driving circuit 120B, and the width W1 of each of the first shift registers LSR(1)-LSR(N) from the first stage to the Nth stage is greater than the width W2 of each of the second shift registers RSR(1)-RSR(N) from the first stage to the Nth stage (the number of transistors in each of the first shift registers LSR(1)-LSR(N) from the first stage to the Nth stage is greater than the number of transistors in each of the second shift registers RSR(1)-RSR(N) from the first stage to the Nth stage), the layout width W LG is greater than the layout width W RG . Therefore, the sub-peripheral region 110B2 has an additional circuit layout space CA for arranging other circuits (such as an electrostatic discharge protection circuit, a test circuit, or other circuits that can be arranged on the active array substrate 112).

[0077] Figure 11B is another schematic diagram of the configuration of the active region 110A and the peripheral region 110B in the display panel 110. In Figure 11B , the peripheral region 110B includes sub-peripheral regions 110B1 and 110B2 respectively located outside opposite sides of the active region 110A. The sub-peripheral regions 110B1 and 110B2 respectively have a boundary width W LB 、W RB ’. Figure 11B The difference between Figure 11A and Figure 11B is that the boundary width W RB ’ of the sub-peripheral region 110B2 in LB, that is, the widths of the sub-peripheral regions 110B1 and 110B2 located outside the opposite sides of the active region 110A are asymmetric. For example, a plurality of display panels 110 of this embodiment can be spliced to form a spliced screen, where the sub-peripheral region 110B2 of one of the adjacent two display panels 110 is spliced with the sub-peripheral region 110B1 of the other, but it is not limited thereto. Figure 11B The rest of Figure 11A is the same as the content shown, so it will not be repeated here.

[0078] As can be seen from the above description, through the special design of the gate driving circuit, the present invention can reduce the frame width of the display device and / or increase the layout area of other circuits in the display device, and can effectively reduce power consumption.

[0079] Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field to which the present invention pertains can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to that defined by the appended claims.

Claims

1. A gate driving circuit for driving a plurality of scan lines of a display panel, characterized in that, Comprising: A first gate driving circuit, including a first shift register of a first stage to an Nth stage, respectively configured to output a first scan signal of the first stage to the Nth stage, and the first scan signals of the first stage to the Nth stage are respectively transmitted to N scan lines among the plurality of scan lines, where N is a positive integer greater than or equal to 4; and A second gate driving circuit, including a second shift register of a first stage to an Nth stage, respectively configured to output a second scan signal of the first stage to the Nth stage, and the second scan signals of the first stage to the Nth stage are respectively transmitted to another N scan lines among the plurality of scan lines; Wherein the number of transistors in each of the second shift registers of the first stage to the Nth stage is less than the number of transistors in each of the first shift registers of the first stage to the Nth stage.

2. The gate driving circuit according to claim 1, wherein Each of the first shift registers of the first stage to the Nth stage has a first width, each of the second shift registers of the first stage to the Nth stage has a second width, and the first width is greater than the second width.

3. The gate driving circuit according to claim 1, wherein Each of the second shift registers of the first stage to the Nth stage is configured to receive a first input signal, and the first input signal of the ith second shift register among the second shift registers of the first stage to the Nth stage is a corresponding one of the first scan signals of the first stage to the Nth stage, where i is a positive integer greater than or equal to 1 and less than or equal to N.

4. The gate driving circuit according to claim 3, wherein Each of the second shift registers of the first stage to the Nth stage is configured to further receive a second input signal, and the second input signal of the jth second shift register among the second shift registers of the first stage to the (N - 1)th stage is a corresponding one of the first scan signals of the first stage to the Nth stage, where j is a positive integer greater than or equal to 1 and less than or equal to (N - 1).

5. The gate driving circuit according to claim 4, wherein The first gate driving circuit further includes a dummy shift register, configured to receive one of the first scan signals of the first stage to the Nth stage, and the dummy shift register outputs a dummy scan signal, where the second input signal of the Nth second shift register is the dummy scan signal.

6. The gate driving circuit according to claim 4, wherein The second gate driving circuit further includes a scan control signal line, the scan control signal line is coupled to the Nth second shift register, and the second input signal of the Nth second shift register is a scan control signal provided by the scan control signal line.

7. The gate driving circuit according to claim 1, wherein The second gate driving circuit further includes at least one clock signal line, and the ith second shift register among the second shift registers of the first stage to the Nth stage includes: A first transistor, whose first end is used to receive a first voltage signal, whose second end is coupled to a first node, and whose control end is used to receive a first input signal; A second transistor, whose first end is used to receive a second voltage signal, whose second end is coupled to the first node, and whose control end is used to receive a second input signal; A third transistor, whose first end is used to receive a clock signal provided by a corresponding one of the at least one clock signal line, the second end is coupled to a second node and is used to output an ith second scan signal, and whose control end is coupled to the first node, where i is a positive integer greater than or equal to 1 and less than or equal to N.

8. The gate driving circuit according to claim 7, wherein The i-th stage second shift register further includes: a fourth transistor, a first end of which is used to receive a first reference potential, and a control end of which is coupled to the first node; a fifth transistor, a first end of which is used to receive the first reference potential, a second end of which is coupled to the first node, and a control end of which is coupled to a second end of the fourth transistor; a sixth transistor, a first end of which is used to receive the first reference potential, a second end of which is coupled to the second node, and a control end of which is coupled to the second end of the fourth transistor; and a seventh transistor, a first end and a control end of which are used to receive a second reference potential, and a second end of which is coupled to the second end of the fourth transistor, wherein the second reference potential is greater than the first reference potential.

9. A display device, characterized in that, including: a display panel having an active area and a peripheral area, and including a plurality of scan lines located in the active area; and a gate driving circuit located in the peripheral area, the gate driving circuit being configured to drive the plurality of scan lines of the display panel, and the gate driving circuit including: a first gate driving circuit including first shift registers of the first stage to the N-th stage, respectively configured to output first scan signals of the first stage to the N-th stage, the first scan signals of the first stage to the N-th stage being respectively transmitted to N scan lines among the plurality of scan lines, where N is a positive integer greater than or equal to 4; and a second gate driving circuit including second shift registers of the first stage to the N-th stage, respectively configured to output second scan signals of the first stage to the N-th stage, the second scan signals of the first stage to the N-th stage being respectively transmitted to another N scan lines among the plurality of scan lines; wherein the number of transistors in each of the second shift registers of the first stage to the N-th stage is less than the number of transistors in each of the first shift registers of the first stage to the N-th stage.

10. The display device according to claim 9, characterized in that, The peripheral area includes a first sub-peripheral area and a second sub-peripheral area, which are respectively located outside opposite sides of the active area, wherein the first gate driving circuit and the second gate driving circuit are respectively located in the first sub-peripheral area and the second sub-peripheral area, each of the first shift registers of the first stage to the N-th stage has a first width, each of the second shift registers of the first stage to the N-th stage has a second width, and the first width is greater than the second width.

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