Gate driver, display device including the same, and driving method of display device

Abstract

The present specification discloses a gate driver, a display device including the gate driver, and a driving method of the display device. When the gate-on voltage of the J-th clock signal is different from the gate-on voltage of the first clock signal, the gate driver applies a compensation gate-on voltage to the gate-on voltage node, the compensation gate-on voltage being a gate-on voltage at which the voltage level changes. The display device includes a sensing unit for sensing a clock signal, and a compensation unit for applying a compensation gate turn-on voltage to the gate driver according to the sensed clock signal. According to the present specification, a gate-source voltage of a transistor disposed on an output unit may be maintained at a previous voltage. In addition, a driving failure caused by a load received by a clock signal provided to a relatively farther stage may be prevented.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority and the benefit of Korean Patent Application No. 10 - 2023 - 0195400, filed on December 28, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This specification relates to a gate driver, a display device including the gate driver, and a driving method of the display device. Background Art

[0004] An organic light - emitting diode (OLED) display device includes OLEDs that emit light by themselves and has advantages such as a fast response time, high luminous efficiency, high brightness, and a wide viewing angle. The OLED display device has excellent contrast and color gamut because it can represent black grayscale as all - black.

[0005] A display device may include a display panel that displays an image and on which pixels are disposed, and a driver that provides a plurality of signals to the display panel. Each of the pixels may include a thin - film transistor (TFT) that supplies the voltage of a data line to a pixel electrode in response to a gate pulse. The gate pulse of the driver may be applied to the pixel TFT, and the data signal of the driver may be provided to the pixel through the pixel TFT to display an image.

[0006] The gate driver may be disposed outside the display panel or may be disposed to be distributed in the pixel array. Recently, a technology of embedding the gate driver and the pixel array in the display panel has been applied. The gate driver includes a shift register, and the shift register may include a plurality of stages connected in cascade with each other.

[0007] The shift register may receive a clock signal that swings between a gate high voltage (VGH) and a gate low voltage (VGL) from a printed circuit board (PCB) electrically connected to the display panel under the control of a timing controller. The shift register sequentially shifts the clock signal to provide a gate pulse (or a scan pulse) to the gate line.

[0008] The clock signal (also referred to as a "shift clock") should be provided to each stage with an actual constant gate high voltage and gate low voltage. However, due to an increase in the length of the clock line, the voltage of the clock provided to a stage disposed far from the printed circuit board may change due to the influence of the load connected to that stage. As the length of the clock line increases, due to the load caused by the resistance of the clock line and the parasitic capacitance connected to the clock line, a clock signal with a constant voltage may not be provided, resulting in defects in the output of the gate pulse. Summary of the Invention

[0009] This specification aims to achieve the above necessities and / or solve the problems of related technologies.

[0010] The purpose of this specification is not limited to the above purposes, and those skilled in the art will clearly understand other purposes not mentioned according to the following description.

[0011] The gate driver according to this specification includes a plurality of stages, which are cascaded with each other through carry signal lines and are configured to receive a clock signal through a clock line. Among them, the plurality of stages may include a first stage configured to receive a first clock signal and a start signal and output a first gate signal and a first carry signal, a Jth stage (J is a positive integer greater than or equal to 2 and less than or equal to N) configured to receive a Jth clock signal and a (J - 1)th carry signal and output a Jth gate signal and a Jth carry signal, and an Nth stage (N is a natural number greater than or equal to 2) configured to receive an Nth clock signal and an (N - 1)th carry signal and output an Nth gate signal and an Nth carry signal. And among them, each of the first stage to the Nth stage includes: a clock node input with the first clock signal, the Jth clock signal or the Nth clock signal; a gate conduction voltage node to which a gate conduction voltage is applied; and a gate cutoff voltage node to which a gate cutoff voltage is applied. Among them, each of the first clock signal and the Jth clock signal can swing between the gate conduction voltage and the gate cutoff voltage. And when the gate conduction voltage of the Jth clock signal is different from the gate conduction voltage of the first clock signal, a compensated gate conduction voltage, which is a gate conduction voltage with a changed voltage level, can be applied to the gate conduction voltage node of the Jth stage.

[0012] The Jth stage may include: a first output node that outputs the Jth gate signal including a scan signal and an emission control signal; a second output node that outputs the Jth carry signal; a start node that inputs the (J - 1)th carry signal; a first transistor that activates a QC node by applying either a compensated gate conduction voltage or a gate cutoff voltage to the QC node according to the Jth clock signal; a sixth transistor that supplies the Jth gate signal at the gate conduction voltage to the first output node synchronously from the time when a bootstrap is performed in synchronization with the activation timing of the first control node and the QC node; a QB control unit configured to activate a QB node opposite to the QC node according to the potentials of the clock node, the start node, and the QC node; and a seventh transistor that supplies the Jth gate signal at the gate cutoff voltage to the first output node when the QB node is activated before the QC node is activated. And the compensated gate conduction voltage can be applied to the second output node.

[0013] The J-th stage may include: an output node that outputs a J-th gate signal including a scan signal and a emission control signal; a start node that receives a (J-1)-th carry signal; a first transistor that activates a QC node by applying either a compensation gate-on voltage or a gate-off voltage to the QC node according to a J-th clock signal; a sixth transistor that supplies the J-th gate signal at the gate-on voltage to the output node from when a bootstrap is synchronized with the activation timing of the first control node and the QC node; a QB control unit configured to activate a QB node opposite to the QC node according to the potentials of a clock node, a start node, and the QC node; a seventh transistor that supplies the J-th gate signal at the gate-off voltage to the output node when the QB node is activated before the QC node is activated; and a tenth transistor that applies a compensation gate-on voltage to the first transistor according to the (J-1)-th carry signal, and wherein the gate-off voltage node may include a first gate-off voltage node to which a first gate-off voltage is applied and a second gate-off voltage node to which a second gate-off voltage is applied.

[0014] The display device according to the present specification includes: a display panel on which a plurality of gate lines, a plurality of power lines, and a gate driver according to the present specification are provided; wherein the gate driver is configured to receive a first clock signal, a J-th clock signal, or an N-th clock signal from a clock generation circuit, and supply a first gate signal, a J-th gate signal, or an N-th gate signal that swings between a gate-on voltage and a gate-off voltage to the plurality of gate lines; a power supply unit configured to generate power input to the display panel and the gate driver through the plurality of power lines; a sensing unit configured to sense the first clock signal, the J-th clock signal, or the N-th clock signal input to the gate driver; and a compensation unit configured to apply a compensation gate-on voltage to the gate driver based on the first clock signal, the J-th clock signal, or the N-th clock signal sensed by the sensing unit.

[0015] The driving method of the display device according to the present specification includes: sensing the gate-on voltage of a J-th clock signal input to the J-th stage; causing a difference between the gate-on voltage of the J-th clock signal sensed through the sensing and the gate-on voltage of the first clock signal; and applying a compensation gate-on voltage to the gate-on voltage node of the J-th stage, wherein the voltage level of the compensation gate-on voltage changes based on the gate-on voltage of the J-th clock signal and the gate-on voltage of a clock signal input from a clock generation circuit. Description of the Drawings

[0016] Figure 1A , Figure 1B and Figure 1C are block diagrams showing a display device according to an embodiment of the present specification.

[0017] Figure 2 is a cross-sectional view showing the cross-sectional structure of the display panel shown Figures 1A to 1C in the figure.

[0018] Figure 3 is a circuit diagram schematically showing a pixel circuit of a display device according to an embodiment of the present specification.

[0019] Figure 4 is a waveform diagram schematically showing a gate signal applied to the pixel circuit according to an embodiment of the present specification.

[0020] Figure 5 is a plan view schematically showing a scan driver and an EM driver according to an embodiment of the present specification.

[0021] Figure 6A and Figure 6B is a circuit diagram showing a pixel circuit included in a display device according to an embodiment of the present specification.

[0022] Figure 7 is schematically showing for outputting an applied to Figure 6A and Figure 6B a view of a gate driver of the gate signal of the pixel circuit shown in the figure.

[0023] Figure 8 is a view showing a gate driver for outputting a gate signal applied to a pixel circuit.

[0024] Figure 9 is showing an input to Figure 8 a waveform diagram of a clock and a start pulse of the shift register shown in the figure.

[0025] Figure 10 is a flowchart showing a method of driving a display device according to an embodiment of the present specification.

[0026] Figure 11 is a view schematically showing a shift register of a gate driver according to an embodiment of the present specification.

[0027] Figure 12 is a circuit diagram showing a single-stage circuit included in a gate driver according to an embodiment of the present specification.

[0028] Figure 13 is showing Figure 12 a waveform diagram of input and output waveforms of the circuit shown in the figure.

[0029] Figure 14 is a table showing operations of stages corresponding to Figure 13 sections A to F of.

[0030] Figures 15A to 15F is a circuit diagram showing the operation states of the stages corresponding to sections A to F of Figure 13 .

[0031] Figure 16A and Figure 16B is a waveform diagram showing the changes in the gate-on and gate-off voltages of the clock signal supplied to the shift register.

[0032] Figure 17A is a circuit diagram showing the output abnormal operation state that occurs when a shift gate voltage is supplied to a defective stage.

[0033] Figure 17B is a circuit diagram showing the output abnormal operation state of the stage that receives a carry signal from a defective stage.

[0034] Figure 18 is a block diagram schematically showing a display device and a gate driver according to an embodiment of the present specification.

[0035] Figure 19 is a block diagram specifically showing a display device and a gate driver according to an embodiment of the present specification.

[0036] Figure 20 is a circuit diagram specifically showing a sensing unit and a compensation unit according to an embodiment of the present specification.

[0037] Figure 21 is a block diagram specifically showing a display device and a gate driver according to another embodiment of the present specification.

[0038] Figure 22 is a single-stage circuit included in a gate driver according to a first embodiment of the present specification.

[0039] Figure 23 is a single-stage circuit included in a gate driver according to a second embodiment of the present specification.

[0040] Figure 24 is a single-stage circuit included in a gate driver according to a third embodiment of the present specification.

[0041] Figure 25 is a single-stage circuit included in a gate driver according to a fourth embodiment of the present specification. Detailed Embodiments

[0042] Advantages and features of the present specification and methods for achieving these advantages and features will become clear with reference to the embodiments described in detail below in conjunction with the accompanying drawings. The present disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms. These embodiments are provided only to make the disclosure of the present disclosure complete and to fully inform those skilled in the art to which the present disclosure pertains of the scope of the present disclosure, and the present disclosure is defined only by the scope of the appended claims.

[0043] When describing the present disclosure, detailed descriptions of related known technologies will be omitted when it is determined that they may unnecessarily obscure the gist of the present disclosure.

[0044] When using the terms "comprising", "including", "having", and "consisting of" described in this specification, unless "only" is used, other parts can be added. When a component is expressed in the singular, it can be interpreted as multiple components unless otherwise specifically stated.

[0045] When describing the positional relationship and interconnection relationship between two components, such as "above", "over", "below", "adjacent", "connected or coupled", "crossed or intersected", etc., unless the terms "immediately" or "directly" are described, one or more other components can be placed between the components.

[0046] When using terms such as "after", "subsequently", "then", "before", etc. to describe the time relationship, unless the term "immediately" or "directly" is used, non - consecutive cases can be included.

[0047] Although terms such as "first", "second", etc. can be used to distinguish components, the function or structure of the components is not limited by the ordinal number or component name added in front of the component.

[0048] The following embodiments can be partially or fully coupled or combined, and various technical interconnections and drivings are possible. The embodiments can be implemented independently of each other and can also be implemented together in an associated relationship.

[0049] In addition, unless explicitly and specifically defined and described, the terms (including technical terms and scientific terms) used in the embodiments of this specification can be interpreted as the meanings that those skilled in the art to which this specification pertains may generally understand, and the meanings of commonly used terms, such as the terms defined in a dictionary, can be interpreted by considering the context meaning of the related technology.

[0050] In the display device according to this specification, the pixel circuit and the gate driving circuit can include multiple transistors. The transistors can be oxide thin - film transistors (TFTs) containing an oxide semiconductor or LTPS TFTs containing low - temperature polycrystalline silicon (LTPS).

[0051] A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode for supplying carriers to the transistor. Carriers flow from the source in the transistor. The drain is an electrode through which carriers move from the transistor to the outside. In a transistor, carriers flow from the source to the drain.

[0052] In the case of an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage, so that electrons can flow from the source to the drain. In an n-channel transistor, the current flows from the drain to the source. In the case of a p-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the present disclosure is not limited to the source and drain of the transistor. In the following description, the source and drain of the transistor are referred to as "first electrode and second electrode".

[0053] The gate signal may swing between a gate-on voltage and a gate-off voltage. The transistor is turned on in response to the gate-on voltage, and the transistor is turned off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage (VGH), and the gate-off voltage may be a gate low voltage (VGL). In the case of a p-channel transistor, the gate-on voltage may be a gate low voltage (VGL), and the gate-off voltage may be a gate high voltage (VGH).

[0054] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0055] Figure 1A , Figure 1B and Figure 1C is a block diagram showing a display device according to an embodiment of the present specification. Figure 2 is a cross-sectional view showing a cross-sectional structure of the display panel shown in FIG. 1 .

[0056] Reference Figure 1A , Figure 1B , Figure 1C and Figure 2 The display device according to the present specification may include: a display panel 100; a display panel driving circuit for writing pixel data on pixels of the display panel 100; and a power supply unit 140 for generating power required to drive the pixels and the display panel driving circuit. The display device according to the present specification may include a display panel 100, a power supply unit 140, and a plurality of display panel driving circuits.

[0057] The display panel 100 can be formed of a plastic substrate, a thin glass substrate, a metal substrate, etc. Pixels 101 can be implemented on the display panel 100.

[0058] The display panel 100 can be a rectangular panel having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction, but is not limited thereto. The display area AA of the display panel 100 can include a pixel array in which an input image is displayed. The pixel array can include a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and a plurality of pixels 101 arranged in a matrix form. The display panel 100 can also include power lines commonly connected to the pixels 101. The power lines can be connected to constant voltage nodes of pixel circuits to provide a constant voltage required to drive the pixels 101 for the pixels 101.

[0059] Each of the pixels 101 can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to achieve colors. Each of the pixels can also include a white sub-pixel. Each sub-pixel can include a pixel circuit for driving a light-emitting element. Each pixel circuit can be connected to a data line, a gate line, and a power line. Hereinafter, a "pixel" can be understood as a "sub-pixel".

[0060] Pixels can be set as true color pixels and pentile pixels. Pentile pixels can achieve a higher resolution than true color pixels by driving two sub-pixels of different colors as one pixel 101 using a preset pixel rendering algorithm. The pixel rendering algorithm can compensate for insufficient color representation in each pixel with the color of light emitted from adjacent pixels.

[0061] The pixel array can include a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln can include the pixels of one row arranged in the row direction (X-axis direction) in the pixel array of the display panel 100. Among the first pixel row L1 to the nth pixel row Ln, the pixels arranged on the same pixel row can share the same gate line 103. The sub-pixels arranged in the column direction Y along the data line direction can share the same data line 102. One horizontal section can be a time obtained by dividing one frame section by the total number of the pixel rows L1 to Ln.

[0062] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel can be applied to a transparent display device in which an image is displayed on a screen and real objects in the background are visible. The display panel 100 can be manufactured as a flexible display panel.

[0063] As Figure 2 shown, the display panel 100 can include a circuit layer CIR, a light-emitting element layer EMIL, and a packaging layer EN stacked on a substrate SUBS.

[0064] The circuit layer CIR may include: a TFT array including pixel circuits connected to lines such as data lines, gate lines, and power lines; a gate driver 120, etc. The circuit layer CIR may include a plurality of metal layers and semiconductor material layers insulated by an insulating layer interposed therebetween.

[0065] The light-emitting element layer EMIL may include light-emitting elements driven by pixel circuits. The light-emitting elements may include light-emitting elements for red sub-pixels, light-emitting elements for green sub-pixels, and light-emitting elements for blue sub-pixels. The light-emitting element layer EMIL may also include light-emitting elements for white sub-pixels. The light-emitting element layer EMIL in each sub-pixel may have a structure in which a light-emitting element and a color filter are stacked. The light-emitting element EL in the light-emitting element layer EMIL may be covered by a plurality of protective layers including organic layers and inorganic layers.

[0066] The encapsulation layer EN may cover the light-emitting element layer EMIL to seal the circuit layer CIR and the light-emitting element layer EMIL. The encapsulation layer EN may have a multi-insulating film structure in which organic films and inorganic films are alternately stacked. The inorganic film may prevent the penetration of moisture or oxygen. The organic film may flatten the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, the movement path of moisture or oxygen may be longer compared to a single layer, thereby effectively blocking the penetration of moisture and oxygen that affect the light-emitting layer EMIL.

[0067] A touch sensor layer (omitted in the drawing) may be formed on the encapsulation layer EN, and a polarizer or a color filter layer may be provided on the touch sensor layer. The touch sensor layer may include a capacitive touch sensor for sensing a touch input based on a capacitance change before and after the touch input. The touch sensor layer may include metal wire patterns and insulating films that generate the capacitance of the touch sensor. The insulating film may insulate the crossing portions of the metal wire patterns and flatten the surface of the touch sensor layer. The polarizer may increase visibility and contrast by converting the polarization of external light reflected by the metal of the touch sensor layer and the circuit layer. The polarizer may be implemented as a polarizer in which a linear polarizer and a phase retardation film are joined or a circular polarizer. A cover glass may be joined to the polarizer. The color filter layer may include red, green, and blue color filters. The color filter layer may also include a black matrix pattern. The color filter layer may absorb light of a part of wavelengths reflected from the circuit layer and the touch sensor layer to be used as a polarizer and improve the color purity of an image displayed in the pixel array.

[0068] The power supply unit 140 can use a DC-DC converter to generate a constant voltage (or DC voltage) required to drive the pixel array and the display panel driving circuit of the display panel 100. The DC-DC converter can include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit 140 can adjust the level of the DC input voltage applied from the host system 200 and output a constant voltage, such as a gamma reference voltage, a gate high voltage, a gate low voltage, a pixel driving voltage, a cathode voltage, and an initialization voltage.

[0069] The gamma reference voltage can be provided to the data driver 110. The dynamic range of the data voltage output from the data driver 110 can be determined according to the voltage range of the gamma reference voltage. The dynamic range of the data voltage can be the voltage range between the highest gray scale voltage and the lowest gray scale voltage.

[0070] The gate high voltage and the gate low voltage can be provided to the level shifter 150 and the gate driver 120.

[0071] Constant voltages such as the pixel driving voltage, the cathode voltage, and the initialization voltage can be provided to the pixel 101 through a power line commonly connected to the pixel 101. The pixel driving voltage can be output from the main power supply of the host system 200 and provided to the display panel 100. In this case, the power supply unit 140 does not need to output the pixel driving voltage.

[0072] The display panel driving circuit can write the pixel data of the input image on the pixels of the display panel 100 under the control of the timing controller 130. The display panel driving circuit can include a data driver 110 and a gate driver 120.

[0073] The display panel driving circuit can also include a touch sensor driver for driving a touch sensor. The touch sensor driver is omitted in FIG. 1. The data driver 110 and the touch sensor driver can be integrated into one driving IC.

[0074] The data driver 110 can receive the pixel data of the input image received as a digital signal from the timing controller 130 and output a data voltage. The data driver 110 can use a digital-to-analog converter (DAC) to convert the pixel data of the input image into a gamma compensation voltage and output a data voltage. The gamma reference voltage VGMA can be divided into gamma compensation voltages for each gray scale through a voltage dividing circuit of the data driver 110 and provided to the DAC. The DAC can generate a data voltage, where the gamma compensation voltage corresponds to the gray scale value of the pixel data. The data voltage output from the DAC can be output to the data line 102 through the output buffer of each channel of the data driver 110.

[0075] The gate driver 120 may be formed on a circuit layer CIR on the display panel 100 together with the lines of the TFT array and the pixel array. The gate driver 120 may be disposed in a non-display area BZ outside the display area AA of the display panel 100, or at least some of the gate driver 120 may be disposed to be distributed in the display area AA.

[0076] The gate driver 120 may include a plurality of shift registers for sequentially shifting pulses of a gate signal. The gate driver 120 may be disposed on either the left or right non-display area BZ outside the display area AA of the display panel 100 to provide a gate signal to the gate line 103 in a single-feed method. In the single-feed method, the gate signal may be applied to one end of the gate line 103.

[0077] The gate driver 120 may be disposed in the left non-display area BZ and the right non-display area BZ of the display panel 100 to apply a gate signal to the gate line 103 in a dual-feed method. In the dual-feed method, the gate signal may be applied to both ends of the gate line 103 simultaneously.

[0078] At least some circuits of the gate driver 120 may be disposed in the display area AA.

[0079] The gate driver 120 may sequentially output pulses of the gate signal to the gate line under the control of the timing controller 130. The gate driver 120 may sequentially provide a signal to the gate line 103 by shifting pulses of the gate signal using a shift register. The gate driver 120 may output a plurality of gate signals having different phases and pulse widths using a plurality of shift registers. The gate signal may be divided into a scan signal and an emission control signal (hereinafter referred to as an “EM signal”).

[0080] The timing controller 130 may receive digital video data of an input image and a timing signal synchronized with the data from the host system 200. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, etc. Since the vertical section and the horizontal section can be known in the method of calculating the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The data enable signal DE may have a section of 1 horizontal section (1H), but is not limited thereto.

[0081] The timing controller 130 can provide a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system 200. The timing controller 130 can synchronize the data driver 110, the touch sensor driver, and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0082] The gate timing control signal generated from the timing controller 130 can be input to the shift register of the gate driver 120 through the level shifter 150. The gate timing control signal can include a start pulse, a clock, etc. The level shifter 150 can receive the gate timing control signal, generate a start pulse and a shift clock, and provide the start pulse and the shift clock to the gate driver 120 through the clock line.

[0083] The input signal of the level shifter 150 can be a digital voltage signal, and its output signal can be an analog voltage signal that swings between the gate high voltage VGH and the gate low voltage VGL.

[0084] The host system 200 can include the main board of any one of a TV system, a set-top box, a navigation system, a personal computer (PC), a vehicle system, a mobile terminal, and a wearable terminal. The host system can scale the image signal from the video source according to the resolution of the display panel 100 and transmit the scaled image signal together with the timing signal to the timing controller 130.

[0085] In a mobile system, the host system 200 can be implemented as an application processor (AP). The host system 200 can transmit the pixel data of the input image to the driving IC through the Mobile Industry Processor Interface (MIPI). The host system 200 can be electrically connected to the driving IC through a flexible printed circuit such as a flexible printed circuit (FPC). The driving IC can be bonded to the display panel 100 in a Chip on Glass (COG) process. The driving IC can have a Chip on Film (COF) structure mounted on a flexible circuit film and can be electrically connected to the lines on the display panel 100.

[0086] The timing controller 130 or the host system 200 may reduce the power consumption of the display device by entering a low power mode when receiving a static image or always-on display (AOD) data. In the normal mode, the refresh rate of the pixel 101 may be 60 Hz, 144 Hz, 240 Hz, etc. The refresh rate may be the frequency at which pixel data is written onto the pixel 101. In the low power mode, the refresh rate of the pixel 101 may be reduced to a frequency lower than 60 Hz, such as 1 Hz to 30 Hz. When the refresh rate is 1 Hz, the first frame out of 60 frames per second may be a refresh frame, and the subsequent 59 frames may be hold frames. After the data voltage Vdata of the pixel data is charged to the pixel 101 during the refresh frame section, during the consecutive hold frame sections, the pixel 101 may hold the data voltage charged during the previous refresh frame without charging a new data voltage Vdata to maintain the light emitting state.

[0087] The display panel driving circuit may include a compensation voltage generator 160 for outputting compensation voltages Vpark, VOBS, and VAR. At least a part of the compensation voltage generator 160 may use resources of other components such as the power supply unit 140, the data driver 110, and the display panel 100. The compensation voltage generator 160 may change the voltage levels of each of the compensation voltages Vpar, VOBS, and VAR under the control of the timing controller 130. The power supply unit 140 may be implemented as a single power IC together with the compensation voltage generator 160.

[0088] Each sub-pixel may include a pixel circuit, the pixel circuit including a driving element for driving a light emitting element and a capacitor connected to the driving element. The pixel circuit of each sub-pixel may include an internal compensation circuit for compensating a data voltage by as much as the threshold voltage of the driving element.

[0089] Figure 3 is a circuit diagram schematically showing a pixel circuit of a display device according to an embodiment of the present specification. Figure 4 is a waveform diagram schematically showing a gate signal applied to the pixel circuit according to an embodiment of the present specification. Figure 5 is a plan view schematically showing a scan driver and an EM driver according to an embodiment of the present specification.

[0090] Referring to Figures 3 to 5 , the pixel circuit may include a light emitting element EL, a switch circuit SWC for programming the gate-source voltage of the driving element DT, a driving element DT for controlling a driving current flowing through the light emitting element EL according to the gate-source voltage, and an emission transistor ET turned on / off by an emission control signal EM to determine the emission timing of the light emitting element EL.

[0091] The switching circuit SWC may include a plurality of switching TFTs, one or more capacitors, etc., and various modifications are possible depending on the product model and specifications.

[0092] Each of the pixels 101 can be driven according to a gate signal. Each of the pixels 101 can perform an initialization operation, a programming operation, and an emission operation according to a scan signal SCAN and an emission control signal EM. In the initialization section a, the switching circuit SWC can initialize a specific node in the pixel circuit to a reference voltage Vref. During the programming section b, the switching circuit SWC can program the gate-source voltage of the driving element DT based on the data voltage Vdata. During the programming section b, the change in the threshold voltage of the driving element DT can be sampled and compensated. During the emission section c, a driving current corresponding to the gate-source voltage can flow between the source and the drain of the driving element DT, and the light-emitting element EL can emit light through the driving current.

[0093] According to the emission control signal EM, the emission transistor ET can be turned on during the initialization section a and the emission section c, and turned off during the programming section b. However, the emission control signal EM can be modified in any of various ways according to the pixel structure, and in this case, the emission transistor ET can be turned on during the emission section c and turned off during other sections.

[0094] The gate driver 120 can be arranged on two opposite sides of the display panel in a dual-feed (double bank) method, thereby minimizing signal distortion caused by load differences at each position. The gate driver 120 can include a scan driver 121 for generating the scan signal SCAN and an EM driver 122 for generating the emission control signal EM.

[0095] The scan driver 121 can supply the scan signal SCAN to the first gate lines 103a1 to 103an connected to the pixels 101 in a line sequential manner.

[0096] The EM driver 122 can supply the emission control signal EM to the second gate lines 103b1 to 103bn connected to the pixels 101 in a line sequential manner. The EM driver 122 can be implemented as including a plurality of stages of shift registers. Each stage of the EM driver 122 can be arranged to minimize the border area of the display panel. Each stage of the EM driver 122 can be implemented to minimize the border area of the display panel and to ensure the stability and reliability of operation even if the display panel has portions with different shapes (e.g., a partially curved surface or a notch).

[0097] Figure 6A and Figure 6Bis a circuit diagram showing a pixel circuit included in a display device according to an embodiment of the present specification.

[0098] Referring to Figure 6A and Figure 6B , the pixel circuit may include a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a plurality of switching elements M1 to M7, and a storage capacitor Cst. The pixel circuit may further include a second capacitor C2.

[0099] Each of the third switching element M3 and the fourth switching element M4 may be implemented as an n-channel oxide TFT. Each of the driving element DT and the first switching element M1, the second switching element M2, the fifth switching element M5, the sixth switching element M6, and the seventh switching element M7 may be implemented as a p-channel LTPS TFT. The n-channel oxide TFT may be turned on in response to a gate high voltage VGH, while the n-channel oxide TFT may be turned off in response to a gate low voltage VGL. The p-channel LTPS TFT may be turned on in response to a gate low voltage VGL, while the p-channel LTPS TFT may be turned off in response to a gate high voltage VGH.

[0100] The pixel circuit may include a data line DL and gate lines GL11, GL1i, GL2, GL3, and GL4. The data line DL is applied with a data voltage Vdata of pixel data and a first compensation voltage Vpark, and the gate lines GL11, GL1i, GL2, GL3, and GL4 are applied with gate signals SC1n, SC1n-i, SC2n, SC3n, and EMn.

[0101] In the low power mode, the data driver provides the data voltage Vdata to the data line DL during the sampling period of the refresh frame section, and does not output the data voltage Vdata during the hold frame section. During the hold frame section, the first compensation voltage Vpark may be provided to the data line DL. The first compensation voltage Vpark may be provided from the above-mentioned compensation voltage generator.

[0102] The pixel circuit may be connected to a first power line PL1 to which a pixel driving voltage ELVDD is applied, a second power line PL2 to which a cathode voltage ELVSS is applied, a third power line PL3 to which an initialization voltage Vini is applied, a fourth power line PL4 to which a second compensation voltage VOBS is applied, and a fifth power line PL5 to which a third compensation voltage VAR is applied. On the display panel 100, the power lines PL1 to PL5 are commonly connected to all pixels.

[0103] The pixel driving voltage ELVDD and the cathode voltage ELVSS can be set to voltages such that the driving element DT can operate in the saturation region. The pixel driving voltage ELVDD can be set to a voltage between 2V and 3V, and the cathode voltage ELVSS can be set to a voltage between -8V and -10V, but this specification is not limited thereto. The gate high voltage VGH can be set to a voltage higher than the pixel driving voltage ELVDD, and the gate low voltage VGL can be set to a voltage lower than the cathode voltage ELVSS, but this specification is not limited thereto.

[0104] The data voltage Vdata can have a dynamic range between 2V and 6V. Within the dynamic range, the voltage level of the data voltage Vdata can be selected according to the gray value of the pixel data.

[0105] The initialization voltage Vini can be set to a voltage lower than the lower limit voltage of the data voltage Vdata and higher than the cathode voltage ELVSS. For example, when the lower limit voltage of the data voltage Vdata is 2V and the cathode voltage ELVSS is -9V, the initialization voltage Vini can be set to a voltage between -5V and -7V or vary within this voltage range.

[0106] The first compensation voltage Vpark can be set within a voltage range smaller than the dynamic range of the data voltage Vdata. For example, when the dynamic range of the data voltage Vdata is between 2V and 6V, the first compensation voltage Vpark can be set to a voltage between 4V and 6V or vary within this voltage range.

[0107] The second compensation voltage VOBS can be lower than the pixel driving voltage ELVDD and is set within a voltage range that partially overlaps with the dynamic range of the data voltage Vdata. For example, when the dynamic range of the data voltage Vdata is between 2V and 6V, the second compensation voltage VOBS can be set to a specific voltage between 4V and 8V or vary within this voltage range.

[0108] The third compensation voltage VAR can be set to a specific voltage or vary. For example, when the dynamic range of the data voltage Vdata is between 2V and 6V, the third compensation voltage VAR can be set to a specific voltage between -4V and -8V or vary within this voltage range.

[0109] The compensation voltages Vpark, VOBS, and VAR applied to a sub-pixel at a specific position in the display area AA can be set to different voltages.

[0110] The gate signals SC1n, SC1n-i, SC2n, SC3n, and EMn may include pulses that swing between a gate high voltage VGH and a gate low voltage VGL. A gate driver for applying the gate signals to the pixel circuits shown may include a first shift register for outputting first scan signals SC1n and SC1n-i, a second shift register for outputting a second scan signal SC2n, a third shift register for outputting a third scan signal SC3n, and a fourth shift register for outputting an EM signal (EMn). Each of the first to fourth shift registers may output pulses during a refresh frame and shift the pulses sequentially. Since the first and second shift registers do not output pulses during a hold frame HF, very little power consumption may occur.

[0111] The first scan signals SC1n and SC1n-i may include a 1-1 scan signal SC1n-i and a 1-2 scan signal SC1n that are sequentially output from the first shift register. The 1-2 scan signal SC1n may be output after the 1-1 scan signal SC1n-i is output from the first shift register. Some sections of the 1-1 scan signal SC1n-i pulses may overlap some sections of the 1-2 scan signal SC1n pulses. The 1-2 scan signal SC1n may have a phase that is later than the phase of the 1-1 scan signal SC1n-i and have the same pulse width W.

[0112] The driving element DT may include a gate electrode connected to a first node n1, a first electrode connected to a second node n2, and a second electrode connected to a third node n3.

[0113] The storage capacitor Cst may be connected between a node on a first power line PL1 to which a pixel driving voltage ELVDD is applied and the first node n1. The storage capacitor Cst may suppress fluctuations in the gate-source voltage Vgs of the driving element DT for driving the light-emitting element EL by charging the pixel driving voltage ELVDD and the voltage at the first node n1.

[0114] The second capacitor C2 may be connected between the first node n1 and the third gate line GL3 to which the third scan signal SC3n is applied. The second capacitor C2 may suppress fluctuations in the gate voltage of the driving element DT at the falling edge of the 1-2 scan signal SC1n and compensate for the fluctuations. The voltage of the 1-2 scan signal SC1n may drop from the gate high voltage VGH to the gate low voltage VGL. In this case, due to the parasitic capacitance between the gate line GL11 to which the voltage of the 1-2 scan signal SC1n is applied and the first node n1, a kickback voltage may be generated, and the gate voltage of the driving element DT may instantaneously drop. When the voltage of the gate line GL11 to which the voltage of the 1-2 scan signal SC1n is applied drops to the gate low voltage VGL, the second capacitor C2 may suppress the kickback voltage by the gate high voltage VGH applied to the gate line GL3. When the voltage of the gate line GL3 to which the voltage of the third scan line SC3n is applied rises to the gate high voltage VGH, the second capacitor C2 may compensate for the fluctuations in the gate voltage of the driving element DT that have dropped as much as the kickback voltage.

[0115] The light-emitting element EL may include an anode connected to the fourth node n4 and a cathode connected to the second power line PL2 to which the cathode voltage ELVSS is applied.

[0116] The first switching element M1 may be connected between the first power line PL1 to which the pixel driving voltage ELVDD is applied and the second node n2. The first switching element M1 may turn on in response to the gate low voltage VGL of the EM signal (EMn). When the first switching element M1 is turned on, the pixel driving voltage ELVDD may be applied to the second node n2. The first switching element M1 may include a gate electrode connected to the fourth gate line GL4 to which the EM signal (EMn) is applied, a first electrode connected to the first power line PL1, and a second electrode connected to the second node n2.

[0117] The second switching element M2 may be connected between the data line DL and the second node n2. The second switching element M2 may turn on in response to the gate low voltage VGL of the second scan signal SC2n. When the second switching element M2 is turned on, the data line DL to which the data voltage Vdata of the pixel data is applied may be connected to the second node n2. The second switching element M2 may include a gate electrode connected to the second gate line GL2 to which the second scan signal SC2n is applied, a first electrode connected to the data line DL, and a second electrode connected to the second node n2.

[0118] The third switching element M3 may be connected between the first node n1 and the third node n3. The third switching element M3 may be turned on in response to the gate high voltage VGH of the 1-2 scan signal SC1n. When the third switching element M3 is turned on, the first node n1 may be connected to the third node n3. Therefore, when the third switching element M3 is turned on, the gate electrode of the driving element DT may be connected to the second electrode, such that the driving element DT operates as a diode. The third switching element M3 may include a gate electrode connected to the 1-2 gate line GL11 to which the 1-2 scan signal SC1n is applied, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0119] The fourth switching element M4 may be connected between the first node n1 and the third power line PL3 to which the initialization voltage Vini is applied. The fourth switching element M4 may be turned on in response to the gate high voltage VGH of the 1-1 scan signal SC1n-i. When the fourth switching element M4 is turned on, the initialization voltage Vini may be applied to the capacitor Cst connected to the first node n1 and the gate electrode of the driving element DT. The fourth switching element M4 may include a gate electrode connected to the 1-1 gate line GL1i to which the 1-1 scan signal SC1n-i is applied, a first electrode connected to the first node n1, and a second electrode connected to the third power line PL3.

[0120] The fifth switching element M5 may be connected between the second node n2 and the fourth power line PL4 to which the second compensation voltage VOBS is applied. The fifth switching element M5 may be turned on in response to the gate low voltage VGL of the third scan signal SC3n. When the fifth switching element M5 is turned on, the second compensation voltage VOBS may be applied to the second node n2. The fifth switching element M5 may include a gate electrode connected to the third gate line GL3 to which the third scan signal SC3n is applied, a first electrode connected to the second node n2, and a second electrode connected to the fourth power line PL4.

[0121] The sixth switching element M6 may be connected between the fourth node n4 and the fifth power line PL5 to which the third compensation voltage VAR is applied. The sixth switching element M6 may be turned on in response to the gate low voltage VGL of the third scan signal SC3n. When the sixth switching element M6 is turned on, the third compensation voltage VAR may be applied to the anode of the light-emitting element EL connected to the fourth node n4. The sixth switching element M6 may include a gate electrode connected to the third gate line GL3, a first electrode connected to the fourth node n4, and a second electrode connected to the fifth power line PL5.

[0122] The seventh switching element M7 may be connected between the third node n3 and the fourth node n4. The seventh switching element M7 may be turned on in response to the low gate voltage VGL of the EM signal EMn to connect the third node n3 to the fourth node n4. The seventh switching element M7 may include a gate electrode connected to the fourth gate line GL4, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4.

[0123] The data voltage Vdata of the pixel data is applied to the data line DL during the refresh frame section in which the pixel data is written to the pixel. The first compensation voltage Vpark may be set as a voltage for compensating for the brightness change of the pixel, and is applied to the data line DL during the hold frame section in which the pixel data is not written to the pixel. During the hold frame, the pixel may be driven by the data voltage Vdata charged in the storage capacitor Cst during the previous refresh frame.

[0124] When the data line DL and the second node n2 are electrically connected through the turned-on second switching element M2, the data voltage Vdata may be applied to the second node n2. The first compensation voltage Vpark may be applied to the second node n2 as the leakage current of the second switching element M2 in the off state of the second switching element M2 (i.e., the state in which the data line DL and the second node n2 are electrically separated), and is applied to the first node n1 through the parasitic capacitance. Here, the parasitic capacitance may include the parasitic capacitance existing between the first node n1 and the second node n2 and the parasitic capacitance existing between the first node n1 and the data line DL. The gate-source voltage Vgs of the driving element DT may be finely adjusted by the first compensation voltage Vpark.

[0125] The compensation voltages Vpark, VOBS, and VAR may improve the image quality of the image displayed in the pixel by compensating for the difference in the brightness characteristics of the pixel 101 between the refresh frame and the hold frame in the low power consumption mode.

[0126] Figure 7 schematically shows for outputting the applied to Figure 6A and Figure 6B a view of the gate driver of the gate signal of the pixel circuit shown.

[0127] Referring to Figure 7 , the gate driver may include a first shift register SR1 for sequentially outputting pulses of the first scan signals SC1n-i and SC1n, a second shift register SR2 for sequentially outputting pulses of the second scan signal SC2n, a third shift register SR3 for sequentially outputting pulses of the third scan signal SC3n, and a fourth shift register SR4 for outputting pulses of the EM signal EMn.

[0128] The first shift register SR1 may include a plurality of stages ST1 connected in cascade with each other. The first shift register SR1 may receive a start pulse VST1 and a clock CLK, and sequentially output pulses of a first scan signal in the order of SC11, SC12, ……, SC1n-i, ……, and SC1n.

[0129] The second shift register SR2 may include a plurality of stages ST2 connected in cascade with each other. The second shift register SR2 may receive a start pulse VST2 and a clock CLK, and sequentially output pulses of a second scan signal in the order of SC21, SC22, ……, SC2n-i, ……, and SC2n.

[0130] The third shift register SR3 may include a plurality of stages ST3 connected in cascade with each other. The third shift register SR3 may receive a start pulse VST3 and a clock CLK, and sequentially output pulses of a third scan signal in the order of SC31, SC32, ……, SC3n-i, ……, and SC3n.

[0131] The fourth shift register SR4 may include a plurality of stages ST4 connected in cascade with each other. The fourth shift register SR4 may receive a start pulse VST4 and a clock CLK, and sequentially output pulses of an EM signal in the order of EM1, EM2, ……, EMn-i, ……, and EMn.

[0132] The clock CLK input to the shift registers SR1, SR2, SR3, and SR4 may be two or more clocks with different phases. One or more of the phases, frequencies, and duty cycles of the start pulses and clocks input from the shift registers SR1, SR2, SR3, and SR4 may be different.

[0133] Figure 8 is a view of a gate driver for outputting a gate signal applied to a pixel circuit. Figure 9 is a view showing the input to Figure 8 the waveforms of the clock and start pulse of the shift register shown.

[0134] Referring to Figure 6A 、 Figure 6B 、 Figure 8 and Figure 9 ,the gate driver may include a first shift register SR1 for sequentially outputting pulses of a first scan signal SC1n-i and SC1n, a second shift register SR2 for sequentially outputting pulses of a second scan signal SC2n, a third shift register SR3 for sequentially outputting pulses of a third scan signal SC3n, and a fourth shift register SR4 for outputting pulses of an EM signal EMn.

[0135] The first shift register SR1 may include a plurality of stages ST1 connected in cascade with each other. The first shift register SR1 may receive a start pulse G1VST and clocks G1CLK1 and G1CLK2, and sequentially output pulses of first scan signals SC1n-i and SC1n. The clocks G1CLK1 and G1CLK2 may include two or more shift clocks having different phases. Pulse widths of the first scan signals SC1n-i and SC1n may be set to be longer than one horizontal section and be simultaneously applied to pixels provided in a plurality of pixel rows. For example, the 1-1 scan signal SC1(n-10) and the 1-2 scan signal SC1(n-2) may be simultaneously applied to vertically adjacent first pixel PXL1 and second pixel PXL2. Subsequently, the 1-1 scan signal SC1(n-8) and the 1-2 scan signal SC1(n) may be simultaneously applied to vertically adjacent third pixel PXL3 and fourth pixel PXL4. Subsequently, the 1-1 scan signal SC1(n-6) and the 1-2 scan signal SC1(n+2) may be simultaneously applied to vertically adjacent fifth pixel PXL5 and sixth pixel PXL6.

[0136] In order to adjust a brightness difference between pixel rows, timings such as phases and pulse widths of pulses of the second scan signals SC21, SC23, and SC25 applied to odd pixel rows and pulses of the second scan signals SC22, SC24, and SC26 applied to even pixel rows may be adjusted differently.

[0137] The second shift register SR2 may include a plurality of odd shift registers ST2O and a plurality of even shift registers ST2E. The plurality of odd shift registers ST2O are for receiving a first start pulse G2VST(ODD) and first clocks G2CLK1 and G2CLK2 and sequentially outputting pulses of odd second scan signals SC21, SC23, and SC25. The plurality of even shift registers ST2E are for receiving a second start pulse G2VST(EVEN) and second clocks G2CLK3 and G2CLK4 and sequentially outputting pulses of even second scan signals SC22, SC24, and SC26. Pulse widths of the second scan signals SC21 to SC26 may be one horizontal section.

[0138] The first clocks G2CLK1 and G2CLK2 may include two or more shift clocks having different phases. The second clocks G2CLK3 and G2CLK4 may include two or more shift clocks having different phases. A carry signal may be transmitted between adjacent odd stage ST2O and even stage ST2E.

[0139] After applying the pulse of the 2-1 scan signal SC21 to the first pixel PXL1, the pulse of the 2-2 scan signal SC22 can be applied to the second pixel PXL2. Subsequently, after applying the pulse of the 2-3 scan signal SC23 to the third pixel PXL3, the pulse of the 2-4 scan signal SC24 can be applied to the fourth pixel PXL4. Subsequently, after applying the pulse of the 2-5 scan signal SC25 to the fifth pixel PXL5, the pulse of the 2-6 scan signal SC26 can be applied to the sixth pixel PXL6.

[0140] The third shift register SR3 may include a plurality of stages ST3 connected in cascade with each other. The third shift register SR3 may receive a start pulse G3VST and clocks G3CLK1 and G3CLK2, and sequentially output pulses of the third scan signal SC3n. The clocks G3CLK1 and G3CLK2 may include two or more shift clocks having different phases. The pulse width of the third scan signal SC3n may be set to be longer than one horizontal section and applied to the pixels provided in a plurality of pixel rows simultaneously. For example, the pulse of the third scan signal SC3(n - 2) may be applied to the vertically adjacent first pixel PXL1 and second pixel PXL2 simultaneously. Subsequently, the pulse of the third scan signal SC3(n) may be applied to the vertically adjacent third pixel PXL3 and fourth pixel PXL4 simultaneously. Subsequently, the pulse of the third scan signal SC3(n + 2) may be applied to the vertically adjacent fifth pixel PXL5 and sixth pixel PXL6 simultaneously.

[0141] The fourth shift register SR4 may include a plurality of stages ST4 connected in cascade with each other. The fourth shift register SR4 may receive a start pulse EVST and clocks ECLK1 and ECLK2, and sequentially output pulses of the EM signal EMn. The clocks ECLK1 and ECLK2 may include two or more shift clocks having different phases. The pulse width of the EM signal EMn may be set to be longer than one horizontal section and applied to the pixels provided in a plurality of pixel rows simultaneously. For example, the pulse of the EM signal EM(n - 2) may be applied to the vertically adjacent first pixel PXL1 and second pixel PXL2 simultaneously. Subsequently, the pulse of the EM signal EM(n) may be applied to the vertically adjacent third pixel PXL3 and fourth pixel PXL4 simultaneously. Subsequently, the pulse of the EM signal EM(n + 2) may be applied to the vertically adjacent fifth pixel PXL5 and sixth pixel PXL6 simultaneously.

[0142] Figure 6A and Figure 6B The pixel circuit shown requires five gate signals SC1n, SC1n - i, SC2n, SC3n, and EMn. As Figure 8As shown, since the present disclosure uses four shift registers SR1, SR2, SR3, and SR4 to output gate signals SC1n, SC1n-i, SC2n, SC3n, and EMn, the size of the circuit of the gate driver can be reduced.

[0143] Figure 10 is a flowchart showing a method of driving a display device according to an embodiment of the present specification.

[0144] Referring to Figure 10 , the method of driving a display device may include sensing a gate-on voltage of a J-th clock signal input to a J-th stage (e.g., operation S1).

[0145] The method of driving a display device may include an operation in which a difference occurs between the sensed gate-on voltage of the J-th clock signal and the gate-on voltage of a first clock signal (e.g., operation S2).

[0146] The method of driving a display device may include applying a compensated gate-on voltage, which is a gate-on voltage applied to a gate-on voltage node, and whose voltage level changes based on the gate-on voltage of the J-th clock signal and the gate-on voltage of a clock signal input from a clock generation circuit (e.g., operation S3).

[0147] Figure 11 is a view schematically showing a shift register of a gate driver according to an embodiment of the present specification.

[0148] Referring to Figure 11 , the gate driver may include one or more shift registers. The shift register may be implemented as a known shift register circuit for driving a display panel. The shift register may include a plurality of stages ST1 to STn connected in cascade with each other. The stages ST1 to STn may be GIP elements formed using an in-panel gate (GIP) method. A stage may be interpreted as a signal transmission part of the shift register.

[0149] Except for the uppermost stage ST1, the remaining stages ST2 to STn are basically the same in configuration and connection relationship as the uppermost stage ST1, except that they receive a carry signal CAR instead of an external start signal VST and output gate signals GOUT1 to GOUTn with different phases. Except for the uppermost stage ST1, the remaining stages ST2 to STn are basically the same in configuration and connection relationship with each other, except that they receive clock signals with different phases and output gate signals GOUT2 to GOUTn with different phases.

[0150] Each in the stage may include a CLK node to which clocks CLK1 to CLK4 are input, a VST node to which a start pulse VST or a carry signal CAR from a previous stage is input, a first control node Q, a second control node QB, an output node nO, and a buffer BUF that outputs a pulse of a gate signal by charging / discharging the output node nO in response to voltages at the control nodes Q and QB. The "previous stage" refers to a stage that generates a gate signal having an earlier phase than the gate signal output from the reference stage.

[0151] The operation of the topmost stage ST1 can be activated according to an external start signal, and the operations of the second topmost stage ST2 to the bottommost stage STn can be activated according to the carry signal CAR from the previous stage. The carry signal CAR can become an interval start signal for the gate signal GOUT of the previous stage.

[0152] The phases of clocks CLK1 to CLK4 can be sequentially shifted. Each stage ST can receive one or more clocks. As shown, each in the stage ST receives two clocks, but it is not limited thereto.

[0153] In the illustrated embodiment, the CLK node of each in the stage ST can be connected to a clock line provided in the non-display area of the display panel to receive clocks CLK1 to CLK4. However, each in the stage ST is not limited to the illustrated embodiment and can receive clocks CLK1 to CLK4 through a clock line provided in the display area.

[0154] The first stage ST can receive the first clock CLK1 and the second clock CLK2 and a start pulse, and output a pulse of the gate signal GOUT1 and a pulse of the carry signal CAR. The second stage ST can receive the second clock CLK2 and the third clock CLK3 and a pulse of the first carry signal CAR, and output a pulse of the second gate signal GOUT2 and a pulse of the second carry signal CAR.

[0155] The nth stage ST can receive the first clock CLK1 and the fourth clock CLK4 and a pulse of the (n - 1)th carry signal CAR from the (n - 1)th stage, and output a pulse of the nth gate signal GOUTn and a pulse of the nth carry signal CAR (n is a natural number).

[0156] The buffer BUF may include a first buffer transistor Tu controlled according to the voltage at the first control node Q and a second buffer transistor Td controlled according to the voltage at the second control node QB.

[0157] The first buffer transistor Tu can be turned on according to the voltage at the first control node Q to charge the voltage at the output node nO to the gate-on voltage Von. The first buffer transistor Tu can include a gate electrode connected to the first control node Q, a first electrode to which the gate-on voltage Von is applied, and a second electrode connected to the output node nO.

[0158] The second buffer transistor Td can be turned on according to the voltage at the second control node QB to supply the gate-off voltage Voff to the output node nO. The second buffer transistor Td can include a gate electrode connected to the second control node QB, a first electrode connected to the output node nO, and a second electrode to which the gate-off voltage Voff is applied.

[0159] As will be described below, the output node nO can include a first output node that outputs pulses of the output gate signals GOUT1 to GOUTn and a second output node that outputs pulses of the carry signal CAR.

[0160] Figure 12 is specifically shown Figure 11 The circuit diagram of the nth stage circuit shown. Figure 11 Each of the stages ST1 to STn shown is Figure 12 substantially the same as the circuit of the nth stage STn shown.

[0161] Referring to Figure 12 , the nth stage circuit can include a plurality of transistors T1 to T7, a plurality of capacitors C3 to C5, and nodes connecting the transistors and the capacitors.

[0162] Each of the first transistor T1 to the seventh transistor T7 can include a p-channel TFT. The p-channel TFT can be turned on in response to Figure 13 the gate low voltage VGL shown and turned off in response to the gate high voltage VGH. In the case of a p-channel transistor, the gate-on voltage can be the gate low voltage VGL, and the gate-off voltage can be the gate high voltage VGH.

[0163] The stage circuit can include: a CLK node nCLK to which the clock signal CLK is input, a VST node nVST to which the start signal or the carry signal VST / CAR from the previous stage is input, a first control node nQ, a second control node nQB, an output node nO through which the output gate signal GOUT and / or the carry signal are output, a gate-on voltage node (hereinafter referred to as the "VGL node") to which the gate-on voltage VGL is applied, a gate-off voltage node (hereinafter referred to as the "VGH node") to which the gate-off voltage VGH is applied, etc.

[0164] The gate turn-on voltage VGL applied to the VGL node may be a first constant voltage. The gate turn-on voltage VGL applied to the VGL node may be a voltage that swings between a gate high voltage and a gate low voltage. The gate turn-off voltage VGH applied to the VGH node may be a second constant voltage.

[0165] Hereinafter, "activating" a specific node means that a gate turn-on voltage or a voltage similar thereto can be applied to the node. Hereinafter, "deactivating" a specific node means that a gate turn-off voltage or a voltage similar thereto can be applied to the node.

[0166] The stage circuit may include a Q control unit, a QB control unit, an output unit, and a first stabilization unit.

[0167] The Q control unit may include a first transistor T1. The first transistor T1 may activate the QC node nQC by applying a start signal VST / CAR at the gate turn-on voltage to the QC node nQC according to the clock signal CLK. The gate electrode of the first transistor T1 may be connected to the CLK node nCLK, and the first electrode and the second electrode of the first transistor T1 may be connected to the VST node nVST and the QC node nQC, respectively.

[0168] The QB control unit may activate a second control node nQB opposite to the QC node nQC according to the clock signal CLK, the start signal VST / CAR, and the potential of the QC node nQC. The QB control unit may include a fifth capacitor C5, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fourth capacitor C4.

[0169] The fifth capacitor C5 may be connected between the CLK node nCLK and the QD node nQD. The third transistor T3 may supply the clock signal CLK to the second control node nQB according to the potential of the QD node nQD. The gate electrode of the third transistor T3 may be connected to the QD node nQD, and the first electrode and the second electrode of the third transistor T3 may be connected to the CLK node nCLK and the second control node nQB, respectively.

[0170] The second transistor T2 may supply a gate turn-off voltage to the QD node nQD according to the start signal VST / CAR. The gate electrode of the second transistor T2 may be connected to the VST node nVST, and the first electrode and the second electrode of the second transistor T2 may be connected to the QD node nQD and the VGH node nVGH, respectively. When the start signal VST / CAR is held at the gate turn-off voltage, the potential of the QD node nQD may be synchronized with the clock signal CLK. When the start signal VST / CAR is held at the gate turn-on voltage, the potential of the QD node nQD may become the gate turn-off voltage.

[0171] The fourth transistor T4 can provide a gate-off voltage to the second control node nQB according to the potential of the QC node nQC. The gate electrode of the fourth transistor T4 can be connected to the QC node nQC, and the first and second electrodes of the fourth transistor T4 can be connected to the second control node nQB and the VGH node nVGH, respectively.

[0172] The fourth capacitor C4 can be connected between the second control node nQB and the VGH node nVGH to stabilize the potential of the second control node nQB.

[0173] The output unit can include a sixth transistor T6 as a pull-down element, a seventh transistor T7 as a pull-up element, and a third capacitor C3.

[0174] The sixth transistor T6 can provide a gate signal GOUT at the gate-on voltage VGL to the output node nO from the time when it is bootstrapped synchronously with the activation timing of the first control node nQ and the QC node nQC. The gate electrode of the sixth transistor T6 can be connected to the first control node nQ, and the first and second electrodes of the sixth transistor T6 can be connected to the VGL node nVGL and the output node nO, respectively.

[0175] The third capacitor C3 can be connected between the first control node nQ and the output node nO. The third capacitor C3 is used to bootstrap the first control node nQ by reflecting the change in the potential of the output node nO to the potential of the first control node nQ when the gate signal GOUT changes from the gate-off voltage to the gate-on voltage.

[0176] The seventh transistor T7 can provide a gate signal GOUT of the gate-off voltage VGH to the output node nO from the time when the second control node nQB is activated. The gate electrode of the seventh transistor T7 can be connected to the second control node nQB, and the first and second electrodes of the seventh transistor T7 can be connected to the output node nO and the VGH node nVGH, respectively.

[0177] The first stabilization unit can include a fifth transistor T5. The gate electrode of the fifth transistor T5 can be connected to the VGL node nVGL, and the first and second electrodes of the fifth transistor T5 can be connected to the QC node nQC and the first control node nQ, respectively. When the first control node nQ is bootstrapped, the channel current between the first and second electrodes of the fifth transistor T5 can become zero. When the first control node nQ is bootstrapped, the fifth transistor T5 can be turned off, thereby blocking the electrical connection between the QC node nQC and the first control node nQ. When the first control node nQ is not bootstrapped, the fifth transistor T5 can remain in the conducting state.

[0178] The fifth transistor T5 can remain in the conducting state and can be turned off only when the first control node nQ is bootstrapped, thereby preventing current from flowing between the QC node nQC and the first control node nQ. When the first control node nQ is bootstrapped, the potential of the QC node nQC can be different from the potential of the first control node nQ. Since the potential of the QC node nQC does not change even when the potential of the first control node nQ changes at the bootstrapping moment, the first transistor T1 and the fourth transistor T4 connected to the QC node nQC can avoid overloading at the bootstrapping moment.

[0179] When the fifth transistor T5 is absent, the drain-source voltage Vds of the first transistor T1 and the gate-source voltage Vgs of the fourth transistor T4 may increase to a critical value or more due to bootstrapping, and when such an overloading phenomenon occurs continuously, an element breakdown phenomenon, i.e., a so-called breakdown phenomenon, may occur. The fifth transistor T5 can prevent the breakdown of the first transistor T1 and the fourth transistor T4 connected to the QC node nQC at the bootstrapping moment of the first control node nQ.

[0180] Figure 13 is a waveform diagram showing Figure 12 the input and output waveforms of the circuit shown. Figure 14 is a table showing Figure 13 the operations of the stages corresponding to sections A to F of Figures 15A to 15F is a circuit diagram showing Figure 13 the operating states of the stages corresponding to sections A to F of . Hereinafter, it will be described on the assumption that the stage circuit receives one clock input, but this specification is not limited thereto, and appropriate modifications can be made within the scope of substantially the same technical spirit according to those skilled in the art.

[0181] In Figure 14 , the potential "low" can refer to the gate conduction voltage, the potential "high" can refer to the gate turn-off voltage, and the potential "very low" can refer to the boosted voltage VGL` / VEL` that is lower than the gate conduction voltage.

[0182] When the QC node nQC is deactivated and the second control node nQB is activated, a gate signal of the gate turn-off voltage VGH can be output from the corresponding stage.

[0183] When the QC node nQC is activated and the second control node nQB is deactivated, a gate signal of the gate conduction voltage VGL can be output from the corresponding stage.

[0184] The stage can output a gate signal at the gate conduction voltage VGL from the time when the stage is bootstrapped synchronously with the activation timing of the first control node nQ and the QC node nQC.

[0185] Referring to Figure 13, Figure 14 and Figure 15A , in section A, a clock signal CLK at a gate-off voltage can be input, and a start signal VST / CAR at a gate-on voltage can be input.

[0186] The operation of section A is the same as that of section F to be described below, except that the first transistor T1 can be turned off according to the clock signal CLK at the gate-off voltage.

[0187] Since the QC node nQC remains at the gate-on voltage in section F even when the first transistor T1 is turned off, the gate signal GOUT of the gate-on voltage VGL can be output to the output node nO.

[0188] Referring to Figure 13 , Figure 14 and Figure 15B , in section B, a start signal VST / CAR at a gate-off voltage and a clock signal CLK can be input. The first transistor T1 can be turned off according to the clock signal CLK at the gate-off voltage, and the second transistor T2 can be turned off according to the start signal VST / CAR at the gate-off voltage. The third transistor T3 can be turned off according to the gate-off voltage at the QD node nQD.

[0189] The QC node nQC can be maintained at the gate-on voltage of the previous frame, and the first control node nQ can be maintained at the boosted voltage VGL` of the previous frame. The boosted voltage VGL` / VEL` can be lower than the gate-on voltage, but is not limited thereto.

[0190] According to the boosted voltage VGL` / VEL` of the first control node nQ, the sixth transistor T6 can be turned on, and the gate signal GOUT of the gate-on voltage VGL can be output to the output node nO.

[0191] Due to the bootstrap of the first control node nQ, no channel current flows through the fifth transistor T5, and the fifth transistor T5 can be substantially turned off.

[0192] Referring to Figure 13 , Figure 14 and Figure 15C , in section C, a start signal VST / CAR at a gate-off voltage can be input, and a clock signal CLK at a gate-on voltage can be input for a predetermined time. The first transistor T1 can be turned on according to the clock signal CLK at the gate-on voltage, and the second transistor T2 can remain off according to the start signal VST / CAR at the gate-off voltage.

[0193] The QD node nQD can be coupled to a clock signal CLK at a gate-on voltage and change to the gate-on voltage to turn on the third transistor T3.

[0194] A start signal VST / CAR at a gate-off voltage can be applied to the QC node nQC through the first transistor T1. The gate-off voltage at the QC node nQC can be applied to the first control node nQ through the fifth transistor T5 to turn off the sixth transistor T6.

[0195] The fourth transistor T4 can be turned off according to the gate-off voltage at the QC node nQC, and the clock signal CLK at the gate-on voltage can be applied to the second control node nQB through the third transistor T3. Therefore, the seventh transistor T7 can be turned on according to the gate-on voltage of the second control node nQB to output a gate signal GOUT of the gate-off voltage VGH to the output node nO.

[0196] Refer to Figure 13 、 Figure 14 and Figure 15D In section D, a start signal VST / CAR at a gate-off voltage and a clock signal CLK can be input. The first transistor T1 can be turned off according to the clock signal CLK at the gate-off voltage, and the second transistor T2 can remain off according to the start signal VST / CAR at the gate-off voltage. The QD node nQD can be coupled to the clock signal CLK at the gate-off voltage and change to the gate-off voltage to turn off the third transistor T3.

[0197] The QC node nQC is in a floating state to maintain the gate-off voltage in section C. The gate-off voltage at the QC node nQC can be applied to the first control node nQ through the fifth transistor T5 to keep the sixth transistor T6 off.

[0198] The fourth transistor T4 can remain off according to the gate-off voltage of the QC node nQC.

[0199] By turning off the third transistor T3, the second control node nQB can be in a floating state to maintain the gate-on voltage in section C. The seventh transistor T7 can remain on according to the gate-on voltage of the second control node nQB, and thus the gate signal GOUT of the gate-off voltage VGH can be output to the output node nO.

[0200] Refer to Figure 13 、 Figure 14 and Figure 15E, in section E, a clock signal CLK at a gate-off voltage can be input, and a start signal VST / CAR at a gate-on voltage can be input. The first transistor T1 can be turned off according to the clock signal CLK at the gate-off voltage, and the second transistor T2 can be turned on according to the start signal VST / CAR at the gate-on voltage to apply the gate-off voltage to the QD node nQD. The third transistor T3 can be turned off according to the gate-off voltage of the QD node nQD.

[0201] The QC node nQC can be in a floating state to maintain the gate-off voltage. The gate-off voltage at the QC node nQC can be applied to the first control node nQ through the fifth transistor T5 to keep the sixth transistor T6 in the off state.

[0202] The fourth transistor T4 can be kept in the off state according to the gate-off voltage of the QC node nQC. By turning off the third transistor T3, the second control node nQB can be in a floating state to maintain the gate-on voltage.

[0203] The seventh transistor T7 can be kept in the on state according to the gate-on voltage of the second control node nQB, and thus a gate signal GOUT at the gate-off voltage VGH can be output to the output node nO.

[0204] Refer to Figure 13 、 Figure 14 and Figure 15F , in section F, a start signal VST / CAR and a clock signal CLK at the gate-on voltage can be input for a predetermined time. The first transistor T1 can be turned on according to the clock signal CLK at the gate-on voltage to apply the start signal VST / CAR at the gate-on voltage to the QC node nQC.

[0205] The gate-on voltage at the QC node nQC can be applied to the first control node nQ through the fifth transistor T5 to turn on the sixth transistor T6. By turning on the sixth transistor T6, a gate signal GOUT at the gate-on voltage VGL can be output to the output node nO to change the potential of the output node nO from the gate-off voltage to the gate-on voltage. In this case, the change in the potential of the output node nO can be reflected in the first control node nQ through the third capacitor C3, and the potential of the first control node nQ can be bootstrapped from the gate-on voltage to the boosted voltage VGL` / VEL`. When the first control node nQ is bootstrapped to the boosted voltage VGL`, the potential of the output node nO can be changed to the gate-on voltage without delay or distortion. At the same time, when the first control node nQ is bootstrapped, no channel current flows through the fifth transistor T5, and the fifth transistor T5 can be substantially turned off.

[0206] According to the start signal VST / CAR at the gate turn-on voltage, the second transistor T2 can remain in the on state to apply the gate turn-off voltage to the QD node nQD. The third transistor T3 can remain in the off state according to the gate turn-off voltage of the QD node nQD.

[0207] The fourth transistor T4 can be turned on according to the gate turn-on voltage of the QC node nQC to apply the gate turn-off voltage to the second control node nQB. The seventh transistor T7 can be turned off according to the gate turn-off voltage of the second control node nQB.

[0208] Figure 16A and Figure 16B is a waveform diagram showing the changes in the gate turn-on and gate turn-off voltages of the clock signal provided to the shift register.

[0209] Referring to Figure 16A and Figure 16B , the first clock signal CLK(1) to be provided to the topmost stage (hereinafter referred to as the "first stage") of the shift register can be provided. The Jth clock signal CLK(J) to be provided to the second topmost to Nth stages (hereinafter referred to as the "second stage to Nth stage") of the shift register can be provided. J can be a natural number of 2 or more and N or less. The first clock signal CLK(1) and the Jth clock signal CLK(J) are provided through the clock line.

[0210] The first clock signal CLK(1) can swing between the target gate high voltage tVGH and the target gate low voltage tVGL. The target gate high voltage tVGH can be in the range of 6V to 8V, but is not limited thereto. The target gate low voltage tVGL can be in the range of -16V to -11V, but is not limited thereto.

[0211] The Jth clock signal CLK(J) is a clock signal provided to a stage farther from the first clock signal CLK(1), and the load received by this clock signal is relatively large. Due to the increase in the length of the clock line, the increase in the ambient temperature of the display device, the increase in the resistance of the lines of the display panel, or the load caused by the floating capacitance or parasitic resistance, it may not be possible to provide a clock signal at a constant gate high voltage or gate low voltage. According to the difference in the resistance and parasitic capacitance of the clock line, RC delay and / or IR drop may occur.

[0212] For example, the gate turn-on voltage VGL of the clock may not reach the target voltage tVGL of the gate turn-on voltage due to a large voltage drop caused by the RC delay at a position where the resistance and parasitic capacitance of the clock line are large, and the voltage becomes higher than the target voltage. The gate turn-on voltage of the Jth clock signal CLK(J) may be different from the gate turn-on voltage of the first clock signal CLK(1).

[0213] The gate-off voltage VGH of the clock may not reach the target voltage tVGH of the gate-off voltage due to a large voltage drop caused by RC delay at a position where the resistance and parasitic capacitance of the clock line are large, and the voltage becomes lower than the target voltage. The gate-off voltage of the J-th clock signal CLK(J) may be different from the gate-off voltage of the first clock signal CLK(1).

[0214] Since the number of lines is increased by distributing the lines in the gate driver in the display area, the above situation exacerbates the problem.

[0215] The J-th clock signal CLK(J) can swing between the falling gate high voltage dVGH and the falling gate low voltage dVGL. The falling gate high voltage dVGH can be in the range of 4V to 6V, but is not limited thereto. The falling gate low voltage dVGL can be in the range of -14V to -10V, but is not limited thereto.

[0216] Figure 17A is a circuit diagram showing an abnormal output operation state that occurs when a shift gate voltage is supplied to a defective stage. Figure 17B is a circuit diagram showing an abnormal output operation state of a stage that receives a carry signal from a defective stage.

[0217] Refer to Figure 17A and Figure 17B As described above, in section F, the start signal VST / CAR and the clock signal CLK(J) at the gate-on voltage can be input for a predetermined time. The first transistor T1 can be turned on according to the clock signal CLK(J) at the gate-on voltage to apply the start signal VST / CAR at the gate-on voltage to the QC node nQC. Channel current can flow in the fifth transistor T5, and the fifth transistor T5 can be substantially turned on. The gate-on voltage at the QC node nQC can be applied to the first control node nQ through the fifth transistor T5 to turn on the sixth transistor T6.

[0218] As described above, when the load of the clock line increases, the VGL level of the J-th clock signal CLK(J) provided through the CLK node nCLK may increase. A defect may occur in which the first control node nQ is not sufficiently charged due to an increase in the VGL level of the clock signal supplied to the gate electrode of the first transistor T1. The sixth transistor T6 may be in the off state. Therefore, the voltage of section E may be maintained, and the gate signal GOUT at the gate-off voltage VGH may be output to the output node nO. In this case, the gate signal GOUT at the gate-on voltage VGL may not be output to the output node nO, the potential of the output node nO does not change, and the potential of the first control node nQ is not bootstrapped.

[0219] Since a gate signal GOUT at a gate-off voltage is output from a previous stage, a start signal VST / CAR supplied to a next stage has a gate-off voltage VGH. The start signal VST / CAR at the gate-off voltage is input, and a clock signal CLK(J+1) at a gate-on voltage is input. A first transistor T1 may be turned on according to the clock signal CLK(J+1) at the gate-on voltage, and a second transistor T2 may remain in an off state according to the start signal VST / CAR at the gate-off voltage. A QD node nQD may be coupled to the clock signal CLK at the gate-on voltage and change to the gate-on voltage to turn on a third transistor T3. The start signal VST / CAR at the gate-off voltage is applied to a QC node nQC through the first transistor T1. The gate-off voltage at the QC node nQC may be applied to a first control node nQ through a fifth transistor T5 to turn off a sixth transistor T6. A fourth transistor T4 may be turned off according to the gate-off voltage at the QC node nQC, and the clock signal CLK at the gate-on voltage may be applied to a second control node nQB through the third transistor T3. Accordingly, a seventh transistor T7 may be turned on according to the gate-on voltage at the second control node nQB to output the gate signal GOUT at the gate-off voltage VGH to an output node nO.

[0220] As described above, a gate signal at a gate-off voltage is output from a stage that receives a carry signal at a gate-off voltage after a defective stage.

[0221] Figure 18 is a block diagram schematically showing a display device and a gate driver according to an embodiment of the present specification. Figure 19 is a block diagram specifically showing a display device and a gate driver according to an embodiment of the present specification.

[0222] Referring to Figure 18 and Figure 19 , the gate driver may include one or more shift registers. The shift register may include a plurality of stages that are cascaded to each other through a line for a carry signal CAR to receive a clock signal through a line for a clock CLK. The plurality of stages may include a first stage ST(1) to an Nth stage ST(N) (N is a constant, which is a natural number of 2 or more). The shift register may include a Jth stage ST(J). J is a natural number of 2 or more and N or less.

[0223] The first-stage ST(1) can receive a first clock signal and a start signal VST, and output a first gate signal GOUT(1) and a first carry signal CAR(1). The second-stage ST(2) can receive a second clock signal and the first carry signal CAR(1), and output a second gate signal GOUT(2) and a second carry signal CAR(2). The third-stage ST(3) can receive a third clock signal and the second carry signal CAR(2), and output a third gate signal GOUT(3) and a third carry signal CAR(3). The fourth-stage ST(4) can receive a fourth clock signal and the third carry signal CAR(3), and output a fourth gate signal GOUT(4) and a fourth carry signal CAR(4). The Jth-stage ST(J) can receive a Jth clock signal and a (J - 1)th carry signal CAR(J - 1), and output a Jth gate signal GOUT(J) and a Jth carry signal CAR(J). The Nth-stage ST(N) can receive an Nth clock signal and an (N - 1)th carry signal CAR(N - 1), and output an Nth gate signal GOUT(N) and an Nth carry signal CAR(N).

[0224] Each of the stages ST(1) to ST(N) can include a CLK node input with a clock signal, a VST node input with a start pulse VST or a carry signal CAR from a previous stage, a first control node Q, a second control node QB, an output node nO, and a buffer BUF. The buffer BUF is used to output a pulse of the gate signal by charging / discharging the output node nO in response to the voltages at the control nodes Q and QB.

[0225] Each of the stages ST(1) to ST(N) can further include a VGL node to which a gate-on voltage is applied and a VGH node to which a gate-off voltage is applied. The gate-on voltage applied to the VGL node can be a first constant voltage. The gate-on voltage applied to the VGL node can be a voltage that swings between a gate high voltage and a gate low voltage. The gate-off voltage applied to the VGH node can be a second constant voltage.

[0226] The gate signal GOUT at the gate-on voltage can be output through the output node nO, which can be conductively connected to a switching element of a pixel circuit of a gate driver. In an embodiment, the gate-on voltage can be in the range of -16V to -11V.

[0227] The first constant voltage can be applied to the VGL node, and the second constant voltage can be applied to the VGH node. The compensated first constant voltage cVGL provided to each stage can be provided to the gate driver through a line. The second constant voltage VGH provided to each of the stages ST(1) to ST(N) can be provided to the gate driver through a line.

[0228] The first compensation constant voltage cVGL can be applied to the gate driver in real time through a line. When the gate-on voltage of the clock signal input to at least one stage among the second stage ST(2) to the Nth stage ST(N) is different from the gate-on voltage applied from the clock generation circuit, the first compensation constant voltage cVGL can be the gate-on voltage applied to the VGL node. When the gate-on voltage of the clock signal input to the Jth stage ST(J) is different from the gate-on voltage applied from the clock generation circuit, the first compensation constant voltage cVGL can be the gate-on voltage applied to the VGL node.

[0229] The clock generation circuit can include the above-mentioned level shifter.

[0230] In an exemplary embodiment, the Jth stage ST(J) can be the Nth stage ST(N) which is the last stage of the corresponding gate driver. Since the same defect will occur in all subsequent stages even if a defect occurs in any one of the second stage to the (N - 1)th stage, the gate-on voltage of the entire gate driver can be compensated even when sensing the clock signal of the last stage that provides the maximum load for the line for the clock CLK. Additionally, since the gate-on voltage is applied to the entire gate driver through a line, the gate-on voltage of the entire gate driver can be compensated even when sensing the clock signal of the last stage that provides the maximum load for the line for the clock CLK.

[0231] When the gate-on voltage of the Jth clock signal CLK(J) is different from the gate-on voltage of the first clock signal, the gate driver according to this specification can change the voltage level of the gate-on voltage applied to the gate-on voltage node. When the gate-on voltage of the clock signal input to at least one stage among the second stage ST(2) to the Nth stage ST(N) is different from the gate-on voltage applied from the clock generation circuit, the first compensation constant voltage cVGL can be the gate-on voltage applied to the VGL node. When the gate-on voltage of the clock signal input to the Jth stage ST(J) is different from the gate-on voltage applied from the clock generation circuit, the compensation gate-on voltage cVGL can be the gate-on voltage applied to the VGL node.

[0232] The gate driver according to the present specification can compensate for the change in the gate turn-on voltage of the clock signal due to RC delay and / or IR drop, which occurs due to the increase in the length and number of lines. Even when the gate turn-on voltage of the J-th clock signal CLK(J) is different from the gate turn-on voltage of the first clock signal, the gate-source voltage of the sixth transistor can be maintained at the previous voltage. Even when the gate turn-on voltage of the J-th clock signal CLK(J) is different from the gate turn-on voltage of the first clock signal, the gate-source voltage of the sixth transistor can be substantially constant.

[0233] When the gate turn-on voltage of the J-th clock signal CLK(J) is higher than the gate turn-on voltage of the first clock signal, the voltage level of the gate turn-on voltage applied to the gate turn-on voltage node may increase. When the gate turn-on voltage of the clock signal input to the J-th stage ST(J) is higher than the gate turn-on voltage applied from the clock generation circuit, the compensated gate turn-on voltage cVGL can be a gate turn-on voltage with an increased voltage level.

[0234] The display device according to the present specification may include a sensing unit SENSING for sensing the J-th clock signal input to the J-th stage ST(J). The display device according to the present specification may include a compensation unit COMPENSATION for comparing the sensed J-th clock signal with the gate turn-on voltage applied from the clock generation circuit and applying a compensated gate turn-on voltage cVGL reflecting and adding the difference to the gate driver. The compensated gate turn-on voltage cVGL can be a first constant voltage. The compensated gate turn-on voltage cVGL can be a voltage that swings between the gate high voltage and the gate low voltage. When the compensated gate turn-on voltage cVGL is the first constant voltage, an appropriate value for compensating the first constant voltage may be in the range of -12V to -8V, but is not limited thereto.

[0235] Figure 20 is a circuit diagram specifically showing the sensing unit and the compensation unit according to an embodiment of the present specification.

[0236] Referring to Figure 20 , the sensing unit and the compensation unit may include a 1-1 gate turn-on voltage input terminal 310, a 1-2 gate turn-on voltage input terminal 320, and a 1-3 gate turn-on voltage input terminal 330, a second gate turn-on voltage input terminal 400, a first differential amplifier 510, a second differential amplifier 520, a compensated first constant voltage output terminal cVGL, a sensing transistor TS, a plurality of resistors R1 to R10, and a plurality of ground terminals. The ground voltage applied to the ground terminal can be 0V.

[0237] A 1-1 gate conduction voltage and a 1-3 gate conduction voltage that do not reflect increases and / or decreases based on various factors can be input from a power supply unit to a 1-1 gate conduction voltage input terminal 310 and a 1-3 gate conduction voltage input terminal 330. The 1-1 gate conduction voltage and the 1-3 gate conduction voltage can be substantially the same value.

[0238] A 1-2 gate conduction voltage can be input from a clock generation circuit to a 1-2 gate conduction voltage input terminal 320. A second gate conduction voltage changed due to the above reasons, problems, etc. can be input from a J-th stage to a second gate conduction voltage input terminal 400.

[0239] The first differential amplifier 510 and the second differential amplifier 520 can each include a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal.

[0240] The 1-1 gate conduction voltage input terminal 310 can be connected to the inverting input terminal (-) of the first differential amplifier 510. A first resistor R1 can be provided between the inverting input terminal (-) of the first differential amplifier 510 and the 1-1 gate conduction voltage input terminal 310.

[0241] The gate electrode of the sensing transistor TS can be connected to the 1-2 gate conduction voltage input terminal 320. The first electrode and the second electrode of the sensing transistor TS can be connected to the second gate conduction voltage input terminal 400 and the non-inverting input terminal (+) of the first differential amplifier 510, respectively. A second resistor R2 can be provided between the sensing transistor TS and the non-inverting input terminal (+) of the first differential amplifier 510. A sixth capacitor C6 can be connected to a B node nB between the sensing transistor TS and the second resistor R2. The sixth capacitor C6 can be connected to a ground terminal. A third resistor R3 can be provided at a C node nC between the non-inverting input terminal (+) of the first differential amplifier 510 and the second resistor R2. The third resistor R3 can be connected to the ground terminal.

[0242] A fourth resistor R4 can be provided between an A node nA, which is between the inverting input terminal (-) of the first differential amplifier 510 and the first resistor R1, and the output terminal of the first differential amplifier 510.

[0243] The output terminal of the first differential amplifier 510 may be connected to the non-inverting input terminal (+) of the second differential amplifier 520. The eighth resistor R8 may be provided between the output terminal of the first differential amplifier 510 and the non-inverting input terminal (+) of the second differential amplifier 520. The seventh capacitor C7 may be connected to node n① between the output terminal of the first differential amplifier 510 and the eighth resistor R8. The seventh capacitor C7 may be connected to the ground terminal. The ninth resistor R9, the fifth resistor R5, and the 1-3 gate conduction input terminal 330 may be connected in series to node nE between the non-inverting input terminal (+) of the second differential amplifier and the eighth resistor R8. The sixth resistor may be connected to node nD between the ninth resistor R9 and the fifth resistor R5. The sixth resistor may be connected to the ground terminal.

[0244] The inverting input terminal (-) of the second differential amplifier may be connected to the ground terminal, with the seventh resistor R7 therebetween. The output terminal of the second differential amplifier 520 may be connected to the compensated first constant voltage output terminal cVGL. The tenth resistor R10 may be provided between node nF and node n②, where node nF is between the inverting input terminal (-) of the second differential amplifier 520 and the seventh resistor R7, and node n② is between the output terminal of the second differential amplifier 520 and the compensated first constant voltage output terminal cVGL.

[0245] The first differential amplifier 510 may perform the function of subtracting the voltage input from the 1-1 gate conduction voltage input terminal 310 and the voltage input from the second gate conduction voltage input terminal 400. The first differential amplifier 510 may compare the voltages and output the value obtained by subtracting the two voltages. The second differential amplifier 520 may perform the function of adding an appropriate value derived from the value output from the first differential amplifier 510 and an appropriate value derived from the voltage input from the 1-3 gate conduction voltage input terminal 330. The second differential amplifier 520 may add these values and output an appropriate compensated first constant voltage cVGL value.

[0246] Their relationship may be represented by the following relationship:

[0247] [Relationship 1]

[0248] The magnitude of the first resistor = the magnitude of the second resistor = the magnitude of the third resistor = the magnitude of the fourth resistor

[0249] [Relationship 2]

[0250] The potential of node B = the second gate conduction voltage

[0251] [Relationship 3]

[0252] Potential of Node C = Potential of Node A = 1 / 2 × Second Gate Conduction Voltage

[0253] [Relationship 4]

[0254] Gate Conduction Voltage - 1 / 2 × Second Gate Conduction Voltage = 1 / 2 × Second Gate Conduction Voltage - Potential of Node ①

[0255] [Relationship 5]

[0256] Potential of Node = 1 - 1 Gate Conduction Voltage - Second Gate Conduction Voltage

[0257] [Relationship 6]

[0258] Size of Seventh Resistor = Size of Eighth Resistor = Size of Ninth Resistor = Size of Tenth Resistor

[0259] [Relationship 7]

[0260] When k = Size of Sixth Resistor / (Size of Fifth Resistor + Size of Sixth Resistor), Potential of Node D = k × 1 - 3 Gate Conduction Voltage

[0261] [Relationship 8]

[0262] When k = Size of Sixth Resistor / (Size of Fifth Resistor + Size of Sixth Resistor), Potential of Node E = Potential of Node F = 1 / 2 × (k × 1 - 3 Gate Conduction Voltage + Potential of Node ①)

[0263] [Relationship 9]

[0264] When k = Size of Sixth Resistor / (Size of Fifth Resistor + Size of Sixth Resistor), (0 - 1 / 2 × (k × 1 - 3 Gate Conduction Voltage + Potential of Node ①)) = (1 / 2 × (k × 1 - 3 Gate Conduction Voltage + Potential of Node ①) - Potential of Node ②)

[0265] [Relationship 10]

[0266] Potential of Node = k × 1 - 3 Gate Conduction Voltage + Potential of Node ①

[0267] In Relationships 1 to 10, the sizes of the First Resistor to the Tenth Resistor represent the sizes of the First Resistor R1, the Second Resistor R2, the Third Resistor R3, the Fourth Resistor R4, the Fifth Resistor R5, the Sixth Resistor R6, the Seventh Resistor R7, the Eighth Resistor R8, the Ninth Resistor R9, and the Tenth Resistor R10. k represents the parameter used to organize the relationships.

[0268] Figure 21It is a block diagram specifically showing a display device and a gate driver according to another embodiment of the present specification. Components that perform substantially the same functions between the embodiments are denoted by the same reference numerals, and repeated descriptions thereof will be omitted.

[0269] Referring to Figure 21 , a first constant voltage cVGL can be applied to the gate driver in real time through a line, and the difference between the gate-on voltage of the clock signal input to at least two or more stages among the second stage ST(2) to the Nth stage ST(N) and the gate-on voltage applied from the power supply unit is reflected in the first constant voltage cVGL.

[0270] The gate driver according to the present specification can compensate for the change in the gate-on voltage caused by RC delay and / or IR drop, which occurs due to the increase in the length and number of lines. The display device according to the present specification may include a sensing unit SENSING for sensing the gate-on voltage of the clock signal input to two or more stages among the second stage ST(2) to the Nth stage ST(N). The display device according to the present specification may include a compensation unit COMPENSATION for comparing the sensed clock signal with the gate-on voltage applied from the power supply unit and applying a compensated gate-on voltage cVGL that reflects and adds the difference to the gate driver. The compensated gate-on voltage cVGL may be a first constant voltage. The compensated gate-on voltage cVGL may be a voltage that swings between the gate high voltage and the gate low voltage. When the compensated gate-on voltage cVGL is the first constant voltage, an appropriate value for compensating the first constant voltage may be in the range of -12V to -8V, but is not limited thereto.

[0271] Figure 22 It is a single-stage circuit included in the gate driver according to the first embodiment of the present specification. Components that perform substantially the same functions as those in the above embodiments are denoted by the same reference numerals, and repeated descriptions thereof will be omitted.

[0272] Referring to Figure 22 , the stage circuit includes a CLK node nCLK to which the Jth clock signal CLK(J) is input, a VST node nVST to which a carry signal CAR from the previous stage is input, and a VGL node nVGL to which the gate-on voltage cVGL is applied. In a shift register including the first stage to the Nth stage, J is a positive integer of 2 or more and N or less.

[0273] In the gate driver according to the first embodiment of the present specification, the difference between the gate-on voltage of the clock signal input to at least one stage among the second stage to the Nth stage and the gate-on voltage applied from the power supply unit can be reflected, and the reflected value can be applied to the gate driver in real time through a line. The sensing unit can be electrically connected to the CLK node nCLK to receive the Jth clock signal CLK(J) having a gate-on voltage changed due to the above reasons and problems. The compensated gate-on voltage cVGL compensated by the compensation unit based on the voltage sensed by the sensing unit can be provided to the VGL node nVGL.

[0274] Figure 23 is a single-stage circuit included in the gate driver according to the second embodiment of the present specification. The second embodiment is different from the first embodiment in the number of transistors, the position where the compensated gate-on voltage is applied, and the signals input to the transistors. Components that perform substantially the same functions as those in the above embodiments are denoted by the same reference numerals, and repeated descriptions thereof will be omitted.

[0275] Referring to Figure 23 , the stage circuit may include a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and nodes connecting these transistors.

[0276] The stage circuit may include a CLK node nCLK to which the Jth clock signal CLK(J) is input, a VST node nVST to which a carry signal CAR from a previous stage is input, a VGL node nVGL to which the compensated gate-on voltage cVGL is applied, a first output node nO1 through which a pulse of the gate signal GOUT is output, and a second output node nO2 through which a pulse of the carry signal CAR is output. In a shift register including the first stage to the Nth stage, J is a positive integer of 2 or more and N or less.

[0277] The output unit may include a sixth transistor T6 and an eighth transistor T8 as pull-down elements, a seventh transistor T7 and a ninth transistor T9 as pull-up elements, and a third capacitor C3.

[0278] The sixth transistor T6 may provide the gate signal GOUT at the gate-on voltage VGL to the first output node nO1 from when the bootstrap is synchronized with the activation timing of the first control node nQ and the QC node nQC. The gate electrode of the sixth transistor T6 may be connected to the first control node nQ, and the first electrode and the second electrode of the sixth transistor T6 may be connected to the DC voltage input terminal DC and the first output node nO1, respectively. The gate-on voltage may be input to the DC voltage input terminal DC from the power supply unit. The gate-on voltage may be in the range of -16V to -11V, but is not limited thereto.

[0279] The gate electrode of the eighth transistor T8 may be connected to the first control node nQ, and the first and second electrodes of the eighth transistor T8 may be connected to the VGL node nVGL and the second output node nO2, respectively. The eighth transistor T8 may be disposed between the VGL node nVGL and the second output node nO2.

[0280] The third capacitor C3 may be connected between the first control node nQ and the first output node nO1. The third capacitor C3 is used to bootstrap the first control node nQ by reflecting the change in the potential of the first output node nO1 to the potential of the first control node nQ when the gate signal GOUT changes from the gate-off voltage to the gate-on voltage.

[0281] The seventh transistor T7 may supply the gate signal GOUT at the gate-off voltage VGH to the output node nO1 from when the second control node nQB is activated. The gate electrode of the seventh transistor T7 may be connected to the second control node nQB, and the first and second electrodes of the seventh transistor T7 may be connected to the first output node nO1 and the VGH node nVGH, respectively.

[0282] The ninth transistor T9 may supply the gate signal GOUT at the gate-off voltage VGH to the second output node nO2 when the second control node nQB is activated. The gate electrode of the ninth transistor T9 may be connected to the second control node nQB, and the first and second electrodes of the ninth transistor T9 may be connected to the second output node nO2 and the VGH node nVGH, respectively. The ninth transistor T9 may be disposed between the VGH node nVGH and the second output node nO2.

[0283] The first stabilization unit may include a fifth transistor T5. The gate electrode of the fifth transistor T5 may be connected to the VGL node nVGL, and the first and second electrodes of the fifth transistor T5 may be connected to the QC node nQC and the first control node nQ, respectively. When the first control node nQ is bootstrapped, the channel current between the first and second electrodes of the fifth transistor T5 may become zero. When the first control node nQ is bootstrapped, the fifth transistor T5 may be turned off, thereby blocking the electrical connection between the QC node nQC and the first control node nQ. When the first control node nQ is not bootstrapped, the fifth transistor T5 may remain in the conducting state.

[0284] In the gate driver according to the second embodiment of the present specification, the difference between the gate-on voltage of the clock signal input to at least one of the second stage to the Nth stage and the gate-on voltage applied from the power supply unit can be reflected, and the reflected value can be applied to the gate driver in real time through a line. The sensing unit can be electrically connected to the CLK node nCLK to receive the Jth clock signal CLK(J) having a gate-on voltage changed due to the above reasons and problems. The compensated gate-on voltage cVGL compensated by the compensation unit based on the voltage sensed by the sensing unit can be provided to the VGL node nVGL.

[0285] Figure 24 is a single-stage circuit included in the gate driver according to the third embodiment of the present specification. The third embodiment is different from the above embodiments in the number of transistors, the position where the compensated gate-on voltage is applied, and the signal input to the transistors. Components that perform substantially the same functions as those in the above embodiments are denoted by the same reference numerals, and repeated descriptions thereof will be omitted.

[0286] Referring to Figure 24 , the stage circuit may include a first transistor T1, a second transistor T2, a sixth transistor T6, a tenth transistor T10, an eleventh transistor T11, and nodes connecting these transistors.

[0287] The stage circuit may include a CLK node nCLK to which the Jth clock signal CLK(J) is input, a VST node nVST to which a carry signal CAR from the previous stage is input, a QE node nQE to which a compensated gate-on voltage cVGL or a second gate-off voltage VGH is applied according to the carry signal CAR of the previous stage and / or the (J - 1)QB signal of the QB node, a VGL node nVGL to which the compensated gate-on voltage cVGL is applied, a first VGH node nVGH_1 to which the first gate-off voltage VGH is applied, and a second VGH node nVGH_2 to which the second gate-off voltage VGH is applied. In a shift register including the first stage to the Nth stage, J is a positive integer less than or equal to 2 and less than or equal to N.

[0288] The Q control unit may include a first transistor T1. The first transistor T1 can activate the QC node nQC by applying a compensated gate-on voltage cVGL or a second gate-off voltage VGH to the QC node nQC according to the Jth clock signal CLK(J). The gate electrode of the first transistor T1 may be connected to the CLK node nCLK, and the first electrode and the second electrode of the first transistor T1 may be connected to the QE node nQE and the QC node nQC, respectively.

[0289] The QB control unit can activate the second control node nQB opposite to the QC node nQC according to the clock signal CLK, the start signal VST / CAR, and the potential of the QC node nQC. The QB control unit can include a fifth capacitor C5, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fourth capacitor C4.

[0290] The fifth capacitor C5 can be connected between the CLK node nCLK and the QD node nQD. The third transistor T3 can supply the clock signal CLK to the second control node nQB according to the potential of the QD node nQD. The gate electrode of the third transistor T3 can be connected to the QD node nQD, and the first and second electrodes of the third transistor T3 can be connected to the CLK node nCLK and the second control node nQB respectively.

[0291] The second transistor T2 can supply the gate-off voltage to the QD node nQD according to the compensation gate conduction voltage cVGL or the second gate-off voltage VGH. The gate electrode of the second transistor T2 can be connected to the QE node nQE, and the first and second electrodes of the second transistor T2 can be connected to the QD node nQD and the first VGH node nVGH_1 respectively. When the QE node nQE is held at the gate-off voltage, the potential of the QD node nQD can be synchronized with the clock signal CLK. When the QE node nQE is held at the compensation gate conduction voltage cVGL, the potential of the QD node nQD can become the gate-off voltage.

[0292] The fourth transistor T4 can supply the gate-off voltage to the second control node nQB according to the potential of the QC node nQC. The gate electrode of the fourth transistor T4 can be connected to the QC node nQC, and the first and second electrodes of the fourth transistor T4 can be connected to the second control node nQB and the VGH node nVGH respectively.

[0293] The fourth capacitor C4 can be connected between the second control node nQB and the VGH node nVGH to stabilize the potential of the second control node nQB.

[0294] The output unit can include a sixth transistor T6 as a pull-down element, a seventh transistor T7 as a pull-up element, and a third capacitor C3.

[0295] The sixth transistor T6 can supply a gate signal GOUT at a gate-on voltage VGL to the output node nO from when the sixth transistor T6 is bootstrapped synchronously with the activation timing of the first control node nQ and the QC node nQC. The gate electrode of the sixth transistor T6 can be connected to the first control node nQ, and the first electrode and the second electrode of the sixth transistor T6 can be connected to the DC voltage input terminal DC and the output node nO, respectively. The gate-on voltage can be input from a power supply unit to the DC voltage input terminal DC. The gate-on voltage can be in the range of -16V to -11V, but is not limited thereto.

[0296] The third capacitor C3 can be connected between the first control node nQ and the output node nO. The third capacitor C3 is used to bootstrap the first control node nQ by reflecting the change in the potential of the output node nO to the potential of the first control node nQ when the gate signal GOUT changes from a gate-off voltage to a gate-on voltage.

[0297] The seventh transistor T7 can supply a gate signal GOUT at a gate-off voltage VGH to the output node nO from when the second control node nQB is activated. The gate electrode of the seventh transistor T7 can be connected to the second control node nQB, and the first electrode and the second electrode of the seventh transistor T7 can be connected to the output node nO and the first VGH node nVGH_1, respectively.

[0298] The first stabilization unit can include a fifth transistor T5. The gate electrode of the fifth transistor T5 can be connected to the VGL node nVGL, and the first electrode and the second electrode of the fifth transistor T5 can be connected to the QC node nQC and the first control node nQ, respectively. When the first control node nQ is bootstrapped, the channel current between the first electrode and the second electrode of the fifth transistor T5 can become zero. When the first control node nQ is bootstrapped, the fifth transistor T5 can be turned off, thereby blocking the electrical connection between the QC node nQC and the first control node nQ. When the first control node nQ is not bootstrapped, the fifth transistor T5 can remain in the conducting state.

[0299] The gate electrode of the tenth transistor T10 can be connected to the VST node nVST, and the first electrode and the second electrode of the tenth transistor T10 can be connected to the VGL node nVGL and the QE node nQE, respectively.

[0300] The gate electrode of the eleventh transistor T11 can be connected to the previous-stage QB node signal input terminal (J-1)QB, and the first electrode and the second electrode of the eleventh transistor T11 can be connected to the second VGH node nVGH_2 and the QE node nQE, respectively.

[0301] In the gate driver according to the third embodiment of the present specification, the difference between the gate-on voltage of the clock signal input to at least one stage among the second stage to the Nth stage and the gate-on voltage applied from the power supply unit can be reflected, and the reflected value can be applied to the gate driver in real time through a line. The sensing unit can be electrically connected to the CLK node nCLK to receive the Jth clock signal CLK(J) having a gate-on voltage changed due to the above reasons and problems. The compensated gate-on voltage cVGL compensated by the compensation unit based on the voltage sensed by the sensing unit can be provided to the VGL node nVGL.

[0302] Figure 25 is a single-stage circuit included in the gate driver according to the fourth embodiment of the present specification. The fourth embodiment is different from the above embodiment in the number of transistors, the position where the compensated gate-on voltage is applied, and the signal input to the transistors. Components that perform substantially the same functions as those in the above embodiment are denoted by the same reference numerals, and repeated descriptions thereof will be omitted.

[0303] Referring to Figure 25 , the stage circuit may include a twelfth transistor T12, a thirteenth transistor T13, and a node connecting these transistors.

[0304] The stage circuit may include a CLK node nCLK to which the Jth clock signal CLK(J) is input, a VST node nVST to which a carry signal CAR from a previous stage is input, a QE node nQE to which a compensated gate-on voltage cVGL or a second gate-off voltage VGH is applied according to the carry signal CAR and / or the inverted carry signal CARB, a VGL node nVGL to which the compensated gate-on voltage cVGL is applied, a first VGH node nVGH_1 to which a first gate-off voltage VGH is applied, and a second VGH node nVGH_2 to which a second gate-off voltage VGH is applied. In a shift register including the first stage to the Nth stage, J is a positive integer of 2 or more and N or less.

[0305] The stage circuit may further include an inverting circuit for generating an inverted carry signal CARB. The phase of the inverted carry signal CARB may be substantially the same as the phase of the signal at the QB node of the previous stage.

[0306] The Q control unit may include a first transistor T1. The first transistor T1 may activate the QC node nQC by applying a compensated gate-on voltage cVGL or a second gate-off voltage VGH to the QC node nQC according to the Jth clock signal CLK(J). The gate electrode of the first transistor T1 may be connected to the CLK node nCLK, and the first electrode and the second electrode of the first transistor T1 may be connected to the QE node nQE and the QC node nQC, respectively.

[0307] The QB control unit can activate a second control node nQB opposite to the QC node nQC according to a clock signal CLK, a start signal VST / CAR, and the potential of the QC node nQC. The QB control unit can include a fifth capacitor C5, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fourth capacitor C4.

[0308] The fifth capacitor C5 can be connected between the CLK node nCLK and the QD node nQD. The third transistor T3 can supply the clock signal CLK to the second control node nQB according to the potential of the QD node nQD. The gate electrode of the third transistor T3 can be connected to the QD node nQD, and the first electrode and the second electrode of the third transistor T3 can be respectively connected to the CLK node nCLK and the second control node nQB.

[0309] The second transistor T2 can supply a gate-off voltage to the QD node nQD according to a compensation gate conduction voltage cVGL or a second gate-off voltage VGH. The gate electrode of the second transistor T2 can be connected to the QE node nQE, and the first electrode and the second electrode of the second transistor T2 can be respectively connected to the QD node nQD and the first VGH node nVGH_1. When the QE node nQE is held at the gate-off voltage, the potential of the QD node nQD can be synchronized with the clock signal CLK. When the QE node nQE is held at the compensation gate conduction voltage cVGL, the potential of the QD node nQD can become the gate-off voltage.

[0310] The fourth transistor T4 can supply a gate-off voltage to the second control node nQB according to the potential of the QC node nQC. The gate electrode of the fourth transistor T4 can be connected to the QC node nQC, and the first electrode and the second electrode of the fourth transistor T4 can be respectively connected to the second control node nQB and the VGH node nVGH.

[0311] The fourth capacitor C4 can be connected between the second control node nQB and the VGH node nVGH to stabilize the potential of the second control node nQB.

[0312] The output unit can include a sixth transistor T6 as a pull-down element, a seventh transistor T7 as a pull-up element, and a third capacitor C3.

[0313] The sixth transistor T6 can provide a gate signal GOUT at a gate-on voltage VGL to the output node nO starting from when the sixth transistor T6 is bootstrapped synchronously with the activation timing of the first control node nQ and the QC node nQC. The gate electrode of the sixth transistor T6 can be connected to the first control node nQ, and the first and second electrodes of the sixth transistor T6 can be connected to the DC voltage input terminal DC and the output node nO, respectively. The gate-on voltage can be input from a power supply unit to the DC voltage input terminal DC. The gate-on voltage can be in the range of -16V to -11V, but is not limited thereto.

[0314] The third capacitor C3 can be connected between the first control node nQ and the output node nO. The third capacitor C3 is used to bootstrap the first control node nQ by reflecting the change in the potential of the output node nO to the potential of the first control node nQ when the gate signal GOUT changes from a gate-off voltage to a gate-on voltage.

[0315] The seventh transistor T7 can provide a gate signal GOUT at a gate-off voltage VGH to the output node nO starting from when the second control node nQB is activated. The gate electrode of the seventh transistor T7 can be connected to the second control node nQB, and the first and second electrodes of the seventh transistor T7 can be connected to the output node nO and the first VGH node nVGH_1, respectively.

[0316] The first stabilization unit can include a fifth transistor T5. The gate electrode of the fifth transistor T5 can be connected to the VGL node nVGL, and the first and second electrodes of the fifth transistor T5 can be connected to the QC node nQC and the first control node nQ, respectively. When the first control node nQ is bootstrapped, the channel current between the first and second electrodes of the fifth transistor T5 can become zero. When the first control node nQ is bootstrapped, the fifth transistor T5 can be turned off, thereby blocking the electrical connection between the QC node nQC and the first control node nQ. When the first control node nQ is not bootstrapped, the fifth transistor T5 can remain in the on state.

[0317] The gate electrode of the twelfth transistor T12 can be connected to the VST node nVST, and the first and second electrodes of the twelfth transistor T12 can be connected to the VGL node nVGL and the QE node nQE, respectively. The twelfth transistor T12 can have substantially the same connection relationship as the tenth transistor.

[0318] The gate electrode of the thirteenth transistor T13 can be connected to the inverted carry signal input terminal CARB, and the first and second electrodes of the thirteenth transistor T13 can be connected to the second VGH node nVGH_2 and the QE node nQE, respectively.

[0319] In the gate driver according to the fourth embodiment of the present specification, the difference between the gate-on voltage of the clock signal input to at least one of the second to Nth stages and the gate-on voltage applied from the power supply unit can be reflected, and the reflected value can be applied to the gate driver in real time through a line. The sensing unit may be electrically connected to the CLK node nCLK to receive the Jth clock signal CLK(J) having a gate-on voltage changed due to the above reasons and problems. The gate-on voltage cVGL compensated by the compensation unit based on the voltage sensed by the sensing unit may be provided to the VGL node nVGL.

[0320] Deviations may occur according to the differences in the resistance and parasitic capacitance of the clock lines, resulting in RC delay and / or IR drop.

[0321] The gate driver according to the present specification, the display device including the gate driver, and the method of driving the display device can reduce driving failures caused by the load received by the clock signal provided to the relatively distant stages.

[0322] The gate driver according to the present specification can standardize the output of the gate signal as the length of the clock line increases.

[0323] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments, and various modifications can be made without departing from the technical spirit of the present disclosure.

[0324] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments.

[0325] Therefore, it should be understood that the above embodiments are illustrative in all aspects and not restrictive.

[0326] The scope of the present disclosure should be interpreted according to the appended claims, and all technical spirits within the equivalent scope should be interpreted as being included within the scope of the present disclosure.

Claims

1. A gate driver comprising a plurality of stages, the plurality of stages being cascade-connected to each other through a carry signal line and configured to receive a clock signal through a clock line, in, The multiple stages include: a first stage configured to receive a first clock signal and a start signal and output a first gate signal and a first carry signal; a Jth stage configured to receive a Jth clock signal and a J-1th carry signal, and output a Jth gate signal and a Jth carry signal, wherein J is a positive integer greater than or equal to 2 and less than or equal to N; and an Nth stage, the Nth stage being configured to receive an Nth clock signal and an N-1th carry signal, and output an Nth gate signal and an Nth carry signal, wherein N is a natural number greater than or equal to 2, and Wherein, each of the first to the Nth levels includes: a clock node inputted with the first clock signal, the Jth clock signal or the Nth clock signal; a gate-on voltage node to which a gate-on voltage is applied; and A gate-off voltage node to which a gate-off voltage is applied, wherein each of the first clock signal and the Jth clock signal swings between a gate-on voltage and a gate-off voltage, and When the gate-on voltage of the Jth clock signal is different from the gate-on voltage of the first clock signal, a compensation gate-on voltage is applied to the gate-on voltage node of the Jth stage, and the compensation gate-on voltage is a gate-on voltage with a changed voltage level.

2. The gate driver according to claim 1, wherein: The J level includes: a first output node, the first output node outputting the Jth gate signal including a scan signal and an emission control signal; a second output node, wherein the second output node outputs the J-th carry signal; The starting node having the J-1th carry signal is input; a first transistor, which activates the QC node by applying any one of the compensation gate-on voltage or the gate-off voltage to the QC node according to the Jth clock signal; a sixth transistor that supplies the Jth gate signal at the gate-on voltage to the first output node from the time when the first control node is bootstrapped in synchronization with the activation timing of the QC node; A QB control unit configured to activate a QB node opposite to the QC node according to potentials of the clock node, the start node, and the QC node; and a seventh transistor that provides the Jth gate signal at the gate-off voltage to the first output node when the QB node is activated before the QC node is activated, and The compensation gate turn-on voltage is applied to the second output node.

3. The gate driver according to claim 2, further comprising: an eighth transistor, the eighth transistor being disposed between the gate-on voltage node of the Jth stage and the second output node; as well as A ninth transistor, the ninth transistor is arranged between the gate-off voltage node of the Jth stage and the second output node.

4. The gate driver according to claim 3, wherein: The gate-on voltage received from a power supply unit is applied to the first output node of the Jth stage.

5. The gate driver according to claim 1, wherein: The J level includes: an output node, the output node outputting the Jth gate signal including a scan signal and an emission control signal; The starting node having the J-1th carry signal is input; a first transistor, which activates the QC node by applying any one of the compensation gate-on voltage and the gate-off voltage to the QC node according to the Jth clock signal; a sixth transistor that supplies the Jth gate signal at the gate-on voltage to the output node from the time when the first control node is bootstrapped in synchronization with the activation timing of the QC node; A QB control unit, the QB control unit being configured to activate a QB node opposite to the QC node according to potentials of the clock node, the start node, and the QC node; a seventh transistor that provides the Jth gate signal at the gate-off voltage to the output node when the QB node is activated before the QC node is activated; and a tenth transistor, the tenth transistor applying the compensation gate turn-on voltage to the first transistor according to the J-1th carry signal, and The gate-off voltage nodes include a first gate-off voltage node to which a first gate-off voltage is applied and a second gate-off voltage node to which a second gate-off voltage is applied. 6 . The gate driver according to claim 5 , the J-th stage further comprising an eleventh transistor which applies the second gate-off voltage to the first transistor according to a potential of a QB node of a J−1-th stage. 7 . The gate driver of claim 5 , the J-th stage further comprising a thirteenth transistor applying the second gate-off voltage to the first transistor according to the J-1-th carry signal.

8. The gate driver according to claim 7, wherein: The thirteenth transistor applies the second gate-off voltage to the first transistor according to the inverted J-1th carry signal.

9. The gate driver according to claim 5, wherein: The QB control unit comprises: a fifth capacitor connected between an input terminal of the J-th clock signal and a QD node; a third transistor, wherein the third transistor provides the Jth clock signal to the QB node according to the potential of the QD node; a second transistor providing a first gate-off voltage to the QD node according to the J-1th carry signal; and A fourth transistor, wherein the fourth transistor provides the first gate-off voltage to the QB node according to the potential of the QC node.

10. The gate driver according to claim 1, wherein: The gate-on voltage applied to the gate-on voltage node is a first constant voltage, and the gate-off voltage applied to the gate-off voltage node is a second constant voltage.

11. The gate driver according to claim 10, wherein: The J level includes: an output node, the output node outputting the J-th gate signal including a scan signal, an emission control signal, and the J-th carry signal; The starting node having the J-1th carry signal is input; a first transistor, which activates the QC node by applying any one of the compensation gate-on voltage and the gate-off voltage to the QC node according to the Jth clock signal; a sixth transistor that supplies the Jth gate signal at the gate-on voltage to the output node from the time when the first control node is bootstrapped in synchronization with the activation timing of the QC node; A QB control unit configured to activate a QB node opposite to the QC node according to potentials of the clock node, the start node, and the QC node; and and a seventh transistor that provides the Jth gate signal at the gate-off voltage to the output node when the QB node is activated before the QC node is activated.

12. The gate driver according to claim 11, wherein: When the first control node is bootstrapped, the potential of the QC node is different from the potential of the first control node. 13 . The gate driver of claim 12 , the Jth stage further comprising a fifth transistor that blocks an electrical connection between the QC node and the first control node when the first control node is bootstrapped.

14. The gate driver according to claim 13, wherein: A gate electrode of the fifth transistor is connected to the gate-on voltage node to which the first constant voltage is applied, a first electrode of the fifth transistor is connected to the QC node, and a second electrode of the fifth transistor is connected to the first control node.

15. The gate driver according to claim 14, wherein: The QB control unit comprises: a fifth capacitor connected between an input terminal of the J-th clock signal and a QD node; a third transistor, wherein the third transistor provides the Jth clock signal to the QB node according to the potential of the QD node; a second transistor providing a first gate-off voltage to the QD node according to the J-1th carry signal; and A fourth transistor, wherein the fourth transistor provides the first gate-off voltage to the QB node according to the potential of the QC node.

16. The gate driver according to claim 15, wherein: The potential of the QD node changes in synchronization with the Jth clock signal while the J-1th carry signal is maintained at the gate-off voltage, and The potential of the QD node changes to the gate-off voltage while the J-1th carry signal remains at the gate-on voltage.

17. The gate driver according to claim 10, wherein: The first constant voltage is applied to the gate-on voltage nodes of the first to N-th stages through one line.

18. The gate driver according to claim 1, wherein: The Jth level is the Nth level.

19. The gate driver according to claim 1, wherein: When the gate-on voltage of the Jth clock signal is higher than the gate-on voltage of the first clock signal, a voltage level of the gate-on voltage applied to the gate-on voltage node increases.

20. A display device, comprising: A display panel, wherein a plurality of gate lines, a plurality of power lines and the gate driver according to claim 1 are arranged on the display panel; wherein the gate driver receives the first clock signal, the Jth clock signal or the Nth clock signal from a clock generating circuit, and provides the first gate signal, the Jth gate signal or the Nth gate signal swinging between the gate-on voltage and the gate-off voltage to the plurality of gate lines; a power supply unit configured to generate power input to the display panel and the gate driver through the plurality of power lines; a sensing unit configured to sense the first clock signal, the Jth clock signal, or the Nth clock signal input to the gate driver; and A compensation unit is configured to apply a compensation gate-on voltage to the gate driver based on the first clock signal, the Jth clock signal, or the Nth clock signal sensed by the sensing unit.

21. The display device according to claim 20, wherein: The sensing unit senses the Jth clock signal.

22. The display device according to claim 21, wherein: The sensing unit senses the Nth clock signal.

23. The display device according to claim 21, wherein: A gate-on voltage of the Jth clock signal sensed by the sensing unit is different from a gate-on voltage of the first clock signal.

24. The display device according to claim 23, wherein: The compensation unit compares the sensed gate-on voltage of the Jth clock signal with the gate-on voltage of the first clock signal, and applies a compensated gate-on voltage to which a difference is reflected and added to the gate driver.

25. A method for driving a display device, the display device comprising a plurality of stages, the plurality of stages being cascade-connected to each other via a carry signal line, wherein: The plurality of stages include: a first stage configured to receive a first clock signal and a start signal and output a first gate signal and a first carry signal; a Jth stage configured to receive a Jth clock signal and a J-1th carry signal and output a Jth gate signal and a Jth carry signal, wherein J is a positive integer greater than or equal to 2 and less than or equal to N; and an Nth stage configured to receive an Nth clock signal and an N-1th carry signal and output an Nth gate signal and an Nth carry signal, wherein N is a natural number greater than or equal to 2, and each of the first stage, the Jth stage, and the Nth stage includes a clock node to which the first clock signal, the Jth clock signal, or the Nth clock signal is input, a gate-on voltage node to which a gate-on voltage is applied, and a gate-off voltage node to which a gate-off voltage is applied, and the method includes: sensing the gate-on voltage of the Jth clock signal input to the Jth stage; causing a difference between a gate-on voltage of the Jth clock signal sensed by the sensing and a gate-on voltage of the first clock signal; and A compensating gate-on voltage is applied to the gate-on voltage node of the Jth stage, wherein a voltage level of the compensating gate-on voltage changes based on the gate-on voltage of the Jth clock signal and the gate-on voltage of a clock signal input from a clock generating circuit.

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