Display device and display panel

Abstract

Embodiments of the present disclosure relate to a display device and a display panel, and more particularly, to a display device including: a display panel including a plurality of sub-pixels formed in a display area and dummy signal lines and a plurality of switching signal lines formed in a bezel area; a data switching circuit including a plurality of switching elements configured to control a data voltage supplied to the display panel; a timing controller configured to provide a plurality of switching signals controlling the plurality of switching elements through the plurality of switching signal lines; and a dummy signal generation circuit configured to generate a dummy signal supplied to the dummy signal line using the plurality of switching signals.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device and a display panel, and more specifically, for example but not limited to, to a display device and a display panel that can effectively reduce noise caused by electromagnetic interference generated during display driving. Background Art

[0002] Representative display devices for displaying images based on digital data include liquid crystal display (LCD) devices using liquid crystals and organic light emitting display devices using organic light emitting diodes (OLEDs), etc.

[0003] Among these display devices, organic light emitting displays use light emitting diodes and thus have fast responsiveness and various advantages in terms of contrast, luminous efficiency, brightness, and viewing angle. In this case, the light emitting diodes can be implemented with inorganic materials or organic materials.

[0004] An organic light emitting diode display includes light emitting diodes in sub-pixels arranged on a display panel, and controls the light emission of the light emitting diodes by controlling the current flowing through the light emitting diodes, thereby controlling the brightness presented by each sub-pixel while displaying an image.

[0005] The descriptions provided in the background art section should not be considered as prior art merely because they are mentioned in or related to the background art section. The background art section may include information describing one or more aspects of the subject technology. Summary of the Invention

[0006] Such a display device may include signal lines for transmitting various signals, and magnetic fields may be generated inside and outside the display device by signals applied to the signal lines.

[0007] Due to these magnetic fields, electromagnetic waves may be generated in the display device, and electromagnetic interference may occur between the display device and other adjacent electronic devices or (in the case of a display device having a touch function) between the display driving period and the touch driving period.

[0008] Thus, when electromagnetic interference occurs in the display device, a failure may occur in the display device due to the noise caused by the electromagnetic interference, and the image quality may deteriorate.

[0009] Therefore, it is necessary to reduce the noise caused by electromagnetic interference generated in the display device.

[0010] Therefore, the inventors of the present disclosure have invented a display device and a display panel that can effectively reduce the noise caused by electromagnetic interference generated during display driving.

[0011] Exemplary embodiments of the present disclosure may provide a display device and a display panel that can effectively reduce noise for a plurality of switching signals through a single dummy signal line by reducing the flipping of a plurality of switching elements that control data voltages applied to the display panel in the same direction.

[0012] Exemplary embodiments of the present disclosure may provide a display device and a display panel that can achieve a narrow bezel by reducing noise for a plurality of switching signals transmitted through a plurality of switching signal lines via a single dummy signal line.

[0013] Exemplary embodiments of the present disclosure may provide a display device including: a display panel including a plurality of sub-pixels formed in a display area and a dummy signal line and a plurality of switching signal lines formed in a bezel area; a data switching circuit including a plurality of switching elements that control data voltages provided to the display panel; a timing controller that transmits a plurality of switching signals for controlling the plurality of switching elements through the plurality of switching signal lines; and a dummy signal generation circuit that generates a dummy signal provided to the dummy signal line using the plurality of switching signals.

[0014] Exemplary embodiments of the present disclosure may provide a display panel including: a plurality of sub-pixels formed in a display area; a plurality of switching signal lines formed in a bezel area to transmit a plurality of switching signals; a dummy signal line located outside the plurality of switching signal lines and transmitting a dummy signal having a phase opposite to at least some of the plurality of switching signals; and a data switching circuit including a plurality of switching elements that control data voltages transmitted through data lines according to the plurality of switching signals.

[0015] According to an exemplary embodiment of the present disclosure, noise caused by electromagnetic interference during display driving can be effectively reduced.

[0016] According to an exemplary embodiment of the present disclosure, by reducing the flipping of a plurality of switching elements that control data voltages applied to the display panel in the same direction, noise for a plurality of switching signals can be effectively reduced through a single dummy signal line.

[0017] According to an exemplary embodiment of the present disclosure, by reducing the number of flips of a plurality of switching elements that control data voltages applied to the display panel, low-power driving can be performed and the lifespan of the switching elements can be increased.

[0018] According to an exemplary embodiment of the present disclosure, a narrow bezel can be achieved by reducing noise for a plurality of switching signals transmitted through a plurality of switching signal lines via a single dummy signal line.

[0019] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concept claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present disclosure includes drawings to provide a further understanding thereof, and the drawings are incorporated into and constitute a part of this application. The drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure.

[0021] In conjunction with the drawings, the above and other objects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description, where:

[0022] Figure 1 is a view schematically showing a display device according to an exemplary embodiment of the present disclosure;

[0023] Figure 2 is a view showing an example of a system of a display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 3 is a view showing an example sub-pixel circuit in a display device according to an exemplary embodiment of the present disclosure;

[0025] Figure 4 is a view showing an example of a switching structure for controlling a data voltage in a display device according to an exemplary embodiment of the present disclosure;

[0026] Figure 5 is a view showing an example structure of a display device according to an exemplary embodiment of the present disclosure in which a dummy signal line is provided;

[0027] Figure 6 is a view showing an example waveform of a dummy signal for reducing noise caused by a switching signal in a display device according to an exemplary embodiment of the present disclosure;

[0028] Figure 7 is a signal waveform diagram showing an example in which switching signals for controlling the operation of switching elements connected to data lines overlap during certain periods in a display device according to an exemplary embodiment of the present disclosure;

[0029] Figure 8 is a signal waveform diagram showing an example in which noise is reduced by one dummy signal when three switching signals for controlling a data voltage overlap in a display device according to an exemplary embodiment of the present disclosure;

[0030] Figure 9 is a signal waveform diagram showing an example of controlling switching signals to avoid an overlapping period in which multiple switching signals simultaneously flip to a conductive level in a display device according to an exemplary embodiment of the present disclosure;

[0031] Figure 10 is a block diagram showing a structure for generating a pseudo signal and a plurality of switch signals in a display device according to an exemplary embodiment of the present disclosure;

[0032] Figure 11 is a view showing an example of a pseudo signal generation circuit and a driving table in a display device according to an exemplary embodiment of the present disclosure;

[0033] Figure 12 is a view showing waveforms of a plurality of switch signals and a pseudo signal generated from a pseudo signal generation circuit in a display device according to an exemplary embodiment of the present disclosure; and

[0034] Figure 13 is a graph showing results of noise cancellation by one pseudo signal in a display device according to an exemplary embodiment of the present disclosure, for cases of temporal overlap of flips of some of the plurality of switch signals and cases where the plurality of switch signals do not flip simultaneously.

[0035] Throughout the drawings and the detailed description, unless otherwise specified, the same reference numerals should be understood to represent the same elements, features, and structures. For clarity, illustration, and convenience, the relative dimensions of these elements may be exaggerated and the description may be amplified. Detailed Embodiments

[0036] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In the following description of examples or embodiments of the present disclosure, reference will be made to the drawings, in which specific examples or embodiments that can be implemented are shown by way of illustration, and in which the same reference numerals and symbols may be used to represent the same or similar components even when shown in different drawings. Further, in the following description of examples or embodiments of the present disclosure, when it is determined that a detailed description of well-known functions and components incorporated herein may obscure the subject matter in some embodiments of the present disclosure, the detailed description will be omitted. Terms such as "including", "having", "containing", "constituting", "consisting of", and "formed of" used herein are generally intended to allow addition of other components, unless these terms are used together with the term "only". When used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise. The names of the respective elements used in the following description may have been selected only for convenience in preparing the specification and may thus be different from the names used in actual products.

[0037] Advantages and features of the present disclosure and methods for realizing the same will be clarified by the following exemplary embodiments described with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Instead, these exemplary embodiments are provided so that the present disclosure will be thorough and complete and will enable those skilled in the art to fully understand the scope of the present disclosure. Furthermore, the present disclosure is only defined by the scope of the claims.

[0038] Terms such as "first", "second", "A", "B", "(A)", or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence, quantity, etc. of an element, but is only used to distinguish the corresponding element from other elements.

[0039] When it is mentioned that a first element is "connected or coupled", "contacted or overlapped" with a second element, etc., it should be interpreted that not only can the first element be "directly connected or coupled" or "directly contacted or overlapped" with the second element, but also a third element may be "interposed" between the first element and the second element, or the first element and the second element may be "connected or coupled", "contacted or overlapped", etc. with each other via a fourth element. Here, the second element may be included in at least one of two or more elements that are "connected or coupled", "contacted or overlapped", etc. with each other.

[0040] When time-related terms such as "after", "subsequently", "then", "before", etc. are used to describe a process or operation of an element or configuration or a flow or step in an operation method, a processing method, a manufacturing method, these terms may be used to describe a non-continuous or non-sequential process or operation unless used together with the terms "directly" or "immediately".

[0041] In addition, when referring to any dimensions, relative sizes, etc., even if no relevant description is specified, the numerical value or corresponding information (e.g., level, range, etc.) of an element or feature should be considered to include a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external impacts, noise, etc.). Furthermore, the term "may" fully encompasses all meanings of the term "can". Any implementation described herein as an "example" is not necessarily to be construed as more preferred or more advantageous than other implementations.

[0042] Terms such as "below", "lower", "above", "upper", etc. may be used herein to describe the relationship between elements as shown in the accompanying drawings. It should be understood that these terms are spatially relative and are based on the orientation depicted in the drawings.

[0043] For example, the meaning of "at least one of the first element, the second element, and the third element" encompasses combinations of all three listed elements, combinations of any two of the three elements, and each individual element (i.e., the first element, the second element, or the third element).

[0044] As can be fully understood by those skilled in the art, the features of various embodiments of the present disclosure can be partially or wholly coupled or combined with each other, and can interoperate in various ways and be technically driven. The embodiments of the present disclosure can be implemented independently of each other, or can be implemented together in a mutually dependent relationship.

[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It should also be understood that terms (e.g., terms defined in a common dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein. For example, as should be understood by one of ordinary skill in the art, terms such as "component" or "unit" can be applied to, for example, a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function.

[0046] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0047] Figure 1 is a view schematically showing a display device according to an exemplary embodiment of the present disclosure.

[0048] Referring to Figure 1 , a display device 100 according to an exemplary embodiment of the present disclosure may include: a display panel 110 in which a plurality of gate lines GL and data lines DL are connected, and a plurality of sub-pixels SP are arranged in a matrix form in a display area; a gate driving circuit 120 that provides signals to the plurality of gate lines GL; a data driving circuit 130 that provides data voltages through the plurality of data lines DL; and a timing controller 140 that controls the gate driving circuit 120 and the data driving circuit 130.

[0049] The display panel 110 displays an image based on a scan signal transmitted from the gate driving circuit 120 through the plurality of gate lines GL and a data voltage transmitted from the data driving circuit 130 through the plurality of data lines DL.

[0050] In the case of a liquid crystal display, the display panel 110 may include a liquid crystal layer formed between two substrates and may operate in any known mode such as, for example, a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in-plane switching (IPS) mode, or an fringe field switching (FFS) mode, but is not limited thereto. In the case of an organic light emitting display, the display panel 110 may be implemented in a top emission scheme, a bottom emission scheme, or a dual emission scheme.

[0051] In the display panel 110, a plurality of pixels may be arranged in a matrix form, and each pixel may include sub-pixels SP having different colors (e.g., a white sub-pixel, a red sub-pixel, a green sub-pixel, and a blue sub-pixel), and each sub-pixel SP may be defined by a plurality of data lines DL and a plurality of gate lines GL. Embodiments are not limited thereto. As an example, each pixel may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Sub-pixels of other colors may be alternatively or additionally included.

[0052] One sub-pixel SP may include, for example, a thin film transistor (TFT) disposed in an area defined by one data line DL and one gate line GL, a light emitting element (e.g., a light emitting diode) that emits light according to a voltage corresponding to a data voltage, and a storage capacitor electrically connected to the light emitting element to hold the voltage.

[0053] For example, when the display device 100 having a resolution of 2160×3840 includes four sub-pixels SP of white (W), red (R), green (G), and blue (B), 3840 data lines DL and 2160 gate lines GL may be connected to each of the four sub-pixels WRGB, and thus 3840×4 = 15360 data lines DL may be provided. Each sub-pixel SP is disposed in an area defined by the gate line GL and the data line DL.

[0054] The gate driving circuit 120 may be controlled by the timing controller 140 to sequentially output scan signals to a plurality of gate lines GL provided in the display panel 110 to control the driving timing of the plurality of sub-pixels SP.

[0055] In the display device 100 having a resolution of 2160×3840, sequentially outputting scan signals from the first gate line to the 2160th gate line to the 2160 gate lines GL may be referred to as 2160-phase driving. Sequentially outputting scan signals to each unit having four gate lines GL (e.g., after sequentially outputting scan signals to the first gate line to the fourth gate line, sequentially outputting scan signals to the fifth gate line to the eighth gate line) is referred to as four-phase driving. In other words, sequentially outputting scan signals to each N gate lines GL may be referred to as N-phase driving.

[0056] The gate driving circuit 120 may include one or more gate driving integrated circuits (GDICs). According to the driving scheme, the gate driving circuit 120 may be located only on one side of the display panel 110 or on each of two opposite sides. The gate driving circuit 120 may be implemented as an in-panel gate (GIP) type, in which the gate driving circuit 120 is directly formed in the border area of the display panel 110. The border area may correspond to a non-display area other than the display area where sub-pixels are provided. The implementation is not limited thereto. As an example, the gate driving circuit 120 may be separately provided (e.g., located on a separate panel), and then connected to the display panel 110 by a tape automated bonding (TAB) method, a chip on glass (COG) method, a chip on panel (COP) method, or a chip on film (COF) method, but is not limited thereto.

[0057] The data driving circuit 130 receives digital image data DATA from the timing controller 140 and converts the received digital image data DATA into an analog data voltage. Then, when the data voltage is output to each data line DL according to the timing of applying a scan signal through the gate line GL, each sub-pixel SP connected to the data line DL displays a light emitting signal having a luminance corresponding to the data voltage.

[0058] Similarly, the data driving circuit 130 may include one or more source driving integrated circuits SDICs, and the source driving integrated circuit SDICs may be connected to the bonding pads of the display panel 110 in a tape automated bonding (TAB) type or a chip on glass (COG) type or may be directly provided on the display panel 110, but is not limited thereto.

[0059] In some cases, each source driving integrated circuit SDIC may be integrated and provided on the display panel 110. In addition, each source driving integrated circuit SDIC may be implemented as a chip on film (COF) type, and in this case, each source driving integrated circuit SDIC may be mounted on a circuit film and may be electrically connected to the data line DL of the display panel 110 through the circuit film.

[0060] The timing controller 140 provides various control signals to the gate driving circuit 120 and the data driving circuit 130 and controls the operations of the gate driving circuit 120 and the data driving circuit 130. As an example, the timing controller 140 may control the gate driving circuit 120 to output a scan signal according to the timing implemented in each frame, and on the other hand, transmit the digital image data DATA received from the outside to the data driving circuit 130.

[0061] In this case, the timing controller 140 receives several timing signals (including, for example, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock MCLK) and digital image data DATA from an external source (e.g., a host system). Accordingly, the timing controller 140 can generate control signals based on the various timing signals received from the external source and transmit the control signals to the gate driving circuit 120 and the data driving circuit 130.

[0062] For example, the timing controller 140 outputs several gate control signals including, for example, a gate start pulse GSP, a gate clock GCLK, and a gate output enable signal GOE to control the gate driving circuit 120, but is not limited thereto. The gate start pulse GSP controls the timing at which one or more gate driving integrated circuits GDICs constituting the gate driving circuit 120 start operating. The gate clock GCLK is a clock signal commonly input to one or more gate driving integrated circuits GDICs and controls the shift timing of the scan signal. The gate output enable signal GOE specifies timing information regarding one or more gate driving integrated circuits GDICs.

[0063] The timing controller 140 outputs various data control signals including, for example, a source start pulse SSP, a source sampling clock SCLK, and a source output enable signal SOE to control the data driving circuit 130, but is not limited thereto. The source start pulse SSP controls the timing at which one or more source driving integrated circuits SDICs constituting the data driving circuit 130 start data sampling. The source sampling clock SCLK is a clock signal that controls the timing of sampled data in the source driving integrated circuit SDIC. The source output enable signal SOE controls the output timing of the data driving circuit 130.

[0064] The display device 100 may further include a power management integrated circuit that supplies various voltages or currents to, for example, the display panel 110, the timing controller 140, the gate driving circuit 120, and / or the data driving circuit 130, or controls the various voltages or currents to be supplied.

[0065] Meanwhile, a light-emitting element may be provided in each sub-pixel SP. For example, an organic light-emitting diode display may include a light-emitting element such as a light-emitting diode in each sub-pixel SP and may display an image by controlling the current flowing through the light-emitting element according to a data voltage.

[0066] Figure 2 is a view showing an example of a system of a display device according to an exemplary embodiment of the present disclosure.

[0067] Refer to Figure 2, in the display device 100 according to an exemplary embodiment of the present disclosure, the source driver integrated circuit SDIC included in the data driver circuit 130 is implemented as a chip-on-film (COF) type among various types (e.g., TAB, COG, or COF), and the gate driver circuit 120 is implemented as an in-panel gate (GIP) type among various types (e.g., TAB, COG, COF, or GIP), but is not limited thereto.

[0068] When the gate driver circuit 120 is implemented as the GIP type, a plurality of gate driver integrated circuits GDIC included in the gate driver circuit 120 can be directly formed in the border area of the display panel 110. In this case, the gate driver integrated circuit GDIC can receive various signals (e.g., clock signal, gate high signal, gate low signal, etc.) required to generate the scan signal SCAN through the gate driver-related signal lines provided in the border area.

[0069] Similarly, one or more source driver integrated circuits SDIC included in the data driver circuit 130 can be respectively mounted on the source film SF, and one side of the source film SF can be electrically connected to the display panel 110. The lines for electrically connecting the source driver integrated circuit SDIC and the display panel 110 can be provided on the source film SF.

[0070] The display device 100 may include: at least one source printed circuit board SPCB for circuit connection between a plurality of source driver integrated circuits SDIC and other devices; and a control printed circuit board CPCB for mounting control components and various electronic devices.

[0071] The other side of the source film SF on which the source driver integrated circuit SDIC is mounted can be connected to at least one source printed circuit board SPCB. As an example, one side of the source film SF on which the source driver integrated circuit SDIC is mounted can be electrically connected to the display panel 110, and the other side thereof can be electrically connected to the source printed circuit board SPCB.

[0072] The timing controller 140 and the power management integrated circuit (PMIC) 150 can be mounted on the control printed circuit board CPCB. The timing controller 140 can control the operations of the data driver circuit 130 and the gate driver circuit 120. The power management integrated circuit 150 can supply a driving voltage or current to the display panel 110, the timing controller 140, the data driver circuit 130, and / or the gate driver circuit 120, and control the supplied voltage or current.

[0073] At least one source printed circuit board SPCB and a control printed circuit board CPCB may be electrically connected through at least one connection member. The connection member may include, for example, a flexible printed circuit FPC or a flexible flat cable FFC, but is not limited thereto. At least one source printed circuit board SPCB and a control printed circuit board CPCB may be integrated into a single printed circuit board.

[0074] As an example, the display device 100 may further include a setting board 170 electrically connected to the control printed circuit board CPCB. As an example, the setting board 170 may also be referred to as a power supply board. A main power management circuit (M-PMC) 160 for managing the overall power of the display device 100 may be provided on the setting board 170. The main power management circuit 160 may interact with the power management integrated circuit 150. The embodiments are not limited thereto. As an example, at least one of the power management integrated circuit 150 and the main power management circuit 160 may be omitted. As an example, the display panel 110 may receive a driving voltage or current from an external device other than the power management integrated circuit 150 and the main power management circuit 160. As an example, at least two of the source printed circuit board SPCB, the control printed circuit board CPCB, and the setting board 170 may be integrated into a single printed circuit board.

[0075] In the display device 100 configured as such, a driving voltage is generated in the setting board 170 and the driving voltage is transmitted to the power management integrated circuit 150 in the control printed circuit board CPCB. The power management integrated circuit 150 transmits the driving voltage required for display driving or eigenvalue sensing, etc. to the source printed circuit board SPCB through, for example, a flexible printed circuit FPC or a flexible flat cable FFC. The driving voltage transmitted to the source printed circuit board SPCB is provided by the source driver integrated circuit SDIC to cause a specific sub-pixel SP in the display panel 110 to emit light or to sense it.

[0076] Each sub-pixel SP arranged in the display panel 110 in the display device 100 may include a light-emitting element and circuit elements (e.g., driving transistors) for driving the light-emitting diode.

[0077] The type and number of circuit elements constituting each sub-pixel SP may vary according to the functions to be provided and the design scheme.

[0078] Figure 3 is a view showing an example sub-pixel circuit in a display device according to an exemplary embodiment of the present disclosure.

[0079] Refer to Figure 3, the sub-pixel circuit of the display device 100 according to an exemplary embodiment of the present disclosure may include a light-emitting element ED, a driving transistor DRT, a plurality of switching transistors T1 to T5, and a storage capacitor Cst. The embodiments are not limited thereto. As an example, the sub-pixel circuit of the display device 100 may include more or fewer transistors and more or fewer storage capacitors. As an example, the sub-pixel circuit of the display device 100 may include at least two transistors and at least one storage capacitor, but is not limited thereto.

[0080] The driving transistor DRT and the plurality of switching transistors T1 to T5 included in the sub-pixel circuit may be implemented as PMOS-type low-temperature polycrystalline silicon (LTPS) transistors, thereby ensuring desired response characteristics.

[0081] Alternatively, at least one of the plurality of switching transistors T1 to T5 may be implemented as an NMOS-type or PMOS-type oxide transistor having good leakage current characteristics in the off state, and the remaining switching transistors may be implemented as PMOS-type LTPS transistors having good response characteristics. The embodiments are not limited thereto. As an example, the driving transistor DRT and the plurality of switching transistors T1 to T5 included in the sub-pixel circuit may be implemented as PMOS-type transistors or NMOS-type transistors. As an example, the driving transistor DRT and the plurality of switching transistors T1 to T5 included in the sub-pixel circuit may be implemented as transistors including any semiconductor (e.g., oxide semiconductor, polycrystalline silicon semiconductor, amorphous silicon semiconductor, compound semiconductor, organic semiconductor, etc.), but is not limited thereto.

[0082] The light-emitting element ED emits light through a driving current regulated according to the gate-source voltage Vgs of the driving transistor DRT. The anode of the light-emitting element ED is connected to the fourth node P4, and the cathode of the light-emitting element ED is connected to the low-potential pixel voltage EVSS.

[0083] When the light-emitting element ED is an organic light-emitting diode, an organic compound layer is provided between the anode and the cathode.

[0084] The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EML, an electron transport layer ETL, and an electron injection layer EIL. For example, two or more organic compound layers emitting different colors of light may be stacked according to a cascade structure. The embodiments are not limited thereto. As an example, at least one of the hole injection layer HIL, the hole transport layer HTL, the electron transport layer ETL, and the electron injection layer EIL may be omitted.

[0085] When a driving current flows through the light-emitting element ED, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the light-emitting layer EML to form excitons. As a result, the light-emitting layer EML can emit light (e.g., visible light or even invisible light).

[0086] The driving transistor DRT controls the current flowing through the light-emitting element ED according to the gate-source voltage Vgs. The gate of the driving transistor DRT is connected to the second node P2, the drain (or source) is connected to the driving voltage line providing the high-potential pixel voltage EVDD, and the source (or drain) is connected to the third node P3.

[0087] The sub-pixel circuit may include first to fifth switching transistors T1 to T5 capable of sampling the gate-source voltage Vgs and a storage capacitor Cst to compensate for the threshold voltage or mobility of the driving transistor DRT.

[0088] The first switching transistor T1 is connected between the data line DL and the first node P1 and switches according to the first scan signal SCAN1. The gate of the first switching transistor T1 is connected to the first gate line to which the first scan signal SCAN1 is applied, the drain (or source) is connected to the data line DL, and the source (or drain) is connected to the first node P1.

[0089] The second switching transistor T2 is connected between the second node P2 and the third node P3 and switches according to the second scan signal SCAN2. The gate of the second switching transistor T2 is connected to the second gate line to which the second scan signal SCAN2 is applied, the drain (or source) is connected to the third node P3, and the source (or drain) is connected to the second node P2.

[0090] Since one electrode of the second switching transistor T2 is connected to the gate of the driving transistor DRT, it is preferable that the second switching transistor T2 has good cut-off current characteristics. Thus, as an example, the second switching transistor T2 may be designed with a double-gate structure to suppress leakage current during cut-off, but is not limited thereto.

[0091] In the double-gate structure, the first gate and the second gate are connected to each other to have the same potential, and the channel length is longer than that of the single-gate structure. As the channel length increases, the resistance increases and the leakage current during cut-off decreases, thereby ensuring the stability of operation. However, the second switching transistor T2 may be implemented as a single-gate structure. As an example, the second switching transistor T2 may be implemented as an oxide transistor with a single-gate structure, but is not limited thereto.

[0092] The third switching transistor T3 is connected between the first node P1 and a reference voltage line to which a reference voltage Vref is applied, and is switched according to a light emission signal EM. The gate of the third switching transistor T3 is connected to a third gate line to which the light emission signal EM is applied, the drain (or source) is connected to the first node P1, and the source (or drain) is connected to the reference voltage line.

[0093] The fourth switching transistor T4 is connected between the third node P3 and the fourth node P4 which is the anode of the light emitting element ED, and is switched according to a light emission signal EM. The gate of the fourth switching transistor T4 is connected to a third gate line to which the light emission signal EM is applied, the drain (or source) is connected to the third node P3, and the source (or drain) is connected to the fourth node P4. Since the fourth switching transistor T4 controls the drive current flowing through the light emitting element ED, it may be referred to as a light emission control transistor.

[0094] The fifth switching transistor T5 is connected between the fourth node P4 and the reference voltage line, and is switched according to a second scan signal SCAN2. The gate of the fifth switching transistor T5 is connected to a second gate line to which the second scan signal SCAN2 is applied, the drain (or source) is connected to the fourth node P4, and the source (or drain) is connected to the reference voltage line.

[0095] The storage capacitor Cst is connected between the first node P1 and the second node P2.

[0096] In addition, the display device 100 of the present disclosure can reduce noise by a switching circuit that controls a data voltage Vdata applied through a data line DL.

[0097] Figure 4 is a view showing an example of a switching structure for controlling a data voltage in a display device according to an exemplary embodiment of the present disclosure.

[0098] Referring to Figure 4 , in the display device 100 according to an exemplary embodiment of the present disclosure, the data driving circuit 130 sequentially inputs and latches image data DATA input from the timing controller 140, for example, line by line, but is not limited thereto.

[0099] The latched line-by-line image data DATA is converted into a data voltage Vdata using a gamma voltage and a digital-to-analog converter, and then output through a plurality of data channels CH1 and CH2 according to a source output enable signal.

[0100] The data switching circuit 190 may include a plurality of switching elements SW1, SW2, and SW3, and may selectively supply the data voltage Vdata transmitted through the data channels CH1 and CH2 of the data driving circuit 130 to the data lines DL(1)-DL(m) of the display panel 110 according to, for example, the switching signals SS1, SS2, and SS3 output from the timing controller 140. The plurality of switching elements SW1, SW2, and SW3 may be transistors that are turned on or off through the switching signals SS1, SS2, and SS3, respectively.

[0101] For example, when the plurality of switching elements SW1, SW2, and SW3 are P-type transistors (e.g., P-type metal oxide semiconductor (MOS) transistors), the plurality of switching elements SW1, SW2, and SW3 may be turned on through low-level switching signals SS1, SS2, and SS3, and may supply the data voltage Vdata transmitted through the channels CH1 and CH2 to the selected data lines DL(1)-DL(m). The embodiments are not limited thereto. For example, the plurality of switching elements SW1, SW2, and SW3 may be N-type transistors, and the plurality of switching elements SW1, SW2, and SW3 may be turned on through high-level switching signals SS1, SS2, and SS3.

[0102] The data switching circuit 190 may function as a multiplexer for controlling the connection between one data channel (e.g., CH1) and multiple data lines (e.g., DL(1), DL(2), and DL(3)). Although described and illustrated herein as one data channel connected to three data lines, the embodiments are not limited thereto. As an example, one data channel may be connected to one data line. As an example, one data channel may be connected to at least two data lines. Thus, as an example, there may be at least two switching elements and at least two switching signals, the number of which may correspond to (e.g., be equal to) the number of the above at least two data lines. In addition, although described and illustrated as having two data channels, the embodiments are not limited thereto. As an example, there may be more than two data channels.

[0103] The data switching circuit 190 may supply the data voltage Vdata output from one data channel (e.g., CH1) extending from the data driving circuit 130 through a data line selected from the three data lines DL1, DL2, and DL3 according to the switching signals SS1, SS2, and SS3.

[0104] As an example, when the first switching signal SS1 is applied at a conductive level, the data switching circuit 190 may supply the data voltage output from each of the data channels CH1 and CH2 of the data driving circuit 130 to the data line (e.g., DL1) of the first color (e.g., red).

[0105] When the second switching signal SS2 is applied at a conductive level, the data voltage output from each of the data channels CH1 and CH2 of the data driving circuit 130 can be provided to the data lines (e.g., DL2) of the second color (e.g., green).

[0106] When the third switching signal SS3 is applied at a conductive level, the data voltage output from each of the data channels CH1 and CH2 of the data driving circuit 130 can be provided to the data lines (e.g., DL3) of the third color (e.g., blue).

[0107] Here, it is illustrated that the data switching circuit 190 includes three switching elements SW1, SW2, and SW3, and the data voltage Vdata transmitted through one of the data channels CH1 or CH2 is provided to the three data lines DL(1), DL(2), and DL(3) according to the three switching signals SS1, SS2, and SS3. However, the data switching circuit 190 is not limited thereto, and the data voltage output from one of the data channels CH1 or CH2 can be provided to m data lines DL(1)-DL(m) according to a plurality of switching signals. As an example, m can be a natural number equal to or greater than 2.

[0108] In this case, since the switching signals SS1, SS2, and SS3 for driving the data switching circuit 190 operate at a high frequency, noise due to electromagnetic interference may be generated. As an example, during the transition process of the switching signals SS1, SS2, and SS3 for driving the data switching circuit 190, capacitance may be generated between adjacent data lines, and noise may be generated due to electromagnetic interference between the data lines.

[0109] To reduce noise, the display device 100 according to an exemplary embodiment of the present disclosure can reduce the noise caused by the switching signals SS1, SS2, and SS3 by setting at least one dummy signal line in the border area of the display panel 110 and applying a dummy signal having a phase opposite to that of the switching signals SS1, SS2, and SS3.

[0110] Figure 5 is a view showing an example structure in which a dummy signal line is provided in a display device according to an exemplary embodiment of the present disclosure.

[0111] Referring to Figure 5 , in the display device 100 according to an exemplary embodiment of the present disclosure, the switching signal lines SL1, SL2, and SL3 for transmitting the switching signals SS1, SS2, and SS3 for controlling the switching elements connected between the data channels and the data lines can extend along the border area of the display panel 110.

[0112] Specifically, multiple switch signal lines SL1, SL2, and SL3 can extend along the side surface of the source electrode film SF on which the source electrode driving integrated circuit SDIC is mounted, and can extend along the border area of the display panel 110 adjacent to the data driving circuit 130. In this case, by way of example, the multiple switch signal lines SL1, SL2, and SL3 can be formed into a multi-feed structure branched from multiple points to reduce resistance, but is not limited thereto.

[0113] Meanwhile, a dummy signal line PL for transmitting a dummy signal PS can extend in the border area of the display panel 110. By way of example, the dummy signal line PL for transmitting the dummy signal PS can extend parallel to the switch signal lines SL1, SL2, and SL3 in the border area of the display panel 110. By way of example, the dummy signal line PL for transmitting the dummy signal PS can extend along the outside of the switch signal lines SL1, SL2, and SL3 in the border area of the display panel 110. In this case, since the switch signal lines SL1, SL2, and SL3 are provided in the area adjacent to the data driving circuit 130, and the dummy signal line PL is provided outside the switch signal lines SL1, SL2, and SL3, the dummy signal line PL can be provided to be farther from the data driving circuit 130 than the switch signal lines SL1, SL2, and SL3. The embodiment is not limited thereto. By way of example, the dummy signal line PL can be provided to be farther from the data driving circuit 130 than at least one of the switch signal lines SL1, SL2, and SL3, or can be provided to be closer to the data driving circuit 130 than the switch signal lines SL1, SL2, and SL3 (for example, by extending along the inside of the switch signal lines SL1, SL2, and SL3 in the border area of the display panel 110).

[0114] By applying the dummy signal PS having a phase at least partially opposite to that of the switch signals SS1, SS2, and SS3 to the dummy signal line PL extending along the outside of the switch signal lines SL1, SL2, and SL3, electromagnetic interference caused by the switch signals SS1, SS2, and SS3 can be at least partially cancelled out.

[0115] By way of example, the dummy signal PS is a signal having a phase opposite to that of the switch signals SS1, SS2, and SS3, and is transmitted through the dummy signal line PL provided adjacent to the switch signal lines SL1, SL2, and SL3 to reduce electromagnetic interference generated during the transition of the switch signals SS1, SS2, and SS3.

[0116] In this case, as the radiation amount of the dummy signal PS becomes more similar to the radiation amount of the switch signals SS1, SS2, and SS3, the effect of reducing electromagnetic noise can be improved. To this end, it may be effective to make the sum of the line widths of the dummy signal line PL and the sum of the line widths of the switch signal lines SL1, SL2, and SL3 the same or similar.

[0117] However, the same number of pseudo-signal lines PL as the number of the switch signal lines SL1, SL2, and SL3 can be formed, but considering the width of the border area, a smaller number of pseudo-signal lines PL than the number of the switch signal lines SL1, SL2, and SL3 can be formed. Here, an example is shown in which one pseudo-signal line PL is formed corresponding to the three switch signal lines SL1, SL2, and SL3. The embodiment is not limited thereto. As an example, two or more pseudo-signal lines PL can be formed corresponding to the three switch signal lines SL1, SL2, and SL3.

[0118] Figure 6 is a view showing an example waveform of a pseudo-signal for reducing noise caused by a switch signal in a display device according to an exemplary embodiment of the present disclosure.

[0119] Referring to Figure 6 , a display device 100 according to an exemplary embodiment of the present disclosure can provide a pseudo-signal PS having a phase opposite to that of the switch signals SS1, SS2, and SS3 applied through the switch signal lines SL1, SL2, and SL3 provided in the border area to the pseudo-signal line PSL, thereby eliminating noise caused by the switch signals SS1, SS2, and SS3.

[0120] Here, as an example, a plurality of switching elements SW1, SW2, and SW3 are formed of P-type MOS transistors and are turned on by low-level switch signals SS1, SS2, and SS3, but the present disclosure is not limited thereto.

[0121] In this case, the three switch signals SS1, SS2, and SS3 can form pulses at different times while each having a high level and a low level, and thus one pseudo-signal PS having a phase opposite to that of the three switch signals SS1, SS2, and SS3 can be generated.

[0122] As described above, the display device 100 according to the present disclosure can apply a pseudo-signal PS having an opposite phase along the pseudo-signal line PL provided in the border area when the switch signals SS1, SS2, and SS3 are flipped, to reduce noise caused by the switch signals SS1, SS2, and SS3 for controlling the data voltage Vdata.

[0123] In this case, as an example, depending on the type of the image displayed on the display panel 110, data of a specific color or a specific pattern may be continuously displayed. Therefore, since the lifetimes of the switching elements SW1, SW2, and SW3 for transmitting the data voltage Vdata may be shortened and the image quality of the display panel 110 may deteriorate, as an example, the switch signals SS1, SS1, and SS3 can be generated such that the conduction periods of the switch signals SS1, SS2, and SS3 partially overlap with each other.

[0124] Figure 7 It is a signal waveform diagram showing an example in which switching signals for controlling the operation of switching elements connected to data lines overlap during certain periods in a display device according to an exemplary embodiment of the present disclosure.

[0125] Referring to Figure 7 , the display device 100 according to an exemplary embodiment of the present disclosure may use switching signals SS1, SS2, and SS3 applied through a plurality of switching signal lines SL1, SL2, and SL3 provided in a border area to control the operation of a plurality of switching elements SW1, SW2, and SW3 connected to data lines.

[0126] When the plurality of switching elements SW1, SW2, and SW3 are P-type MOS transistors, the plurality of switching elements SW1, SW2, and SW3 may be turned on by low-level switching signals SS1, SS2, and SS3, but it is not limited thereto.

[0127] For example, the three switching signals SS1, SS2, and SS3 may flip while each having a high level and a low level, and may form pulses of a conductive level at different times.

[0128] In this case, as an example, when data of a specific color or a specific pattern is continuously input, the lifespan of the switching elements SW1, SW2, and SW3 may be shortened, and the image quality of the display panel 110 may deteriorate. Therefore, to solve this problem, the switching signals SS1, SS2, and SS3 may be generated such that the conduction periods of the switching signals SS1, SS2, and SS3 may partially overlap.

[0129] For example, the first switching signal SS1 may include a plurality of first conduction periods T1 for turning on the first switching element SW1, the second switching signal SS2 may include a plurality of second conduction periods T2 for turning on the second switching element SW2, and the third switching signal SS3 may include a plurality of third conduction periods T3 for turning on the third switching element SW3.

[0130] In this case, between the plurality of first conduction periods T1 for turning on the first switching element SW1, a first buffer period T1B for flipping the first switching signal SS1 of a cut-off level to a conductive level within a predetermined time may be included.

[0131] Here, the first buffer period T1B may at least partially overlap with the second conduction period T2 during which the second switching element SW2 is turned on or the third conduction period T3 during which the third switching element SW3 is turned on. Accordingly, the first switching element SW1 may also be turned on during a partial period that overlaps with the second conduction period T2 during which the second switching element SW2 is turned on or the third conduction period T3 during which the third switching element SW3 is turned on. As a result, the time intervals during which the first switching element SW1 is turned on and off can be effectively allocated, and the image quality of pixels (red sub-pixels, green sub-pixels, and blue sub-pixels) controlled by the first switching element SW1, the second switching element SW2, and the third switching element SW3 can be maintained in a coordinated manner.

[0132] In addition, even between the multiple second conduction periods T2 for turning on the second switching element SW2, a second buffer period T2B for flipping a second switching signal SS2 at a cut-off level to a conduction level within a predetermined time may be included. In this case, the second buffer period T2B may at least partially overlap with the first conduction period T1 during which the first switching element SW1 is turned on or the third conduction period T3 during which the third switching element SW3 is turned on.

[0133] In addition, even between the multiple third conduction periods T3 for turning on the third switching element SW3, a third buffer period T3B for flipping a third switching signal SS3 at a cut-off level to a conduction level within a predetermined time may be included. In this case, the third buffer period T3B may at least partially overlap with the first conduction period T1 during which the first switching element SW1 is turned on or the second conduction period T2 during which the second switching element SW2 is turned on.

[0134] As described above, when some periods of multiple switching signals SS1, SS2, and SS3 for controlling the operations of multiple switching elements SW1, SW2, and SW3 overlap with each other, the times at which some of the multiple switching signals SS1, SS2, and SS3 are flipped may overlap with each other, and thus it may be difficult to use one pseudo signal PS to eliminate noise when the switching signals SS1, SS2, and SS3 are flipped.

[0135] Figure 8 is a signal waveform diagram showing an example of reducing noise by one pseudo signal when three switching signals for controlling a data voltage overlap in a display device according to an exemplary embodiment of the present disclosure.

[0136] Refer to Figure 8, when data of a specific color or a specific pattern is continuously input, the lifetimes of specific switching elements SW1, SW2, and SW3 for transmitting data voltage Vdata may be shortened, and the image quality of the display panel 110 may deteriorate. Accordingly, the display device 100 according to an exemplary embodiment of the present disclosure may perform overlapping driving such that the on periods of switching signals SS1, SS2, and SS3 overlap with each other partially.

[0137] As described above, in the case of overlapping driving in which some periods of switching signals SS1, SS2, and SS3 for controlling the operations of switching elements SW1, SW2, and SW3 overlap with each other, the times at which the switching signals SS1, SS2, and SS3 flip may overlap with each other. Accordingly, it may be difficult to use one pseudo signal PS to eliminate noise when the switching signals SS1, SS2, and SS3 flip.

[0138] Here, an example of generating a pseudo signal PS through a NAND gate that receives three switching signals SS1, SS2, and SS3 is shown.

[0139] For example, when driving is performed such that some periods of three switching signals SS1, SS2, and SS3 for controlling the operations of three switching elements SW1, SW2, and SW3 overlap with each other, periods (e.g., first overlapping period TO1 and fourth overlapping period TO4) may occur in which the second switching signal SS2 and the third switching signal SS3 flip while overlapping with each other at the conductive level L. In addition, periods (e.g., second overlapping period TO2) may occur in which the first switching signal SS1 and the second switching signal SS2 flip while overlapping with each other at the conductive level L, and periods (e.g., third overlapping period TO3) may occur in which the first switching signal SS1 and the third switching signal SS3 flip while overlapping with each other at the conductive level L.

[0140] In this case, in overlapping period TO in which two of the three switching signals SS1, SS2, and SS3 flip while overlapping with each other, it becomes difficult to use one pseudo signal PS to eliminate the noise of the switching signals SS1, SS2, and SS3.

[0141] The display device 100 according to the present disclosure may control the switching signals such that an overlapping period in which a plurality of switching signals simultaneously flip to the conductive level does not occur, thereby eliminating the noise of the plurality of switching signals using one pseudo signal.

[0142] Figure 9 is a signal waveform diagram showing an example of controlling switching signals in a display device according to an exemplary embodiment of the present disclosure to reduce or avoid an overlapping period in which a plurality of switching signals simultaneously flip to the conductive level.

[0143] Refer to Figure 9, the display device 100 according to an exemplary embodiment of the present disclosure may generate switching signals SS1, SS2, and SS3 for controlling a plurality of switching elements SW1, SW2, and SW3 constituting the data switching circuit 190 through the timing controller 140.

[0144] In this case, the first switching signal SS1 may include a plurality of first conduction periods T1 for turning on the first switching element SW1, the second switching signal SS2 may include a plurality of second conduction periods T2 for turning on the second switching element SW2, and the third switching signal SS3 may include a plurality of third conduction periods T3 for turning on the third switching element SW3.

[0145] A first buffer period T1B for flipping the first switching signal SS1 of the cut-off level to the conduction level within a predetermined time may be included between the plurality of first conduction periods T1 for turning on the first switching element SW1. Here, the first buffer period T1B may at least partially overlap with the second conduction period T2 during which the second switching element SW2 is turned on or the third conduction period T3 during which the third switching element SW3 is turned on.

[0146] In this case, the first conduction period T1 during which the first switching signal SS1 flips to the conduction level may overlap with the second buffer period T2B of the second switching signal SS2 or the third buffer period T3B of the third switching signal SS3. Here, the time when the first switching signal SS1 flips to the conduction level overlaps with the time when the third switching signal SS3 flips to the conduction level in the third buffer period T3B.

[0147] In this case, the timing controller 140 may eliminate the first flip period T1T between the first buffer period T1B and the first conduction period T1. In other words, when it is determined that the time when the first switching signal SS1 flips to the conduction level overlaps with the time when the third switching signal SS3 flips to the conduction level in the third buffer period T3B, the timing controller 140 may maintain the first buffer period T1B and the first conduction period T1 at a constant conduction level without generating the first flip period T1T between the first buffer period T1B and the first conduction period T1. In this case, since the first flip period T1T corresponds to a period during which the data voltage Vdata is not supplied to the first switching element SW1, the quality of the image emitted by the display panel 110 is not affected.

[0148] As a result, since the overlapping period during which the first switching signal SS1 and the third switching signal SS3 simultaneously flip to the conduction level can be eliminated, noise for the plurality of switching signals SS1, SS2, and SS3 can be effectively eliminated using one pseudo signal PS.

[0149] In addition, a second buffer period T2B for switching a second switch signal SS2 of a cut-off level to a conductive level within a predetermined time may be included between a plurality of second conduction periods T2 for turning on a second switching element SW2. In this case, the second buffer period T2B may at least partially overlap with a first conduction period T1 during which a first switching element SW1 is turned on or a third conduction period T3 during which a third switching element SW3 is turned on.

[0150] In addition, a second conduction period T2 during which the second switch signal SS2 is flipped to the conductive level may overlap with a first buffer period T1B of the first switch signal SS1 or a third buffer period T3B of the third switch signal SS3. An example in which the time when the second switch signal SS2 is flipped to the conductive level overlaps with the time when the first switch signal SS1 is flipped to the conductive level during the first buffer period T1B is shown here.

[0151] In this case, the timing controller 140 may eliminate a second flip period T2T between the second buffer period T2B and the second conduction period T2. In other words, when it is determined that the time when the second switch signal SS2 is flipped to the conductive level and the time when the first switch signal SS1 is flipped to the conductive level during the first buffer period T1B overlap, the timing controller 140 may maintain the second buffer period T2B and the second conduction period T2 at the same conductive level without generating a second flip period T2T between the second buffer period T2B and the second conduction period T2.

[0152] As a result, since an overlapping period during which the second switch signal SS2 and the first switch signal SS1 are simultaneously flipped to the conductive level can be eliminated, noise for a plurality of switch signals SS1, SS2, and SS3 can be effectively eliminated using one pseudo signal PS.

[0153] In addition, a third conduction period T3 during which the third switch signal SS3 is flipped to the conductive level may overlap with a first buffer period T1B of the first switch signal SS1 or a second buffer period T2B of the second switch signal SS2. An example in which the time when the third switch signal SS3 is flipped to the conductive level overlaps with the time when the second switch signal SS2 is flipped to the conductive level during the second buffer period T2B is shown here.

[0154] In this case, the timing controller 140 may eliminate the third transition period T3T between the third buffer period T3B and the third conduction period T3. In other words, when it is determined that the time at which the third switching signal SS3 flips to the conduction level and the time at which the second switching signal SS2 flips to the conduction level in the second buffer period T2B overlap with each other, the timing controller 140 may maintain the third buffer period T3B and the third conduction period T3 at the same conduction level without generating a third transition period T3T between the third buffer period T3B and the third conduction period T3.

[0155] As a result, since the overlapping period in which the third switching signal SS3 and the second switching signal SS2 simultaneously flip to the conduction level can be eliminated, noise for the plurality of switching signals SS1, SS2, and SS3 can be effectively eliminated using one pseudo signal PS.

[0156] Figure 10 is a block diagram showing a structure for generating a pseudo signal and a plurality of switching signals in a display device according to an exemplary embodiment of the present disclosure.

[0157] Referring to Figure 10 , a display device 100 according to an exemplary embodiment of the present disclosure may include: a timing controller 140 that generates a plurality of switching signals SS1, SS2, and SS3; a pseudo signal generation circuit 180 that generates a pseudo signal PS using the plurality of switching signals SS1, SS2, and SS3; a data switching circuit 190 that selectively provides a data voltage Vdata according to the plurality of switching signals SS1, SS2, and SS3; and a display panel 110, wherein switching signal lines for transmitting the plurality of switching signals SS1, SS2, and SS3 and a pseudo signal line for transmitting the pseudo signal PS are formed in a border area. Although the timing controller 140 and the pseudo signal generation circuit 180 are shown as separate blocks, the embodiment is not limited thereto. As an example, the timing controller 140 and the pseudo signal generation circuit 180 may be integrated into a single controller.

[0158] The timing controller 140 generates a plurality of switching signals SS1, SS2, and SS3 for controlling a plurality of switching elements SW1, SW2, and SW3 that constitute the data switching circuit 190. In this case, as described above, when it is determined that there is an overlapping period in which at least two of the plurality of switching signals SS1, SS2, and SS3 simultaneously flip to the conductive level, the timing controller 140 can eliminate the flip period between the buffer period and the conductive period for the switching signals including the overlapping period, thereby reducing or preventing the plurality of switching signals SS1, SS2, and SS3 from simultaneously flipping to the conductive level. The embodiments are not limited thereto. As an example, the timing controller 140 can generate the switching signals SS1, SS2, and SS3 such that there is no overlapping period in which at least two of the plurality of switching signals SS1, SS2, and SS3 simultaneously flip to the conductive level.

[0159] The data switching circuit 190 may include a plurality of switching elements SW1, SW2, and SW3 controlled by a plurality of switching signals SS1, SS2, and SS3. The data switching circuit 190 may further include an amplifier for maintaining the levels of the plurality of switching signals SS1, SS2, and SS3 and the pseudo signal PS at the same level, or a phase delay circuit for matching the phases of the plurality of switching signals SS1, SS2, and SS3 and the pseudo signal PS.

[0160] In the border area of the display panel 110, a switching signal line for transmitting a plurality of switching signals SS1, SS2, and SS3 and a pseudo signal line for transmitting the pseudo signal PS may be formed.

[0161] The display device 100 according to the present disclosure can reduce or prevent the plurality of switching signals SS1, SS2, and SS3 from simultaneously flipping to the conductive level, and thus can form only one pseudo signal line to eliminate noise caused by the plurality of switching signals SS1, SS2, and SS3 transmitted through a plurality of switching signal lines.

[0162] Figure 11 is a view showing an example of a pseudo signal generation circuit and a driving table in a display device according to an exemplary embodiment of the present disclosure. Figure 12 is a view showing waveforms of a plurality of switching signals and a pseudo signal generated from a pseudo signal generation circuit in a display device according to an exemplary embodiment of the present disclosure.

[0163] Refer to Figure 11 and Figure 12 , the timing controller 140 of the display device 100 according to an exemplary embodiment of the present disclosure can eliminate the flip period between the buffer period and the conductive period for the switching signals including the overlapping period, thereby reducing or preventing the plurality of switching signals SS1, SS2, and SS3 from simultaneously flipping to the conductive level.

[0164] The pseudo signal generation circuit 180 may include an XOR logic gate and an inverter.

[0165] In this case, the XOR logic gate generates a switched output signal SSO of a low level L only during a period in which an odd number of the switched signals SS1, SS2, and SS3 transmitted from the timing controller 140 are applied at the conductive level L, and generates a switched output signal SSO of a high level H during a period in which an even number of the switched signals are applied at the conductive level L.

[0166] The inverter inverts the switched output signal SSO.

[0167] Accordingly, the pseudo signal PS output through the pseudo signal generation circuit 180 exhibits a high level H only during a period in which an odd number of the switched signals are applied at the conductive level L.

[0168] In other words, since the timing controller 140 generates a plurality of switched signals SS1, SS2, and SS3 that do not simultaneously flip to the conductive level, the display device 100 according to the present disclosure may eliminate noise caused by the plurality of switched signals SS1, SS2, and SS3 through one pseudo signal PS generated by the pseudo signal generation circuit 180 including an XOR logic gate and an inverter. The embodiment is not limited thereto. As an example, as long as the pseudo signal generation circuit 180 outputs the pseudo signal PS exhibiting a high level H only during a period in which an odd number of the switched signals are applied at the conductive level L, the pseudo signal generation circuit 180 may include any logic gate other than an XOR logic gate and an inverter.

[0169] Figure 13 is a graph showing results of eliminating noise through one pseudo signal in a case of time overlap of flipping of some of a plurality of switched signals and a case in which the plurality of switched signals do not simultaneously switch in a display device according to an exemplary embodiment of the present disclosure.

[0170] Referring to Figure 13 , in the display device 100 according to an exemplary embodiment of the present disclosure, when there is an overlapping period in which a plurality of switched signals SS1, SS2, and SS3 simultaneously flip to the conductive level, it may be difficult to effectively eliminate noise using one pseudo signal PS (case (a)).

[0171] However, when the timing controller 140 generates the plurality of switched signals SS1, SS2, and SS3 such that they do not simultaneously flip to the conductive level, it can be recognized that noise caused by the plurality of switched signals SS1, SS2, and SS3 is effectively eliminated through one pseudo signal PS (case (b)).

[0172] Embodiments of the above disclosure will be briefly described below.

[0173] A display device according to an exemplary embodiment of the present disclosure may include: a display panel including a plurality of sub-pixels formed in a display area and a dummy signal line and a plurality of switching signal lines formed in a border area; a data switching circuit including a plurality of switching elements for controlling data voltages supplied to the display panel; a timing controller for transmitting a plurality of switching signals for controlling the plurality of switching elements through the plurality of switching signal lines; and a dummy signal generation circuit for generating a dummy signal supplied to the dummy signal line using the plurality of switching signals.

[0174] The dummy signal line may be disposed along an area adjacent to a data driving circuit to which a data voltage is applied.

[0175] The plurality of switching signal lines may be disposed between the data driving circuit and the dummy signal line.

[0176] The plurality of switching elements may include a first switching element connected between a first data channel and a data line of a red sub-pixel, a second switching element connected between the first data channel and a data line of a green sub-pixel, and a third switching element connected between the first data channel and a data line of a blue sub-pixel.

[0177] The plurality of switching elements may include P-type MOS transistors.

[0178] The plurality of switching signals may include: a conduction period for turning on the plurality of switching elements; and a buffer period between the conduction periods and for switching a signal of a cut-off level to a conduction level within a predetermined time.

[0179] The timing controller may be controlled not to generate an overlapping period in which a plurality of switching signals simultaneously flip to the conduction level.

[0180] The timing controller may eliminate a flip period between the buffer period and the conduction period.

[0181] When it is determined that a time at which a first switching signal among the plurality of switching signals flips to the conduction level overlaps with a time at which a second switching signal flips to the conduction level during the buffer period, the timing controller may hold a period between the buffer period and the conduction period of the first switching signal at the conduction level.

[0182] The dummy signal generation circuit may include: a logic gate for generating a low-level switching output signal only during a period in which an odd number of switching signals among the plurality of switching signals are applied at the conduction level; and an inverter for generating a dummy signal by inverting the switching output signal.

[0183] The logic gate may be an XOR gate.

[0184] The data switching circuit may further include an amplifier for maintaining levels of the plurality of switching signals and the dummy signal at the same level.

[0185] The data switching circuit may further include a phase delay circuit that matches the phases of a plurality of switching signals and a dummy signal.

[0186] A display panel according to the present disclosure may include: a plurality of sub-pixels formed in a display area; a plurality of switch signal lines formed in a border area to transmit a plurality of switching signals; a dummy signal line located outside the plurality of switch signal lines and transmitting a dummy signal having a phase opposite to that of at least some of the plurality of switching signals; and a data switching circuit including a plurality of switching elements that control data voltages transmitted through data lines according to the plurality of switching signals.

[0187] The plurality of switching signals may be controlled such that there is no overlapping period in which the plurality of switching signals simultaneously flip to a conductive level.

[0188] When it is determined that the time at which a first switching signal among the plurality of switching signals flips to a conductive level overlaps with the time at which a second switching signal flips to a conductive level during a buffer period, the plurality of switching signals may be held at the conductive level between the buffer period and the conductive period of the first switching signal.

[0189] The foregoing description has been presented to enable any person skilled in the art to make and use the inventive concepts of the present disclosure, and the foregoing description has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The foregoing description and the drawings have provided examples of the inventive concepts of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the inventive concepts of the present disclosure.

[0190] Cross-reference to Related Applications

[0191] This application claims the priority and benefit of Korean Patent Application No. 10-2023-0193988, filed on December 28, 2023, which is hereby incorporated by reference for all purposes as if fully set forth herein.

Claims

1. A display device, comprising: A display panel, the display panel comprising a plurality of sub-pixels formed in a display area, and a dummy signal line and a plurality of switch signal lines formed in a frame area; a data switching circuit, the data switching circuit comprising a plurality of switching elements configured to control a data voltage supplied to the display panel; a timing controller configured to provide a plurality of switching signals for controlling the plurality of switching elements through the plurality of switching signal lines; as well as A dummy signal generating circuit is configured to generate a dummy signal provided to the dummy signal line using the plurality of switching signals.

2. The display device according to claim 1, wherein: The dummy signal line is disposed along a region of the frame region adjacent to a data driving circuit configured to provide the data voltage.

3. The display device according to claim 2, wherein: The plurality of switch signal lines are disposed between the data driving circuit and the dummy signal lines.

4. The display device according to claim 2, wherein: The plurality of switching signal lines and the dummy signal lines extend along a side surface of a source film on which the data driving circuit is mounted.

5. The display device according to claim 1, wherein: The plurality of switch elements include: a first switch element, the first switch element being connected between the first data channel and the data line of the red sub-pixel; a second switch element, the second switch element being connected between the first data channel and a data line of a green sub-pixel; and A third switch element is connected between the first data channel and the data line of the blue sub-pixel.

6. The display device according to claim 1, wherein: The plurality of switch elements include P-type MOS transistors.

7. The display device according to claim 1, wherein: Each of the plurality of switch signals comprises: a conduction period for turning on a corresponding one of the plurality of switch elements; and A buffer period is provided between the on-periods and is used to switch the signal at the off-level to the on-level and maintain the on-level within a predetermined time.

8. The display device according to claim 7, wherein: The timing controller performs control so as not to generate an overlapping period in which at least two of the plurality of switching signals simultaneously flip to the on-level.

9. The display device according to claim 7, wherein: The timing controller eliminates a transition period between the buffer period and the turn-on period of at least one switching signal among the plurality of switching signals.

10. The display device according to claim 9, wherein: A time at which the at least one switching signal turns over to the on-level in the on-period and a time at which another switching signal among the plurality of switching signals turns over to the on-level in the buffer period overlap with each other.

11. The display device according to claim 9, wherein: The inversion period corresponds to a standby state in which the corresponding switching element controlled by the at least one switching signal waits for input of the data voltage.

12. The display device according to claim 7, wherein: Based on the overlap between the time when the first switch signal among the multiple switch signals flips to the conduction level in the conduction period and the time when the second switch signal among the multiple switch signals flips to the conduction level in the buffer period, the timing controller maintains the period between the buffer period and the conduction period of the first switch signal at the conduction level.

13. The display device according to claim 7, wherein: The on-period of a first switching signal among the plurality of switching signals is separated from the on-period of at least one switching signal among the remaining switching signals among the plurality of switching signals, and the buffer period of the first switching signal overlaps with the on-period of the at least one switching signal.

14. The display device according to claim 13, wherein: The turn-on period of the first switching signal overlaps with the buffer period of the at least one switching signal.

15. The display device according to claim 1, wherein: The pseudo signal generating circuit comprises: a logic gate configured to generate a low-level switch output signal in a period in which an odd number of switch signals among the plurality of switch signals are applied at an on-level; and An inverter is configured to generate the pseudo signal by inverting the switch output signal.

16. The display device according to claim 15, wherein: The logic gate is a XOR gate.

17. The display device according to claim 1, wherein: The pseudo signal generating circuit is configured to generate the pseudo signal of the off-level during a period in which an odd number of switch signals among the multiple switch signals are applied at the on-level, and to generate the pseudo signal of the on-level during a period in which an even number of switch signals among the multiple switch signals are applied at the on-level.

18. The display device according to claim 1, wherein: The data switching circuit further includes an amplifier configured to maintain levels of the plurality of switching signals and a level of the dummy signal at the same level.

19. The display device according to claim 1, wherein: The data switching circuit further includes a phase delay circuit configured to match phases of the plurality of switching signals with a phase of the dummy signal.

20. A display panel, comprising: a plurality of sub-pixels, the plurality of sub-pixels being formed in a display area; a plurality of switch signal lines formed in the frame area to transmit a plurality of switch signals; a dummy signal line, the dummy signal line being located outside the plurality of switch signal lines and transmitting a dummy signal having a phase opposite to that of at least some of the plurality of switch signals; as well as A data switching circuit includes a plurality of switching elements configured to control a data voltage transmitted through the data line according to the plurality of switching signals.

21. The display panel according to claim 20, wherein: The dummy signal line is disposed along a region of the frame region adjacent to a data driving circuit configured to provide the data voltage.

22. The display panel according to claim 21, wherein: The plurality of switch signal lines are disposed between the data driving circuit and the dummy signal lines.

23. The display panel according to claim 20, wherein: Each of the plurality of switch signals comprises: a conduction period, the conduction period being used to turn on a corresponding one of the plurality of switch elements; and A buffer period is provided between the on-periods and is used to switch the signal at the off-level to the on-level and maintain the on-level within a predetermined time.

24. The display panel according to claim 23, wherein: The plurality of switch signals are controlled so as not to generate an overlapping period in which at least two switch signals among the plurality of switch signals are simultaneously switched to the on-level.

25. The display panel according to claim 23, wherein: Based on the overlap between the time when a first switch signal among the multiple switch signals flips to the conduction level in the conduction period and the time when a second switch signal among the multiple switch signals flips to the conduction level in the buffer period, the multiple switch signals are maintained at the conduction level between the buffer period and the conduction period of the first switch signal.

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