Pad design for interconnect bridge in package substrate

Abstract

The invention discloses a pad design for an interconnect bridge in a package substrate. Semiconductor chip package substrates having interconnect bridges, assemblies including these semiconductor chip package substrates, and methods of manufacturing semiconductor chip package substrates including interconnect bridges are provided. The interconnect bridge may include a through-bridge via electrically coupled to the semiconductor package substrate. The embedded bridge may be aligned with a reference within the semiconductor package substrate.

Description

Technical Field

[0001] The description generally relates to semiconductor manufacturing, and more particularly to packaging semiconductor chips, packaging substrates for semiconductor chips, and interconnect bridges. Background Art

[0002] Semiconductor chips are at the heart of intelligent devices and systems such as personal computers, laptops, tablets, phones, servers, and other consumer and industrial products and systems. Manufacturing semiconductor chips presents many challenges, and these challenges are amplified as devices become smaller and performance requirements increase. Challenges include, for example, unwanted material interactions, precision and scaling requirements, power delivery requirements, limited fault tolerance, and material and manufacturing costs.

[0003] High-performance computing (HPC) applications, such as, for example, artificial intelligence (AI) inference and Chat Generative Pretrained Transformer (ChatGPT), are driving significant growth in packaging form factors. Proposals for computing systems for HPC applications include integrating six times the silicon reticule size and more than 16 high-bandwidth memory (HBM) units (die stacks) into the package. HBM can be composed of a stack of dynamic random access memory (DRAM) dies. A semiconductor chip package assembly including multiple semiconductor chips can include interconnect bridges, such as, for example, embedded multi-die interconnect bridges (EMIBs) in the package and / or EMIBs with through-bridge vias (EMIB-T) structures. The interconnect bridges can provide interconnections between semiconductor chips within the package. Brief Description of the Drawings

[0004] The figures are provided to aid in understanding the present invention. The figures may include diagrams and descriptions of exemplary structures, components, data, methods, and systems. For ease of explanation and understanding of these structures, components, data, methods, and systems, the figures are not an exhaustive detailed description. Thus, the figures should not be understood as depicting the overall boundaries and limits of possible structures, components, data, methods, and systems without departing from the scope of the present invention. Additionally, partly due to the small size of some features and the desire for clarity of the explanations in the figures, the features are not necessarily drawn to scale relative to each other.

[0005] Figure 1 A semiconductor package assembly including an interconnect bridge in a packaging substrate is illustrated.

[0006] Figures 2A to 2C A section of a semiconductor packaging substrate having an interconnect bridge is provided.

[0007] Figures 3A to 3D A method of manufacturing a semiconductor packaging substrate including an interconnect bridge is described.

[0008] Figure 4 An exemplary multi-chip package is shown, in which the package incorporates an interconnect bridge.

[0009] Figure 5 An exemplary computing system is provided.

[0010] The following is a description of specific details and implementations, including a non-limiting description of the figures depicting some examples and implementations. Detailed Description

[0011] References to one or more examples are to be understood as describing a particular feature, structure, or characteristic included in at least one implementation of the present invention. The phrases "an example" or "example" do not necessarily refer to the same example or embodiment. Any aspect described herein can potentially be combined with any other aspect or similar aspect described herein, whether or not the aspects are described with respect to the same figure or element.

[0012] The words "connected" and / or "coupled" can indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" can also mean that two or more elements are not in direct contact with each other and instead are separated by one or more elements, but they can still cooperate or interact with each other physically, magnetically, or electrically, for example.

[0013] The words "first", "second", and the like do not denote order, quantity, or importance, but rather are used to distinguish one element from another. The word "a" or "an" in this document does not denote a limitation of quantity, but rather indicates the presence of at least one of the items being referenced. The terms "subsequent" or "after" can indicate immediately following or succeeding some other event or events. According to alternative embodiments, other sequences of operations can also be performed. Further, additional operations can be added or removed depending on the application.

[0014] Disjunctive language such as the phrase "at least one of X, Y, or Z" is generally used to indicate that an element or feature can be X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, this disjunctive language should be understood as not implying that a particular embodiment requires the presence of each of at least one of X, at least one of Y, or at least one of Z.

[0015] The flowcharts illustrated herein provide examples of sequences of various processing actions. The flowcharts may indicate operations performed by software or firmware routines, as well as physical operations. The physical operations may be performed by semiconductor processing equipment. Although shown in a particular order or sequence, the order of actions may be modified unless otherwise specified. Accordingly, the illustrated diagrams should be understood only as examples, and the processing may be performed in a different order, and some actions may be performed in parallel. Additionally, one or more actions may be omitted, and not all implementations will perform all actions.

[0016] The various components described may be units for performing the described operations or functions. Each component described may include software, hardware, or a combination thereof. Some components may be implemented as software modules, hardware modules, dedicated hardware (e.g., application-specific hardware, application-specific integrated circuits (ASICs), digital signal processors (DSPs), etc., embedded controllers, or hardwired circuits). Other components may be semiconductor processing and / or test equipment capable of performing physical operations such as, for example, lithography, laser drilling, electroplating, chemical vapor deposition, atomic layer deposition, and / or sputtering, chemical mechanical polishing, and / or etching.

[0017] To the extent that various computer operations or functions are described herein, they may be described or defined as software code, instructions, configurations, and / or data. The software content may be provided via a manufactured article having the content stored thereon, or via a method of operating a communication interface to send data via the communication interface. A machine-readable storage medium may cause a machine to perform the described functions or operations. A machine-readable storage medium includes any mechanism that stores information in a tangible form accessible by a machine (e.g., a computing device), such as a recordable / non-recordable medium (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices). The instructions may be stored on the machine-readable storage medium in a non-transitory form. A communication interface includes any mechanism that interfaces with, for example, a hardwired, wireless, or optical medium to communicate with another device, such as, for example, a memory bus interface, a processor bus interface, an Internet connection, a disk controller.

[0018] Terms such as chip, die, IC (integrated circuit) chip, IC die, microelectronic chip, microelectronic die, semiconductor die, and / or semiconductor chip are interchangeable and refer to semiconductor devices that include integrated circuits.

[0019] Semiconductor chip manufacturing processes are sometimes divided into front-end-of-line (FEOL) processes and back-end-of-line (BEOL) processes. The electronic circuits and active and passive devices within the chip, such as transistors, capacitors, resistors, and / or memory cells, for example, are fabricated in a process known as FEOL processing. Memory cells include, for example, electronic circuits for random access memory (RAM) (such as static RAM (sRAM), dynamic RAM (DRAM)), read-only memory (ROM), non-volatile memory, and / or flash memory. FEOL processing can be, for example, complementary metal oxide semiconductor (CMOS) processing. BEOL processing includes metallization of the chip, where interconnects are formed in layers and the feature size of the interconnects increases in the layers closer to the semiconductor chip surface. For example, the interconnects in a semiconductor chip integrated into a heterogeneous package (such as a package including a memory and a logic chip) can also include through-silicon vias (TSVs) that pass through the device region of the semiconductor chip. Semiconductor devices with TSVs can blur the distinction between BEOL processing and FEOL processing.

[0020] Semiconductor chip interconnects can be created by etching a trench or via structure into a dielectric layer and filling the trench or via with metal to form a trench or through-layer via. The dielectric layer can include, for example, a low-k dielectric, SiO2, silicon nitride (SiN), silicon carbide (SiC), and / or silicon carbonitride (SiCN). Low-k dielectrics include, for example, fluorine-doped SiO2, carbon-doped SiO2, porous SiO2, porous carbon-doped SiO2, combinations of the foregoing materials, and also these materials with air gaps. A dielectric layer including metal features can be an interlayer dielectric (ILD) feature.

[0021] The terms "package", "assembly", "IC package" or "chip package", "microelectronic package" or "semiconductor chip package" are interchangeable and generally refer to an enclosed carrier for one or more dies, where the dies are attached to a package substrate and encapsulated. The package substrate provides electrical interconnects between the die(s) and other dies and / or a motherboard, board, mainboard, logic board, or printed circuit board (PCB) for I / O (input / output) communication and power delivery. For example, a package with multiple dies can be a system-in-package.

[0022] A packaging substrate generally includes a dielectric layer or a structure having a conductive structure, the conductive structure being located on, through, and / or embedded in the dielectric layer. The dielectric layer can be, for example, a build-up layer. Dielectric materials include Ajinomoto Build-up Film (ABF), although other dielectric materials are possible. A semiconductor packaging substrate can have a core or be coreless. A semiconductor package with a core can have dielectric layers, such as build-up layers, on more than one side of the core, such as on two opposite sides of the core. The core can include through-core vias containing conductive material. Within the packaging substrate, other structures or devices are also possible.

[0023] A "core" or "package core" generally refers to a layer that is typically embedded within a packaging substrate. The core can provide structure or stiffness to the packaging substrate. The core is an optional feature of the packaging substrate. The core can be a dielectric organic or inorganic material and can have conductive vias extending through the layer. The conductive vias can include metals, such as copper. The package core can be composed of, for example: glass materials (such as aluminosilicate, borosilicate, aluminoborosilicate, silica, and fused silica), silicon, silicon nitride, silicon carbide, gallium nitride, or alumina. In some examples, the core material is a glass fiber-reinforced organic resin, such as an epoxy-based resin. A further example of a packaging substrate core is FR4 (woven glass fiber-reinforced epoxy resin). In other examples, the packaging substrate core is a solid amorphous glass material.

[0024] In a further example of a packaging substrate core, the substrate core is a glass core including a solid amorphous glass material. The glass substrate core can include glass, such as aluminosilicate, borosilicate, aluminoborosilicate, silica, and fused silica, and additionally can optionally include one or more of the following: Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and / or Zn. In a further example of the glass core, the glass can include silicon and oxygen, and optionally any one or more of the following: aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and / or zinc. In some examples, the glass packaging substrate core includes at least 23% silicon and at least 26% oxygen by weight. In a further example, the glass packaging substrate core includes at least 23% silicon, at least 26% oxygen, and at least 5% aluminum by weight.

[0025] Additionally, an exemplary solid-state amorphous glass substrate core can be considered to have a rectangular prism volume. The rectangular prism volume can contain through-holes that have been filled with one or more different materials. The material in the through-holes can be a conductive metal, such as copper. The thickness of the exemplary solid-state amorphous glass substrate core can have a thickness in the range of 50 μm to 1.4 mm. Additionally, the package substrate can include a multi-layer glass substrate. The package substrate in this example can be a coreless substrate. The multi-layer glass substrate can have a thickness, for example, in the range of 25 μm to 50 μm. Further, the glass substrate core can have a side dimension of 10 mm to 250 mm. For example, the substrate core can be 10 mm × 10 mm up to 250 mm × 250 mm in two dimensions, but the substrate core does not necessarily have to have the same value in these two dimensions.

[0026] The package substrate can include interconnect bridges, such as, for example, an embedded multi-die interconnect bridge (EMIB) and an EMIB that includes through-bridge vias (TBVs) that can be referred to as EMIB-Ts. Interconnect bridges have proven to be a cost-effective packaging technology, and components that include interconnect bridges are sometimes referred to as 2.5D components. Interconnect bridges can enable heterogeneous semiconductor device integration and improve high-performance computing at the system level. Interconnect bridges that include TBVs can enable direct power delivery through the bridge die, which can further improve the performance of the system.

[0027] A packaged substrate may include one or more interconnect bridges. The interconnect bridges may be partially, fully, or not embedded in the packaged substrate. The interconnect bridges provide interconnections between chips accommodated on the packaged substrate. The interconnections can be used for I / O between chips. Some interconnect bridges, such as those with metal through-bridge vias, can also supply power to the operatively connected chips. The interconnect bridges may include regions with traces having a smaller width dimension (the minimum dimension of the traces), a smaller height dimension, and / or a smaller length dimension compared to the vias and traces of the surrounding packaged substrate. For example, in some regions, the width dimension (or minimum dimension) may be 3 μm or less and / or 10 μm or less. The interconnect bridges may also have a smaller trace pitch than the surrounding packaged substrate. For example, in some regions, the center-to-center pitch of the traces may be 3 μm and / or less, or 10 μm or less. The bridge may include, for example, a silicon substrate, a silicon-on-insulator substrate, a float glass substrate, a borosilicate glass substrate, a silica substrate, and / or a silicon nitride substrate. The substrate may include, for example, one or more dielectric layers composed of silicon oxide, silicon nitride, silicon oxynitride, carbon-doped oxide, methylsilsesquioxane, hydrogen silsesquioxane, dieback film (DBF), epoxy film, B-stage epoxy film, other dielectric materials. The bridge may also be a coreless substrate composed of multiple dielectric layers. The dielectric layers may be, for example, dieback film (DBF), epoxy film, B-stage epoxy film, other dielectric materials. Other materials are possible.

[0028] For a package including interconnect bridges, the pitch in the interconnect bridge region for the first-level interconnect (FLI) assembly may be smaller than the pitch in other regions of the FLI assembly. The pitch in the interconnect bridge region may be, for example, less than or equal to 25 μm. In a mixed-pitch system where there is a pitch less than or equal to 25 μm, it may be more difficult to achieve a low regression bump thickness variation (rBTV). A larger rBTV may negatively affect the package component yield.

[0029] Thermal compression bonding (TCB) may use solder on the die, or on both the die and the packaged substrate, to form solder bump FLI. Chip gap height (CGH) control across the die-to-substrate plane is crucial and can be compensated for by pre-measuring the rBTV and the bonding head tilt to achieve quality-controlled collapsed chip connection (C4) bonding. After forming the solder bump FLI, epoxy underfill is dispensed to encapsulate the C4 interface to enhance reliability.

[0030] The encapsulation substrate manufacturing process includes laser drilling and lithography processes that may cause via-to-pad overlap errors. These overlap errors may cause a shift in the true position of the first-level interconnect bumps relative to the bumps on the encapsulation substrate for the interconnect bridges. The bump true position shift may be as large as 20 μm. The overlap errors may have a significant negative impact on the encapsulation process yield.

[0031] Figure 1 A cross-sectional view of an assembly including an encapsulation substrate 105 and semiconductor chips 110 and 111 is shown. The encapsulation substrate 110 includes an interconnect bridge 115. The interconnect bridge 115 includes a through-bridge via 132. The interconnect bridge 115 contains metal vias and traces 131 that allow the operatively connected semiconductor chips 110 and 111 to communicate with each other. The interconnect bridge 115 includes a metal through-bridge via (TBV) 132 that can supply power, and the interconnect bridge 115 can be, for example, an EMIB-T. In this example, the encapsulation substrate 105 includes an encapsulation substrate core 120, which can be an organic core or a glass core as described herein. The encapsulation substrate 105 can also be a coreless encapsulation substrate, and the encapsulation substrate core 120 is optional. Additionally, the encapsulation substrate 105 has dielectric regions 124, 125, and 126, which can be one or more dielectric layers (such as build-up layers) having metal traces and vias 130 and board-side pads 135. The board-side pads 135 can be connected to a board (e.g., a motherboard, a PCB, a system board, a logic board, or a main board). The connection to the board can be a through-solder joint. The metal traces and vias 130 can be made of, for example, copper.

[0032] The interconnect bridge 115 is connected to a subset of the metal traces and vias 130 through a conductive interconnect 140, which can be made of, for example, solder. The solder can be, for example, a tin-based alloy including silver. The encapsulation-side interconnect for the interconnect bridge 115 also includes a landing pad surface coating 145 on the encapsulation-side interconnect bridge landing pad 144. The landing pad surface coating 145 can change the contact behavior of the metal interconnect 140 such that the metal interconnect 140 partially surface-wets, fully surface-wets, or surface- and side-wall-wets the encapsulation-side interconnect bridge landing pad 144. The landing pad surface coating 145 can be a material such as, for example, NiPdAu, NiAu, and / or organic solderability preservative (OSP). The landing pad surface coating 145 can be a layer of a material such as a metal, where the surface layer is Au. The organic solderability protection compound for the surface coating can be an azole, such as benzotriazole, imidazole, and benzimidazole. The encapsulation-side interconnect bridge landing pad 144 is shown in the "N2" build-up layer of the encapsulation substrate 105 in this illustration. Other designs for the encapsulation substrate 105 are possible, such as, for example, a design where the encapsulation-side interconnect bridge landing pad 144 is in the N3 or N4 layer.

[0033] As further illustrated in Figures 2A to 2C the greater size of the interconnect-bridge side package landing pad 147 relative to the package side interconnect-bridge landing pad 144 allows misalignment of the interconnect-bridge side package landing pad 147 and the package side interconnect-bridge landing pad 144 during the bonding between the interconnect bridge 115 and the package substrate 105. Advantageously, the misalignment with respect to the N2 layer interconnect region (in this example) allows alignment of the chip side interconnect-bridge landing pad 150 to the N1 layer of the quasi-package substrate 105 instead, which can facilitate the formation of the FLI in the case of semiconductor chips 110 and 111. The alignment of the chip side interconnect-bridge landing pad 150 can be accomplished, for example, with respect to an optional datum 155. The interconnections 160 and 161 between the semiconductor chips 110 and 111 can include solder, for example.

[0034] Figures 2A to 2C The features of a semiconductor package substrate including an interconnect bridge with a TBV 275 are further illustrated. In Figures 2A to 2C the numbers of the respective parts are in some cases the same as those for Figure 1 In cases where the numbers are the same in Figures 2A to 2C and in Figure 1 the description herein for Figure 1 can be used with respect to Figures 2A to 2C Figure 2A A section of a semiconductor package 205 is illustrated, which includes dielectric regions 125 and 126 that can be one or more dielectric layers (such as stacked layers) with metal traces and vias 130. The section of the semiconductor package 20 has an interconnect bridge 115 including traces 131 and a TBV 270. In Figure 2A a partial view of a portion of the package substrate 105 illustrates a possible misalignment between the package side interconnect-bridge landing pad 144 and the interconnect-bridge side package landing pad 147. The center-to-center misalignment indicated by the dashed lines and the distance “A” (the separation between the dashed lines) in Figure 2A can be in the range of 0 μm to 30 μm, in the range of 5 μm to 30 μm, or in the range of 10 μm to 30 μm. The center-to-center misalignment indicated by “A” allows alignment of the landing pads 270 associated with the interconnect bridge on the package substrate 205 with the landing pads 275 associated with the package substrate, as indicated by the arrows “B” and “C”.

[0035] Figure 2B Illustrated is from Figure 2A ​Region 250 (delimited by dashed lines), which has been expanded along an axis, and for ease of explanation, the through-metal interconnect 140 has been removed. The possible misalignment between the package-side interconnect-bridge landing pads 144 and the interconnect-bridge-side package landing pads 147 is facilitated by the size difference between them. In Figure 2B "E" indicates the dimension between the package-side interconnect-bridge landing pads 144, which can be, for example, from 10 μm to 70 μm. The dimension indicated by "F" is the dimension between the interconnect-bridge-side package landing pads 147, which can be, for example, 10% to 200% times larger, 20% to 200% times larger, 50% to 200% times larger, or 75% to 200% times larger than the package-side interconnect-bridge landing pads 144. Depending on the pad footprint area, the dimension "E" and / or "F" can be, for example, the diameter of a circle or the side length of a rectangular shape if the pads have a circular shape or a rectangular shape on one side.

[0036] Figure 2C Illustrates some example configurations (251a, 251b, and 251c) of the interconnects in the Figure 2A region 251 (delimited by dashed lines). In the example configuration 251a, the landing pad surface coating 145a partially covers the surface of the interconnect-bridge-side package landing pad 147, and the interconnect region 140a is composed of a flowable material such as solder, and the solder has partially wetted the surface of the surface coating 145 of the interconnect-bridge-side package landing pad 147. In the example configuration 251b, the landing pad surface coating 145b covers the surface of the interconnect-bridge-side package landing pad 147, and the interconnect region 140b is composed of a flowable material such as solder, and the solder has wetted the surface of the surface coating 145 of the interconnect-bridge-side package landing pad 147. Partial or complete wetting of the surface of the surface coating 145 of the interconnect-bridge-side package landing pad 147 is possible, such as in configuration 251b. In the example configuration 251c, the landing pad surface coating 145c covers the surface and at least partially covers the sides of the interconnect-bridge-side package landing pad 147. The interconnect region 140c is composed of a flowable material such as solder, and the solder has wetted the surface of the interconnect-bridge-side package landing pad 147 and at least partially wetted the sides of the interconnect-bridge-side package landing pad 147. The solder can be, for example, a tin-based alloy including silver. The landing pad surface coatings 145a, 145b, and / or 145c can be materials such as, for example, NiPdAu, NiAu, and / or organic solderability preservative (OSP). The organic solderability protection compound for the surface coating can be azoles such as benzotriazole, imidazole, and benzimidazole. The landing pad surface coatings 145a, 145b, and / or 145c can be layers of materials such as metals, where the surface layer is Au.

[0037] Figures 3A to 3DA method for manufacturing a package substrate including an interconnect bridge having a TBV is described. In Figures 3A to 3D the numbers of the various parts are in some cases the same as those for Figure 1 . Where the numbers are the same in Figures 3A to 3D and in Figure 1 , the description herein for Figure 1 can be used with respect to Figures 3A to 3D . In Figure 3A , the partially completed package substrate 300 includes an optional package substrate core 120. However, the partially completed package substrate 300 can also be a coreless package substrate. Laser cavity drilling processing creates cavities 310 in the partially completed package substrate 300, thereby creating the partially completed package substrate 301. The laser cavity drilling processing exposes the interconnect bridge side package landing pads 147.

[0038] In Figure 3B , a surface coating 145 is applied to the exposed interconnect bridge side package landing pads 147 of the partially fabricated package substrate 301, creating the partially fabricated package substrate 302. In this example, the surface coating 145 is similar to the surface coating example configuration 251b of Figure 2C , however Figure 2C any one of the surface coating 145 configurations is possible (e.g., 251a or 251c). The surface coating 145 can be a material such as, for example, NiPdAu, NiAu, and / or organic solderability preservative (OSP). For NiPdAu and NiAu surface coating 145 materials, the final surface layer can be composed of Au. The surface coating 145 can be applied using electroless plating, electroplating, and / or other coating processes. The organic solderability protection compound for the surface coating can be azoles such as benzotriazole, imidazole, and benzimidazole. These azoles are typically water-soluble and can be applied, for example, in solution form.

[0039] An interconnect bridge 115 having vias and traces 131, a TBV 132, and solder 315 on the package side interconnect bridge landing pads 144 is placed into the cavities 310 of the partially fabricated package substrate 302. The solder can be, for example, a tin-based alloy including silver. The package side interconnect bridge landing pads 144 and the interconnect bridge side package landing pads 147 have as described herein, for example, with respect to Figures 2A to 2CThe described pad size differences. The larger size of the interconnect bridge side package landing pad 147 can allow the interconnect bridge 115 to align with the optional datum 155 or other features of the partially fabricated package substrate 302, rather than aligning with the interconnect bridge side package landing pad 147 during assembly. The interconnect bridge 115 is attached to the partially fabricated package substrate 302 by a solder 315 wetting the surface coating 145 of the interconnect bridge side package landing pad 147, which creates a metal interconnect 140. Bonding the interconnect bridge 115 to the package substrate can be achieved by a thermocompression bonding process that utilizes heat and pressure as well as precise control of solder collapse and chip gap height. A underfill material is placed between the interconnect bridge 115 and the partially fabricated package substrate 302, creating Figure 3C the partially fabricated package substrate 303. Different underfill processes and materials are possible and can be applied during or after the die attach process. These include, for example, capillary underfill (CUF), molded underfill (MUF), non-conductive film (NCF), and non-conductive paste (NCP).

[0040] In Figure 3C , a dielectric layer 126 can be deposited or laminated onto the surface of the partially fabricated package substrate 303. The dielectric layer 125 can be, for example, ABF. Via cavities 360 and 361 can be laser drilled into the dielectric layer 126 to form the partially fabricated package substrate 304. The vias can also be formed by a dry reactive ion etching process. Conductive material is deposited into the via cavities 360 and 361 to create Figure 3D the package substrate 105. The conductive material can be, for example, copper. The deposition can be accomplished by an electroplating process. Bonding pads 170 and 171 (FLI bonding pads) can be formed, for example, on the surface of the vias by lateral overgrowth of a metallic material during electroplating, or they can be patterned using a deposition mask lithography. Interconnect materials such as solder are attached to (or deposited through a mask on) the FLI bonding pads 170 and 171, forming interconnects 160 and 161 for semiconductor chip attachment. A thermocompression bonding process can be used for semiconductor chip attachment.

[0041] Figure 4 An exemplary configuration for a packaged semiconductor chip mounted on a board is shown. Many other configurations are possible. Figure 4 can be considered a top-down view relative to Figure 1 , and Figure 1 can be considered a cross-sectional view of the packaged semiconductor chip. In Figure 4In this case, a board 405 (e.g., a motherboard, a printed circuit board, a system board, a logic board, a circuit board, or a main board) has packaged semiconductor chips 410 and 415 operatively coupled to the board 405. An interconnect bridge 425 is shown in dashed lines and is covered by the packaged semiconductor chips 410 and 415 in this view. The interconnect bridge 425 can be more than one interconnect bridge, can be an interconnect bridge with or without a TBV, and the semiconductor chip package substrate can include more than one type of interconnect bridge. As described herein with respect to Figure 1 , Figures 2A to 2C and Figures 3A to 3D the interconnect bridge can be mounted in the package substrate. For example, one or more of the chips 410 can be a processor or a field programmable gate array (FPGA), and one or more of the chips 415 can be an HBM die stack and / or and one or more of the chips 415 can be a transceiver die.

[0042] The semiconductor chips 110, 111, 410, and 415 can be, for example, any combination of the following: a microprocessor, a CPU (central processing unit), a GPU (graphics processing unit), a processing core, a system-on-chip, other processing hardware, a combination of processors or processing cores, a programmable general or special-purpose microprocessor, an accelerator, a DSP, I / O management, a programmable controller, an ASIC, a programmable logic device (PLD), an HBM die stack, and / or other memory devices. The semiconductor chips 110, 111, 410, and 415 can be, for example, any one of the chips described herein with respect to Figure 5 The interconnect bridge assemblies described herein can generally be used between semiconductor chips in various package configurations, and the foregoing examples are not meant to limit the possible component types.

[0043] Figure 5 An example computing system is depicted. The computing system can be a system used to operate equipment in a semiconductor manufacturing facility. For example, instructions for operating semiconductor processing equipment or for performing one or more aspects of the processing described in Figures 3A to 3D can be stored and / or run on the computing system. The computing system employed can include more, different, or fewer features compared to the computing systems described with respect to Figure 5 The computing systems described herein can include more, different, or fewer features compared to the computing systems described with respect to

[0044] The computing system 500 includes a processor 510 that provides processing, operation management, and execution of instructions for the system 500. The processor 510 can include any type of microprocessor, CPU (Central Processing Unit), GPU (Graphics Processing Unit), processing core, or other processing hardware that provides processing for the system 500, or a combination of processors or processing cores. The processor 510 controls the overall operation of the system 500 and can be or can include one or more programmable general or special microprocessors, DSPs, programmable controllers, ASICs, or programmable logic devices (PLDs), etc., or a combination of such devices.

[0045] In one example, the system 500 includes an interface 512 coupled to the processor 510. The interface 512 can represent a higher-speed interface or a high-throughput interface for system components that require a higher-bandwidth connection, such as the memory subsystem 520 or the graphics interface component 540 and / or the accelerator 542. The interface 512 represents interface circuitry that can be a separate component or integrated onto the processor die. When present, the graphics interface 540 interfaces to a graphics component for providing a visual display to a user of the system 500. In one example, the display can include a touchscreen display.

[0046] The accelerator 542 can be a fixed-function or programmable offload engine that can be accessed or used by the processor 510. For example, the accelerators among the accelerators 542 can provide data compression (DC) capabilities, cryptographic services such as public-key encryption (PKE), cryptography, hash / authentication capabilities, decryption, or other capabilities or services. In some cases, the accelerator 542 can be integrated into the CPU socket (e.g., into the connector of a motherboard (or circuit board, printed circuit board, main board, system board, or logic board) that includes the CPU and provides an electrical interface to the CPU). For example, the accelerator 542 can include a single-core or multi-core processor, a graphics processing unit, a logic execution unit, a single-level or multi-level cache, functional units available for independent execution of programs or threads, an application-specific integrated circuit (ASIC), a neural network processor (NNP), programmable control logic, and programmable processing elements such as field-programmable gate arrays (FPGAs) or programmable logic devices (PLDs). The accelerator 542 can provide multiple neural networks, CPUs, processor cores, general-purpose graphics processing units, or the graphics processing units can be made available for use by artificial intelligence (AI) or machine learning (ML) models.

[0047] The memory subsystem 520 represents the main memory of the system 500 and provides storage for code to be executed by the processor 510 or data values to be used in execution routines. The memory subsystem 520 may include one or more memory devices 530, such as read-only memory (ROM), flash memory, one or more variants of random access memory (RAM) such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), and / or other memory devices, or combinations of such devices. The memory 530 stores and hosts, among other things, an operating system (OS) 532 that provides a software platform for executing instructions in the system 500, and stores and hosts applications 534 and processes 536. In one example, the memory subsystem 520 includes a memory controller 522 that is a memory controller for generating commands and issuing commands to the memory 530. The memory controller 522 may be a physical part of the processor 510 or a physical part of the interface 512. For example, the memory controller 522 may be an integrated memory controller on a circuit integrated into the processor 510.

[0048] The system 500 may also optionally include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, and / or an interface bus. Buses or other signal lines may communicatively or electrically couple components together, or both communicatively and electrically couple components. A bus may include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuitry or combinations. A bus may include, for example, one or more of the following: a system bus, a Peripheral Component Interconnect (PCI) or Peripheral Component Interconnect Express (PCIe) bus, a HyperTransport or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or a FireWire bus.

[0049] In one example, the system 500 includes an interface 514 that may be coupled to the interface 512. In one example, the interface 514 represents interface circuitry that may include discrete components and integrated circuits. In one example, a user interface component or a peripheral component or both are coupled to the interface 514. The network interface 550 provides the system 500 with the ability to communicate with remote devices (e.g., servers or other computing devices) on one or more networks. The network interface 550 may include an Ethernet adapter, a wireless interconnect component, a cellular network interconnect component, a USB, or other wired or wireless standard-based or proprietary interface. The network interface 550 may transfer data to devices in the same data center or rack or to remote devices, which may include sending data stored in the memory.

[0050] Some examples of network interface 550 are part of an infrastructure processing unit (IPU) or a data processing unit (DPU), or are used by an IPU or a DPU. xPU can at least refer to an IPU, a DPU, a GPU, a GPGPU (general-purpose computing on a graphics processing unit), or other processing units (e.g., accelerator devices). An IPU or a DPU can include a network interface having one or more programmable pipelines or fixed-function processors to perform offloading of operations that might have been performed by a CPU. An IPU or a DPU can include one or more memory devices.

[0051] In one example, system 500 includes one or more input / output (I / O) interfaces 560. The I / O interfaces 560 can include one or more interface components through which a user interacts with system 500 (e.g., audio, alphanumeric, tactile / touch, or other docking). The peripheral interface 570 can include additional types of hardware interfaces, such as, for example, interfaces to semiconductor manufacturing equipment and / or electrostatic charge management devices.

[0052] In one example, system 500 includes a storage subsystem 580. The storage subsystem 580 includes (one or more) memory devices 584, which can be or can include any conventional medium for storing data in a non-volatile manner, such as one or more magnetic, solid-state, and / or optical-based disks. While memory 530 is typically an execution or operating memory for providing instructions to processor 510, storage device 584 can generally be considered “memory”. Although storage device 584 is non-volatile, memory 530 can include volatile memory (e.g., if the power to system 500 is interrupted, the value or state of the data is indeterminate). In one example, the storage subsystem 580 includes a controller 582 to interface with the storage device 584. In one example, the controller 582 is a physical part of interface 512 or processor 510, or can include circuitry or logic in both processor 510 and interface 514.

[0053] A power source (not depicted) provides power to the components of system 500. More specifically, the power source typically interfaces with one or more power supplies in system 500 to provide power to the components of system 500.

[0054] Exemplary systems can be implemented in various types of computing, smart phones, tablets, personal computers, and networking equipment, such as switches, routers, racks, and blade servers, such as those employed in data center and / or server farm environments.

[0055] Example

[0056] A semiconductor package substrate may include: an interconnecting bridge, wherein the interconnecting bridge includes a metal trace and a metal through-bridge via, wherein the interconnecting bridge has a package-side landing pad, and wherein the package-side landing pad has a surface, and wherein the surface of the package-side landing pad has a size; and an interconnecting-bridge-side landing pad, wherein the interconnecting-bridge-side landing pad is electrically connected to the package-side landing pad, wherein the interconnecting-bridge-side landing pad has a surface, wherein the surface of the interconnecting-bridge-side landing pad has a size, and wherein the surface size of the interconnecting-bridge-side landing pad is 10% to 200% larger than the surface size of the package-side landing pad. The interconnecting-bridge-side landing pad may have a surface coating, and the surface coating includes Au. The interconnecting-bridge-side landing pad may have a surface coating, and the surface coating includes NiPdAu or NiAu. The surface size of the interconnecting-bridge-side landing pad may be 20% to 200% larger than the surface size of the package-side landing pad. The surface size of the interconnecting-bridge-side landing pad may be 50% to 200% larger than the surface size of the package-side landing pad. The surface of the package-side landing pad has a center, wherein the surface of the interconnecting-bridge-side landing pad has a center, and wherein the center of the surface of the package-side landing pad may deviate from the center of the surface of the interconnecting-bridge-side landing pad by an amount between 5 μm and 30 μm. The package substrate may be a coreless semiconductor package substrate. The semiconductor package substrate may further include a package substrate core made of glass or an organic material.

[0057] A semiconductor chip assembly can include: at least two semiconductor chips; a package substrate, wherein the package substrate includes: at least one interconnect bridge, wherein the interconnect bridge includes a metal trace and a metal through-bridge via, wherein the interconnect bridge has a package-side landing pad, wherein the package-side landing pad has a surface, wherein the package-side landing pad surface has a size; and an interconnect-bridge-side landing pad, wherein the interconnect-bridge-side landing pad is electrically connected to the package-side landing pad, wherein the interconnect-bridge-side landing pad has a surface, wherein the interconnect-bridge-side landing pad surface has a size, and wherein the interconnect-bridge-side landing pad surface size is 10% to 200% times larger than the package-side landing pad surface size, wherein a first semiconductor chip of the at least two semiconductor chips is communicatively coupled to a second semiconductor chip of the at least two semiconductor chips via the interconnect bridge. The interconnect-bridge-side landing pad can have a surface coating, and wherein the surface coating includes Au. The interconnect-bridge-side landing pad surface size can be 20% to 200% times larger than the package-side landing pad surface size. The package-side landing pad surface has a center, the interconnect-bridge-side landing pad surface has a center, and the package-side landing pad surface center can deviate from the interconnect-bridge-side landing pad surface center by an amount between 5 μm and 30 μm. The first semiconductor chip of the at least two semiconductor chips can be a processor, and the second semiconductor chip of the at least two semiconductor chips can be a high-bandwidth memory dynamic random access memory chip. The semiconductor chip assembly can further include a circuit board, wherein the package substrate is operatively coupled to the circuit board, wherein the circuit board includes a power supply, and wherein the power supply is capable of providing power to the at least two semiconductor chips via the interconnect bridge.

[0058] A method of manufacturing a semiconductor package substrate can include: creating a cavity in a partially manufactured semiconductor package substrate to expose an interconnect-bridge-side landing pad within the partially manufactured semiconductor package substrate; coating the exposed interconnect-bridge-side landing pad with a metal material; placing the interconnect bridge into the cavity, wherein an electrical interconnect is formed between the interconnect bridge and the interconnect-bridge-side landing pad within the partially manufactured semiconductor package substrate, and wherein the interconnect bridge is aligned with a datum in the partially manufactured semiconductor package substrate; and placing an underfill between the interconnect bridge and the partially manufactured semiconductor package substrate. The interconnect bridge can include a package-side landing pad, the interconnect-bridge-side landing pad can be electrically connected to the package-side landing pad, wherein the interconnect-bridge-side landing pad has a surface, wherein the interconnect-bridge-side landing pad surface has a size, wherein the package-side landing pad has a surface, wherein the package-side landing pad surface has a size, and wherein the interconnect-bridge-side landing pad surface size can be 10% to 200% times larger than the package-side landing pad surface size. The coating can include Au. The coating can partially cover the surface of the exposed interconnect-bridge-side landing pad. The coating can cover the exposed portion of the interconnect-bridge-side landing pad. The coating can completely cover the surface of the exposed interconnect-bridge-side landing pad.

[0059] Except as otherwise described herein, various modifications to the disclosure and implementation of the present invention may be made without departing from the scope of the present invention. Accordingly, the description and examples herein are to be construed in an illustrative rather than a restrictive sense. The scope of the present invention should be measured only by reference to the following claims.

Claims

1. A device comprising: Package substrate; an interconnect bridge, wherein the interconnect bridge comprises a metal trace and a metal through-bridge via, wherein the interconnect bridge has a package-side landing pad, wherein the package-side landing pad has a surface, wherein the package-side landing pad surface has a size, and wherein the interconnect bridge is within or on the package substrate; and An interconnect bridge side landing pad, wherein the interconnect bridge side landing pad is electrically connected to the package side landing pad, wherein the interconnect bridge side landing pad has a surface, wherein the interconnect bridge side landing pad surface has a size, and wherein the interconnect bridge side landing pad surface size is 10% to 200% larger than the package side landing pad surface size. 2 . The apparatus of claim 1 , wherein the interconnect bridge side landing pad has a surface coating, and wherein the surface coating comprises Au. 3 . The apparatus of claim 1 , wherein the interconnect bridge side landing pad has a surface coating, and wherein the surface coating comprises NiPdAu or NiAu. 4 . The apparatus of claim 1 , wherein a surface size of the interconnect bridge side landing pad is 20% to 200% larger than a surface size of the package side landing pad. The apparatus of claim 1 , wherein the packaging substrate is a coreless packaging substrate.

6. The device of claim 1, wherein the encapsulation substrate comprises a core composed of glass or an organic material.

7. The device of any one of claims 1 to 6, wherein the package side landing pad surface has a center, wherein the interconnect bridge side landing pad surface has a center, and wherein the package side landing pad surface center deviates from the interconnect bridge side landing pad surface center by an amount between 5 μm and 30 μm.

8. The device according to any one of claims 1 to 6, wherein the interconnection bridge side landing pad surface size is 50% to 200% larger than the package side landing pad surface size.

9. A semiconductor chip assembly comprising: at least two semiconductor chips; as well as A packaging substrate, wherein the packaging substrate comprises: at least one interconnect bridge, wherein the interconnect bridge comprises a metal trace and a metal through bridge via, wherein the interconnect bridge has a package-side landing pad, wherein the package-side landing pad has a surface, wherein the package-side landing pad surface has a size; and an interconnect bridge side landing pad, wherein the interconnect bridge side landing pad is electrically connected to the package side landing pad, wherein the interconnect bridge side landing pad has a surface, wherein the interconnect bridge side landing pad surface has a size, and wherein the interconnect bridge side landing pad surface size is 10% to 200% larger than the package side landing pad surface size, and Wherein a first semiconductor chip of the at least two semiconductor chips is communicatively coupled to a second semiconductor chip of the at least two semiconductor chips through the interconnection bridge. 10 . The semiconductor chip assembly according to claim 9 , wherein the interconnection bridge side landing pad has a surface coating, and wherein the surface coating comprises Au. 11 . The semiconductor chip assembly according to claim 9 , wherein the interconnection bridge side landing pad has a surface coating and wherein the surface coating comprises NiPdAu or NiAu.

12. The semiconductor chip assembly of claim 9, wherein a surface size of the interconnection bridge side landing pad is 20% to 200% larger than a surface size of the package side landing pad.

13. The semiconductor chip assembly according to claim 9, wherein a first semiconductor chip of the at least two semiconductor chips is a processor, and wherein a second semiconductor chip of the at least two semiconductor chips is a high bandwidth memory (dynamic random access memory) chip.

14. The semiconductor chip assembly of claim 9, further comprising a circuit board, wherein the package substrate is operably coupled to the circuit board, wherein the circuit board comprises a power supply, and wherein the power supply is capable of providing power to the at least two semiconductor chips through the interconnection bridge.

15. The semiconductor chip assembly of any one of claims 9 to 14, wherein the package-side landing pad surface has a center, wherein the interconnection bridge-side landing pad surface has a center, and wherein the package-side landing pad surface center deviates from the interconnection bridge-side landing pad surface center by an amount between 5 μm and 30 μm.

16. The semiconductor chip assembly according to any one of claims 9 to 14, wherein a surface size of the interconnection bridge side landing pad is 50% to 200% larger than a surface size of the package side landing pad.

17. A method for manufacturing a semiconductor package substrate, comprising: creating a cavity in a partially fabricated semiconductor package substrate to expose an interconnect bridge side landing pad within the partially fabricated semiconductor package substrate; coating the interconnect bridge side landing pad with a metal material; placing an interconnect bridge into the cavity, wherein electrical interconnects are formed between the interconnect bridge and the interconnect bridge-side landing pads within the partially fabricated semiconductor package substrate, and wherein the interconnect bridge is aligned with a fiducial in the partially fabricated semiconductor package substrate; and An underfill is placed between the interconnect bridge and the partially fabricated semiconductor package substrate.

18. A method for manufacturing a semiconductor package substrate according to claim 17, wherein the interconnection bridge includes a package side landing pad, wherein the interconnection bridge side landing pad is electrically connected to the package side landing pad, wherein the interconnection bridge side landing pad has a surface, wherein the interconnection bridge side landing pad surface has a size, wherein the package side landing pad has a surface, wherein the package side landing pad surface has a size, and wherein the interconnection bridge side landing pad surface size is 10% to 200% larger than the package side landing pad surface size.

19. The method for manufacturing a semiconductor package substrate according to claim 17, wherein the metal material comprises Au. 20 . The method for manufacturing a semiconductor package substrate according to claim 17 , wherein the metal material comprises NiPdAu or NiAu. 21 . The method of manufacturing a semiconductor package substrate according to claim 17 , wherein the metal material covers an exposed portion of the interconnection bridge-side landing pad. 22 . The method of manufacturing a semiconductor package substrate according to claim 17 , wherein the metal material covers an exposed portion of the interconnection bridge-side landing pad. 23 . The method for manufacturing a semiconductor package substrate according to claim 17 , wherein the metal material completely covers the exposed surface of the interconnection bridge-side landing pad.

24. A computer readable medium comprising instructions stored thereon which, when executed by a computer, cause the performance of the method according to any one of claims 17 to 23.

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