Anti-interference type bidirectional electrostatic protection circuit

Abstract

The application provides an anti-interference bidirectional electrostatic protection circuit, which comprises a first electrostatic discharge path and a second electrostatic discharge path arranged in parallel, the first electrostatic discharge path comprises a first electrostatic discharge unit and a second electrostatic discharge unit arranged in stack, the second electrostatic discharge path comprises a third electrostatic discharge unit and a fourth electrostatic discharge unit arranged in stack, the first electrostatic discharge unit and the second electrostatic discharge unit are arranged in opposite directions, the capacitance value of the first electrostatic discharge unit is greater than that of the second electrostatic discharge unit, the third electrostatic discharge unit and the fourth electrostatic discharge unit are arranged in opposite directions, the capacitance value of the third electrostatic discharge unit is greater than that of the fourth electrostatic discharge unit, and the first electrostatic discharge unit and the third electrostatic discharge unit are arranged in opposite directions. Through the optimization of the circuit structure and the layout, the accumulated charges on the internal floating nodes can be discharged.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection circuits, and more specifically to an anti-interference bidirectional ESD protection circuit. Background Technology

[0002] During the use of electronic devices, static electricity can easily be generated on the human body, clothing, and device surfaces due to friction, contact separation, and other reasons. When static electricity accumulates to a certain level, it will cause electrostatic discharge, releasing high-energy charges. This electrostatic discharge can seriously damage sensitive components such as integrated circuits inside electronic devices, leading to decreased device performance or even complete failure.

[0003] In some electronic devices, signal swings at certain ports may exhibit both positive and negative voltages simultaneously. For these ports, bidirectional ESD protection circuitry is required: bidirectional voltage blocking capability during normal chip operation, and bidirectional electrostatic discharge capability in the event of an ESD event. In practical ESD protection engineering, bidirectional ESD protection is achieved by connecting two unidirectional ESD devices in series, either head-to-head or tail-to-tail. In this case, to provide effective ESD protection, the clamping voltage after the ESD circuit is turned on needs to be monitored; typically, it must not exceed the failure voltage of the protected circuit under a specific ESD excitation level.

[0004] Existing bidirectional stacked ESD circuits, such as Figure 1(a)-Figure 1(c) As shown, for bidirectional I / O or power ports, a common ESD protection circuit strategy is to connect Zener diodes, BJTs (bipolar junction transistors), or MOSFETs in series "head-to-head" or "tail-to-tail". In this case, the internal node Ax is floating, where x = 1, 2, 3. Resistors R1 and R2 are used to limit the base current, ensuring the transistor conducts under appropriate conditions; resistors R3 and R4 are used to limit the gate current, ensuring the MOSFET conducts under appropriate conditions.

[0005] However, for chip ports employing the aforementioned bidirectional ESD protection circuit, the actual ESD protection level of the port sometimes falls far short of its design value. Research indicates that this is typically due to the charge storage behavior of the internal floating nodes within the bidirectional ESD circuit. When an ESD event occurs, the non-zero potential caused by these stored charges has a certain probability of being superimposed on the IV characteristic curve of the ESD protection device, thus drastically deteriorating its clamping voltage characteristics and ultimately significantly reducing the port's ESD protection level.

[0006] Figure 2(a) shows the influence of the ESD circuit's IV characteristics on the floating potential of Ax. The applied bias voltage represents the port voltage or the pre-charge phenomenon during ESD testing. As shown in Figure 2(a), under certain circumstances, when the applied bias voltage disappears, the Ax potential cannot be discharged to zero. As shown in Figure 2(c), when the Ax potential is not zero, the IV curve of the ESD circuit (two red lines) will drift to the right along the X-axis, thus significantly deteriorating the electrostatic protection effect of the ESD circuit. In other words, the ESD robustness will be severely affected by the Ax potential. Summary of the Invention

[0007] To address the problems in the prior art, this invention provides an anti-interference bidirectional electrostatic protection circuit. Through circuit structure and layout optimization, it can effectively and promptly discharge the accumulated charge on the floating nodes inside the circuit, avoiding interference from the non-zero potential on the internal floating nodes on the ESD protection effect.

[0008] This invention discloses an anti-interference bidirectional electrostatic discharge (ESD) protection circuit, comprising a first ESD discharge path and a second ESD discharge path arranged in parallel. One end of each ESD discharge path is connected to a first port, and the other end is connected to a second port. The first ESD discharge path includes a first ESD discharge unit and a second ESD discharge unit stacked together. The second ESD discharge path includes a third ESD discharge unit and a fourth ESD discharge unit stacked together. The first and second ESD discharge units are arranged in opposite directions. The capacitance of the first ESD discharge unit is greater than that of the second ESD discharge unit. The third and fourth ESD discharge units are arranged in opposite directions, with the capacitance of the third ESD discharge unit being greater than that of the fourth ESD discharge unit. Furthermore, the first and third ESD discharge units are arranged in opposite directions.

[0009] Furthermore, the first and third electrostatic discharge units are provided with m parallel ESD elements, and the second and fourth electrostatic discharge units are provided with n parallel ESD elements, where m and n are both positive integers, and m>n.

[0010] In another improvement of the present invention, the first electrostatic discharge unit and the third electrostatic discharge unit are provided with m parallel ESD elements, and the second electrostatic discharge unit and the fourth electrostatic discharge unit are provided with n parallel ESD elements, wherein m and n are both positive integers, and m = n. The first electrostatic discharge unit is connected in parallel with k capacitors, and the third electrostatic discharge unit is connected in parallel with k capacitors, where k is a positive integer.

[0011] Furthermore, the ESD element includes a diode, a MOSFET, a bipolar junction transistor (BJT), or a thyristor.

[0012] Furthermore, the first electrostatic discharge path and the second electrostatic discharge path have the same number of stacking levels, both being 2 or more. The number of the first electrostatic discharge unit and the second electrostatic discharge unit are both more than one, and the number of the second electrostatic discharge unit and the third electrostatic discharge unit are both more than one.

[0013] Furthermore, the second electrostatic discharge path is replaced by a second electrostatic discharge unit and a first resistor connected in parallel across the first electrostatic discharge unit.

[0014] Furthermore, a second resistor is connected in parallel across the two ends of the second electrostatic discharge unit. The resistance values ​​of the first resistor and the second resistor are determined by a trade-off between the discharge duration of the floating charge and the static power consumption.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: By optimizing the circuit structure and layout, the present invention changes the electrostatic discharge path from the same layout to a design with different capacitor ratios. This can effectively and promptly discharge the accumulated charge on the floating nodes inside the series-type ESD protection circuit through the small capacitor end, avoiding the interference of the non-zero potential on the internal floating nodes on the ESD protection effect, thereby realizing the intrinsic ESD protection capability of the protection circuit. By setting the two electrostatic discharge paths with different capacitor ratios and opposite directions, for bidirectional port bias, there is always one path that can effectively perform electrostatic protection, realizing the anti-interference of ESD function. Attached Figure Description

[0016] To more clearly illustrate the solutions in this invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1(a) is a circuit schematic diagram of an embodiment of an existing bidirectional stacked ESD circuit;

[0018] Figure 1(b) is a circuit schematic diagram of an existing bidirectional stacked ESD circuit embodiment two;

[0019] Figure 1(c) is a circuit schematic diagram of an existing bidirectional stacked ESD circuit embodiment three;

[0020] Figures 2(a) and 2(b) are schematic diagrams showing the influence of the Ax floating potential on the IV characteristics of the existing bidirectional stacked ESD circuit.

[0021] Figure 2(c) is a schematic diagram of the rightward drift of the IV curve of the existing bidirectional stacked ESD circuit;

[0022] Figure 3(a) is an equivalent circuit diagram of the first embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention;

[0023] Figure 3(b) is a circuit network diagram of the first embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention;

[0024] Figure 3(c) is a schematic diagram of the first embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention;

[0025] Figure 4(a) is an equivalent circuit diagram of the second embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention;

[0026] Figure 4(b) is a circuit network diagram of the second embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention;

[0027] Figure 4(c) is a schematic diagram of the second embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention;

[0028] Figure 5 This is an equivalent circuit diagram of the third embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention;

[0029] Figure 6 This is an equivalent circuit diagram of the fourth embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention;

[0030] Figure 7 This is an equivalent circuit diagram of the fifth embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention;

[0031] Figure 8 This is an equivalent circuit diagram of the sixth embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention. Detailed Implementation

[0032] Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains; the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings are used to distinguish different objects, not to describe a particular order.

[0033] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment to other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this invention can be combined with other embodiments.

[0034] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0035] like Figures 3(a)-6 As shown, the anti-interference bidirectional electrostatic discharge (ESD) protection circuit of the present invention includes a first ESD discharge path and a second ESD discharge path arranged in parallel. One end of each of the first and second ESD discharge paths is connected to a first port, and the other end is connected to a second port. The first ESD discharge path includes a first ESD discharge unit and a second ESD discharge unit stacked together. The second ESD discharge path includes a third ESD discharge unit and a fourth ESD discharge unit stacked together. The first and second ESD discharge units are arranged in opposite directions. The capacitance of the first ESD discharge unit is greater than that of the second ESD discharge unit. The third and fourth ESD discharge units are arranged in opposite directions, and the capacitance of the third ESD discharge unit is greater than that of the fourth ESD discharge unit. Furthermore, the first and third ESD discharge units are arranged in opposite directions.

[0036] The first and third electrostatic discharge units are equipped with m parallel ESD elements, and the second and fourth electrostatic discharge units are equipped with n parallel ESD elements, where m and n are both positive integers. The ESD elements in this example include diodes, MOSFETs, bipolar junction transistors (BJTs), or thyristors, etc. The connection method can be found in [reference needed]. Figure 1(a)-Figure 1(c) In addition to the above connection method, the gate of the MOSFET, the base of the bipolar junction transistor (BJT), and the control terminal of the thyristor can also be set to float.

[0037] The following description is based on a specific embodiment. In this example, a diode is used as the ESD component. The various reference numerals in the embodiments are explained as follows:

[0038] ● 100, 200, 300, 400, 500, and 600 represent port 1;

[0039] ●101, 201, 301, 401, 501, and 601 represent port 2;

[0040] ● 110, 210, 310, and 410 typically represent "reverse ESD discharge path," indicating that current is discharged from port 2 to port 1.

[0041] ● 111, 211, 311, and 411 typically represent "forward ESD discharge path," indicating that current is discharged from port 2 to port 1.

[0042] ●510 and 610 usually represent "bidirectional ESD discharge path", meaning that current can be discharged from port 2 to port 1, or from port 1 to port 2.

[0043] ●120, 121, 130, 131, 220, 221, 230, 231, 120-1, 120-2, 120-N 11 121-1, 121-2

[0044] 121-N 21 130-1, 130-2, 130-N 12 131-1, 131-2, 131-N 22 220-1, 220-2, 220-N 31 ,

[0045] 221-1, 221-2, 221-N 41 230-1, 230-2, 230-N 32 231-1, 231-2, 231-N 42 320

[0046] 321, 330, 331, 420, 421, 430, 431, 520, 521, 620, and 621 represent diodes;

[0047] ●122, 123, 132, 133, 222, 223, 232, 233 represent diode layouts;

[0048] ●340, 341, 441, and 441 represent capacitors;

[0049] ●550, 650, and 651 represent resistors;

[0050] ●A1, A2, A3, B1, B2, C1, C2, D1, D2, E1, E2, F1, G1 represent the internal floating nodes of the bidirectional electrostatic protection circuit;

[0051] ●N 11 N 12 N 21 N 22 N 31 N32 N 41 N 42 This represents the number of ESD diodes connected in parallel.

[0052] like Figures 3(a)-3(c) As shown, in the first embodiment of the present invention, this embodiment consists of two bidirectional ESD paths: In the reverse ESD discharge path 110, the area of ​​diode 120 is smaller than the area of ​​diode 121, that is, the parasitic capacitance of diode 120 is smaller than the parasitic capacitance of diode 121. When port 100 is negatively biased, this path can discharge the potential of the internal floating node B1 to zero, thus not affecting the ESD protection effect; In the forward ESD discharge path 111, the area of ​​diode 130 is larger than the area of ​​diode 131, that is, the parasitic capacitance of diode 130 is larger than the parasitic capacitance of diode 131; When port 100 is forward biased, this path can discharge the potential of B2 to zero, thus not affecting the ESD protection effect.

[0053] In summary, this embodiment ensures that there is always one effective path for electrostatic discharge (ESD) protection for bidirectional port bias, achieving ESD interference immunity. It is particularly important to note that the internal floating nodes B1 and B2 must not be short-circuited. This embodiment uses a Zener diode as an example, but it is also applicable to other ESD diodes or other ESD devices.

[0054] As shown in Figures 3(b) and 3(c), the forward-biased diode (N 11 +N 12 The total number of parallel diodes and the reverse bias diodes (N) 21 +N 22 The total number of parallel connections is equal, i.e., N 11 +N 12 =N 21 +N 22 Therefore, the total layout area of ​​the forward and reverse bias tubes is equal, which is consistent with the design principles of this type of bidirectional ESD architecture. However, the area ratio of the forward and reverse bias tubes is not the same on different ESD discharge paths, i.e., N 11 <N 12 N 21 >N 22 This allows for the control of parasitic capacitance ratios, ultimately achieving bidirectional floating charge discharge and effective ESD protection.

[0055] like Figures 4(a)-4(c)As shown, as a second embodiment of the present invention, this example, based on the first embodiment, changes the series connection method of diodes 230 and 231: from "head-to-head" to "tail-to-tail". In this case, the reverse ESD discharge path 210 is a "head-to-head" series connection, while the forward ESD discharge path 211 is a "tail-to-tail" series connection. The advantage of this second embodiment is that it is suitable for situations where the overall upper layout space is relatively small, such as... Figure 4(b) and 4(c) As shown, the upper half of the layout is smaller than the lower half. This embodiment increases the freedom of layout design.

[0056] like Figure 5 As shown, as a third embodiment of the present invention, this example further considers the ESD protection efficiency of the forward and reverse components. Here, all diodes are made to be of completely equal size, that is, the parasitic capacitance is the same. In order to make their capacitance ratios different, this example uses external capacitors 340 and 341 to adjust the capacitance ratios on the bidirectional path respectively.

[0057] like Figure 6 As shown, as the fourth embodiment of the present invention, compared with the third embodiment, the present invention adjusts the direction of diodes 430 and 431 on the second electrostatic discharge path, and then sets the external capacitors 440 and 441 in the lower half of the layout, thereby increasing the design freedom of the layout.

[0058] like Figure 7 As shown, in the fifth embodiment of the present invention, the second electrostatic discharge path is replaced by a second electrostatic discharge unit and a first resistor connected in parallel across the first electrostatic discharge unit. Structurally, this example has only one ESD discharge path, and the capacitance of diode 520 is smaller than that of diode 521. This example is particularly suitable for "full-chip ESD networks based on power rails." Here, diode 520 specifically refers to the "ESD diode" of the I / O port, and diode 521 specifically refers to the power clamp element. In this embodiment, by connecting a resistor in parallel with diode 521, the charge of the internal floating node F1 is effectively discharged, thereby achieving effective ESD protection. Of course, the value of resistor 550 in this example requires careful compromise: it must be able to discharge the charge of the floating node within a limited time while also considering the deterioration of the static leakage current.

[0059] like Figure 8As shown in the sixth embodiment of the present invention, based on the fifth embodiment, this invention can effectively discharge floating charge by adding a resistor network to a single ESD discharge path. In this example, the resistor network includes resistor 651 connected in parallel across diode 621 and resistor 650 connected in parallel across diode 620. The resistance values ​​of resistors 650 and 651 in this example also need to be balanced between "floating charge discharge time" and "static power consumption". The parasitic capacitances of diodes 620 and 621 can be different or the same, and then the effective discharge of floating charge is achieved by adjusting the resistor network.

[0060] It is worth mentioning that the number of stacking levels in all embodiments of the present invention is not limited to the number of stacking levels in existing embodiments, and can be set to any number of stacking levels.

[0061] As can be seen from the above, the present invention provides a robust bidirectional electrostatic discharge (ESD) protection solution. Through circuit structure and layout optimization, the accumulated charge on the floating nodes inside the series-type ESD protection circuit can be effectively and timely discharged, avoiding the interference of the non-zero potential on the internal floating nodes on the ESD protection effect, thereby realizing the intrinsic ESD protection capability of the protection circuit.

[0062] The specific embodiments described above are preferred embodiments of the present invention and are not intended to limit the specific scope of the present invention. The scope of the present invention includes, but is not limited to, these specific embodiments. All equivalent changes made in accordance with the present invention are within the protection scope of the present invention.

Claims

1. An anti-interference bidirectional electrostatic protection circuit, characterized in that: The system includes a first electrostatic discharge path and a second electrostatic discharge path connected in parallel. One end of each path is connected to a first port, and the other end is connected to a second port. The first path includes a first electrostatic discharge unit and a second electrostatic discharge unit stacked together. The second path includes a third electrostatic discharge unit and a fourth electrostatic discharge unit stacked together. The first and second units are arranged in opposite directions. The capacitance of the first unit is greater than that of the second unit. The third and fourth units are arranged in opposite directions, with the capacitance of the third unit being greater than that of the fourth unit. Furthermore, the first and third electrostatic discharge units are arranged in opposite directions. The layout area of ​​the first electrostatic discharge unit is larger than that of the second electrostatic discharge unit, and the layout area of ​​the third electrostatic discharge unit is larger than that of the fourth electrostatic discharge unit. There are floating nodes between the first and second electrostatic discharge units and between the third and fourth electrostatic discharge units. The first or second electrostatic discharge path can discharge the accumulated charge on the floating nodes inside the circuit, realizing bidirectional floating charge discharge.

2. The anti-interference bidirectional electrostatic protection circuit according to claim 1, characterized in that: The first and third electrostatic discharge units are provided with m parallel ESD elements, and the second and fourth electrostatic discharge units are provided with n parallel ESD elements, where m and n are both positive integers, and m>n.

3. The anti-interference bidirectional electrostatic protection circuit according to claim 1, characterized in that: The first and third electrostatic discharge units are provided with m parallel ESD elements, and the second and fourth electrostatic discharge units are provided with n parallel ESD elements, where m and n are both positive integers and m=n. The first electrostatic discharge unit is connected in parallel with k capacitors, and the third electrostatic discharge unit is connected in parallel with k capacitors, where k is a positive integer.

4. The anti-interference bidirectional electrostatic protection circuit according to claim 2 or 3, characterized in that: The ESD components include diodes, MOSFETs, bipolar junction transistors (BJTs), or thyristors.

5. The anti-interference bidirectional electrostatic protection circuit according to any one of claims 1-3, characterized in that: The first electrostatic discharge path and the second electrostatic discharge path have the same number of stacking levels, both being 2 or more. The number of the first electrostatic discharge unit and the second electrostatic discharge unit are both more than one, and the number of the second electrostatic discharge unit and the third electrostatic discharge unit are both more than one.

6. The anti-interference bidirectional electrostatic protection circuit according to any one of claims 1-3, characterized in that: The second electrostatic discharge path is replaced by a second electrostatic discharge unit and a first resistor connected in parallel across the first electrostatic discharge unit.

7. The anti-interference bidirectional electrostatic protection circuit according to claim 6, characterized in that: A second resistor is connected in parallel across the two ends of the second electrostatic discharge unit. The resistance values ​​of the first resistor and the second resistor are determined by a trade-off between the discharge duration of the floating charge and the static power consumption.

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