Data acquisition and processing method of multi-core single-chip power distribution intelligent terminal

Abstract

The invention discloses a data acquisition and processing method of a multi-core single-chip power distribution intelligent terminal, which relates to the technical field of data acquisition and processing, and obviously optimizes the real-time response and data processing capability of the multi-core power distribution terminal through dynamic priority scheduling and intelligent memory management. The dynamic priority model fuses task types, nuclear loads and aging attenuation factors, intelligent queue jumping processing of emergency interruption is achieved, and time sequence conflicts between periodic sampling and sudden interruption are effectively relieved; the shared memory fragmentation design isolates real-time data streams from historical caches, and an independent access channel and a conflict arbitration mechanism are combined, so that the inter-core communication blocking risk is reduced; the self-adaptive sampling frequency tracks the fluctuation of a power grid, combines with an improved compression algorithm, and considers the high-frequency signal acquisition efficiency and storage resource optimization.

Description

Technical Field

[0001] The present invention relates to the technical field of data acquisition and processing, and particularly to a data acquisition and processing method for a multi-core single-chip power distribution intelligent terminal. Background Art

[0002] In a power distribution system, a multi-core single-chip terminal undertakes the core tasks of data acquisition, fault diagnosis, and real-time control. Its typical application scenarios, such as simultaneously processing periodic sampling data and aperiodic emergency events, specifically collecting voltage and current waveforms and handling faults such as circuit breaker tripping and grounding; traditional architectures mostly adopt a division of labor mode between a data processing core and a microprocessor core: the former is responsible for high-frequency analog quantity acquisition, and the latter executes protocol parsing and logic control.

[0003] Existing systems mostly adopt static priority scheduling or polling mechanisms to handle timing conflicts; for periodic sampling tasks, most trigger ADC conversion with a fixed time window and store the data in a shared memory; aperiodic interrupts rely on hardware trigger signals to preempt processing resources; this mode can be maintained in low-load scenarios, but it has poor effects in complex working conditions such as feeder automation and frequent instantaneous faults: the interrupt response delay grows non-linearly with the increase in system load, and key fault signals will miss the best disposal opportunity due to queuing. In addition, the continuity of periodic sampling tasks is easily disrupted by high-frequency interrupts, resulting in waveform data loss or phase distortion.

[0004] To alleviate the above problems, some solutions introduce a hybrid priority mechanism at the task scheduling layer to hierarchically manage aperiodic interrupts; adopt a double-buffer technology at the data storage layer to isolate the data streams of periodic sampling and interrupt processing; optimize the mutex granularity at the inter-core communication layer to reduce resource sharing conflicts; and these methods are essentially still local optimizations under static rules. Facing the dynamically changing load characteristics and event distributions, traditional solutions lack the ability to quantitatively evaluate the urgency of tasks and cannot achieve elastic allocation of processing resources. Summary of the Invention

[0005] In view of the above existing problems, the present invention is proposed.

[0006] The present invention provides a data acquisition and processing method for a multi-core single-chip power distribution intelligent terminal to solve the problems that traditional multi-core terminals using static priority scheduling and fixed timing windows have inherent problems such as interrupt response delay, data aliasing, and memory access conflicts, and it is difficult to meet the real-time requirements under dynamic loads.

[0007] To solve the above technical problems, the present invention provides the following technical solutions: An embodiment of the present invention provides a data acquisition and processing method for a multi-core single-chip power distribution intelligent terminal, which includes, Step S1, configure a periodic sampling task in the data processing core, set a sampling time window synchronized with the fundamental frequency of the power grid, and trigger analog-to-digital conversion through a hardware timer; Step S2, deploy an aperiodic interrupt monitoring module in the microprocessor core to capture the circuit breaker tripping signal, ground fault signal, and communication protocol interrupt request in real time; Step S3, based on the dynamic priority calculation model, quantify the priorities of the periodic sampling task and the aperiodic interrupt task. The model dynamically adjusts the weights according to the task type, the current core load rate, and the data timeliness decay factor; Step S4, through the shared memory sharding management unit, divide the storage area into a real-time data area, a historical cache area, and an interrupt event queue, and each area uses an independent memory access channel; Step S5, after the data processing core completes the preprocessing of the sampled data, write the data packet into the corresponding memory area according to the priority weight, and at the same time trigger the inter-core communication flag bit; Step S6, after the microprocessor core responds to the communication flag bit, process the memory data in the order of the timeliness weight from high to low, and output the processing result to the communication interface; The triggering conditions of the inter-core communication flag bit in Step S6 include: The write volume of the real-time data area reaches 80% of its capacity; There is a task in the interrupt event queue whose waiting time exceeds the set threshold; The current load rate of the microprocessor core is lower than 30%.

[0008] As a preferred solution of the data acquisition and processing method of the distribution intelligent terminal with a multi-core single chip according to the present invention, wherein: the configuration of the periodic sampling task in Step S1 includes: The sampling frequency is set to 2N times an integer multiple of the fundamental frequency, where N is a natural number greater than or equal to 10; The length of the sampling time window is adaptively adjusted according to the power grid frequency fluctuation range, and the adjustment step is 1 ms.

[0009] As a preferred solution of the data acquisition and processing method of the distribution intelligent terminal with a multi-core single chip according to the present invention, wherein: in Step S1, configure a periodic sampling task in the data processing core, set a sampling time window synchronized with the fundamental frequency of the power grid, and trigger analog-to-digital conversion through a hardware timer; In Step S1, the sampling frequency is defined as , where, represents the sampling frequency, represents the sampling exponent, and the value range is a natural number greater than or equal to 10, represents the fundamental frequency of the power grid, represents the integer multiple sampling coefficient; For the highest signal bandwidth satisfy wherein indicates the highest signal bandwidth; When the fundamental frequency deviates introduce a dynamic sampling interval : , wherein represents the dynamic sampling interval, represents the fundamental frequency deviation; Define the reference sampling interval and its correction amount as: , , wherein represents the reference sampling interval, represents the sampling interval correction amount.

[0010] As a preferred solution of the data acquisition and processing method of the power distribution intelligent terminal of a multi-core single-chip described in the present invention, wherein: the construction method of the dynamic priority calculation model in step S3 includes: Assign a basic weight coefficient K1 to the periodic sampling task, and its value is positively correlated with the number of sampling channels; Assign an emergency weight coefficient K2 to the aperiodic interrupt task, and its value matches the grid security level associated with the interrupt type; Introduce an aging attenuation factor, and its value decays exponentially with the task waiting time.

[0011] As a preferred solution of the data acquisition and processing method of the power distribution intelligent terminal of a multi-core single-chip described in the present invention, wherein: in step S3, the step of dynamically adjusting the weight according to the task type, the current core load rate, and the data timeliness attenuation factor is: Calculate the dynamic priority for task In each scheduling cycle, the priority is updated according to the following formula: , wherein represents the dynamic priority of task , represents the basic weight coefficient of task , represents the current core load adjustment function, represents the aging attenuation factor of task ; Subsequently, each sub-item is defined respectively, including: The core load adjustment function is defined as: , wherein Indicates the current core load rate, and the value range is , Indicates the load impact factor, which is used to control the decay rate of the load weight.

[0012] As a preferred solution of the data acquisition and processing method of the power distribution intelligent terminal of a multi-core single-chip as described in the present invention, wherein: in step S3, each sub-item further includes: The aging decay factor, which comprehensively considers the task waiting time The decay effect on the priority is defined as: , where Indicates the aging decay factor of task , Indicates the decay rate of task , Indicates the cumulative waiting time of task ; The task urgency Is discretized into four levels, 1-4, and is mapped to the minimum and maximum decay rates in the linear interval: , where Indicates the decay rate of task , Indicates the lowest decay rate corresponding to the lowest urgency, Indicates the highest decay rate corresponding to the highest urgency, Indicates the urgency level of task , with a value range of 1-4; The update and calculation of the above functions and factors are executed once in each scheduling cycle, and its update cycle is set to , where Indicates the cycle of dynamic priority calculation and decay update.

[0013] As a preferred solution of the data acquisition and processing method of the power distribution intelligent terminal of a multi-core single-chip as described in the present invention, wherein: the operations of the shared memory sharding management unit in step S4 include: The real-time data area stores the original sampling data within the most recent 2 cycles, and adopts a cyclic overwrite writing strategy; The historical buffer stores the compressed feature data, and adopts a paged storage structure, and each page of data is attached with a timestamp mark; The interrupt event queue adopts a double-buffer structure, allowing high-priority tasks to directly write to the activation buffer.

[0014] As a preferred solution of the data acquisition and processing method of the power distribution intelligent terminal of a multi-core single-chip of the present invention, wherein: the shared memory sharding management unit further includes: A memory access conflict arbitration mechanism that comprehensively sorts simultaneous read and write requests according to task priority and timeliness; A data integrity verification module that appends a 2-byte CRC verification code after each memory write operation; An access timestamp recording function that attaches a write time mark accurate to the microsecond level to each memory block.

[0015] As a preferred solution of the data acquisition and processing method of the power distribution intelligent terminal of a multi-core single-chip of the present invention, wherein: the data preprocessing in step S5 includes: Performing sliding window feature extraction on the sampled data, and the window length is equal to the power grid fundamental wave period; Using an improved run-length encoding to perform lossless compression on the feature data, and the compression block size is fixed at 64 bytes.

[0016] As a preferred solution of the data acquisition and processing method of the power distribution intelligent terminal of a multi-core single-chip of the present invention, wherein: in step S5, the step of performing lossless compression on the feature data using the improved run-length encoding is: Adopting a two-stage lossless compression process of differential encoding and run-length encoding; For the feature sequence of length Perform first-order difference: wherein, represents the th difference value, represents the th feature value, is the initial reference value, taking or 0; Perform run-length encoding on the difference sequence to obtain an encoded pair sequence: , wherein, represents the difference value of the th run, represents the length of this run, and the length is the number of consecutive identical , represents the total number of run pairs; Pack the run pairs into each block of a fixed size bytes: ; The number of bits occupied by each pair of encodings is: , wherein, Add 1 to the maximum value of all and add 1 to the maximum allowable run length, is the bit width of the difference value field, is the bit width of the run length field; Then the maximum number of encoded pairs per block is: , When , store them in multiple blocks sequentially. When there is not enough, fill them with zero-value pairs until the block is full.

[0017] The beneficial effects of the present invention are as follows: Through dynamic priority scheduling and intelligent memory management, the present invention significantly optimizes the real-time response and data processing capabilities of multi-core power distribution terminals; the dynamic priority model integrates task types, core loads, and time decay factors to achieve intelligent queuing for emergency interrupts, effectively alleviating the timing conflicts between periodic sampling and sudden interrupts; the shared memory sharding design isolates real-time data streams and historical caches, combined with independent access channels and conflict arbitration mechanisms, reducing the risk of inter-core communication blocking; the adaptive sampling frequency tracks power grid fluctuations, combined with an improved compression algorithm, taking into account both the acquisition efficiency of high-frequency signals and the optimization of storage resources.

[0018] On the premise of maintaining hardware compatibility, the present invention systematically solves the problems of response delay, data loss, and memory contention caused by rigid scheduling in traditional methods, providing high-reliability algorithm-level support for power distribution automation under complex working conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0020] Figure 1 It is a schematic flowchart of the data acquisition and processing method of the multi-core single-chip power distribution intelligent terminal in Embodiment 1. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] In order to make the above objects, features, and advantages of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the drawings of the specification.

[0022] In the following description, many specific details are set forth in order to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below. ​

[0023] Second, the "one embodiment" or "embodiment" mentioned herein refers to specific features, structures, or characteristics that may be included in at least one implementation manner of the present invention. The "in one embodiment" that appears in different places in this specification does not all refer to the same embodiment, nor is it an individual or alternative embodiment that is mutually exclusive with other embodiments.

[0024] Embodiment 1, referring to Figure 1 , this embodiment provides a data acquisition and processing method for a power distribution intelligent terminal of a multi-core single-chip, including: Step S1, configure a periodic sampling task in the data processing core, set a sampling time window synchronized with the power grid fundamental frequency, and trigger analog-to-digital conversion through a hardware timer; The configuration of the periodic sampling task in Step S1 includes: The sampling frequency is set to 2N times an integer multiple of the fundamental frequency, where N is a natural number greater than or equal to 10; The length of the sampling time window is adaptively adjusted according to the power grid frequency fluctuation range, and the adjustment step is 1 ms; In Step S1, configure a periodic sampling task in the data processing core, set a sampling time window synchronized with the power grid fundamental frequency, and trigger analog-to-digital conversion through a hardware timer; In Step S1, the sampling frequency is defined as , where represents the sampling frequency, represents the sampling exponent, and the value range is a natural number greater than or equal to 10, represents the power grid fundamental frequency, represents the integer multiple sampling coefficient; For the signal highest bandwidth , it satisfies , where represents the signal highest bandwidth; When the fundamental frequency has a deviation , introduce a dynamic sampling interval : , where represents the dynamic sampling interval, represents the fundamental frequency deviation; Define the reference sampling interval and its correction amount as: , , where represents the reference sampling interval, represents the sampling interval correction amount; Specifically, by setting the sampling frequency to Combined with the highest signal bandwidth Under the premise of satisfying the Nyquist sampling theorem, the sampling exponent N can be flexibly selected, so as to balance the time-domain resolution and system resource consumption, and the dynamic sampling interval The design of allows for precise compensation according to the real-time frequency offset, keeps the sampling window synchronized with the power grid fundamental wave, reduces the influence of aliasing and time-base drift, and the reference interval and the correction amount are introduced to achieve a fast response to frequency mutations, improve the robustness of data processing against grid changes and the sampling accuracy; Step S2, deploy an aperiodic interrupt monitoring module in the microprocessor core to capture the circuit breaker tripping signal, ground fault signal and communication protocol interrupt request in real time; Step S3, based on the dynamic priority calculation model, quantify the priorities of periodic sampling tasks and aperiodic interrupt tasks. The model dynamically adjusts the weights according to the task type, the current core load rate and the data timeliness decay factor; The construction method of the dynamic priority calculation model in step S3 includes: Assign a basic weight coefficient K1 to the periodic sampling task, and its value is positively correlated with the number of sampling channels; Assign an emergency weight coefficient K2 to the aperiodic interrupt task, and its value matches the grid security level associated with the interrupt type; Introduce a timeliness decay factor, and its value decays exponentially with the task waiting time; In step S3, the steps of dynamically adjusting the weights according to the task type, the current core load rate and the data timeliness decay factor are: Calculate the dynamic priority for the task In each scheduling period, the priority is updated according to the following formula: , where represents the dynamic priority of the task , represents the basic weight coefficient of the task , represents the current core load adjustment function, represents the task 's timeliness decay factor; Subsequently, each sub-item is defined respectively, including: The core load adjustment function is defined as: , where represents the current core load rate, and the value range , represents the load influence coefficient, which is used to control the load weight decay rate; In step S3, each sub-item further includes: The aging attenuation factor, which comprehensively considers the task waiting time The attenuation effect on the priority, which is defined as: , where represents the aging attenuation factor of task , represents the attenuation rate of task , represents the cumulative waiting time of task ; Discretize the task urgency into four levels, 1 - 4, and map it to the minimum and maximum attenuation rates in the linear interval: , where represents the attenuation rate of task , represents the lowest attenuation rate corresponding to the lowest urgency, represents the highest attenuation rate corresponding to the highest urgency, represents the urgency level of task , with values ranging from 1 to 4; The update and calculation of the above functions and factors are executed once in each scheduling period, and its update period is set to , where represents the period of dynamic priority calculation and attenuation update; Specifically, through the above model, the basic weight of the task, the current core load, and the aging attenuation are closely combined to achieve dynamic priority adjustment for different types of tasks. The core load adjustment function can automatically reduce the weight of newly arrived tasks according to the busy degree of the processing unit to avoid overload. The aging attenuation factor reflects the task waiting time in an exponential form. The higher the urgency of the task, the greater its attenuation rate , and it can restore the priority faster, so as to quickly respond to interrupts related to security. Low-urgency tasks are naturally postponed. The method of linearly mapping the urgency and the attenuation rate takes into account both simple implementation and controllability of parameter adjustment; Step S4: Through the shared memory sharding management unit, divide the storage area into a real-time data area, a historical cache area, and an interrupt event queue, and each area uses an independent memory access channel; The operations of the shared memory sharding management unit in step S4 include: The real-time data area stores the original sampling data within the most recent 2 cycles, and adopts a circular overwrite writing strategy; The historical cache area stores the compressed feature data, and adopts a paged storage structure, with each page of data attached with a timestamp mark; The interrupt event queue adopts a double-buffer structure, allowing high-priority tasks to directly write to the active buffer; The shared memory sharding management unit also includes: A memory access conflict arbitration mechanism that comprehensively sorts simultaneous read and write requests according to task priority and timeliness; A data integrity verification module that appends a 2-byte CRC verification code after each memory write operation; An access timestamp recording function that attaches a write time mark accurate to the microsecond level to each memory block; Step S5: After the data processing core completes the preprocessing of the sampled data, write the data packet to the corresponding memory area according to the priority weight, and at the same time trigger the inter-core communication flag bit; The data preprocessing in step S5 includes: Performing sliding window feature extraction on the sampled data, where the window length is equal to the fundamental cycle of the power grid; Using improved run-length encoding to losslessly compress the feature data, with the fixed compression block size of 64 bytes; In step S5, the steps of using improved run-length encoding to losslessly compress the feature data are: Adopting a two-stage lossless compression process of differential encoding and run-length encoding; Performing first-order difference on the feature sequence of length : where, represents the difference value of the th item, represents the feature value of the th item, is the initial reference value, taking or 0; Performing run-length encoding on the difference sequence to obtain the encoded pair sequence: , where, represents the difference value of the th run, represents the length of this run, and the length is the number of consecutive identical s, represents the total number of run pairs; Packing the run pairs into each block with a fixed size of bytes: ; The number of bits occupied by each pair of encodings is: , where, is the maximum value of all plus 1,​ is the maximum allowable run length plus 1, is the bit width of the difference value field, is the bit width of the run length field; Then the maximum number of encoded pairs per block is: , When , it is stored in multiple blocks in sequence. When it is insufficient, it is filled with zero-value pairs until the block is full; Specifically, introducing differential coding condenses the changes in adjacent feature values into , significantly improving the aggregation degree of the same value segment, creating longer constant segments for subsequent run-length coding, thereby reducing the total number of run pairs , reducing the coding header overhead. The differential is mapped to the unsigned domain and combined with the bit width calculation , ensuring the optimal ratio of the sign and length fields, and maximizing the utilization rate of the fixed byte block; Step S6, after the microprocessor core responds to the communication flag bit, it processes the memory data in the order of decreasing timeliness weight from high to low, and outputs the processing result to the communication interface; The triggering conditions of the inter-core communication flag bit in step S6 include: The write volume in the real-time data area reaches 80% of its capacity; There are tasks in the interrupt event queue whose waiting time exceeds the set threshold; The current load rate of the microprocessor core is lower than 30%.

[0025] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A data acquisition and processing method for a power distribution intelligent terminal of a multi-core single-chip, characterized in that including Step S1: Configure a periodic sampling task in the data processing core, set a sampling time window synchronized with the fundamental frequency of the power grid, and trigger analog-to-digital conversion through a hardware timer; Step S2: Deploy an aperiodic interrupt monitoring module in the microprocessor core to capture circuit breaker tripping signals, ground fault signals, and communication protocol interrupt requests in real time; Step S3: Based on a dynamic priority calculation model, quantify the priorities of the periodic sampling task and the aperiodic interrupt task. The model dynamically adjusts the weights according to the task type, the current core load rate, and the data timeliness decay factor; Step S4: Through a shared memory sharding management unit, divide the storage area into a real-time data area, a historical cache area, and an interrupt event queue, and each area uses an independent memory access channel; Step S5: After the data processing core completes the preprocessing of the sampled data, write the data packet into the corresponding memory area according to the priority weight, and at the same time trigger the inter-core communication flag bit; Step S6: After the microprocessor core responds to the communication flag bit, process the memory data in descending order of timeliness weight and output the processing result to the communication interface.

2. The data acquisition and processing method of the power distribution intelligent terminal of a multi-core single-chip as claimed in claim 1, wherein, The configuration of the periodic sampling task in Step S1 includes: The sampling frequency is set to 2N times an integer multiple of the fundamental frequency, where N is a natural number greater than or equal to 10; The length of the sampling time window is adaptively adjusted according to the power grid frequency fluctuation range, and the adjustment step is 1 ms.

3. The data acquisition and processing method of a power distribution intelligent terminal of a multi-core single-chip as described in claim 2, characterized in that, In Step S1, configure a periodic sampling task in the data processing core, set a sampling time window synchronized with the fundamental frequency of the power grid, and trigger analog-to-digital conversion through a hardware timer; In step S1, the sampling frequency is defined as , where represents the sampling frequency, represents the sampling exponent, and its value range is natural numbers greater than or equal to 10, represents the fundamental grid frequency, represents the integer multiple sampling coefficient; For the highest signal bandwidth , meet , where indicates the highest signal bandwidth; When the fundamental frequency deviates a dynamic sampling interval is introduced : ， Among them, represents the dynamic sampling interval, represents the fundamental frequency deviation; Define the reference sampling interval and its correction amount as: ， ， Among them, represents the reference sampling interval, represents the sampling interval correction amount.

4. The data acquisition and processing method of the power distribution intelligent terminal of a multi-core single-chip as described in claim 1, characterized in that, The construction method of the dynamic priority calculation model in Step S3 includes: Assign a basic weight coefficient K1 to the periodic sampling task, and its value is positively correlated with the number of sampling channels; Assign an emergency weight coefficient K2 to the aperiodic interrupt task, and its value matches the power grid security level associated with the interrupt type; Introduce a timeliness decay factor, and its value decays exponentially with the task waiting time.

5. The data acquisition and processing method of a power distribution intelligent terminal of a multi-core single-chip as claimed in claim 4, wherein, In Step S3, the steps of dynamically adjusting the weight according to the task type, the current core load rate, and the data timeliness decay factor are: For the task Calculate the dynamic priority. Within each scheduling period, the priority is updated according to the following formula: , where represents the dynamic priority of the task , represents the basic weight coefficient of the task , represents the current core load adjustment function represents the task 's aging decay factor; Subsequently, define each sub-item, including: The core load adjustment function is defined as: ， Among them, represents the current core load rate, and the value range , represents the load impact coefficient, which is used to control the load weight attenuation rate.

6. The data acquisition and processing method of a power distribution intelligent terminal of a multi-core single-chip as claimed in claim 5, characterized in that, In Step S3, each sub-item also includes: Aging attenuation factor, comprehensive task waiting time The attenuation effect on priority is defined as: , where represents the aging attenuation factor of the task , represents the attenuation rate of the task , represents the cumulative waiting time of the task ; Discretize the task urgency into four levels, 1 - 4, and map them to the minimum and maximum attenuation rates in the linear range: ， Among them, represents the decay rate of the task, represents the lowest decay rate corresponding to the lowest urgency level, represents the highest decay rate corresponding to the highest urgency level, represents the urgency level of the task, with values ranging from 1 to 4; The update and calculation of the above functions and factors are executed once in each scheduling period, and its update period is set to , where represents the period of dynamic priority calculation and decay update.

7. The data acquisition and processing method of a power distribution intelligent terminal of a multi-core single-chip as described in claim 1, characterized in that, The operations of the shared memory sharding management unit in Step S4 include: The real-time data area stores the original sampled data within the last 2 cycles, and adopts a circular overwrite writing strategy; The historical cache area stores the compressed feature data, adopts a paged storage structure, and each page of data is attached with a timestamp mark; The interrupt event queue adopts a double-buffer structure, allowing high-priority tasks to directly write to the active buffer.

8. The data acquisition and processing method of a power distribution intelligent terminal of a multi-core single-chip as claimed in claim 7, characterized in that, The shared memory sharding management unit also includes: A memory access conflict arbitration mechanism that comprehensively sorts simultaneous read and write requests according to the task priority and timeliness; A data integrity verification module that attaches a 2-byte CRC verification code after each memory write operation; An access timestamp recording function that attaches a write time mark accurate to the microsecond level to each memory block.

9. The data acquisition and processing method of the power distribution intelligent terminal of a multi-core single-chip as claimed in claim 1, characterized in that, The data preprocessing in Step S5 includes: Perform sliding window feature extraction on the sampled data, and the window length is equal to the fundamental period of the power grid; The improved run-length encoding is used to perform lossless compression on the feature data, and the compression block size is fixed at 64 bytes.

10. The data acquisition and processing method of a power distribution intelligent terminal of a multi-core single-chip as claimed in claim 9, characterized in that, In step S5, the step of performing lossless compression on the feature data by using the improved run-length encoding is as follows: Adopt a two-stage lossless compression process of differential encoding and run-length encoding; Perform a first-order difference on the characteristic sequence of length : ​ , where represents the th difference value, represents the th eigenvalue, is the initial reference value, taking or 0; For the difference sequence Perform run-length encoding to obtain a sequence of encoded pairs: ， Among them, represents the difference value of the th run, represents the length of the run, and the length is the number of consecutive identical ones, represents the total number of run pairs; Pack run pairs into a fixed size per block Bytes: ; The number of bits occupied by each pair of codes is: , Among them, is the maximum value of all plus 1, is the maximum allowable run length plus 1, is the bit width of the difference value field, is the bit width of the run length field; Then the maximum number of encoding pairs per block is: ， When it is stored in multiple blocks sequentially by minute, and filled with zero values to a full block when insufficient.

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